Large diffs are not rendered by default.

@@ -2,11 +2,10 @@
turn_led <= inst60.DB_MAX_OUTPUT_PORT_TYPE
clock => g07_debounder:inst34.CLK
clock => LPM_COUNTER:inst4.clock
clock => bjt52:inst67.clock
clock => bjt52:inst32.clock
clock => g07_register6:inst5.clock
clock => g07_register6:inst14.clock
clock => bjt52:inst66.clock
clock => LPM_COUNTER:inst31.clock
clock => randinator:inst87.clock
clock => g07_dealerFSM:inst23.clock
clock => LPM_FF:inst1.clock
@@ -17,6 +16,7 @@ clock => g07_debounder:inst36.CLK
clock => g07_register6:inst9.clock
clock => compFSM:inst.clock
clock => systemFSM:inst74.clock
clock => LPM_COUNTER:inst31.clock
playp => inst37.IN0
resetp => inst33.IN0
upp => inst38.IN0
@@ -71,6 +71,11 @@ play => state.DATAA
play => state.DATAA
done => state.DATAA
done => state.DATAA
reset => kronus[0].ACLR
reset => kronus[1].ACLR
reset => kronus[2].ACLR
reset => kronus[3].ACLR
reset => kronus[4].ACLR
reset => state~5.DATAIN
reset => invalid_state.ENA
valid => Selector3.IN3
@@ -82,13 +87,11 @@ card_dealt => state.DATAB
card_dealt => state.DATAA
card_dealt => Selector2.IN1
card_dealt => Selector5.IN2
count[0] => LessThan0.IN10
count[0] => cpu_en.IN0
count[0] => hum_en.IN0
count[1] => LessThan0.IN9
count[2] => LessThan0.IN8
count[3] => LessThan0.IN7
count[4] => LessThan0.IN6
count[0] => ~NO_FANOUT~
count[1] => ~NO_FANOUT~
count[2] => ~NO_FANOUT~
count[3] => ~NO_FANOUT~
count[4] => ~NO_FANOUT~
cpu_num[0] => Equal1.IN5
cpu_num[1] => Equal1.IN4
cpu_num[2] => Equal1.IN3
@@ -108,15 +111,20 @@ deck_num[3] => Equal2.IN2
deck_num[4] => Equal2.IN1
deck_num[5] => Equal2.IN0
clock => invalid_state.CLK
clock => kronus[0].CLK
clock => kronus[1].CLK
clock => kronus[2].CLK
clock => kronus[3].CLK
clock => kronus[4].CLK
clock => state~3.DATAIN
turn <= turn.DB_MAX_OUTPUT_PORT_TYPE
request_deal <= request_deal.DB_MAX_OUTPUT_PORT_TYPE
game_start <= game_start.DB_MAX_OUTPUT_PORT_TYPE
cpu_en <= cpu_en.DB_MAX_OUTPUT_PORT_TYPE
hum_en <= hum_en.DB_MAX_OUTPUT_PORT_TYPE
cnt_en <= cnt_en.DB_MAX_OUTPUT_PORT_TYPE
deck_mode[0] <= deck_mode[0].DB_MAX_OUTPUT_PORT_TYPE
deck_mode[1] <= <VCC>
deck_mode[0] <= deck_mode.DB_MAX_OUTPUT_PORT_TYPE
deck_mode[1] <= deck_mode.DB_MAX_OUTPUT_PORT_TYPE
init_deck <= init_deck.DB_MAX_OUTPUT_PORT_TYPE
invalid_led <= invalid_state.DB_MAX_OUTPUT_PORT_TYPE
gg_led <= gg_led.DB_MAX_OUTPUT_PORT_TYPE
@@ -477,7 +485,7 @@ q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT


|g07_lab5|bjt52:inst67
|g07_lab5|bjt52:inst32
clock => t_num[0].CLK
clock => t_num[1].CLK
clock => t_num[2].CLK
@@ -3358,116 +3366,6 @@ value[4] <= value.DB_MAX_OUTPUT_PORT_TYPE
value[5] <= value.DB_MAX_OUTPUT_PORT_TYPE


|g07_lab5|g07_busmux21:inst32
data0[0] => output.DATAB
data0[1] => output.DATAB
data0[2] => output.DATAB
data0[3] => output.DATAB
data0[4] => output.DATAB
data0[5] => output.DATAB
data1[0] => output.DATAA
data1[1] => output.DATAA
data1[2] => output.DATAA
data1[3] => output.DATAA
data1[4] => output.DATAA
data1[5] => output.DATAA
sel => output.OUTPUTSELECT
sel => output.OUTPUTSELECT
sel => output.OUTPUTSELECT
sel => output.OUTPUTSELECT
sel => output.OUTPUTSELECT
sel => output.OUTPUTSELECT
output[0] <= output.DB_MAX_OUTPUT_PORT_TYPE
output[1] <= output.DB_MAX_OUTPUT_PORT_TYPE
output[2] <= output.DB_MAX_OUTPUT_PORT_TYPE
output[3] <= output.DB_MAX_OUTPUT_PORT_TYPE
output[4] <= output.DB_MAX_OUTPUT_PORT_TYPE
output[5] <= output.DB_MAX_OUTPUT_PORT_TYPE


|g07_lab5|LPM_COUNTER:inst31
clock => cntr_qbi:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_qbi:auto_generated.cnt_en
updown => ~NO_FANOUT~
aclr => cntr_qbi:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_qbi:auto_generated.q[0]
q[1] <= cntr_qbi:auto_generated.q[1]
q[2] <= cntr_qbi:auto_generated.q[2]
q[3] <= cntr_qbi:auto_generated.q[3]
q[4] <= cntr_qbi:auto_generated.q[4]
q[5] <= cntr_qbi:auto_generated.q[5]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|g07_lab5|LPM_COUNTER:inst31|cntr_qbi:auto_generated
aclr => counter_reg_bit1a[5].ACLR
aclr => counter_reg_bit1a[4].ACLR
aclr => counter_reg_bit1a[3].ACLR
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
cnt_en => _.IN1
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
q[3] <= counter_reg_bit1a[3].REGOUT
q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT


|g07_lab5|LPM_COUNTER:inst31|cntr_qbi:auto_generated|cmpr_acc:cmpr2
aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
dataa[0] => data_wire[0].IN0
dataa[1] => data_wire[0].IN0
dataa[2] => data_wire[1].IN0
dataa[3] => data_wire[1].IN0
dataa[4] => data_wire[2].IN0
dataa[5] => data_wire[2].IN0
datab[0] => data_wire[0].IN1
datab[1] => data_wire[0].IN1
datab[2] => data_wire[1].IN1
datab[3] => data_wire[1].IN1
datab[4] => data_wire[2].IN1
datab[5] => data_wire[2].IN1


|g07_lab5|randinator:inst87
clock => s[0].CLK
clock => s[1].CLK
@@ -4933,15 +4831,15 @@ value[5] <= value.DB_MAX_OUTPUT_PORT_TYPE


|g07_lab5|LPM_COUNTER:inst12
clock => cntr_hoe:auto_generated.clock
clock => cntr_j6f:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_hoe:auto_generated.cnt_en
updown => cntr_hoe:auto_generated.updown
aclr => ~NO_FANOUT~
cnt_en => cntr_j6f:auto_generated.cnt_en
updown => cntr_j6f:auto_generated.updown
aclr => cntr_j6f:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => cntr_hoe:auto_generated.sclr
sclr => cntr_j6f:auto_generated.sclr
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
@@ -4952,12 +4850,12 @@ data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_hoe:auto_generated.q[0]
q[1] <= cntr_hoe:auto_generated.q[1]
q[2] <= cntr_hoe:auto_generated.q[2]
q[3] <= cntr_hoe:auto_generated.q[3]
q[4] <= cntr_hoe:auto_generated.q[4]
q[5] <= cntr_hoe:auto_generated.q[5]
q[0] <= cntr_j6f:auto_generated.q[0]
q[1] <= cntr_j6f:auto_generated.q[1]
q[2] <= cntr_j6f:auto_generated.q[2]
q[3] <= cntr_j6f:auto_generated.q[3]
q[4] <= cntr_j6f:auto_generated.q[4]
q[5] <= cntr_j6f:auto_generated.q[5]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
@@ -4977,7 +4875,13 @@ eq[14] <= <GND>
eq[15] <= <GND>


|g07_lab5|LPM_COUNTER:inst12|cntr_hoe:auto_generated
|g07_lab5|LPM_COUNTER:inst12|cntr_j6f:auto_generated
aclr => counter_reg_bit1a[5].ACLR
aclr => counter_reg_bit1a[4].ACLR
aclr => counter_reg_bit1a[3].ACLR
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
@@ -5546,6 +5450,89 @@ output[4] <= output.DB_MAX_OUTPUT_PORT_TYPE
output[5] <= output.DB_MAX_OUTPUT_PORT_TYPE


|g07_lab5|LPM_COUNTER:inst31
clock => cntr_qbi:auto_generated.clock
clk_en => ~NO_FANOUT~
cnt_en => cntr_qbi:auto_generated.cnt_en
updown => ~NO_FANOUT~
aclr => cntr_qbi:auto_generated.aclr
aset => ~NO_FANOUT~
aconst => ~NO_FANOUT~
aload => ~NO_FANOUT~
sclr => ~NO_FANOUT~
sset => ~NO_FANOUT~
sconst => ~NO_FANOUT~
sload => ~NO_FANOUT~
data[0] => ~NO_FANOUT~
data[1] => ~NO_FANOUT~
data[2] => ~NO_FANOUT~
data[3] => ~NO_FANOUT~
data[4] => ~NO_FANOUT~
data[5] => ~NO_FANOUT~
cin => ~NO_FANOUT~
q[0] <= cntr_qbi:auto_generated.q[0]
q[1] <= cntr_qbi:auto_generated.q[1]
q[2] <= cntr_qbi:auto_generated.q[2]
q[3] <= cntr_qbi:auto_generated.q[3]
q[4] <= cntr_qbi:auto_generated.q[4]
q[5] <= cntr_qbi:auto_generated.q[5]
cout <= <GND>
eq[0] <= <GND>
eq[1] <= <GND>
eq[2] <= <GND>
eq[3] <= <GND>
eq[4] <= <GND>
eq[5] <= <GND>
eq[6] <= <GND>
eq[7] <= <GND>
eq[8] <= <GND>
eq[9] <= <GND>
eq[10] <= <GND>
eq[11] <= <GND>
eq[12] <= <GND>
eq[13] <= <GND>
eq[14] <= <GND>
eq[15] <= <GND>


|g07_lab5|LPM_COUNTER:inst31|cntr_qbi:auto_generated
aclr => counter_reg_bit1a[5].ACLR
aclr => counter_reg_bit1a[4].ACLR
aclr => counter_reg_bit1a[3].ACLR
aclr => counter_reg_bit1a[2].ACLR
aclr => counter_reg_bit1a[1].ACLR
aclr => counter_reg_bit1a[0].ACLR
clock => counter_reg_bit1a[5].CLK
clock => counter_reg_bit1a[4].CLK
clock => counter_reg_bit1a[3].CLK
clock => counter_reg_bit1a[2].CLK
clock => counter_reg_bit1a[1].CLK
clock => counter_reg_bit1a[0].CLK
cnt_en => _.IN1
q[0] <= counter_reg_bit1a[0].REGOUT
q[1] <= counter_reg_bit1a[1].REGOUT
q[2] <= counter_reg_bit1a[2].REGOUT
q[3] <= counter_reg_bit1a[3].REGOUT
q[4] <= counter_reg_bit1a[4].REGOUT
q[5] <= counter_reg_bit1a[5].REGOUT


|g07_lab5|LPM_COUNTER:inst31|cntr_qbi:auto_generated|cmpr_acc:cmpr2
aeb <= aeb_result_wire[0].DB_MAX_OUTPUT_PORT_TYPE
dataa[0] => data_wire[0].IN0
dataa[1] => data_wire[0].IN0
dataa[2] => data_wire[1].IN0
dataa[3] => data_wire[1].IN0
dataa[4] => data_wire[2].IN0
dataa[5] => data_wire[2].IN0
datab[0] => data_wire[0].IN1
datab[1] => data_wire[0].IN1
datab[2] => data_wire[1].IN1
datab[3] => data_wire[1].IN1
datab[4] => data_wire[2].IN1
datab[5] => data_wire[2].IN1


|g07_lab5|g07_busmux21:inst13
data0[0] => output.DATAB
data0[1] => output.DATAB
BIN -487 Bytes (92%) Lab5/db/g07_lab5.hif
Binary file not shown.
@@ -288,6 +288,38 @@
<TD >0</TD>
</TR>
<TR >
<TD >inst31|auto_generated|cmpr2</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst31|auto_generated</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst72</TD>
<TD >13</TD>
<TD >0</TD>
@@ -433,7 +465,7 @@
</TR>
<TR >
<TD >inst12|auto_generated</TD>
<TD >4</TD>
<TD >5</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
@@ -608,54 +640,6 @@
<TD >0</TD>
</TR>
<TR >
<TD >inst31|auto_generated|cmpr2</TD>
<TD >12</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst31|auto_generated</TD>
<TD >3</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >6</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst32</TD>
<TD >13</TD>
<TD >1</TD>
<TD >0</TD>
<TD >1</TD>
<TD >6</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
</TR>
<TR >
<TD >inst66</TD>
<TD >11</TD>
<TD >2</TD>
@@ -784,7 +768,7 @@
<TD >0</TD>
</TR>
<TR >
<TD >inst67</TD>
<TD >inst32</TD>
<TD >17</TD>
<TD >2</TD>
<TD >0</TD>
@@ -898,13 +882,13 @@
<TR >
<TD >inst74</TD>
<TD >29</TD>
<TD >2</TD>
<TD >0</TD>
<TD >2</TD>
<TD >1</TD>
<TD >5</TD>
<TD >1</TD>
<TD >17</TD>
<TD >2</TD>
<TD >2</TD>
<TD >2</TD>
<TD >1</TD>
<TD >1</TD>
<TD >1</TD>
<TD >0</TD>
<TD >0</TD>
<TD >0</TD>
BIN -28 Bytes (98%) Lab5/db/g07_lab5.lpc.rdb
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@@ -20,6 +20,8 @@
; inst49 ; 6 ; 3 ; 0 ; 3 ; 12 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst45 ; 5 ; 1 ; 0 ; 1 ; 7 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst13 ; 15 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst31|auto_generated|cmpr2 ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst31|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst72 ; 13 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst9 ; 8 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst25 ; 12 ; 2 ; 0 ; 2 ; 3 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
@@ -29,7 +31,7 @@
; inst35|inst8|auto_generated ; 2 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst35|inst21|auto_generated ; 24 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst35 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst12|auto_generated ; 4 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst12|auto_generated ; 5 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst11 ; 17 ; 3 ; 0 ; 3 ; 14 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst8 ; 13 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst7|m2 ; 6 ; 3 ; 0 ; 3 ; 12 ; 3 ; 3 ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ;
@@ -40,9 +42,6 @@
; inst87|randu|M1|auto_generated ; 64 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst87|randu ; 32 ; 1 ; 0 ; 1 ; 32 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst87 ; 2 ; 0 ; 0 ; 0 ; 32 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst31|auto_generated|cmpr2 ; 12 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst31|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst32 ; 13 ; 1 ; 0 ; 1 ; 6 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst66 ; 11 ; 2 ; 0 ; 2 ; 14 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst22 ; 6 ; 1 ; 1 ; 1 ; 6 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst69 ; 12 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
@@ -51,12 +50,12 @@
; inst23 ; 4 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst5 ; 8 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst28 ; 3 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst67 ; 17 ; 2 ; 0 ; 2 ; 14 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst32 ; 17 ; 2 ; 0 ; 2 ; 14 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst4|auto_generated ; 3 ; 0 ; 0 ; 0 ; 6 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst6 ; 12 ; 2 ; 0 ; 2 ; 3 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 6 ; 0 ; 0 ; 0 ; 7 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst34|inst8|auto_generated ; 2 ; 0 ; 0 ; 0 ; 24 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst34|inst21|auto_generated ; 24 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst34 ; 2 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst74 ; 29 ; 2 ; 0 ; 2 ; 17 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst74 ; 29 ; 1 ; 5 ; 1 ; 17 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+--------------------------------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
BIN +11 Bytes (100%) Lab5/db/g07_lab5.map.bpm
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BIN -183 Bytes (100%) Lab5/db/g07_lab5.map.cdb
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BIN -140 Bytes (100%) Lab5/db/g07_lab5.map.hdb
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BIN +50 Bytes (100%) Lab5/db/g07_lab5.map.kpt
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BIN +2 Bytes (100%) Lab5/db/g07_lab5.map.rdb
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BIN +0 Bytes (100%) Lab5/db/g07_lab5.map_bb.cdb
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BIN -17 Bytes (100%) Lab5/db/g07_lab5.map_bb.hdb
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BIN -49 Bytes (100%) Lab5/db/g07_lab5.pre_map.hdb
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BIN +545 Bytes (100%) Lab5/db/g07_lab5.routing.rdb
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BIN -5 Bytes (100%) Lab5/db/g07_lab5.rtlv.hdb
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BIN +617 Bytes (100%) Lab5/db/g07_lab5.rtlv_sg.cdb
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BIN -24 Bytes (100%) Lab5/db/g07_lab5.rtlv_sg_swap.cdb
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BIN -2.93 KB (98%) Lab5/db/g07_lab5.sgdiff.cdb
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BIN -176 Bytes (100%) Lab5/db/g07_lab5.sgdiff.hdb
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@@ -17,10 +17,10 @@ state.ACCEPT_CARD 0 1 0 0 0 0 1
state.E 1 0 0 0 0 0 1

State Machine - |g07_lab5|systemFSM:inst74|state
Name state.PILE_RECV_CARD state.PILE state.DEAL_PILE state.G state.F state.HUM_RECV_CARD state.E state.D state.C state.GET_CARD state.B state.DEAL_NEXT state.WAIT_FOR_NEW_DECK state.A
Name state.PILE_RECV_CARD state.PILE state.DEAL_PILE state.G state.F state.HUM_RECV_CARD state.E state.D state.C state.GET_CARD state.B state.WAIT_FOR_NEW_DECK state.DEAL_NEXT state.A
state.A 0 0 0 0 0 0 0 0 0 0 0 0 0 0
state.WAIT_FOR_NEW_DECK 0 0 0 0 0 0 0 0 0 0 0 0 1 1
state.DEAL_NEXT 0 0 0 0 0 0 0 0 0 0 0 1 0 1
state.DEAL_NEXT 0 0 0 0 0 0 0 0 0 0 0 0 1 1
state.WAIT_FOR_NEW_DECK 0 0 0 0 0 0 0 0 0 0 0 1 0 1
state.B 0 0 0 0 0 0 0 0 0 0 1 0 0 1
state.GET_CARD 0 0 0 0 0 0 0 0 0 1 0 0 0 1
state.C 0 0 0 0 0 0 0 0 1 0 0 0 0 1

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BIN -54 Bytes (100%) Lab5/db/g07_lab5.sta.rdb
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BIN +5 Bytes (100%) Lab5/db/g07_lab5.vpr.ammdb
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BIN -660 Bytes (99%) Lab5/db/logic_util_heursitic.dat
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@@ -1,5 +1,5 @@
Assembler report for g07_lab5
Wed Apr 5 20:00:43 2017
Wed Apr 5 23:57:53 2017
Quartus II 32-bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition


@@ -38,7 +38,7 @@ applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Apr 5 20:00:43 2017 ;
; Assembler Status ; Successful - Wed Apr 5 23:57:53 2017 ;
; Revision Name ; g07_lab5 ;
; Top-level Entity Name ; g07_lab5 ;
; Family ; Cyclone II ;
@@ -94,8 +94,8 @@ applicable agreement for further details.
; Option ; Setting ;
+----------------+-----------------------+
; Device ; EP2C20F484C7 ;
; JTAG usercode ; 0x003145F0 ;
; Checksum ; 0x003145F0 ;
; JTAG usercode ; 0x0030D32F ;
; Checksum ; 0x0030D32F ;
+----------------+-----------------------+


@@ -106,7 +106,7 @@ applicable agreement for further details.
+--------------------+-------------------+
; Device ; EPCS16 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x1DB5CE53 ;
; Checksum ; 0x1DB99634 ;
; Compression Ratio ; 2 ;
+--------------------+-------------------+

@@ -117,14 +117,14 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit Assembler
Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
Info: Processing started: Wed Apr 5 20:00:42 2017
Info: Processing started: Wed Apr 5 23:57:51 2017
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off g07_lab5 -c g07_lab5
Info (115031): Writing out detailed assembly data for power analysis
Info (115030): Assembler is generating device programming files
Info: Quartus II 32-bit Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 349 megabytes
Info: Processing ended: Wed Apr 5 20:00:43 2017
Info: Elapsed time: 00:00:01
Info: Peak virtual memory: 345 megabytes
Info: Processing ended: Wed Apr 5 23:57:53 2017
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02


@@ -1 +1 @@
Wed Apr 5 20:00:57 2017
Wed Apr 5 23:58:07 2017
@@ -1,5 +1,5 @@
EDA Netlist Writer report for g07_lab5
Wed Apr 5 20:00:55 2017
Wed Apr 5 23:58:04 2017
Quartus II 32-bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition


@@ -36,7 +36,7 @@ applicable agreement for further details.
+-------------------------------------------------------------------+
; EDA Netlist Writer Summary ;
+---------------------------+---------------------------------------+
; EDA Netlist Writer Status ; Successful - Wed Apr 5 20:00:55 2017 ;
; EDA Netlist Writer Status ; Successful - Wed Apr 5 23:58:04 2017 ;
; Revision Name ; g07_lab5 ;
; Top-level Entity Name ; g07_lab5 ;
; Family ; Cyclone II ;
@@ -84,12 +84,12 @@ applicable agreement for further details.
Info: *******************************************************************
Info: Running Quartus II 32-bit EDA Netlist Writer
Info: Version 13.0.0 Build 156 04/24/2013 SJ Web Edition
Info: Processing started: Wed Apr 5 20:00:53 2017
Info: Processing started: Wed Apr 5 23:58:02 2017
Info: Command: quartus_eda --read_settings_files=off --write_settings_files=off g07_lab5 -c g07_lab5
Info (204026): Generated files "g07_lab5.vho", "g07_lab5_fast.vho", "g07_lab5_vhd.sdo" and "g07_lab5_vhd_fast.sdo" in directory "/home/harwiltz/DSDLabs/Lab5/simulation/modelsim/" for EDA simulation tool
Info: Quartus II 32-bit EDA Netlist Writer was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 338 megabytes
Info: Processing ended: Wed Apr 5 20:00:55 2017
Info: Peak virtual memory: 343 megabytes
Info: Processing ended: Wed Apr 5 23:58:04 2017
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:02

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@@ -1,14 +1,14 @@
Fitter Status : Successful - Wed Apr 5 20:00:37 2017
Fitter Status : Successful - Wed Apr 5 23:57:47 2017
Quartus II 32-bit Version : 13.0.0 Build 156 04/24/2013 SJ Web Edition
Revision Name : g07_lab5
Top-level Entity Name : g07_lab5
Family : Cyclone II
Device : EP2C20F484C7
Timing Models : Final
Total logic elements : 2,055 / 18,752 ( 11 % )
Total combinational functions : 1,750 / 18,752 ( 9 % )
Dedicated logic registers : 952 / 18,752 ( 5 % )
Total registers : 952
Total logic elements : 2,034 / 18,752 ( 11 % )
Total combinational functions : 1,730 / 18,752 ( 9 % )
Dedicated logic registers : 957 / 18,752 ( 5 % )
Total registers : 957
Total pins : 42 / 315 ( 13 % )
Total virtual pins : 0
Total memory bits : 0 / 239,616 ( 0 % )
@@ -1,5 +1,5 @@
Flow report for g07_lab5
Wed Apr 5 20:00:55 2017
Wed Apr 5 23:58:04 2017
Quartus II 32-bit Version 13.0.0 Build 156 04/24/2013 SJ Web Edition


@@ -40,17 +40,17 @@ applicable agreement for further details.
+---------------------------------------------------------------------------------+
; Flow Summary ;
+------------------------------------+--------------------------------------------+
; Flow Status ; Successful - Wed Apr 5 20:00:55 2017 ;
; Flow Status ; Successful - Wed Apr 5 23:58:04 2017 ;
; Quartus II 32-bit Version ; 13.0.0 Build 156 04/24/2013 SJ Web Edition ;
; Revision Name ; g07_lab5 ;
; Top-level Entity Name ; g07_lab5 ;
; Family ; Cyclone II ;
; Device ; EP2C20F484C7 ;
; Timing Models ; Final ;
; Total logic elements ; 2,055 / 18,752 ( 11 % ) ;
; Total combinational functions ; 1,750 / 18,752 ( 9 % ) ;
; Dedicated logic registers ; 952 / 18,752 ( 5 % ) ;
; Total registers ; 952 ;
; Total logic elements ; 2,034 / 18,752 ( 11 % ) ;
; Total combinational functions ; 1,730 / 18,752 ( 9 % ) ;
; Dedicated logic registers ; 957 / 18,752 ( 5 % ) ;
; Total registers ; 957 ;
; Total pins ; 42 / 315 ( 13 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 239,616 ( 0 % ) ;
@@ -64,7 +64,7 @@ applicable agreement for further details.
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 04/05/2017 20:00:12 ;
; Start date & time ; 04/05/2017 23:57:22 ;
; Main task ; Compilation ;
; Revision Name ; g07_lab5 ;
+-------------------+---------------------+
@@ -75,7 +75,7 @@ applicable agreement for further details.
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+-------------------------------------+---------------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 0.149143681230145 ; -- ; -- ; -- ;
; COMPILER_SIGNATURE_ID ; 0.149145104205173 ; -- ; -- ; -- ;
; EDA_OUTPUT_DATA_FORMAT ; Vhdl ; -- ; -- ; eda_simulation ;
; EDA_SIMULATION_TOOL ; ModelSim-Altera (VHDL) ; <None> ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
@@ -96,12 +96,12 @@ applicable agreement for further details.
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:06 ; 1.0 ; 381 MB ; 00:00:07 ;
; Fitter ; 00:00:14 ; 1.6 ; 503 MB ; 00:00:22 ;
; Assembler ; 00:00:01 ; 1.0 ; 349 MB ; 00:00:02 ;
; Analysis & Synthesis ; 00:00:07 ; 1.0 ; 385 MB ; 00:00:07 ;
; Fitter ; 00:00:15 ; 1.2 ; 508 MB ; 00:00:21 ;
; Assembler ; 00:00:02 ; 1.0 ; 345 MB ; 00:00:02 ;
; TimeQuest Timing Analyzer ; 00:00:02 ; 1.0 ; 368 MB ; 00:00:02 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 329 MB ; 00:00:02 ;
; Total ; 00:00:25 ; -- ; -- ; 00:00:35 ;
; EDA Netlist Writer ; 00:00:02 ; 1.0 ; 334 MB ; 00:00:02 ;
; Total ; 00:00:28 ; -- ; -- ; 00:00:34 ;
+---------------------------+--------------+-------------------------+---------------------+------------------------------------+


@@ -1,6 +1,6 @@
<sld_project_info>
<project>
<hash md5_digest_80b="18faa2e4fa88453de4e8"/>
<hash md5_digest_80b="14f39f661f042307f6be"/>
</project>
<file_info>
<file device="EP2C20F484C7" path="g07_lab5.sof" usercode="0xFFFFFFFF"/>

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@@ -1,12 +1,12 @@
Analysis & Synthesis Status : Successful - Wed Apr 5 20:00:19 2017
Analysis & Synthesis Status : Successful - Wed Apr 5 23:57:28 2017
Quartus II 32-bit Version : 13.0.0 Build 156 04/24/2013 SJ Web Edition
Revision Name : g07_lab5
Top-level Entity Name : g07_lab5
Family : Cyclone II
Total logic elements : 2,057
Total combinational functions : 1,749
Dedicated logic registers : 952
Total registers : 952
Total logic elements : 2,037
Total combinational functions : 1,729
Dedicated logic registers : 957
Total registers : 957
Total pins : 42
Total virtual pins : 0
Total memory bits : 0
BIN +0 Bytes (100%) Lab5/output_files/g07_lab5.pof
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BIN +0 Bytes (100%) Lab5/output_files/g07_lab5.sof
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@@ -3,43 +3,43 @@ TimeQuest Timing Analyzer Summary
------------------------------------------------------------

Type : Slow Model Setup 'clock'
Slack : -15.189
TNS : -6677.786
Slack : -15.357
TNS : -6773.792

Type : Slow Model Hold 'clock'
Slack : 0.445
TNS : 0.000

Type : Slow Model Recovery 'clock'
Slack : -1.040
TNS : -6.240
Slack : -1.003
TNS : -6.018

Type : Slow Model Removal 'clock'
Slack : 1.657
Slack : 1.647
TNS : 0.000

Type : Slow Model Minimum Pulse Width 'clock'
Slack : -1.631
TNS : -1164.975
TNS : -1171.085

Type : Fast Model Setup 'clock'
Slack : -4.994
TNS : -1999.053
Slack : -5.112
TNS : -2052.260

Type : Fast Model Hold 'clock'
Slack : 0.215
TNS : 0.000

Type : Fast Model Recovery 'clock'
Slack : 0.083
Slack : 0.078
TNS : 0.000

Type : Fast Model Removal 'clock'
Slack : 0.753
Slack : 0.771
TNS : 0.000

Type : Fast Model Minimum Pulse Width 'clock'
Slack : -1.380
TNS : -953.380
TNS : -958.380

------------------------------------------------------------

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@@ -1,5 +1,6 @@
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity systemFSM is
port (
@@ -32,30 +33,35 @@ entity systemFSM is
end systemFSM;

architecture system of systemFSM is
Type State_Type is (A,WAIT_FOR_NEW_DECK,DEAL_NEXT,B,GET_CARD,C,D,E,HUM_RECV_CARD,F,G,DEAL_PILE,PILE, PILE_RECV_CARD);
SIGNAL state: State_Type;
Type State_Type is (A,DEAL_NEXT,WAIT_FOR_NEW_DECK,B,GET_CARD,C,D,E,HUM_RECV_CARD,F,G,DEAL_PILE,PILE, PILE_RECV_CARD);
SIGNAL state: State_Type := A;
SIGNAL invalid_state: std_logic := '1';

SIGNAL kronus: integer range 0 to 31 := 0;
begin
machine: process(clock, reset)
begin
if(reset = '1') then
state <= A;
kronus <= 0;
elsif(clock'Event and clock='1') then
case state is
when A =>
state <= WAIT_FOR_NEW_DECK;
kronus <= 0;
when WAIT_FOR_NEW_DECK =>
state <= DEAL_NEXT;
kronus <= 0;
when DEAL_NEXT =>
state <= B;
when B =>
if(count >= "10000") then
-- if(count >= "10000") then
if(kronus >= 16) then
state <= DEAL_PILE;
elsif (card_dealt = '1') then state <= GET_CARD;
else state <= B;
end if;
when GET_CARD =>
kronus <= kronus + 1;
state <= DEAL_NEXT;
when DEAL_PILE =>
state <= PILE;
@@ -99,19 +105,21 @@ begin
turn <= '1' when state = F else '0';
request_deal <= '1' when (state = E or state = DEAL_NEXT or state = DEAL_PILE or state = PILE) else '0';
game_start <= '1' when state = B or state = GET_CARD or state = DEAL_NEXT else '0';
cpu_en <= '1' when state = GET_CARD and count(0) = '1' else '0';
hum_en <= '1' when (state = GET_CARD and count(0) = '0' ) or (state = D and valid = '1') or state = HUM_RECV_CARD else '0';
cnt_en <= '1' when state = GET_CARD or state <= PILE else '0';
deck_mode <= "10" when state = A else "11";
-- deck_mode <= "10" when state = A else "11" when (state = B or state = DEAL_NEXT or state = GET_CARD or state = PILE or state = PILE_RECV_CARD or state = E or state = F) else "00";
-- cpu_en <= '1' when state = GET_CARD and count(0) = '1' else '0';
-- hum_en <= '1' when (state = GET_CARD and count(0) = '0' ) or (state = D and valid = '1') or state = HUM_RECV_CARD else '0';
cpu_en <= '1' when state = GET_CARD and (kronus mod 2 = 1) else '0';
hum_en <= '1' when (state = GET_CARD and (kronus mod 2 = 0)) or (state = D and valid = '1') or state = HUM_RECV_CARD else '0';
cnt_en <= '1' when state = GET_CARD else '0';
-- cnt_en <= '1' when state = GET_CARD or state <= PILE else '0';
deck_mode <= "10" when state = A else "00" when state = WAIT_FOR_NEW_DECK or state = DEAL_NEXT else "11";
init_deck <= '1' when state = PILE else '0';
gg_led <= '0' when state = G else '1';
w_led <= '0' when state = G and hum_num = "000000" else '1';
l_led <= '0' when state = G and cpu_num = "000000" else '1';
--d_led <= '0' when state = PILE else '1';
d_led <= '0' when state = G and deck_num = "000000" else '1';
--deck_en <= '0' when (state = A or state = B or state = PILE) else '0';
deck_en <= '1' when state = A or state = PILE_RECV_CARD else '0';
deck_en <= '1' when state = A else '0';
-- deck_en <= '1' when state = A or state = PILE_RECV_CARD else '0';
hum_mode <= "01" when state = B or state = GET_CARD or state = E or state = HUM_RECV_CARD else "11";
invalid_led <= invalid_state;
end system;