From a71c390d7af4e157b535a7508fdc1317cf9a9ad0 Mon Sep 17 00:00:00 2001 From: ArtVVB Date: Wed, 24 Oct 2018 16:28:05 -0700 Subject: [PATCH] 2018.2: Add missing BD TCL; Update README.md --- .gitignore | 17 +- README.md | 74 +++++- digilent-vivado-scripts | 2 +- src/bd/user_35t.tcl | 494 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 569 insertions(+), 18 deletions(-) create mode 100644 src/bd/user_35t.tcl diff --git a/.gitignore b/.gitignore index f30da40..f074732 100644 --- a/.gitignore +++ b/.gitignore @@ -30,7 +30,7 @@ repo/cache/** src/** !src/bd src/bd/** -!src/bd/system.tcl +!src/bd/*.tcl !src/constraints src/constraints/** !src/constraints/*.xdc @@ -39,10 +39,10 @@ src/hdl/** !src/hdl/*.v !src/hdl/*.vhd !src/ip -src/ip/** +!src/ip/* +src/ip/*/** !src/ip/**/*.xci !src/other -src/other/** !src/other/** # sdk application sources @@ -50,16 +50,5 @@ sdk/** !sdk/appsrc !sdk/appsrc/** -# version controlled sources -!src/bd/system.tcl -src/constraints/* -!src/constraints/*.xdc -src/hdl/* -!src/hdl/*.vhd -!src/hdl/*.v -src/ip/*/** -!src/ip/*/*.xci -!src/others/* - # maintain required directories !**/.keep diff --git a/README.md b/README.md index 7c218a5..26e7e51 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,73 @@ -# Cmod A7-35T Out of Box Demo -Created for Vivado 2016.4 +Cmod A7-35T Out of Box Demo +==================== -[Link to the project wiki](https://reference.digilentinc.com/learn/programmable-logic/tutorials/cmod-a7-user-demo/start) +Description +----------- + +This project demonstrates how to use the Cmod A7-35T's Artix 7 FPGA's Microblaze processor with the SRAM, LED's, RGB LED's, Pushbuttons and the USB UART bridge. Vivado is used to build the demo's hardware platform, and Xilinx SDK is used to program the bitstream onto the board and to build and deploy a C application. + +To use this demo, the Cmod A7-35T must be connected to a computer over MicroUSB, which must be running a serial terminal. For more information on how to set up and use a serial terminal, such as Tera Term or PuTTY, refer to [this tutorial](https://reference.digilentinc.com/vivado/installing-vivado/start). + +Whenever the demo is started from Vivado SDK, the board will go through a memory test and will print out the result to the serial terminal. Whenever one of the buttons is pressed, the line “Button Pressed” is sent. Every time BTN1 is pressed, the LED state changes. The user LEDs create a 2 bit binary counter that increments every time the button is pressed. The RGB LED smoothly transitions between colors. + +Requirements +------------ +* **Cmod A7-35T**: To purchase a Cmod A7-35T, see the [Digilent Store](https://store.digilentinc.com/cmod-a7-breadboardable-artix-7-fpga-module/). +* **Vivado 2018.2 Installation with Xilinx SDK**: To set up Vivado, see the [Installing Vivado and Digilent Board Files Tutorial](https://reference.digilentinc.com/vivado/installing-vivado/start). +* **Serial Terminal Emulator**: +* **MicroUSB Cable** + +Demo Setup +---------- + +1. Download the most recent release ZIP archive ("Cmod-A7-35T-OOB-2018.2-*.zip") from the repo's [releases page](https://github.com/Digilent/Cmod-A7-35T-OOB/releases). +2. Extract the downloaded ZIP. +3. Open the XPR project file, found at \/vivado_proj/Cmod-A7-35T-OOB.xpr, included in the extracted release archive in Vivado 2018.2. +4. In the toolbar at the top of the Vivado window, select **File -> Export -> Export Hardware**. Select **\** as the Exported Location and make sure that the **Include bitstream** box is checked, then click **OK**. +5. In the toolbar at the top of the Vivado window, select **File -> Launch SDK**. Select **\** as both the workspace location and exported location, then click **OK**. +6. With Vivado SDK opened, wait for the hardware platform exported by Vivado to be imported. +7. In the toolbar at the top of the SDK window, select **File -> New -> Application Project**. +8. Fill out the fields in the first page of the New Application Project Wizard as in the table below. Most of the listed values will be the wizard's defaults, but are included in the table for completeness. + +| Setting | Value | +| --------------------------------------- | --------------------------------- | +| Project Name | Cmod-A7-35T-OOB | +| Use default location | Checked box | +| OS Platform | standalone | +| Target Hardware: Hardware Platform | design_1_wrapper_hw_platform_0 | +| Target Hardware: Processor | microblaze_0 | +| Target Software: Language | C | +| Target Software: Board Support Package | Create New (Cmod-A7-35T-OOB_bsp) | + +9. Click **Next**. +10. From the list of template applications, select "Empty Application", then click **Finish**. +11. In the Project Explorer pane to the left of the SDK window, expand the new application project (named "Cmod-A7-35T-OOB"). +12. Right click on the "src" subdirectory of the application project and select **Import**. +13. In the "Select an import wizard" pane of the window that pops up, expand **General** and select **File System**. Then click **Next**. +14. Fill out the fields of the "File system" screen as in the table below. Most of the listed values will be the defaults, but are included in the table for completeness. + +| Setting | Value | +| - | - | +| From directory | \/sdk_appsrc | +| Files to import pane: sdk_appsrc | Checked box | +| Into folder | Cmod-A7-35T-OOB/src | +| Options: Overwrite existing resources without warning | Checked box | +| Options: Create top-level folder | Unchecked box | + +15. Click **Finish**. + + + +16. Open a serial terminal application (such as TeraTerm) and connect it to the Cmod A7's serial port, using a baud rate of 9600. +17. In the toolbar at the top of the SDK window, select **Xilinx -> Program FPGA**. Leave all fields as their defaults and click "Program". +18. In the Project Explorer pane, right click on the "Cmod-A7-35T-OOB" application project and select "Run As -> Launch on Hardware (System Debugger)". +19.The application will now be running on the Cmod A7. It can be interacted with as described in the first section of this README. + +Next Steps +---------- +This demo can be used as a basis for other projects by modifying the hardware platform in the Vivado project's block design or by modifying the SDK application project. + +Additional Notes +-------------- +For more information on how this project is version controlled, refer to the [Digilent Vivado Scripts Repository](https://github.com/digilent/digilent-vivado-scripts) diff --git a/digilent-vivado-scripts b/digilent-vivado-scripts index ffa3f4f..fd7ce6b 160000 --- a/digilent-vivado-scripts +++ b/digilent-vivado-scripts @@ -1 +1 @@ -Subproject commit ffa3f4f7bea46dc30645e1b618701ea3806b7707 +Subproject commit fd7ce6be4a1b3883c819d3c633d95b8ed5d0c210 diff --git a/src/bd/user_35t.tcl b/src/bd/user_35t.tcl new file mode 100644 index 0000000..b88e32e --- /dev/null +++ b/src/bd/user_35t.tcl @@ -0,0 +1,494 @@ + +################################################################ +# This is a generated script based on design: user_35t +# +# Though there are limitations about the generated script, +# the main purpose of this utility is to make learning +# IP Integrator Tcl commands easier. +################################################################ + +namespace eval _tcl { +proc get_script_folder {} { + set script_path [file normalize [info script]] + set script_folder [file dirname $script_path] + return $script_folder +} +} +variable script_folder +set script_folder [_tcl::get_script_folder] + +################################################################ +# Check if script is running in correct Vivado version. +################################################################ +set scripts_vivado_version 2018.2 +set current_vivado_version [version -short] + +if { [string first $scripts_vivado_version $current_vivado_version] == -1 } { + puts "" + catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."} + + return 1 +} + +################################################################ +# START +################################################################ + +# To test this script, run the following commands from Vivado Tcl console: +# source user_35t_script.tcl + +# If there is no project opened, this script will create a +# project, but make sure you do not have an existing project +# <./myproj/project_1.xpr> in the current working folder. + +set list_projs [get_projects -quiet] +if { $list_projs eq "" } { + create_project project_1 myproj -part xc7a35tcpg236-1 + set_property BOARD_PART digilentinc.com:cmod_a7-35t:part0:1.1 [current_project] +} + + +# CHANGE DESIGN NAME HERE +variable design_name +set design_name user_35t + +# If you do not already have an existing IP Integrator design open, +# you can create a design using the following command: +# create_bd_design $design_name + +# Creating design if needed +set errMsg "" +set nRet 0 + +set cur_design [current_bd_design -quiet] +set list_cells [get_bd_cells -quiet] + +if { ${design_name} eq "" } { + # USE CASES: + # 1) Design_name not set + + set errMsg "Please set the variable to a non-empty value." + set nRet 1 + +} elseif { ${cur_design} ne "" && ${list_cells} eq "" } { + # USE CASES: + # 2): Current design opened AND is empty AND names same. + # 3): Current design opened AND is empty AND names diff; design_name NOT in project. + # 4): Current design opened AND is empty AND names diff; design_name exists in project. + + if { $cur_design ne $design_name } { + common::send_msg_id "BD_TCL-001" "INFO" "Changing value of from <$design_name> to <$cur_design> since current design is empty." + set design_name [get_property NAME $cur_design] + } + common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..." + +} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } { + # USE CASES: + # 5) Current design opened AND has components AND same names. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 1 +} elseif { [get_files -quiet ${design_name}.bd] ne "" } { + # USE CASES: + # 6) Current opened design, has components, but diff names, design_name exists in project. + # 7) No opened design, design_name exists in project. + + set errMsg "Design <$design_name> already exists in your project, please set the variable to another value." + set nRet 2 + +} else { + # USE CASES: + # 8) No opened design, design_name not in project. + # 9) Current opened design, has components, but diff names, design_name not in project. + + common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..." + + create_bd_design $design_name + + common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design." + current_bd_design $design_name + +} + +common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable is equal to \"$design_name\"." + +if { $nRet != 0 } { + catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg} + return $nRet +} + +set bCheckIPsPassed 1 +################################################################## +# CHECK IPs +################################################################## +set bCheckIPs 1 +if { $bCheckIPs == 1 } { + set list_check_ips "\ +xilinx.com:ip:axi_emc:3.0\ +xilinx.com:ip:axi_gpio:2.0\ +xilinx.com:ip:axi_intc:4.1\ +xilinx.com:ip:axi_timer:2.0\ +xilinx.com:ip:axi_uartlite:2.0\ +xilinx.com:ip:clk_wiz:6.0\ +xilinx.com:ip:mdm:3.2\ +xilinx.com:ip:microblaze:10.0\ +xilinx.com:ip:proc_sys_reset:5.0\ +xilinx.com:ip:xlconcat:2.1\ +xilinx.com:ip:lmb_bram_if_cntlr:4.0\ +xilinx.com:ip:lmb_v10:3.0\ +xilinx.com:ip:blk_mem_gen:8.4\ +" + + set list_ips_missing "" + common::send_msg_id "BD_TCL-006" "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ." + + foreach ip_vlnv $list_check_ips { + set ip_obj [get_ipdefs -all $ip_vlnv] + if { $ip_obj eq "" } { + lappend list_ips_missing $ip_vlnv + } + } + + if { $list_ips_missing ne "" } { + catch {common::send_msg_id "BD_TCL-115" "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." } + set bCheckIPsPassed 0 + } + +} + +if { $bCheckIPsPassed != 1 } { + common::send_msg_id "BD_TCL-1003" "WARNING" "Will not continue with creation of design due to the error(s) above." + return 3 +} + +################################################################## +# DESIGN PROCs +################################################################## + + +# Hierarchical cell: microblaze_0_local_memory +proc create_hier_cell_microblaze_0_local_memory { parentCell nameHier } { + + variable script_folder + + if { $parentCell eq "" || $nameHier eq "" } { + catch {common::send_msg_id "BD_TCL-102" "ERROR" "create_hier_cell_microblaze_0_local_memory() - Empty argument(s)!"} + return + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + # Create cell and set as current instance + set hier_obj [create_bd_cell -type hier $nameHier] + current_bd_instance $hier_obj + + # Create interface pins + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 DLMB + create_bd_intf_pin -mode MirroredMaster -vlnv xilinx.com:interface:lmb_rtl:1.0 ILMB + + # Create pins + create_bd_pin -dir I -type clk LMB_Clk + create_bd_pin -dir I -from 0 -to 0 -type rst SYS_Rst + + # Create instance: dlmb_bram_if_cntlr, and set properties + set dlmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 dlmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $dlmb_bram_if_cntlr + + # Create instance: dlmb_v10, and set properties + set dlmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 dlmb_v10 ] + + # Create instance: ilmb_bram_if_cntlr, and set properties + set ilmb_bram_if_cntlr [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_bram_if_cntlr:4.0 ilmb_bram_if_cntlr ] + set_property -dict [ list \ + CONFIG.C_ECC {0} \ + ] $ilmb_bram_if_cntlr + + # Create instance: ilmb_v10, and set properties + set ilmb_v10 [ create_bd_cell -type ip -vlnv xilinx.com:ip:lmb_v10:3.0 ilmb_v10 ] + + # Create instance: lmb_bram, and set properties + set lmb_bram [ create_bd_cell -type ip -vlnv xilinx.com:ip:blk_mem_gen:8.4 lmb_bram ] + set_property -dict [ list \ + CONFIG.EN_SAFETY_CKT {false} \ + CONFIG.Enable_B {Use_ENB_Pin} \ + CONFIG.Memory_Type {True_Dual_Port_RAM} \ + CONFIG.Port_B_Clock {100} \ + CONFIG.Port_B_Enable_Rate {100} \ + CONFIG.Port_B_Write_Rate {50} \ + CONFIG.Use_RSTB_Pin {true} \ + CONFIG.use_bram_block {BRAM_Controller} \ + ] $lmb_bram + + # Create interface connections + connect_bd_intf_net -intf_net microblaze_0_dlmb [get_bd_intf_pins DLMB] [get_bd_intf_pins dlmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_dlmb_bus [get_bd_intf_pins dlmb_bram_if_cntlr/SLMB] [get_bd_intf_pins dlmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_dlmb_cntlr [get_bd_intf_pins dlmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTA] + connect_bd_intf_net -intf_net microblaze_0_ilmb [get_bd_intf_pins ILMB] [get_bd_intf_pins ilmb_v10/LMB_M] + connect_bd_intf_net -intf_net microblaze_0_ilmb_bus [get_bd_intf_pins ilmb_bram_if_cntlr/SLMB] [get_bd_intf_pins ilmb_v10/LMB_Sl_0] + connect_bd_intf_net -intf_net microblaze_0_ilmb_cntlr [get_bd_intf_pins ilmb_bram_if_cntlr/BRAM_PORT] [get_bd_intf_pins lmb_bram/BRAM_PORTB] + + # Create port connections + connect_bd_net -net SYS_Rst_1 [get_bd_pins SYS_Rst] [get_bd_pins dlmb_bram_if_cntlr/LMB_Rst] [get_bd_pins dlmb_v10/SYS_Rst] [get_bd_pins ilmb_bram_if_cntlr/LMB_Rst] [get_bd_pins ilmb_v10/SYS_Rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins LMB_Clk] [get_bd_pins dlmb_bram_if_cntlr/LMB_Clk] [get_bd_pins dlmb_v10/LMB_Clk] [get_bd_pins ilmb_bram_if_cntlr/LMB_Clk] [get_bd_pins ilmb_v10/LMB_Clk] + + # Restore current instance + current_bd_instance $oldCurInst +} + + +# Procedure to create entire design; Provide argument to make +# procedure reusable. If parentCell is "", will use root. +proc create_root_design { parentCell } { + + variable script_folder + variable design_name + + if { $parentCell eq "" } { + set parentCell [get_bd_cells /] + } + + # Get object for parentCell + set parentObj [get_bd_cells $parentCell] + if { $parentObj == "" } { + catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"} + return + } + + # Make sure parentObj is hier blk + set parentType [get_property TYPE $parentObj] + if { $parentType ne "hier" } { + catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be ."} + return + } + + # Save current instance; Restore later + set oldCurInst [current_bd_instance .] + + # Set parent object as current + current_bd_instance $parentObj + + + # Create interface ports + set cellular_ram [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:emc_rtl:1.0 cellular_ram ] + set led_2bits [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 led_2bits ] + set push_buttons_1bit [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 push_buttons_1bit ] + set rgb_led [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:gpio_rtl:1.0 rgb_led ] + set usb_uart [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:uart_rtl:1.0 usb_uart ] + + # Create ports + set reset [ create_bd_port -dir I -type rst reset ] + set_property -dict [ list \ + CONFIG.POLARITY {ACTIVE_HIGH} \ + ] $reset + set sys_clock [ create_bd_port -dir I -type clk sys_clock ] + set_property -dict [ list \ + CONFIG.FREQ_HZ {12000000} \ + CONFIG.PHASE {0.000} \ + ] $sys_clock + + # Create instance: axi_emc_0, and set properties + set axi_emc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_emc:3.0 axi_emc_0 ] + set_property -dict [ list \ + CONFIG.C_MAX_MEM_WIDTH {8} \ + CONFIG.C_MEM0_TYPE {1} \ + CONFIG.C_MEM0_WIDTH {8} \ + CONFIG.C_TAVDV_PS_MEM_0 {8000} \ + CONFIG.C_TCEDV_PS_MEM_0 {8000} \ + CONFIG.C_THZCE_PS_MEM_0 {8000} \ + CONFIG.C_THZOE_PS_MEM_0 {8000} \ + CONFIG.C_TLZWE_PS_MEM_0 {3000} \ + CONFIG.C_TWC_PS_MEM_0 {8000} \ + CONFIG.C_TWP_PS_MEM_0 {8000} \ + CONFIG.EMC_BOARD_INTERFACE {cellular_ram} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_emc_0 + + # Create instance: axi_gpio_0, and set properties + set axi_gpio_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_0 ] + set_property -dict [ list \ + CONFIG.C_INTERRUPT_PRESENT {1} \ + CONFIG.GPIO2_BOARD_INTERFACE {push_buttons_1bit} \ + CONFIG.GPIO_BOARD_INTERFACE {led_2bits} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_0 + + # Create instance: axi_gpio_1, and set properties + set axi_gpio_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_gpio:2.0 axi_gpio_1 ] + set_property -dict [ list \ + CONFIG.C_DOUT_DEFAULT {0x00000007} \ + CONFIG.GPIO_BOARD_INTERFACE {rgb_led} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_gpio_1 + + # Create instance: axi_intc_0, and set properties + set axi_intc_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_intc:4.1 axi_intc_0 ] + + # Create instance: axi_mem_intercon, and set properties + set axi_mem_intercon [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 axi_mem_intercon ] + set_property -dict [ list \ + CONFIG.M00_HAS_DATA_FIFO {2} \ + CONFIG.M00_HAS_REGSLICE {4} \ + CONFIG.NUM_MI {1} \ + CONFIG.NUM_SI {2} \ + CONFIG.S00_HAS_DATA_FIFO {2} \ + CONFIG.S00_HAS_REGSLICE {4} \ + CONFIG.S01_HAS_DATA_FIFO {2} \ + CONFIG.S01_HAS_REGSLICE {4} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $axi_mem_intercon + + # Create instance: axi_timer_0, and set properties + set axi_timer_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_timer:2.0 axi_timer_0 ] + + # Create instance: axi_uartlite_0, and set properties + set axi_uartlite_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_uartlite:2.0 axi_uartlite_0 ] + set_property -dict [ list \ + CONFIG.UARTLITE_BOARD_INTERFACE {usb_uart} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $axi_uartlite_0 + + # Create instance: clk_wiz_0, and set properties + set clk_wiz_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 clk_wiz_0 ] + set_property -dict [ list \ + CONFIG.CLKIN1_JITTER_PS {833.33} \ + CONFIG.CLKOUT1_JITTER {479.872} \ + CONFIG.CLKOUT1_PHASE_ERROR {668.310} \ + CONFIG.CLK_IN1_BOARD_INTERFACE {sys_clock} \ + CONFIG.MMCM_CLKFBOUT_MULT_F {62.500} \ + CONFIG.MMCM_CLKIN1_PERIOD {83.333} \ + CONFIG.MMCM_CLKIN2_PERIOD {10.0} \ + CONFIG.MMCM_CLKOUT0_DIVIDE_F {7.500} \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $clk_wiz_0 + + # Create instance: mdm_1, and set properties + set mdm_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:mdm:3.2 mdm_1 ] + + # Create instance: microblaze_0, and set properties + set microblaze_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:microblaze:10.0 microblaze_0 ] + set_property -dict [ list \ + CONFIG.C_DEBUG_ENABLED {1} \ + CONFIG.C_D_AXI {1} \ + CONFIG.C_D_LMB {1} \ + CONFIG.C_ICACHE_LINE_LEN {8} \ + CONFIG.C_ILL_OPCODE_EXCEPTION {0} \ + CONFIG.C_I_LMB {1} \ + CONFIG.C_MMU_ZONES {2} \ + CONFIG.C_M_AXI_D_BUS_EXCEPTION {1} \ + CONFIG.C_M_AXI_I_BUS_EXCEPTION {0} \ + CONFIG.C_NUMBER_OF_PC_BRK {2} \ + CONFIG.C_OPCODE_0x0_ILLEGAL {0} \ + CONFIG.C_UNALIGNED_EXCEPTIONS {0} \ + CONFIG.C_USE_BARREL {1} \ + CONFIG.C_USE_DCACHE {1} \ + CONFIG.C_USE_HW_MUL {1} \ + CONFIG.C_USE_ICACHE {1} \ + CONFIG.C_USE_MMU {0} \ + CONFIG.C_USE_MSR_INSTR {1} \ + CONFIG.C_USE_PCMP_INSTR {1} \ + CONFIG.G_TEMPLATE_LIST {6} \ + CONFIG.G_USE_EXCEPTIONS {1} \ + ] $microblaze_0 + + # Create instance: microblaze_0_axi_periph, and set properties + set microblaze_0_axi_periph [ create_bd_cell -type ip -vlnv xilinx.com:ip:axi_interconnect:2.1 microblaze_0_axi_periph ] + set_property -dict [ list \ + CONFIG.NUM_MI {5} \ + CONFIG.SYNCHRONIZATION_STAGES {2} \ + ] $microblaze_0_axi_periph + + # Create instance: microblaze_0_local_memory + create_hier_cell_microblaze_0_local_memory [current_bd_instance .] microblaze_0_local_memory + + # Create instance: rst_clk_wiz_0_100M, and set properties + set rst_clk_wiz_0_100M [ create_bd_cell -type ip -vlnv xilinx.com:ip:proc_sys_reset:5.0 rst_clk_wiz_0_100M ] + set_property -dict [ list \ + CONFIG.RESET_BOARD_INTERFACE {reset} \ + CONFIG.USE_BOARD_FLOW {true} \ + ] $rst_clk_wiz_0_100M + + # Create instance: xlconcat_0, and set properties + set xlconcat_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconcat:2.1 xlconcat_0 ] + + # Create interface connections + connect_bd_intf_net -intf_net axi_emc_0_EMC_INTF [get_bd_intf_ports cellular_ram] [get_bd_intf_pins axi_emc_0/EMC_INTF] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO [get_bd_intf_ports led_2bits] [get_bd_intf_pins axi_gpio_0/GPIO] + connect_bd_intf_net -intf_net axi_gpio_0_GPIO2 [get_bd_intf_ports push_buttons_1bit] [get_bd_intf_pins axi_gpio_0/GPIO2] + connect_bd_intf_net -intf_net axi_gpio_1_GPIO [get_bd_intf_ports rgb_led] [get_bd_intf_pins axi_gpio_1/GPIO] + connect_bd_intf_net -intf_net axi_intc_0_interrupt [get_bd_intf_pins axi_intc_0/interrupt] [get_bd_intf_pins microblaze_0/INTERRUPT] + connect_bd_intf_net -intf_net axi_mem_intercon_M00_AXI [get_bd_intf_pins axi_emc_0/S_AXI_MEM] [get_bd_intf_pins axi_mem_intercon/M00_AXI] + connect_bd_intf_net -intf_net axi_uartlite_0_UART [get_bd_intf_ports usb_uart] [get_bd_intf_pins axi_uartlite_0/UART] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DC [get_bd_intf_pins axi_mem_intercon/S00_AXI] [get_bd_intf_pins microblaze_0/M_AXI_DC] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_DP [get_bd_intf_pins microblaze_0/M_AXI_DP] [get_bd_intf_pins microblaze_0_axi_periph/S00_AXI] + connect_bd_intf_net -intf_net microblaze_0_M_AXI_IC [get_bd_intf_pins axi_mem_intercon/S01_AXI] [get_bd_intf_pins microblaze_0/M_AXI_IC] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M00_AXI [get_bd_intf_pins axi_gpio_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M00_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M01_AXI [get_bd_intf_pins axi_gpio_1/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M01_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M02_AXI [get_bd_intf_pins axi_uartlite_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M02_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M03_AXI [get_bd_intf_pins axi_timer_0/S_AXI] [get_bd_intf_pins microblaze_0_axi_periph/M03_AXI] + connect_bd_intf_net -intf_net microblaze_0_axi_periph_M04_AXI [get_bd_intf_pins axi_intc_0/s_axi] [get_bd_intf_pins microblaze_0_axi_periph/M04_AXI] + connect_bd_intf_net -intf_net microblaze_0_debug [get_bd_intf_pins mdm_1/MBDEBUG_0] [get_bd_intf_pins microblaze_0/DEBUG] + connect_bd_intf_net -intf_net microblaze_0_dlmb_1 [get_bd_intf_pins microblaze_0/DLMB] [get_bd_intf_pins microblaze_0_local_memory/DLMB] + connect_bd_intf_net -intf_net microblaze_0_ilmb_1 [get_bd_intf_pins microblaze_0/ILMB] [get_bd_intf_pins microblaze_0_local_memory/ILMB] + + # Create port connections + connect_bd_net -net axi_gpio_0_ip2intc_irpt [get_bd_pins axi_gpio_0/ip2intc_irpt] [get_bd_pins xlconcat_0/In1] + connect_bd_net -net axi_timer_0_interrupt [get_bd_pins axi_timer_0/interrupt] [get_bd_pins xlconcat_0/In0] + connect_bd_net -net clk_wiz_0_locked [get_bd_pins clk_wiz_0/locked] [get_bd_pins rst_clk_wiz_0_100M/dcm_locked] + connect_bd_net -net mdm_1_debug_sys_rst [get_bd_pins mdm_1/Debug_SYS_Rst] [get_bd_pins rst_clk_wiz_0_100M/mb_debug_sys_rst] + connect_bd_net -net microblaze_0_Clk [get_bd_pins axi_emc_0/rdclk] [get_bd_pins axi_emc_0/s_axi_aclk] [get_bd_pins axi_gpio_0/s_axi_aclk] [get_bd_pins axi_gpio_1/s_axi_aclk] [get_bd_pins axi_intc_0/s_axi_aclk] [get_bd_pins axi_mem_intercon/ACLK] [get_bd_pins axi_mem_intercon/M00_ACLK] [get_bd_pins axi_mem_intercon/S00_ACLK] [get_bd_pins axi_mem_intercon/S01_ACLK] [get_bd_pins axi_timer_0/s_axi_aclk] [get_bd_pins axi_uartlite_0/s_axi_aclk] [get_bd_pins clk_wiz_0/clk_out1] [get_bd_pins microblaze_0/Clk] [get_bd_pins microblaze_0_axi_periph/ACLK] [get_bd_pins microblaze_0_axi_periph/M00_ACLK] [get_bd_pins microblaze_0_axi_periph/M01_ACLK] [get_bd_pins microblaze_0_axi_periph/M02_ACLK] [get_bd_pins microblaze_0_axi_periph/M03_ACLK] [get_bd_pins microblaze_0_axi_periph/M04_ACLK] [get_bd_pins microblaze_0_axi_periph/S00_ACLK] [get_bd_pins microblaze_0_local_memory/LMB_Clk] [get_bd_pins rst_clk_wiz_0_100M/slowest_sync_clk] + connect_bd_net -net reset_1 [get_bd_ports reset] [get_bd_pins clk_wiz_0/reset] [get_bd_pins rst_clk_wiz_0_100M/ext_reset_in] + connect_bd_net -net rst_clk_wiz_0_100M_bus_struct_reset [get_bd_pins microblaze_0_local_memory/SYS_Rst] [get_bd_pins rst_clk_wiz_0_100M/bus_struct_reset] + connect_bd_net -net rst_clk_wiz_0_100M_interconnect_aresetn [get_bd_pins axi_mem_intercon/ARESETN] [get_bd_pins microblaze_0_axi_periph/ARESETN] [get_bd_pins rst_clk_wiz_0_100M/interconnect_aresetn] + connect_bd_net -net rst_clk_wiz_0_100M_mb_reset [get_bd_pins microblaze_0/Reset] [get_bd_pins rst_clk_wiz_0_100M/mb_reset] + connect_bd_net -net rst_clk_wiz_0_100M_peripheral_aresetn [get_bd_pins axi_emc_0/s_axi_aresetn] [get_bd_pins axi_gpio_0/s_axi_aresetn] [get_bd_pins axi_gpio_1/s_axi_aresetn] [get_bd_pins axi_intc_0/s_axi_aresetn] [get_bd_pins axi_mem_intercon/M00_ARESETN] [get_bd_pins axi_mem_intercon/S00_ARESETN] [get_bd_pins axi_mem_intercon/S01_ARESETN] [get_bd_pins axi_timer_0/s_axi_aresetn] [get_bd_pins axi_uartlite_0/s_axi_aresetn] [get_bd_pins microblaze_0_axi_periph/M00_ARESETN] [get_bd_pins microblaze_0_axi_periph/M01_ARESETN] [get_bd_pins microblaze_0_axi_periph/M02_ARESETN] [get_bd_pins microblaze_0_axi_periph/M03_ARESETN] [get_bd_pins microblaze_0_axi_periph/M04_ARESETN] [get_bd_pins microblaze_0_axi_periph/S00_ARESETN] [get_bd_pins rst_clk_wiz_0_100M/peripheral_aresetn] + connect_bd_net -net sys_clock_1 [get_bd_ports sys_clock] [get_bd_pins clk_wiz_0/clk_in1] + connect_bd_net -net xlconcat_0_dout [get_bd_pins axi_intc_0/intr] [get_bd_pins xlconcat_0/dout] + + # Create address segments + create_bd_addr_seg -range 0x00080000 -offset 0x60000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_emc_0/S_AXI_MEM/Mem0] SEG_axi_emc_0_MEM0 + create_bd_addr_seg -range 0x00080000 -offset 0x60000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs axi_emc_0/S_AXI_MEM/Mem0] SEG_axi_emc_0_MEM0 + create_bd_addr_seg -range 0x00010000 -offset 0x40000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_0/S_AXI/Reg] SEG_axi_gpio_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40010000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_gpio_1/S_AXI/Reg] SEG_axi_gpio_1_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x41200000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_intc_0/S_AXI/Reg] SEG_axi_intc_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x41C00000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_timer_0/S_AXI/Reg] SEG_axi_timer_0_Reg + create_bd_addr_seg -range 0x00010000 -offset 0x40600000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs axi_uartlite_0/S_AXI/Reg] SEG_axi_uartlite_0_Reg + create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Data] [get_bd_addr_segs microblaze_0_local_memory/dlmb_bram_if_cntlr/SLMB/Mem] SEG_dlmb_bram_if_cntlr_Mem + create_bd_addr_seg -range 0x00008000 -offset 0x00000000 [get_bd_addr_spaces microblaze_0/Instruction] [get_bd_addr_segs microblaze_0_local_memory/ilmb_bram_if_cntlr/SLMB/Mem] SEG_ilmb_bram_if_cntlr_Mem + + + # Restore current instance + current_bd_instance $oldCurInst + + save_bd_design +} +# End of create_root_design() + + +################################################################## +# MAIN FLOW +################################################################## + +create_root_design "" + +