This project is a demonstration of the Pmod I2S2. It creates a pass-through from Line-In to the Line-Out jack. The audio data coming through this passthrough is scaled by the number of switches on the FPGA that are closed. All switches open means that the data stream will be muted. All switches closed means that the data stream will be at full volume. The audio volume scales linearly between these two points.
In order to use this demo, a Pmod I2S2 and one of the Digilent FPGA development boards presented in the table below are required. In addition, headphones or speakers and an audio input source (such as a personal computer) are also required.
WARNING!!! This project is only supported in the 2017.4 version of Vivado.
The table below describes how inputs and outputs to this demo are connected, depending on the development board used:
|Board (Resource Center Link)||I2S2 Pmod Connector||Volume Input||Reset|
|Arty A7-35||JA||SW3-SW0||RESET Button|
|Arty A7-100||JA||SW3-SW0||RESET Button|
|Arty S7-25||JA||SW3-SW0||RESET Button|
|Arty S7-50||JA||SW3-SW0||RESET Button|
This project is formatted a little differently than the standard Digilent Github project.
In order to program the project onto an FPGA:
Download the latest release ZIP (not the source ZIP) for the target FPGA board from the repo's releases page.
Extract and open the downloaded ZIP. Double click on "I2S2.xpr". This will launch an archived version of the project, in which a bitstream has already been generated.
Open the Vivado Hardware Manager, select "Open Target", and find the target board.
Program top.bit onto the target. This file can be found within the PmodI2S2/PmodI2S2.runs/impl_1 folder.
In order to open a Vivado project after cloning this repo:
Open Vivado, in the TCL console at the bottom of the window, CD into the folder of the target board (ex: arty-a7-35).
Call "source ./create_project.tcl". This will set appropriate parameters, then source ../scripts/create_project.tcl, then make any other necessary modifications to the project.