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@sbobrowicz
sbobrowicz Add support for Arty S7-50 
Initial commit, adding support for the Arty S7-50.
Latest commit 06fa767 Aug 18, 2017
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Arty-S7-50 Add support for Arty S7-50 Aug 18, 2017
README.md Add support for Arty S7-50 Aug 18, 2017

README.md

This Repository holds Xilinx Memory Interface Generator (MIG) settings for Digilent boards. These settings can be imported directly in the MIG IP Core in Vivado.