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A crazy small 8-bit CPU built with only seventeen 7400-series chips.
Perl Verilog Makefile Shell
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Docs Fixed up the assembler docs a bit more. Jun 8, 2019
Examples I've added the scripts that I use to burn the ROMs. I've added a new Jun 5, 2019
ROMs Updated the journal with details of the new logic analyser and the Jun 6, 2019
Schematic I've updated the schematic and the PCB to have the 74HCT151 chip. Jun 7, 2019
.gitignore I've added the scripts that I use to burn the ROMs. I've added a new Jun 5, 2019
74138.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
74139.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
74151.v I just realised that a 74HCT151 should fix the jump glitch. Jun 6, 2019
74161.v
74251.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
74574.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
74593.v Fixed a bug with the PC incrementing incorrectly. May 4, 2019
LICENSE Initial commit Mar 27, 2019
Makefile Updated the diagrams of the design. Apr 24, 2019
README.md More details on RAM & ROM Sep 14, 2019
cas I've added the scripts that I use to burn the ROMs. I've added a new Jun 5, 2019
clc
csim
disasm
empty.ram I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
gen_alu Some more rewording of the documentation. May 13, 2019
gen_ucode
icarus_tb.v The rewiring of the TTL verilog version has forced an increase in the Apr 25, 2019
journal.md Another journal update. Jun 9, 2019
microcode I've updated the microcode to have the jump instructions with Jun 7, 2019
opcodes I've added the scripts that I use to burn the ROMs. I've added a new Jun 5, 2019
ram.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
rom.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
tbhelper.v I've removed the original Verilog version and now have just the TTL V… Apr 23, 2019
ttlcsvon8.v I've updated the Verilog version of the CPU, and the documentation, Jun 7, 2019
uart.v

README.md

CSCvon8: 8-bit von Neumann Crazy Small CPU

This repository holds the files for my 8-bit "big brother" CPU to the 4-bit Crazy Small CPU. This is a von Neumann style CPU designed with 7400-style logic chips, 32K of RAM, 32K of ROM and a UART. The CPU requires only seventeen chips, not including the clock circuitry. A short video is here.

The overall design of the CPU is covered in Docs/CSCvon8_design.md. Also read the getting started guide and the guide to building the PCB version.

As at the 18th May 2019 I have the CPU running solidly at 3.57MHz on the PCBs that I ordered from the PCB design in the Schematics folder. I've kept a journal with details of my progress from the initial design phase through to the successful build.

The files and folders in this repository are:

  • Docs, documents on the design and how to use the tools below
  • Examples, example programs for the CPU
  • Schematic, a KiCad schematic of the CPU
  • cas, the assembler for the CPU
  • clc, a very crude compiler that outputs assembly that can be given to cas
  • csim, a simulator of the CPU written in Perl
  • disasm, a tool to disassemble the instruction ROM contents
  • gen_alu, a program to generate the contents of the ALU ROM
  • gen_ucode, a program to generate the contents of the Decode ROM
  • journal.txt, my running journal of the design and implementation of CSCvon8

There is also a Verilog version with the top-level file being ttlcsvon8.v, the testbench is icarus_tb.v and the Makefile will build and run the Verilog testbench. Some notes on this implementation are in the Docs/implementation_notes.md file.

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