Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.
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ArtyS7_RPU_SoC.srcs
PREBUILT
RPU @ 12f77e8
code
hdl
rom/coe
.gitmodules
ArtyS7_RPU_SoC.xpr
LICENSE
README.md

README.md

ArtyS7-RPU-SoC

Project for an RPU RISC-V system on chip implementation on the Digilent Arty S7-50 FPGA development board.