{"payload":{"header_redesign_enabled":false,"results":[{"id":"381388002","archived":false,"color":"#b2b7f8","followers":4,"has_funding_file":false,"hl_name":"Dreadrik/fpga-stopwatch","hl_trunc_description":"A breadboard stopwatch implemented using an iCE40HX8K FPGA.","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":381388002,"name":"fpga-stopwatch","owner_id":6776756,"owner_login":"Dreadrik","updated_at":"2021-06-30T11:42:09.817Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":93,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ADreadrik%252Ffpga-stopwatch%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/Dreadrik/fpga-stopwatch/star":{"post":"-bzxxurk2qGn0ZMIAuqGpmM8YSbsRzG6NJqgtq_hEapNqGCi18WsBD6kSnqpvRj-cv9NJImWv3jgMLAoVta2iw"},"/Dreadrik/fpga-stopwatch/unstar":{"post":"h8mzq0RtSIocyJxXVrsezoCNTu9qQpl8FpToaTMD9dfwKxhUCD3V1LgzURhJFu-6pMjSHf-tAPfBrDS-1xfKrg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"crY3zEYFUaFF28uPbiMCodplPOyn8_Gxjxc74A2rDdlZte_IEr_ZIuCYKPZpzxsH0IgIJuaWH1vUaT6jLy7hKw"}}},"title":"Repository search results"}