diff --git a/core/arch/aarch64/proc.c b/core/arch/aarch64/proc.c
index e3bfc9f4b3f..989d6bf856d 100644
--- a/core/arch/aarch64/proc.c
+++ b/core/arch/aarch64/proc.c
@@ -114,7 +114,6 @@ get_processor_specific_info(void)
      */
 #        if !defined(DR_HOST_NOT_TARGET)
     if (proc_has_feature(FEATURE_SVE)) {
-#            if !defined(BUILD_TESTS)
         uint64 vl;
         /* This RDVL instruction is inserted as raw hex because we don't build
          * with SVE enabled: i.e. not -march=armv8-a+sve, so that we can run a
@@ -129,10 +128,6 @@ get_processor_specific_info(void)
             : "x0");
         cpu_info.sve_vector_length_bytes = vl;
         dr_set_sve_vector_length(vl * 8);
-#            else
-        cpu_info.sve_vector_length_bytes = 32;
-        dr_set_sve_vector_length(256);
-#            endif
     } else {
         cpu_info.sve_vector_length_bytes = 32;
         dr_set_sve_vector_length(256);
diff --git a/core/ir/aarch64/codec.h b/core/ir/aarch64/codec.h
index 4fe2eaa54c8..81de59b069f 100644
--- a/core/ir/aarch64/codec.h
+++ b/core/ir/aarch64/codec.h
@@ -57,7 +57,7 @@ encode_common(byte *pc, instr_t *i, decode_info_t *di);
 #define BITS(_enc, bitmax, bitmin) \
     ((((uint32)(_enc)) >> (bitmin)) & (uint32)MASK((bitmax) - (bitmin) + 1))
 
-#if !defined(DR_HOST_NOT_TARGET) && !defined(STANDALONE_DECODER)
+#if !defined(DR_HOST_NOT_TARGET) && !defined(STANDALONE_DECODER) && !defined(BUILD_TESTS)
 #    define OPSZ_SVE_VL_BYTES opnd_size_from_bytes(proc_get_vector_length_bytes())
 #    define OPSZ_SVE_PL_BYTES opnd_size_from_bytes(proc_get_vector_length_bytes() / 8)
 #else