From d0f6386d7765871d70ecbb87e768bbd84165130e Mon Sep 17 00:00:00 2001 From: Derek Bruening Date: Wed, 9 Aug 2023 17:04:03 -0400 Subject: [PATCH] i#5843 scheduler: Use input instead of tid in launcher (#6255) Switches from using the tid in scheduler_launcher to distinguish inputs to the input ordinal. Tid values can be duplicated so they should not be used as unique identifiers across workloads. Tested: No automated test currently relies on the launcher; it is there for experimentation and as an example for how to use the scheduler, so we want it to use the recommended techniques. I ran it on the threadsig app and confirmed record and replay are using ordinals: ``` $ rm -rf drmemtrace.*.dir; bin64/drrun -stderr_mask 12 -t drcachesim -offline -- ~/dr/test/threadsig 16 2000 && bin64/drrun -t drcachesim -simulator_type basic_counts -indir drmemtrace.*.dir > COUNTS 2>&1 && clients/bin64/scheduler_launcher -trace_dir drmemtrace.*.dir/trace -num_cores 4 -sched_quantum 2000 -record_file record.zip > RECORD 2>&1 && clients/bin64/scheduler_launcher -trace_dir drmemtrace.*.dir/trace -num_cores 4 -replay_file record.zip > REPLAY 2>&1 && tail -n 4 RECORD REPLAY Estimation of pi is 3.141592674423126 Received 89 alarms ==> RECORD <== Core #0: 16 15 16 15 16 0 15 16 15 8 16 6 5 7 Core #1: 9 3 12 16 11 16 8 0 16 0 16 1 16 Core #2: 3 14 16 14 16 0 15 16 8 16 2 6 8 1 10 Core #3: 13 3 13 9 11 12 16 6 16 6 16 2 4 ==> REPLAY <== Core #0: 16 15 16 15 16 0 15 16 15 8 16 6 5 7 Core #1: 9 3 12 16 11 16 8 0 16 0 16 1 16 Core #2: 3 14 16 14 16 0 15 16 8 16 2 6 8 1 10 Core #3: 13 3 13 9 11 12 16 6 16 6 16 2 4 ``` Issue: #5843 --- .../drcachesim/tests/scheduler_launcher.cpp | 25 ++++++++++--------- 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/clients/drcachesim/tests/scheduler_launcher.cpp b/clients/drcachesim/tests/scheduler_launcher.cpp index 75aec0db159..46cb0a64721 100644 --- a/clients/drcachesim/tests/scheduler_launcher.cpp +++ b/clients/drcachesim/tests/scheduler_launcher.cpp @@ -54,7 +54,6 @@ using ::dynamorio::drmemtrace::disable_popups; using ::dynamorio::drmemtrace::memref_t; -using ::dynamorio::drmemtrace::memref_tid_t; using ::dynamorio::drmemtrace::scheduler_t; using ::dynamorio::drmemtrace::TRACE_TYPE_MARKER; using ::dynamorio::drmemtrace::trace_type_names; @@ -107,10 +106,11 @@ droption_t void simulate_core(int ordinal, scheduler_t::stream_t *stream, const scheduler_t &scheduler, - std::vector &thread_sequence) + std::vector &thread_sequence) { memref_t record; - memref_tid_t prev_tid = INVALID_THREAD_ID; + // Thread ids can be duplicated, so use the input ordinals to distinguish. + scheduler_t::input_ordinal_t prev_input = scheduler_t::INVALID_INPUT_ORDINAL; for (scheduler_t::stream_status_t status = stream->next_record(record); status != scheduler_t::STATUS_EOF; status = stream->next_record(record)) { if (status == scheduler_t::STATUS_WAIT) { @@ -142,18 +142,18 @@ simulate_core(int ordinal, scheduler_t::stream_t *stream, const scheduler_t &sch line << "\n"; std::cerr << line.str(); } + scheduler_t::input_ordinal_t input = stream->get_input_stream_ordinal(); if (thread_sequence.empty()) - thread_sequence.push_back(record.instr.tid); - else if (record.instr.tid != prev_tid) { - thread_sequence.push_back(record.instr.tid); + thread_sequence.push_back(input); + else if (stream->get_input_stream_ordinal() != prev_input) { + thread_sequence.push_back(input); if (op_verbose.get_value() > 0) { std::ostringstream line; line << "Core #" << std::setw(2) << ordinal << " @" << std::setw(9) << stream->get_record_ordinal() << " refs, " << std::setw(9) << stream->get_instruction_ordinal() << " instrs: input " - << std::setw(4) << stream->get_input_stream_ordinal() << " @" - << std::setw(9) + << std::setw(4) << input << " @" << std::setw(9) << scheduler .get_input_stream_interface(stream->get_input_stream_ordinal()) ->get_record_ordinal() @@ -169,7 +169,7 @@ simulate_core(int ordinal, scheduler_t::stream_t *stream, const scheduler_t &sch std::cerr << line.str(); } } - prev_tid = record.instr.tid; + prev_input = input; } } @@ -227,7 +227,8 @@ _tmain(int argc, const TCHAR *targv[]) } std::vector threads; - std::vector> schedules(op_num_cores.get_value()); + std::vector> schedules( + op_num_cores.get_value()); std::cerr << "Creating " << op_num_cores.get_value() << " simulator threads\n"; threads.reserve(op_num_cores.get_value()); for (int i = 0; i < op_num_cores.get_value(); ++i) { @@ -239,8 +240,8 @@ _tmain(int argc, const TCHAR *targv[]) for (int i = 0; i < op_num_cores.get_value(); ++i) { std::cerr << "Core #" << i << ": "; - for (memref_tid_t tid : schedules[i]) - std::cerr << tid << " "; + for (scheduler_t::input_ordinal_t input : schedules[i]) + std::cerr << input << " "; std::cerr << "\n"; }