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MMX - Miner Manager with Extension

Miner Manager is a stratum task generator firmware that fit FPGA and ASIC miners.

Main objectives

  • It is using stratum protocol
  • It generate the tasks (block headers) inside FPGA. all Double-SHA256 was done by FPGA, far more faster than CPU
  • Test the nonce inside the FPGA. only report the >= DIFF tasks back to the host (CGMiner)
  • It fits any kinds of stratum mining ASIC
  • It has a RISC-V 32 bit CPU inside (PicoRV32)

Directory structure

  • firmware: C codes running in PicoRV32 soft processor
  • platform: platform hardware library
  • testbench: hardware testbench
  • top: hardware top module & constrain
  • modules: 3rd party modules

Clone the code

  $ git clone --recursive

Tools being used

  1. Vivado: install vivado and source the setttings, we use 2019.2 as default
  2. FuseSoC: for IP-packaging and project generation
  3. Cheby: for register-map generation
  4. vhd2vl: for converting from VHDL to Verilog code
  5. RV32IMC toolchain: compile with IMC extension, we choose /opt/riscv32imc as default install directory.

How to build & sim?

Before the build & sim, we need to setup the environment first.

  $ fusesoc init
  $ fusesoc library add --global mmx .
  • Build with Vivado
   $ make
  • Load the bitstream with Vivado
   $ make load      # Load the bitstream to FPGA
  • Sim with icarus
   $ make sim
   $ make view

Hardware support

  • ZedBoard



  • Add toolchain compile support
  • Add uart debug support
  • Add btc core support


This is free and unencumbered public domain software. For more information, see or the accompanying UNLICENSE file.

Some files may have their own license disclaim by the author.


MM firmware with extension




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