EE 201 Final Project
Verilog VHDL
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finalprojct_ee201_AJ_TL
README.md
add_module.v
bak.ucf
calc_project_top.ucf
calc_project_top.v
ee201_debounce_DPB_SCEN_CCEN_MCEN.v
lcd_core.v
lcd_screen_core_tb.v
main_calc_cu.v
main_cu.v
merge_arrays_mcu_top.v

README.md

EE201

Project Overview:

Our project is to design a scientific calculator using an FPGA to get user input and a combination of SSDs and the LCD Screen to give visual feedback to the user. Our calculator will implement the following functions: addition, subtraction, multiplication, division, gcd, square root, prime factorization, isPrime.

Each one of these functions will lead the user into a sub-State Machine that will prompt the user for the correct number of inputs (one or two) and then step slowly through the operation (slow enough for the user to see) selected in the main state machine.
The User will enter numbers through the 8 switches at the bottom of the FPGA. The maximum value needed to hold the maximum possible variables is a 16-bit value (2^8 * 2^8 is the largest operation possible in this calculator, which is 16 bits long).
After the value is calculated, it will be marched across the screen until the user wants to perform a new action. Then the entire operation repeats itself.

Tech. Requirements: LCD Screen Only

Usage: Implement calc_project_top.bit

Editing: Run calc_project.xise

Members: Alex Jones Tobias Lee