FPGA code for Elphel NC393 camera
Verilog Python HCL SystemVerilog Coq Tcl Other
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.eclipse_project_setup updated settings Oct 4, 2016
.settings restored settins for tghe x393 simulation (from dct-iv) Dec 6, 2016
axi
cocotb correcting histograms to system memory transfer Jan 9, 2017
compressor_jp corrected memsensor/memcompressor line comparison Nov 17, 2016
ddr3 testing and simulating, improving timing Nov 3, 2015
docs Description of the memory controller clocks and programmable delays Mar 15, 2015
dsp committing pending changes Jan 7, 2017
hardware_tests eye pattern tests at 400MHz Jun 15, 2014
helpers
includes synchronized with x393_sata, added irq on/off logging Dec 11, 2016
input_data added more simulation images, more fixing of JPEG tail Nov 14, 2016
logger modifying timestamps/triggering Nov 13, 2016
memctrl corrected memsensor/memcompressor line comparison Nov 17, 2016
py393
sensor correcting histograms to system memory transfer Jan 9, 2017
simulation_data improving sensor_i2c May 15, 2016
simulation_modules added more simulation images, more fixing of JPEG tail Nov 14, 2016
timing correcting triggering - there was a false trigger when turning on ext… Nov 22, 2016
unisims_extra Modified headers to work with doxverilog2.5/doxygen1.7.0 Jun 5, 2016
unisims_patches patch to work with Icarus Verilog simulator Jun 15, 2014
util_modules disabling SoF for disabled channels Nov 7, 2016
wrap working with cocotb simulation Jul 10, 2016
x393_sata synchronized with x393_sata, added irq on/off logging Dec 11, 2016
.editor_defines working to add cocotb simualtion Jul 1, 2016
.gitignore
INIT_PROJECT tweaking INIT_PROJECT May 17, 2016
Makefile more startup commands variants Nov 5, 2016
OSERDESE1.diff Modifications for Icarus Verilog Jun 24, 2014
README.md Update README.md Jul 12, 2016
VERSION Changed interrupt lines Aug 1, 2016
address_map.txt before adding extra register layer between channel buffers outputs an… Feb 23, 2015
copy_x393_sata.sh removed stray line Apr 13, 2016
dct_tests_01.sav committing pending changes Jan 7, 2017
ddrc_test01.xcf Typo in file headers Nov 8, 2015
ddrc_test01.xdc Typo in file headers Nov 8, 2015
ddrc_test01_testbench.sav more changes to convert project Jan 11, 2015
ddrc_test01_timing.xdc Typo in file headers Nov 8, 2015
fpga_version.vh correcting histograms to system memory transfer Jan 9, 2017
glbl.v debugging larger frames write/read Feb 17, 2015
install.sh added cocotb server/client Jul 20, 2016
system_defines.vh Added odd/even shift to parallel sensors hact Oct 15, 2016
x393.v Implemented Eyesis external trigger, lost trigger recover Oct 27, 2016
x393.xcf Typo in file headers Nov 8, 2015
x393_1_7_0.Doxyfile Switched to new implementation of 8x8 DCT, generated documentation Jun 13, 2016
x393_1_8_2.Doxyfile minor fixes Jul 12, 2016
x393_diagram.png Cropped image Jun 19, 2016
x393_diagram.svg Cropped image Jun 19, 2016
x393_global.tcl made a separate constraints file with global definitions (used in bot… Mar 29, 2016
x393_hispi.bit
x393_parallel.bit correcting histograms to system memory transfer Jan 9, 2017
x393_placement.tcl
x393_testbench01.sav making previous simulation tasks run on the full x393 code Aug 1, 2015
x393_testbench01.tf working on address export for C, fixed some copied typos in multiple … Mar 24, 2016
x393_testbench02.sav testing and simulating, improving timing Nov 3, 2015
x393_testbench02.tf exported compressor channel status, some typo fixes Mar 30, 2016
x393_testbench03.sav multiple changes, synchronizing simulation with hardware May 5, 2016
x393_testbench03.tf individual camsync timestamp control Aug 6, 2016
x393_testbench04.gtkw another samll set of simulation signals Mar 16, 2016
x393_testbench04.sav fixing hispi decoder (had problems for large (>1 clock after re-sync)… Jul 13, 2016
x393_timing.tcl modified to work with Vivado 2016.2, but 2015.3 still provides better… Jul 14, 2016

README.md

x393

x393 Block Diagram

FPGA code for Elphel 393 camera, created with VDT plugin. It runs on Xilinx Zynq 7030 SoC (FPGA plus dual ARM).

Documentation is generated with Doxygen-based Doxverilog.

Run ./INIT_PROJECT in the top directory to copy initial .project and .pydevproject files for Eclipse

Simulation of this project requires some files from the Xilinx proprietary unisims library (list of dependencies is in this blog post). VDT plugin README file describes steps needed after installation of Xilinx software (unisims library is not distributed separately).

Python program used on the target and during Cocotb simulation requires Python numpy module, on Ubuntu you may install it with

sudo apt-get install python-numpy