RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
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README.md

RISC-V CPU

Zhou Fan (范舟)

This project is a RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, which is a course project of Computer Architecture, ACM Class @ SJTU.

Documents

Design

Feature RISC-V CPU
ISA RISC-V (RV32I subset)
Pipelining 5 stages
Data forwarding
Cache N-way set associate I-cache and D-cache [1]
UART module passed simulation [2]
Security perfect proof against Meltdown and Spectre attack [3]
  • [1] The cache is based on Zhekai Zhang's code
  • [2] UART module has not passed test on FPGA yet for the limited time. I re-designed part of CPU code to avoid hidden danger on FPGA, and it may need some more debugging.
  • [3] Just kidding ;-) That's because the CPU is not with branch prediction or out-of-order execution.

This CPU project has a five stage pipeline with data forwarding. In the picture below, red paths show stall control flow, while orange ones show data forwarding path. cpu-pipeline-graph

For program test on FPGA without capable memory, this CPU uses UART protocol to communicate with PC, where runs a memory simulator. uart-simulate-memory

Simulation

This CPU is simulated with UART communication module in Xilinx vivado. test-bench-wave

Implementation

Implementation on Basys3 FPGA, using Xilinx vivado. implementation-graph Scematic Overview implementation-circuit-overview CPU Module Scematic implementation-circuit-cpu

References