Zhou Fan (范舟)
This project is a RISC-V CPU with 5-stage pipeline implemented in Verilog HDL, which is a course project of Computer Architecture, ACM Class @ SJTU.
- My Project Report
- My blog post for installation and usage of RISV-V GNU toolchain (In Chinese) (on GitHub)
- RISC-V 32I subset supported in this CPU project
|ISA||RISC-V (RV32I subset)|
|Cache||N-way set associate I-cache and D-cache |
|UART module||passed simulation |
|Security||perfect proof against Meltdown and Spectre attack |
-  The cache is based on Zhekai Zhang's code
-  UART module has not passed test on FPGA yet for the limited time. I re-designed part of CPU code to avoid hidden danger on FPGA, and it may need some more debugging.
-  Just kidding ;-) That's because the CPU is not with branch prediction or out-of-order execution.