From 9203b58a422dd3c395debc8198df776c9f1be07b Mon Sep 17 00:00:00 2001 From: "C.Prados" Date: Thu, 30 Mar 2017 11:45:33 +0200 Subject: [PATCH] plls: add new pll arria5 with only 1 clock output for butis 200Mhz Every time white rabbit is down and up the pps pulses were getting lock to a different point +/- 8ns in step of 1ns. For more information about the bug a how this commit fixes the issue, read: https://github.com/GSI-CS-CO/bel_projects/issues/6 --- modules/monster/monster.vhd | 16 ++- modules/pll/arria5/arria5_pll.tcl | 2 +- modules/pll/arria5/butis_pll5.txt | 206 ++++++++++++++++++++++++++++++ modules/pll/pll_pkg.vhd | 8 ++ 4 files changed, 227 insertions(+), 5 deletions(-) create mode 100644 modules/pll/arria5/butis_pll5.txt diff --git a/modules/monster/monster.vhd b/modules/monster/monster.vhd index a7663249be..80cdbc72c9 100644 --- a/modules/monster/monster.vhd +++ b/modules/monster/monster.vhd @@ -545,12 +545,14 @@ architecture rtl of monster is -- Ref PLL from clk_125m_pllref_i signal ref_locked : std_logic; + signal butis_locked : std_logic; signal clk_ref0 : std_logic; signal clk_ref1 : std_logic; signal clk_ref2 : std_logic; signal clk_ref3 : std_logic; signal clk_ref4 : std_logic; - + signal clk_ref_butis : std_logic; + signal clk_ref : std_logic; signal clk_butis : std_logic; signal clk_phase : std_logic; @@ -905,7 +907,13 @@ begin outclk_2 => clk_ref2, -- 25 MHz outclk_3 => clk_ref3, --1000 MHz outclk_4 => clk_ref4, -- 125 MHz, 1/8 duty, -1.5ns phase - locked => ref_locked, + locked => ref_locked); + + butis_inst : butis_pll5 port map( + rst => pll_rst, + refclk => core_clk_125m_pllref_i, -- 125 MHz + outclk_0 => clk_ref_butis, -- 200 MHz + locked => butis_locked, scanclk => clk_free, cntsel => phase_sel, phase_en => phase_step, @@ -920,7 +928,7 @@ begin g_base => 0, g_vco_freq => 1000, -- 1GHz g_output_freq => (0 => 200), - g_output_select => (0 => f_pick(c_is_arria5, 4, 3))) + g_output_select => (0 => f_pick(c_is_arria5, 0, 3))) port map( clk_i => clk_free, rstn_i => rstn_free, @@ -938,7 +946,7 @@ begin --butis_clk : global_region port map( -- inclk => clk_ref1, -- outclk => clk_butis); - clk_butis <= clk_ref1; + clk_butis <= clk_ref_butis; clk_div: process(clk_ref0) variable cnt: integer := 0; diff --git a/modules/pll/arria5/arria5_pll.tcl b/modules/pll/arria5/arria5_pll.tcl index a70d38d397..fd668169d8 100644 --- a/modules/pll/arria5/arria5_pll.tcl +++ b/modules/pll/arria5/arria5_pll.tcl @@ -1 +1 @@ -qmegawiz { sys_pll5 ref_pll5 dmtd_pll5 } +qmegawiz { sys_pll5 ref_pll5 dmtd_pll5 butis_pll5} diff --git a/modules/pll/arria5/butis_pll5.txt b/modules/pll/arria5/butis_pll5.txt new file mode 100644 index 0000000000..e53d25a86d --- /dev/null +++ b/modules/pll/arria5/butis_pll5.txt @@ -0,0 +1,206 @@ +-- megafunction wizard: %Altera PLL v13.0% +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval info: +-- Retrieval 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butis_pll5 is -- arria5 + port( + refclk : in std_logic := 'X'; -- 125 MHz + outclk_0 : out std_logic; -- 200 MHz + rst : in std_logic := 'X'; locked : out std_logic; scanclk : in std_logic; cntsel : in std_logic_vector(4 downto 0);