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ZPUino variant for the Arcade MegaWing 2.1 on the P1 500K.

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1 parent c78b251 commit 71c21378ab3fecbdc163da5e605f73fa63031aa2 @jackgassett jackgassett committed Aug 6, 2012
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+PROJECT=papilio_one
+PART=xc3s500e-vq100-4
+
+# For bootloader
+BOARD=PAPILIO_ONE
+SIZE=16384
+DEFINES="-D__S3E_500__ -DBOARD_ID=0xA4010E01 -DBOARD_MEMORYSIZE=0x4000 -DCLK_FREQ=92000000"
+
+BOOTPATH=../../../../../
+
+all: ${PROJECT}_routed.bit ${PROJECT}_routed.bin
+
+prom-generic-dp-32.vhd:
+ $(MAKE) -C $(BOOTPATH)bootloader BOARD=$(BOARD) SIZE=$(SIZE) DEFINES=$(DEFINES)
+ cp $(BOOTPATH)bootloader/prom-generic-dp-32.vhd .
+
+${PROJECT}.ngc: prom-generic-dp-32.vhd
+ mkdir -p xst/projnav.tmp/
+ xst -intstyle ise -ifn ${PROJECT}.xst -ofn ${PROJECT}.syr
+
+${PROJECT}.ngd: ${PROJECT}.ngc
+ ngdbuild -intstyle ise -dd _ngo -nt timestamp \
+ -uc ${PROJECT}.ucf -p ${PART} ${PROJECT}.ngc ${PROJECT}.ngd
+
+${PROJECT}.ncd: ${PROJECT}.ngd
+ map -intstyle ise -p ${PART} \
+ -cm speed -detail -ir off -ignore_keep_hierarchy -pr b -register_duplication on \
+ -timing -ol high -logic_opt on \
+ -o ${PROJECT}.ncd ${PROJECT}.ngd ${PROJECT}.pcf
+
+${PROJECT}_routed.ncd: ${PROJECT}.ncd
+ par -w -intstyle ise -ol high -t 1 ${PROJECT}.ncd ${PROJECT}_routed.ncd ${PROJECT}.pcf
+
+${PROJECT}_routed.bit: ${PROJECT}_routed.ncd
+ bitgen -f ${PROJECT}.ut ${PROJECT}_routed.ncd
+
+${PROJECT}_routed.bin: ${PROJECT}_routed.bit
+ promgen -w -spi -p bin -o ${PROJECT}_routed.bin -s 1024 -u 0 ${PROJECT}_routed.bit
+
+clean:
+ @rm -rf ${PROJECT}.{ngc,ngd,ncd,_routed.ncd,pcf,bit,_routed.bit}
+ $(MAKE) -C $(BOOTPATH)bootloader clean
@@ -0,0 +1,205 @@
+--
+-- System Clock generator for ZPUINO (papilio one)
+--
+-- Copyright 2010 Alvaro Lopes <alvieboy@alvie.com>
+--
+-- Version: 1.0
+--
+-- The FreeBSD license
+--
+-- Redistribution and use in source and binary forms, with or without
+-- modification, are permitted provided that the following conditions
+-- are met:
+--
+-- 1. Redistributions of source code must retain the above copyright
+-- notice, this list of conditions and the following disclaimer.
+-- 2. Redistributions in binary form must reproduce the above
+-- copyright notice, this list of conditions and the following
+-- disclaimer in the documentation and/or other materials
+-- provided with the distribution.
+--
+-- THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY
+-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
+-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+-- PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+-- ZPU PROJECT OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+-- INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+-- OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+-- HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+-- ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+--
+--
+
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_unsigned.all;
+use ieee.numeric_std.all;
+
+library UNISIM;
+use UNISIM.VCOMPONENTS.all;
+
+entity clkgen is
+ port (
+ clkin: in std_logic;
+ rstin: in std_logic;
+ clkout: out std_logic;
+ vgaclkout: out std_logic;
+ rstout: out std_logic
+ );
+end entity clkgen;
+
+architecture behave of clkgen is
+
+signal dcmlocked: std_logic;
+signal dcmclock: std_logic;
+
+signal rst1_q: std_logic;
+signal rst2_q: std_logic;
+signal clkout_i: std_logic;
+signal clkin_i: std_logic;
+signal clkin_i_2: std_logic;
+signal clkfb: std_logic;
+signal clk0: std_logic;
+
+signal vgaclk_0_b, vgaclk_fb, vgaclk_fx_b, vgaclk_in: std_logic;
+
+begin
+
+ clkout <= clkout_i;
+
+ rstout <= rst1_q;
+
+ process(dcmlocked, clkout_i, rstin)
+ begin
+ if dcmlocked='0' or rstin='1' then
+ rst1_q <= '1';
+ rst2_q <= '1';
+ else
+ if rising_edge(clkout_i) then
+ rst1_q <= rst2_q;
+ rst2_q <= '0';
+ end if;
+ end if;
+ end process;
+
+ -- Clock buffers
+
+ clkfx_inst: BUFG
+ port map (
+ I => dcmclock,
+ O => clkout_i
+ );
+
+ clkin_inst: IBUFG
+ port map (
+ I => clkin,
+ O => clkin_i
+ );
+
+ clkin2_inst: BUFG
+ port map (
+ I => clkin_i,
+ O => clkin_i_2
+ );
+
+ --clkfb_inst: BUFG
+ -- port map (
+ -- I=> clk0,
+ -- O=> clkfb
+ -- );
+
+
+DCM_inst : DCM
+ generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 8, -- Can be any integer from 1 to 32
+ CLKFX_MULTIPLY => 23, -- Can be any integer from 1 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => 31.25, -- Specify period of input clock
+ CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+ CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"C080", -- FACTORY JF Values
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+ STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ )
+ port map (
+ CLK0 => open,--clk0, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => open, -- 270 degree DCM CLK output
+ CLK2X => open, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => dcmclock, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => dcmlocked, -- DCM LOCK status output
+ PSDONE => open, -- Dynamic phase adjust done output
+ STATUS => open, -- 8-bit DCM status bits output
+ CLKFB => '0',--clkfb, -- DCM clock feedback
+ CLKIN => clkin_i, -- Clock input (from IBUFG, BUFG or DCM)
+ PSCLK => '0', -- Dynamic phase adjust clock input
+ PSEN => '0', -- Dynamic phase adjust enable input
+ PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
+ RST => '0' -- DCM asynchronous reset input
+ );
+
+ vgaclkfx_inst: BUFG
+ port map (
+ I => vgaclk_fx_b,
+ O => vgaclkout
+ );
+
+ --vgaclkfb_inst: BUFG
+ -- port map (
+ -- I=> vgaclk_0_b,
+ -- O=> vgaclk_fb
+ -- );
+
+
+ VGADCM_inst : DCM -- Generate 50Mhz
+ generic map (
+ CLKDV_DIVIDE => 2.0, -- Divide by: 1.5,2.0,2.5,3.0,3.5,4.0,4.5,5.0,5.5,6.0,6.5,7.0,7.5,8.0,9.0,10.0,11.0,12.0,13.0,14.0,15.0 or 16.0
+ CLKFX_DIVIDE => 16,--8, -- Can be any integer from 1 to 32
+ CLKFX_MULTIPLY => 25,--23, -- Can be any integer from 1 to 32
+ CLKIN_DIVIDE_BY_2 => FALSE, -- TRUE/FALSE to enable CLKIN divide by two feature
+ CLKIN_PERIOD => 31.25, -- Specify period of input clock
+ CLKOUT_PHASE_SHIFT => "NONE", -- Specify phase shift of NONE, FIXED or VARIABLE
+ CLK_FEEDBACK => "NONE", -- Specify clock feedback of NONE, 1X or 2X
+ DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS", -- SOURCE_SYNCHRONOUS, SYSTEM_SYNCHRONOUS or an integer from 0 to 15
+ DFS_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for frequency synthesis
+ DLL_FREQUENCY_MODE => "LOW", -- HIGH or LOW frequency mode for DLL
+ DUTY_CYCLE_CORRECTION => TRUE, -- Duty cycle correction, TRUE or FALSE
+ FACTORY_JF => X"C080", -- FACTORY JF Values
+ PHASE_SHIFT => 0, -- Amount of fixed phase shift from -255 to 255
+ STARTUP_WAIT => FALSE -- Delay configuration DONE until DCM LOCK, TRUE/FALSE
+ )
+ port map (
+ CLK0 => open,--vgaclk_0_b, -- 0 degree DCM CLK ouptput
+ CLK180 => open, -- 180 degree DCM CLK output
+ CLK270 => open, -- 270 degree DCM CLK output
+ CLK2X => open, -- 2X DCM CLK output
+ CLK2X180 => open, -- 2X, 180 degree DCM CLK out
+ CLK90 => open, -- 90 degree DCM CLK output
+ CLKDV => open, -- Divided DCM CLK out (CLKDV_DIVIDE)
+ CLKFX => vgaclk_fx_b, -- DCM CLK synthesis out (M/D)
+ CLKFX180 => open, -- 180 degree CLK synthesis out
+ LOCKED => open,--dcmlocked_b, -- DCM LOCK status output
+ PSDONE => open, -- Dynamic phase adjust done output
+ STATUS => open, -- 8-bit DCM status bits output
+ CLKFB => '0',--vgaclk_fb, -- DCM clock feedback
+ CLKIN => clkin_i_2, -- Clock input (from IBUFG, BUFG or DCM)
+ PSCLK => '0', -- Dynamic phase adjust clock input
+ PSEN => '0', -- Dynamic phase adjust enable input
+ PSINCDEC => '0', -- Dynamic phase adjust increment/decrement
+ RST => '0' -- DCM asynchronous reset input
+ );
+
+
+end behave;
@@ -0,0 +1,80 @@
+##################################################################################
+## papilio_one.ucf
+##
+## Author: Alvaro Lopes, Jack Gasset
+##
+## Contains assignment and iostandard information for
+## all used pins as well as timing and area constraints for
+## Papilio One Version 2.03 and greater that uses 32Mhz oscillator.
+##
+##################################################################################
+
+# Crystal Clock - use 32MHz onboard oscillator
+NET "clk" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.25ns ;
+#NET "clk" LOC = "P89" | IOSTANDARD = LVCMOS25 | PERIOD = 31.00ns ;
+
+# Wing1 Column A
+NET "WING_A<0>" LOC = "P18" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A0
+NET "WING_A<1>" LOC = "P23" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A1
+NET "WING_A<2>" LOC = "P26" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A2
+NET "WING_A<3>" LOC = "P33" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A3
+NET "WING_A<4>" LOC = "P35" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A4
+NET "WING_A<5>" LOC = "P40" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A5
+NET "WING_A<6>" LOC = "P53" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A6
+NET "WING_A<7>" LOC = "P57" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A7
+NET "WING_A<8>" LOC = "P60" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A8
+NET "WING_A<9>" LOC = "P62" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A9
+NET "WING_A<10>" LOC = "P65" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A10
+NET "WING_A<11>" LOC = "P67" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A11
+NET "WING_A<12>" LOC = "P70" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A12
+NET "WING_A<13>" LOC = "P79" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A13
+NET "WING_A<14>" LOC = "P84" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A14
+NET "WING_A<15>" LOC = "P86" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #A15
+
+# Wing1 Column B
+NET "WING_B<0>" LOC = "P85" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B0
+NET "WING_B<1>" LOC = "P83" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B1
+NET "WING_B<2>" LOC = "P78" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B2
+NET "WING_B<3>" LOC = "P71" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B3
+NET "WING_B<4>" LOC = "P68" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B4
+NET "WING_B<5>" LOC = "P66" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B5
+NET "WING_B<6>" LOC = "P63" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B6
+NET "WING_B<7>" LOC = "P61" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B7
+NET "WING_B<8>" LOC = "P58" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B8
+NET "WING_B<9>" LOC = "P54" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B9
+NET "WING_B<10>" LOC = "P41" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B10
+NET "WING_B<11>" LOC = "P36" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B11
+NET "WING_B<12>" LOC = "P34" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B12
+NET "WING_B<13>" LOC = "P32" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B13
+NET "WING_B<14>" LOC = "P25" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B14
+NET "WING_B<15>" LOC = "P22" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #B15
+
+# Wing2 Column A
+NET "WING_C<0>" LOC = "P91" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C0
+NET "WING_C<1>" LOC = "P92" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C1
+NET "WING_C<2>" LOC = "P94" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C2
+NET "WING_C<3>" LOC = "P95" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C3
+NET "WING_C<4>" LOC = "P98" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C4
+NET "WING_C<5>" LOC = "P2" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C5
+NET "WING_C<6>" LOC = "P3" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C6
+NET "WING_C<7>" LOC = "P4" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C7
+NET "WING_C<8>" LOC = "P5" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C8
+NET "WING_C<9>" LOC = "P9" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C9
+NET "WING_C<10>" LOC = "P10" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C10
+NET "WING_C<11>" LOC = "P11" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C11
+NET "WING_C<12>" LOC = "P12" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C12
+NET "WING_C<13>" LOC = "P15" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C13
+NET "WING_C<14>" LOC = "P16" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C14
+NET "WING_C<15>" LOC = "P17" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8 ; #C15
+
+## RS232
+NET "rxd" LOC = "P88" | IOSTANDARD = LVTTL ;
+NET "txd" LOC = "P90" | IOSTANDARD = LVTTL | DRIVE = 8 | SLEW = FAST ;
+
+## SPI flash
+NET "SPI_CS" LOC = "P24" | IOSTANDARD = LVCMOS33 | SLEW = SLOW | DRIVE = 8;
+NET "SPI_SCK" LOC = "P50" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "SPI_MISO" LOC = "P44" | IOSTANDARD = LVCMOS33 | SLEW = FAST | DRIVE = 8;
+NET "SPI_MOSI" LOC = "P27" | IOSTANDARD = LVCMOS33 ;
+
+#NET "vgaclk" TIG;
@@ -0,0 +1,21 @@
+-w
+-g DebugBitstream:No
+-g Binary:no
+-g CRC:Enable
+-g ConfigRate:25
+-g ProgPin:PullUp
+-g DonePin:PullUp
+-g TckPin:PullUp
+-g TdiPin:PullUp
+-g TdoPin:PullUp
+-g TmsPin:PullUp
+-g UnusedPin:PullDown
+-g UserID:0xFFFFFFFF
+-g StartUpClk:CClk
+-g DONE_cycle:4
+-g GTS_cycle:5
+-g GWE_cycle:6
+-g LCK_cycle:NoWait
+-g Security:None
+-g DonePipe:No
+-g DriveDone:No
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