Schematics & Layout TODO for revC3

[electroniceel]

A list of everything that should be decided and/or done for revC3 of the Glasgow hardware.

• Finish qualification tests for revC2 ( Qualification tests for revC2: pre INA233 #220 Qualification tests for revC2: post INA233 #221 )
• Fix I2C address clash between SMBus Alert Response Address and the DAC of port A
• Add note about the SMBus Alert Response Address to the schematics
• Fix internal I2C testpoint silkscreen labels ( Silkscreen labels swapped on SCL and SDA testpoints #250 )
• Review all changes added to revC2 between the version the prototypes were made from and merge of the branch
• Check all DFM issues @esden mentioned on stream while assembling the prototypes, are they already incorporated into revC2?
• Increase spacing between the mounting holes and the 3V3 flood fill on the internal power layer to prevent shorts when using serrated washers that could penetrate into the power layer
• Remove the port pinout marking on the top silkscreen ( Decide on port pinout marking on the top silkscreen #256 )
• Decide if to keep the CDSOD323-T36S TVS diodes or to change to another model with better availibility. CDSOD323-T36S stay, @esden said they are ok
• Decide if to add filter for Vsense ( Qualification tests for revC2: post INA233 #221 (comment) ) -> filter added in wip-revC3-hardware branch
• Schematics+BOM: adapt LEDs and LED-resistors ( revC LED type and resistor selection #259 )
• Fix reset button part number
• Decide on LVDS connector alignment hole size
• Decide on resistor pack footprint spacing
• Decide on improved decoupling for Vio_Aux (LVDS io rail). Currently it has 100nF, maybe go up to 1µF, also check trace width
• Add pin 1 marker or something similar to the LVDS header to make the pinout unambiguous

[electroniceel]

@esden While reviewing the changes to revC2 since the prototypes I found these issues:

1. LVDS alignment holes

You mentioned that the LVDS connector alignment holes are quite large and fitting loose. They haven't been changed yet and are still 1.1mm.

The samples you sent me measure alignment pins of 1.02 x 0.98 mm (cross-pattern).
The samples of Samtec FLE-122-01-G-DV-A I have measure a diameter of 0.65mm tough (round). Samtec suggests a hole of 0.76mm

So the alignment pins of Samtec and your parts have different sizes and I'd say the tolerances look reasonable in CAD, maybe JLCPCB added too much tolerance and drilled much larger in the prototypes?

So to me it looks ok, but please check and decide what to do.

2. Reset button part number

The reset button part no is currently "TC-1109DE-X-X". The Xes stand for ordering options for length and actuation force. Please review your ordering/manufacturing data and fill in the correct part nos.

[electroniceel]

@esden I found another thing that I'm not sure about:

The new footprint for the resistor packs (R_Array_Convex_4x0402) has unequal spacing between the pads. The inner pads have 0.2 mm space between them, the space between the outer and the inner pads is 0.15 mm. I thought the issue was increased likelihood of shorts between the outer and inner pads. So moving the outer pads a bit more outside is good, but you also increased them to the point that the spacing is reduced. I don't know if that will really help.

I suggest to move them out a little bit more so that they get the same space of 0.2 mm.

[electroniceel]

@smunaut I added a 4.7 µF cap to VIO_AUX now, because adding 1 µF would have meant adding a new BOM line, as we don't have 1 µF yet.

Unfortunately I couldn't get it as close to the FPGA as I wanted, but I didn't want to reroute bigger parts of the LVDS data lines this late in the design.

You can check it in the wip-revC3-hardware branch. Maybe you find a better spot to fit it or a second 100 nF nearer to the balls?

[smunaut]

4u7 is fine.

And location will have to do. That's a rather crowded area and the 'clkref' line splitting the line and also going across the whole reference plane for half the lvds lines is a bit of a bummer but with 6/6 rules there is only so much you can do :/

[electroniceel]

And location will have to do. That's a rather crowded area and the 'clkref' line splitting the line and also going across the whole reference plane for half the lvds lines is a bit of a bummer but with 6/6 rules there is only so much you can do :/

Yeah, the layout in that area is a bit crowded and convoluted, not optimized for EMI, but for keeping it at 4 layers. But I think it will still do fine as it is now.

Thanks for reviewing.

[esden]

Decide on LVDS connector alignment hole size

The part that we have sourced for the production of Glasgow revC3 has a smaller alignment pin than alternative models. This results in alignment wobble. The peg is rectangular with dimensions of 0.5mm x 0.7mm. The footprint recommendation by the connector manufacturer lists a hole of 1.1mm which is very large and does not result in a very good alignment. Based on reading of other manufacturer datasheets and recommendations, the rule of thumb seems to be 0.1mm larger hole than the alignment pin. Thus I would recommend to decrease the alignment hole size to 0.8mm.

Note: The size that @electroniceel recommended based on Samtec FLE-122-01-G-DV-A alignment pin size is 0.76mm that would also be an acceptable size. (I did random spot check measurements of the alignment pins in the 3k production batch of the connectors that I received and they all seem to be slightly smaller than the datasheet indicates at ~0.65mm)

[esden]

Fix reset button part number

Fixed in commit 8481072 the full part number is TC-1109DE-B-F.

[esden]

Decide on resistor pack footprint spacing

The current footprint is based on the Samsung recommended footprint dimensions.

https://www.samsungsem.com/resources/file/global/support/product_catalog/Chip_Resistor.pdf

The RP104P is the 0402x4 package type. The strange part about those dimensions is that the P1 distance indicates 0.55mm between the inner pad and the outer pad centers. Which results in a 0.15mm gap. The outer gap is not defined otherwise only the center gap which is 0.2mm. I guess we could move the pad out by 0.05mm so that the gaps are balanced.

On another note, looking through a bunch of datasheets the bigger outer pads recommendation is not the most common one. (if the manufacturer recommends any footprint at all) I tried to resolve it by going to JEDEC standard. But so far I was not able to locate that. Based on one stack overflow post it seems that there is no up to date standard for resistor array footprints at the moment. But it would be nice to at least find a copy of the IEC 60115-8 document.

I would for now leave the footprint as it is, as I know that it works in production. But if we can get some better industry recommendation we can consider updating it.

[esden]

Schematics+BOM: adapt LEDs and LED-resistors

Resolved with: bd0d5b1

[esden]

Decide on LVDS connector alignment hole size

Changed to 0.76mm diameter holes, and removed pad chamfers that are not needed any more in: ae8d47c

[attie]

@esden / @electroniceel - is this still in progress?

[esden]

I have also corrected the resistor pack footprint. That was the last remaining todo item. I have pushed all the remaining patches to the wip branch. I will open a PR as soon as I rebase it onto main.