- 1.Sequence Detector(10111) Using Moore State Machine
- 2.Block Diagram of a Sequence Detector
- 3.State Machine Diagram
- 4.Sequence Detector Schematic
- 5.Simulation Waveform
- 6.Synthesizing Verilog Code
- 7. Physical Design from Netlist to GDSII
- 8. Floorplan
- 9. Placement
- 10. CTS
- 11. Routing
- 12. Reports
- 13. References
- 14. Contributors
- 15. Acknowledgments
- 16. Contact Information
-Here I have implemented the Moore finite state machine sequence detector “10111”. Where the Moore finite state machine keeps detecting the digital input and the output of the fsm goes only high when the sequence is detected I.e., “10111”. In Moore fsm output depends only on the present state logic but not on the present input So in this -case we need the extra state to represent the ouput.Here when the sequence is detected at the input the output will represent as a 1. Whereas the next state logic is dependent upon the present input also on the present state. Here I used “10111” as a pattern when the input sequence is detected as a 10111 then the we see output as 1. -Here I performed a overlapping sequence to detect the pattern “10111”.
To clone the Repository and download the Netlist files for Simulation, enter the following commands in your terminal.
$ sudo apt install -y git
$ git clone https://github.com/Gogireddyravikiran/iiitb_sd_fsm
$ cd iiitb_sd_fsm
For Functional simulation run the following commands.
$ iverilog -o iiitb_sd_fsm iiitb_sd_fsm.v iiitb_sd_fsm_tb.v
To see the ouput waveform run the following commands
$ ./sd_fsm
$ gtkwave sd_fsm.vcd
This is a framework for RTL synthesis tools. It currently has extensive Verilog-2005 support and provides a basic set of synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining the existing passes (algorithms) using synthesis scripts and adding additional passes as needed by extending the yosys C++ code base.
Yosys is free software licensed under the ISC license (a GPL compatible license that is similar in terms to the MIT license or the 2-clause BSD license).
git clone https://github.com/YosysHQ/yosys.git
make
sudo make install make test
read_verilog iiitb_sd_fsm.v
# generic synthesis
synth -top iiitb_sd_fsm
# mapping to mycells.lib
dfflibmap -liberty /home/gogireddyravikiranreddy1/Desktop/iiitb_sd_fsm/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
abc -liberty /home/gogireddyravikiranreddy1/Desktop/iiitb_sd_fsm/lib/sky130_fd_sc_hd__tt_025C_1v80.lib
clean
flatten
# write synthesized design
write_verilog -noattr iiitb_sd_fsm_synth.v
Printing statistics.
=== iiitb_sd_fsm ===
Number of wires: 19
Number of wire bits: 19
Number of public wires: 10
Number of public wire bits: 10
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 16
sky130_fd_sc_hd__a21o_2 1
sky130_fd_sc_hd__a2bb2oi_2 1
sky130_fd_sc_hd__and2b_2 1
sky130_fd_sc_hd__and3b_2 1
sky130_fd_sc_hd__buf_1 1
sky130_fd_sc_hd__dfrtp_2 3
sky130_fd_sc_hd__inv_2 3
sky130_fd_sc_hd__nand2_2 1
sky130_fd_sc_hd__nand3b_2 1
sky130_fd_sc_hd__nor2_2 1
sky130_fd_sc_hd__o211a_2 1
sky130_fd_sc_hd__o21ba_2 1
Now the synthesized netlist is written in "iiitb_sd_fsm_synth.v" file.
GLS is generating the simulation output by running test bench with netlist file generated from synthesis as design under test. Netlist is logically same as RTL code, therefore, same test bench can be used for it.We perform this to verify logical correctness of the design after synthesizing it. Also ensuring the timing of the design is met.
iverilog -DFUNCTIONAL -DUNIT_DELAY=#1 verilog_model/primitives.v verilog_model/sky130_fd_sc_hd.v iiitb_sd_fsm_synth.v iiitb_sd_fsm_tb.v
./a.out --> For Generating the vcd file.
gtkwave sd_fsm.vcd
The gtkwave output for the netlist should match the output waveform for the RTL design file. As netlist and design code have same set of inputs and outputs, we can use the same testbench and compare the waveforms.
I observed that Pre Level Simulation and Post Level Simulation Waveforms are matched.
Physical design is process of transforming netlist into layout which is manufacture-able [GDS]. Physical design process is often referred as PnR (Place and Route). Main steps in physical design are placement of all logical cells, clock tree synthesis & routing. During this process of physical design timing, power, design & technology constraints have to be met. Further design might require being optimized w.r.t power, performance and area.
Below are the stages and the respective tools that are called by openlane for the functionalities as described:
- Synthesis
- Floorplanning
- Placement
- Clock Tree Synthesis (CTS)
- Synthesizing the clock tree (TritonCTS).
- Routing
- Performing global routing to generate a guide file for the detailed router (FastRoute).
- Performing detailed routing (TritonRoute)
- GDSII Generation
- Streaming out the final GDSII layout file from the routed def (Magic).
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen, CVC, SPEF-Extractor, CU-GR, Klayout and a number of custom scripts for design exploration and optimization. The flow performs full ASIC implementation steps from RTL all the way down to GDSII.
$ apt install -y build-essential python3 python3-venv python3-pip
Docker installation process: https://docs.docker.com/engine/install/ubuntu/
goto home directory->
$ git clone https://github.com/The-OpenROAD-Project/OpenLane.git
$ cd OpenLane/
$ sudo make
To test the open lane
$ sudo make test
It takes approximate time of 5min to complete. After 43 steps, if it ended with saying Basic test passed then open lane installed succesfully.
-
Magic is a venerable VLSI layout tool, written in the 1980's at Berkeley by John Ousterhout, now famous primarily for writing the scripting interpreter language Tcl. Due largely in part to its liberal Berkeley open-source license, magic has remained popular with universities and small companies. The open-source license has allowed VLSI engineers with a bent toward programming to implement clever ideas and help magic stay abreast of fabrication technology. However, it is the well thought-out core algorithms which lend to magic the greatest part of its popularity. Magic is widely cited as being the easiest tool to use for circuit layout, even for people who ultimately rely on commercial tools for their product design flow.
-More about magic at http://opencircuitdesign.com/magic/index.html
Run following commands one by one to fulfill the system requirement.
$ sudo apt-get install m4
$ sudo apt-get install tcsh
$ sudo apt-get install csh
$ sudo apt-get install libx11-dev
$ sudo apt-get install tcl-dev tk-dev
$ sudo apt-get install libcairo2-dev
$ sudo apt-get install mesa-common-dev libglu1-mesa-dev
$ sudo apt-get install libncurses-dev
To install magic goto home directory
$ git clone https://github.com/RTimothyEdwards/magic
$ cd magic/
$ ./configure
$ sudo make
$ sudo make install
type magic terminal to check whether it installed succesfully or not. type exit to exit magic.
Generating Layout without including sky130_vsdinv cell
Open terminal in home directory
$ cd OpenLane/
$ cd designs/
$ mkdir iiitb_pwm_gen
$ cd iiitb_pwm_gen/
$ wget https://raw.githubusercontent.com/Gogireddyravikiran/iiitb_sd_fsm/main/config.json
$ mkdir src
$ cd src/
$ wget https://raw.githubusercontent.com/Gogireddyravikiran/iiitb_sd_fsm/main/iiitb_sd_fsm.v
$ cd ../../../
$ sudo make mount
$ ./flow.tcl -design iiitb_sd_fsm
To see the layout we use a tool called magic which we installed earlier.
open terminal in home directory
$ cd OpenLane/designs/iiitb_sd_fsm/run
$ ls
example:
$ cd RUN_2022.08.21_10.59.29
run following instruction
$ cd results/final/def
update the highlited text with appropriate path
$ magic -T /home/ravi/Desktop/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech lef read ../../../tmp/merged.lef def read iiitb_sd_fsm.def &
copy the sky130A.tech to vsdcelldesign directory and type the following command to see the inverter layout in magic tool.
magic -T sky130A.tech sky130A_inv.mag &
Generating the sky130_vsdinv.lef file
In tkcon terminal type the following command
lef write sky130_vsdinv.lef
Move the sky130_fd_sc_hd__fast.lib,sky130_fd_sc_hd__slow.lib,sky130_fd_sc_hd__typical.lib,sky130_vsdinv.lef files to your design src folder.
Invoking openlane by following command.
sudo make mount
Run the following commands.
$ ./flow.tcl -interactive
% package require openlane 0.9
% prep -design iiitb_sd_fsm
These commands are used for reading the sky130_vsdinv.lef file
% set lefs [glob $::env(DESIGN_DIR)/src/*.lef]
% add_lefs -src $lefs
** Reading the design
**Include the following the commands in the flow **
run_synthesis
Printing Statistics
run_floorplan
Type the following command to run placement
run_placement
Type the following command to run placement
run_cts
run_routing
In tkcon terminal type the following command to know whether the cell is present or not
One sky130_vsdinv cell is present in the design
sky130_vsdinv _14_
Identifying the sky130_vsdinv cell
Expanded version of sky130_vsdinv cell
power = 2.25uwatts
Area of the design = 1952.054um^2
$ sudo make mount
$ sta
% read_liberty -min /home/ravi/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib
% read_liberty -max /home/ravi/Desktop/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v56.lib
% read_verilog /home/ravi/Desktop/OpenLane/pdks/sky130A/iiitb_pwm_gen.v
% link_design iiitb_pwm_gen
% read_sdc /home/ravi/Desktop/OpenLane/pdks/sky130A/iiitb_pwm_gen.sdc
% set_propagated_clock [all_clocks]
% report_checks
% report_checks -from _37_(FlipFlop) -to _27_(FlipFlop)
performance = 1.4953GHZ
[1] VLSI System Design: https://www.vlsisystemdesign.com/
[2] SkyWater SKY130 PDK: https://skywater-pdk.readthedocs.io/en/main/contents/libraries/foundry-provided.html
[3] RTL Design using Verilog with Sky130 Technology: https://www.vsdiat.com/dashboard
[4] Openlane - SKY130: https://github.com/The-OpenROAD-Project/OpenLane
[5] Magic Installation: https://github.com/RTimothyEdwards/magic
- GogiReddy Ravi Kiran Reddy
- Kunal Ghosh
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd.
- GogiReddy Ravi Kiran Reddy, Postgraduate Student, International Institute of Information Technology, Bangalore.
- Email: gogireddyravikiranreddy1@gmail.com
- Kunal Ghosh, Director, VSD Corp. Pvt. Ltd. kunalghosh@gmail.com