I was looking for a quick implementation of RC4 and I couldn't find one, so I wrote one based on the wikipedia example.
It's quite easy to use:
1) First, issue rst 2) Load the password byte-by-byte into the password\_input port. The lenght of the password is KEY\_SIZE 3) Issue 768 clocks to perform key expansion 4) Wait 1536 clocks while the module discards the first 1536 weak bytes of the stream (as per rfc4345.txt). 5) Now you should start receiving the pseudo-random stream via the output bus, one byte every clock. The output\_ready signal signals when a valid byte is present at the output K.
To encrypt or decrypt using RC4 you simply xor your data with the output stream.
#How to test
The testbench and makefile work using icarus verilog and you can peer into rc4_tb.v to see an example implementation. After installing icarus verilog in your path, just issue:
And you should see the output of the simulation.
RC4-PRBS Copyright (c) 2013, Groundworks Technologies, All rights reserved.
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