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@HackerFoo
HackerFoo committed Jul 2, 2019
1 parent b3d433a commit 9e4aff4
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Showing 6 changed files with 135 additions and 7 deletions.
23 changes: 23 additions & 0 deletions xc7/primitives/idelaye2/idelaye2.pb_type.xml
View file
@@ -1,4 +1,27 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="IDELAYE2" num_pb="1">
<input name="C" num_pins="1"/>
<input name="CE" num_pins="1"/>
<input name="CINVCTRL" num_pins="1"/>
<input name="CNTVALUEIN0" num_pins="1"/>
<input name="CNTVALUEIN1" num_pins="1"/>
<input name="CNTVALUEIN2" num_pins="1"/>
<input name="CNTVALUEIN3" num_pins="1"/>
<input name="CNTVALUEIN4" num_pins="1"/>
<output name="CNTVALUEOUT0" num_pins="1"/>
<output name="CNTVALUEOUT1" num_pins="1"/>
<output name="CNTVALUEOUT2" num_pins="1"/>
<output name="CNTVALUEOUT3" num_pins="1"/>
<output name="CNTVALUEOUT4" num_pins="1"/>
<input name="DATAIN" num_pins="1"/>
<output name="DATAOUT" num_pins="1"/>
<input name="IDATAIN" num_pins="1"/>
<input name="IFDLY0" num_pins="1"/>
<input name="IFDLY1" num_pins="1"/>
<input name="IFDLY2" num_pins="1"/>
<input name="INC" num_pins="1"/>
<input name="LD" num_pins="1"/>
<input name="LDPIPEEN" num_pins="1"/>
<input name="REGRST" num_pins="1"/>
<!-- TODO -->
</pb_type>
30 changes: 30 additions & 0 deletions xc7/primitives/ilogice3/ilogice3.pb_type.xml
View file
@@ -1,4 +1,34 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="ILOGICE3" num_pb="1">
<input name="BITSLIP" num_pins="1"/>
<input name="CE1" num_pins="1"/>
<input name="CE2" num_pins="1"/>
<input name="CLK" num_pins="1"/>
<input name="CLKB" num_pins="1"/>
<input name="CLKDIV" num_pins="1"/>
<input name="CLKDIVP" num_pins="1"/>
<input name="D" num_pins="1"/>
<input name="DDLY" num_pins="1"/>
<input name="DYNCLKDIVPSEL" num_pins="1"/>
<input name="DYNCLKDIVSEL" num_pins="1"/>
<input name="DYNCLKSEL" num_pins="1"/>
<output name="O" num_pins="1"/>
<input name="OCLK" num_pins="1"/>
<input name="OCLKB" num_pins="1"/>
<input name="OFB" num_pins="1"/>
<output name="Q1" num_pins="1"/>
<output name="Q2" num_pins="1"/>
<output name="Q3" num_pins="1"/>
<output name="Q4" num_pins="1"/>
<output name="Q5" num_pins="1"/>
<output name="Q6" num_pins="1"/>
<output name="Q7" num_pins="1"/>
<output name="Q8" num_pins="1"/>
<input name="SHIFTIN1" num_pins="1"/>
<input name="SHIFTIN2" num_pins="1"/>
<output name="SHIFTOUT1" num_pins="1"/>
<output name="SHIFTOUT2" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="TFB" num_pins="1"/>
<!-- TODO -->
</pb_type>
13 changes: 13 additions & 0 deletions xc7/primitives/iob33m/iob33m.pb_type.xml
View file
@@ -1,4 +1,17 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="IOB33M" num_pb="1">
<input name="DIFFI_IN" num_pins="1"/>
<output name="DIFFO_OUT" num_pins="1"/>
<output name="I" num_pins="1"/>
<input name="IBUFDISABLE" num_pins="1"/>
<input name="INTERMDISABLE" num_pins="1"/>
<input name="KEEPER_INT_EN" num_pins="1"/>
<input name="O" num_pins="1"/>
<output name="O_OUT" num_pins="1"/>
<output name="PADOUT" num_pins="1"/>
<input name="PD_INT_EN" num_pins="1"/>
<input name="PU_INT_EN" num_pins="1"/>
<input name="T" num_pins="1"/>
<output name="T_OUT" num_pins="1"/>
<!-- TODO -->
</pb_type>
17 changes: 17 additions & 0 deletions xc7/primitives/iob33s/iob33s.pb_type.xml
View file
@@ -1,4 +1,21 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="IOB33S" num_pb="1">
<input name="DIFFI_IN" num_pins="1"/>
<input name="DIFFO_IN" num_pins="1"/>
<output name="DIFFO_OUT" num_pins="1"/>
<input name="DIFF_TERM_INT_EN" num_pins="1"/>
<output name="I" num_pins="1"/>
<input name="IBUFDISABLE" num_pins="1"/>
<input name="INTERMDISABLE" num_pins="1"/>
<input name="KEEPER_INT_EN" num_pins="1"/>
<input name="O" num_pins="1"/>
<input name="O_IN" num_pins="1"/>
<output name="O_OUT" num_pins="1"/>
<output name="PADOUT" num_pins="1"/>
<input name="PD_INT_EN" num_pins="1"/>
<input name="PU_INT_EN" num_pins="1"/>
<input name="T" num_pins="1"/>
<input name="T_IN" num_pins="1"/>
<output name="T_OUT" num_pins="1"/>
<!-- TODO -->
</pb_type>
32 changes: 32 additions & 0 deletions xc7/primitives/ologice3/ologice3.pb_type.xml
View file
@@ -1,4 +1,36 @@
<!-- set: ai sw=1 ts=1 sta et -->
<pb_type name="OLOGICE3" num_pb="1">
<input name="CLK" num_pins="1"/>
<input name="CLKB" num_pins="1"/>
<input name="CLKDIV" num_pins="1"/>
<input name="CLKDIVB" num_pins="1"/>
<input name="CLKDIVF" num_pins="1"/>
<input name="CLKDIVFB" num_pins="1"/>
<input name="D1" num_pins="1"/>
<input name="D2" num_pins="1"/>
<input name="D3" num_pins="1"/>
<input name="D4" num_pins="1"/>
<input name="D5" num_pins="1"/>
<input name="D6" num_pins="1"/>
<input name="D7" num_pins="1"/>
<input name="D8" num_pins="1"/>
<output name="IOCLKGLITCH" num_pins="1"/>
<input name="OCE" num_pins="1"/>
<output name="OFB" num_pins="1"/>
<output name="OQ" num_pins="1"/>
<output name="SHIFTOUT1" num_pins="1"/>
<output name="SHIFTOUT2" num_pins="1"/>
<input name="SR" num_pins="1"/>
<input name="T1" num_pins="1"/>
<input name="T2" num_pins="1"/>
<input name="T3" num_pins="1"/>
<input name="T4" num_pins="1"/>
<input name="TBYTEIN" num_pins="1"/>
<output name="TBYTEOUT" num_pins="1"/>
<input name="TCE" num_pins="1"/>
<output name="TFB" num_pins="1"/>
<output name="TQ" num_pins="1"/>
<input name="SHIFTIN1" num_pins="1"/>
<input name="SHIFTIN2" num_pins="1"/>
<!-- TODO -->
</pb_type>
27 changes: 20 additions & 7 deletions xc7/utils/prjxray_tile_import.py
View file
Expand Up @@ -462,23 +462,30 @@ def import_tile(db, args):

site_type = db.get_site_type(site.type)

if args.generate_missing_pins:
print("\nsite.type: {}".format(site.type))

interconnect_xml.append(ET.Comment(" Tile->Site "))
for site_pin in sorted(site.site_pins,
key=lambda site_pin: site_pin.name):
if site_pin.wire is None:
continue

port = find_port(site_pin.name, site_type_ports[site_instance])
site_type_pin = site_type.get_site_pin(site_pin.name)

if port is None:
print(
"*** WARNING *** Didn't find port for name {} for site type {}"
.format(site_pin.name, site.type),
file=sys.stderr
)
if args.generate_missing_pins:
direction = "input" if site_type_pin.direction == prjxray.site_type.SitePinDirection.IN else "output"
print("<{} name=\"{}\" num_pins=\"1\"/>".format(direction, site_pin.name))
else:
print(
"*** WARNING *** Didn't find port for name {} for site type {}"
.format(site_pin.name, site.type),
file=sys.stderr
)
continue

site_type_pin = site_type.get_site_pin(site_pin.name)

if site_type_pin.direction == prjxray.site_type.SitePinDirection.IN:
add_direct(
interconnect_xml,
Expand Down Expand Up @@ -769,6 +776,12 @@ def main():
"Typically a tile can treat the sites within the tile as independent. For tiles where this is not true, fused sites only imports 1 primatative for the entire tile, which should be named the same as the tile type."
)

parser.add_argument(
'--generate_missing_pins',
action='store_true',
help="Print missing pin warnings as XML."
)

args = parser.parse_args()

db = prjxray.db.Database(os.path.join(prjxray_db, args.part))
Expand Down

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