{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":722016452,"defaultBranch":"main","name":"riscv-isa-manual","ownerLogin":"HepoH3","currentUserCanPush":false,"isFork":true,"isEmpty":false,"createdAt":"2023-11-22T09:03:49.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/17159587?v=4","public":true,"private":false,"isOrgOwned":false},"refInfo":{"name":"","listCacheKey":"v0:1700644297.772275","currentOid":""},"activityList":{"items":[{"before":"b36aecfd9930a800f4000f79803be9e6d52ab77e","after":"25e8dbc5bbc8ff2ce7f1aa7c83f909f59c60cc87","ref":"refs/heads/patch-1","pushedAt":"2023-11-22T09:46:52.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"HepoH3","name":"Andrei Solodovnikov","path":"/HepoH3","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/17159587?s=80&v=4"},"commit":{"message":"Fix MODE field description of mtvec register\n\nFix MODE field description in the mtvec register\r\n\r\nIn Section 1.6, \"Exceptions, Traps, and Interrupts\" of the unprivileged\r\nspecification, a distinction is made between exceptions and interrupts.\r\n\r\nTable 13 in the privileged specification uses the term \"exceptions\" as a\r\ncatch-all expression, encompassing both \"exceptions and interrupts\"\r\nwhich may not be immediately apparent.\r\n\r\nReading \"exceptions\" merely as \"exceptions\" initially led me to believe\r\nthat the 0th bit is used to control exception handling behavior, while\r\nthe 1st bit is used to control interrupt handling behavior.\r\n\r\n\n\nSigned-off-by: Andrei Solodovnikov <VoultBoy@yandex.ru>","shortMessageHtmlLink":"Fix MODE field description of mtvec register"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAADtQ2LnAA","startCursor":null,"endCursor":null}},"title":"Activity · HepoH3/riscv-isa-manual"}