verilator 3.833 #12798

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@saperant

Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.

@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial simulators. It compiles synthesizable Verilog (not test-bench code!), plus some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It is designed for large projects where fast simulation performance is of primary concern, and is especially well suited to generate executable models of CPUs for embedded software design teams.
43a59ee
@jacknagel jacknagel commented on an outdated diff Jun 12, 2012
Library/Formula/verilator.rb
@@ -0,0 +1,22 @@
+require 'formula'
+
+class Verilator < Formula
+ homepage 'http://www.veripool.org/wiki/verilator'
+ url 'http://www.veripool.org/ftp/verilator-3.833.tgz'
+ sha1 '4ca58d609371b0a6309c5564a5e8ba6857aa15db'
+
+ skip_clean 'bin' # Allows perl scripts to keep their executable flag
+
+ def install
+ args = ["--prefix=#{prefix}"]
+
+ ohai "#{bin}"
+ system "./configure", *args
@jacknagel
jacknagel added a line comment Jun 12, 2012

Don't need an args array here, just pass --prefix directly. And remove the ohai line.

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@saperant

Those were left after debugging. Sorry. Now they are fixed. Anything else?

@adamv adamv added a commit that closed this pull request Jul 23, 2012
@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
6445e29
@adamv adamv closed this in 6445e29 Jul 23, 2012
@hmac hmac added a commit that referenced this pull request Aug 8, 2012
@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
3fc77d2
@fgeller fgeller added a commit to fgeller/homebrew that referenced this pull request Aug 22, 2012
@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
5c1dbd2
@Nexuapex Nexuapex pushed a commit that referenced this pull request Aug 29, 2012
@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
8829933
@Sharpie Sharpie pushed a commit to Sharpie/homebrew that referenced this pull request Sep 12, 2012
@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
cff654a
@snakeyroc3 snakeyroc3 pushed a commit to snakeyroc3/homebrew that referenced this pull request Dec 17, 2012
@saperant saperant verilator 3.833
Verilator is the fastest free Verilog HDL simulator, and beats most commercial
simulators. It compiles synthesizable Verilog (not test-bench code!), plus
some PSL, SystemVerilog and Synthesis assertions into C++ or SystemC code. It
is designed for large projects where fast simulation performance is of primary
concern, and is especially well suited to generate executable models of CPUs
for embedded software design teams.

Closes #12798.

Signed-off-by: Adam Vandenberg <flangy@gmail.com>
65d6009
@xu-cheng xu-cheng locked and limited conversation to collaborators Feb 16, 2016
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