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ar100-boot
.gitignore
Makefile
README
ar100-info.ld
clock.h
cpu.h
dram.h
dram_sun6i.c
gpio.c
gpio.h
instruction_tests.h
io.h
main.c
platform.h
spr-defs.h
spr.h
start.S
timer.h
type.h
uart.c
uart.h

README

Introduction
============
A small OpenRISC 1000 baremetal application to be run on the Allwinner A31
and Allwinner H3 SoCs to gain some information about the AR100 core (an or1k
implementation) present in that SoCs.

Usage
=====
The application is intended to be loaded into SRAM from the FEL mode with the
'sunxi-fel' tool available from https://github.com/linux-sunxi/sunxi-tools.

Embedded in the OpenRISC 1000 binary is a small ARM "boot loader",
which is intended to be run first, it's sole purpose is to deassert the
reset line to the AR100 core.

To build the ARM "boot loader":
$ make -C ar100-boot/

To build, load and run the OpenRISC baremetal application:
$ make load

A note about the SRAM and exception vectors
===========================================
AR100 uses an SRAM located at addresses 0x40000 - 0x54000
(as seen from the ARM cores) as instruction and data memory.
The OpenRISC 1000 architecture defines a generous space (0x100 bytes) for each
exception vector i.e.

0x100 vector0
...
0x200 vector1
...
0x300 vector3
...
etc

This is rather memory consuming, especially if you are using an internal
SRAM as the main memory.
To avoid this, the Allwinner engineers have added address decode logic to
the lower addresses of the SRAM, so that only the first word of each 0x100
multiple is actually routed to the memory.
The second word of each 0x100 multiple reads out as 0x15000000 = l.nop and the
rest as 0x00000000.
i.e. all exception vectors have to be implemented like this:

l.j exception_handler
 l.nop

The actual contiguous SRAM memory starts at address 0x44000. The size of this
contiguous SRAM memory is 64 KiB in Allwinner A31 and 32 KiB in Allwinner H3.

Results (application output)
============================
OpenRISC-1200 (rev 1)
D-Cache: no
I-Cache: 4096 bytes, 16 bytes/line, 1 way(s)
DMMU: no
IMMU: no
MAC unit: yes
Debug unit: yes
Performance counters: no
Power management: yes
Interrupt controller: yes
Timer: yes
Custom unit(s): no
ORBIS32: yes
ORBIS64: no
ORFPX32: no
ORFPX64: no
Test support for l.addc...yes
Test support for l.cmov...yes
Test support for l.cust1...no
Test support for l.cust2...no
Test support for l.cust3...no
Test support for l.cust4...no
Test support for l.cust5...no
Test support for l.cust6...no
Test support for l.cust7...no
Test support for l.cust8...no
Test support for l.div...yes
Test support for l.divu...yes
Test support for l.extbs...yes
Test support for l.extbz...yes
Test support for l.exths...yes
Test support for l.exthz...yes
Test support for l.extws...yes
Test support for l.extwz...yes
Test support for l.ff1...yes
Test support for l.fl1...yes
Test support for l.lws...no
Test support for l.mac...yes
Test support for l.maci...yes
Test support for l.macrc...yes
Test support for l.mul...yes
Test support for l.muli...yes
Test support for l.mulu...yes
Test support for l.ror...yes
Test support for l.rori...yes
Init DRAM...done
Test DRAM read/write...OK
Test timer functionality...OK
Set clock source to LOSC...done
Test CLK freq...33 KHz
Set clock source to HOSC (POSTDIV=0, DIV=0)...done
Test CLK freq...24 MHz
Set clock source to HOSC (POSTDIV=0, DIV=1)...done
Test CLK freq...12 MHz
Set clock source to HOSC (POSTDIV=1, DIV=1)...done
Test CLK freq...12 MHz
Setup PLL6 (M=1, K=1, N=24)...done
Set clock source to PLL6 (POSTDIV=1, DIV=0)...done
Test CLK freq...300 MHz
Set clock source to PLL6 (POSTDIV=2, DIV=0)...done
Test CLK freq...200 MHz
Set clock source to PLL6 (POSTDIV=2, DIV=1)...done
Test CLK freq...100 MHz
Setup PLL6 (M=2, K=1, N=24)...done
Test CLK freq...100 MHz
Setup PLL6 (M=1, K=2, N=24)...done
Test CLK freq...150 MHz
Setup PLL6 (M=1, K=1, N=12)...done
Test CLK freq...52 MHz
Restore clock config to original state...done
All tests completed!
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