From 88bb037bf5088ec41180122aa777de6005d1bab6 Mon Sep 17 00:00:00 2001 From: gitlab-runner Date: Wed, 14 Apr 2021 10:25:38 -0500 Subject: [PATCH] Upload TARGET_CY8CPROTO-062-4343W 2.1.0.21729 --- .cyignore | 9 + .../GeneratedSource/cycfg.c | 2 +- .../GeneratedSource/cycfg.h | 3 +- .../GeneratedSource/cycfg.timestamp | 2 +- .../GeneratedSource/cycfg_capsense.c | 2 +- .../GeneratedSource/cycfg_capsense.h | 2 +- .../GeneratedSource/cycfg_clocks.c | 2 +- .../GeneratedSource/cycfg_clocks.h | 6 +- .../GeneratedSource/cycfg_connectivity_bt.c | 30 + .../GeneratedSource/cycfg_connectivity_bt.h | 54 ++ .../GeneratedSource/cycfg_notices.h | 2 +- .../GeneratedSource/cycfg_peripherals.c | 2 +- .../GeneratedSource/cycfg_peripherals.h | 2 +- .../GeneratedSource/cycfg_pins.c | 2 +- .../GeneratedSource/cycfg_pins.h | 130 ++- .../GeneratedSource/cycfg_routing.c | 2 +- .../GeneratedSource/cycfg_routing.h | 2 +- .../GeneratedSource/cycfg_system.c | 2 +- .../GeneratedSource/cycfg_system.h | 2 +- COMPONENT_BSP_DESIGN_MODUS/design.modus | 22 +- CY8CPROTO-062-4343W.mk | 12 +- README.md | 15 +- RELEASE.md | 19 +- bluetooth/cybsp_bt_config.c | 77 ++ bluetooth/cybsp_bt_config.h | 69 ++ cybsp.c | 105 ++- cybsp.h | 74 +- cybsp_doc.h | 838 ++++++++++++++++++ cybsp_types.h | 801 +---------------- docs/html/group__group__bsp__bt.html | 240 +++++ docs/html/group__group__bsp__bt.js | 9 + ...os.html => group__group__bsp__errors.html} | 7 +- docs/html/group__group__bsp__errors.js | 4 + docs/html/group__group__bsp__functions.html | 3 +- docs/html/group__group__bsp__macros.js | 4 - docs/html/group__group__bsp__pin__state.html | 3 +- docs/html/group__group__bsp__pins.html | 15 +- docs/html/group__group__bsp__pins.js | 3 - .../group__group__bsp__pins__arduino.html | 106 --- docs/html/group__group__bsp__pins__btn.html | 1 + .../group__group__bsp__pins__capsense.html | 5 + .../html/group__group__bsp__pins__capsense.js | 3 +- docs/html/group__group__bsp__pins__comm.html | 1 + docs/html/group__group__bsp__pins__j2.html | 106 --- docs/html/group__group__bsp__pins__j6.html | 106 --- docs/html/group__group__bsp__pins__led.html | 1 + docs/html/group__group__bsp__pins__wco.html | 1 + docs/html/index.html | 7 +- docs/html/md_bsp_settings.html | 2 +- ... => md_source_bsps_mt_bsp_user_guide.html} | 2 +- docs/html/menudata.js | 2 +- docs/html/modules.html | 22 +- docs/html/modules.js | 7 +- docs/html/navtreedata.js | 4 +- docs/html/navtreeindex0.js | 165 ++-- docs/html/search/all_0.js | 3 +- docs/html/search/all_1.js | 78 +- docs/html/search/all_2.js | 71 +- docs/html/search/all_4.js | 3 +- docs/html/search/all_5.js | 2 +- docs/html/search/all_6.js | 5 +- docs/html/search/all_7.js | 4 +- docs/html/search/all_8.js | 4 - docs/html/search/groups_0.js | 3 +- docs/html/search/groups_1.js | 3 +- docs/html/search/groups_2.js | 3 +- docs/html/search/groups_4.js | 3 +- docs/html/search/groups_5.js | 3 +- docs/html/search/groups_6.js | 2 +- docs/html/search/groups_7.html | 30 - docs/html/search/groups_7.js | 5 - docs/html/search/groups_8.html | 30 - docs/html/search/groups_8.js | 4 - docs/html/search/pages_1.js | 2 +- docs/html/search/pages_2.js | 2 +- docs/html/search/searchdata.js | 17 +- .../search/{all_8.html => variables_0.html} | 2 +- docs/html/search/variables_0.js | 4 + locate_recipe.mk | 2 +- version.xml | 2 +- 80 files changed, 1899 insertions(+), 1507 deletions(-) create mode 100644 .cyignore mode change 100755 => 100644 COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp create mode 100644 COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c create mode 100644 COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h create mode 100644 bluetooth/cybsp_bt_config.c create mode 100644 bluetooth/cybsp_bt_config.h create mode 100644 cybsp_doc.h create mode 100644 docs/html/group__group__bsp__bt.html create mode 100644 docs/html/group__group__bsp__bt.js rename docs/html/{group__group__bsp__macros.html => group__group__bsp__errors.html} (95%) create mode 100644 docs/html/group__group__bsp__errors.js delete mode 100644 docs/html/group__group__bsp__macros.js delete mode 100644 docs/html/group__group__bsp__pins__arduino.html delete mode 100644 docs/html/group__group__bsp__pins__j2.html delete mode 100644 docs/html/group__group__bsp__pins__j6.html rename docs/html/{md_bsp_boards_mt_bsp_user_guide.html => md_source_bsps_mt_bsp_user_guide.html} (98%) delete mode 100644 docs/html/search/all_8.js delete mode 100644 docs/html/search/groups_7.html delete mode 100644 docs/html/search/groups_7.js delete mode 100644 docs/html/search/groups_8.html delete mode 100644 docs/html/search/groups_8.js rename docs/html/search/{all_8.html => variables_0.html} (95%) create mode 100644 docs/html/search/variables_0.js diff --git a/.cyignore b/.cyignore new file mode 100644 index 0000000..3091af8 --- /dev/null +++ b/.cyignore @@ -0,0 +1,9 @@ +docs + +# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 2) +$(SEARCH_wifi-host-driver)/WiFi_Host_Driver/resources/nvram_deprecated/ +$(SEARCH_bluetooth-freertos)/firmware/firmware_deprecated/ + +# Exclude old firmware resources that were not flexible enough for custom BSPs (Flow version 1) +../wifi-host-driver/WiFi_Host_Driver/resources/nvram_deprecated/ +../bluetooth-freertos/firmware/firmware_deprecated/ diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c index bb093b6..3149a70 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.c @@ -4,7 +4,7 @@ * Description: * Wrapper function to initialize all generated code. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h index 172c277..1705a37 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.h @@ -4,7 +4,7 @@ * Description: * Simple wrapper header containing all generated files. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 @@ -35,6 +35,7 @@ extern "C" { #include "cycfg_notices.h" #include "cycfg_system.h" +#include "cycfg_connectivity_bt.h" #include "cycfg_clocks.h" #include "cycfg_routing.h" #include "cycfg_peripherals.h" diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp old mode 100755 new mode 100644 index 97baf87..52d9c5b --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg.timestamp @@ -4,7 +4,7 @@ * Description: * Sentinel file for determining if generated source is up to date. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c index 0296d57..a338079 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.c @@ -5,7 +5,7 @@ * Description: * CapSense Middleware configuration * This file should not be modified. It was automatically generated by -* CapSense Configurator 3.10.0.3166 +* CapSense Configurator 3.10.0.3158 * ******************************************************************************** * Copyright 2020 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h index 9204a5a..c2fb8d3 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_capsense.h @@ -5,7 +5,7 @@ * Description: * CapSense Middleware configuration * This file should not be modified. It was automatically generated by -* CapSense Configurator 3.10.0.3166 +* CapSense Configurator 3.10.0.3158 * ******************************************************************************** * Copyright 2020 Cypress Semiconductor Corporation diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c index db2b311..9a168dd 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.c @@ -4,7 +4,7 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h index deeb642..ae3f05e 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_clocks.h @@ -4,7 +4,7 @@ * Description: * Clock configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 @@ -40,11 +40,15 @@ extern "C" { #endif #define CYBSP_CSD_CLK_DIV_ENABLED 1U +#define CYBSP_CS_CLK_DIV_ENABLED CYBSP_CSD_CLK_DIV_ENABLED #define CYBSP_CSD_CLK_DIV_HW CY_SYSCLK_DIV_8_BIT +#define CYBSP_CS_CLK_DIV_HW CYBSP_CSD_CLK_DIV_HW #define CYBSP_CSD_CLK_DIV_NUM 0U +#define CYBSP_CS_CLK_DIV_NUM CYBSP_CSD_CLK_DIV_NUM #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_CLK_DIV_obj; + #define CYBSP_CS_CLK_DIV_obj CYBSP_CSD_CLK_DIV_obj #endif //defined (CY_USING_HAL) void init_cycfg_clocks(void); diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c new file mode 100644 index 0000000..954b06f --- /dev/null +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.c @@ -0,0 +1,30 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.c +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#include "cycfg_connectivity_bt.h" + diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h new file mode 100644 index 0000000..545ebcc --- /dev/null +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_connectivity_bt.h @@ -0,0 +1,54 @@ +/******************************************************************************* +* File Name: cycfg_connectivity_bt.h +* +* Description: +* Connectivity BT configuration +* This file was automatically generated and should not be modified. +* Tools Package 2.2.0.2790 +* latest-v2.X 2.0.0.6211 +* personalities 3.0.0.0 +* udd 3.0.0.562 +* +******************************************************************************** +* Copyright 2020 Cypress Semiconductor Corporation +* SPDX-License-Identifier: Apache-2.0 +* +* Licensed under the Apache License, Version 2.0 (the "License"); +* you may not use this file except in compliance with the License. +* You may obtain a copy of the License at +* +* http://www.apache.org/licenses/LICENSE-2.0 +* +* Unless required by applicable law or agreed to in writing, software +* distributed under the License is distributed on an "AS IS" BASIS, +* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +* See the License for the specific language governing permissions and +* limitations under the License. +********************************************************************************/ + +#if !defined(CYCFG_CONNECTIVITY_BT_H) +#define CYCFG_CONNECTIVITY_BT_H + +#include "cycfg_notices.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#define bt_0_power_0_ENABLED 1U +#define CYCFG_BT_LP_ENABLED (1u) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_LOW (0) +#define CYCFG_BT_WAKE_EVENT_ACTIVE_HIGH (1) +#define CYCFG_BT_HOST_WAKE_GPIO CYBSP_BT_HOST_WAKE +#define CYCFG_BT_HOST_WAKE_IRQ_EVENT CYBT_WAKE_ACTIVE_LOW +#define CYCFG_BT_DEV_WAKE_GPIO CYBSP_BT_DEVICE_WAKE +#define CYCFG_BT_DEV_WAKE_POLARITY CYBT_WAKE_ACTIVE_LOW + + +#if defined(__cplusplus) +} +#endif + + +#endif /* CYCFG_CONNECTIVITY_BT_H */ diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h index 4b1517e..dad34f4 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_notices.h @@ -5,7 +5,7 @@ * Contains warnings and errors that occurred while generating code for the * design. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c index 8e4647c..443364d 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.c @@ -4,7 +4,7 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h index 6dcfd0a..780a2ea 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_peripherals.h @@ -4,7 +4,7 @@ * Description: * Peripheral Hardware Block configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c index 89f1305..d794b6a 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.c @@ -4,7 +4,7 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h index 45655ae..b151d44 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_pins.h @@ -4,7 +4,7 @@ * Description: * Pin configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 @@ -151,31 +151,45 @@ extern "C" { #define CYBSP_USER_LED CYBSP_LED4 #endif //defined (CY_USING_HAL) #define CYBSP_CSD_TX_ENABLED 1U +#define CYBSP_CS_TX_ENABLED CYBSP_CSD_TX_ENABLED #define CYBSP_CSD_TX_PORT GPIO_PRT1 +#define CYBSP_CS_TX_PORT CYBSP_CSD_TX_PORT #define CYBSP_CSD_TX_PORT_NUM 1U +#define CYBSP_CS_TX_PORT_NUM CYBSP_CSD_TX_PORT_NUM #define CYBSP_CSD_TX_PIN 0U +#define CYBSP_CS_TX_PIN CYBSP_CSD_TX_PIN #define CYBSP_CSD_TX_NUM 0U +#define CYBSP_CS_TX_NUM CYBSP_CSD_TX_NUM #define CYBSP_CSD_TX_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_TX_DRIVEMODE CYBSP_CSD_TX_DRIVEMODE #define CYBSP_CSD_TX_INIT_DRIVESTATE 1 +#define CYBSP_CS_TX_INIT_DRIVESTATE CYBSP_CSD_TX_INIT_DRIVESTATE #ifndef ioss_0_port_1_pin_0_HSIOM #define ioss_0_port_1_pin_0_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_TX_HSIOM ioss_0_port_1_pin_0_HSIOM +#define CYBSP_CS_TX_HSIOM CYBSP_CSD_TX_HSIOM #define CYBSP_CSD_TX_IRQ ioss_interrupts_gpio_1_IRQn +#define CYBSP_CS_TX_IRQ CYBSP_CSD_TX_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_PORT_PIN P1_0 + #define CYBSP_CS_TX_HAL_PORT_PIN CYBSP_CSD_TX_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX P1_0 + #define CYBSP_CS_TX CYBSP_CSD_TX #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_TX_HAL_IRQ CYBSP_CSD_TX_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_TX_HAL_DIR CYBSP_CSD_TX_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_TX_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_TX_HAL_DRIVEMODE CYBSP_CSD_TX_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_WIFI_SDIO_D0 (P2_0) @@ -411,193 +425,291 @@ extern "C" { #define CYBSP_CMOD_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG #endif //defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_ENABLED 1U +#define CYBSP_CS_BTN0_ENABLED CYBSP_CSD_BTN0_ENABLED #define CYBSP_CSD_BTN0_PORT GPIO_PRT8 +#define CYBSP_CS_BTN0_PORT CYBSP_CSD_BTN0_PORT #define CYBSP_CSD_BTN0_PORT_NUM 8U +#define CYBSP_CS_BTN0_PORT_NUM CYBSP_CSD_BTN0_PORT_NUM #define CYBSP_CSD_BTN0_PIN 1U +#define CYBSP_CS_BTN0_PIN CYBSP_CSD_BTN0_PIN #define CYBSP_CSD_BTN0_NUM 1U +#define CYBSP_CS_BTN0_NUM CYBSP_CSD_BTN0_NUM #define CYBSP_CSD_BTN0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_BTN0_DRIVEMODE CYBSP_CSD_BTN0_DRIVEMODE #define CYBSP_CSD_BTN0_INIT_DRIVESTATE 1 +#define CYBSP_CS_BTN0_INIT_DRIVESTATE CYBSP_CSD_BTN0_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_1_HSIOM #define ioss_0_port_8_pin_1_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_BTN0_HSIOM ioss_0_port_8_pin_1_HSIOM +#define CYBSP_CS_BTN0_HSIOM CYBSP_CSD_BTN0_HSIOM #define CYBSP_CSD_BTN0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_BTN0_IRQ CYBSP_CSD_BTN0_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_PORT_PIN P8_1 + #define CYBSP_CS_BTN0_HAL_PORT_PIN CYBSP_CSD_BTN0_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0 P8_1 + #define CYBSP_CS_BTN0 CYBSP_CSD_BTN0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_BTN0_HAL_IRQ CYBSP_CSD_BTN0_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_BTN0_HAL_DIR CYBSP_CSD_BTN0_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_BTN0_HAL_DRIVEMODE CYBSP_CSD_BTN0_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_ENABLED 1U +#define CYBSP_CS_BTN1_ENABLED CYBSP_CSD_BTN1_ENABLED #define CYBSP_CSD_BTN1_PORT GPIO_PRT8 +#define CYBSP_CS_BTN1_PORT CYBSP_CSD_BTN1_PORT #define CYBSP_CSD_BTN1_PORT_NUM 8U +#define CYBSP_CS_BTN1_PORT_NUM CYBSP_CSD_BTN1_PORT_NUM #define CYBSP_CSD_BTN1_PIN 2U +#define CYBSP_CS_BTN1_PIN CYBSP_CSD_BTN1_PIN #define CYBSP_CSD_BTN1_NUM 2U +#define CYBSP_CS_BTN1_NUM CYBSP_CSD_BTN1_NUM #define CYBSP_CSD_BTN1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_BTN1_DRIVEMODE CYBSP_CSD_BTN1_DRIVEMODE #define CYBSP_CSD_BTN1_INIT_DRIVESTATE 1 +#define CYBSP_CS_BTN1_INIT_DRIVESTATE CYBSP_CSD_BTN1_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_2_HSIOM #define ioss_0_port_8_pin_2_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_BTN1_HSIOM ioss_0_port_8_pin_2_HSIOM +#define CYBSP_CS_BTN1_HSIOM CYBSP_CSD_BTN1_HSIOM #define CYBSP_CSD_BTN1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_BTN1_IRQ CYBSP_CSD_BTN1_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_PORT_PIN P8_2 + #define CYBSP_CS_BTN1_HAL_PORT_PIN CYBSP_CSD_BTN1_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1 P8_2 + #define CYBSP_CS_BTN1 CYBSP_CSD_BTN1 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_BTN1_HAL_IRQ CYBSP_CSD_BTN1_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_BTN1_HAL_DIR CYBSP_CSD_BTN1_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_BTN1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_BTN1_HAL_DRIVEMODE CYBSP_CSD_BTN1_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_ENABLED 1U +#define CYBSP_CS_SLD0_ENABLED CYBSP_CSD_SLD0_ENABLED #define CYBSP_CSD_SLD0_PORT GPIO_PRT8 +#define CYBSP_CS_SLD0_PORT CYBSP_CSD_SLD0_PORT #define CYBSP_CSD_SLD0_PORT_NUM 8U +#define CYBSP_CS_SLD0_PORT_NUM CYBSP_CSD_SLD0_PORT_NUM #define CYBSP_CSD_SLD0_PIN 3U +#define CYBSP_CS_SLD0_PIN CYBSP_CSD_SLD0_PIN #define CYBSP_CSD_SLD0_NUM 3U +#define CYBSP_CS_SLD0_NUM CYBSP_CSD_SLD0_NUM #define CYBSP_CSD_SLD0_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD0_DRIVEMODE CYBSP_CSD_SLD0_DRIVEMODE #define CYBSP_CSD_SLD0_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD0_INIT_DRIVESTATE CYBSP_CSD_SLD0_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_3_HSIOM #define ioss_0_port_8_pin_3_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD0_HSIOM ioss_0_port_8_pin_3_HSIOM +#define CYBSP_CS_SLD0_HSIOM CYBSP_CSD_SLD0_HSIOM #define CYBSP_CSD_SLD0_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD0_IRQ CYBSP_CSD_SLD0_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_PORT_PIN P8_3 + #define CYBSP_CS_SLD0_HAL_PORT_PIN CYBSP_CSD_SLD0_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0 P8_3 + #define CYBSP_CS_SLD0 CYBSP_CSD_SLD0 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD0_HAL_IRQ CYBSP_CSD_SLD0_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD0_HAL_DIR CYBSP_CSD_SLD0_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD0_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD0_HAL_DRIVEMODE CYBSP_CSD_SLD0_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_ENABLED 1U +#define CYBSP_CS_SLD1_ENABLED CYBSP_CSD_SLD1_ENABLED #define CYBSP_CSD_SLD1_PORT GPIO_PRT8 +#define CYBSP_CS_SLD1_PORT CYBSP_CSD_SLD1_PORT #define CYBSP_CSD_SLD1_PORT_NUM 8U +#define CYBSP_CS_SLD1_PORT_NUM CYBSP_CSD_SLD1_PORT_NUM #define CYBSP_CSD_SLD1_PIN 4U +#define CYBSP_CS_SLD1_PIN CYBSP_CSD_SLD1_PIN #define CYBSP_CSD_SLD1_NUM 4U +#define CYBSP_CS_SLD1_NUM CYBSP_CSD_SLD1_NUM #define CYBSP_CSD_SLD1_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD1_DRIVEMODE CYBSP_CSD_SLD1_DRIVEMODE #define CYBSP_CSD_SLD1_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD1_INIT_DRIVESTATE CYBSP_CSD_SLD1_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_4_HSIOM #define ioss_0_port_8_pin_4_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD1_HSIOM ioss_0_port_8_pin_4_HSIOM +#define CYBSP_CS_SLD1_HSIOM CYBSP_CSD_SLD1_HSIOM #define CYBSP_CSD_SLD1_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD1_IRQ CYBSP_CSD_SLD1_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_PORT_PIN P8_4 + #define CYBSP_CS_SLD1_HAL_PORT_PIN CYBSP_CSD_SLD1_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1 P8_4 + #define CYBSP_CS_SLD1 CYBSP_CSD_SLD1 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD1_HAL_IRQ CYBSP_CSD_SLD1_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD1_HAL_DIR CYBSP_CSD_SLD1_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD1_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD1_HAL_DRIVEMODE CYBSP_CSD_SLD1_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_ENABLED 1U +#define CYBSP_CS_SLD2_ENABLED CYBSP_CSD_SLD2_ENABLED #define CYBSP_CSD_SLD2_PORT GPIO_PRT8 +#define CYBSP_CS_SLD2_PORT CYBSP_CSD_SLD2_PORT #define CYBSP_CSD_SLD2_PORT_NUM 8U +#define CYBSP_CS_SLD2_PORT_NUM CYBSP_CSD_SLD2_PORT_NUM #define CYBSP_CSD_SLD2_PIN 5U +#define CYBSP_CS_SLD2_PIN CYBSP_CSD_SLD2_PIN #define CYBSP_CSD_SLD2_NUM 5U +#define CYBSP_CS_SLD2_NUM CYBSP_CSD_SLD2_NUM #define CYBSP_CSD_SLD2_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD2_DRIVEMODE CYBSP_CSD_SLD2_DRIVEMODE #define CYBSP_CSD_SLD2_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD2_INIT_DRIVESTATE CYBSP_CSD_SLD2_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_5_HSIOM #define ioss_0_port_8_pin_5_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD2_HSIOM ioss_0_port_8_pin_5_HSIOM +#define CYBSP_CS_SLD2_HSIOM CYBSP_CSD_SLD2_HSIOM #define CYBSP_CSD_SLD2_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD2_IRQ CYBSP_CSD_SLD2_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_PORT_PIN P8_5 + #define CYBSP_CS_SLD2_HAL_PORT_PIN CYBSP_CSD_SLD2_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2 P8_5 + #define CYBSP_CS_SLD2 CYBSP_CSD_SLD2 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD2_HAL_IRQ CYBSP_CSD_SLD2_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD2_HAL_DIR CYBSP_CSD_SLD2_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD2_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD2_HAL_DRIVEMODE CYBSP_CSD_SLD2_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_ENABLED 1U +#define CYBSP_CS_SLD3_ENABLED CYBSP_CSD_SLD3_ENABLED #define CYBSP_CSD_SLD3_PORT GPIO_PRT8 +#define CYBSP_CS_SLD3_PORT CYBSP_CSD_SLD3_PORT #define CYBSP_CSD_SLD3_PORT_NUM 8U +#define CYBSP_CS_SLD3_PORT_NUM CYBSP_CSD_SLD3_PORT_NUM #define CYBSP_CSD_SLD3_PIN 6U +#define CYBSP_CS_SLD3_PIN CYBSP_CSD_SLD3_PIN #define CYBSP_CSD_SLD3_NUM 6U +#define CYBSP_CS_SLD3_NUM CYBSP_CSD_SLD3_NUM #define CYBSP_CSD_SLD3_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD3_DRIVEMODE CYBSP_CSD_SLD3_DRIVEMODE #define CYBSP_CSD_SLD3_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD3_INIT_DRIVESTATE CYBSP_CSD_SLD3_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_6_HSIOM #define ioss_0_port_8_pin_6_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD3_HSIOM ioss_0_port_8_pin_6_HSIOM +#define CYBSP_CS_SLD3_HSIOM CYBSP_CSD_SLD3_HSIOM #define CYBSP_CSD_SLD3_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD3_IRQ CYBSP_CSD_SLD3_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_PORT_PIN P8_6 + #define CYBSP_CS_SLD3_HAL_PORT_PIN CYBSP_CSD_SLD3_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3 P8_6 + #define CYBSP_CS_SLD3 CYBSP_CSD_SLD3 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD3_HAL_IRQ CYBSP_CSD_SLD3_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD3_HAL_DIR CYBSP_CSD_SLD3_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD3_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD3_HAL_DRIVEMODE CYBSP_CSD_SLD3_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_ENABLED 1U +#define CYBSP_CS_SLD4_ENABLED CYBSP_CSD_SLD4_ENABLED #define CYBSP_CSD_SLD4_PORT GPIO_PRT8 +#define CYBSP_CS_SLD4_PORT CYBSP_CSD_SLD4_PORT #define CYBSP_CSD_SLD4_PORT_NUM 8U +#define CYBSP_CS_SLD4_PORT_NUM CYBSP_CSD_SLD4_PORT_NUM #define CYBSP_CSD_SLD4_PIN 7U +#define CYBSP_CS_SLD4_PIN CYBSP_CSD_SLD4_PIN #define CYBSP_CSD_SLD4_NUM 7U +#define CYBSP_CS_SLD4_NUM CYBSP_CSD_SLD4_NUM #define CYBSP_CSD_SLD4_DRIVEMODE CY_GPIO_DM_ANALOG +#define CYBSP_CS_SLD4_DRIVEMODE CYBSP_CSD_SLD4_DRIVEMODE #define CYBSP_CSD_SLD4_INIT_DRIVESTATE 1 +#define CYBSP_CS_SLD4_INIT_DRIVESTATE CYBSP_CSD_SLD4_INIT_DRIVESTATE #ifndef ioss_0_port_8_pin_7_HSIOM #define ioss_0_port_8_pin_7_HSIOM HSIOM_SEL_GPIO #endif #define CYBSP_CSD_SLD4_HSIOM ioss_0_port_8_pin_7_HSIOM +#define CYBSP_CS_SLD4_HSIOM CYBSP_CSD_SLD4_HSIOM #define CYBSP_CSD_SLD4_IRQ ioss_interrupts_gpio_8_IRQn +#define CYBSP_CS_SLD4_IRQ CYBSP_CSD_SLD4_IRQ #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_PORT_PIN P8_7 + #define CYBSP_CS_SLD4_HAL_PORT_PIN CYBSP_CSD_SLD4_HAL_PORT_PIN #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4 P8_7 + #define CYBSP_CS_SLD4 CYBSP_CSD_SLD4 #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_IRQ CYHAL_GPIO_IRQ_NONE + #define CYBSP_CS_SLD4_HAL_IRQ CYBSP_CSD_SLD4_HAL_IRQ #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DIR CYHAL_GPIO_DIR_INPUT + #define CYBSP_CS_SLD4_HAL_DIR CYBSP_CSD_SLD4_HAL_DIR #endif //defined (CY_USING_HAL) #if defined (CY_USING_HAL) #define CYBSP_CSD_SLD4_HAL_DRIVEMODE CYHAL_GPIO_DRIVE_ANALOG + #define CYBSP_CS_SLD4_HAL_DRIVEMODE CYBSP_CSD_SLD4_HAL_DRIVEMODE #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_WCO_IN_config; @@ -609,8 +721,10 @@ extern const cy_stc_gpio_pin_config_t CYBSP_WCO_OUT_config; extern const cyhal_resource_inst_t CYBSP_WCO_OUT_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_TX_config; +#define CYBSP_CS_TX_config CYBSP_CSD_TX_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_TX_obj; + #define CYBSP_CS_TX_obj CYBSP_CSD_TX_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_SWO_config; #if defined (CY_USING_HAL) @@ -637,32 +751,46 @@ extern const cy_stc_gpio_pin_config_t CYBSP_CMOD_config; extern const cyhal_resource_inst_t CYBSP_CMOD_obj; #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN0_config; +#define CYBSP_CS_BTN0_config CYBSP_CSD_BTN0_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_BTN0_obj; + #define CYBSP_CS_BTN0_obj CYBSP_CSD_BTN0_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_BTN1_config; +#define CYBSP_CS_BTN1_config CYBSP_CSD_BTN1_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_BTN1_obj; + #define CYBSP_CS_BTN1_obj CYBSP_CSD_BTN1_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD0_config; +#define CYBSP_CS_SLD0_config CYBSP_CSD_SLD0_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD0_obj; + #define CYBSP_CS_SLD0_obj CYBSP_CSD_SLD0_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD1_config; +#define CYBSP_CS_SLD1_config CYBSP_CSD_SLD1_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD1_obj; + #define CYBSP_CS_SLD1_obj CYBSP_CSD_SLD1_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD2_config; +#define CYBSP_CS_SLD2_config CYBSP_CSD_SLD2_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD2_obj; + #define CYBSP_CS_SLD2_obj CYBSP_CSD_SLD2_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD3_config; +#define CYBSP_CS_SLD3_config CYBSP_CSD_SLD3_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD3_obj; + #define CYBSP_CS_SLD3_obj CYBSP_CSD_SLD3_obj #endif //defined (CY_USING_HAL) extern const cy_stc_gpio_pin_config_t CYBSP_CSD_SLD4_config; +#define CYBSP_CS_SLD4_config CYBSP_CSD_SLD4_config #if defined (CY_USING_HAL) extern const cyhal_resource_inst_t CYBSP_CSD_SLD4_obj; + #define CYBSP_CS_SLD4_obj CYBSP_CSD_SLD4_obj #endif //defined (CY_USING_HAL) void init_cycfg_pins(void); diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c index f3bff59..805668d 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.c @@ -4,7 +4,7 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h index 1a304c0..ea1de77 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_routing.h @@ -4,7 +4,7 @@ * Description: * Establishes all necessary connections between hardware elements. * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c index efb5cd5..1397ecb 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.c @@ -4,7 +4,7 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h index 8a4c421..3ec01db 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h +++ b/COMPONENT_BSP_DESIGN_MODUS/GeneratedSource/cycfg_system.h @@ -4,7 +4,7 @@ * Description: * System configuration * This file was automatically generated and should not be modified. -* Tools Package 2.2.0.2801 +* Tools Package 2.2.0.2790 * latest-v2.X 2.0.0.6211 * personalities 3.0.0.0 * udd 3.0.0.562 diff --git a/COMPONENT_BSP_DESIGN_MODUS/design.modus b/COMPONENT_BSP_DESIGN_MODUS/design.modus index 24310b8..1423119 100644 --- a/COMPONENT_BSP_DESIGN_MODUS/design.modus +++ b/COMPONENT_BSP_DESIGN_MODUS/design.modus @@ -1,6 +1,6 @@ - + @@ -133,6 +133,7 @@ + @@ -295,6 +296,7 @@ + @@ -308,6 +310,7 @@ + @@ -321,6 +324,7 @@ + @@ -334,6 +338,7 @@ + @@ -347,6 +352,7 @@ + @@ -360,6 +366,7 @@ + @@ -373,6 +380,7 @@ + @@ -386,6 +394,7 @@ + @@ -574,7 +583,16 @@ - + + + + + + + + + + diff --git a/CY8CPROTO-062-4343W.mk b/CY8CPROTO-062-4343W.mk index 078f4cb..e54ac37 100644 --- a/CY8CPROTO-062-4343W.mk +++ b/CY8CPROTO-062-4343W.mk @@ -6,7 +6,7 @@ # ################################################################################ # \copyright -# Copyright 2018-2020 Cypress Semiconductor Corporation +# Copyright 2018-2021 Cypress Semiconductor Corporation # SPDX-License-Identifier: Apache-2.0 # # Licensed under the Apache License, Version 2.0 (the "License"); @@ -30,17 +30,23 @@ endif include $(dir $(lastword $(MAKEFILE_LIST)))/locate_recipe.mk # MCU device selection +# Changing the device should be done using “make bsp” or “make update_bsp” with the “DEVICE_GEN” +# variable set to the new MCU. If you change the device manually here you must also update the +# design.modus file and re-run the device configurator. DEVICE:=CY8C624ABZI-S2D44 # Additional devices on the board +# If you change the additional device here you must also update the design.modus file and re-run +# the device configurator. You may also need to update the COMPONENT variable to include the +# correct Wi-Fi and Bluetooth firmware. ADDITIONAL_DEVICES:=CYW4343WKUBG # Default target core to CM4 if not already set CORE?=CM4 # Basic architecture specific components -COMPONENTS+=CAT1A +COMPONENTS+=$(TARGET) CAT1 CAT1A ifeq ($(CORE),CM4) # Additional components supported by the target -COMPONENTS+=CM0P_SLEEP BSP_DESIGN_MODUS PSOC6HAL 4343W +COMPONENTS+=CM0P_SLEEP BSP_DESIGN_MODUS PSOC6HAL 4343W WLBGA # Use CyHAL DEFINES+=CY_USING_HAL endif diff --git a/README.md b/README.md index 5138c0d..b71ab9c 100644 --- a/README.md +++ b/README.md @@ -28,13 +28,13 @@ To use code from the BSP, simply include a reference to `cybsp.h`. The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CPROTO-062-4343W.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile. Components: - * Device specific HAL reference (e.g.: PSOC6HAL) - This component, enabled by default, pulls in the version of the HAL that is applicable for this board. - * BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component. - * CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component. +* Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board. +* BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component. +* CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component. Defines: - * CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip. - * CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers. +* CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one. +* CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers. ### Clock Configuration @@ -51,6 +51,8 @@ Defines: * VDDA Voltage: 3300 mV * VDDD Voltage: 3300 mV +See the [BSP Setttings][settings] for additional board specific configuration settings. + ## API Reference Manual The CY8CPROTO-062-4343W Board Support Package provides a set of APIs to configure, initialize and use the board resources. @@ -65,6 +67,7 @@ See the [BSP API Reference Manual][api] for the complete list of the provided in * [ModusToolbox](https://www.cypress.com/products/modustoolbox-software-environment) [api]: https://cypresssemiconductorco.github.io/TARGET_CY8CPROTO-062-4343W/html/modules.html +[settings]: https://cypresssemiconductorco.github.io/TARGET_CY8CPROTO-062-4343W/html/md_bsp_settings.html --- -© Cypress Semiconductor Corporation, 2019-2020. \ No newline at end of file +© Cypress Semiconductor Corporation, 2019-2021. \ No newline at end of file diff --git a/RELEASE.md b/RELEASE.md index 9cedb3d..3a91507 100644 --- a/RELEASE.md +++ b/RELEASE.md @@ -8,17 +8,24 @@ The CY8CPROTO-062-4343W library includes the following: * BSP specific makefile to configure the build process for the board * cybsp.c/h files to initialize the board and any system peripherals * cybsp_types.h file describing basic board setup -* CM4 Linker script & startup code for GCC, IAR, ARM toolchains -* CM0+ Linker script & startup code for GCC, IAR, ARM toolchains +* CM4 Linker script & startup code for GCC, IAR, and ARM toolchains +* CM0+ Linker script & startup code for GCC, IAR, and ARM toolchains * Configurator design files (and generated code) to setup board specific peripherals * .lib file references for all dependent libraries * API documentation ### What Changed? +#### v2.1.0 +* Added component CAT1 to all boards +* Added new components for connectivity chips +* Added BT configuration settings for boards that support it +* Minor documentation updates +#### v2.0.1 +* Minor update to better handle when to include the SCL library in the build #### v2.0.0 * Updated design files and GeneratedSource with ModusToolbox 2.2 release * Migrated pin definitions into design.modus file -* Updated clock frequencies to 144 MHz (fast) / 72 MHz (slow) +* Updated clock frequencies to 100 MHz (fast) / 50 MHz (slow) * Updated MPNs on some boards to non-obsolete parts * Switched psoc6pdl dependency to new mtb-pdl * Switched psoc6hal dependency to new mtb-hal @@ -51,8 +58,8 @@ This version of the CY8CPROTO-062-4343W BSP was validated for compatibility with | Software and Tools | Version | | :--- | :----: | -| ModusToolbox Software Environment | 2.2 | -| GCC Compiler | 9.2 | +| ModusToolbox Software Environment | 2.2.1 | +| GCC Compiler | 9.3.1 | | IAR Compiler | 8.4 | | ARM Compiler | 6.11 | @@ -68,4 +75,4 @@ Minimum required ModusToolbox Software Environment: v2.2 [api]: modules.html --- -© Cypress Semiconductor Corporation, 2019-2020. \ No newline at end of file +© Cypress Semiconductor Corporation, 2019-2021. \ No newline at end of file diff --git a/bluetooth/cybsp_bt_config.c b/bluetooth/cybsp_bt_config.c new file mode 100644 index 0000000..3ce8aba --- /dev/null +++ b/bluetooth/cybsp_bt_config.c @@ -0,0 +1,77 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2020-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) + +#include "cybsp_bt_config.h" +#include "wiced_bt_dev.h" + +const cybt_platform_config_t cybsp_bt_platform_cfg = +{ + .hci_config = + { + .hci_transport = CYBT_HCI_UART, + + .hci = + { + .hci_uart = + { + .uart_tx_pin = CYBSP_BT_UART_TX, + .uart_rx_pin = CYBSP_BT_UART_RX, + .uart_rts_pin = CYBSP_BT_UART_RTS, + .uart_cts_pin = CYBSP_BT_UART_CTS, + + .baud_rate_for_fw_download = CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD, + .baud_rate_for_feature = CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE, + + .data_bits = CYBSP_BT_PLATFORM_CFG_BITS_DATA, + .stop_bits = CYBSP_BT_PLATFORM_CFG_BITS_STOP, + .parity = CYHAL_UART_PARITY_NONE, + .flow_control = true + } + } + }, + + .controller_config = + { + .bt_power_pin = CYBSP_BT_POWER, + #if (bt_0_power_0_ENABLED == 1) + .sleep_mode = + { + .sleep_mode_enabled = CYCFG_BT_LP_ENABLED, + .device_wakeup_pin = CYCFG_BT_DEV_WAKE_GPIO, + .host_wakeup_pin = CYCFG_BT_HOST_WAKE_GPIO, + .device_wake_polarity = CYCFG_BT_DEV_WAKE_POLARITY, + .host_wake_polarity = CYCFG_BT_HOST_WAKE_IRQ_EVENT + } + #else + .sleep_mode = + { + .sleep_mode_enabled = true, + .device_wakeup_pin = CYBSP_BT_DEVICE_WAKE, + .host_wakeup_pin = CYBSP_BT_HOST_WAKE, + .device_wake_polarity = CYBT_WAKE_ACTIVE_LOW, + .host_wake_polarity = CYBT_WAKE_ACTIVE_LOW + } + #endif /* (bt_0_power_0_ENABLED == 1) */ + }, + + .task_mem_pool_size = CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES +}; + +#endif /* defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) */ diff --git a/bluetooth/cybsp_bt_config.h b/bluetooth/cybsp_bt_config.h new file mode 100644 index 0000000..79f54f4 --- /dev/null +++ b/bluetooth/cybsp_bt_config.h @@ -0,0 +1,69 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2020-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +/** + * \addtogroup group_bsp_bt Bluetooth Configuration Structure + * \{ + * Basic configuration structure for the Bluetooth interface on this board. + */ +#pragma once + +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) + +#include "cybt_platform_config.h" +#include "cycfg_pins.h" + +#if defined(__cplusplus) +extern "C" { +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD) +/** If not already defined, the baud rate to download data at. */ +#define CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD (115200) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE) +/** If not already defined, the baud rate for general operation. */ +#define CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE (115200) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BITS_DATA) +/** If not already defined, the number of data bits to transmit. */ +#define CYBSP_BT_PLATFORM_CFG_BITS_DATA (8) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_BITS_STOP) +/** If not already defined, the number of stop bits to transmit. */ +#define CYBSP_BT_PLATFORM_CFG_BITS_STOP (1) +#endif + +#if !defined(CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES) +/** If not already defined, the number of bytes to allocated for the task memory pool. */ +#define CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES (2048) +#endif + +/** Bluetooth platform configuration settings for the board. */ +extern const cybt_platform_config_t cybsp_bt_platform_cfg; + +#ifdef __cplusplus +} +#endif // __cplusplus + +#endif /* defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) */ + +/** \} group_bsp_bt */ diff --git a/cybsp.c b/cybsp.c index 4d49b35..e8407b7 100644 --- a/cybsp.c +++ b/cybsp.c @@ -7,7 +7,7 @@ * ******************************************************************************** * \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation +* Copyright 2018-2021 Cypress Semiconductor Corporation * SPDX-License-Identifier: Apache-2.0 * * Licensed under the Apache License, Version 2.0 (the "License"); @@ -36,11 +36,9 @@ extern "C" { #endif -/* The sysclk deep sleep callback is recommended to be the last callback that -* is executed before entry into deep sleep mode and the first one upon -* exit the deep sleep mode. -* Doing so minimizes the time spent on low power mode entry and exit. -*/ +// The sysclk deep sleep callback is recommended to be the last callback that is executed before +// entry into deep sleep mode and the first one upon exit the deep sleep mode. +// Doing so minimizes the time spent on low power mode entry and exit. #ifndef CYBSP_SYSCLK_PM_CALLBACK_ORDER #define CYBSP_SYSCLK_PM_CALLBACK_ORDER (255u) #endif @@ -48,26 +46,34 @@ extern "C" { #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) static cyhal_sdio_t sdio_obj; +//-------------------------------------------------------------------------------------------------- +// cybsp_get_wifi_sdio_obj +//-------------------------------------------------------------------------------------------------- cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void) { return &sdio_obj; } -#endif -/** - * Registers a power management callback that prepares the clock system - * for entering deep sleep mode and restore the clocks upon wakeup from deep sleep. - * NOTE: This is called automatically as part of \ref cybsp_init - */ + +#endif // if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + +//-------------------------------------------------------------------------------------------------- +// cybsp_register_sysclk_pm_callback +// +// Registers a power management callback that prepares the clock system for entering deep sleep mode +// and restore the clocks upon wakeup from deep sleep. +// NOTE: This is called automatically as part of \ref cybsp_init +//-------------------------------------------------------------------------------------------------- static cy_rslt_t cybsp_register_sysclk_pm_callback(void) { - cy_rslt_t result = CY_RSLT_SUCCESS; - static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = {NULL, NULL}; - static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = { - .callback = &Cy_SysClk_DeepSleepCallback, - .type = CY_SYSPM_DEEPSLEEP, + cy_rslt_t result = CY_RSLT_SUCCESS; + static cy_stc_syspm_callback_params_t cybsp_sysclk_pm_callback_param = { NULL, NULL }; + static cy_stc_syspm_callback_t cybsp_sysclk_pm_callback = + { + .callback = &Cy_SysClk_DeepSleepCallback, + .type = CY_SYSPM_DEEPSLEEP, .callbackParams = &cybsp_sysclk_pm_callback_param, - .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER + .order = CYBSP_SYSCLK_PM_CALLBACK_ORDER }; if (!Cy_SysPm_RegisterCallback(&cybsp_sysclk_pm_callback)) @@ -77,10 +83,15 @@ static cy_rslt_t cybsp_register_sysclk_pm_callback(void) return result; } + +//-------------------------------------------------------------------------------------------------- +// cybsp_init +//-------------------------------------------------------------------------------------------------- cy_rslt_t cybsp_init(void) { - /* Setup hardware manager to track resource usage then initialize all system (clock/power) board configuration */ -#if defined(CY_USING_HAL) + // Setup hardware manager to track resource usage then initialize all system (clock/power) board + // configuration + #if defined(CY_USING_HAL) cy_rslt_t result = cyhal_hwmgr_init(); if (CY_RSLT_SUCCESS == result) @@ -88,55 +99,53 @@ cy_rslt_t cybsp_init(void) result = cyhal_syspm_init(); } -#ifdef CY_CFG_PWR_VDDA_MV - if(CY_RSLT_SUCCESS == result) + #ifdef CY_CFG_PWR_VDDA_MV + if (CY_RSLT_SUCCESS == result) { cyhal_syspm_set_supply_voltage(CYHAL_VOLTAGE_SUPPLY_VDDA, CY_CFG_PWR_VDDA_MV); } -#endif + #endif -#else + #else // if defined(CY_USING_HAL) cy_rslt_t result = CY_RSLT_SUCCESS; -#endif + #endif // if defined(CY_USING_HAL) -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) + #if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) init_cycfg_all(); -#endif + #endif if (CY_RSLT_SUCCESS == result) { result = cybsp_register_sysclk_pm_callback(); } -#if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) - /* Initialize SDIO interface. This must be done before other HAL API calls as some SDIO implementations require - * specific peripheral instances. - * NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). This is typically - * done when starting up WiFi. - */ + #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) + // Initialize SDIO interface. This must be done before other HAL API calls as some SDIO + // implementations require specific peripheral instances. + // NOTE: The full WiFi interface still needs to be initialized via cybsp_wifi_init_primary(). + // This is typically done when starting up WiFi. if (CY_RSLT_SUCCESS == result) { - /* Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, CYBSP_WIFI_SDIO_D3 - * CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. - */ + // Reserves: CYBSP_WIFI_SDIO, CYBSP_WIFI_SDIO_D0, CYBSP_WIFI_SDIO_D1, CYBSP_WIFI_SDIO_D2, + // CYBSP_WIFI_SDIO_D3, CYBSP_WIFI_SDIO_CMD and CYBSP_WIFI_SDIO_CLK. result = cyhal_sdio_init( - &sdio_obj, - CYBSP_WIFI_SDIO_CMD, - CYBSP_WIFI_SDIO_CLK, - CYBSP_WIFI_SDIO_D0, - CYBSP_WIFI_SDIO_D1, - CYBSP_WIFI_SDIO_D2, - CYBSP_WIFI_SDIO_D3); + &sdio_obj, + CYBSP_WIFI_SDIO_CMD, + CYBSP_WIFI_SDIO_CLK, + CYBSP_WIFI_SDIO_D0, + CYBSP_WIFI_SDIO_D1, + CYBSP_WIFI_SDIO_D2, + CYBSP_WIFI_SDIO_D3); } -#endif /* defined(CYBSP_WIFI_CAPABLE) */ + #endif // defined(CYBSP_WIFI_CAPABLE) - /* CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was reserved by - * user previously. Please review the Device Configurator (design.modus) and the BSP reservation list - * (cyreservedresources.list) to make sure no resources are reserved by both. - */ + // CYHAL_HWMGR_RSLT_ERR_INUSE error code could be returned if any needed for BSP resource was + // reserved by user previously. Please review the Device Configurator (design.modus) and the BSP + // reservation list (cyreservedresources.list) to make sure no resources are reserved by both. return result; } + #if defined(__cplusplus) } #endif diff --git a/cybsp.h b/cybsp.h index 1ec5ff5..c60384c 100644 --- a/cybsp.h +++ b/cybsp.h @@ -1,26 +1,26 @@ -/***************************************************************************//** -* \file cybsp.h -* -* \brief -* Basic API for setting up boards containing a Cypress MCU. -* -******************************************************************************** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \file cybsp.h + * + * \brief + * Basic API for setting up boards containing a Cypress MCU. + * + *************************************************************************************************** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #pragma once @@ -29,29 +29,35 @@ #if defined(CYBSP_WIFI_CAPABLE) && defined(CY_USING_HAL) #include "cyhal_sdio.h" #endif +#if defined(COMPONENT_WICED_BLE) || defined(COMPONENT_WICED_DUALMODE) +#include "cybsp_bt_config.h" +#endif #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_macros Macros -* \{ -*/ + * \addtogroup group_bsp_errors Error Codes + * \{ + * Error codes specific to the board. + */ /** Failed to configure sysclk power management callback */ -#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) +#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK \ + (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0)) -/** \} group_bsp_macros */ +/** \} group_bsp_errors */ /** -* \addtogroup group_bsp_functions Functions -* \{ -*/ + * \addtogroup group_bsp_functions Functions + * \{ + * All functions exposed by the board. + */ /** * \brief Initialize all hardware on the board - * \returns CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is + * \returns CY_RSLT_SUCCESS if the board is successfully initialized, if there is * a problem initializing any hardware it returns an error code specific * to the hardware module that had a problem. */ @@ -64,10 +70,10 @@ cy_rslt_t cybsp_init(void); * \returns The initialized sdio object. */ cyhal_sdio_t* cybsp_get_wifi_sdio_obj(void); -#endif /* defined(CYBSP_WIFI_CAPABLE) */ +#endif // defined(CYBSP_WIFI_CAPABLE) /** \} group_bsp_functions */ #ifdef __cplusplus } -#endif /* __cplusplus */ +#endif // __cplusplus diff --git a/cybsp_doc.h b/cybsp_doc.h new file mode 100644 index 0000000..997d9fb --- /dev/null +++ b/cybsp_doc.h @@ -0,0 +1,838 @@ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ + +#pragma once + +#if defined(CY_USING_HAL) +#include "cyhal_pin_package.h" +#endif +#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) +#include "cycfg.h" +#endif + +#if defined(__cplusplus) +extern "C" { +#endif + +/** + * \addtogroup group_bsp_pins Pin Mappings + * \{ + * Macro definitions for common peripheral pins on the board. + */ + +#if defined(CYBSP_USER_LED) +/** + * \addtogroup group_bsp_pins_led LED Pins + * \{ + * Pins connected to user LEDs on the board. + */ + +#ifdef CYBSP_LED_RGB_RED +/** RGB LED - Red \def CYBSP_LED_RGB_RED + */ +#endif +#ifdef CYBSP_LED_RGB_GREEN +/** RGB LED - Green \def CYBSP_LED_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED_RGB_BLUE +/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE + */ +#endif +#ifdef CYBSP_USER_LED +/** User LED \def CYBSP_USER_LED + */ +#endif +#ifdef CYBSP_USER_LED1 +/** User LED1 \def CYBSP_USER_LED1 + */ +#endif +#ifdef CYBSP_USER_LED2 +/** User LED2 \def CYBSP_USER_LED2 + */ +#endif +#ifdef CYBSP_USER_LED3 +/** User LED3 \def CYBSP_USER_LED3 + */ +#endif +#ifdef CYBSP_USER_LED4 +/** User LED 4 \def CYBSP_USER_LED4 + */ +#endif +#ifdef CYBSP_USER_LED5 +/** User LED 5 \def CYBSP_USER_LED5 + */ +#endif +#ifdef CYBSP_USER_LED6 +/** User LED 6 \def CYBSP_USER_LED6 + */ +#endif +#ifdef CYBSP_USER_LED7 +/** User LED 7 \def CYBSP_USER_LED7 + */ +#endif +#ifdef CYBSP_USER_LED8 +/** User LED 8 \def CYBSP_USER_LED8 + */ +#endif +#ifdef CYBSP_USER_LED9 +/** User LED 9 \def CYBSP_USER_LED9 + */ +#endif +#ifdef CYBSP_USER_LED10 +/** User LED 10 \def CYBSP_USER_LED10 + */ +#endif +#ifdef CYBSP_LED1 +/** LED 1 \def CYBSP_LED1 + */ +#endif +#ifdef CYBSP_LED2 +/** LED 2 \def CYBSP_LED2 + */ +#endif +#ifdef CYBSP_LED3 +/** LED 3 \def CYBSP_LED3 + */ +#endif +#ifdef CYBSP_LED3_RGB_RED +/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED + */ +#endif +#ifdef CYBSP_LED3_RGB_GREEN +/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN + */ +#endif +#ifdef CYBSP_LED3_RGB_BLUE +/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE + */ +#endif +#ifdef CYBSP_LED4 +/** LED 4 \def CYBSP_LED4 + */ +#endif +#ifdef CYBSP_LED5 +/** LED 5 \def CYBSP_LED5 + */ +#endif +#ifdef CYBSP_LED6 +/** LED 6 \def CYBSP_LED6 + */ +#endif +#ifdef CYBSP_LED7 +/** LED 7 \def CYBSP_LED7 + */ +#endif +#ifdef CYBSP_LED8 +/** LED 8 \def CYBSP_LED8 + */ +#endif +#ifdef CYBSP_LED9 +/** LED 9 \def CYBSP_LED9 + */ +#endif +#ifdef CYBSP_LED10 +/** LED 10 \def CYBSP_LED10 + */ +#endif +#ifdef CYBSP_LED11 +/** LED 11 \def CYBSP_LED11 + */ +#endif +#ifdef CYBSP_LED12 +/** LED 12 \def CYBSP_LED12 + */ +#endif +#ifdef CYBSP_LED13 +/** LED 13 \def CYBSP_LED13 + */ +#endif +#ifdef CYBSP_LED_SLD0 +/** Slider LED 0 \def CYBSP_LED_SLD0 + */ +#endif +#ifdef CYBSP_LED_SLD1 +/** Slider LED 1 \def CYBSP_LED_SLD1 + */ +#endif +#ifdef CYBSP_LED_SLD2 +/** Slider LED 2 \def CYBSP_LED_SLD2 + */ +#endif +#ifdef CYBSP_LED_SLD3 +/** Slider LED 3 \def CYBSP_LED_SLD3 + */ +#endif +#ifdef CYBSP_LED_SLD4 +/** Slider LED 4 \def CYBSP_LED_SLD4 + */ +#endif +#ifdef CYBSP_LED_SLD5 +/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5 + */ +#endif +#ifdef CYBSP_LED_BTN0 +/** Button LED 0 \def CYBSP_LED_BTN0 + */ +#endif +#ifdef CYBSP_LED_BTN1 +/** Button LED 1 \def CYBSP_LED_BTN1 + */ +#endif +#ifdef CYBSP_LED_BTN2 +/** Button LED 2 \def CYBSP_LED_BTN2 + */ +#endif + +/** \} group_bsp_pins_led */ +#endif // defined(CYBSP_USER_LED) + +#if defined(CYBSP_USER_BTN) +/** + * \addtogroup group_bsp_pins_btn Button Pins + * \{ + * Pins connected to user buttons on the board. + */ + +#ifdef CYBSP_SW1 +/** Switch 1 \def CYBSP_SW1 + */ +#endif +#ifdef CYBSP_SW2 +/** Switch 2 \def CYBSP_SW2 + */ +#endif +#ifdef CYBSP_SW3 +/** Switch 3 \def CYBSP_SW3 + */ +#endif +#ifdef CYBSP_SW4 +/** Switch 4 \def CYBSP_SW4 + */ +#endif +#ifdef CYBSP_USER_BTN +/** User Button 1 \def CYBSP_USER_BTN + */ +#endif +#ifdef CYBSP_USER_BTN1 +/** User Button 1 \def CYBSP_USER_BTN1 + */ +#endif +#ifdef CYBSP_USER_BTN2 +/** User Button 2 \def CYBSP_USER_BTN2 + */ +#endif +#ifdef CYBSP_POTENTIOMETER_INPUT +/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT + */ +#endif + +/** \} group_bsp_pins_btn */ +#endif // defined(CYBSP_USER_BTN) + +#if defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) +/** + * \addtogroup group_bsp_pins_comm Communication Pins + * \{ + * Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...) + */ + +#ifdef CYBSP_DEBUG_UART_RX +/** Pin: UART RX \def CYBSP_DEBUG_UART_RX + */ +#endif +#ifdef CYBSP_DEBUG_UART_TX +/** Pin: UART TX \def CYBSP_DEBUG_UART_TX + */ +#endif +#ifdef CYBSP_I2C_SCL +/** Pin: I2C SCL \def CYBSP_I2C_SCL + */ +#endif +#ifdef CYBSP_I2C_SDA +/** Pin: I2C SDA \def CYBSP_I2C_SDA + */ +#endif +#ifdef CYBSP_SWDIO +/** Pin: SWDIO \def CYBSP_SWDIO + */ +#endif +#ifdef CYBSP_SWDCK +/** Pin: SWDCK \def CYBSP_SWDCK + */ +#endif +#ifdef CYBSP_SPI_MOSI +/** Pin: SPI MOSI \def CYBSP_SPI_MOSI + */ +#endif +#ifdef CYBSP_SPI_MISO +/** Pin: SPI MISO \def CYBSP_SPI_MISO + */ +#endif +#ifdef CYBSP_SPI_CLK +/** Pin: SPI CLK \def CYBSP_SPI_CLK + */ +#endif +#ifdef CYBSP_SPI_CS +/** Pin: SPI CS \def CYBSP_SPI_CS + */ +#endif +#ifdef CYBSP_SWO +/** Pin: SWO \def CYBSP_SWO + */ +#endif +#ifdef CYBSP_QSPI_SS +/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS + */ +#endif +#ifdef CYBSP_QSPI_D3 +/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3 + */ +#endif +#ifdef CYBSP_QSPI_D2 +/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2 + */ +#endif +#ifdef CYBSP_QSPI_D1 +/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1 + */ +#endif +#ifdef CYBSP_QSPI_D0 +/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0 + */ +#endif +#ifdef CYBSP_QSPI_SCK +/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D0 +/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D1 +/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D2 +/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_D3 +/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3 + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CMD +/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD + */ +#endif +#ifdef CYBSP_WIFI_SDIO_CLK +/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK + */ +#endif +#ifdef CYBSP_WIFI_WL_REG_ON +/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON + */ +#endif +#ifdef CYBSP_WIFI_HOST_WAKE +/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE + */ + +/** WiFi host-wake GPIO drive mode */ +#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) +/** WiFi host-wake IRQ event */ +#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) +#endif +#ifdef CYBSP_BT_UART_RX +/** Pin: BT UART RX \def CYBSP_BT_UART_RX + */ +#endif +#ifdef CYBSP_BT_UART_TX +/** Pin: BT UART TX \def CYBSP_BT_UART_TX + */ +#endif +#ifdef CYBSP_BT_UART_RTS +/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS + */ +#endif +#ifdef CYBSP_BT_UART_CTS +/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS + */ +#endif +#ifdef CYBSP_BT_POWER +/** Pin: BT Power \def CYBSP_BT_POWER + */ +#endif +#ifdef CYBSP_BT_HOST_WAKE +/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE + */ +/** BT host-wake GPIO drive mode */ +#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE) +/** BT host wake IRQ event */ +#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL) +#endif +#ifdef CYBSP_BT_DEVICE_WAKE +/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE + */ +/** BT device wakeup GPIO drive mode */ +#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG) +/** BT device wakeup polarity */ +#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u) +#endif +#ifdef CYBSP_PDM_CLK +/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK + */ +#endif +#ifdef CYBSP_PDM_DATA +/** Pin PDM PCM DATA \def CYBSP_PDM_DATA + */ +#endif +#ifdef CYBSP_I2S_MCLK +/** Pin: I2S MCLK \def CYBSP_I2S_MCLK + */ +#endif +#ifdef CYBSP_I2S_TX_SCK +/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK + */ +#endif +#ifdef CYBSP_I2S_TX_WS +/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS + */ +#endif +#ifdef CYBSP_I2S_TX_DATA +/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA + */ +#endif +#ifdef CYBSP_I2S_RX_SCK +/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK + */ +#endif +#ifdef CYBSP_I2S_RX_WS +/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS + */ +#endif +#ifdef CYBSP_I2S_RX_DATA +/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA + */ +#endif +#ifdef CYBSP_DEBUG_UART_RTS +/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS + */ +#endif +#ifdef CYBSP_DEBUG_UART_CTS +/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS + */ +#endif +#ifdef CYBSP_UART_RX +/** Pin: UART RX \def CYBSP_UART_RX + */ +#endif +#ifdef CYBSP_UART_TX +/** Pin: UART TX \def CYBSP_UART_TX + */ +#endif +#ifdef CYBSP_TDO_SWO +/** Pin: \def CYBSP_TDO_SWO + */ +#endif +#ifdef CYBSP_TMS_SWDIO +/** Pin: \def CYBSP_TMS_SWDIO + */ +#endif +#ifdef CYBSP_SWCLK +/** Pin: \def CYBSP_SWCLK + */ +#endif + +/** \} group_bsp_pins_comm */ +#endif // defined(CYBSP_DEBUG_UART_RX) || defined(CYBSP_SWDIO) + +#if defined(CYBSP_A0) +/** + * \addtogroup group_bsp_pins_arduino Arduino Header Pins + * \{ + * Pins mapped to the Arduino header on the board. + */ + +#ifdef CYBSP_A0 +/** Arduino A0 \def CYBSP_A0 + */ +#endif +#ifdef CYBSP_A1 +/** Arduino A1 \def CYBSP_A1 + */ +#endif +#ifdef CYBSP_A2 +/** Arduino A2 \def CYBSP_A2 + */ +#endif +#ifdef CYBSP_A3 +/** Arduino A3 \def CYBSP_A3 + */ +#endif +#ifdef CYBSP_A4 +/** Arduino A4 \def CYBSP_A4 + */ +#endif +#ifdef CYBSP_A5 +/** Arduino A5 \def CYBSP_A5 + */ +#endif +#ifdef CYBSP_D0 +/** Arduino D0 \def CYBSP_D0 + */ +#endif +#ifdef CYBSP_D1 +/** Arduino D1 \def CYBSP_D1 + */ +#endif +#ifdef CYBSP_D2 +/** Arduino D2 \def CYBSP_D2 + */ +#endif +#ifdef CYBSP_D3 +/** Arduino D3 \def CYBSP_D3 + */ +#endif +#ifdef CYBSP_D4 +/** Arduino D4 \def CYBSP_D4 + */ +#endif +#ifdef CYBSP_D5 +/** Arduino D5 \def CYBSP_D5 + */ +#endif +#ifdef CYBSP_D6 +/** Arduino D6 \def CYBSP_D6 + */ +#endif +#ifdef CYBSP_D7 +/** Arduino D7 \def CYBSP_D7 + */ +#endif +#ifdef CYBSP_D8 +/** Arduino D8 \def CYBSP_D8 + */ +#endif +#ifdef CYBSP_D9 +/** Arduino D9 \def CYBSP_D9 + */ +#endif +#ifdef CYBSP_D10 +/** Arduino D10 \def CYBSP_D10 + */ +#endif +#ifdef CYBSP_D11 +/** Arduino D11 \def CYBSP_D11 + */ +#endif +#ifdef CYBSP_D12 +/** Arduino D12 \def CYBSP_D12 + */ +#endif +#ifdef CYBSP_D13 +/** Arduino D13 \def CYBSP_D13 + */ +#endif +#ifdef CYBSP_D14 +/** Arduino D14 \def CYBSP_D14 + */ +#endif +#ifdef CYBSP_D15 +/** Arduino D15 \def CYBSP_D15 + */ +#endif + +/** \} group_bsp_pins_arduino */ +#endif // defined(CYBSP_A0) + +#if defined(CYBSP_J2_1) +/** + * \addtogroup group_bsp_pins_j2 J2 Header Pins + * \{ + * Pins mapped to the J2 header on the board. + */ + +#ifdef CYBSP_J2_1 +/** Cypress J2 Header pin 1 \def CYBSP_J2_1 + */ +#endif +#ifdef CYBSP_J2_2 +/** Cypress J2 Header pin 2 \def CYBSP_J2_2 + */ +#endif +#ifdef CYBSP_J2_3 +/** Cypress J2 Header pin 3 \def CYBSP_J2_3 + */ +#endif +#ifdef CYBSP_J2_4 +/** Cypress J2 Header pin 4 \def CYBSP_J2_4 + */ +#endif +#ifdef CYBSP_J2_5 +/** Cypress J2 Header pin 5 \def CYBSP_J2_5 + */ +#endif +#ifdef CYBSP_J2_7 +/** Cypress J2 Header pin 7 \def CYBSP_J2_7 + */ +#endif +#ifdef CYBSP_J2_8 +/** Cypress J2 Header pin 8 \def CYBSP_J2_8 + */ +#endif +#ifdef CYBSP_J2_9 +/** Cypress J2 Header pin 9 \def CYBSP_J2_9 + */ +#endif +#ifdef CYBSP_J2_10 +/** Cypress J2 Header pin 10 \def CYBSP_J2_10 + */ +#endif +#ifdef CYBSP_J2_11 +/** Cypress J2 Header pin 11 \def CYBSP_J2_11 + */ +#endif +#ifdef CYBSP_J2_12 +/** Cypress J2 Header pin 12 \def CYBSP_J2_12 + */ +#endif +#ifdef CYBSP_J2_13 +/** Cypress J2 Header pin 13 \def CYBSP_J2_13 + */ +#endif +#ifdef CYBSP_J2_15 +/** Cypress J2 Header pin 15 \def CYBSP_J2_15 + */ +#endif +#ifdef CYBSP_J2_16 +/** Cypress J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_16 +/** Cypress J2 Header pin 16 \def CYBSP_J2_16 + */ +#endif +#ifdef CYBSP_J2_6 +/** Cypress J2 Header pin 6 \def CYBSP_J2_6 + */ +#endif +#ifdef CYBSP_J2_17 +/** Cypress J2 Header pin 17 \def CYBSP_J2_17 + */ +#endif +#ifdef CYBSP_J2_18 +/** Cypress J2 Header pin 18 \def CYBSP_J2_18 + */ +#endif +#ifdef CYBSP_J2_19 +/** Cypress J2 Header pin 19 \def CYBSP_J2_19 + */ +#endif +#ifdef CYBSP_J2_20 +/** Cypress J2 Header pin 20 \def CYBSP_J2_20 + */ +#endif +#ifdef CYBSP_J2_14 +/** Cypress J2 Header pin 14 \def CYBSP_J2_14 + */ +#endif + +/** \} group_bsp_pins_j2 */ +#endif // defined(CYBSP_J2_1) + +#if defined(CYBSP_J6_1) +/** + * \addtogroup group_bsp_pins_j6 J6 Header Pins + * \{ + * Pins mapped to the J6 header on the board. + */ + +#ifdef CYBSP_J6_1 +/** Cypress J6 Header pin 1 \def CYBSP_J6_1 + */ +#endif +#ifdef CYBSP_J6_2 +/** Cypress J6 Header pin 2 \def CYBSP_J6_2 + */ +#endif +#ifdef CYBSP_J6_3 +/** Cypress J6 Header pin 3 \def CYBSP_J6_3 + */ +#endif +#ifdef CYBSP_J6_4 +/** Cypress J6 Header pin 4 \def CYBSP_J6_4 + */ +#endif +#ifdef CYBSP_J6_5 +/** Cypress J6 Header pin 5 \def CYBSP_J6_5 + */ +#endif +#ifdef CYBSP_J6_6 +/** Cypress J6 Header pin 6 \def CYBSP_J6_6 + */ +#endif +#ifdef CYBSP_J6_7 +/** Cypress J6 Header pin 7 \def CYBSP_J6_7 + */ +#endif +#ifdef CYBSP_J6_8 +/** Cypress J6 Header pin 8 \def CYBSP_J6_8 + */ +#endif +#ifdef CYBSP_J6_9 +/** Cypress J6 Header pin 9 \def CYBSP_J6_9 + */ +#endif +#ifdef CYBSP_J6_10 +/** Cypress J6 Header pin 10 \def CYBSP_J6_10 + */ +#endif +#ifdef CYBSP_J6_11 +/** Cypress J6 Header pin 11 \def CYBSP_J6_11 + */ +#endif +#ifdef CYBSP_J6_12 +/** Cypress J6 Header pin 12 \def CYBSP_J6_12 + */ +#endif +#ifdef CYBSP_J6_13 +/** Cypress J6 Header pin 13 \def CYBSP_J6_13 + */ +#endif +#ifdef CYBSP_J6_14 +/** Cypress J6 Header pin 14 \def CYBSP_J6_14 + */ +#endif +#ifdef CYBSP_J6_15 +/** Cypress J6 Header pin 15 \def CYBSP_J6_15 + */ +#endif +#ifdef CYBSP_J6_16 +/** Cypress J6 Header pin 16 \def CYBSP_J6_16 + */ +#endif + +/** \} group_bsp_pins_j6 */ +#endif // defined(CYBSP_J6_1) + +#if defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) +/** + * \addtogroup group_bsp_pins_capsense Capsense + * \{ + * Pins connected to CapSense sensors on the board. + */ + +#ifdef CYBSP_CSD_TX +/** Pin: CapSesnse TX \def CYBSP_CSD_TX + */ +#endif +#ifdef CYBSP_CINA +/** Pin: CapSesnse CINA \def CYBSP_CINA + */ +#endif +#ifdef CYBSP_CINTA +/** Pin: CapSesnse CINTA \def CYBSP_CINTA + */ +#endif +#ifdef CYBSP_CINB +/** Pin: CapSesnse CINB \def CYBSP_CINB + */ +#endif +#ifdef CYBSP_CINTB +/** Pin: CapSesnse CINTB \def CYBSP_CINTB + */ +#endif +#ifdef CYBSP_CMOD +/** Pin: CapSesnse CMOD \def CYBSP_CMOD + */ +#endif +#ifdef CYBSP_CSD_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0 + */ +#endif +#ifdef CYBSP_CSD_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1 + */ +#endif +#ifdef CYBSP_CSD_SLD0 +/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0 + */ +#endif +#ifdef CYBSP_CSD_SLD1 +/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1 + */ +#endif +#ifdef CYBSP_CSD_SLD2 +/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2 + */ +#endif +#ifdef CYBSP_CSD_SLD3 +/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3 + */ +#endif +#ifdef CYBSP_CSD_SLD4 +/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD4 + */ +#endif +#ifdef CYBSP_CSD_SLD5 +/** Pin: CapSesnse Slider 5 \def CYBSP_CSD_SLD5 + */ +#endif +#ifdef CYBSP_CSX_BTN_TX +/** Pin: CapSesnse Button TX \def CYBSP_CSX_BTN_TX + */ +#endif +#ifdef CYBSP_CSX_BTN0 +/** Pin: CapSesnse Button 0 \def CYBSP_CSX_BTN0 + */ +#endif +#ifdef CYBSP_CSX_BTN1 +/** Pin: CapSesnse Button 1 \def CYBSP_CSX_BTN1 + */ +#endif +#ifdef CYBSP_CSX_BTN2 +/** Pin: CapSesnse Button 2 \def CYBSP_CSX_BTN2 + */ +#endif + +/** \} group_bsp_pins_capsense */ +#endif // defined(CYBSP_CMOD) || defined(CYBSP_CINA) || defined(CYBSP_CINTA) + +#if defined(CYBSP_WCO_IN) +/** + * \addtogroup group_bsp_pins_wco WCO + * \{ + * Pins connected to the WCO on the board. + */ +#ifdef CYBSP_WCO_IN +/** Pin: WCO input \def CYBSP_WCO_IN + */ +#endif +#ifdef CYBSP_WCO_OUT +/** Pin: WCO output \def CYBSP_WCO_OUT + */ +#endif + +/** \} group_bsp_pins_wco */ +#endif // defined(CYBSP_WCO_IN) + +/** \} group_bsp_pins */ + +#if defined(__cplusplus) +} +#endif diff --git a/cybsp_types.h b/cybsp_types.h index 8a5ecfc..4f704a2 100644 --- a/cybsp_types.h +++ b/cybsp_types.h @@ -1,38 +1,34 @@ -/***************************************************************************//** -* \copyright -* Copyright 2018-2020 Cypress Semiconductor Corporation -* SPDX-License-Identifier: Apache-2.0 -* -* Licensed under the Apache License, Version 2.0 (the "License"); -* you may not use this file except in compliance with the License. -* You may obtain a copy of the License at -* -* http://www.apache.org/licenses/LICENSE-2.0 -* -* Unless required by applicable law or agreed to in writing, software -* distributed under the License is distributed on an "AS IS" BASIS, -* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -* See the License for the specific language governing permissions and -* limitations under the License. -*******************************************************************************/ +/***********************************************************************************************//** + * \copyright + * Copyright 2018-2021 Cypress Semiconductor Corporation + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + **************************************************************************************************/ #pragma once -#if defined(CY_USING_HAL) -#include "cyhal_pin_package.h" -#endif -#if defined(COMPONENT_BSP_DESIGN_MODUS) || defined(COMPONENT_CUSTOM_DESIGN_MODUS) -#include "cycfg.h" -#endif +#include "cybsp_doc.h" #if defined(__cplusplus) extern "C" { #endif /** -* \addtogroup group_bsp_pin_state Pin States -* \{ -*/ + * \addtogroup group_bsp_pin_state Pin States + * \{ + * Macros to abstract out whether the LEDs & Buttons are wired high or active low. + */ /** Pin state for the LED on. */ #ifndef CYBSP_LED_STATE_ON #define CYBSP_LED_STATE_ON (0U) @@ -51,759 +47,6 @@ extern "C" { #endif /** \} group_bsp_pin_state */ -/** -* \addtogroup group_bsp_pins Pin Mappings -* \{ -*/ - -/** -* \addtogroup group_bsp_pins_led LED Pins -* \{ -*/ - -#ifdef CYBSP_LED_RGB_RED -/** RGB LED - Red \def CYBSP_LED_RGB_RED -*/ -#endif -#ifdef CYBSP_LED_RGB_GREEN -/** RGB LED - Green \def CYBSP_LED_RGB_GREEN -*/ -#endif -#ifdef CYBSP_LED_RGB_BLUE -/** RGB LED - Blue \def CYBSP_LED_RGB_BLUE -*/ -#endif -#ifdef CYBSP_USER_LED -/** User LED \def CYBSP_USER_LED -*/ -#endif -#ifdef CYBSP_USER_LED1 -/** User LED1 \def CYBSP_USER_LED1 -*/ -#endif -#ifdef CYBSP_USER_LED2 -/** User LED2 \def CYBSP_USER_LED2 -*/ -#endif -#ifdef CYBSP_USER_LED3 -/** User LED3 \def CYBSP_USER_LED3 -*/ -#endif -#ifdef CYBSP_USER_LED4 -/** User LED 4 \def CYBSP_USER_LED4 -*/ -#endif -#ifdef CYBSP_USER_LED5 -/** User LED 5 \def CYBSP_USER_LED5 -*/ -#endif -#ifdef CYBSP_USER_LED6 -/** User LED 6 \def CYBSP_USER_LED6 -*/ -#endif -#ifdef CYBSP_USER_LED7 -/** User LED 7 \def CYBSP_USER_LED7 -*/ -#endif -#ifdef CYBSP_USER_LED8 -/** User LED 8 \def CYBSP_USER_LED8 -*/ -#endif -#ifdef CYBSP_USER_LED9 -/** User LED 9 \def CYBSP_USER_LED9 -*/ -#endif -#ifdef CYBSP_USER_LED10 -/** LED 10 \def CYBSP_USER_LED10 -*/ -#endif -#ifdef CYBSP_LED1 -/** LED 1 \def CYBSP_LED1 -*/ -#endif -#ifdef CYBSP_LED2 -/** LED 2 \def CYBSP_LED2 -*/ -#endif -#ifdef CYBSP_LED3 -/** LED 3 \def CYBSP_LED3 -*/ -#endif -#ifdef CYBSP_LED3_RGB_RED -/** LED 3: RGB LED - Red \def CYBSP_LED3_RGB_RED -*/ -#endif -#ifdef CYBSP_LED3_RGB_GREEN -/** LED 3: RGB LED - Green \def CYBSP_LED3_RGB_GREEN -*/ -#endif -#ifdef CYBSP_LED3_RGB_BLUE -/** LED 3: RGB LED - Blue \def CYBSP_LED3_RGB_BLUE -*/ -#endif -#ifdef CYBSP_LED4 -/** LED 4 \def CYBSP_LED4 -*/ -#endif -#ifdef CYBSP_LED5 -/** LED 5 \def CYBSP_LED5 -*/ -#endif -#ifdef CYBSP_LED6 -/** LED 6 \def CYBSP_LED6 -*/ -#endif -#ifdef CYBSP_LED7 -/** LED 7 \def CYBSP_LED7 -*/ -#endif -#ifdef CYBSP_LED8 -/** LED 8 \def CYBSP_LED8 -*/ -#endif -#ifdef CYBSP_LED9 -/** LED 9 \def CYBSP_LED9 -*/ -#endif -#ifdef CYBSP_LED10 -/** LED 10 \def CYBSP_LED10 -*/ -#endif -#ifdef CYBSP_LED11 -/** LED 11 \def CYBSP_LED11 -*/ -#endif -#ifdef CYBSP_LED12 -/** LED 12 \def CYBSP_LED12 -*/ -#endif -#ifdef CYBSP_LED13 -/** LED 13 \def CYBSP_LED13 -*/ -#endif -#ifdef CYBSP_LED_SLD0 -/** Slider LED 0 \def CYBSP_LED_SLD0 -*/ -#endif -#ifdef CYBSP_LED_SLD1 -/** Slider LED 1 \def CYBSP_LED_SLD1 -*/ -#endif -#ifdef CYBSP_LED_SLD2 -/** Slider LED 2 \def CYBSP_LED_SLD2 -*/ -#endif -#ifdef CYBSP_LED_SLD3 -/** Slider LED 3 \def CYBSP_LED_SLD3 -*/ -#endif -#ifdef CYBSP_LED_SLD4 -/** Slider LED 4 \def CYBSP_LED_SLD4 -*/ -#endif -#ifdef CYBSP_LED_SLD5 -/** LED 10; Slider LED 5 \def CYBSP_LED_SLD5 -*/ -#endif -#ifdef CYBSP_LED_BTN0 -/** Button LED 0 \def CYBSP_LED_BTN0 -*/ -#endif -#ifdef CYBSP_LED_BTN1 -/** Button LED 1 \def CYBSP_LED_BTN1 -*/ -#endif -#ifdef CYBSP_LED_BTN2 -/** Button LED 2 \def CYBSP_LED_BTN2 -*/ -#endif - -/** \} group_bsp_pins_led */ - -/** -* \addtogroup group_bsp_pins_btn Button Pins -* \{ -*/ - -#ifdef CYBSP_SW1 -/** Switch 1 \def CYBSP_SW1 -*/ -#endif -#ifdef CYBSP_SW2 -/** Switch 2 \def CYBSP_SW2 -*/ -#endif -#ifdef CYBSP_SW3 -/** Switch 3 \def CYBSP_SW3 -*/ -#endif -#ifdef CYBSP_SW4 -/** Switch 4 \def CYBSP_SW4 -*/ -#endif -#ifdef CYBSP_USER_BTN -/** User Button 1 \def CYBSP_USER_BTN -*/ -#endif -#ifdef CYBSP_USER_BTN1 -/** User Button 1 \def CYBSP_USER_BTN1 -*/ -#endif -#ifdef CYBSP_USER_BTN2 -/** User Button 2 \def CYBSP_USER_BTN2 -*/ -#endif -#ifdef CYBSP_POTENTIOMETER_INPUT -/** Potentiometer input \def CYBSP_POTENTIOMETER_INPUT -*/ -#endif - -/** \} group_bsp_pins_btn */ - -/** -* \addtogroup group_bsp_pins_comm Communication Pins -* \{ -*/ - -#ifdef CYBSP_DEBUG_UART_RX -/** Pin: UART RX \def CYBSP_DEBUG_UART_RX -*/ -#endif -#ifdef CYBSP_DEBUG_UART_TX -/** Pin: UART TX \def CYBSP_DEBUG_UART_TX -*/ -#endif -#ifdef CYBSP_I2C_SCL -/** Pin: I2C SCL \def CYBSP_I2C_SCL -*/ -#endif -#ifdef CYBSP_I2C_SDA -/** Pin: I2C SDA \def CYBSP_I2C_SDA -*/ -#endif -#ifdef CYBSP_SWDIO -/** Pin: SWDIO \def CYBSP_SWDIO -*/ -#endif -#ifdef CYBSP_SWDCK -/** Pin: SWDCK \def CYBSP_SWDCK -*/ -#endif -#ifdef CYBSP_SPI_MOSI -/** Pin: SPI MOSI \def CYBSP_SPI_MOSI -*/ -#endif -#ifdef CYBSP_SPI_MISO -/** Pin: SPI MISO \def CYBSP_SPI_MISO -*/ -#endif -#ifdef CYBSP_SPI_CLK -/** Pin: SPI CLK \def CYBSP_SPI_CLK -*/ -#endif -#ifdef CYBSP_SPI_CS -/** Pin: SPI CS \def CYBSP_SPI_CS -*/ -#endif -#ifdef CYBSP_SWO -/** Pin: SWO \def CYBSP_SWO -*/ -#endif -#ifdef CYBSP_QSPI_SS -/** Pin: QUAD SPI SS \def CYBSP_QSPI_SS -*/ -#endif -#ifdef CYBSP_QSPI_D3 -/** Pin: QUAD SPI D3 \def CYBSP_QSPI_D3 -*/ -#endif -#ifdef CYBSP_QSPI_D2 -/** Pin: QUAD SPI D2 \def CYBSP_QSPI_D2 -*/ -#endif -#ifdef CYBSP_QSPI_D1 -/** Pin: QUAD SPI D1 \def CYBSP_QSPI_D1 -*/ -#endif -#ifdef CYBSP_QSPI_D0 -/** Pin: QUAD SPI D0 \def CYBSP_QSPI_D0 -*/ -#endif -#ifdef CYBSP_QSPI_SCK -/** Pin: QUAD SPI SCK \def CYBSP_QSPI_SCK -*/ -#endif -#ifdef CYBSP_WIFI_SDIO_D0 -/** Pin: WIFI SDIO D0 \def CYBSP_WIFI_SDIO_D0 -*/ -#endif -#ifdef CYBSP_WIFI_SDIO_D1 -/** Pin: WIFI SDIO D1 \def CYBSP_WIFI_SDIO_D1 -*/ -#endif -#ifdef CYBSP_WIFI_SDIO_D2 -/** Pin: WIFI SDIO D2 \def CYBSP_WIFI_SDIO_D2 -*/ -#endif -#ifdef CYBSP_WIFI_SDIO_D3 -/** Pin: WIFI SDIO D3 \def CYBSP_WIFI_SDIO_D3 -*/ -#endif -#ifdef CYBSP_WIFI_SDIO_CMD -/** Pin: WIFI SDIO CMD \def CYBSP_WIFI_SDIO_CMD -*/ -#endif -#ifdef CYBSP_WIFI_SDIO_CLK -/** Pin: WIFI SDIO CLK \def CYBSP_WIFI_SDIO_CLK -*/ -#endif -#ifdef CYBSP_WIFI_WL_REG_ON -/** Pin: WIFI ON \def CYBSP_WIFI_WL_REG_ON -*/ -#endif -#ifdef CYBSP_WIFI_HOST_WAKE -/** Pin: WIFI Host Wakeup \def CYBSP_WIFI_HOST_WAKE -*/ - -/** WiFi host-wake GPIO drive mode */ -#define CYBSP_WIFI_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_ANALOG) -/** WiFi host-wake IRQ event */ -#define CYBSP_WIFI_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_RISE) -#endif -#ifdef CYBSP_BT_UART_RX -/** Pin: BT UART RX \def CYBSP_BT_UART_RX -*/ -#endif -#ifdef CYBSP_BT_UART_TX -/** Pin: BT UART TX \def CYBSP_BT_UART_TX -*/ -#endif -#ifdef CYBSP_BT_UART_RTS -/** Pin: BT UART RTS \def CYBSP_BT_UART_RTS -*/ -#endif -#ifdef CYBSP_BT_UART_CTS -/** Pin: BT UART CTS \def CYBSP_BT_UART_CTS -*/ -#endif -#ifdef CYBSP_BT_POWER -/** Pin: BT Power \def CYBSP_BT_POWER -*/ -#endif -#ifdef CYBSP_BT_HOST_WAKE -/** Pin: BT Host Wakeup \def CYBSP_BT_HOST_WAKE -*/ -/** BT host-wake GPIO drive mode */ -#define CYBSP_BT_HOST_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_NONE) -/** BT host wake IRQ event */ -#define CYBSP_BT_HOST_WAKE_IRQ_EVENT (CYHAL_GPIO_IRQ_FALL) -#endif -#ifdef CYBSP_BT_DEVICE_WAKE -/** Pin: BT Device Wakeup \def CYBSP_BT_DEVICE_WAKE -*/ -/** BT device wakeup GPIO drive mode */ -#define CYBSP_BT_DEVICE_WAKE_GPIO_DM (CYHAL_GPIO_DRIVE_STRONG) -/** BT device wakeup polarity */ -#define CYBSP_BT_DEVICE_WAKE_POLARITY (0u) -#endif -#ifdef CYBSP_PDM_CLK -/** Pin: PDM PCM CLK \def CYBSP_PDM_CLK -*/ -#endif -#ifdef CYBSP_PDM_DATA -/** Pin PDM PCM DATA \def CYBSP_PDM_DATA -*/ -#endif -#ifdef CYBSP_I2S_MCLK -/** Pin: I2S MCLK \def CYBSP_I2S_MCLK -*/ -#endif -#ifdef CYBSP_I2S_TX_SCK -/** Pin: I2S TX SCK \def CYBSP_I2S_TX_SCK -*/ -#endif -#ifdef CYBSP_I2S_TX_WS -/** Pin: I2S TX WS \def CYBSP_I2S_TX_WS -*/ -#endif -#ifdef CYBSP_I2S_TX_DATA -/** Pin: I2S TX DATA \def CYBSP_I2S_TX_DATA -*/ -#endif -#ifdef CYBSP_I2S_RX_SCK -/** Pin: I2S RX SCK \def CYBSP_I2S_RX_SCK -*/ -#endif -#ifdef CYBSP_I2S_RX_WS -/** Pin: I2S RX WS \def CYBSP_I2S_RX_WS -*/ -#endif -#ifdef CYBSP_I2S_RX_DATA -/** Pin: I2S RX DATA \def CYBSP_I2S_RX_DATA -*/ -#endif -#ifdef CYBSP_DEBUG_UART_RTS -/** Pin: UART RX \def CYBSP_DEBUG_UART_RTS -*/ -#endif -#ifdef CYBSP_DEBUG_UART_CTS -/** Pin: UART TX \def CYBSP_DEBUG_UART_CTS -*/ -#endif -#ifdef CYBSP_UART_RX -/** Pin: UART RX \def CYBSP_UART_RX -*/ -#endif -#ifdef CYBSP_UART_TX -/** Pin: UART TX \def CYBSP_UART_TX -*/ -#endif -#ifdef CYBSP_TDO_SWO -/** Pin: \def CYBSP_TDO_SWO -*/ -#endif -#ifdef CYBSP_TMS_SWDIO -/** Pin: \def CYBSP_TMS_SWDIO -*/ -#endif -#ifdef CYBSP_SWCLK -/** Pin: \def CYBSP_SWCLK -*/ -#endif - -/** \} group_bsp_pins_comm */ - - -/** -* \addtogroup group_bsp_pins_arduino Arduino Header Pins -* \{ -*/ - -#ifdef CYBSP_A0 -/** Arduino A0 \def CYBSP_A0 -*/ -#endif -#ifdef CYBSP_A1 -/** Arduino A1 \def CYBSP_A1 -*/ -#endif -#ifdef CYBSP_A2 -/** Arduino A2 \def CYBSP_A2 -*/ -#endif -#ifdef CYBSP_A3 -/** Arduino A3 \def CYBSP_A3 -*/ -#endif -#ifdef CYBSP_A4 -/** Arduino A4 \def CYBSP_A4 -*/ -#endif -#ifdef CYBSP_A5 -/** Arduino A5 \def CYBSP_A5 -*/ -#endif -#ifdef CYBSP_D0 -/** Arduino D0 \def CYBSP_D0 -*/ -#endif -#ifdef CYBSP_D1 -/** Arduino D1 \def CYBSP_D1 -*/ -#endif -#ifdef CYBSP_D2 -/** Arduino D2 \def CYBSP_D2 -*/ -#endif -#ifdef CYBSP_D3 -/** Arduino D3 \def CYBSP_D3 -*/ -#endif -#ifdef CYBSP_D4 -/** Arduino D4 \def CYBSP_D4 -*/ -#endif -#ifdef CYBSP_D5 -/** Arduino D5 \def CYBSP_D5 -*/ -#endif -#ifdef CYBSP_D6 -/** Arduino D6 \def CYBSP_D6 -*/ -#endif -#ifdef CYBSP_D7 -/** Arduino D7 \def CYBSP_D7 -*/ -#endif -#ifdef CYBSP_D8 -/** Arduino D8 \def CYBSP_D8 -*/ -#endif -#ifdef CYBSP_D9 -/** Arduino D9 \def CYBSP_D9 -*/ -#endif -#ifdef CYBSP_D10 -/** Arduino D10 \def CYBSP_D10 -*/ -#endif -#ifdef CYBSP_D11 -/** Arduino D11 \def CYBSP_D11 -*/ -#endif -#ifdef CYBSP_D12 -/** Arduino D12 \def CYBSP_D12 -*/ -#endif -#ifdef CYBSP_D13 -/** Arduino D13 \def CYBSP_D13 -*/ -#endif -#ifdef CYBSP_D14 -/** Arduino D14 \def CYBSP_D14 -*/ -#endif -#ifdef CYBSP_D15 -/** Arduino D15 \def CYBSP_D15 -*/ -#endif - -/** \} group_bsp_pins_arduino */ - -/** -* \addtogroup group_bsp_pins_j2 J2 Header Pins -* \{ -*/ - -#ifdef CYBSP_J2_1 -/** Cypress J2 Header pin 1 \def CYBSP_J2_1 -*/ -#endif -#ifdef CYBSP_J2_2 -/** Cypress J2 Header pin 2 \def CYBSP_J2_2 -*/ -#endif -#ifdef CYBSP_J2_3 -/** Cypress J2 Header pin 3 \def CYBSP_J2_3 -*/ -#endif -#ifdef CYBSP_J2_4 -/** Cypress J2 Header pin 4 \def CYBSP_J2_4 -*/ -#endif -#ifdef CYBSP_J2_5 -/** Cypress J2 Header pin 5 \def CYBSP_J2_5 -*/ -#endif -#ifdef CYBSP_J2_7 -/** Cypress J2 Header pin 7 \def CYBSP_J2_7 -*/ -#endif -#ifdef CYBSP_J2_8 -/** Cypress J2 Header pin 8 \def CYBSP_J2_8 -*/ -#endif -#ifdef CYBSP_J2_9 -/** Cypress J2 Header pin 9 \def CYBSP_J2_9 -*/ -#endif -#ifdef CYBSP_J2_10 -/** Cypress J2 Header pin 10 \def CYBSP_J2_10 -*/ -#endif -#ifdef CYBSP_J2_11 -/** Cypress J2 Header pin 11 \def CYBSP_J2_11 -*/ -#endif -#ifdef CYBSP_J2_12 -/** Cypress J2 Header pin 12 \def CYBSP_J2_12 -*/ -#endif -#ifdef CYBSP_J2_13 -/** Cypress J2 Header pin 13 \def CYBSP_J2_13 -*/ -#endif -#ifdef CYBSP_J2_15 -/** Cypress J2 Header pin 15 \def CYBSP_J2_15 -*/ -#endif -#ifdef CYBSP_J2_16 -/** Cypress J2 Header pin 16 \def CYBSP_J2_16 -*/ -#endif -#ifdef CYBSP_J2_16 -/** Cypress J2 Header pin 16 \def CYBSP_J2_16 -*/ -#endif -#ifdef CYBSP_J2_6 -/** Cypress J2 Header pin 6 \def CYBSP_J2_6 -*/ -#endif -#ifdef CYBSP_J2_17 -/** Cypress J2 Header pin 17 \def CYBSP_J2_17 -*/ -#endif -#ifdef CYBSP_J2_18 -/** Cypress J2 Header pin 18 \def CYBSP_J2_18 -*/ -#endif -#ifdef CYBSP_J2_19 -/** Cypress J2 Header pin 19 \def CYBSP_J2_19 -*/ -#endif -#ifdef CYBSP_J2_20 -/** Cypress J2 Header pin 20 \def CYBSP_J2_20 -*/ -#endif -#ifdef CYBSP_J2_14 -/** Cypress J2 Header pin 14 \def CYBSP_J2_14 -*/ -#endif - -/** \} group_bsp_pins_j2 */ - -/** -* \addtogroup group_bsp_pins_j6 J6 Header Pins -* \{ -*/ - -#ifdef CYBSP_J6_1 -/** Cypress J6 Header pin 1 \def CYBSP_J6_1 -*/ -#endif -#ifdef CYBSP_J6_2 -/** Cypress J6 Header pin 2 \def CYBSP_J6_2 -*/ -#endif -#ifdef CYBSP_J6_3 -/** Cypress J6 Header pin 3 \def CYBSP_J6_3 -*/ -#endif -#ifdef CYBSP_J6_4 -/** Cypress J6 Header pin 4 \def CYBSP_J6_4 -*/ -#endif -#ifdef CYBSP_J6_5 -/** Cypress J6 Header pin 5 \def CYBSP_J6_5 -*/ -#endif -#ifdef CYBSP_J6_6 -/** Cypress J6 Header pin 6 \def CYBSP_J6_6 -*/ -#endif -#ifdef CYBSP_J6_7 -/** Cypress J6 Header pin 7 \def CYBSP_J6_7 -*/ -#endif -#ifdef CYBSP_J6_8 -/** Cypress J6 Header pin 8 \def CYBSP_J6_8 -*/ -#endif -#ifdef CYBSP_J6_9 -/** Cypress J6 Header pin 9 \def CYBSP_J6_9 -*/ -#endif -#ifdef CYBSP_J6_10 -/** Cypress J6 Header pin 10 \def CYBSP_J6_10 -*/ -#endif -#ifdef CYBSP_J6_11 -/** Cypress J6 Header pin 11 \def CYBSP_J6_11 -*/ -#endif -#ifdef CYBSP_J6_12 -/** Cypress J6 Header pin 12 \def CYBSP_J6_12 -*/ -#endif -#ifdef CYBSP_J6_13 -/** Cypress J6 Header pin 13 \def CYBSP_J6_13 -*/ -#endif -#ifdef CYBSP_J6_14 -/** Cypress J6 Header pin 14 \def CYBSP_J6_14 -*/ -#endif -#ifdef CYBSP_J6_15 -/** Cypress J6 Header pin 15 \def CYBSP_J6_15 -*/ -#endif -#ifdef CYBSP_J6_16 -/** Cypress J6 Header pin 16 \def CYBSP_J6_16 -*/ -#endif - -/** \} group_bsp_pins_j6 */ - -/** -* \addtogroup group_bsp_pins_capsense Capsense -* \{ -*/ - -#ifdef CYBSP_CSD_TX -/** Pin: CapSesnse TX \def CYBSP_CSD_TX -*/ -#endif -#ifdef CYBSP_CINA -/** Pin: CapSesnse CINA \def CYBSP_CINA -*/ -#endif -#ifdef CYBSP_CINB -/** Pin: CapSesnse CINB \def CYBSP_CINB -*/ -#endif -#ifdef CYBSP_CMOD -/** Pin: CapSesnse CMOD \def CYBSP_CMOD -*/ -#endif -#ifdef CYBSP_CSD_BTN0 -/** Pin: CapSesnse Button 0 \def CYBSP_CSD_BTN0 -*/ -#endif -#ifdef CYBSP_CSD_BTN1 -/** Pin: CapSesnse Button 1 \def CYBSP_CSD_BTN1 -*/ -#endif -#ifdef CYBSP_CSD_SLD0 -/** Pin: CapSesnse Slider 0 \def CYBSP_CSD_SLD0 -*/ -#endif -#ifdef CYBSP_CSD_SLD1 -/** Pin: CapSesnse Slider 1 \def CYBSP_CSD_SLD1 -*/ -#endif -#ifdef CYBSP_CSD_SLD2 -/** Pin: CapSesnse Slider 2 \def CYBSP_CSD_SLD2 -*/ -#endif -#ifdef CYBSP_CSD_SLD3 -/** Pin: CapSesnse Slider 3 \def CYBSP_CSD_SLD3 -*/ -#endif -#ifdef CYBSP_CSD_SLD -/** Pin: CapSesnse Slider 4 \def CYBSP_CSD_SLD -*/ -#endif - -/** \} group_bsp_pins_capsense */ - -/** -* \addtogroup group_bsp_pins_wco WCO -* \{ -*/ -#ifdef CYBSP_WCO_IN -/** Pin: WCO input \def CYBSP_WCO_IN -*/ -#endif -#ifdef CYBSP_WCO_OUT -/** Pin: WCO output \def CYBSP_WCO_OUT -*/ -#endif - -/** \} group_bsp_pins_wco */ - - -/** \} group_bsp_pins */ - #if defined(__cplusplus) } #endif diff --git a/docs/html/group__group__bsp__bt.html b/docs/html/group__group__bsp__bt.html new file mode 100644 index 0000000..08f3adf --- /dev/null +++ b/docs/html/group__group__bsp__bt.html @@ -0,0 +1,240 @@ + + + + + + + + +CY8CPROTO-062-4343W BSP + + + + + + + + + + + + + + +
+
+ + + + + + + +
+
CY8CPROTO-062-4343W BSP
+
+
+ + + + + + + +
+
+ +
+
+
+ +
+ +
+
+ + +
+ +
+ +
+
+Macros | +Variables
+
+
Bluetooth Configuration Structure
+
+
+

General Description

+

Basic configuration structure for the Bluetooth interface on this board.

+
Copyright
Copyright 2020-2021 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0
+

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at 

http://www.apache.org/licenses/LICENSE-2.0
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+ + + + + + + + + + + + + + + + + +

+Macros

#define CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD   (115200)
 If not already defined, the baud rate to download data at. More...
 
#define CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE   (115200)
 If not already defined, the baud rate for general operation. More...
 
#define CYBSP_BT_PLATFORM_CFG_BITS_DATA   (8)
 If not already defined, the number of data bits to transmit. More...
 
#define CYBSP_BT_PLATFORM_CFG_BITS_STOP   (1)
 If not already defined, the number of stop bits to transmit. More...
 
#define CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES   (2048)
 If not already defined, the number of bytes to allocated for the task memory pool. More...
 
+ + + + +

+Variables

const cybt_platform_config_t cybsp_bt_platform_cfg
 Bluetooth platform configuration settings for the board. More...
 
+

Macro Definition Documentation

+ +

◆ CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD

+ +
+
+ + + + +
#define CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD   (115200)
+
+ +

If not already defined, the baud rate to download data at.

+ +
+
+ +

◆ CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE

+ +
+
+ + + + +
#define CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE   (115200)
+
+ +

If not already defined, the baud rate for general operation.

+ +
+
+ +

◆ CYBSP_BT_PLATFORM_CFG_BITS_DATA

+ +
+
+ + + + +
#define CYBSP_BT_PLATFORM_CFG_BITS_DATA   (8)
+
+ +

If not already defined, the number of data bits to transmit.

+ +
+
+ +

◆ CYBSP_BT_PLATFORM_CFG_BITS_STOP

+ +
+
+ + + + +
#define CYBSP_BT_PLATFORM_CFG_BITS_STOP   (1)
+
+ +

If not already defined, the number of stop bits to transmit.

+ +
+
+ +

◆ CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES

+ +
+
+ + + + +
#define CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES   (2048)
+
+ +

If not already defined, the number of bytes to allocated for the task memory pool.

+ +
+
+

Variable Documentation

+ +

◆ cybsp_bt_platform_cfg

+ +
+
+ + + + +
const cybt_platform_config_t cybsp_bt_platform_cfg
+
+ +

Bluetooth platform configuration settings for the board.

+
Copyright
Copyright 2020-2021 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0
+

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at 

http://www.apache.org/licenses/LICENSE-2.0
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+ +
+
+
+
+ + + diff --git a/docs/html/group__group__bsp__bt.js b/docs/html/group__group__bsp__bt.js new file mode 100644 index 0000000..6a2bcd2 --- /dev/null +++ b/docs/html/group__group__bsp__bt.js @@ -0,0 +1,9 @@ +var group__group__bsp__bt = +[ + [ "CYBSP_BT_PLATFORM_CFG_BAUD_DOWNLOAD", "group__group__bsp__bt.html#gae6fcfdb93cc3e51a046b0cacbc49b4c2", null ], + [ "CYBSP_BT_PLATFORM_CFG_BAUD_FEATURE", "group__group__bsp__bt.html#ga58d129cbeb845f8547f2140b8656ef88", null ], + [ "CYBSP_BT_PLATFORM_CFG_BITS_DATA", "group__group__bsp__bt.html#ga874350ee5d9bfcafa5ddbb771f0770f9", null ], + [ "CYBSP_BT_PLATFORM_CFG_BITS_STOP", "group__group__bsp__bt.html#gab7d4fad6bdee9bdff173acbbf1fbacee", null ], + [ "CYBSP_BT_PLATFORM_CFG_MEM_POOL_BYTES", "group__group__bsp__bt.html#ga668864091ac3c80319d2051f04b1bddf", null ], + [ "cybsp_bt_platform_cfg", "group__group__bsp__bt.html#gad2a1cd8a260feac884c816510f34c23e", null ] +]; \ No newline at end of file diff --git a/docs/html/group__group__bsp__macros.html b/docs/html/group__group__bsp__errors.html similarity index 95% rename from docs/html/group__group__bsp__macros.html rename to docs/html/group__group__bsp__errors.html index 7537863..6b786fc 100644 --- a/docs/html/group__group__bsp__macros.html +++ b/docs/html/group__group__bsp__errors.html @@ -67,7 +67,7 @@
@@ -89,15 +89,16 @@
Macros
-
Macros
+
Error Codes

General Description

+

Error codes specific to the board.

+#define 

Macros

-#define CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK   (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK   (CY_RSLT_CREATE(CY_RSLT_TYPE_ERROR, CY_RSLT_MODULE_ABSTRACTION_BSP, 0))
 Failed to configure sysclk power management callback.
 
diff --git a/docs/html/group__group__bsp__errors.js b/docs/html/group__group__bsp__errors.js new file mode 100644 index 0000000..9ee1e95 --- /dev/null +++ b/docs/html/group__group__bsp__errors.js @@ -0,0 +1,4 @@ +var group__group__bsp__errors = +[ + [ "CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK", "group__group__bsp__errors.html#gaee745bd3fccec6eb2df1e83fc4c9f775", null ] +]; \ No newline at end of file diff --git a/docs/html/group__group__bsp__functions.html b/docs/html/group__group__bsp__functions.html index 7954afc..2bb1c89 100644 --- a/docs/html/group__group__bsp__functions.html +++ b/docs/html/group__group__bsp__functions.html @@ -93,6 +93,7 @@

General Description

+

All functions exposed by the board.

@@ -118,7 +119,7 @@

Initialize all hardware on the board.

-
Returns
CY_RSLT_SUCCESS if the board is sucessfully initialized, if there is a problem initializing any hardware it returns an error code specific to the hardware module that had a problem.
+
Returns
CY_RSLT_SUCCESS if the board is successfully initialized, if there is a problem initializing any hardware it returns an error code specific to the hardware module that had a problem.
diff --git a/docs/html/group__group__bsp__macros.js b/docs/html/group__group__bsp__macros.js deleted file mode 100644 index 20431a2..0000000 --- a/docs/html/group__group__bsp__macros.js +++ /dev/null @@ -1,4 +0,0 @@ -var group__group__bsp__macros = -[ - [ "CYBSP_RSLT_ERR_SYSCLK_PM_CALLBACK", "group__group__bsp__macros.html#gaee745bd3fccec6eb2df1e83fc4c9f775", null ] -]; \ No newline at end of file diff --git a/docs/html/group__group__bsp__pin__state.html b/docs/html/group__group__bsp__pin__state.html index 6470adf..27d2a3a 100644 --- a/docs/html/group__group__bsp__pin__state.html +++ b/docs/html/group__group__bsp__pin__state.html @@ -93,7 +93,8 @@

General Description

-
Copyright
Copyright 2018-2020 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0
+

Macros to abstract out whether the LEDs & Buttons are wired high or active low.

+
Copyright
Copyright 2018-2021 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at 

http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

Functions

diff --git a/docs/html/group__group__bsp__pins.html b/docs/html/group__group__bsp__pins.html index ea97c46..e4f743a 100644 --- a/docs/html/group__group__bsp__pins.html +++ b/docs/html/group__group__bsp__pins.html @@ -93,24 +93,27 @@

General Description

+

Macro definitions for common peripheral pins on the board.

+
Copyright
Copyright 2018-2021 Cypress Semiconductor Corporation SPDX-License-Identifier: Apache-2.0
+

Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at 

http://www.apache.org/licenses/LICENSE-2.0
+

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

+ + - - - - - - + + +

API Reference

 LED Pins
 Pins connected to user LEDs on the board.
 
 Button Pins
 Pins connected to user buttons on the board.
 
 Communication Pins
 
 Arduino Header Pins
 
 J2 Header Pins
 
 J6 Header Pins
 Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)
 
 Capsense
 Pins connected to CapSense sensors on the board.
 
 WCO
 Pins connected to the WCO on the board.
 
diff --git a/docs/html/group__group__bsp__pins.js b/docs/html/group__group__bsp__pins.js index 851e6cf..92f28d6 100644 --- a/docs/html/group__group__bsp__pins.js +++ b/docs/html/group__group__bsp__pins.js @@ -3,9 +3,6 @@ var group__group__bsp__pins = [ "LED Pins", "group__group__bsp__pins__led.html", "group__group__bsp__pins__led" ], [ "Button Pins", "group__group__bsp__pins__btn.html", "group__group__bsp__pins__btn" ], [ "Communication Pins", "group__group__bsp__pins__comm.html", "group__group__bsp__pins__comm" ], - [ "Arduino Header Pins", "group__group__bsp__pins__arduino.html", null ], - [ "J2 Header Pins", "group__group__bsp__pins__j2.html", null ], - [ "J6 Header Pins", "group__group__bsp__pins__j6.html", null ], [ "Capsense", "group__group__bsp__pins__capsense.html", "group__group__bsp__pins__capsense" ], [ "WCO", "group__group__bsp__pins__wco.html", "group__group__bsp__pins__wco" ] ]; \ No newline at end of file diff --git a/docs/html/group__group__bsp__pins__arduino.html b/docs/html/group__group__bsp__pins__arduino.html deleted file mode 100644 index 17d3614..0000000 --- a/docs/html/group__group__bsp__pins__arduino.html +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - - - -CY8CPROTO-062-4343W BSP - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CY8CPROTO-062-4343W BSP
-
-
- - - - - - - -
-
- -
-
-
- -
- -
-
- - -
- -
- -
-
-
Arduino Header Pins
Pin Mappings
-
-
-
-
- - - diff --git a/docs/html/group__group__bsp__pins__btn.html b/docs/html/group__group__bsp__pins__btn.html index 39dda02..dd403ed 100644 --- a/docs/html/group__group__bsp__pins__btn.html +++ b/docs/html/group__group__bsp__pins__btn.html @@ -93,6 +93,7 @@

General Description

+

Pins connected to user buttons on the board.

diff --git a/docs/html/group__group__bsp__pins__capsense.html b/docs/html/group__group__bsp__pins__capsense.html index 048e14a..ea6689f 100644 --- a/docs/html/group__group__bsp__pins__capsense.html +++ b/docs/html/group__group__bsp__pins__capsense.html @@ -93,6 +93,7 @@

General Description

+

Pins connected to CapSense sensors on the board.

Macros

@@ -136,6 +137,10 @@ #define  + + +

Macros

CYBSP_CSD_SLD3   P8_6
 Pin: CapSesnse Slider 3.
 
+#define CYBSP_CSD_SLD4   P8_7
 Pin: CapSesnse Slider 4.
 
diff --git a/docs/html/group__group__bsp__pins__capsense.js b/docs/html/group__group__bsp__pins__capsense.js index 90301d5..3c86ae9 100644 --- a/docs/html/group__group__bsp__pins__capsense.js +++ b/docs/html/group__group__bsp__pins__capsense.js @@ -9,5 +9,6 @@ var group__group__bsp__pins__capsense = [ "CYBSP_CSD_SLD0", "group__group__bsp__pins__capsense.html#ga36e321396e39f0173bcc05314b63f72b", null ], [ "CYBSP_CSD_SLD1", "group__group__bsp__pins__capsense.html#gaf7f9017ffd06ebcf8ba709d858ba5411", null ], [ "CYBSP_CSD_SLD2", "group__group__bsp__pins__capsense.html#ga2ab777c7d3a69627e91a5c7efed6d320", null ], - [ "CYBSP_CSD_SLD3", "group__group__bsp__pins__capsense.html#gaeb41a9ba4c9ae8316bebe53f348cc2ed", null ] + [ "CYBSP_CSD_SLD3", "group__group__bsp__pins__capsense.html#gaeb41a9ba4c9ae8316bebe53f348cc2ed", null ], + [ "CYBSP_CSD_SLD4", "group__group__bsp__pins__capsense.html#ga0cfdc4c8461ae89960e23dfc9bc51d14", null ] ]; \ No newline at end of file diff --git a/docs/html/group__group__bsp__pins__comm.html b/docs/html/group__group__bsp__pins__comm.html index 3499cd1..96065d2 100644 --- a/docs/html/group__group__bsp__pins__comm.html +++ b/docs/html/group__group__bsp__pins__comm.html @@ -93,6 +93,7 @@

General Description

+

Pins associated with connections on the board for communication interfaces (UART/I2C/SPI/...)

diff --git a/docs/html/group__group__bsp__pins__j2.html b/docs/html/group__group__bsp__pins__j2.html deleted file mode 100644 index 688fe00..0000000 --- a/docs/html/group__group__bsp__pins__j2.html +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - - - -CY8CPROTO-062-4343W BSP - - - - - - - - - - - - - - -
-
-

Macros

- - - - - - -
-
CY8CPROTO-062-4343W BSP
-
-
- - - - - - - - -
- -
-
-
- -
- -
-
- - -
- -
- -
-
-
J2 Header Pins
Pin Mappings
-
-
-
-
- - - diff --git a/docs/html/group__group__bsp__pins__j6.html b/docs/html/group__group__bsp__pins__j6.html deleted file mode 100644 index 0da6f0b..0000000 --- a/docs/html/group__group__bsp__pins__j6.html +++ /dev/null @@ -1,106 +0,0 @@ - - - - - - - - -CY8CPROTO-062-4343W BSP - - - - - - - - - - - - - - -
-
- - - - - - - -
-
CY8CPROTO-062-4343W BSP
-
-
- - - - - - - -
-
- -
-
-
- -
- -
-
- - -
- -
- -
-
-
J6 Header Pins
Pin Mappings
-
-
-
-
- - - diff --git a/docs/html/group__group__bsp__pins__led.html b/docs/html/group__group__bsp__pins__led.html index 5832753..cc65ad9 100644 --- a/docs/html/group__group__bsp__pins__led.html +++ b/docs/html/group__group__bsp__pins__led.html @@ -93,6 +93,7 @@

General Description

+

Pins connected to user LEDs on the board.

diff --git a/docs/html/group__group__bsp__pins__wco.html b/docs/html/group__group__bsp__pins__wco.html index 7330e73..f35e60c 100644 --- a/docs/html/group__group__bsp__pins__wco.html +++ b/docs/html/group__group__bsp__pins__wco.html @@ -93,6 +93,7 @@

General Description

+

Pins connected to the WCO on the board.

Macros

diff --git a/docs/html/index.html b/docs/html/index.html index 82d5e20..f038a5d 100644 --- a/docs/html/index.html +++ b/docs/html/index.html @@ -113,12 +113,12 @@

Kit Contents:

BSP Configuration

The BSP has a few hooks that allow its behavior to be configured. Some of these items are enabled by default while others must be explicitly enabled. Items enabled by default are specified in the CY8CPROTO-062-4343W.mk file. The items that are enabled can be changed by creating a custom BSP or by editing the application makefile.

Components:

    -
  • Device specific HAL reference (e.g.: PSOC6HAL) - This component, enabled by default, pulls in the version of the HAL that is applicable for this board.
    • +
  • Device specific category reference (e.g.: CAT1) - This component, enabled by default, pulls in any device specific code for this board.
  • BSP_DESIGN_MODUS - This component, enabled by default, causes the Configurator generated code for this specific BSP to be included. This should not be used at the same time as the CUSTOM_DESIGN_MODUS component.
  • CUSTOM_DESIGN_MODUS - This component, disabled by default, causes the Configurator generated code from the application to be included. This assumes that the application provides configurator generated code. This should not be used at the same time as the BSP_DESIGN_MODUS component.

Defines:

    -
  • CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip.
    • +
  • CYBSP_WIFI_CAPABLE - This define, disabled by default, causes the BSP to initialize the interface to an onboard wireless chip if it has one.
  • CY_USING_HAL - This define, enabled by default, specifies that the HAL is intended to be used by the application. This will cause the BSP to include the applicable header file and to initialize the system level drivers.

Clock Configuration

@@ -139,6 +139,7 @@

Power Configuration

  • VDDA Voltage: 3300 mV
  • VDDD Voltage: 3300 mV
    • +

    See the BSP Setttings for additional board specific configuration settings.

    API Reference Manual

    The CY8CPROTO-062-4343W Board Support Package provides a set of APIs to configure, initialize and use the board resources.

    See the BSP API Reference Manual for the complete list of the provided interfaces.

    @@ -151,7 +152,7 @@

    More information

  • ModusToolbox
    • -

    © Cypress Semiconductor Corporation, 2019-2020.

    +

    © Cypress Semiconductor Corporation, 2019-2021.

    diff --git a/docs/html/modules.js b/docs/html/modules.js index 9f57f04..5060d18 100644 --- a/docs/html/modules.js +++ b/docs/html/modules.js @@ -1,7 +1,8 @@ var modules = [ - [ "Macros", "group__group__bsp__macros.html", "group__group__bsp__macros" ], - [ "Functions", "group__group__bsp__functions.html", "group__group__bsp__functions" ], + [ "Pin Mappings", "group__group__bsp__pins.html", "group__group__bsp__pins" ], [ "Pin States", "group__group__bsp__pin__state.html", "group__group__bsp__pin__state" ], - [ "Pin Mappings", "group__group__bsp__pins.html", "group__group__bsp__pins" ] + [ "Error Codes", "group__group__bsp__errors.html", "group__group__bsp__errors" ], + [ "Functions", "group__group__bsp__functions.html", "group__group__bsp__functions" ], + [ "Bluetooth Configuration Structure", "group__group__bsp__bt.html", "group__group__bsp__bt" ] ]; \ No newline at end of file diff --git a/docs/html/navtreedata.js b/docs/html/navtreedata.js index 7e7ca7c..dd2065d 100644 --- a/docs/html/navtreedata.js +++ b/docs/html/navtreedata.js @@ -24,7 +24,7 @@ for the JavaScript code in this file var NAVTREE = [ [ "CY8CPROTO-062-4343W BSP", "index.html", [ - [ "BSP Overview", "md_bsp_boards_mt_bsp_user_guide.html", null ], + [ "BSP Overview", "md_source_bsps_mt_bsp_user_guide.html", null ], [ "BSP Settings", "md_bsp_settings.html", null ], [ "BSP API Reference", "modules.html", "modules" ] ] ] @@ -32,7 +32,7 @@ var NAVTREE = var NAVTREEINDEX = [ -"group__group__bsp__functions.html" +"group__group__bsp__bt.html" ]; var SYNCONMSG = 'click to disable panel synchronisation'; diff --git a/docs/html/navtreeindex0.js b/docs/html/navtreeindex0.js index ad28400..50eb0fb 100644 --- a/docs/html/navtreeindex0.js +++ b/docs/html/navtreeindex0.js @@ -1,87 +1,92 @@ var NAVTREEINDEX0 = { -"group__group__bsp__functions.html":[2,1], -"group__group__bsp__functions.html#gab989986b285e127f78f61c29f6ccbbfa":[2,1,0], -"group__group__bsp__macros.html":[2,0], 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