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I came from high-level Scala/Java background and had no previous experience with Chisel, Verilog -- or in-depth understanding of processor architecture for that matter
Learning journey feedback
While it's done in admirable fashion, there are still some points that could be improved:
- It's targeted specifically to people with Verilog background. For those without it it would be beneficial to provide brief descriptions (or links, at least) to what LFSR16 or ALU2 are.
- Source code of many examples don't match exactly between repo and learning journey wiki
- There's little to no docs about "ready/valid interface" and
DecoupledIO, would be really helpful to have it though.