{"payload":{"header_redesign_enabled":false,"results":[{"id":"675834974","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"Iosaias/VLSI_Bootcamp","hl_trunc_description":null,"language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":675834974,"name":"VLSI_Bootcamp","owner_id":99456315,"owner_login":"Iosaias","updated_at":"2023-09-05T04:56:38.214Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public template","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":46,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AIosaias%252FVLSI_Bootcamp%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/Iosaias/VLSI_Bootcamp/star":{"post":"Mgk9srR80IwkR6FVCzyLiRCY2EnCa5LYMXCIk1ip9uDTiPeqWWV33T96kbppOBQyp9vJRl35z8lU5Z7sammrkA"},"/Iosaias/VLSI_Bootcamp/unstar":{"post":"rqbp7vdgF4kBTIjqb2a6DiGwpnYeXN2obJon1ybInFo3U8FzFVQ4U4GJtyM0d1MFxQmSXO3UALFTvzCFJljPKg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"5FlGEIj69OGfw_DmLORYovlAGC3pWftFtXmkb9mpueBFq9M3IrXD8-1nZQfD0hkA_pDxVmBmkfSEVS35TAYSfA"}}},"title":"Repository search results"}