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126 additions
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- +26 β2 src/cpu/cpu.cpp
- +17 β0 src/cpu/cpu.h
- +13 β0 src/device/cache_control.cpp
- +54 β0 src/device/cache_control.h
- +1 β1 src/device/serial.cpp
- +1 β1 src/state/state.cpp
- +11 β6 src/system.cpp
- +3 β0 src/system.h
@@ -0,0 +1,13 @@ | ||
#include "cache_control.h" | ||
#include "system.h" | ||
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CacheControl::CacheControl(System* sys) : sys(sys) { reset(); } | ||
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void CacheControl::reset() { cache._reg = 0; } | ||
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uint32_t CacheControl::read(uint32_t address) { return cache._reg; } | ||
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void CacheControl::write(uint32_t address, uint32_t data) { | ||
cache._reg = data; | ||
sys->cpu->icacheEnabled = cache.icacheEnable; | ||
} |
@@ -0,0 +1,54 @@ | ||
#pragma once | ||
#include "device.h" | ||
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struct System; | ||
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union CacheConfiguration { | ||
struct { | ||
uint32_t lock : 1; // lock, Tag Test Mode | ||
uint32_t inv : 1; // inv, Invalidate Mode | ||
uint32_t tag : 1; // tag, Tag Test Mode (used by BIOS when invalidating icache) | ||
uint32_t scratchpad : 1; // ram, use dcache as scratchpad (ignore valid bits) | ||
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uint32_t dcacheRefillSize : 2; // dblksz | ||
uint32_t : 1; | ||
uint32_t dcacheEnable : 1; // ds, used with bit3 to enable scratchpad | ||
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uint32_t icacheRefillSize : 2; // iblksz | ||
uint32_t is0 : 1; // is0, enable icache set 0 - cleared to 0 | ||
uint32_t icacheEnable : 1; // is1, enable icache set 1 - 1 to enable | ||
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uint32_t interruptPolarity : 1; // intp, not used, should be 0 | ||
uint32_t enableReadPriority : 1; // rdpri, loads operations will have priority over store | ||
uint32_t noWaitState : 1; // nopad | ||
uint32_t enableBusGrant : 1; // bgnt, should be 0 | ||
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uint32_t loadScheduling : 1; // ldsch | ||
uint32_t noStreaming : 1; // nostr, not used, should be 0 | ||
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uint32_t : 14; | ||
}; | ||
uint32_t _reg; | ||
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template <class Archive> | ||
void serialize(Archive& ar) { | ||
ar(_reg); | ||
} | ||
}; | ||
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class CacheControl { | ||
System* sys; | ||
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CacheConfiguration cache; | ||
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public: | ||
CacheControl(System* sys); | ||
void reset(); | ||
uint32_t read(uint32_t address); | ||
void write(uint32_t address, uint32_t data); | ||
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template <class Archive> | ||
void serialize(Archive& ar) { | ||
ar(cache); | ||
} | ||
}; |
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