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dma: refactoring, fixes for Channel 6/OTC
Tested against dma/otc-test
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@@ -1,7 +1,36 @@ | ||
#include "dma6_channel.h" | ||
#include <fmt/core.h> | ||
#include <magic_enum.hpp> | ||
#include "system.h" | ||
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namespace device::dma { | ||
uint32_t DMA6Channel::readDevice() { return 0xffffffff; } | ||
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DMA6Channel::DMA6Channel(Channel channel, System* sys) : DMAChannel(channel, sys) {} | ||
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void DMA6Channel::maskControl() { | ||
control._reg &= ~CHCR::MASK; | ||
control.direction = CHCR::Direction::toRam; | ||
control.syncMode = CHCR::SyncMode::block; | ||
control.memoryAddressStep = CHCR::MemoryAddressStep::backward; | ||
control.choppingEnable = false; | ||
control.choppingDmaWindowSize = 0; | ||
control.choppingCpuWindowSize = 0; | ||
control.unknown1 = false; | ||
} | ||
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void DMA6Channel::startTransfer() { | ||
control.startTrigger = CHCR::StartTrigger::clear; | ||
uint32_t addr = baseAddress.address; | ||
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if (verbose) { | ||
fmt::print("[DMA{}] {:<8} -> RAM @ 0x{:08x}, block, count: 0x{:04x}\n", (int)channel, magic_enum::enum_name(channel), addr, | ||
static_cast<int>(count.syncMode0.wordCount)); | ||
} | ||
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for (int i = count.syncMode0.wordCount - 1; i >= 0; i--, addr -= 4) { | ||
sys->writeMemory32(addr, (i == 0) ? 0xffffff : (addr - 4) & 0xffffff); | ||
} | ||
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irqFlag = true; | ||
control.enabled = CHCR::Enabled::completed; | ||
} | ||
} // namespace device::dma |
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