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Computer Architecture homework assignment - simple ALU for the MIPS architecture
Verilog Python Shell
branch: master

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python
.gitignore
README.mkd
adder.v
adderTest.png
adderTest.sh
adderTest.v
alu.v
aluTest.sh
aluTest.v
arithShiftRight.v
arithShiftRightTest.sh
arithShiftRightTest.v
multiply.v
multiplyTest.sh
multiplyTest.v
shiftLeft.v
shiftLeftTest.png
shiftLeftTest.sh
shiftLeftTest.v
shiftRight.v
shiftRightTest.sh
shiftRightTest.v
sign.v
signTest.sh
signTest.v
slt.v
sltTest.png
sltTest.sh
sltTest.v
sub.v
subTest.png
subTest.sh
subTest.v

README.mkd

ca-Lab2

in which it becomes apparent that Ian and Jimmy can quickly accomplish that which needs doing.

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