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  1. +0 −6 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/AsmParser/CMakeLists.txt
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  7. +0 −314 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0AsmPrinter.cpp
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  45. +0 −224 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/MCTargetDesc/Cpu0AsmBackend.cpp
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  47. +0 −245 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/MCTargetDesc/Cpu0ELFObjectWriter.cpp
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  58. +0 −6 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/AsmParser/CMakeLists.txt
  59. +0 −1,064 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/AsmParser/Cpu0AsmParser.cpp
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  64. +0 −314 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0AsmPrinter.cpp
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  66. +0 −49 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0CallingConv.td
  67. +0 −99 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0EmitGPRestore.cpp
  68. +0 −250 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0FrameLowering.cpp
  69. +0 −48 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0FrameLowering.h
  70. +0 −265 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0ISelDAGToDAG.cpp
  71. +0 −738 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0ISelLowering.cpp
  72. +0 −115 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0ISelLowering.h
  73. +0 −142 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0InstrFormats.td
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  79. +0 −44 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0MachineFunction.cpp
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  81. +0 −178 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0RegisterInfo.cpp
  82. +0 −58 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0RegisterInfo.h
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  85. +0 −23 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0SelectionDAGInfo.cpp
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  91. +0 −102 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Cpu0TargetObjectFile.cpp
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  93. +0 −15 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/Disassembler/CMakeLists.txt
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  102. +0 −224 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/MCTargetDesc/Cpu0AsmBackend.cpp
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  104. +0 −245 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/MCTargetDesc/Cpu0ELFObjectWriter.cpp
  105. +0 −107 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/2/Cpu0/MCTargetDesc/Cpu0FixupKinds.h
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  143. +0 −23 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/1/Cpu0/Cpu0SelectionDAGInfo.cpp
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  186. +0 −265 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0ISelDAGToDAG.cpp
  187. +0 −738 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0ISelLowering.cpp
  188. +0 −115 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0ISelLowering.h
  189. +0 −142 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0InstrFormats.td
  190. +0 −123 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0InstrInfo.cpp
  191. +0 −64 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0InstrInfo.h
  192. +0 −637 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0InstrInfo.td
  193. +0 −182 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0MCInstLower.cpp
  194. +0 −45 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0MCInstLower.h
  195. +0 −44 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0MachineFunction.cpp
  196. +0 −112 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0MachineFunction.h
  197. +0 −178 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0RegisterInfo.cpp
  198. +0 −58 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0RegisterInfo.h
  199. +0 −78 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0RegisterInfo.td
  200. +0 −41 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0Schedule.td
  201. +0 −23 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0SelectionDAGInfo.cpp
  202. +0 −31 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0SelectionDAGInfo.h
  203. +0 −50 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0Subtarget.cpp
  204. +0 −73 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0Subtarget.h
  205. +0 −115 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0TargetMachine.cpp
  206. +0 −92 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0TargetMachine.h
  207. +0 −102 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0TargetObjectFile.cpp
  208. +0 −41 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Cpu0TargetObjectFile.h
  209. +0 −15 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Disassembler/CMakeLists.txt
  210. +0 −243 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Disassembler/Cpu0Disassembler.cpp
  211. +0 −23 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/Disassembler/LLVMBuild.txt
  212. +0 −7 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/InstPrinter/CMakeLists.txt
  213. +0 −129 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/InstPrinter/Cpu0InstPrinter.cpp
  214. +0 −46 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/InstPrinter/Cpu0InstPrinter.h
  215. +0 −23 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/InstPrinter/LLVMBuild.txt
  216. +0 −56 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/LLVMBuild.txt
  217. +0 −10 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/CMakeLists.txt
  218. +0 −226 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0AsmBackend.cpp
  219. +0 −183 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0BaseInfo.h
  220. +0 −245 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0ELFObjectWriter.cpp
  221. +0 −111 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0FixupKinds.h
  222. +0 −41 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0MCAsmInfo.cpp
  223. +0 −31 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0MCAsmInfo.h
  224. +0 −266 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/11/2/Cpu0/MCTargetDesc/Cpu0MCCodeEmitter.cpp
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6 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/AsmParser/CMakeLists.txt
@@ -1,6 +0,0 @@
-include_directories( ${CMAKE_CURRENT_BINARY_DIR}/.. ${CMAKE_CURRENT_SOURCE_DIR}/.. )
-add_llvm_library(LLVMCpu0AsmParser
- Cpu0AsmParser.cpp
- )
-
-add_dependencies(LLVMCpu0AsmParser Cpu0CommonTableGen)
View
1,064 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/AsmParser/Cpu0AsmParser.cpp
@@ -1,1064 +0,0 @@
-//===-- Cpu0AsmParser.cpp - Parse Cpu0 assembly to MCInst instructions ----===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-
-#include "MCTargetDesc/Cpu0MCTargetDesc.h"
-#include "Cpu0RegisterInfo.h"
-#include "llvm/ADT/StringSwitch.h"
-#include "llvm/MC/MCContext.h"
-#include "llvm/MC/MCExpr.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCSubtargetInfo.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/MC/MCParser/MCAsmLexer.h"
-#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
-#include "llvm/MC/MCTargetAsmParser.h"
-#include "llvm/Support/TargetRegistry.h"
-
-using namespace llvm;
-
-namespace {
-class Cpu0AssemblerOptions {
-public:
- Cpu0AssemblerOptions():
- aTReg(1), reorder(true), macro(true) {
- }
-
- bool isReorder() {return reorder;}
- void setReorder() {reorder = true;}
- void setNoreorder() {reorder = false;}
-
- bool isMacro() {return macro;}
- void setMacro() {macro = true;}
- void setNomacro() {macro = false;}
-
-private:
- unsigned aTReg;
- bool reorder;
- bool macro;
-};
-}
-
-namespace {
-class Cpu0AsmParser : public MCTargetAsmParser {
- MCSubtargetInfo &STI;
- MCAsmParser &Parser;
- Cpu0AssemblerOptions Options;
-
-
-#define GET_ASSEMBLER_HEADER
-#include "Cpu0GenAsmMatcher.inc"
-
- bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- MCStreamer &Out, unsigned &ErrorInfo,
- bool MatchingInlineAsm);
-
- bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
-
- bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
- SMLoc NameLoc,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands);
-
- bool parseMathOperation(StringRef Name, SMLoc NameLoc,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands);
-
- bool ParseDirective(AsmToken DirectiveID);
-
- Cpu0AsmParser::OperandMatchResultTy
- parseMemOperand(SmallVectorImpl<MCParsedAsmOperand*>&);
-
- bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &,
- StringRef Mnemonic);
-
- int tryParseRegister(StringRef Mnemonic);
-
- bool tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- StringRef Mnemonic);
-
- bool needsExpansion(MCInst &Inst);
-
- void expandInstruction(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions);
- void expandLoadImm(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions);
- void expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions);
- void expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions);
- bool reportParseError(StringRef ErrorMsg);
-
- bool parseMemOffset(const MCExpr *&Res);
- bool parseRelocOperand(const MCExpr *&Res);
-
- bool parseDirectiveSet();
-
- bool parseSetAtDirective();
- bool parseSetNoAtDirective();
- bool parseSetMacroDirective();
- bool parseSetNoMacroDirective();
- bool parseSetReorderDirective();
- bool parseSetNoReorderDirective();
-
- MCSymbolRefExpr::VariantKind getVariantKind(StringRef Symbol);
-
- int matchRegisterName(StringRef Symbol);
-
- int matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic);
-
- unsigned getReg(int RC,int RegNo);
-
-public:
- Cpu0AsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
- : MCTargetAsmParser(), STI(sti), Parser(parser) {
- // Initialize the set of available features.
- setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
- }
-
- MCAsmParser &getParser() const { return Parser; }
- MCAsmLexer &getLexer() const { return Parser.getLexer(); }
-
-};
-}
-
-namespace {
-
-/// Cpu0Operand - Instances of this class represent a parsed Cpu0 machine
-/// instruction.
-class Cpu0Operand : public MCParsedAsmOperand {
-
- enum KindTy {
- k_CondCode,
- k_CoprocNum,
- k_Immediate,
- k_Memory,
- k_PostIndexRegister,
- k_Register,
- k_Token
- } Kind;
-
- Cpu0Operand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
-
- union {
- struct {
- const char *Data;
- unsigned Length;
- } Tok;
-
- struct {
- unsigned RegNum;
- } Reg;
-
- struct {
- const MCExpr *Val;
- } Imm;
-
- struct {
- unsigned Base;
- const MCExpr *Off;
- } Mem;
- };
-
- SMLoc StartLoc, EndLoc;
-
-public:
- void addRegOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- Inst.addOperand(MCOperand::CreateReg(getReg()));
- }
-
- void addExpr(MCInst &Inst, const MCExpr *Expr) const{
- // Add as immediate when possible. Null MCExpr = 0.
- if (Expr == 0)
- Inst.addOperand(MCOperand::CreateImm(0));
- else if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr))
- Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
- else
- Inst.addOperand(MCOperand::CreateExpr(Expr));
- }
-
- void addImmOperands(MCInst &Inst, unsigned N) const {
- assert(N == 1 && "Invalid number of operands!");
- const MCExpr *Expr = getImm();
- addExpr(Inst,Expr);
- }
-
- void addMemOperands(MCInst &Inst, unsigned N) const {
- assert(N == 2 && "Invalid number of operands!");
-
- Inst.addOperand(MCOperand::CreateReg(getMemBase()));
-
- const MCExpr *Expr = getMemOff();
- addExpr(Inst,Expr);
- }
-
- bool isReg() const { return Kind == k_Register; }
- bool isImm() const { return Kind == k_Immediate; }
- bool isToken() const { return Kind == k_Token; }
- bool isMem() const { return Kind == k_Memory; }
-
- StringRef getToken() const {
- assert(Kind == k_Token && "Invalid access!");
- return StringRef(Tok.Data, Tok.Length);
- }
-
- unsigned getReg() const {
- assert((Kind == k_Register) && "Invalid access!");
- return Reg.RegNum;
- }
-
- const MCExpr *getImm() const {
- assert((Kind == k_Immediate) && "Invalid access!");
- return Imm.Val;
- }
-
- unsigned getMemBase() const {
- assert((Kind == k_Memory) && "Invalid access!");
- return Mem.Base;
- }
-
- const MCExpr *getMemOff() const {
- assert((Kind == k_Memory) && "Invalid access!");
- return Mem.Off;
- }
-
- static Cpu0Operand *CreateToken(StringRef Str, SMLoc S) {
- Cpu0Operand *Op = new Cpu0Operand(k_Token);
- Op->Tok.Data = Str.data();
- Op->Tok.Length = Str.size();
- Op->StartLoc = S;
- Op->EndLoc = S;
- return Op;
- }
-
- static Cpu0Operand *CreateReg(unsigned RegNum, SMLoc S, SMLoc E) {
- Cpu0Operand *Op = new Cpu0Operand(k_Register);
- Op->Reg.RegNum = RegNum;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static Cpu0Operand *CreateImm(const MCExpr *Val, SMLoc S, SMLoc E) {
- Cpu0Operand *Op = new Cpu0Operand(k_Immediate);
- Op->Imm.Val = Val;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- static Cpu0Operand *CreateMem(unsigned Base, const MCExpr *Off,
- SMLoc S, SMLoc E) {
- Cpu0Operand *Op = new Cpu0Operand(k_Memory);
- Op->Mem.Base = Base;
- Op->Mem.Off = Off;
- Op->StartLoc = S;
- Op->EndLoc = E;
- return Op;
- }
-
- /// getStartLoc - Get the location of the first token of this operand.
- SMLoc getStartLoc() const { return StartLoc; }
- /// getEndLoc - Get the location of the last token of this operand.
- SMLoc getEndLoc() const { return EndLoc; }
-
- virtual void print(raw_ostream &OS) const {
- llvm_unreachable("unimplemented!");
- }
-};
-}
-
-bool Cpu0AsmParser::needsExpansion(MCInst &Inst) {
-
- switch(Inst.getOpcode()) {
- case Cpu0::LoadImm32Reg:
- case Cpu0::LoadAddr32Imm:
- case Cpu0::LoadAddr32Reg:
- return true;
- default:
- return false;
- }
-}
-
-void Cpu0AsmParser::expandInstruction(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions){
- switch(Inst.getOpcode()) {
- case Cpu0::LoadImm32Reg:
- return expandLoadImm(Inst, IDLoc, Instructions);
- case Cpu0::LoadAddr32Imm:
- return expandLoadAddressImm(Inst,IDLoc,Instructions);
- case Cpu0::LoadAddr32Reg:
- return expandLoadAddressReg(Inst,IDLoc,Instructions);
- }
-}
-
-void Cpu0AsmParser::expandLoadImm(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions){
- MCInst tmpInst;
- const MCOperand &ImmOp = Inst.getOperand(1);
- assert(ImmOp.isImm() && "expected immediate operand kind");
- const MCOperand &RegOp = Inst.getOperand(0);
- assert(RegOp.isReg() && "expected register operand kind");
-
- int ImmValue = ImmOp.getImm();
- tmpInst.setLoc(IDLoc);
- if ( -32768 <= ImmValue && ImmValue <= 32767) {
- // for -32768 <= j < 32767.
- // li d,j => addiu d,$zero,j
- tmpInst.setOpcode(Cpu0::ADDiu); //TODO:no ADDiu64 in td files?
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(
- MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
- Instructions.push_back(tmpInst);
- } else {
- // for any other value of j that is representable as a 32-bit integer.
- // li d,j => addiu d, $0, hi16(j)
- // shl d, d, 16
- // addiu at, $0, lo16(j)
- // or d, d, at
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::SHL);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateImm(16));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::AT));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0x0000ffff));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::OR);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::AT));
- tmpInst.setLoc(IDLoc);
- Instructions.push_back(tmpInst);
- }
-}
-
-void Cpu0AsmParser::expandLoadAddressReg(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions){
- MCInst tmpInst;
- const MCOperand &ImmOp = Inst.getOperand(2);
- assert(ImmOp.isImm() && "expected immediate operand kind");
- const MCOperand &SrcRegOp = Inst.getOperand(1);
- assert(SrcRegOp.isReg() && "expected register operand kind");
- const MCOperand &DstRegOp = Inst.getOperand(0);
- assert(DstRegOp.isReg() && "expected register operand kind");
- int ImmValue = ImmOp.getImm();
- if ( -32768 <= ImmValue && ImmValue <= 32767) {
- // for -32768 <= j < 32767.
- //la d,j(s) => addiu d,s,j
- tmpInst.setOpcode(Cpu0::ADDiu); //TODO:no ADDiu64 in td files?
- tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
- Instructions.push_back(tmpInst);
- } else {
- // for any other value of j that is representable as a 32-bit integer.
- // li d,j(s) => addiu d, $0, hi16(j)
- // shl d, d, 16
- // addiu at, $0, lo16(j)
- // or d, d, at
- // add d,d,s
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::SHL);
- tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateImm(16));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::AT));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0x0000ffff));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::OR);
- tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::AT));
- tmpInst.setLoc(IDLoc);
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::ADD);
- tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(DstRegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(SrcRegOp.getReg()));
- Instructions.push_back(tmpInst);
- }
-}
-
-void Cpu0AsmParser::expandLoadAddressImm(MCInst &Inst, SMLoc IDLoc,
- SmallVectorImpl<MCInst> &Instructions){
- MCInst tmpInst;
- const MCOperand &ImmOp = Inst.getOperand(1);
- assert(ImmOp.isImm() && "expected immediate operand kind");
- const MCOperand &RegOp = Inst.getOperand(0);
- assert(RegOp.isReg() && "expected register operand kind");
- int ImmValue = ImmOp.getImm();
- if ( -32768 <= ImmValue && ImmValue <= 32767) {
- // for -32768 <= j < 32767.
- //la d,j => addiu d,$zero,j
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(
- MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue));
- Instructions.push_back(tmpInst);
- } else {
- // for any other value of j that is representable as a 32-bit integer.
- // la d,j => addiu d, $0, hi16(j)
- // shl d, d, 16
- // addiu at, $0, lo16(j)
- // or d, d, at
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm((ImmValue & 0xffff0000) >> 16));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::SHL);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateImm(16));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::ADDiu);
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::AT));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::ZERO));
- tmpInst.addOperand(MCOperand::CreateImm(ImmValue & 0x0000ffff));
- Instructions.push_back(tmpInst);
- tmpInst.clear();
- tmpInst.setOpcode(Cpu0::OR);
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(RegOp.getReg()));
- tmpInst.addOperand(MCOperand::CreateReg(Cpu0::AT));
- tmpInst.setLoc(IDLoc);
- Instructions.push_back(tmpInst);
- }
-}
-
-bool Cpu0AsmParser::
-MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- MCStreamer &Out, unsigned &ErrorInfo,
- bool MatchingInlineAsm) {
- MCInst Inst;
- unsigned MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
- MatchingInlineAsm);
-
- switch (MatchResult) {
- default: break;
- case Match_Success: {
- if (needsExpansion(Inst)) {
- SmallVector<MCInst, 4> Instructions;
- expandInstruction(Inst, IDLoc, Instructions);
- for(unsigned i =0; i < Instructions.size(); i++){
- Out.EmitInstruction(Instructions[i]);
- }
- } else {
- Inst.setLoc(IDLoc);
- Out.EmitInstruction(Inst);
- }
- return false;
- }
- case Match_MissingFeature:
- Error(IDLoc, "instruction requires a CPU feature not currently enabled");
- return true;
- case Match_InvalidOperand: {
- SMLoc ErrorLoc = IDLoc;
- if (ErrorInfo != ~0U) {
- if (ErrorInfo >= Operands.size())
- return Error(IDLoc, "too few operands for instruction");
-
- ErrorLoc = ((Cpu0Operand*)Operands[ErrorInfo])->getStartLoc();
- if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
- }
-
- return Error(ErrorLoc, "invalid operand for instruction");
- }
- case Match_MnemonicFail:
- return Error(IDLoc, "invalid instruction");
- }
- return true;
-}
-
-int Cpu0AsmParser::matchRegisterName(StringRef Name) {
-
- int CC;
- CC = StringSwitch<unsigned>(Name)
- .Case("zero", Cpu0::ZERO)
- .Case("at", Cpu0::AT)
- .Case("v0", Cpu0::V0)
- .Case("v1", Cpu0::V1)
- .Case("a0", Cpu0::A0)
- .Case("a1", Cpu0::A1)
- .Case("t9", Cpu0::T9)
- .Case("s0", Cpu0::S0)
- .Case("s1", Cpu0::S1)
- .Case("s2", Cpu0::S2)
- .Case("gp", Cpu0::GP)
- .Case("fp", Cpu0::FP)
- .Case("sw", Cpu0::SW)
- .Case("sp", Cpu0::SP)
- .Case("lr", Cpu0::LR)
- .Case("pc", Cpu0::PC)
- .Default(-1);
-
- if (CC != -1)
- return CC;
-
- return -1;
-}
-
-unsigned Cpu0AsmParser::getReg(int RC,int RegNo) {
- return *(getContext().getRegisterInfo().getRegClass(RC).begin() + RegNo);
-}
-
-int Cpu0AsmParser::matchRegisterByNumber(unsigned RegNum, StringRef Mnemonic) {
- if (RegNum > 15)
- return -1;
-
- return getReg(Cpu0::CPURegsRegClassID, RegNum);
-}
-
-int Cpu0AsmParser::tryParseRegister(StringRef Mnemonic) {
- const AsmToken &Tok = Parser.getTok();
- int RegNum = -1;
-
- if (Tok.is(AsmToken::Identifier)) {
- std::string lowerCase = Tok.getString().lower();
- RegNum = matchRegisterName(lowerCase);
- } else if (Tok.is(AsmToken::Integer))
- RegNum = matchRegisterByNumber(static_cast<unsigned>(Tok.getIntVal()),
- Mnemonic.lower());
- else
- return RegNum; //error
- return RegNum;
-}
-
-bool Cpu0AsmParser::
- tryParseRegisterOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands,
- StringRef Mnemonic){
-
- SMLoc S = Parser.getTok().getLoc();
- int RegNo = -1;
-
- RegNo = tryParseRegister(Mnemonic);
- if (RegNo == -1)
- return true;
-
- Operands.push_back(Cpu0Operand::CreateReg(RegNo, S,
- Parser.getTok().getLoc()));
- Parser.Lex(); // Eat register token.
- return false;
-}
-
-bool Cpu0AsmParser::ParseOperand(SmallVectorImpl<MCParsedAsmOperand*>&Operands,
- StringRef Mnemonic) {
- // Check if the current operand has a custom associated parser, if so, try to
- // custom parse the operand, or fallback to the general approach.
- OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
- if (ResTy == MatchOperand_Success)
- return false;
- // If there wasn't a custom match, try the generic matcher below. Otherwise,
- // there was a match, but an error occurred, in which case, just return that
- // the operand parsing failed.
- if (ResTy == MatchOperand_ParseFail)
- return true;
-
- switch (getLexer().getKind()) {
- default:
- Error(Parser.getTok().getLoc(), "unexpected token in operand");
- return true;
- case AsmToken::Dollar: {
- // parse register
- SMLoc S = Parser.getTok().getLoc();
- Parser.Lex(); // Eat dollar token.
- // parse register operand
- if (!tryParseRegisterOperand(Operands, Mnemonic)) {
- if (getLexer().is(AsmToken::LParen)) {
- // check if it is indexed addressing operand
- Operands.push_back(Cpu0Operand::CreateToken("(", S));
- Parser.Lex(); // eat parenthesis
- if (getLexer().isNot(AsmToken::Dollar))
- return true;
-
- Parser.Lex(); // eat dollar
- if (tryParseRegisterOperand(Operands, Mnemonic))
- return true;
-
- if (!getLexer().is(AsmToken::RParen))
- return true;
-
- S = Parser.getTok().getLoc();
- Operands.push_back(Cpu0Operand::CreateToken(")", S));
- Parser.Lex();
- }
- return false;
- }
- // maybe it is a symbol reference
- StringRef Identifier;
- if (Parser.parseIdentifier(Identifier))
- return true;
-
- SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-
- MCSymbol *Sym = getContext().GetOrCreateSymbol("$" + Identifier);
-
- // Otherwise create a symbol ref.
- const MCExpr *Res = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
- getContext());
-
- Operands.push_back(Cpu0Operand::CreateImm(Res, S, E));
- return false;
- }
- case AsmToken::Identifier:
- case AsmToken::LParen:
- case AsmToken::Minus:
- case AsmToken::Plus:
- case AsmToken::Integer:
- case AsmToken::String: {
- // quoted label names
- const MCExpr *IdVal;
- SMLoc S = Parser.getTok().getLoc();
- if (getParser().parseExpression(IdVal))
- return true;
- SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
- Operands.push_back(Cpu0Operand::CreateImm(IdVal, S, E));
- return false;
- }
- case AsmToken::Percent: {
- // it is a symbol reference or constant expression
- const MCExpr *IdVal;
- SMLoc S = Parser.getTok().getLoc(); // start location of the operand
- if (parseRelocOperand(IdVal))
- return true;
-
- SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-
- Operands.push_back(Cpu0Operand::CreateImm(IdVal, S, E));
- return false;
- } // case AsmToken::Percent
- } // switch(getLexer().getKind())
- return true;
-}
-
-bool Cpu0AsmParser::parseRelocOperand(const MCExpr *&Res) {
-
- Parser.Lex(); // eat % token
- const AsmToken &Tok = Parser.getTok(); // get next token, operation
- if (Tok.isNot(AsmToken::Identifier))
- return true;
-
- std::string Str = Tok.getIdentifier().str();
-
- Parser.Lex(); // eat identifier
- // now make expression from the rest of the operand
- const MCExpr *IdVal;
- SMLoc EndLoc;
-
- if (getLexer().getKind() == AsmToken::LParen) {
- while (1) {
- Parser.Lex(); // eat '(' token
- if (getLexer().getKind() == AsmToken::Percent) {
- Parser.Lex(); // eat % token
- const AsmToken &nextTok = Parser.getTok();
- if (nextTok.isNot(AsmToken::Identifier))
- return true;
- Str += "(%";
- Str += nextTok.getIdentifier();
- Parser.Lex(); // eat identifier
- if (getLexer().getKind() != AsmToken::LParen)
- return true;
- } else
- break;
- }
- if (getParser().parseParenExpression(IdVal,EndLoc))
- return true;
-
- while (getLexer().getKind() == AsmToken::RParen)
- Parser.Lex(); // eat ')' token
-
- } else
- return true; // parenthesis must follow reloc operand
-
- // Check the type of the expression
- if (const MCConstantExpr *MCE = dyn_cast<MCConstantExpr>(IdVal)) {
- // it's a constant, evaluate lo or hi value
- int Val = MCE->getValue();
- if (Str == "lo") {
- Val = Val & 0xffff;
- } else if (Str == "hi") {
- Val = (Val & 0xffff0000) >> 16;
- }
- Res = MCConstantExpr::Create(Val, getContext());
- return false;
- }
-
- if (const MCSymbolRefExpr *MSRE = dyn_cast<MCSymbolRefExpr>(IdVal)) {
- // it's a symbol, create symbolic expression from symbol
- StringRef Symbol = MSRE->getSymbol().getName();
- MCSymbolRefExpr::VariantKind VK = getVariantKind(Str);
- Res = MCSymbolRefExpr::Create(Symbol,VK,getContext());
- return false;
- }
- return true;
-}
-
-bool Cpu0AsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
- SMLoc &EndLoc) {
-
- StartLoc = Parser.getTok().getLoc();
- RegNo = tryParseRegister("");
- EndLoc = Parser.getTok().getLoc();
- return (RegNo == (unsigned)-1);
-}
-
-bool Cpu0AsmParser::parseMemOffset(const MCExpr *&Res) {
-
- SMLoc S;
-
- switch(getLexer().getKind()) {
- default:
- return true;
- case AsmToken::Integer:
- case AsmToken::Minus:
- case AsmToken::Plus:
- return (getParser().parseExpression(Res));
- case AsmToken::Percent:
- return parseRelocOperand(Res);
- case AsmToken::LParen:
- return false; // it's probably assuming 0
- }
- return true;
-}
-
-// eg, 12($sp) or 12(la)
-Cpu0AsmParser::OperandMatchResultTy Cpu0AsmParser::parseMemOperand(
- SmallVectorImpl<MCParsedAsmOperand*>&Operands) {
-
- const MCExpr *IdVal = 0;
- SMLoc S;
- // first operand is the offset
- S = Parser.getTok().getLoc();
-
- if (parseMemOffset(IdVal))
- return MatchOperand_ParseFail;
-
- const AsmToken &Tok = Parser.getTok(); // get next token
- if (Tok.isNot(AsmToken::LParen)) {
- Cpu0Operand *Mnemonic = static_cast<Cpu0Operand*>(Operands[0]);
- if (Mnemonic->getToken() == "la") {
- SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer()-1);
- Operands.push_back(Cpu0Operand::CreateImm(IdVal, S, E));
- return MatchOperand_Success;
- }
- Error(Parser.getTok().getLoc(), "'(' expected");
- return MatchOperand_ParseFail;
- }
-
- Parser.Lex(); // Eat '(' token.
-
- const AsmToken &Tok1 = Parser.getTok(); // get next token
- if (Tok1.is(AsmToken::Dollar)) {
- Parser.Lex(); // Eat '$' token.
- if (tryParseRegisterOperand(Operands,"")) {
- Error(Parser.getTok().getLoc(), "unexpected token in operand");
- return MatchOperand_ParseFail;
- }
-
- } else {
- Error(Parser.getTok().getLoc(), "unexpected token in operand");
- return MatchOperand_ParseFail;
- }
-
- const AsmToken &Tok2 = Parser.getTok(); // get next token
- if (Tok2.isNot(AsmToken::RParen)) {
- Error(Parser.getTok().getLoc(), "')' expected");
- return MatchOperand_ParseFail;
- }
-
- SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
-
- Parser.Lex(); // Eat ')' token.
-
- if (IdVal == 0)
- IdVal = MCConstantExpr::Create(0, getContext());
-
- // now replace register operand with the mem operand
- Cpu0Operand* op = static_cast<Cpu0Operand*>(Operands.back());
- int RegNo = op->getReg();
- // remove register from operands
- Operands.pop_back();
- // and add memory operand
- Operands.push_back(Cpu0Operand::CreateMem(RegNo, IdVal, S, E));
- delete op;
- return MatchOperand_Success;
-}
-
-MCSymbolRefExpr::VariantKind Cpu0AsmParser::getVariantKind(StringRef Symbol) {
-
- MCSymbolRefExpr::VariantKind VK
- = StringSwitch<MCSymbolRefExpr::VariantKind>(Symbol)
- .Case("hi", MCSymbolRefExpr::VK_Cpu0_ABS_HI)
- .Case("lo", MCSymbolRefExpr::VK_Cpu0_ABS_LO)
- .Case("gp_rel", MCSymbolRefExpr::VK_Cpu0_GPREL)
- .Case("call24", MCSymbolRefExpr::VK_Cpu0_GOT_CALL)
- .Case("got", MCSymbolRefExpr::VK_Cpu0_GOT)
- .Case("tlsgd", MCSymbolRefExpr::VK_Cpu0_TLSGD)
- .Case("tlsldm", MCSymbolRefExpr::VK_Cpu0_TLSLDM)
- .Case("dtprel_hi", MCSymbolRefExpr::VK_Cpu0_DTPREL_HI)
- .Case("dtprel_lo", MCSymbolRefExpr::VK_Cpu0_DTPREL_LO)
- .Case("gottprel", MCSymbolRefExpr::VK_Cpu0_GOTTPREL)
- .Case("tprel_hi", MCSymbolRefExpr::VK_Cpu0_TPREL_HI)
- .Case("tprel_lo", MCSymbolRefExpr::VK_Cpu0_TPREL_LO)
- .Case("got_disp", MCSymbolRefExpr::VK_Cpu0_GOT_DISP)
- .Case("got_page", MCSymbolRefExpr::VK_Cpu0_GOT_PAGE)
- .Case("got_ofst", MCSymbolRefExpr::VK_Cpu0_GOT_OFST)
- .Case("hi(%neg(%gp_rel", MCSymbolRefExpr::VK_Cpu0_GPOFF_HI)
- .Case("lo(%neg(%gp_rel", MCSymbolRefExpr::VK_Cpu0_GPOFF_LO)
- .Default(MCSymbolRefExpr::VK_None);
-
- return VK;
-}
-
-bool Cpu0AsmParser::
-parseMathOperation(StringRef Name, SMLoc NameLoc,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
- // split the format
- size_t Start = Name.find('.'), Next = Name.rfind('.');
- StringRef Format1 = Name.slice(Start, Next);
- // and add the first format to the operands
- Operands.push_back(Cpu0Operand::CreateToken(Format1, NameLoc));
- // now for the second format
- StringRef Format2 = Name.slice(Next, StringRef::npos);
- Operands.push_back(Cpu0Operand::CreateToken(Format2, NameLoc));
-
- // set the format for the first register
-// setFpFormat(Format1);
-
- // Read the remaining operands.
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- // Read the first operand.
- if (ParseOperand(Operands, Name)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
-
- if (getLexer().isNot(AsmToken::Comma)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
-
- }
- Parser.Lex(); // Eat the comma.
-
- // Parse and remember the operand.
- if (ParseOperand(Operands, Name)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
- }
-
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
-
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-bool Cpu0AsmParser::
-ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
- SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
-
- // Create the leading tokens for the mnemonic, split by '.' characters.
- size_t Start = 0, Next = Name.find('.');
- StringRef Mnemonic = Name.slice(Start, Next);
-
- Operands.push_back(Cpu0Operand::CreateToken(Mnemonic, NameLoc));
-
- // Read the remaining operands.
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- // Read the first operand.
- if (ParseOperand(Operands, Name)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
-
- while (getLexer().is(AsmToken::Comma) ) {
- Parser.Lex(); // Eat the comma.
-
- // Parse and remember the operand.
- if (ParseOperand(Operands, Name)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
- }
- }
-
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, "unexpected token in argument list");
- }
-
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-bool Cpu0AsmParser::reportParseError(StringRef ErrorMsg) {
- SMLoc Loc = getLexer().getLoc();
- Parser.eatToEndOfStatement();
- return Error(Loc, ErrorMsg);
-}
-
-bool Cpu0AsmParser::parseSetReorderDirective() {
- Parser.Lex();
- // if this is not the end of the statement, report error
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- reportParseError("unexpected token in statement");
- return false;
- }
- Options.setReorder();
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-bool Cpu0AsmParser::parseSetNoReorderDirective() {
- Parser.Lex();
- // if this is not the end of the statement, report error
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- reportParseError("unexpected token in statement");
- return false;
- }
- Options.setNoreorder();
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-bool Cpu0AsmParser::parseSetMacroDirective() {
- Parser.Lex();
- // if this is not the end of the statement, report error
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- reportParseError("unexpected token in statement");
- return false;
- }
- Options.setMacro();
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-
-bool Cpu0AsmParser::parseSetNoMacroDirective() {
- Parser.Lex();
- // if this is not the end of the statement, report error
- if (getLexer().isNot(AsmToken::EndOfStatement)) {
- reportParseError("`noreorder' must be set before `nomacro'");
- return false;
- }
- if (Options.isReorder()) {
- reportParseError("`noreorder' must be set before `nomacro'");
- return false;
- }
- Options.setNomacro();
- Parser.Lex(); // Consume the EndOfStatement
- return false;
-}
-bool Cpu0AsmParser::parseDirectiveSet() {
-
- // get next token
- const AsmToken &Tok = Parser.getTok();
-
- if (Tok.getString() == "reorder") {
- return parseSetReorderDirective();
- } else if (Tok.getString() == "noreorder") {
- return parseSetNoReorderDirective();
- } else if (Tok.getString() == "macro") {
- return parseSetMacroDirective();
- } else if (Tok.getString() == "nomacro") {
- return parseSetNoMacroDirective();
- }
- return true;
-}
-
-bool Cpu0AsmParser::ParseDirective(AsmToken DirectiveID) {
-
- if (DirectiveID.getString() == ".ent") {
- // ignore this directive for now
- Parser.Lex();
- return false;
- }
-
- if (DirectiveID.getString() == ".end") {
- // ignore this directive for now
- Parser.Lex();
- return false;
- }
-
- if (DirectiveID.getString() == ".frame") {
- // ignore this directive for now
- Parser.eatToEndOfStatement();
- return false;
- }
-
- if (DirectiveID.getString() == ".set") {
- return parseDirectiveSet();
- }
-
- if (DirectiveID.getString() == ".fmask") {
- // ignore this directive for now
- Parser.eatToEndOfStatement();
- return false;
- }
-
- if (DirectiveID.getString() == ".mask") {
- // ignore this directive for now
- Parser.eatToEndOfStatement();
- return false;
- }
-
- if (DirectiveID.getString() == ".gpword") {
- // ignore this directive for now
- Parser.eatToEndOfStatement();
- return false;
- }
-
- return true;
-}
-
-extern "C" void LLVMInitializeCpu0AsmParser() {
- RegisterMCAsmParser<Cpu0AsmParser> X(TheCpu0Target);
- RegisterMCAsmParser<Cpu0AsmParser> Y(TheCpu0elTarget);
-}
-
-#define GET_REGISTER_MATCHER
-#define GET_MATCHER_IMPLEMENTATION
-#include "Cpu0GenAsmMatcher.inc"
-
View
23 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/AsmParser/LLVMBuild.txt
@@ -1,23 +0,0 @@
-;===- ./lib/Target/Mips/AsmParser/LLVMBuild.txt ----------------*- Conf -*--===;
-;
-; The LLVM Compiler Infrastructure
-;
-; This file is distributed under the University of Illinois Open Source
-; License. See LICENSE.TXT for details.
-;
-;===------------------------------------------------------------------------===;
-;
-; This is an LLVMBuild description file for the components in this subdirectory.
-;
-; For more information on the LLVMBuild system, please see:
-;
-; http://llvm.org/docs/LLVMBuild.html
-;
-;===------------------------------------------------------------------------===;
-
-[component_0]
-type = Library
-name = Cpu0AsmParser
-parent = Mips
-required_libraries = MC MCParser Support MipsDesc MipsInfo
-add_to_library_groups = Cpu0
View
47 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/CMakeLists.txt
@@ -1,47 +0,0 @@
-# CMakeLists.txt
-# Our td all in Cpu0.td, Cpu0RegisterInfo.td and Cpu0InstrInfo.td included in
-# Cpu0.td.
-set(LLVM_TARGET_DEFINITIONS Cpu0.td)
-
-# Generate Cpu0GenRegisterInfo.inc and Cpu0GenInstrInfo.inc which included by
-# your hand code C++ files.
-# Cpu0GenRegisterInfo.inc came from Cpu0RegisterInfo.td, Cpu0GenInstrInfo.inc
-# came from Cpu0InstrInfo.td.
-tablegen(LLVM Cpu0GenRegisterInfo.inc -gen-register-info)
-tablegen(LLVM Cpu0GenInstrInfo.inc -gen-instr-info)
-tablegen(LLVM Cpu0GenDisassemblerTables.inc -gen-disassembler)
-tablegen(LLVM Cpu0GenCodeEmitter.inc -gen-emitter)
-tablegen(LLVM Cpu0GenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-
-tablegen(LLVM Cpu0GenAsmWriter.inc -gen-asm-writer)
-tablegen(LLVM Cpu0GenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM Cpu0GenCallingConv.inc -gen-callingconv)
-tablegen(LLVM Cpu0GenSubtargetInfo.inc -gen-subtarget)
-tablegen(LLVM Cpu0GenAsmMatcher.inc -gen-asm-matcher)
-
-# Cpu0CommonTableGen must be defined
-add_public_tablegen_target(Cpu0CommonTableGen)
-
-# Cpu0CodeGen should match with LLVMBuild.txt Cpu0CodeGen
-add_llvm_target(Cpu0CodeGen
- Cpu0AsmPrinter.cpp
- Cpu0EmitGPRestore.cpp
- Cpu0InstrInfo.cpp
- Cpu0ISelDAGToDAG.cpp
- Cpu0ISelLowering.cpp
- Cpu0FrameLowering.cpp
- Cpu0MCInstLower.cpp
- Cpu0MachineFunction.cpp
- Cpu0RegisterInfo.cpp
- Cpu0Subtarget.cpp
- Cpu0TargetMachine.cpp
- Cpu0TargetObjectFile.cpp
- Cpu0SelectionDAGInfo.cpp
- )
-
-# Should match with "subdirectories = MCTargetDesc TargetInfo" in LLVMBuild.txt
-add_subdirectory(InstPrinter)
-add_subdirectory(Disassembler)
-add_subdirectory(TargetInfo)
-add_subdirectory(MCTargetDesc)
-add_subdirectory(AsmParser)
View
30 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0.h
@@ -1,30 +0,0 @@
-//===-- Cpu0.h - Top-level interface for Cpu0 representation ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the entry points for global functions defined in
-// the LLVM Cpu0 back-end.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef TARGET_CPU0_H
-#define TARGET_CPU0_H
-
-#include "MCTargetDesc/Cpu0MCTargetDesc.h"
-#include "llvm/Target/TargetMachine.h"
-
-namespace llvm {
- class Cpu0TargetMachine;
- class FunctionPass;
-
- FunctionPass *createCpu0ISelDag(Cpu0TargetMachine &TM);
- FunctionPass *createCpu0EmitGPRestorePass(Cpu0TargetMachine &TM);
-
-} // end namespace llvm;
-
-#endif
View
73 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0.td
@@ -1,73 +0,0 @@
-//===-- Cpu0.td - Describe the Cpu0 Target Machine ---------*- tablegen -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// This is the top level entry point for the Cpu0 target.
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Target-independent interfaces
-//===----------------------------------------------------------------------===//
-
-include "llvm/Target/Target.td"
-
-//===----------------------------------------------------------------------===//
-// Register File, Calling Conv, Instruction Descriptions
-//===----------------------------------------------------------------------===//
-
-include "Cpu0RegisterInfo.td"
-include "Cpu0Schedule.td"
-include "Cpu0InstrInfo.td"
-include "Cpu0CallingConv.td"
-
-def Cpu0InstrInfo : InstrInfo;
-
-// Without this will have error: 'cpu032' is not a recognized processor for
-// this target (ignoring processor)
-//===----------------------------------------------------------------------===//
-// Cpu0 Subtarget features //
-//===----------------------------------------------------------------------===//
-
-def FeatureCpu032 : SubtargetFeature<"cpu032", "Cpu0ArchVersion", "Cpu032",
- "Cpu032 ISA Support">;
-
-//===----------------------------------------------------------------------===//
-// Cpu0 processors supported.
-//===----------------------------------------------------------------------===//
-
-class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, Cpu0GenericItineraries, Features>;
-
-def : Proc<"cpu032", [FeatureCpu032]>;
-
-def Cpu0AsmWriter : AsmWriter {
- string AsmWriterClassName = "InstPrinter";
- bit isMCAsmWriter = 1;
-}
-
-def Cpu0AsmParser : AsmParser {
- let ShouldEmitMatchRegisterName = 0;
-}
-
-def Cpu0AsmParserVariant : AsmParserVariant {
- int Variant = 0;
-
- // Recognize hard coded registers.
- string RegisterPrefix = "$";
-}
-
-// Will generate Cpu0GenAsmWrite.inc included by Cpu0InstPrinter.cpp, contents
-// as follows,
-// void Cpu0InstPrinter::printInstruction(const MCInst *MI, raw_ostream &O) {...}
-// const char *Cpu0InstPrinter::getRegisterName(unsigned RegNo) {...}
-def Cpu0 : Target {
-// def Cpu0InstrInfo : InstrInfo as before.
- let InstructionSet = Cpu0InstrInfo;
- let AssemblyParsers = [Cpu0AsmParser];
- let AssemblyWriters = [Cpu0AsmWriter];
- let AssemblyParserVariants = [Cpu0AsmParserVariant];
-}
View
314 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0AsmPrinter.cpp
@@ -1,314 +0,0 @@
-//===-- Cpu0AsmPrinter.cpp - Cpu0 LLVM Assembly Printer -------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains a printer that converts from our internal representation
-// of machine-dependent LLVM code to GAS-format CPU0 assembly language.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "cpu0-asm-printer"
-#include "Cpu0AsmPrinter.h"
-#include "Cpu0.h"
-#include "Cpu0InstrInfo.h"
-#include "InstPrinter/Cpu0InstPrinter.h"
-#include "MCTargetDesc/Cpu0BaseInfo.h"
-#include "llvm/ADT/SmallString.h"
-#include "llvm/ADT/StringExtras.h"
-#include "llvm/ADT/Twine.h"
-#include "llvm/IR/BasicBlock.h"
-#include "llvm/IR/Instructions.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineConstantPool.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineInstr.h"
-#include "llvm/CodeGen/MachineMemOperand.h"
-#include "llvm/MC/MCStreamer.h"
-#include "llvm/MC/MCAsmInfo.h"
-#include "llvm/MC/MCInst.h"
-#include "llvm/MC/MCSymbol.h"
-#include "llvm/Support/TargetRegistry.h"
-#include "llvm/Support/raw_ostream.h"
-#include "llvm/Target/Mangler.h"
-#include "llvm/Target/TargetLoweringObjectFile.h"
-#include "llvm/Target/TargetOptions.h"
-
-using namespace llvm;
-
-void Cpu0AsmPrinter::EmitInstrWithMacroNoAT(const MachineInstr *MI) {
- MCInst TmpInst;
-
- MCInstLowering.Lower(MI, TmpInst);
- OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
- if (Cpu0FI->getEmitNOAT())
- OutStreamer.EmitRawText(StringRef("\t.set\tat"));
- OutStreamer.EmitInstruction(TmpInst);
- if (Cpu0FI->getEmitNOAT())
- OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
- OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
-}
-
-bool Cpu0AsmPrinter::runOnMachineFunction(MachineFunction &MF) {
- Cpu0FI = MF.getInfo<Cpu0FunctionInfo>();
- AsmPrinter::runOnMachineFunction(MF);
- return true;
-}
-
-//- EmitInstruction() must exists or will have run time error.
-void Cpu0AsmPrinter::EmitInstruction(const MachineInstr *MI) {
- if (MI->isDebugValue()) {
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
-
- PrintDebugValueComment(MI, OS);
- return;
- }
-
- unsigned Opc = MI->getOpcode();
- MCInst TmpInst0;
- SmallVector<MCInst, 4> MCInsts;
-
- switch (Opc) {
- case Cpu0::CPRESTORE: {
- const MachineOperand &MO = MI->getOperand(0);
- assert(MO.isImm() && "CPRESTORE's operand must be an immediate.");
- int64_t Offset = MO.getImm();
-
- if (OutStreamer.hasRawTextSupport()) {
- if (!isInt<16>(Offset)) {
- EmitInstrWithMacroNoAT(MI);
- return;
- }
- } else {
- MCInstLowering.LowerCPRESTORE(Offset, MCInsts);
-
- for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
- I != MCInsts.end(); ++I)
- OutStreamer.EmitInstruction(*I);
-
- return;
- }
-
- break;
- }
- default:
- break;
- }
-
- MCInstLowering.Lower(MI, TmpInst0);
- OutStreamer.EmitInstruction(TmpInst0);
-}
-
-//===----------------------------------------------------------------------===//
-//
-// Cpu0 Asm Directives
-//
-// -- Frame directive "frame Stackpointer, Stacksize, RARegister"
-// Describe the stack frame.
-//
-// -- Mask directives "(f)mask bitmask, offset"
-// Tells the assembler which registers are saved and where.
-// bitmask - contain a little endian bitset indicating which registers are
-// saved on function prologue (e.g. with a 0x80000000 mask, the
-// assembler knows the register 31 (RA) is saved at prologue.
-// offset - the position before stack pointer subtraction indicating where
-// the first saved register on prologue is located. (e.g. with a
-//
-// Consider the following function prologue:
-//
-// .frame $fp,48,$ra
-// .mask 0xc0000000,-8
-// addiu $sp, $sp, -48
-// st $ra, 40($sp)
-// st $fp, 36($sp)
-//
-// With a 0xc0000000 mask, the assembler knows the register 31 (RA) and
-// 30 (FP) are saved at prologue. As the save order on prologue is from
-// left to right, RA is saved first. A -8 offset means that after the
-// stack pointer subtration, the first register in the mask (RA) will be
-// saved at address 48-8=40.
-//
-//===----------------------------------------------------------------------===//
-
-//===----------------------------------------------------------------------===//
-// Mask directives
-//===----------------------------------------------------------------------===//
-// .frame $sp,8,$lr
-//-> .mask 0x00000000,0
-// .set noreorder
-// .set nomacro
-
-// Create a bitmask with all callee saved registers for CPU or Floating Point
-// registers. For CPU registers consider RA, GP and FP for saving if necessary.
-void Cpu0AsmPrinter::printSavedRegsBitmask(raw_ostream &O) {
- // CPU and FPU Saved Registers Bitmasks
- unsigned CPUBitmask = 0;
- int CPUTopSavedRegOff;
-
- // Set the CPU and FPU Bitmasks
- const MachineFrameInfo *MFI = MF->getFrameInfo();
- const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
- // size of stack area to which FP callee-saved regs are saved.
- unsigned CPURegSize = Cpu0::CPURegsRegClass.getSize();
- unsigned i = 0, e = CSI.size();
-
- // Set CPU Bitmask.
- for (; i != e; ++i) {
- unsigned Reg = CSI[i].getReg();
- unsigned RegNum = getCpu0RegisterNumbering(Reg);
- CPUBitmask |= (1 << RegNum);
- }
-
- CPUTopSavedRegOff = CPUBitmask ? -CPURegSize : 0;
-
- // Print CPUBitmask
- O << "\t.mask \t"; printHex32(CPUBitmask, O);
- O << ',' << CPUTopSavedRegOff << '\n';
-}
-
-// Print a 32 bit hex number with all numbers.
-void Cpu0AsmPrinter::printHex32(unsigned Value, raw_ostream &O) {
- O << "0x";
- for (int i = 7; i >= 0; i--)
- O.write_hex((Value & (0xF << (i*4))) >> (i*4));
-}
-
-//===----------------------------------------------------------------------===//
-// Frame and Set directives
-//===----------------------------------------------------------------------===//
-//-> .frame $sp,8,$lr
-// .mask 0x00000000,0
-// .set noreorder
-// .set nomacro
-/// Frame Directive
-void Cpu0AsmPrinter::emitFrameDirective() {
- const TargetRegisterInfo &RI = *TM.getRegisterInfo();
-
- unsigned stackReg = RI.getFrameRegister(*MF);
- unsigned returnReg = RI.getRARegister();
- unsigned stackSize = MF->getFrameInfo()->getStackSize();
-
- if (OutStreamer.hasRawTextSupport())
- OutStreamer.EmitRawText("\t.frame\t$" +
- StringRef(Cpu0InstPrinter::getRegisterName(stackReg)).lower() +
- "," + Twine(stackSize) + ",$" +
- StringRef(Cpu0InstPrinter::getRegisterName(returnReg)).lower());
-}
-
-/// Emit Set directives.
-const char *Cpu0AsmPrinter::getCurrentABIString() const {
- switch (Subtarget->getTargetABI()) {
- case Cpu0Subtarget::O32: return "abi32";
- default: llvm_unreachable("Unknown Cpu0 ABI");;
- }
-}
-
-// .type main,@function
-//-> .ent main # @main
-// main:
-void Cpu0AsmPrinter::EmitFunctionEntryLabel() {
- if (OutStreamer.hasRawTextSupport())
- OutStreamer.EmitRawText("\t.ent\t" + Twine(CurrentFnSym->getName()));
- OutStreamer.EmitLabel(CurrentFnSym);
-}
-
-
-// .frame $sp,8,$pc
-// .mask 0x00000000,0
-//-> .set noreorder
-//-> .set nomacro
-/// EmitFunctionBodyStart - Targets can override this to emit stuff before
-/// the first basic block in the function.
-void Cpu0AsmPrinter::EmitFunctionBodyStart() {
- MCInstLowering.Initialize(Mang, &MF->getContext());
-
- emitFrameDirective();
- bool EmitCPLoad = (MF->getTarget().getRelocationModel() == Reloc::PIC_) &&
- Cpu0FI->globalBaseRegSet() &&
- Cpu0FI->globalBaseRegFixed();
-
- if (OutStreamer.hasRawTextSupport()) {
- SmallString<128> Str;
- raw_svector_ostream OS(Str);
- printSavedRegsBitmask(OS);
- OutStreamer.EmitRawText(OS.str());
-
- OutStreamer.EmitRawText(StringRef("\t.set\tnoreorder"));
-
- // Emit .cpload directive if needed.
- if (EmitCPLoad)
- //- .cpload $t9
- OutStreamer.EmitRawText(StringRef("\t.cpload\t$t9"));
- //- .cpload $10
- // OutStreamer.EmitRawText(StringRef("\t.cpload\t$6"));
-
- OutStreamer.EmitRawText(StringRef("\t.set\tnomacro"));
-
- if (Cpu0FI->getEmitNOAT())
- OutStreamer.EmitRawText(StringRef("\t.set\tnoat"));
- } else if (EmitCPLoad) {
- SmallVector<MCInst, 4> MCInsts;
- MCInstLowering.LowerCPLOAD(MCInsts);
- for (SmallVector<MCInst, 4>::iterator I = MCInsts.begin();
- I != MCInsts.end(); ++I)
- OutStreamer.EmitInstruction(*I);
- }
-}
-
-//-> .set macro
-//-> .set reorder
-//-> .end main
-/// EmitFunctionBodyEnd - Targets can override this to emit stuff after
-/// the last basic block in the function.
-void Cpu0AsmPrinter::EmitFunctionBodyEnd() {
- // There are instruction for this macros, but they must
- // always be at the function end, and we can't emit and
- // break with BB logic.
- if (OutStreamer.hasRawTextSupport()) {
- OutStreamer.EmitRawText(StringRef("\t.set\tmacro"));
- OutStreamer.EmitRawText(StringRef("\t.set\treorder"));
- OutStreamer.EmitRawText("\t.end\t" + Twine(CurrentFnSym->getName()));
- }
-}
-
-// .section .mdebug.abi32
-// .previous
-void Cpu0AsmPrinter::EmitStartOfAsmFile(Module &M) {
- // FIXME: Use SwitchSection.
-
- // Tell the assembler which ABI we are using
- if (OutStreamer.hasRawTextSupport())
- OutStreamer.EmitRawText("\t.section .mdebug." +
- Twine(getCurrentABIString()));
-
- // return to previous section
- if (OutStreamer.hasRawTextSupport())
- OutStreamer.EmitRawText(StringRef("\t.previous"));
-}
-
-MachineLocation
-Cpu0AsmPrinter::getDebugValueLocation(const MachineInstr *MI) const {
- // Handles frame addresses emitted in Cpu0InstrInfo::emitFrameIndexDebugValue.
- assert(MI->getNumOperands() == 4 && "Invalid no. of machine operands!");
- assert(MI->getOperand(0).isReg() && MI->getOperand(1).isImm() &&
- "Unexpected MachineOperand types");
- return MachineLocation(MI->getOperand(0).getReg(),
- MI->getOperand(1).getImm());
-}
-
-void Cpu0AsmPrinter::PrintDebugValueComment(const MachineInstr *MI,
- raw_ostream &OS) {
- // TODO: implement
- OS << "PrintDebugValueComment()";
-}
-
-// Force static initialization.
-extern "C" void LLVMInitializeCpu0AsmPrinter() {
- RegisterAsmPrinter<Cpu0AsmPrinter> X(TheCpu0Target);
- RegisterAsmPrinter<Cpu0AsmPrinter> Y(TheCpu0elTarget);
-}
View
68 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0AsmPrinter.h
@@ -1,68 +0,0 @@
-//===-- Cpu0AsmPrinter.h - Cpu0 LLVM Assembly Printer ----------*- C++ -*--===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// Cpu0 Assembly printer class.
-//
-//===----------------------------------------------------------------------===//
-
-#ifndef CPU0ASMPRINTER_H
-#define CPU0ASMPRINTER_H
-
-#include "Cpu0MachineFunction.h"
-#include "Cpu0MCInstLower.h"
-#include "Cpu0Subtarget.h"
-#include "llvm/CodeGen/AsmPrinter.h"
-#include "llvm/Support/Compiler.h"
-#include "llvm/Target/TargetMachine.h"
-
-namespace llvm {
-class MCStreamer;
-class MachineInstr;
-class MachineBasicBlock;
-class Module;
-class raw_ostream;
-
-class LLVM_LIBRARY_VISIBILITY Cpu0AsmPrinter : public AsmPrinter {
-
- void EmitInstrWithMacroNoAT(const MachineInstr *MI);
-
-public:
-
- const Cpu0Subtarget *Subtarget;
- const Cpu0FunctionInfo *Cpu0FI;
- Cpu0MCInstLower MCInstLowering;
-
- explicit Cpu0AsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
- : AsmPrinter(TM, Streamer), MCInstLowering(*this) {
- Subtarget = &TM.getSubtarget<Cpu0Subtarget>();
- }
-
- virtual const char *getPassName() const {
- return "Cpu0 Assembly Printer";
- }
-
- virtual bool runOnMachineFunction(MachineFunction &MF);
-
-//- EmitInstruction() must exists or will have run time error.
- void EmitInstruction(const MachineInstr *MI);
- void printSavedRegsBitmask(raw_ostream &O);
- void printHex32(unsigned int Value, raw_ostream &O);
- void emitFrameDirective();
- const char *getCurrentABIString() const;
- virtual void EmitFunctionEntryLabel();
- virtual void EmitFunctionBodyStart();
- virtual void EmitFunctionBodyEnd();
- void EmitStartOfAsmFile(Module &M);
- virtual MachineLocation getDebugValueLocation(const MachineInstr *MI) const;
- void PrintDebugValueComment(const MachineInstr *MI, raw_ostream &OS);
-};
-}
-
-#endif
-
View
49 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0CallingConv.td
@@ -1,49 +0,0 @@
-//===-- Cpu0CallingConv.td - Calling Conventions for Cpu0 --*- tablegen -*-===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-// This describes the calling conventions for Cpu0 architecture.
-//===----------------------------------------------------------------------===//
-
-/// CCIfSubtarget - Match if the current subtarget has a feature F.
-class CCIfSubtarget<string F, CCAction A>:
- CCIf<!strconcat("State.getTarget().getSubtarget<Cpu0Subtarget>().", F), A>;
-
-def RetCC_Cpu0EABI : CallingConv<[
- // i32 are returned in registers V0, V1, A0, A1
- CCIfType<[i32], CCAssignToReg<[V0, V1, A0, A1]>>
-]>;
-
-//===----------------------------------------------------------------------===//
-// Cpu0 EABI Calling Convention
-//===----------------------------------------------------------------------===//
-
-def CC_Cpu0EABI : CallingConv<[
- // Promote i8/i16 arguments to i32.
- CCIfType<[i8, i16], CCPromoteToType<i32>>,
- // Integer values get stored in stack slots that are 4 bytes in
- // size and 4-byte aligned.
- CCIfType<[i32], CCAssignToStack<4, 4>>
-]>;
-
-
-//===----------------------------------------------------------------------===//
-// Cpu0 Calling Convention Dispatch
-//===----------------------------------------------------------------------===//
-
-def CC_Cpu0 : CallingConv<[
- CCDelegateTo<CC_Cpu0EABI>
-]>;
-
-
-def RetCC_Cpu0 : CallingConv<[
- CCDelegateTo<RetCC_Cpu0EABI>
-]>;
-
-def CSR_O32 : CalleeSavedRegs<(add LR, FP,
- (sequence "S%u", 2, 0))>;
-
View
99 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0EmitGPRestore.cpp
@@ -1,99 +0,0 @@
-//===-- Cpu0EmitGPRestore.cpp - Emit GP Restore Instruction ---------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This pass emits instructions that restore $gp right
-// after jalr instructions.
-//
-//===----------------------------------------------------------------------===//
-
-#define DEBUG_TYPE "emit-gp-restore"
-
-#include "Cpu0.h"
-#include "Cpu0TargetMachine.h"
-#include "Cpu0MachineFunction.h"
-#include "llvm/CodeGen/MachineFunctionPass.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/Target/TargetInstrInfo.h"
-#include "llvm/ADT/Statistic.h"
-
-using namespace llvm;
-
-namespace {
- struct Inserter : public MachineFunctionPass {
-
- TargetMachine &TM;
- const TargetInstrInfo *TII;
-
- static char ID;
- Inserter(TargetMachine &tm)
- : MachineFunctionPass(ID), TM(tm), TII(tm.getInstrInfo()) { }
-
- virtual const char *getPassName() const {
- return "Cpu0 Emit GP Restore";
- }
-
- bool runOnMachineFunction(MachineFunction &F);
- };
- char Inserter::ID = 0;
-} // end of anonymous namespace
-
-bool Inserter::runOnMachineFunction(MachineFunction &F) {
- Cpu0FunctionInfo *Cpu0FI = F.getInfo<Cpu0FunctionInfo>();
-
- if ((TM.getRelocationModel() != Reloc::PIC_) ||
- (!Cpu0FI->globalBaseRegFixed()))
- return false;
-
- bool Changed = false;
- int FI = Cpu0FI->getGPFI();
-
- for (MachineFunction::iterator MFI = F.begin(), MFE = F.end();
- MFI != MFE; ++MFI) {
- MachineBasicBlock& MBB = *MFI;
- MachineBasicBlock::iterator I = MFI->begin();
-
- /// IsLandingPad - Indicate that this basic block is entered via an
- /// exception handler.
- // If MBB is a landing pad, insert instruction that restores $gp after
- // EH_LABEL.
- if (MBB.isLandingPad()) {
- // Find EH_LABEL first.
- for (; I->getOpcode() != TargetOpcode::EH_LABEL; ++I) ;
-
- // Insert ld.
- ++I;
- DebugLoc dl = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
- BuildMI(MBB, I, dl, TII->get(Cpu0::LD), Cpu0::GP).addFrameIndex(FI)
- .addImm(0);
- Changed = true;
- }
-
- while (I != MFI->end()) {
- if (I->getOpcode() != Cpu0::JALR) {
- ++I;
- continue;
- }
-
- DebugLoc dl = I->getDebugLoc();
- // emit lw $gp, ($gp save slot on stack) after jalr
- BuildMI(MBB, ++I, dl, TII->get(Cpu0::LD), Cpu0::GP).addFrameIndex(FI)
- .addImm(0);
- Changed = true;
- }
- }
-
- return Changed;
-}
-
-/// createCpu0EmitGPRestorePass - Returns a pass that emits instructions that
-/// restores $gp clobbered by jalr instructions.
-FunctionPass *llvm::createCpu0EmitGPRestorePass(Cpu0TargetMachine &tm) {
- return new Inserter(tm);
-}
-
View
250 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0FrameLowering.cpp
@@ -1,250 +0,0 @@
-//===-- Cpu0FrameLowering.cpp - Cpu0 Frame Information --------------------===//
-//
-// The LLVM Compiler Infrastructure
-//
-// This file is distributed under the University of Illinois Open Source
-// License. See LICENSE.TXT for details.
-//
-//===----------------------------------------------------------------------===//
-//
-// This file contains the Cpu0 implementation of TargetFrameLowering class.
-//
-//===----------------------------------------------------------------------===//
-
-#include "Cpu0FrameLowering.h"
-#include "Cpu0InstrInfo.h"
-#include "Cpu0MachineFunction.h"
-#include "MCTargetDesc/Cpu0BaseInfo.h"
-#include "llvm/IR/Function.h"
-#include "llvm/CodeGen/MachineFrameInfo.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/MachineInstrBuilder.h"
-#include "llvm/CodeGen/MachineModuleInfo.h"
-#include "llvm/CodeGen/MachineRegisterInfo.h"
-#include "llvm/IR/DataLayout.h"
-#include "llvm/Target/TargetOptions.h"
-#include "llvm/Support/CommandLine.h"
-
-using namespace llvm;
-
-//- emitPrologue() and emitEpilogue must exist for main().
-
-//===----------------------------------------------------------------------===//
-//
-// Stack Frame Processing methods
-// +----------------------------+
-//
-// The stack is allocated decrementing the stack pointer on
-// the first instruction of a function prologue. Once decremented,
-// all stack references are done thought a positive offset
-// from the stack/frame pointer, so the stack is considering
-// to grow up! Otherwise terrible hacks would have to be made
-// to get this stack ABI compliant :)
-//
-// The stack frame required by the ABI (after call):
-// Offset
-//
-// 0 ----------
-// 4 Args to pass
-// . saved $GP (used in PIC)
-// . Alloca allocations
-// . Local Area
-// . CPU "Callee Saved" Registers
-// . saved FP
-// . saved RA
-// . FPU "Callee Saved" Registers
-// StackSize -----------
-//
-// Offset - offset from sp after stack allocation on function prologue
-//
-// The sp is the stack pointer subtracted/added from the stack size
-// at the Prologue/Epilogue
-//
-// References to the previous stack (to obtain arguments) are done
-// with offsets that exceeds the stack size: (stacksize+(4*(num_arg-1))
-//
-// Examples:
-// - reference to the actual stack frame
-// for any local area var there is smt like : FI >= 0, StackOffset: 4
-// st REGX, 4(SP)
-//
-// - reference to previous stack frame
-// suppose there's a load to the 5th arguments : FI < 0, StackOffset: 16.
-// The emitted instruction will be something like:
-// ld REGX, 16+StackSize(SP)
-//
-// Since the total stack size is unknown on LowerFormalArguments, all
-// stack references (ObjectOffset) created to reference the function
-// arguments, are negative numbers. This way, on eliminateFrameIndex it's
-// possible to detect those references and the offsets are adjusted to
-// their real location.
-//
-//===----------------------------------------------------------------------===//
-
-//- Must have, hasFP() is pure virtual of parent
-// hasFP - Return true if the specified function should have a dedicated frame
-// pointer register. This is true if the function has variable sized allocas or
-// if frame pointer elimination is disabled.
-bool Cpu0FrameLowering::hasFP(const MachineFunction &MF) const {
- const MachineFrameInfo *MFI = MF.getFrameInfo();
- return MF.getTarget().Options.DisableFramePointerElim(MF) ||
- MFI->hasVarSizedObjects() || MFI->isFrameAddressTaken();
-}
-
-void Cpu0FrameLowering::emitPrologue(MachineFunction &MF) const {
- MachineBasicBlock &MBB = MF.front();
- MachineFrameInfo *MFI = MF.getFrameInfo();
- Cpu0FunctionInfo *Cpu0FI = MF.getInfo<Cpu0FunctionInfo>();
- const Cpu0InstrInfo &TII =
- *static_cast<const Cpu0InstrInfo*>(MF.getTarget().getInstrInfo());
- MachineBasicBlock::iterator MBBI = MBB.begin();
- DebugLoc dl = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
- unsigned SP = Cpu0::SP;
- unsigned ADDiu = Cpu0::ADDiu;
- // First, compute final stack size.
- unsigned StackAlign = getStackAlignment();
- unsigned RegSize = 4;
- unsigned LocalVarAreaOffset = Cpu0FI->needGPSaveRestore() ?
- (MFI->getObjectOffset(Cpu0FI->getGPFI()) + RegSize) :
- Cpu0FI->getMaxCallFrameSize();
- uint64_t StackSize = RoundUpToAlignment(LocalVarAreaOffset, StackAlign) +
- RoundUpToAlignment(MFI->getStackSize(), StackAlign);
-
- // Update stack size
- MFI->setStackSize(StackSize);
-
- // No need to allocate space on the stack.
- if (StackSize == 0 && !MFI->adjustsStack()) return;
-
- MachineModuleInfo &MMI = MF.getMMI();
- std::vector<MachineMove> &Moves = MMI.getFrameMoves();
- MachineLocation DstML, SrcML;
-
- // Adjust stack.
- if (isInt<16>(-StackSize)) // addiu sp, sp, (-stacksize)
- BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(-StackSize);
- else { // Expand immediate that doesn't fit in 16-bit.
- assert("No expandLargeImm(SP, -StackSize, false, TII, MBB, MBBI, dl);");
-// expandLargeImm(SP, -StackSize, false, TII, MBB, MBBI, dl);
- }
-
- // emit ".cfi_def_cfa_offset StackSize"
- MCSymbol *AdjustSPLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl,
- TII.get(TargetOpcode::PROLOG_LABEL)).addSym(AdjustSPLabel);
- DstML = MachineLocation(MachineLocation::VirtualFP);
- SrcML = MachineLocation(MachineLocation::VirtualFP, -StackSize);
- Moves.push_back(MachineMove(AdjustSPLabel, DstML, SrcML));
-
- const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
-
- if (CSI.size()) {
- // Find the instruction past the last instruction that saves a callee-saved
- // register to the stack.
- for (unsigned i = 0; i < CSI.size(); ++i)
- ++MBBI;
-
- // Iterate over list of callee-saved registers and emit .cfi_offset
- // directives.
- MCSymbol *CSLabel = MMI.getContext().CreateTempSymbol();
- BuildMI(MBB, MBBI, dl,
- TII.get(TargetOpcode::PROLOG_LABEL)).addSym(CSLabel);
-
- for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
- E = CSI.end(); I != E; ++I) {
- int64_t Offset = MFI->getObjectOffset(I->getFrameIdx());
- unsigned Reg = I->getReg();
- {
- // Reg is either in CPURegs or FGR32.
- DstML = MachineLocation(MachineLocation::VirtualFP, Offset);
- SrcML = MachineLocation(Reg);
- Moves.push_back(MachineMove(CSLabel, DstML, SrcML));
- }
- }
- }
-
- // Restore GP from the saved stack location
- if (Cpu0FI->needGPSaveRestore()) {
- unsigned Offset = MFI->getObjectOffset(Cpu0FI->getGPFI());
- BuildMI(MBB, MBBI, dl, TII.get(Cpu0::CPRESTORE)).addImm(Offset)
- .addReg(Cpu0::GP);
- }
-}
-
-void Cpu0FrameLowering::emitEpilogue(MachineFunction &MF,
- MachineBasicBlock &MBB) const {
- MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
- MachineFrameInfo *MFI = MF.getFrameInfo();
- const Cpu0InstrInfo &TII =
- *static_cast<const Cpu0InstrInfo*>(MF.getTarget().getInstrInfo());
- DebugLoc dl = MBBI->getDebugLoc();
- unsigned SP = Cpu0::SP;
- unsigned ADDiu = Cpu0::ADDiu;
-
- // Get the number of bytes from FrameInfo
- uint64_t StackSize = MFI->getStackSize();
-
- if (!StackSize)
- return;
-
- // Adjust stack.
- if (isInt<16>(StackSize)) // addiu sp, sp, (stacksize)
- BuildMI(MBB, MBBI, dl, TII.get(ADDiu), SP).addReg(SP).addImm(StackSize);
- else // Expand immediate that doesn't fit in 16-bit.
- assert("No expandLargeImm(SP, StackSize, false, TII, MBB, MBBI, dl);");
-// expandLargeImm(SP, StackSize, false, TII, MBB, MBBI, dl);
-
-}
-
-// This function eliminate ADJCALLSTACKDOWN,
-// ADJCALLSTACKUP pseudo instructions
-void Cpu0FrameLowering::
-eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
- MachineBasicBlock::iterator I) const {
- // Simply discard ADJCALLSTACKDOWN, ADJCALLSTACKUP instructions.
- MBB.erase(I);
-}
-
-// This method is called immediately before PrologEpilogInserter scans the
-// physical registers used to determine what callee saved registers should be
-// spilled. This method is optional.
-// Without this will have following errors,
-// Target didn't implement TargetInstrInfo::storeRegToStackSlot!
-// UNREACHABLE executed at /usr/local/llvm/3.1.test/cpu0/1/src/include/llvm/
-// Target/TargetInstrInfo.h:390!
-// Stack dump:
-// 0. Program arguments: /usr/local/llvm/3.1.test/cpu0/1/cmake_debug_build/
-// bin/llc -march=cpu0 -relocation-model=pic -filetype=asm ch0.bc -o
-// ch0.cpu0.s
-// 1. Running pass 'Function Pass Manager' on module 'ch0.bc'.
-// 2. Running pass 'Prologue/Epilogue Insertion & Frame Finalization' on
-// function '@main'
-// Aborted (core dumped)
-
-// Must exist
-// ldi $sp, $sp, 8
-//-> ret $lr
-// .set macro
-// .set reorder
-// .end main
-void Cpu0FrameLowering::
-processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
- RegScavenger *RS) const {
- MachineRegisterInfo& MRI = MF.getRegInfo();
-
- // FIXME: remove this code if register allocator can correctly mark
- // $fp and $ra used or unused.
-
- // The register allocator might determine $ra is used after seeing
- // instruction "jr $ra", but we do not want PrologEpilogInserter to insert
- // instructions to save/restore $ra unless there is a function call.
- // To correct this, $ra is explicitly marked unused if there is no
- // function call.
- if (MF.getFrameInfo()->hasCalls())
- MRI.setPhysRegUsed(Cpu0::LR);
- else {
- MRI.setPhysRegUnused(Cpu0::LR);
- }
-}
-
-
View
48 lib/Target/Cpu0/LLVMBackendTutorialExampleCode/10/1/Cpu0/Cpu0FrameLowering.h
@@ -1,48 +0,0 @@
-//===-- Cpu0FrameLowering.h - Define frame lowering for Cpu0 ----*- C++ -*-===//
-//
-// The LLVM Compiler Infrastructure