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Fix #460: reg1.isOverlapWith(reg2) and mem1.isOverlapWith(mem2)

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1 parent 247a0a4 commit 00c1f5a640ca290047887f35ef60a47951826644 @JonathanSalwan committed Jan 11, 2017
@@ -301,10 +301,7 @@ namespace triton {
const triton::arch::MemoryAccess& m1 = pair.first;
const triton::arch::MemoryAccess& m2 = target.getConstMemory();
- if (m1.getAddress() <= m2.getAddress() && m2.getAddress() < (m1.getAddress() + m1.getSize()))
- return true;
-
- if (m2.getAddress() <= m1.getAddress() && m1.getAddress() < (m2.getAddress() + m2.getSize()))
+ if (m1.isOverlapWith(m2))
return true;
}
break;
@@ -314,10 +311,8 @@ namespace triton {
const triton::arch::Register& r1 = pair.first;
const triton::arch::Register& r2 = target.getConstRegister();
- if (r1.getParent().getId() == r2.getParent().getId()) {
- if (r1.getLow() <= r2.getLow() && r2.getLow() <= r1.getHigh()) return true;
- if (r2.getLow() <= r1.getLow() && r1.getLow() <= r2.getHigh()) return true;
- }
+ if (r1.isOverlapWith(r2))
+ return true;
}
break;
@@ -340,10 +335,7 @@ namespace triton {
const triton::arch::MemoryAccess& m1 = pair.first;
const triton::arch::MemoryAccess& m2 = target.getConstMemory();
- if (m1.getAddress() <= m2.getAddress() && m2.getAddress() < (m1.getAddress() + m1.getSize()))
- return true;
-
- if (m2.getAddress() <= m1.getAddress() && m1.getAddress() < (m2.getAddress() + m2.getSize()))
+ if (m1.isOverlapWith(m2))
return true;
}
break;
@@ -353,10 +345,8 @@ namespace triton {
const triton::arch::Register& r1 = pair.first;
const triton::arch::Register& r2 = target.getConstRegister();
- if (r1.getParent().getId() == r2.getParent().getId()) {
- if (r1.getLow() <= r2.getLow() && r2.getLow() <= r1.getHigh()) return true;
- if (r2.getLow() <= r1.getLow() && r1.getLow() <= r2.getHigh()) return true;
- }
+ if (r1.isOverlapWith(r2))
+ return true;
}
break;
@@ -235,6 +235,13 @@ namespace triton {
}
+ bool MemoryAccess::isOverlapWith(const MemoryAccess& other) const {
+ if (this->getAddress() <= other.getAddress() && other.getAddress() < (this->getAddress() + this->getSize())) return true;
+ if (other.getAddress() <= this->getAddress() && this->getAddress() < (other.getAddress() + other.getSize())) return true;
+ return false;
+ }
+
+
bool MemoryAccess::hasConcreteValue(void) const {
return this->concreteValueDefined;
}
@@ -188,6 +188,15 @@ namespace triton {
}
+ bool Register::isOverlapWith(const Register& other) const {
+ if (this->getParent().getId() == other.getParent().getId()) {
+ if (this->getLow() <= other.getLow() && other.getLow() <= this->getHigh()) return true;
+ if (other.getLow() <= this->getLow() && this->getLow() <= other.getHigh()) return true;
+ }
+ return false;
+ }
+
+
bool Register::hasConcreteValue(void) const {
return this->concreteValueDefined;
}
@@ -123,6 +123,9 @@ e.g: `8`
- <b>\ref py_OPERAND_page getType(void)</b><br>
Returns type of the memory access. In this case this function returns `OPERAND.MEM`.
+- <b>bool isOverlapWith(\ref py_MemoryAccess_page other)</b><br>
+Returns true if `other` and `self` overlap.
+
- <b>void setBaseRegister(\ref py_Register_page reg)</b><br>
Sets the base register of the memory access.
@@ -284,6 +287,24 @@ namespace triton {
}
+ static PyObject* MemoryAccess_isOverlapWith(PyObject* self, PyObject* mem2) {
+ try {
+ triton::arch::MemoryAccess* mem1;
+
+ if (!PyMemoryAccess_Check(mem2))
+ return PyErr_Format(PyExc_TypeError, "MemoryAccess::isOverlapWith(): Expected a MemoryAccess as argument.");
+
+ mem1 = PyMemoryAccess_AsMemoryAccess(self);
+ if (mem1->isOverlapWith(*PyMemoryAccess_AsMemoryAccess(mem2)))
+ Py_RETURN_TRUE;
+ Py_RETURN_FALSE;
+ }
+ catch (const triton::exceptions::Exception& e) {
+ return PyErr_Format(PyExc_TypeError, "%s", e.what());
+ }
+ }
+
+
static PyObject* MemoryAccess_setBaseRegister(PyObject* self, PyObject* reg) {
try {
triton::arch::MemoryAccess* mem;
@@ -424,6 +445,7 @@ namespace triton {
{"getSegmentRegister", MemoryAccess_getSegmentRegister, METH_NOARGS, ""},
{"getSize", MemoryAccess_getSize, METH_NOARGS, ""},
{"getType", MemoryAccess_getType, METH_NOARGS, ""},
+ {"isOverlapWith", MemoryAccess_isOverlapWith, METH_O, ""},
{"setBaseRegister", MemoryAccess_setBaseRegister, METH_O, ""},
{"setConcreteValue", MemoryAccess_setConcreteValue, METH_O, ""},
{"setDisplacement", MemoryAccess_setDisplacement, METH_O, ""},
@@ -100,6 +100,9 @@ Returns true if the register is valid.
- <b>bool isFlag(void)</b><br>
Returns true if the register is a flag.
+- <b>bool isOverlapWith(\ref py_Register_page other)</b><br>
+Returns true if `other` and `self` overlap.
+
- <b>bool isRegister(void)</b><br>
Returns true if the register is a register.
@@ -229,6 +232,24 @@ namespace triton {
}
+ static PyObject* Register_isOverlapWith(PyObject* self, PyObject* reg2) {
+ try {
+ triton::arch::Register* reg1;
+
+ if (!PyRegister_Check(reg2))
+ return PyErr_Format(PyExc_TypeError, "Register::isOverlapWith(): Expected a Register as argument.");
+
+ reg1 = PyRegister_AsRegister(self);
+ if (reg1->isOverlapWith(*PyRegister_AsRegister(reg2)))
+ Py_RETURN_TRUE;
+ Py_RETURN_FALSE;
+ }
+ catch (const triton::exceptions::Exception& e) {
+ return PyErr_Format(PyExc_TypeError, "%s", e.what());
+ }
+ }
+
+
static PyObject* Register_setConcreteValue(PyObject* self, PyObject* value) {
triton::arch::Register* reg;
@@ -321,6 +342,7 @@ namespace triton {
{"getSize", Register_getSize, METH_NOARGS, ""},
{"getType", Register_getType, METH_NOARGS, ""},
{"isFlag", Register_isFlag, METH_NOARGS, ""},
+ {"isOverlapWith", Register_isOverlapWith, METH_O, ""},
{"isRegister", Register_isRegister, METH_NOARGS, ""},
{"isValid", Register_isValid, METH_NOARGS, ""},
{"setConcreteValue", Register_setConcreteValue, METH_O, ""},
@@ -166,6 +166,9 @@ namespace triton {
//! True if the memory is not empty.
bool isValid(void) const;
+ //! Returns true if `other` and `self` overlap.
+ bool isOverlapWith(const MemoryAccess& other) const;
+
//! Returns true if the memory contains a concrete value.
bool hasConcreteValue(void) const;
@@ -103,6 +103,9 @@ namespace triton {
//! Returns true if the register is immutable.
bool isImmutable(void) const;
+ //! Returns true if `other` and `self` overlap.
+ bool isOverlapWith(const Register& other) const;
+
//! Returns true if the register contains a concrete value.
bool hasConcreteValue(void) const;
@@ -1009,6 +1009,71 @@ def test_2():
except:
count += 1
+ setArchitecture(ARCH.X86_64)
+ if REG.AX.isOverlapWith(REG.EAX):
+ count += 1
+ else:
+ print '[KO] REG.AX.isOverlapWith(REG.EAX)'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if REG.AX.isOverlapWith(REG.RAX):
+ count += 1
+ else:
+ print '[KO] REG.AX.isOverlapWith(REG.RAX)'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if REG.RAX.isOverlapWith(REG.AX):
+ count += 1
+ else:
+ print '[KO] REG.RAX.isOverlapWith(REG.AX)'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if REG.AH.isOverlapWith(REG.AL):
+ print '[KO] REG.AH.isOverlapWith(REG.AL)'
+ print '\tOutput : True'
+ print '\tExpected : False'
+ return -1
+ else:
+ count += 1
+
+ if REG.AL.isOverlapWith(REG.AH):
+ print '[KO] REG.AL.isOverlapWith(REG.AH)'
+ print '\tOutput : True'
+ print '\tExpected : False'
+ return -1
+ else:
+ count += 1
+
+ if REG.AL.isOverlapWith(REG.AX):
+ count += 1
+ else:
+ print '[KO] REG.AL.isOverlapWith(REG.AX)'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if REG.AX.isOverlapWith(REG.AL):
+ count += 1
+ else:
+ print '[KO] REG.AX.isOverlapWith(REG.AL)'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if REG.EAX.isOverlapWith(REG.EDX):
+ print '[KO] REG.EAX.isOverlapWith(REG.EDX)'
+ print '\tOutput : True'
+ print '\tExpected : False'
+ return -1
+ else:
+ count += 1
+
return count
@@ -1192,6 +1257,70 @@ def test_3():
print '\tExpected : False'
return -1
+ if MemoryAccess(0x1000, 2).isOverlapWith(MemoryAccess(0x1001, 2)):
+ count += 1
+ else:
+ print '[KO] MemoryAccess(0x1000, 2).isOverlapWith(MemoryAccess(0x1001, 2))'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if MemoryAccess(0xfff, 2).isOverlapWith(MemoryAccess(0x1000, 2)):
+ count += 1
+ else:
+ print '[KO] MemoryAccess(0xfff, 2).isOverlapWith(MemoryAccess(0x1000, 2))'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x1004, 4)):
+ print '[KO] MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x1004, 4))'
+ print '\tOutput : True'
+ print '\tExpected : False'
+ return -1
+ else:
+ count += 1
+
+ if MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x1003, 2)):
+ count += 1
+ else:
+ print '[KO] MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x1003, 2))'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x1002, 1)):
+ count += 1
+ else:
+ print '[KO] MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x1002, 1))'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if MemoryAccess(0x1002, 1).isOverlapWith(MemoryAccess(0x1000, 4)):
+ count += 1
+ else:
+ print '[KO] MemoryAccess(0x1002, 1).isOverlapWith(MemoryAccess(0x1000, 4))'
+ print '\tOutput : False'
+ print '\tExpected : True'
+ return -1
+
+ if MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x10000, 4)):
+ print '[KO] MemoryAccess(0x1000, 4).isOverlapWith(MemoryAccess(0x10000, 4))'
+ print '\tOutput : True'
+ print '\tExpected : False'
+ return -1
+ else:
+ count += 1
+
+ if MemoryAccess(0x10000, 4).isOverlapWith(MemoryAccess(0x1000, 4)):
+ print '[KO] MemoryAccess(0x10000, 4).isOverlapWith(MemoryAccess(0x1000, 4))'
+ print '\tOutput : True'
+ print '\tExpected : False'
+ return -1
+ else:
+ count += 1
+
return count

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