diff --git a/include/arch/arm/cortex_m/asm_inline_gcc.h b/include/arch/arm/cortex_m/asm_inline_gcc.h
index d64bf7902b2a78..3266b440ba3552 100644
--- a/include/arch/arm/cortex_m/asm_inline_gcc.h
+++ b/include/arch/arm/cortex_m/asm_inline_gcc.h
@@ -175,6 +175,8 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
 #endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE */
 }
 
+/* Used to unconditionally enable interrupts when MULTITHREADING=n */
+#define Z_ARCH_INT_ENABLE() _arch_irq_unlock(0)
 
 #endif /* _ASMLANGUAGE */
 
diff --git a/include/arch/x86/arch.h b/include/arch/x86/arch.h
index 01bb41b4e55d93..c28a1a030985e8 100644
--- a/include/arch/x86/arch.h
+++ b/include/arch/x86/arch.h
@@ -445,6 +445,9 @@ static ALWAYS_INLINE void _arch_irq_unlock(unsigned int key)
 	_do_irq_unlock();
 }
 
+/* Used to unconditionally enable interrupts when MULTITHREADING=n */
+#define Z_ARCH_INT_ENABLE() _arch_irq_unlock(0x200)
+
 /**
  * The NANO_SOFT_IRQ macro must be used as the value for the @a irq parameter
  * to NANO_CPU_INT_REGISTER when connecting to an interrupt that does not
diff --git a/kernel/init.c b/kernel/init.c
index 878e27b55360a9..92cd6a48efe64d 100644
--- a/kernel/init.c
+++ b/kernel/init.c
@@ -436,6 +436,18 @@ u32_t z_early_boot_rand32_get(void)
 extern uintptr_t __stack_chk_guard;
 #endif /* CONFIG_STACK_CANARIES */
 
+#ifndef CONFIG_MULTITHREADING
+static void enable_interrupts(void)
+{
+#ifdef Z_ARCH_INT_ENABLE
+	Z_ARCH_INT_ENABLE();
+#else
+# pragma message "Z_ARCH_INT_ENABLE not defined for this architecture."
+# pragma message "Entry to MULTITHREADING=n app code will be with interrupts disabled."
+#endif
+}
+#endif
+
 /**
  *
  * @brief Initialize kernel
@@ -490,6 +502,7 @@ FUNC_NORETURN void _Cstart(void)
 	prepare_multithreading(dummy_thread);
 	switch_to_main_thread();
 #else
+	enable_interrupts();
 	bg_thread_main(NULL, NULL, NULL);
 
 	while (1) {