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PDP1 implementaton in Verilog
Verilog
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LICENSE
README.md
pdp1_alu.v
pdp1_cpu.v
pdp1_defs.v
pdp1_iot.v
pdp1_memory.v
pdp1_opr_decoder.v
pdp1_sbs.v
pdp1_sbs16.v
pdp1_sbs_decoder.v
pdp1_shrot.v
pdp1_shrot_lut.v
pdp1_sim.flatptr.v
pdp1_sim.lp.v
pdp1_skp_decoder.v
pdp1_tb.v
pdp1_write_decoder.v

README.md

PDP-1(D) in Verilog

Basic usage

  • Adjust the readmemh pdp1_memory.v to load a hex dump of some program (default is "test.hex")
  • The simulation will stop if the more than 1000000000 cycles have passed or if CPU is halted over the OPR instruction or gets an unknown instruction.
  • Default output is pdp1.vcd

Current Status

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