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This is the start towards proper SIMD support in Base. Currently the main things missing are support for masked/predicated instructions, and an intrinsic to load an arbitrarily chosen sized NTuple{n, VecElement} from a Memory. Many thanks to Alexandre Prieur for pair programming this with me, and @vtjnash, @gbaraldi and @vchuravy for answering the 50 million questions about C++/LLVM/debugging.

julia> f(a,b) = Core.Intrinsics.mul_float(a, b)
julia> a = ntuple(i->VecElement(sqrt(i)), 8);

julia> @code_llvm f(a,a)
; Function Signature: f(NTuple{8, VecElement{Float64}}, NTuple{8, VecElement{Float64}})
;  @ REPL[1]:1 within `f`
define <8 x double> @julia_f_949(<8 x double> %"a::Tuple", <8 x double> %"b::Tuple") #0 {
top:
  %0 = fmul <8 x double> %"a::Tuple", %"b::Tuple"
  ret <8 x double> %0
}

@nsajko nsajko added the compiler:simd instruction-level vectorization label Jul 13, 2024
@oscardssmith oscardssmith force-pushed the os/vectorized-intrinsics branch from 7ee1df5 to 6aced19 Compare July 28, 2024 03:13
@oscardssmith oscardssmith marked this pull request as draft July 28, 2024 12:01
@tecosaur
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tecosaur commented Sep 9, 2024

As one of the people rather excited about this, I'm wondering whether I might hope to see this progress to a non-draft PR in the near future, or whether this has some blocker/major further work needed? 🙂

@oscardssmith
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I'm unlikely to have time to do all the things that likely will be necessary to finish this off. there's no blockers, just a bunch more work.

@vchuravy vchuravy force-pushed the os/vectorized-intrinsics branch from e05da0d to b5117ac Compare October 7, 2024 10:02
export vload, vstore!, natural_vecwidth

# TODO: See C# and Co Vec type
# TODO: Hardware portable vector types...
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Would this include vscale? 👀

import Core.Intrinsics: add_float, sub_float, mul_float, div_float, muladd_float, neg_float

## floating point promotions ##
promote_rule(::Type{Vec{N, Float32}}, ::Type{Vec{N, Float16}}) where N = Vec{N, Float32}
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It is not obvious to me that these should be defined. When you are doing low level SIMD stuff you probably don't want to accidentally promote things and in case where you really want to work with different types, an explicit convert might be better for clarity?

@vchuravy vchuravy force-pushed the os/vectorized-intrinsics branch from 52aac7d to 039bf72 Compare September 26, 2025 18:02
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6 participants