{"payload":{"header_redesign_enabled":false,"results":[{"id":"366504198","archived":false,"color":"#b2b7f8","followers":2,"has_funding_file":false,"hl_name":"Kammann123/ev21g1","hl_trunc_description":"General purpose processor with a RISC architecture and a five stage pipeline, implemented on a Cyclone IV FPGA using a development board","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":366504198,"name":"ev21g1","owner_id":18316450,"owner_login":"Kammann123","updated_at":"2021-06-23T19:01:02.624Z","has_issues":true}},"sponsorable":false,"topics":["cpu","fpga","architecture","verilog","hdl","cpu-architecture","de0-nano"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":73,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AKammann123%252Fev21g1%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/Kammann123/ev21g1/star":{"post":"E2GWtVYFgWgyF-RpGii278R9nRtzz_GsvJ96t0qEx9kHYlCfsro_Gf6qJIIJhvmd0DNk3RbiKGsjvopueeBTGQ"},"/Kammann123/ev21g1/unstar":{"post":"K_RvuuGMsr4B_I1AcwgecVmKFTqI__od1H5QIEnKimS-d8U6MX0MGwbiQ4d2gYTCBIfmSRH6M_KtYvWLnLdFKg"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"4lvefjs8b4MjpYse9eIdRiD8Hal5ZyBUepAL37jeljbTAdrnSoFCS5mcbKwrR9Q5_F0nnd39na0SYEaSk7mC2A"}}},"title":"Repository search results"}