diff --git a/README.md b/README.md index 349973f..083dddf 100644 --- a/README.md +++ b/README.md @@ -5,7 +5,7 @@ ## Table of Contents -- [ZSWatch Hardware](#zswatch-hardware) +- [LoRa-GPS-Tracker](#lora-gps-tracker) - [Table of Contents](#table-of-contents) - [About](#about) - [Directory structure](#directory-structure) diff --git a/docs/images/Image_Complete.jpg b/docs/images/Image_Complete.jpg index 028e74b..fc404ac 100644 Binary files a/docs/images/Image_Complete.jpg and b/docs/images/Image_Complete.jpg differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.cyclo new file mode 100644 index 0000000..e16cfc8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.cyclo @@ -0,0 +1,6 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1303:22:LL_APB2_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1351:22:LL_APB2_GRP1_DisableClock 1 +../Core/Src/adc.c:30:6:MX_ADC_Init 2 +../Core/Src/adc.c:72:6:HAL_ADC_MspInit 2 +../Core/Src/adc.c:99:6:HAL_ADC_MspDeInit 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.d new file mode 100644 index 0000000..16089c4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.d @@ -0,0 +1,83 @@ +Core/Src/adc.o: ../Core/Src/adc.c ../Core/Inc/adc.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/adc.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.o new file mode 100644 index 0000000..c3c88d2 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.su new file mode 100644 index 0000000..34d97d1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/adc.su @@ -0,0 +1,6 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1303:22:LL_APB2_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1351:22:LL_APB2_GRP1_DisableClock 16 static +../Core/Src/adc.c:30:6:MX_ADC_Init 8 static +../Core/Src/adc.c:72:6:HAL_ADC_MspInit 40 static +../Core/Src/adc.c:99:6:HAL_ADC_MspDeInit 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.cyclo new file mode 100644 index 0000000..72d8471 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:287:22:LL_AHB1_GRP1_EnableClock 1 +../Core/Src/dma.c:39:6:MX_DMA_Init 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.d new file mode 100644 index 0000000..5b9e3fc --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.d @@ -0,0 +1,83 @@ +Core/Src/dma.o: ../Core/Src/dma.c ../Core/Inc/dma.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/dma.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.o new file mode 100644 index 0000000..a159853 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.su new file mode 100644 index 0000000..6fe4ee8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/dma.su @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:287:22:LL_AHB1_GRP1_EnableClock 24 static +../Core/Src/dma.c:39:6:MX_DMA_Init 8 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.cyclo new file mode 100644 index 0000000..691d8a1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Core/Src/gpio.c:44:6:MX_GPIO_Init 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.d new file mode 100644 index 0000000..f22943d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.d @@ -0,0 +1,83 @@ +Core/Src/gpio.o: ../Core/Src/gpio.c ../Core/Inc/gpio.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/gpio.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.o new file mode 100644 index 0000000..90863ff Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.su new file mode 100644 index 0000000..3b73659 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/gpio.su @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Core/Src/gpio.c:44:6:MX_GPIO_Init 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.cyclo new file mode 100644 index 0000000..de785b2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.cyclo @@ -0,0 +1,4 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1257:22:LL_RCC_LSE_SetDriveCapability 1 +../Core/Src/main.c:68:5:main 1 +../Core/Src/main.c:118:6:SystemClock_Config 3 +../Core/Src/main.c:170:6:Error_Handler 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.d new file mode 100644 index 0000000..c72c650 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.d @@ -0,0 +1,91 @@ +Core/Src/main.o: ../Core/Src/main.c ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/adc.h ../Core/Inc/main.h ../Core/Inc/dma.h \ + ../Core/Inc/usart.h ../SubGHz_Phy/App/app_subghz_phy.h \ + ../Core/Inc/gpio.h +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/adc.h: +../Core/Inc/main.h: +../Core/Inc/dma.h: +../Core/Inc/usart.h: +../SubGHz_Phy/App/app_subghz_phy.h: +../Core/Inc/gpio.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.o new file mode 100644 index 0000000..9da4806 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.su new file mode 100644 index 0000000..600213c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/main.su @@ -0,0 +1,4 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1257:22:LL_RCC_LSE_SetDriveCapability 16 static +../Core/Src/main.c:68:5:main 8 static +../Core/Src/main.c:118:6:SystemClock_Config 112 static +../Core/Src/main.c:170:6:Error_Handler 4 static,ignoring_inline_asm diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.cyclo new file mode 100644 index 0000000..f9042ba --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.cyclo @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2331:22:LL_RCC_EnableRTC 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2341:22:LL_RCC_DisableRTC 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:914:22:LL_APB1_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1018:22:LL_APB1_GRP1_DisableClock 1 +../Core/Src/rtc.c:30:6:MX_RTC_Init 4 +../Core/Src/rtc.c:79:6:HAL_RTC_MspInit 3 +../Core/Src/rtc.c:114:6:HAL_RTC_MspDeInit 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.d new file mode 100644 index 0000000..543d8d2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.d @@ -0,0 +1,83 @@ +Core/Src/rtc.o: ../Core/Src/rtc.c ../Core/Inc/rtc.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/rtc.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.o new file mode 100644 index 0000000..e506bc5 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.su new file mode 100644 index 0000000..5ae8751 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/rtc.su @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2331:22:LL_RCC_EnableRTC 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2341:22:LL_RCC_DisableRTC 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:914:22:LL_APB1_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1018:22:LL_APB1_GRP1_DisableClock 16 static +../Core/Src/rtc.c:30:6:MX_RTC_Init 8 static +../Core/Src/rtc.c:79:6:HAL_RTC_MspInit 72 static +../Core/Src/rtc.c:114:6:HAL_RTC_MspDeInit 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.cyclo new file mode 100644 index 0000000..d946d53 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.cyclo @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2196:22:LL_PWR_ClearFlag_C1STOP_C1STB 1 +../Core/Src/stm32_lpm_if.c:78:6:PWR_EnterOffMode 1 +../Core/Src/stm32_lpm_if.c:85:6:PWR_ExitOffMode 1 +../Core/Src/stm32_lpm_if.c:92:6:PWR_EnterStopMode 1 +../Core/Src/stm32_lpm_if.c:110:6:PWR_ExitStopMode 1 +../Core/Src/stm32_lpm_if.c:129:6:PWR_EnterSleepMode 1 +../Core/Src/stm32_lpm_if.c:145:6:PWR_ExitSleepMode 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.d new file mode 100644 index 0000000..6e63dbb --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.d @@ -0,0 +1,111 @@ +Core/Src/stm32_lpm_if.o: ../Core/Src/stm32_lpm_if.c \ + ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h \ + ../Utilities/lpm/tiny_lpm/stm32_lpm.h ../Core/Inc/stm32_lpm_if.h \ + ../Core/Inc/usart_if.h ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Core/Inc/usart.h ../Core/Inc/dma.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Utilities/lpm/tiny_lpm/stm32_lpm.h: +../Core/Inc/stm32_lpm_if.h: +../Core/Inc/usart_if.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Core/Inc/usart.h: +../Core/Inc/dma.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.o new file mode 100644 index 0000000..d0116b7 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.su new file mode 100644 index 0000000..0150788 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32_lpm_if.su @@ -0,0 +1,7 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2196:22:LL_PWR_ClearFlag_C1STOP_C1STB 4 static +../Core/Src/stm32_lpm_if.c:78:6:PWR_EnterOffMode 4 static +../Core/Src/stm32_lpm_if.c:85:6:PWR_ExitOffMode 4 static +../Core/Src/stm32_lpm_if.c:92:6:PWR_EnterStopMode 8 static +../Core/Src/stm32_lpm_if.c:110:6:PWR_ExitStopMode 8 static +../Core/Src/stm32_lpm_if.c:129:6:PWR_EnterSleepMode 8 static +../Core/Src/stm32_lpm_if.c:145:6:PWR_ExitSleepMode 8 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.cyclo new file mode 100644 index 0000000..954d57c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.cyclo @@ -0,0 +1 @@ +../Core/Src/stm32wlxx_hal_msp.c:64:6:HAL_MspInit 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.d new file mode 100644 index 0000000..41f9c4a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.d @@ -0,0 +1,82 @@ +Core/Src/stm32wlxx_hal_msp.o: ../Core/Src/stm32wlxx_hal_msp.c \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.o new file mode 100644 index 0000000..bc8bf6d Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.su new file mode 100644 index 0000000..eaefb05 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_hal_msp.su @@ -0,0 +1 @@ +../Core/Src/stm32wlxx_hal_msp.c:64:6:HAL_MspInit 4 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.cyclo new file mode 100644 index 0000000..c635087 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.cyclo @@ -0,0 +1,15 @@ +../Core/Src/stm32wlxx_it.c:73:6:NMI_Handler 1 +../Core/Src/stm32wlxx_it.c:88:6:HardFault_Handler 1 +../Core/Src/stm32wlxx_it.c:103:6:MemManage_Handler 1 +../Core/Src/stm32wlxx_it.c:118:6:BusFault_Handler 1 +../Core/Src/stm32wlxx_it.c:133:6:UsageFault_Handler 1 +../Core/Src/stm32wlxx_it.c:148:6:SVC_Handler 1 +../Core/Src/stm32wlxx_it.c:161:6:DebugMon_Handler 1 +../Core/Src/stm32wlxx_it.c:174:6:PendSV_Handler 1 +../Core/Src/stm32wlxx_it.c:187:6:SysTick_Handler 1 +../Core/Src/stm32wlxx_it.c:208:6:TAMP_STAMP_LSECSS_SSRU_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:222:6:RTC_WKUP_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:236:6:DMA1_Channel1_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:250:6:USART1_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:264:6:LPUART1_IRQHandler 1 +../Core/Src/stm32wlxx_it.c:278:6:SUBGHZ_Radio_IRQHandler 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.d new file mode 100644 index 0000000..fd195a5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.d @@ -0,0 +1,84 @@ +Core/Src/stm32wlxx_it.o: ../Core/Src/stm32wlxx_it.c ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/stm32wlxx_it.h +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/stm32wlxx_it.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.o new file mode 100644 index 0000000..cb4d4c0 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.su new file mode 100644 index 0000000..4587b39 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/stm32wlxx_it.su @@ -0,0 +1,15 @@ +../Core/Src/stm32wlxx_it.c:73:6:NMI_Handler 4 static +../Core/Src/stm32wlxx_it.c:88:6:HardFault_Handler 4 static +../Core/Src/stm32wlxx_it.c:103:6:MemManage_Handler 4 static +../Core/Src/stm32wlxx_it.c:118:6:BusFault_Handler 4 static +../Core/Src/stm32wlxx_it.c:133:6:UsageFault_Handler 4 static +../Core/Src/stm32wlxx_it.c:148:6:SVC_Handler 4 static +../Core/Src/stm32wlxx_it.c:161:6:DebugMon_Handler 4 static +../Core/Src/stm32wlxx_it.c:174:6:PendSV_Handler 4 static +../Core/Src/stm32wlxx_it.c:187:6:SysTick_Handler 8 static +../Core/Src/stm32wlxx_it.c:208:6:TAMP_STAMP_LSECSS_SSRU_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:222:6:RTC_WKUP_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:236:6:DMA1_Channel1_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:250:6:USART1_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:264:6:LPUART1_IRQHandler 8 static +../Core/Src/stm32wlxx_it.c:278:6:SUBGHZ_Radio_IRQHandler 8 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subdir.mk new file mode 100644 index 0000000..9e57a8d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subdir.mk @@ -0,0 +1,75 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Core/Src/adc.c \ +../Core/Src/dma.c \ +../Core/Src/gpio.c \ +../Core/Src/main.c \ +../Core/Src/rtc.c \ +../Core/Src/stm32_lpm_if.c \ +../Core/Src/stm32wlxx_hal_msp.c \ +../Core/Src/stm32wlxx_it.c \ +../Core/Src/subghz.c \ +../Core/Src/sys_app.c \ +../Core/Src/sys_debug.c \ +../Core/Src/syscalls.c \ +../Core/Src/sysmem.c \ +../Core/Src/system_stm32wlxx.c \ +../Core/Src/timer_if.c \ +../Core/Src/usart.c \ +../Core/Src/usart_if.c + +OBJS += \ +./Core/Src/adc.o \ +./Core/Src/dma.o \ +./Core/Src/gpio.o \ +./Core/Src/main.o \ +./Core/Src/rtc.o \ +./Core/Src/stm32_lpm_if.o \ +./Core/Src/stm32wlxx_hal_msp.o \ +./Core/Src/stm32wlxx_it.o \ +./Core/Src/subghz.o \ +./Core/Src/sys_app.o \ +./Core/Src/sys_debug.o \ +./Core/Src/syscalls.o \ +./Core/Src/sysmem.o \ +./Core/Src/system_stm32wlxx.o \ +./Core/Src/timer_if.o \ +./Core/Src/usart.o \ +./Core/Src/usart_if.o + +C_DEPS += \ +./Core/Src/adc.d \ +./Core/Src/dma.d \ +./Core/Src/gpio.d \ +./Core/Src/main.d \ +./Core/Src/rtc.d \ +./Core/Src/stm32_lpm_if.d \ +./Core/Src/stm32wlxx_hal_msp.d \ +./Core/Src/stm32wlxx_it.d \ +./Core/Src/subghz.d \ +./Core/Src/sys_app.d \ +./Core/Src/sys_debug.d \ +./Core/Src/syscalls.d \ +./Core/Src/sysmem.d \ +./Core/Src/system_stm32wlxx.d \ +./Core/Src/timer_if.d \ +./Core/Src/usart.d \ +./Core/Src/usart_if.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Src/%.o Core/Src/%.su Core/Src/%.cyclo: ../Core/Src/%.c Core/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Core-2f-Src + +clean-Core-2f-Src: + -$(RM) ./Core/Src/adc.cyclo ./Core/Src/adc.d ./Core/Src/adc.o ./Core/Src/adc.su ./Core/Src/dma.cyclo ./Core/Src/dma.d ./Core/Src/dma.o ./Core/Src/dma.su ./Core/Src/gpio.cyclo ./Core/Src/gpio.d ./Core/Src/gpio.o ./Core/Src/gpio.su ./Core/Src/main.cyclo ./Core/Src/main.d ./Core/Src/main.o ./Core/Src/main.su ./Core/Src/rtc.cyclo ./Core/Src/rtc.d ./Core/Src/rtc.o ./Core/Src/rtc.su ./Core/Src/stm32_lpm_if.cyclo ./Core/Src/stm32_lpm_if.d ./Core/Src/stm32_lpm_if.o ./Core/Src/stm32_lpm_if.su ./Core/Src/stm32wlxx_hal_msp.cyclo ./Core/Src/stm32wlxx_hal_msp.d ./Core/Src/stm32wlxx_hal_msp.o ./Core/Src/stm32wlxx_hal_msp.su ./Core/Src/stm32wlxx_it.cyclo ./Core/Src/stm32wlxx_it.d ./Core/Src/stm32wlxx_it.o ./Core/Src/stm32wlxx_it.su ./Core/Src/subghz.cyclo ./Core/Src/subghz.d ./Core/Src/subghz.o ./Core/Src/subghz.su ./Core/Src/sys_app.cyclo ./Core/Src/sys_app.d ./Core/Src/sys_app.o ./Core/Src/sys_app.su ./Core/Src/sys_debug.cyclo ./Core/Src/sys_debug.d ./Core/Src/sys_debug.o ./Core/Src/sys_debug.su ./Core/Src/syscalls.cyclo ./Core/Src/syscalls.d ./Core/Src/syscalls.o ./Core/Src/syscalls.su ./Core/Src/sysmem.cyclo ./Core/Src/sysmem.d ./Core/Src/sysmem.o ./Core/Src/sysmem.su ./Core/Src/system_stm32wlxx.cyclo ./Core/Src/system_stm32wlxx.d ./Core/Src/system_stm32wlxx.o ./Core/Src/system_stm32wlxx.su ./Core/Src/timer_if.cyclo ./Core/Src/timer_if.d ./Core/Src/timer_if.o ./Core/Src/timer_if.su ./Core/Src/usart.cyclo ./Core/Src/usart.d ./Core/Src/usart.o ./Core/Src/usart.su ./Core/Src/usart_if.cyclo ./Core/Src/usart_if.d ./Core/Src/usart_if.o ./Core/Src/usart_if.su + +.PHONY: clean-Core-2f-Src + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.cyclo new file mode 100644 index 0000000..17cb04f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.cyclo @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1488:22:LL_APB3_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1516:22:LL_APB3_GRP1_DisableClock 1 +../Core/Src/subghz.c:30:6:MX_SUBGHZ_Init 2 +../Core/Src/subghz.c:51:6:HAL_SUBGHZ_MspInit 1 +../Core/Src/subghz.c:68:6:HAL_SUBGHZ_MspDeInit 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.d new file mode 100644 index 0000000..34c779e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.d @@ -0,0 +1,83 @@ +Core/Src/subghz.o: ../Core/Src/subghz.c ../Core/Inc/subghz.h \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Core/Inc/subghz.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.o new file mode 100644 index 0000000..da3260f Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.su new file mode 100644 index 0000000..d2f1f5f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/subghz.su @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1488:22:LL_APB3_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1516:22:LL_APB3_GRP1_DisableClock 16 static +../Core/Src/subghz.c:30:6:MX_SUBGHZ_Init 8 static +../Core/Src/subghz.c:51:6:HAL_SUBGHZ_MspInit 16 static +../Core/Src/subghz.c:68:6:HAL_SUBGHZ_MspDeInit 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.cyclo new file mode 100644 index 0000000..c04a4c2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 1 +../Core/Src/sys_app.c:83:6:SystemApp_Init 1 +../Core/Src/sys_app.c:125:6:UTIL_SEQ_Idle 1 +../Core/Src/sys_app.c:142:13:TimestampNow 1 +../Core/Src/sys_app.c:156:6:UTIL_ADV_TRACE_PreSendHook 1 +../Core/Src/sys_app.c:167:6:UTIL_ADV_TRACE_PostSendHook 1 +../Core/Src/sys_app.c:178:13:tiny_snprintf_like 1 +../Core/Src/sys_app.c:201:10:HAL_GetTick 2 +../Core/Src/sys_app.c:233:6:HAL_Delay 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.d new file mode 100644 index 0000000..f1c6550 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.d @@ -0,0 +1,118 @@ +Core/Src/sys_app.o: ../Core/Src/sys_app.c ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h ../Core/Inc/sys_app.h \ + ../Core/Inc/sys_conf.h ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Utilities/sequencer/stm32_seq.h \ + ../Utilities/misc/stm32_systime.h ../Utilities/lpm/tiny_lpm/stm32_lpm.h \ + ../Core/Inc/timer_if.h ../Utilities/timer/stm32_timer.h \ + ../Core/Inc/utilities_def.h ../Core/Inc/sys_debug.h \ + ../Core/Inc/platform.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/sys_app.h: +../Core/Inc/sys_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Utilities/sequencer/stm32_seq.h: +../Utilities/misc/stm32_systime.h: +../Utilities/lpm/tiny_lpm/stm32_lpm.h: +../Core/Inc/timer_if.h: +../Utilities/timer/stm32_timer.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/platform.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.o new file mode 100644 index 0000000..5edb7ef Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.su new file mode 100644 index 0000000..89cde6a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_app.su @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 16 static +../Core/Src/sys_app.c:83:6:SystemApp_Init 8 static +../Core/Src/sys_app.c:125:6:UTIL_SEQ_Idle 8 static +../Core/Src/sys_app.c:142:13:TimestampNow 32 static +../Core/Src/sys_app.c:156:6:UTIL_ADV_TRACE_PreSendHook 8 static +../Core/Src/sys_app.c:167:6:UTIL_ADV_TRACE_PostSendHook 8 static +../Core/Src/sys_app.c:178:13:tiny_snprintf_like 24 static +../Core/Src/sys_app.c:201:10:HAL_GetTick 16 static +../Core/Src/sys_app.c:233:6:HAL_Delay 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.cyclo new file mode 100644 index 0000000..98eb0d5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.cyclo @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 1 +../Core/Src/sys_debug.c:64:6:DBG_Init 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.d new file mode 100644 index 0000000..774eeca --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.d @@ -0,0 +1,98 @@ +Core/Src/sys_debug.o: ../Core/Src/sys_debug.c ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.o new file mode 100644 index 0000000..919944c Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.su new file mode 100644 index 0000000..f9c1850 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sys_debug.su @@ -0,0 +1,2 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 16 static +../Core/Src/sys_debug.c:64:6:DBG_Init 8 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.cyclo new file mode 100644 index 0000000..6cbfdd0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.cyclo @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 1 +../Core/Src/syscalls.c:48:5:_getpid 1 +../Core/Src/syscalls.c:53:5:_kill 1 +../Core/Src/syscalls.c:61:6:_exit 1 +../Core/Src/syscalls.c:67:27:_read 2 +../Core/Src/syscalls.c:80:27:_write 2 +../Core/Src/syscalls.c:92:5:_close 1 +../Core/Src/syscalls.c:99:5:_fstat 1 +../Core/Src/syscalls.c:106:5:_isatty 1 +../Core/Src/syscalls.c:112:5:_lseek 1 +../Core/Src/syscalls.c:120:5:_open 1 +../Core/Src/syscalls.c:128:5:_wait 1 +../Core/Src/syscalls.c:135:5:_unlink 1 +../Core/Src/syscalls.c:142:5:_times 1 +../Core/Src/syscalls.c:148:5:_stat 1 +../Core/Src/syscalls.c:155:5:_link 1 +../Core/Src/syscalls.c:163:5:_fork 1 +../Core/Src/syscalls.c:169:5:_execve 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.d new file mode 100644 index 0000000..8667c70 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.d @@ -0,0 +1 @@ +Core/Src/syscalls.o: ../Core/Src/syscalls.c diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.o new file mode 100644 index 0000000..372b499 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.su new file mode 100644 index 0000000..50b547a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/syscalls.su @@ -0,0 +1,18 @@ +../Core/Src/syscalls.c:44:6:initialise_monitor_handles 4 static +../Core/Src/syscalls.c:48:5:_getpid 4 static +../Core/Src/syscalls.c:53:5:_kill 16 static +../Core/Src/syscalls.c:61:6:_exit 16 static +../Core/Src/syscalls.c:67:27:_read 32 static +../Core/Src/syscalls.c:80:27:_write 32 static +../Core/Src/syscalls.c:92:5:_close 16 static +../Core/Src/syscalls.c:99:5:_fstat 16 static +../Core/Src/syscalls.c:106:5:_isatty 16 static +../Core/Src/syscalls.c:112:5:_lseek 24 static +../Core/Src/syscalls.c:120:5:_open 12 static +../Core/Src/syscalls.c:128:5:_wait 16 static +../Core/Src/syscalls.c:135:5:_unlink 16 static +../Core/Src/syscalls.c:142:5:_times 16 static +../Core/Src/syscalls.c:148:5:_stat 16 static +../Core/Src/syscalls.c:155:5:_link 16 static +../Core/Src/syscalls.c:163:5:_fork 8 static +../Core/Src/syscalls.c:169:5:_execve 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.cyclo new file mode 100644 index 0000000..0090c10 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.cyclo @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 3 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.d new file mode 100644 index 0000000..74fecf9 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.d @@ -0,0 +1 @@ +Core/Src/sysmem.o: ../Core/Src/sysmem.c diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.o new file mode 100644 index 0000000..eaf8d14 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.su new file mode 100644 index 0000000..12d5f17 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/sysmem.su @@ -0,0 +1 @@ +../Core/Src/sysmem.c:53:7:_sbrk 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.cyclo new file mode 100644 index 0000000..ca65f98 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.cyclo @@ -0,0 +1,2 @@ +../Core/Src/system_stm32wlxx.c:211:6:SystemInit 1 +../Core/Src/system_stm32wlxx.c:266:6:SystemCoreClockUpdate 8 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.d new file mode 100644 index 0000000..22f2255 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.d @@ -0,0 +1,81 @@ +Core/Src/system_stm32wlxx.o: ../Core/Src/system_stm32wlxx.c \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.o new file mode 100644 index 0000000..c0bd0ab Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.su new file mode 100644 index 0000000..bd11e85 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/system_stm32wlxx.su @@ -0,0 +1,2 @@ +../Core/Src/system_stm32wlxx.c:211:6:SystemInit 4 static +../Core/Src/system_stm32wlxx.c:266:6:SystemCoreClockUpdate 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.cyclo new file mode 100644 index 0000000..5c07a1f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.cyclo @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h:1526:26:LL_RTC_TIME_GetSubSecond 1 +../Core/Src/timer_if.c:181:21:TIMER_IF_Init 2 +../Core/Src/timer_if.c:218:21:TIMER_IF_StartTimer 2 +../Core/Src/timer_if.c:246:21:TIMER_IF_StopTimer 1 +../Core/Src/timer_if.c:264:10:TIMER_IF_SetTimerContext 1 +../Core/Src/timer_if.c:278:10:TIMER_IF_GetTimerContext 1 +../Core/Src/timer_if.c:289:10:TIMER_IF_GetTimerElapsedTime 1 +../Core/Src/timer_if.c:302:10:TIMER_IF_GetTimerValue 2 +../Core/Src/timer_if.c:318:10:TIMER_IF_GetMinimumTimeout 1 +../Core/Src/timer_if.c:331:10:TIMER_IF_Convert_ms2Tick 1 +../Core/Src/timer_if.c:344:10:TIMER_IF_Convert_Tick2ms 1 +../Core/Src/timer_if.c:357:6:TIMER_IF_DelayMs 2 +../Core/Src/timer_if.c:375:6:HAL_RTC_AlarmAEventCallback 1 +../Core/Src/timer_if.c:386:6:HAL_RTCEx_SSRUEventCallback 1 +../Core/Src/timer_if.c:401:10:TIMER_IF_GetTime 1 +../Core/Src/timer_if.c:425:6:TIMER_IF_BkUp_Write_Seconds 1 +../Core/Src/timer_if.c:436:6:TIMER_IF_BkUp_Write_SubSeconds 1 +../Core/Src/timer_if.c:447:10:TIMER_IF_BkUp_Read_Seconds 1 +../Core/Src/timer_if.c:460:10:TIMER_IF_BkUp_Read_SubSeconds 1 +../Core/Src/timer_if.c:478:13:TIMER_IF_BkUp_Write_MSBticks 1 +../Core/Src/timer_if.c:489:17:TIMER_IF_BkUp_Read_MSBticks 1 +../Core/Src/timer_if.c:502:24:GetTimerTicks 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.d new file mode 100644 index 0000000..c2deba1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.d @@ -0,0 +1,100 @@ +Core/Src/timer_if.o: ../Core/Src/timer_if.c ../Core/Inc/timer_if.h \ + ../Utilities/timer/stm32_timer.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/Inc/utilities_conf.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../Utilities/misc/stm32_systime.h \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/rtc.h ../Core/Inc/main.h ../Core/Inc/utilities_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h +../Core/Inc/timer_if.h: +../Utilities/timer/stm32_timer.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/Inc/utilities_conf.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Utilities/misc/stm32_systime.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/rtc.h: +../Core/Inc/main.h: +../Core/Inc/utilities_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.o new file mode 100644 index 0000000..0c3ac01 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.su new file mode 100644 index 0000000..006e62b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/timer_if.su @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h:1526:26:LL_RTC_TIME_GetSubSecond 16 static +../Core/Src/timer_if.c:181:21:TIMER_IF_Init 16 static +../Core/Src/timer_if.c:218:21:TIMER_IF_StartTimer 64 static +../Core/Src/timer_if.c:246:21:TIMER_IF_StopTimer 16 static +../Core/Src/timer_if.c:264:10:TIMER_IF_SetTimerContext 8 static +../Core/Src/timer_if.c:278:10:TIMER_IF_GetTimerContext 4 static +../Core/Src/timer_if.c:289:10:TIMER_IF_GetTimerElapsedTime 16 static +../Core/Src/timer_if.c:302:10:TIMER_IF_GetTimerValue 16 static +../Core/Src/timer_if.c:318:10:TIMER_IF_GetMinimumTimeout 16 static +../Core/Src/timer_if.c:331:10:TIMER_IF_Convert_ms2Tick 32 static +../Core/Src/timer_if.c:344:10:TIMER_IF_Convert_Tick2ms 48 static +../Core/Src/timer_if.c:357:6:TIMER_IF_DelayMs 24 static,ignoring_inline_asm +../Core/Src/timer_if.c:375:6:HAL_RTC_AlarmAEventCallback 16 static +../Core/Src/timer_if.c:386:6:HAL_RTCEx_SSRUEventCallback 24 static +../Core/Src/timer_if.c:401:10:TIMER_IF_GetTime 80 static +../Core/Src/timer_if.c:425:6:TIMER_IF_BkUp_Write_Seconds 16 static +../Core/Src/timer_if.c:436:6:TIMER_IF_BkUp_Write_SubSeconds 16 static +../Core/Src/timer_if.c:447:10:TIMER_IF_BkUp_Read_Seconds 16 static +../Core/Src/timer_if.c:460:10:TIMER_IF_BkUp_Read_SubSeconds 16 static +../Core/Src/timer_if.c:478:13:TIMER_IF_BkUp_Write_MSBticks 16 static +../Core/Src/timer_if.c:489:17:TIMER_IF_BkUp_Read_MSBticks 16 static +../Core/Src/timer_if.c:502:24:GetTimerTicks 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.cyclo new file mode 100644 index 0000000..40dc66f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:935:22:LL_APB1_GRP2_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1034:22:LL_APB1_GRP2_DisableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1303:22:LL_APB2_GRP1_EnableClock 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1351:22:LL_APB2_GRP1_DisableClock 1 +../Core/Src/usart.c:36:6:MX_LPUART1_UART_Init 5 +../Core/Src/usart.c:82:6:MX_USART1_UART_Init 5 +../Core/Src/usart.c:125:6:HAL_UART_MspInit 6 +../Core/Src/usart.c:224:6:HAL_UART_MspDeInit 3 +../Core/Src/usart.c:273:9:MX_USART1_GPS_Init 3 +../Core/Src/usart.c:290:9:MX_USART1_GPS_SendCommand 6 +../Core/Src/usart.c:345:6:MX_USART1_GPS_Sleep 3 +../Core/Src/usart.c:358:6:MX_USART1_GPS_WakeUp 1 +../Core/Src/usart.c:363:9:MX_USART1_GPS_GetNMEA 5 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.d new file mode 100644 index 0000000..a61f941 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.d @@ -0,0 +1,96 @@ +Core/Src/usart.o: ../Core/Src/usart.c ../Core/Inc/usart.h \ + ../Core/Inc/main.h ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/sys_app.h ../Core/Inc/sys_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/sys_app.h: +../Core/Inc/sys_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.o new file mode 100644 index 0000000..8ed70b4 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.su new file mode 100644 index 0000000..935866e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart.su @@ -0,0 +1,14 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:935:22:LL_APB1_GRP2_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1034:22:LL_APB1_GRP2_DisableClock 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1303:22:LL_APB2_GRP1_EnableClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1351:22:LL_APB2_GRP1_DisableClock 16 static +../Core/Src/usart.c:36:6:MX_LPUART1_UART_Init 8 static +../Core/Src/usart.c:82:6:MX_USART1_UART_Init 8 static +../Core/Src/usart.c:125:6:HAL_UART_MspInit 96 static +../Core/Src/usart.c:224:6:HAL_UART_MspDeInit 16 static +../Core/Src/usart.c:273:9:MX_USART1_GPS_Init 16 static +../Core/Src/usart.c:290:9:MX_USART1_GPS_SendCommand 288 static +../Core/Src/usart.c:345:6:MX_USART1_GPS_Sleep 8 static +../Core/Src/usart.c:358:6:MX_USART1_GPS_WakeUp 8 static +../Core/Src/usart.c:363:9:MX_USART1_GPS_GetNMEA 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.cyclo new file mode 100644 index 0000000..9c55273 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.cyclo @@ -0,0 +1,11 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1374:22:LL_APB2_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1397:22:LL_APB2_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 1 +../Core/Src/usart_if.c:101:25:vcom_Init 1 +../Core/Src/usart_if.c:116:25:vcom_DeInit 1 +../Core/Src/usart_if.c:139:6:vcom_Trace 1 +../Core/Src/usart_if.c:150:25:vcom_Trace_DMA 1 +../Core/Src/usart_if.c:162:25:vcom_ReceiveInit 3 +../Core/Src/usart_if.c:198:6:vcom_Resume 3 +../Core/Src/usart_if.c:219:6:HAL_UART_TxCpltCallback 2 +../Core/Src/usart_if.c:234:6:HAL_UART_RxCpltCallback 4 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.d new file mode 100644 index 0000000..32467ce --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.d @@ -0,0 +1,96 @@ +Core/Src/usart_if.o: ../Core/Src/usart_if.c ../Core/Inc/usart_if.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/usart.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/dma.h +../Core/Inc/usart_if.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/dma.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.o new file mode 100644 index 0000000..a33b303 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.su b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.su new file mode 100644 index 0000000..e623fbb --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Src/usart_if.su @@ -0,0 +1,11 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1374:22:LL_APB2_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1397:22:LL_APB2_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 16 static +../Core/Src/usart_if.c:101:25:vcom_Init 16 static +../Core/Src/usart_if.c:116:25:vcom_DeInit 8 static +../Core/Src/usart_if.c:139:6:vcom_Trace 16 static +../Core/Src/usart_if.c:150:25:vcom_Trace_DMA 16 static +../Core/Src/usart_if.c:162:25:vcom_ReceiveInit 24 static +../Core/Src/usart_if.c:198:6:vcom_Resume 8 static +../Core/Src/usart_if.c:219:6:HAL_UART_TxCpltCallback 16 static +../Core/Src/usart_if.c:234:6:HAL_UART_RxCpltCallback 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/startup_stm32wle5ccux.d b/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/startup_stm32wle5ccux.d new file mode 100644 index 0000000..4a973fe --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/startup_stm32wle5ccux.d @@ -0,0 +1,2 @@ +Core/Startup/startup_stm32wle5ccux.o: \ + ../Core/Startup/startup_stm32wle5ccux.s diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/startup_stm32wle5ccux.o b/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/startup_stm32wle5ccux.o new file mode 100644 index 0000000..b0e1b06 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/startup_stm32wle5ccux.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/subdir.mk new file mode 100644 index 0000000..cf651bc --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Core/Startup/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Core/Startup/startup_stm32wle5ccux.s + +OBJS += \ +./Core/Startup/startup_stm32wle5ccux.o + +S_DEPS += \ +./Core/Startup/startup_stm32wle5ccux.d + + +# Each subdirectory must supply rules for building sources it contributes +Core/Startup/%.o: ../Core/Startup/%.s Core/Startup/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Core-2f-Startup + +clean-Core-2f-Startup: + -$(RM) ./Core/Startup/startup_stm32wle5ccux.d ./Core/Startup/startup_stm32wle5ccux.o + +.PHONY: clean-Core-2f-Startup + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.d new file mode 100644 index 0000000..a7d8cb1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.d @@ -0,0 +1,2 @@ +Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o: \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.c diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o new file mode 100644 index 0000000..488bb83 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.cyclo new file mode 100644 index 0000000..756ee82 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.cyclo @@ -0,0 +1,8 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 1 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:46:9:BSP_RADIO_Init 1 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:78:9:BSP_RADIO_DeInit 1 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:105:9:BSP_RADIO_ConfigRFSwitch 5 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:155:9:BSP_RADIO_GetTxConfig 1 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:167:9:BSP_RADIO_IsTCXO 1 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:179:9:BSP_RADIO_IsDCDC 1 +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:190:9:BSP_RADIO_GetRFOMaxPowerConfig 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.d new file mode 100644 index 0000000..16512cf --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.d @@ -0,0 +1,88 @@ +Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o: \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o new file mode 100644 index 0000000..1d151c6 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.su new file mode 100644 index 0000000..d5ce3cf --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.su @@ -0,0 +1,8 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:449:22:LL_AHB2_GRP1_EnableClock 24 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:46:9:BSP_RADIO_Init 32 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:78:9:BSP_RADIO_DeInit 8 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:105:9:BSP_RADIO_ConfigRFSwitch 16 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:155:9:BSP_RADIO_GetTxConfig 4 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:167:9:BSP_RADIO_IsTCXO 4 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:179:9:BSP_RADIO_IsDCDC 4 static +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c:190:9:BSP_RADIO_GetRFOMaxPowerConfig 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/subdir.mk new file mode 100644 index 0000000..079428a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/BSP/LoRa-GPS-Tracker/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.c \ +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.c + +OBJS += \ +./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o \ +./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o + +C_DEPS += \ +./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.d \ +./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/BSP/LoRa-GPS-Tracker/%.o Drivers/BSP/LoRa-GPS-Tracker/%.su Drivers/BSP/LoRa-GPS-Tracker/%.cyclo: ../Drivers/BSP/LoRa-GPS-Tracker/%.c Drivers/BSP/LoRa-GPS-Tracker/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-BSP-2f-LoRa-2d-GPS-2d-Tracker + +clean-Drivers-2f-BSP-2f-LoRa-2d-GPS-2d-Tracker: + -$(RM) ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.cyclo ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.d ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.su ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.cyclo ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.d ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o ./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.su + +.PHONY: clean-Drivers-2f-BSP-2f-LoRa-2d-GPS-2d-Tracker + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/Core/Template/ARMv8-M/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/Core/Template/ARMv8-M/subdir.mk new file mode 100644 index 0000000..aae4ebf --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/Core/Template/ARMv8-M/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/Core/Template/ARMv8-M/main_s.c \ +../Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.c + +OBJS += \ +./Drivers/CMSIS/Core/Template/ARMv8-M/main_s.o \ +./Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.o + +C_DEPS += \ +./Drivers/CMSIS/Core/Template/ARMv8-M/main_s.d \ +./Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/Core/Template/ARMv8-M/%.o Drivers/CMSIS/Core/Template/ARMv8-M/%.su Drivers/CMSIS/Core/Template/ARMv8-M/%.cyclo: ../Drivers/CMSIS/Core/Template/ARMv8-M/%.c Drivers/CMSIS/Core/Template/ARMv8-M/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-Core-2f-Template-2f-ARMv8-2d-M + +clean-Drivers-2f-CMSIS-2f-Core-2f-Template-2f-ARMv8-2d-M: + -$(RM) ./Drivers/CMSIS/Core/Template/ARMv8-M/main_s.cyclo ./Drivers/CMSIS/Core/Template/ARMv8-M/main_s.d ./Drivers/CMSIS/Core/Template/ARMv8-M/main_s.o ./Drivers/CMSIS/Core/Template/ARMv8-M/main_s.su ./Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.cyclo ./Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.d ./Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.o ./Drivers/CMSIS/Core/Template/ARMv8-M/tz_context.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-Core-2f-Template-2f-ARMv8-2d-M + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/subdir.mk new file mode 100644 index 0000000..f1044f2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-JTest-2f-src + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-JTest-2f-src: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_cycle.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_dump_str_segments.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_fw.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/JTest/src/jtest_trigger_action.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-JTest-2f-src + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/subdir.mk new file mode 100644 index 0000000..c004247 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.s \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/%.o: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/%.s Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-ARMCC + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-ARMCC: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/Retarget.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv6-m.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCC/startup_armv7-m.o + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-ARMCC + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/subdir.mk new file mode 100644 index 0000000..32757ad --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_UPPER_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.S \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.S + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.o + +S_UPPER_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/%.o: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/%.S Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-ARMCLANG + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-ARMCLANG: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv6-m.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/ARMCLANG/startup_armv7-m.o + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-ARMCLANG + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/subdir.mk new file mode 100644 index 0000000..2ecc6af --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.c + +S_UPPER_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.S \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.S + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.o + +S_UPPER_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/%.o: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/%.S Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-GCC + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-GCC: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/Retarget.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv6-m.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/GCC/startup_armv7-m.o + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform-2f-GCC + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/subdir.mk new file mode 100644 index 0000000..1a73a56 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/subdir.mk @@ -0,0 +1,66 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.c + +S_UPPER_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.S + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.o + +S_UPPER_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/%.o: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/%.S Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/startup_generic.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM0.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM23.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM3.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM33.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM4.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMCM7.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC000.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMSC300.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MBL.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_ARMv8MML.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/platform/system_generic.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-platform + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/subdir.mk new file mode 100644 index 0000000..df61393 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/subdir.mk @@ -0,0 +1,57 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-basic_math_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-basic_math_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/abs_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/add_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/basic_math_test_group.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/dot_prod_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/mult_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/negate_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/offset_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/scale_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/shift_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/basic_math_tests/sub_tests.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-basic_math_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/subdir.mk new file mode 100644 index 0000000..46b48f1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-complex_math_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-complex_math_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_conj_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_dot_prod_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_squared_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mag_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_cmplx_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/cmplx_mult_real_test.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/complex_math_tests/complex_math_test_group.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-complex_math_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/subdir.mk new file mode 100644 index 0000000..7f1695c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-controller_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-controller_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/controller_test_group.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_reset_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/pid_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/controller_tests/sin_cos_tests.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-controller_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/subdir.mk new file mode 100644 index 0000000..29207e1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-fast_math_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-fast_math_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/fast_math_tests/fast_math_tests_common_data.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-fast_math_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/subdir.mk new file mode 100644 index 0000000..38700c7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-filtering_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-filtering_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/biquad_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/conv_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/correlate_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/filtering_test_group.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/fir_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/iir_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/filtering_tests/lms_tests.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-filtering_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/subdir.mk new file mode 100644 index 0000000..e0ab47c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-intrinsics_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-intrinsics_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/intrinsics_tests/intrinsics_tests_common_data.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-intrinsics_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/subdir.mk new file mode 100644 index 0000000..f5a38a2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/subdir.mk @@ -0,0 +1,57 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-matrix_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-matrix_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_add_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_cmplx_mult_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_init_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_inverse_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_fast_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_mult_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_scale_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_sub_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/mat_trans_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/matrix_tests/matrix_test_group.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-matrix_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/subdir.mk new file mode 100644 index 0000000..eff71c5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-statistics_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-statistics_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/max_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/mean_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/min_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/power_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/rms_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/statistics_test_group.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/std_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/statistics_tests/var_tests.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-statistics_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/subdir.mk new file mode 100644 index 0000000..f18fed0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/all_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/main.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/subdir.mk new file mode 100644 index 0000000..49580a0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-support_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-support_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/copy_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/fill_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_common_data.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/support_test_group.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/support_tests/x_to_y_tests.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-support_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/subdir.mk new file mode 100644 index 0000000..6169faa --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/subdir.mk @@ -0,0 +1,45 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-transform_tests + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-transform_tests: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_family_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/cfft_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/dct4_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_fast_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/rfft_tests.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_test_group.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/Common/src/transform_tests/transform_tests_common_data.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-Common-2f-src-2f-transform_tests + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/subdir.mk new file mode 100644 index 0000000..cf7908a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5-2f-RTE-2f-CMSIS + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5-2f-RTE-2f-CMSIS: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/RTX_Config.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/CMSIS/handlers.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5-2f-RTE-2f-CMSIS + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/subdir.mk new file mode 100644 index 0000000..d6ddf68 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5-2f-RTE-2f-Device-2f-ARMCA5 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5-2f-RTE-2f-Device-2f-ARMCA5: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/mmu_ARMCA5.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/startup_ARMCA5.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/RTE/Device/ARMCA5/system_ARMCA5.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5-2f-RTE-2f-Device-2f-ARMCA5 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/subdir.mk new file mode 100644 index 0000000..aa921d0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/DspLibTest_FVP_A5/main.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-DspLibTest_FVP_A5 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/subdir.mk new file mode 100644 index 0000000..b36467a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/subdir.mk @@ -0,0 +1,54 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-BasicMathFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-BasicMathFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/BasicMathFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/abs.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/add.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/dot_prod.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/mult.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/negate.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/offset.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/scale.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/shift.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/BasicMathFunctions/sub.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-BasicMathFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/subdir.mk new file mode 100644 index 0000000..c5a72e8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/subdir.mk @@ -0,0 +1,45 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-ComplexMathFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-ComplexMathFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/ComplexMathFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_conj.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_dot_prod.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mag_squared.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_cmplx.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ComplexMathFunctions/cmplx_mult_real.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-ComplexMathFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/subdir.mk new file mode 100644 index 0000000..90df4a8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-ControllerFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-ControllerFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/ControllerFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/pid.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/ControllerFunctions/sin_cos.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-ControllerFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/subdir.mk new file mode 100644 index 0000000..519f793 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-FastMathFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-FastMathFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/FastMathFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/cos.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sin.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FastMathFunctions/sqrt.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-FastMathFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/subdir.mk new file mode 100644 index 0000000..c3c4138 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/subdir.mk @@ -0,0 +1,57 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-FilteringFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-FilteringFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/FilteringFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/biquad.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/conv.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/correlate.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_decimate.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_interpolate.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_lattice.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/fir_sparse.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/iir_lattice.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/FilteringFunctions/lms.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-FilteringFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/subdir.mk new file mode 100644 index 0000000..fdcbc8e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-HelperFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-HelperFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/HelperFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/mat_helper.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/HelperFunctions/ref_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-HelperFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/subdir.mk new file mode 100644 index 0000000..12472c8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-Intrinsics + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-Intrinsics: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/Intrinsics_.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/Intrinsics/intrinsics.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-Intrinsics + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/subdir.mk new file mode 100644 index 0000000..31bb101 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-MatrixFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-MatrixFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/MatrixFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_add.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_cmplx_mult.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_inverse.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_mult.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_scale.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_sub.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/MatrixFunctions/mat_trans.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-MatrixFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/subdir.mk new file mode 100644 index 0000000..51d05ef --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/subdir.mk @@ -0,0 +1,48 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-StatisticsFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-StatisticsFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/StatisticsFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/max.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/mean.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/min.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/power.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/rms.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/std.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/StatisticsFunctions/var.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-StatisticsFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/subdir.mk new file mode 100644 index 0000000..bd0f8f5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/subdir.mk @@ -0,0 +1,42 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-SupportFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-SupportFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/SupportFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/copy.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fill.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_fixed.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/fixed_to_float.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/SupportFunctions/float_to_fixed.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-SupportFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/subdir.mk new file mode 100644 index 0000000..efa8b80 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.c \ +../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.c + +OBJS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.o \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.d \ +./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/%.o Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/%.su Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/%.cyclo: ../Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/%.c Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-TransformFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-TransformFunctions: + -$(RM) ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/TransformFunctions.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/bitreversal.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/cfft.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/dct4.su ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.cyclo ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.d ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.o ./Drivers/CMSIS/DSP/DSP_Lib_TestSuite/RefLibs/src/TransformFunctions/rfft.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-DSP_Lib_TestSuite-2f-RefLibs-2f-src-2f-TransformFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..b55f213 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..a868603 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..d3b599f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..7004f1e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/subdir.mk new file mode 100644 index 0000000..3c14273 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_class_marks_example/arm_class_marks_example_f32.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_class_marks_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..cd18957 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..c5054b4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..55582a7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..ca6c299 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/subdir.mk new file mode 100644 index 0000000..dc1ad75 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/arm_convolution_example_f32.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_convolution_example/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_convolution_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..c516f5c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..2fd7dbc --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..73a0884 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..a447440 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/subdir.mk new file mode 100644 index 0000000..4ef1d12 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_dotproduct_example/arm_dotproduct_example_f32.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_dotproduct_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..40b2123 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..1c66eae --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..e0c73c7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..c80ca09 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/subdir.mk new file mode 100644 index 0000000..7908bde --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_data.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fft_bin_example/arm_fft_bin_example_f32.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fft_bin_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..7b0c29a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..bdb7bee --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..95aac8c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..2b8feda --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/subdir.mk new file mode 100644 index 0000000..a0f8405 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_data.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/arm_fir_example_f32.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_fir_example/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_fir_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..e1b20f5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..a16ec2c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..d8fc5b9 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..c475cee --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/subdir.mk new file mode 100644 index 0000000..a81aff7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_data.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/arm_graphic_equalizer_example_q31.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_graphic_equalizer_example/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_graphic_equalizer_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..85b63a5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..9d5bd53 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..01338c1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..8ac878a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/subdir.mk new file mode 100644 index 0000000..f960dca --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_data.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/arm_linear_interp_example_f32.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_linear_interp_example/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_linear_interp_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..c762441 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..215a7c5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..3359d59 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..5f3c398 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/subdir.mk new file mode 100644 index 0000000..fb16d41 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/arm_matrix_example_f32.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_matrix_example/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_matrix_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..caea604 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..2757287 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..4c92c21 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..f703fc9 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/subdir.mk new file mode 100644 index 0000000..373b5f5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.c \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.d \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_data.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/arm_signal_converge_example_f32.su ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_signal_converge_example/math_helper.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_signal_converge_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..bd162d3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..e4c5f38 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..04c3d0f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..4c106fa --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/subdir.mk new file mode 100644 index 0000000..dd1939d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_sin_cos_example/arm_sin_cos_example_f32.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_sin_cos_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..d0c154d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..951f22a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..ae19f45 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..add7d19 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/subdir.mk new file mode 100644 index 0000000..5b4ab0d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.c + +OBJS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/%.o Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/%.su Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/%.cyclo: ../Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/%.c Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example: + -$(RM) ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.cyclo ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.d ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.o ./Drivers/CMSIS/DSP/Examples/ARM/arm_variance_example/arm_variance_example_f32.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Examples-2f-ARM-2f-arm_variance_example + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/subdir.mk new file mode 100644 index 0000000..3035f52 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.c \ +../Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.c + +OBJS += \ +./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.o \ +./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.d \ +./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/%.o Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/%.su Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/%.cyclo: ../Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/%.c Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-PythonWrapper-2f-cmsisdsp_pkg-2f-src + +clean-Drivers-2f-CMSIS-2f-DSP-2f-PythonWrapper-2f-cmsisdsp_pkg-2f-src: + -$(RM) ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.cyclo ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.d ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.o ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/cmsismodule.su ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.cyclo ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.d ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.o ./Drivers/CMSIS/DSP/PythonWrapper/cmsisdsp_pkg/src/fftinit.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-PythonWrapper-2f-cmsisdsp_pkg-2f-src + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/BasicMathFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/BasicMathFunctions/subdir.mk new file mode 100644 index 0000000..2f49f87 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/BasicMathFunctions/subdir.mk @@ -0,0 +1,133 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.c \ +../Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.o \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.d \ +./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/BasicMathFunctions/%.o Drivers/CMSIS/DSP/Source/BasicMathFunctions/%.su Drivers/CMSIS/DSP/Source/BasicMathFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/BasicMathFunctions/%.c Drivers/CMSIS/DSP/Source/BasicMathFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-BasicMathFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-BasicMathFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/BasicMathFunctions.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_abs_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_add_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_dot_prod_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_mult_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_negate_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.d + -$(RM) ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_offset_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_scale_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_shift_q7.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_f32.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q15.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q31.su ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.cyclo ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.d ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.o ./Drivers/CMSIS/DSP/Source/BasicMathFunctions/arm_sub_q7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-BasicMathFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/CommonTables/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/CommonTables/subdir.mk new file mode 100644 index 0000000..f094026 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/CommonTables/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.c \ +../Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.c \ +../Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.o \ +./Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.o \ +./Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.d \ +./Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.d \ +./Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/CommonTables/%.o Drivers/CMSIS/DSP/Source/CommonTables/%.su Drivers/CMSIS/DSP/Source/CommonTables/%.cyclo: ../Drivers/CMSIS/DSP/Source/CommonTables/%.c Drivers/CMSIS/DSP/Source/CommonTables/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-CommonTables + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-CommonTables: + -$(RM) ./Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.cyclo ./Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.d ./Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.o ./Drivers/CMSIS/DSP/Source/CommonTables/CommonTables.su ./Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.cyclo ./Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.d ./Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.o ./Drivers/CMSIS/DSP/Source/CommonTables/arm_common_tables.su ./Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.cyclo ./Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.d ./Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.o ./Drivers/CMSIS/DSP/Source/CommonTables/arm_const_structs.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-CommonTables + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/subdir.mk new file mode 100644 index 0000000..4b8fdce --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/ComplexMathFunctions/subdir.mk @@ -0,0 +1,81 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c \ +../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.o \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.d \ +./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/ComplexMathFunctions/%.o Drivers/CMSIS/DSP/Source/ComplexMathFunctions/%.su Drivers/CMSIS/DSP/Source/ComplexMathFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/ComplexMathFunctions/%.c Drivers/CMSIS/DSP/Source/ComplexMathFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-ComplexMathFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-ComplexMathFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/ComplexMathFunctions.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_f32.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q15.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_conj_q31.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_f32.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q15.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_q31.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.su ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.cyclo ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.d ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.o ./Drivers/CMSIS/DSP/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-ComplexMathFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/ControllerFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/ControllerFunctions/subdir.mk new file mode 100644 index 0000000..af06335 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/ControllerFunctions/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.c \ +../Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.o \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.d \ +./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/ControllerFunctions/%.o Drivers/CMSIS/DSP/Source/ControllerFunctions/%.su Drivers/CMSIS/DSP/Source/ControllerFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/ControllerFunctions/%.c Drivers/CMSIS/DSP/Source/ControllerFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-ControllerFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-ControllerFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/ControllerFunctions.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_f32.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q15.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_init_q31.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_f32.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q15.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_pid_reset_q31.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_f32.su ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.cyclo ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.d ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.o ./Drivers/CMSIS/DSP/Source/ControllerFunctions/arm_sin_cos_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-ControllerFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/FastMathFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/FastMathFunctions/subdir.mk new file mode 100644 index 0000000..9a9f6f9 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/FastMathFunctions/subdir.mk @@ -0,0 +1,51 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.c \ +../Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.o \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.d \ +./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/FastMathFunctions/%.o Drivers/CMSIS/DSP/Source/FastMathFunctions/%.su Drivers/CMSIS/DSP/Source/FastMathFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/FastMathFunctions/%.c Drivers/CMSIS/DSP/Source/FastMathFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-FastMathFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-FastMathFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/FastMathFunctions.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_f32.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q15.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_cos_q31.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_f32.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q15.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sin_q31.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q15.su ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.cyclo ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.d ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.o ./Drivers/CMSIS/DSP/Source/FastMathFunctions/arm_sqrt_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-FastMathFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/FilteringFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/FilteringFunctions/subdir.mk new file mode 100644 index 0000000..1996da2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/FilteringFunctions/subdir.mk @@ -0,0 +1,328 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.c \ +../Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.o \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_opt_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_opt_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_opt_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_partial_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_conv_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_opt_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_opt_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_correlate_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_decimate_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_init_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.d \ +./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/FilteringFunctions/%.o Drivers/CMSIS/DSP/Source/FilteringFunctions/%.su Drivers/CMSIS/DSP/Source/FilteringFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/FilteringFunctions/%.c Drivers/CMSIS/DSP/Source/FilteringFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-FilteringFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-FilteringFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/FilteringFunctions.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.d 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./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_interpolate_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_lattice_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_q7.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_init_q7.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_fir_sparse_q7.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.d + -$(RM) ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_iir_lattice_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_f32.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_init_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_norm_q31.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q15.su ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.cyclo ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.d ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.o ./Drivers/CMSIS/DSP/Source/FilteringFunctions/arm_lms_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-FilteringFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/MatrixFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/MatrixFunctions/subdir.mk new file mode 100644 index 0000000..db8ff3a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/MatrixFunctions/subdir.mk @@ -0,0 +1,103 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.c \ +../Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.o \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.d \ +./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/MatrixFunctions/%.o Drivers/CMSIS/DSP/Source/MatrixFunctions/%.su Drivers/CMSIS/DSP/Source/MatrixFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/MatrixFunctions/%.c Drivers/CMSIS/DSP/Source/MatrixFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-MatrixFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-MatrixFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/MatrixFunctions.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_add_q31.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_init_q31.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_inverse_f64.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_fast_q31.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_mult_q31.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_scale_q31.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_sub_q31.su + -$(RM) ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_f32.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q15.su ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.cyclo ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.d ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.o ./Drivers/CMSIS/DSP/Source/MatrixFunctions/arm_mat_trans_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-MatrixFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/StatisticsFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/StatisticsFunctions/subdir.mk new file mode 100644 index 0000000..c1628d3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/StatisticsFunctions/subdir.mk @@ -0,0 +1,103 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.c \ +../Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.o \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.d \ +./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/StatisticsFunctions/%.o Drivers/CMSIS/DSP/Source/StatisticsFunctions/%.su Drivers/CMSIS/DSP/Source/StatisticsFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/StatisticsFunctions/%.c Drivers/CMSIS/DSP/Source/StatisticsFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-StatisticsFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-StatisticsFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/StatisticsFunctions.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q31.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_max_q7.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q31.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_mean_q7.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q31.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_min_q7.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q31.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_power_q7.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_rms_q31.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_std_q31.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.o + -$(RM) ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_f32.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q15.su ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.cyclo ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.d ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.o ./Drivers/CMSIS/DSP/Source/StatisticsFunctions/arm_var_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-StatisticsFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/SupportFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/SupportFunctions/subdir.mk new file mode 100644 index 0000000..1a5d0b9 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/SupportFunctions/subdir.mk @@ -0,0 +1,87 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.c \ +../Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.c + +OBJS += \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.o \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.o + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.d \ +./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/SupportFunctions/%.o Drivers/CMSIS/DSP/Source/SupportFunctions/%.su Drivers/CMSIS/DSP/Source/SupportFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/SupportFunctions/%.c Drivers/CMSIS/DSP/Source/SupportFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-SupportFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-SupportFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/SupportFunctions.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_f32.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q15.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q31.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_copy_q7.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_f32.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q15.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q31.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_fill_q7.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q15.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q31.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_float_to_q7.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_float.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q31.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q15_to_q7.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_float.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q15.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q31_to_q7.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_float.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q15.su ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.cyclo ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.d ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.o ./Drivers/CMSIS/DSP/Source/SupportFunctions/arm_q7_to_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-SupportFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/TransformFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/TransformFunctions/subdir.mk new file mode 100644 index 0000000..3bcd15f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/DSP/Source/TransformFunctions/subdir.mk @@ -0,0 +1,132 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.c \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.c + +S_UPPER_SRCS += \ +../Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.S + +OBJS += \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.o \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.o + +S_UPPER_DEPS += \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.d + +C_DEPS += \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.d \ +./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/DSP/Source/TransformFunctions/%.o Drivers/CMSIS/DSP/Source/TransformFunctions/%.su Drivers/CMSIS/DSP/Source/TransformFunctions/%.cyclo: ../Drivers/CMSIS/DSP/Source/TransformFunctions/%.c Drivers/CMSIS/DSP/Source/TransformFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/CMSIS/DSP/Source/TransformFunctions/%.o: ../Drivers/CMSIS/DSP/Source/TransformFunctions/%.S Drivers/CMSIS/DSP/Source/TransformFunctions/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-TransformFunctions + +clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-TransformFunctions: + -$(RM) ./Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/TransformFunctions.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_bitreversal2.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_init_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix2_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_init_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix4_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_cfft_radix8_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.o + -$(RM) ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_init_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_dct4_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_fast_init_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_f32.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_init_q31.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q15.su ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.cyclo ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.d ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.o ./Drivers/CMSIS/DSP/Source/TransformFunctions/arm_rfft_q31.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-DSP-2f-Source-2f-TransformFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..a32d19b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..a168768 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..fb2937f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..4a9814e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,38 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.c \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.d \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/startup_ARMCM7.su ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/cifar10/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-cifar10-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..ae8e017 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..d030f1c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..5b67280 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..f3f9cc3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,38 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.c \ +../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.d \ +./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/startup_ARMCM7.su ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/NN/Examples/ARM/arm_nn_examples/gru/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Examples-2f-ARM-2f-arm_nn_examples-2f-gru-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/subdir.mk new file mode 100644 index 0000000..dafdc8e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.s + +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.o + +S_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.d + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/%.o: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/%.s Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM0 + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM0: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/startup_ARMCM0.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM0/system_ARMCM0.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM0 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/subdir.mk new file mode 100644 index 0000000..3d1b2e7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.s + +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.o + +S_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.d + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/%.o: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/%.s Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM3 + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM3: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/startup_ARMCM3.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM3/system_ARMCM3.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM3 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/subdir.mk new file mode 100644 index 0000000..d16064d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/%.o: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/%.s Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM4 + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM4: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/startup_ARMCM4.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM4 + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/subdir.mk new file mode 100644 index 0000000..66db781 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.s + +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.o + +S_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.d + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/%.o: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/%.s Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM4_FP + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM4_FP: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/startup_ARMCM4.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM4_FP/system_ARMCM4.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM4_FP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/subdir.mk new file mode 100644 index 0000000..6f45695 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/subdir.mk @@ -0,0 +1,38 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.s + +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.o + +S_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.d + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/%.o: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/%.s Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM7_SP + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM7_SP: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/startup_ARMCM7.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/ARMCM7_SP/system_ARMCM7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-ARMCM7_SP + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/subdir.mk new file mode 100644 index 0000000..2b4b270 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +S_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.s + +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.o + +S_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.d + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/%.o: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/%.s Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/subdir.mk + arm-none-eabi-gcc -mcpu=cortex-m4 -g3 -DDEBUG -c -x assembler-with-cpp -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" "$<" +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-STM32F411RETx + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-STM32F411RETx: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/startup_stm32f411xe.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/RTE/Device/STM32F411RETx/system_stm32f4xx.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-RTE-2f-Device-2f-STM32F411RETx + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/subdir.mk new file mode 100644 index 0000000..6e85c0d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/subdir.mk @@ -0,0 +1,69 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.c \ +../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.c + +OBJS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.o \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.o + +C_DEPS += \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.d \ +./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/%.o Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/%.su Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/%.cyclo: ../Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/%.c Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-Ref_Implementations + +clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-Ref_Implementations: + -$(RM) ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q15_ref_nonsquare.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_convolve_HWC_q7_ref_nonsquare.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_depthwise_separable_conv_HWC_q7_ref_nonsquare.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_opt_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_mat_q7_vec_q15_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_opt_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q15_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_opt_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_fully_connected_q7_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_nn_mult_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_pool_ref.su ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.cyclo ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.d ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.o ./Drivers/CMSIS/NN/NN_Lib_Tests/nn_test/Ref_Implementations/arm_relu_ref.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-NN_Lib_Tests-2f-nn_test-2f-Ref_Implementations + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/ActivationFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/ActivationFunctions/subdir.mk new file mode 100644 index 0000000..a7dbb9f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/ActivationFunctions/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.c \ +../Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.c \ +../Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.c \ +../Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.c + +OBJS += \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.o \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.o \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.o \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.o + +C_DEPS += \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.d \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.d \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.d \ +./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Source/ActivationFunctions/%.o Drivers/CMSIS/NN/Source/ActivationFunctions/%.su Drivers/CMSIS/NN/Source/ActivationFunctions/%.cyclo: ../Drivers/CMSIS/NN/Source/ActivationFunctions/%.c Drivers/CMSIS/NN/Source/ActivationFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-ActivationFunctions + +clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-ActivationFunctions: + -$(RM) ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.cyclo ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.d ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.o ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q15.su ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.cyclo ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.d ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.o ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_nn_activations_q7.su ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.cyclo ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.d ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.o ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q15.su ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.cyclo ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.d ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.o ./Drivers/CMSIS/NN/Source/ActivationFunctions/arm_relu_q7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-ActivationFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/ConvolutionFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/ConvolutionFunctions/subdir.mk new file mode 100644 index 0000000..090b18f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/ConvolutionFunctions/subdir.mk @@ -0,0 +1,66 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.c \ +../Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.c + +OBJS += \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.o \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.o + +C_DEPS += \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.d \ +./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Source/ConvolutionFunctions/%.o Drivers/CMSIS/NN/Source/ConvolutionFunctions/%.su Drivers/CMSIS/NN/Source/ConvolutionFunctions/%.cyclo: ../Drivers/CMSIS/NN/Source/ConvolutionFunctions/%.c Drivers/CMSIS/NN/Source/ConvolutionFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-ConvolutionFunctions + +clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-ConvolutionFunctions: + -$(RM) ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_1x1_HWC_q7_fast_nonsquare.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_basic.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q15_fast_nonsquare.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_RGB.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_basic_nonsquare.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_convolve_HWC_q7_fast_nonsquare.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_conv_u8_basic_ver1.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_depthwise_separable_conv_HWC_q7_nonsquare.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15.su ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.cyclo ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.d ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.o ./Drivers/CMSIS/NN/Source/ConvolutionFunctions/arm_nn_mat_mult_kernel_q7_q15_reordered.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-ConvolutionFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/subdir.mk new file mode 100644 index 0000000..bda6a9b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/FullyConnectedFunctions/subdir.mk @@ -0,0 +1,42 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.c \ +../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.c \ +../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.c \ +../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.c \ +../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.c \ +../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.c + +OBJS += \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.o \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.o \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.o \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.o \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.o \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.o + +C_DEPS += \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.d \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.d \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.d \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.d \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.d \ +./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Source/FullyConnectedFunctions/%.o Drivers/CMSIS/NN/Source/FullyConnectedFunctions/%.su Drivers/CMSIS/NN/Source/FullyConnectedFunctions/%.cyclo: ../Drivers/CMSIS/NN/Source/FullyConnectedFunctions/%.c Drivers/CMSIS/NN/Source/FullyConnectedFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-FullyConnectedFunctions + +clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-FullyConnectedFunctions: + -$(RM) ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.cyclo ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.d ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.o ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15.su ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.cyclo ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.d ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.o ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_mat_q7_vec_q15_opt.su ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.cyclo ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.d ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.o ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15.su ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.cyclo ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.d ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.o ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q15_opt.su ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.cyclo ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.d ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.o ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7.su ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.cyclo ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.d ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.o ./Drivers/CMSIS/NN/Source/FullyConnectedFunctions/arm_fully_connected_q7_opt.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-FullyConnectedFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/subdir.mk new file mode 100644 index 0000000..4d03f84 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/NNSupportFunctions/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.c \ +../Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.c \ +../Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.c \ +../Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.c \ +../Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.c + +OBJS += \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.o \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.o \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.o \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.o \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.o + +C_DEPS += \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.d \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.d \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.d \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.d \ +./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Source/NNSupportFunctions/%.o Drivers/CMSIS/NN/Source/NNSupportFunctions/%.su Drivers/CMSIS/NN/Source/NNSupportFunctions/%.cyclo: ../Drivers/CMSIS/NN/Source/NNSupportFunctions/%.c Drivers/CMSIS/NN/Source/NNSupportFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-NNSupportFunctions + +clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-NNSupportFunctions: + -$(RM) ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.cyclo ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.d ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.o ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q15.su ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.cyclo ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.d ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.o ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nn_mult_q7.su ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.cyclo ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.d ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.o ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_nntables.su ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.cyclo ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.d ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.o ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_no_shift.su ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.cyclo ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.d ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.o ./Drivers/CMSIS/NN/Source/NNSupportFunctions/arm_q7_to_q15_reordered_no_shift.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-NNSupportFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/subdir.mk new file mode 100644 index 0000000..10b0d28 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/PoolingFunctions/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.c + +OBJS += \ +./Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.o + +C_DEPS += \ +./Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Source/PoolingFunctions/%.o Drivers/CMSIS/NN/Source/PoolingFunctions/%.su Drivers/CMSIS/NN/Source/PoolingFunctions/%.cyclo: ../Drivers/CMSIS/NN/Source/PoolingFunctions/%.c Drivers/CMSIS/NN/Source/PoolingFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-PoolingFunctions + +clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-PoolingFunctions: + -$(RM) ./Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.cyclo ./Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.d ./Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.o ./Drivers/CMSIS/NN/Source/PoolingFunctions/arm_pool_q7_HWC.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-PoolingFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/subdir.mk new file mode 100644 index 0000000..f25f8f0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/NN/Source/SoftmaxFunctions/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.c \ +../Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.c + +OBJS += \ +./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.o \ +./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.o + +C_DEPS += \ +./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.d \ +./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/NN/Source/SoftmaxFunctions/%.o Drivers/CMSIS/NN/Source/SoftmaxFunctions/%.su Drivers/CMSIS/NN/Source/SoftmaxFunctions/%.cyclo: ../Drivers/CMSIS/NN/Source/SoftmaxFunctions/%.c Drivers/CMSIS/NN/Source/SoftmaxFunctions/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-SoftmaxFunctions + +clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-SoftmaxFunctions: + -$(RM) ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.cyclo ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.d ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.o ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q15.su ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.cyclo ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.d ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.o ./Drivers/CMSIS/NN/Source/SoftmaxFunctions/arm_softmax_q7.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-NN-2f-Source-2f-SoftmaxFunctions + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_systick.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_systick.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_systick.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_systick.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_gtim.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/os_tick_ptim.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/subdir.mk new file mode 100644 index 0000000..3131a55 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Source/subdir.mk @@ -0,0 +1,33 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/RTOS2/Source/os_systick.c \ +../Drivers/CMSIS/RTOS2/Source/os_tick_gtim.c \ +../Drivers/CMSIS/RTOS2/Source/os_tick_ptim.c + +OBJS += \ +./Drivers/CMSIS/RTOS2/Source/os_systick.o \ +./Drivers/CMSIS/RTOS2/Source/os_tick_gtim.o \ +./Drivers/CMSIS/RTOS2/Source/os_tick_ptim.o + +C_DEPS += \ +./Drivers/CMSIS/RTOS2/Source/os_systick.d \ +./Drivers/CMSIS/RTOS2/Source/os_tick_gtim.d \ +./Drivers/CMSIS/RTOS2/Source/os_tick_ptim.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/RTOS2/Source/%.o Drivers/CMSIS/RTOS2/Source/%.su Drivers/CMSIS/RTOS2/Source/%.cyclo: ../Drivers/CMSIS/RTOS2/Source/%.c Drivers/CMSIS/RTOS2/Source/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-RTOS2-2f-Source + +clean-Drivers-2f-CMSIS-2f-RTOS2-2f-Source: + -$(RM) ./Drivers/CMSIS/RTOS2/Source/os_systick.cyclo ./Drivers/CMSIS/RTOS2/Source/os_systick.d ./Drivers/CMSIS/RTOS2/Source/os_systick.o ./Drivers/CMSIS/RTOS2/Source/os_systick.su ./Drivers/CMSIS/RTOS2/Source/os_tick_gtim.cyclo ./Drivers/CMSIS/RTOS2/Source/os_tick_gtim.d ./Drivers/CMSIS/RTOS2/Source/os_tick_gtim.o ./Drivers/CMSIS/RTOS2/Source/os_tick_gtim.su ./Drivers/CMSIS/RTOS2/Source/os_tick_ptim.cyclo ./Drivers/CMSIS/RTOS2/Source/os_tick_ptim.d ./Drivers/CMSIS/RTOS2/Source/os_tick_ptim.o ./Drivers/CMSIS/RTOS2/Source/os_tick_ptim.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-RTOS2-2f-Source + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/cmsis_os1.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/cmsis_os1.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/cmsis_os1.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/cmsis_os1.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/subdir.mk new file mode 100644 index 0000000..4dc2859 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/CMSIS/RTOS2/Template/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/CMSIS/RTOS2/Template/cmsis_os1.c + +OBJS += \ +./Drivers/CMSIS/RTOS2/Template/cmsis_os1.o + +C_DEPS += \ +./Drivers/CMSIS/RTOS2/Template/cmsis_os1.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/CMSIS/RTOS2/Template/%.o Drivers/CMSIS/RTOS2/Template/%.su Drivers/CMSIS/RTOS2/Template/%.cyclo: ../Drivers/CMSIS/RTOS2/Template/%.c Drivers/CMSIS/RTOS2/Template/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-CMSIS-2f-RTOS2-2f-Template + +clean-Drivers-2f-CMSIS-2f-RTOS2-2f-Template: + -$(RM) ./Drivers/CMSIS/RTOS2/Template/cmsis_os1.cyclo ./Drivers/CMSIS/RTOS2/Template/cmsis_os1.d ./Drivers/CMSIS/RTOS2/Template/cmsis_os1.o ./Drivers/CMSIS/RTOS2/Template/cmsis_os1.su + +.PHONY: clean-Drivers-2f-CMSIS-2f-RTOS2-2f-Template + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo new file mode 100644 index 0000000..b97e8a0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo @@ -0,0 +1,63 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:346:22:LL_AHB1_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:365:22:LL_AHB1_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:508:22:LL_AHB2_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:527:22:LL_AHB2_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:763:22:LL_AHB3_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:806:22:LL_AHB3_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1062:22:LL_APB1_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1079:22:LL_APB1_GRP2_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1107:22:LL_APB1_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1124:22:LL_APB1_GRP2_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1374:22:LL_APB2_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1397:22:LL_APB2_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1529:22:LL_APB3_GRP1_ForceReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1541:22:LL_APB3_GRP1_ReleaseReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:460:22:LL_SYSCFG_EnableAnalogBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:479:22:LL_SYSCFG_DisableAnalogBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:604:22:LL_SYSCFG_EnableSRAM2Erase 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:747:22:LL_SYSCFG_UnlockSRAM2WRP 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1161:26:LL_DBGMCU_GetDeviceID 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1172:26:LL_DBGMCU_GetRevisionID 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1182:22:LL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1192:22:LL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1204:22:LL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1214:22:LL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1226:22:LL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1236:22:LL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1450:22:LL_VREFBUF_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1460:22:LL_VREFBUF_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1493:22:LL_VREFBUF_SetVoltageScaling 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1559:22:LL_VREFBUF_SetTrimming 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:152:19:HAL_Init 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:208:19:HAL_DeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:240:13:HAL_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:251:13:HAL_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:274:26:HAL_InitTick 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:347:13:HAL_IncTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:358:17:HAL_GetTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:367:10:HAL_GetTickPrio 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:376:19:HAL_SetTickFreq 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:407:21:HAL_GetTickFreq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:423:13:HAL_Delay 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:450:13:HAL_SuspendTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:466:13:HAL_ResumeTick 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:476:10:HAL_GetHalVersion 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:487:10:HAL_GetREVID 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:496:10:HAL_GetDEVID 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:506:10:HAL_GetUIDw0 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:515:10:HAL_GetUIDw1 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:524:10:HAL_GetUIDw2 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:555:6:HAL_DBGMCU_EnableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:564:6:HAL_DBGMCU_DisableDBGSleepMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:575:6:HAL_DBGMCU_EnableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:584:6:HAL_DBGMCU_DisableDBGStopMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:595:6:HAL_DBGMCU_EnableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:604:6:HAL_DBGMCU_DisableDBGStandbyMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:637:6:HAL_SYSCFG_SRAM2Erase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:657:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:688:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:709:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:722:19:HAL_SYSCFG_EnableVREFBUF 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:748:6:HAL_SYSCFG_DisableVREFBUF 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:758:6:HAL_SYSCFG_EnableIOAnalogSwitchBooster 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:768:6:HAL_SYSCFG_DisableIOAnalogSwitchBooster 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d new file mode 100644 index 0000000..d05ce34 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o new file mode 100644 index 0000000..97d5fa8 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su new file mode 100644 index 0000000..529c632 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su @@ -0,0 +1,63 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:346:22:LL_AHB1_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:365:22:LL_AHB1_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:508:22:LL_AHB2_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:527:22:LL_AHB2_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:763:22:LL_AHB3_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:806:22:LL_AHB3_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1062:22:LL_APB1_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1079:22:LL_APB1_GRP2_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1107:22:LL_APB1_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1124:22:LL_APB1_GRP2_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1374:22:LL_APB2_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1397:22:LL_APB2_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1529:22:LL_APB3_GRP1_ForceReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h:1541:22:LL_APB3_GRP1_ReleaseReset 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:460:22:LL_SYSCFG_EnableAnalogBooster 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:479:22:LL_SYSCFG_DisableAnalogBooster 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:604:22:LL_SYSCFG_EnableSRAM2Erase 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:747:22:LL_SYSCFG_UnlockSRAM2WRP 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1161:26:LL_DBGMCU_GetDeviceID 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1172:26:LL_DBGMCU_GetRevisionID 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1182:22:LL_DBGMCU_EnableDBGSleepMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1192:22:LL_DBGMCU_DisableDBGSleepMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1204:22:LL_DBGMCU_EnableDBGStopMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1214:22:LL_DBGMCU_DisableDBGStopMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1226:22:LL_DBGMCU_EnableDBGStandbyMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1236:22:LL_DBGMCU_DisableDBGStandbyMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1450:22:LL_VREFBUF_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1460:22:LL_VREFBUF_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1493:22:LL_VREFBUF_SetVoltageScaling 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h:1559:22:LL_VREFBUF_SetTrimming 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:152:19:HAL_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:208:19:HAL_DeInit 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:240:13:HAL_MspInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:251:13:HAL_MspDeInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:274:26:HAL_InitTick 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:347:13:HAL_IncTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:358:17:HAL_GetTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:367:10:HAL_GetTickPrio 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:376:19:HAL_SetTickFreq 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:407:21:HAL_GetTickFreq 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:423:13:HAL_Delay 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:450:13:HAL_SuspendTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:466:13:HAL_ResumeTick 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:476:10:HAL_GetHalVersion 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:487:10:HAL_GetREVID 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:496:10:HAL_GetDEVID 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:506:10:HAL_GetUIDw0 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:515:10:HAL_GetUIDw1 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:524:10:HAL_GetUIDw2 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:555:6:HAL_DBGMCU_EnableDBGSleepMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:564:6:HAL_DBGMCU_DisableDBGSleepMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:575:6:HAL_DBGMCU_EnableDBGStopMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:584:6:HAL_DBGMCU_DisableDBGStopMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:595:6:HAL_DBGMCU_EnableDBGStandbyMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:604:6:HAL_DBGMCU_DisableDBGStandbyMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:637:6:HAL_SYSCFG_SRAM2Erase 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:657:6:HAL_SYSCFG_VREFBUF_VoltageScalingConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:688:6:HAL_SYSCFG_VREFBUF_HighImpedanceConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:709:6:HAL_SYSCFG_VREFBUF_TrimmingConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:722:19:HAL_SYSCFG_EnableVREFBUF 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:748:6:HAL_SYSCFG_DisableVREFBUF 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:758:6:HAL_SYSCFG_EnableIOAnalogSwitchBooster 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c:768:6:HAL_SYSCFG_DisableIOAnalogSwitchBooster 8 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.cyclo new file mode 100644 index 0000000..f5ab291 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.cyclo @@ -0,0 +1,59 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1796:22:LL_ADC_SetCommonPathInternalCh 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1890:26:LL_ADC_GetCommonPathInternalCh 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2260:22:LL_ADC_SetSamplingTimeCommonChannels 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2293:26:LL_ADC_GetSamplingTimeCommonChannels 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2395:26:LL_ADC_REG_IsTriggerSourceSWStart 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2806:22:LL_ADC_REG_SetSequencerRanks 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3073:22:LL_ADC_REG_SetSequencerChAdd 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3165:22:LL_ADC_REG_SetSequencerChRem 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3376:26:LL_ADC_REG_GetDMATransfer 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3502:22:LL_ADC_SetChannelSamplingTime 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3664:22:LL_ADC_SetAnalogWDMonitChannels 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3883:22:LL_ADC_ConfigAnalogWDThresholds 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4218:22:LL_ADC_EnableInternalRegulator 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4237:22:LL_ADC_DisableInternalRegulator 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4248:26:LL_ADC_IsInternalRegulatorEnabled 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4269:22:LL_ADC_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4289:22:LL_ADC_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4308:26:LL_ADC_IsEnabled 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4319:26:LL_ADC_IsDisableOngoing 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4399:22:LL_ADC_REG_StartConversion 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4419:22:LL_ADC_REG_StopConversion 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4435:26:LL_ADC_REG_IsConversionOngoing 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4737:22:LL_ADC_ClearFlag_AWD1 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4748:22:LL_ADC_ClearFlag_AWD2 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4759:22:LL_ADC_ClearFlag_AWD3 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4855:22:LL_ADC_EnableIT_AWD1 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4866:22:LL_ADC_EnableIT_AWD2 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4877:22:LL_ADC_EnableIT_AWD3 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4965:22:LL_ADC_DisableIT_AWD1 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4976:22:LL_ADC_DisableIT_AWD2 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4987:22:LL_ADC_DisableIT_AWD3 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:379:19:HAL_ADC_Init 21 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:728:19:HAL_ADC_DeInit 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:854:13:HAL_ADC_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:871:13:HAL_ADC_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1138:19:HAL_ADC_Start 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1205:19:HAL_ADC_Stop 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1256:19:HAL_ADC_PollForConversion 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1389:19:HAL_ADC_PollForEvent 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1519:19:HAL_ADC_Start_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1610:19:HAL_ADC_Stop_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1657:19:HAL_ADC_Start_DMA 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1753:19:HAL_ADC_Stop_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1834:10:HAL_ADC_GetValue 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1851:6:HAL_ADC_IRQHandler 26 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2061:13:HAL_ADC_ConvCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2076:13:HAL_ADC_ConvHalfCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2091:13:HAL_ADC_LevelOutOfWindowCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2113:13:HAL_ADC_ErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2159:19:HAL_ADC_ConfigChannel 23 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2367:19:HAL_ADC_AnalogWDGConfig 21 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2603:10:HAL_ADC_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2617:10:HAL_ADC_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2644:19:ADC_ConversionStop 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2698:19:ADC_Enable 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2791:19:ADC_Disable 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2853:13:ADC_DMAConvCplt 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2931:13:ADC_DMAHalfConvCplt 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2949:13:ADC_DMAError 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.d new file mode 100644 index 0000000..d63ad2a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o new file mode 100644 index 0000000..8253b40 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.su new file mode 100644 index 0000000..3af2149 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.su @@ -0,0 +1,59 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1796:22:LL_ADC_SetCommonPathInternalCh 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1890:26:LL_ADC_GetCommonPathInternalCh 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2260:22:LL_ADC_SetSamplingTimeCommonChannels 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2293:26:LL_ADC_GetSamplingTimeCommonChannels 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2395:26:LL_ADC_REG_IsTriggerSourceSWStart 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:2806:22:LL_ADC_REG_SetSequencerRanks 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3073:22:LL_ADC_REG_SetSequencerChAdd 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3165:22:LL_ADC_REG_SetSequencerChRem 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3376:26:LL_ADC_REG_GetDMATransfer 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3502:22:LL_ADC_SetChannelSamplingTime 24 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3664:22:LL_ADC_SetAnalogWDMonitChannels 32 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:3883:22:LL_ADC_ConfigAnalogWDThresholds 32 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4218:22:LL_ADC_EnableInternalRegulator 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4237:22:LL_ADC_DisableInternalRegulator 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4248:26:LL_ADC_IsInternalRegulatorEnabled 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4269:22:LL_ADC_Enable 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4289:22:LL_ADC_Disable 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4308:26:LL_ADC_IsEnabled 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4319:26:LL_ADC_IsDisableOngoing 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4399:22:LL_ADC_REG_StartConversion 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4419:22:LL_ADC_REG_StopConversion 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4435:26:LL_ADC_REG_IsConversionOngoing 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4737:22:LL_ADC_ClearFlag_AWD1 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4748:22:LL_ADC_ClearFlag_AWD2 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4759:22:LL_ADC_ClearFlag_AWD3 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4855:22:LL_ADC_EnableIT_AWD1 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4866:22:LL_ADC_EnableIT_AWD2 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4877:22:LL_ADC_EnableIT_AWD3 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4965:22:LL_ADC_DisableIT_AWD1 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4976:22:LL_ADC_DisableIT_AWD2 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4987:22:LL_ADC_DisableIT_AWD3 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:379:19:HAL_ADC_Init 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:728:19:HAL_ADC_DeInit 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:854:13:HAL_ADC_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:871:13:HAL_ADC_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1138:19:HAL_ADC_Start 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1205:19:HAL_ADC_Stop 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1256:19:HAL_ADC_PollForConversion 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1389:19:HAL_ADC_PollForEvent 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1519:19:HAL_ADC_Start_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1610:19:HAL_ADC_Stop_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1657:19:HAL_ADC_Start_DMA 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1753:19:HAL_ADC_Stop_DMA 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1834:10:HAL_ADC_GetValue 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:1851:6:HAL_ADC_IRQHandler 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2061:13:HAL_ADC_ConvCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2076:13:HAL_ADC_ConvHalfCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2091:13:HAL_ADC_LevelOutOfWindowCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2113:13:HAL_ADC_ErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2159:19:HAL_ADC_ConfigChannel 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2367:19:HAL_ADC_AnalogWDGConfig 56 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2603:10:HAL_ADC_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2617:10:HAL_ADC_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2644:19:ADC_ConversionStop 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2698:19:ADC_Enable 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2791:19:ADC_Disable 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2853:13:ADC_DMAConvCplt 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2931:13:ADC_DMAHalfConvCplt 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c:2949:13:ADC_DMAError 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.cyclo new file mode 100644 index 0000000..937a41c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.cyclo @@ -0,0 +1,17 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1970:22:LL_ADC_SetCalibrationFactor 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1986:26:LL_ADC_GetCalibrationFactor 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4237:22:LL_ADC_DisableInternalRegulator 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4269:22:LL_ADC_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4289:22:LL_ADC_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4308:26:LL_ADC_IsEnabled 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4352:22:LL_ADC_StartCalibration 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4368:26:LL_ADC_IsCalibrationOnGoing 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4435:26:LL_ADC_REG_IsConversionOngoing 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:101:19:HAL_ADCEx_Calibration_Start 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:220:10:HAL_ADCEx_Calibration_GetValue 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:236:19:HAL_ADCEx_Calibration_SetValue 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:279:13:HAL_ADCEx_LevelOutOfWindow2Callback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:294:13:HAL_ADCEx_LevelOutOfWindow3Callback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:310:13:HAL_ADCEx_EndOfSamplingCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:325:13:HAL_ADCEx_ChannelConfigReadyCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:348:19:HAL_ADCEx_DisableVoltageRegulator 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.d new file mode 100644 index 0000000..4797c32 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o new file mode 100644 index 0000000..3abfbf6 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.su new file mode 100644 index 0000000..1de9d2f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.su @@ -0,0 +1,17 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1970:22:LL_ADC_SetCalibrationFactor 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:1986:26:LL_ADC_GetCalibrationFactor 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4237:22:LL_ADC_DisableInternalRegulator 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4269:22:LL_ADC_Enable 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4289:22:LL_ADC_Disable 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4308:26:LL_ADC_IsEnabled 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4352:22:LL_ADC_StartCalibration 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4368:26:LL_ADC_IsCalibrationOnGoing 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h:4435:26:LL_ADC_REG_IsConversionOngoing 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:101:19:HAL_ADCEx_Calibration_Start 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:220:10:HAL_ADCEx_Calibration_GetValue 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:236:19:HAL_ADCEx_Calibration_SetValue 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:279:13:HAL_ADCEx_LevelOutOfWindow2Callback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:294:13:HAL_ADCEx_LevelOutOfWindow3Callback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:310:13:HAL_ADCEx_EndOfSamplingCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:325:13:HAL_ADCEx_ChannelConfigReadyCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c:348:19:HAL_ADCEx_DisableVoltageRegulator 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo new file mode 100644 index 0000000..0f7a920 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo @@ -0,0 +1,32 @@ +../Drivers/CMSIS/Include/core_cm4.h:1648:22:__NVIC_SetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1667:26:__NVIC_GetPriorityGrouping 1 +../Drivers/CMSIS/Include/core_cm4.h:1679:22:__NVIC_EnableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1717:22:__NVIC_DisableIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1736:26:__NVIC_GetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1755:22:__NVIC_SetPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1770:22:__NVIC_ClearPendingIRQ 2 +../Drivers/CMSIS/Include/core_cm4.h:1787:26:__NVIC_GetActive 2 +../Drivers/CMSIS/Include/core_cm4.h:1809:22:__NVIC_SetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1831:26:__NVIC_GetPriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1856:26:NVIC_EncodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1883:22:NVIC_DecodePriority 2 +../Drivers/CMSIS/Include/core_cm4.h:1933:34:__NVIC_SystemReset 1 +../Drivers/CMSIS/Include/core_cm4.h:2017:26:SysTick_Config 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:184:6:HAL_NVIC_SetPriorityGrouping 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:207:6:HAL_NVIC_SetPriority 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:231:6:HAL_NVIC_EnableIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:248:6:HAL_NVIC_DisableIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:261:6:HAL_NVIC_SystemReset 0 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:274:10:HAL_SYSTICK_Config 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:318:10:HAL_NVIC_GetPriorityGrouping 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:346:6:HAL_NVIC_GetPriority 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:363:10:HAL_NVIC_GetActive 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:379:6:HAL_NVIC_SetPendingIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:398:10:HAL_NVIC_GetPendingIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:415:6:HAL_NVIC_ClearPendingIRQ 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:432:6:HAL_SYSTICK_CLKSourceConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:450:6:HAL_SYSTICK_IRQHandler 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:459:13:HAL_SYSTICK_Callback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:479:6:HAL_MPU_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:494:6:HAL_MPU_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:510:6:HAL_MPU_ConfigRegion 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d new file mode 100644 index 0000000..e79fd43 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o new file mode 100644 index 0000000..1fd865d Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su new file mode 100644 index 0000000..d05e321 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su @@ -0,0 +1,32 @@ +../Drivers/CMSIS/Include/core_cm4.h:1648:22:__NVIC_SetPriorityGrouping 24 static +../Drivers/CMSIS/Include/core_cm4.h:1667:26:__NVIC_GetPriorityGrouping 4 static +../Drivers/CMSIS/Include/core_cm4.h:1679:22:__NVIC_EnableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1717:22:__NVIC_DisableIRQ 16 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:1736:26:__NVIC_GetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1755:22:__NVIC_SetPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1770:22:__NVIC_ClearPendingIRQ 16 static +../Drivers/CMSIS/Include/core_cm4.h:1787:26:__NVIC_GetActive 16 static +../Drivers/CMSIS/Include/core_cm4.h:1809:22:__NVIC_SetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1831:26:__NVIC_GetPriority 16 static +../Drivers/CMSIS/Include/core_cm4.h:1856:26:NVIC_EncodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1883:22:NVIC_DecodePriority 40 static +../Drivers/CMSIS/Include/core_cm4.h:1933:34:__NVIC_SystemReset 4 static,ignoring_inline_asm +../Drivers/CMSIS/Include/core_cm4.h:2017:26:SysTick_Config 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:184:6:HAL_NVIC_SetPriorityGrouping 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:207:6:HAL_NVIC_SetPriority 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:231:6:HAL_NVIC_EnableIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:248:6:HAL_NVIC_DisableIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:261:6:HAL_NVIC_SystemReset 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:274:10:HAL_SYSTICK_Config 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:318:10:HAL_NVIC_GetPriorityGrouping 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:346:6:HAL_NVIC_GetPriority 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:363:10:HAL_NVIC_GetActive 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:379:6:HAL_NVIC_SetPendingIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:398:10:HAL_NVIC_GetPendingIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:415:6:HAL_NVIC_ClearPendingIRQ 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:432:6:HAL_SYSTICK_CLKSourceConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:450:6:HAL_SYSTICK_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:459:13:HAL_SYSTICK_Callback 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:479:6:HAL_MPU_Enable 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:494:6:HAL_MPU_Disable 4 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c:510:6:HAL_MPU_ConfigRegion 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo new file mode 100644 index 0000000..ea062ad --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo @@ -0,0 +1,15 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:152:19:HAL_DMA_Init 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:255:19:HAL_DMA_DeInit 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:370:19:HAL_DMA_Start 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:421:19:HAL_DMA_Start_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:494:19:HAL_DMA_Abort 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:555:19:HAL_DMA_Abort_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:616:19:HAL_DMA_PollForTransfer 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:744:6:HAL_DMA_IRQHandler 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:838:19:HAL_DMA_RegisterCallback 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:889:19:HAL_DMA_UnRegisterCallback 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:967:22:HAL_DMA_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:979:10:HAL_DMA_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1209:13:DMA_SetConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1252:13:DMA_CalcDMAMUXChannelBaseAndMask 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1290:13:DMA_CalcDMAMUXRequestGenBaseAndMask 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d new file mode 100644 index 0000000..5a0b64f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o new file mode 100644 index 0000000..303063f Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su new file mode 100644 index 0000000..0996331 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su @@ -0,0 +1,15 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:152:19:HAL_DMA_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:255:19:HAL_DMA_DeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:370:19:HAL_DMA_Start 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:421:19:HAL_DMA_Start_IT 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:494:19:HAL_DMA_Abort 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:555:19:HAL_DMA_Abort_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:616:19:HAL_DMA_PollForTransfer 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:744:6:HAL_DMA_IRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:838:19:HAL_DMA_RegisterCallback 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:889:19:HAL_DMA_UnRegisterCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:967:22:HAL_DMA_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:979:10:HAL_DMA_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1209:13:DMA_SetConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1252:13:DMA_CalcDMAMUXChannelBaseAndMask 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c:1290:13:DMA_CalcDMAMUXRequestGenBaseAndMask 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo new file mode 100644 index 0000000..4f55c73 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:96:19:HAL_DMAEx_ConfigMuxSync 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:145:19:HAL_DMAEx_ConfigMuxRequestGenerator 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:203:19:HAL_DMAEx_EnableMuxRequestGenerator 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:231:19:HAL_DMAEx_DisableMuxRequestGenerator 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:259:6:HAL_DMAEx_MUX_IRQHandler 6 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d new file mode 100644 index 0000000..4b9e752 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o new file mode 100644 index 0000000..db0903f Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su new file mode 100644 index 0000000..c609e11 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:96:19:HAL_DMAEx_ConfigMuxSync 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:145:19:HAL_DMAEx_ConfigMuxRequestGenerator 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:203:19:HAL_DMAEx_EnableMuxRequestGenerator 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:231:19:HAL_DMAEx_DisableMuxRequestGenerator 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c:259:6:HAL_DMAEx_MUX_IRQHandler 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo new file mode 100644 index 0000000..b1bab83 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:275:19:HAL_EXTI_GetConfigLine 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:375:19:HAL_EXTI_ClearConfigLine 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:447:19:HAL_EXTI_RegisterCallback 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:473:19:HAL_EXTI_GetHandle 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:514:6:HAL_EXTI_IRQHandler 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:552:10:HAL_EXTI_GetPending 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:588:6:HAL_EXTI_ClearPending 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:615:6:HAL_EXTI_GenerateSWI 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d new file mode 100644 index 0000000..294591f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o new file mode 100644 index 0000000..d034438 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su new file mode 100644 index 0000000..7a316b3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:143:19:HAL_EXTI_SetConfigLine 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:275:19:HAL_EXTI_GetConfigLine 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:375:19:HAL_EXTI_ClearConfigLine 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:447:19:HAL_EXTI_RegisterCallback 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:473:19:HAL_EXTI_GetHandle 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:514:6:HAL_EXTI_IRQHandler 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:552:10:HAL_EXTI_GetPending 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:588:6:HAL_EXTI_ClearPending 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c:615:6:HAL_EXTI_GenerateSWI 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo new file mode 100644 index 0000000..60a115e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo @@ -0,0 +1,14 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:178:19:HAL_FLASH_Program 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:246:19:HAL_FLASH_Program_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:409:13:HAL_FLASH_EndOfOperationCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:427:13:HAL_FLASH_OperationErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:460:19:HAL_FLASH_Unlock 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:484:19:HAL_FLASH_Lock 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:505:19:HAL_FLASH_OB_Unlock 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:530:19:HAL_FLASH_OB_Lock 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:551:19:HAL_FLASH_OB_Launch 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:595:10:HAL_FLASH_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:619:19:FLASH_WaitForLastOperation 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:682:13:FLASH_Program_DoubleWord 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:712:13:FLASH_Program_Fast 3 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d new file mode 100644 index 0000000..e0a51b6 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o new file mode 100644 index 0000000..97d90c8 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su new file mode 100644 index 0000000..561b88a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su @@ -0,0 +1,14 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:178:19:HAL_FLASH_Program 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:246:19:HAL_FLASH_Program_IT 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:304:6:HAL_FLASH_IRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:409:13:HAL_FLASH_EndOfOperationCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:427:13:HAL_FLASH_OperationErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:460:19:HAL_FLASH_Unlock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:484:19:HAL_FLASH_Lock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:505:19:HAL_FLASH_OB_Unlock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:530:19:HAL_FLASH_OB_Lock 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:551:19:HAL_FLASH_OB_Launch 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:595:10:HAL_FLASH_GetError 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:619:19:FLASH_WaitForLastOperation 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:682:13:FLASH_Program_DoubleWord 24 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c:712:13:FLASH_Program_Fast 40 static,ignoring_inline_asm diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo new file mode 100644 index 0000000..39927c2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:174:19:HAL_FLASHEx_Erase 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:246:19:HAL_FLASHEx_Erase_IT 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:310:19:HAL_FLASHEx_OBProgram 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:413:6:HAL_FLASHEx_OBGetConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:460:10:HAL_FLASHEx_FlashEmptyCheck 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:477:6:HAL_FLASHEx_ForceFlashEmpty 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:493:6:HAL_FLASHEx_SuspendOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:511:6:HAL_FLASHEx_AllowOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:531:10:HAL_FLASHEx_IsOperationSuspended 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:631:13:FLASH_MassErase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:647:6:FLASH_PageErase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:664:6:FLASH_FlushCaches 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:696:13:FLASH_AcknowledgePageErase 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:728:13:FLASH_OB_WRPConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:820:13:FLASH_OB_OptrConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:850:13:FLASH_OB_PCROP1AConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:901:13:FLASH_OB_PCROP1BConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1056:13:FLASH_OB_GetWRP 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1082:17:FLASH_OB_GetRDP 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1136:17:FLASH_OB_GetUser 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1157:13:FLASH_OB_GetPCROP 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1289:26:FLASH_OB_ProceedWriteOperation 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d new file mode 100644 index 0000000..ae911fa --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o new file mode 100644 index 0000000..e82da71 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su new file mode 100644 index 0000000..8adc7bf --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:174:19:HAL_FLASHEx_Erase 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:246:19:HAL_FLASHEx_Erase_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:310:19:HAL_FLASHEx_OBProgram 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:413:6:HAL_FLASHEx_OBGetConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:460:10:HAL_FLASHEx_FlashEmptyCheck 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:477:6:HAL_FLASHEx_ForceFlashEmpty 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:493:6:HAL_FLASHEx_SuspendOperation 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:511:6:HAL_FLASHEx_AllowOperation 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:531:10:HAL_FLASHEx_IsOperationSuspended 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:631:13:FLASH_MassErase 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:647:6:FLASH_PageErase 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:664:6:FLASH_FlushCaches 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:696:13:FLASH_AcknowledgePageErase 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:728:13:FLASH_OB_WRPConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:820:13:FLASH_OB_OptrConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:850:13:FLASH_OB_PCROP1AConfig 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:901:13:FLASH_OB_PCROP1BConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1056:13:FLASH_OB_GetWRP 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1082:17:FLASH_OB_GetRDP 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1136:17:FLASH_OB_GetUser 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1157:13:FLASH_OB_GetPCROP 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c:1289:26:FLASH_OB_ProceedWriteOperation 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo new file mode 100644 index 0000000..96d8ee0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:159:6:HAL_GPIO_Init 15 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:299:6:HAL_GPIO_DeInit 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:386:15:HAL_GPIO_ReadPin 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:418:6:HAL_GPIO_WritePin 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:448:6:HAL_GPIO_WriteMultipleStatePin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:468:6:HAL_GPIO_TogglePin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:493:19:HAL_GPIO_LockPin 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:528:6:HAL_GPIO_EXTI_IRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:543:13:HAL_GPIO_EXTI_Callback 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d new file mode 100644 index 0000000..93da9ed --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o new file mode 100644 index 0000000..161f27a Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su new file mode 100644 index 0000000..a93fc07 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su @@ -0,0 +1,9 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:159:6:HAL_GPIO_Init 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:299:6:HAL_GPIO_DeInit 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:386:15:HAL_GPIO_ReadPin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:418:6:HAL_GPIO_WritePin 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:448:6:HAL_GPIO_WriteMultipleStatePin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:468:6:HAL_GPIO_TogglePin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:493:19:HAL_GPIO_LockPin 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:528:6:HAL_GPIO_EXTI_IRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c:543:13:HAL_GPIO_EXTI_Callback 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo new file mode 100644 index 0000000..d9d093b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:407:22:LL_EXTI_DisableIT_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:989:22:LL_EXTI_EnableRisingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1049:22:LL_EXTI_DisableRisingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1164:22:LL_EXTI_EnableFallingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1223:22:LL_EXTI_DisableFallingTrig_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:90:6:HAL_PWR_DeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:149:6:HAL_PWR_EnableBkUpAccess 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:159:6:HAL_PWR_DisableBkUpAccess 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:348:19:HAL_PWR_ConfigPVD 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:389:6:HAL_PWR_EnablePVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:399:6:HAL_PWR_DisablePVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:421:6:HAL_PWR_EnableWakeUpPin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:446:6:HAL_PWR_DisableWakeUpPin 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:479:6:HAL_PWR_EnterSLEEPMode 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:562:6:HAL_PWR_EnterSTOPMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:597:6:HAL_PWR_EnterSTANDBYMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:635:6:HAL_PWR_EnableSleepOnExit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:647:6:HAL_PWR_DisableSleepOnExit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:659:6:HAL_PWR_EnableSEVOnPend 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:671:6:HAL_PWR_DisableSEVOnPend 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:681:13:HAL_PWR_PVDCallback 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d new file mode 100644 index 0000000..bbfcf98 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o new file mode 100644 index 0000000..6ed9954 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su new file mode 100644 index 0000000..3d1ba0c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su @@ -0,0 +1,22 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:407:22:LL_EXTI_DisableIT_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:989:22:LL_EXTI_EnableRisingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1049:22:LL_EXTI_DisableRisingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1164:22:LL_EXTI_EnableFallingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1223:22:LL_EXTI_DisableFallingTrig_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:90:6:HAL_PWR_DeInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:149:6:HAL_PWR_EnableBkUpAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:159:6:HAL_PWR_DisableBkUpAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:348:19:HAL_PWR_ConfigPVD 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:389:6:HAL_PWR_EnablePVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:399:6:HAL_PWR_DisablePVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:421:6:HAL_PWR_EnableWakeUpPin 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:446:6:HAL_PWR_DisableWakeUpPin 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:479:6:HAL_PWR_EnterSLEEPMode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:562:6:HAL_PWR_EnterSTOPMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:597:6:HAL_PWR_EnterSTANDBYMode 4 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:635:6:HAL_PWR_EnableSleepOnExit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:647:6:HAL_PWR_DisableSleepOnExit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:659:6:HAL_PWR_EnableSEVOnPend 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:671:6:HAL_PWR_DisableSEVOnPend 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c:681:13:HAL_PWR_PVDCallback 4 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo new file mode 100644 index 0000000..fa5643d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo @@ -0,0 +1,55 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:705:22:LL_PWR_EnableSRAM2Retention 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:715:22:LL_PWR_DisableSRAM2Retention 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:737:22:LL_PWR_EnableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:747:22:LL_PWR_DisableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1272:22:LL_PWR_SetRadioBusyPolarity 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1327:22:LL_PWR_SetRadioIRQTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:831:22:LL_EXTI_DisableEvent_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1011:22:LL_EXTI_EnableRisingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1072:22:LL_EXTI_DisableRisingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1186:22:LL_EXTI_EnableFallingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1244:22:LL_EXTI_DisableFallingTrig_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1446:26:LL_EXTI_ReadFlag_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1463:26:LL_EXTI_ReadFlag_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1496:22:LL_EXTI_ClearFlag_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1513:22:LL_EXTI_ClearFlag_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:83:10:HAL_PWREx_GetVoltageRange 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:108:19:HAL_PWREx_ControlVoltageScaling 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:158:6:HAL_PWREx_EnableBatteryCharging 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableBatteryCharging 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:184:6:HAL_PWREx_EnableInternalWakeUpLine 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:197:6:HAL_PWREx_DisableInternalWakeUpLine 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:213:6:HAL_PWREx_SetRadioBusyPolarity 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:231:6:HAL_PWREx_SetRadioBusyTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:251:6:HAL_PWREx_SetRadioIRQTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:306:19:HAL_PWREx_EnableGPIOPullUp 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:354:19:HAL_PWREx_DisableGPIOPullUp 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:404:19:HAL_PWREx_EnableGPIOPullDown 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:452:19:HAL_PWREx_DisableGPIOPullDown 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:491:6:HAL_PWREx_EnablePullUpPullDownConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:506:6:HAL_PWREx_DisablePullUpPullDownConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:591:6:HAL_PWREx_EnableSRAMRetention 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:602:6:HAL_PWREx_DisableSRAMRetention 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:618:6:HAL_PWREx_EnableFlashPowerDown 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:653:6:HAL_PWREx_DisableFlashPowerDown 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:673:6:HAL_PWREx_EnableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:686:6:HAL_PWREx_DisableWPVD 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:703:6:HAL_PWREx_EnableBORPVD_ULP 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:715:6:HAL_PWREx_DisableBORPVD_ULP 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:726:6:HAL_PWREx_EnablePVM3 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:735:6:HAL_PWREx_DisablePVM3 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:752:19:HAL_PWREx_ConfigPVM 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:808:6:HAL_PWREx_SetRadioEOL 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:823:6:HAL_PWREx_SMPS_SetMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:839:10:HAL_PWREx_SMPS_GetEffectiveMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:854:6:HAL_PWREx_EnableLowPowerRunMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:868:19:HAL_PWREx_DisableLowPowerRunMode 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:915:6:HAL_PWREx_EnterSTOP0Mode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:974:6:HAL_PWREx_EnterSTOP1Mode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1033:6:HAL_PWREx_EnterSTOP2Mode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1078:6:HAL_PWREx_EnterSHUTDOWNMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1113:6:HAL_PWREx_PVD_PVM_IRQHandler 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1139:13:HAL_PWREx_PVM3Callback 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d new file mode 100644 index 0000000..d51f18a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o new file mode 100644 index 0000000..07cc698 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su new file mode 100644 index 0000000..1d75fde --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su @@ -0,0 +1,55 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:705:22:LL_PWR_EnableSRAM2Retention 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:715:22:LL_PWR_DisableSRAM2Retention 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:737:22:LL_PWR_EnableWPVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:747:22:LL_PWR_DisableWPVD 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1272:22:LL_PWR_SetRadioBusyPolarity 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1327:22:LL_PWR_SetRadioIRQTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:831:22:LL_EXTI_DisableEvent_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1011:22:LL_EXTI_EnableRisingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1072:22:LL_EXTI_DisableRisingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1186:22:LL_EXTI_EnableFallingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1244:22:LL_EXTI_DisableFallingTrig_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1446:26:LL_EXTI_ReadFlag_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1463:26:LL_EXTI_ReadFlag_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1496:22:LL_EXTI_ClearFlag_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:1513:22:LL_EXTI_ClearFlag_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:83:10:HAL_PWREx_GetVoltageRange 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:108:19:HAL_PWREx_ControlVoltageScaling 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:158:6:HAL_PWREx_EnableBatteryCharging 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:173:6:HAL_PWREx_DisableBatteryCharging 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:184:6:HAL_PWREx_EnableInternalWakeUpLine 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:197:6:HAL_PWREx_DisableInternalWakeUpLine 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:213:6:HAL_PWREx_SetRadioBusyPolarity 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:231:6:HAL_PWREx_SetRadioBusyTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:251:6:HAL_PWREx_SetRadioIRQTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:306:19:HAL_PWREx_EnableGPIOPullUp 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:354:19:HAL_PWREx_DisableGPIOPullUp 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:404:19:HAL_PWREx_EnableGPIOPullDown 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:452:19:HAL_PWREx_DisableGPIOPullDown 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:491:6:HAL_PWREx_EnablePullUpPullDownConfig 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:506:6:HAL_PWREx_DisablePullUpPullDownConfig 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:591:6:HAL_PWREx_EnableSRAMRetention 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:602:6:HAL_PWREx_DisableSRAMRetention 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:618:6:HAL_PWREx_EnableFlashPowerDown 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:653:6:HAL_PWREx_DisableFlashPowerDown 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:673:6:HAL_PWREx_EnableWPVD 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:686:6:HAL_PWREx_DisableWPVD 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:703:6:HAL_PWREx_EnableBORPVD_ULP 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:715:6:HAL_PWREx_DisableBORPVD_ULP 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:726:6:HAL_PWREx_EnablePVM3 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:735:6:HAL_PWREx_DisablePVM3 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:752:19:HAL_PWREx_ConfigPVM 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:808:6:HAL_PWREx_SetRadioEOL 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:823:6:HAL_PWREx_SMPS_SetMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:839:10:HAL_PWREx_SMPS_GetEffectiveMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:854:6:HAL_PWREx_EnableLowPowerRunMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:868:19:HAL_PWREx_DisableLowPowerRunMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:915:6:HAL_PWREx_EnterSTOP0Mode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:974:6:HAL_PWREx_EnterSTOP1Mode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1033:6:HAL_PWREx_EnterSTOP2Mode 16 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1078:6:HAL_PWREx_EnterSHUTDOWNMode 4 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1113:6:HAL_PWREx_PVD_PVM_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c:1139:13:HAL_PWREx_PVM3Callback 4 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo new file mode 100644 index 0000000..8d02118 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo @@ -0,0 +1,63 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:421:26:LL_PWR_IsEnabledBkUpAccess 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:968:22:LL_RCC_HSE_EnableTcxo 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:978:22:LL_RCC_HSE_DisableTcxo 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1029:22:LL_RCC_HSE_EnableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1039:22:LL_RCC_HSE_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1049:22:LL_RCC_HSE_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1059:26:LL_RCC_HSE_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1108:22:LL_RCC_HSI_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1118:22:LL_RCC_HSI_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1173:22:LL_RCC_HSI_SetCalibTrimming 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1389:22:LL_RCC_LSI_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1399:22:LL_RCC_LSI_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1427:22:LL_RCC_MSI_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1437:22:LL_RCC_MSI_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1519:22:LL_RCC_MSI_SetRange 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1594:22:LL_RCC_MSI_SetCalibTrimming 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1730:22:LL_RCC_SetSysClkSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1744:26:LL_RCC_GetSysClkSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1770:22:LL_RCC_SetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1822:22:LL_RCC_SetAHB3Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1838:22:LL_RCC_SetAPB1Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1854:22:LL_RCC_SetAPB2Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1928:26:LL_RCC_GetAHB3Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2020:22:LL_RCC_ConfigMCO 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2390:22:LL_RCC_PLL_Enable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2401:22:LL_RCC_PLL_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2678:26:LL_RCC_PLL_GetR 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3035:26:LL_RCC_IsActiveFlag_HPRE 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3057:26:LL_RCC_IsActiveFlag_SHDHPRE 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3068:26:LL_RCC_IsActiveFlag_PPRE1 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3078:26:LL_RCC_IsActiveFlag_PPRE2 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:228:19:HAL_RCC_DeInit 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:335:19:HAL_RCC_OscConfig 84 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:925:19:HAL_RCC_ClockConfig 30 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1188:6:HAL_RCC_MCOConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1251:10:HAL_RCC_GetSysClockFreq 15 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1337:10:HAL_RCC_GetHCLKFreq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1359:10:HAL_RCC_GetHCLK3Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1369:10:HAL_RCC_GetPCLK1Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1379:10:HAL_RCC_GetPCLK2Freq 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1392:6:HAL_RCC_GetOscConfig 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1455:6:HAL_RCC_GetClockConfig 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1510:6:HAL_RCC_EnableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1520:6:HAL_RCC_NMI_IRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1537:13:HAL_RCC_CSSCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1550:10:HAL_RCC_GetResetSource 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1583:26:RCC_SetFlashLatencyFromMSIRange 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1605:26:RCC_SetFlashLatency 8 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d new file mode 100644 index 0000000..d323653 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o new file mode 100644 index 0000000..8eb4e33 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su new file mode 100644 index 0000000..ffb89ab --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su @@ -0,0 +1,63 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:421:26:LL_PWR_IsEnabledBkUpAccess 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:968:22:LL_RCC_HSE_EnableTcxo 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:978:22:LL_RCC_HSE_DisableTcxo 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1029:22:LL_RCC_HSE_EnableCSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1039:22:LL_RCC_HSE_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1049:22:LL_RCC_HSE_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1059:26:LL_RCC_HSE_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1108:22:LL_RCC_HSI_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1118:22:LL_RCC_HSI_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1173:22:LL_RCC_HSI_SetCalibTrimming 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1389:22:LL_RCC_LSI_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1399:22:LL_RCC_LSI_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1427:22:LL_RCC_MSI_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1437:22:LL_RCC_MSI_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1519:22:LL_RCC_MSI_SetRange 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1594:22:LL_RCC_MSI_SetCalibTrimming 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1730:22:LL_RCC_SetSysClkSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1744:26:LL_RCC_GetSysClkSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1770:22:LL_RCC_SetAHBPrescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1822:22:LL_RCC_SetAHB3Prescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1838:22:LL_RCC_SetAPB1Prescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1854:22:LL_RCC_SetAPB2Prescaler 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1928:26:LL_RCC_GetAHB3Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2020:22:LL_RCC_ConfigMCO 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2390:22:LL_RCC_PLL_Enable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2401:22:LL_RCC_PLL_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2678:26:LL_RCC_PLL_GetR 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3035:26:LL_RCC_IsActiveFlag_HPRE 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3057:26:LL_RCC_IsActiveFlag_SHDHPRE 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3068:26:LL_RCC_IsActiveFlag_PPRE1 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3078:26:LL_RCC_IsActiveFlag_PPRE2 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:228:19:HAL_RCC_DeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:335:19:HAL_RCC_OscConfig 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:925:19:HAL_RCC_ClockConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1188:6:HAL_RCC_MCOConfig 56 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1251:10:HAL_RCC_GetSysClockFreq 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1337:10:HAL_RCC_GetHCLKFreq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1359:10:HAL_RCC_GetHCLK3Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1369:10:HAL_RCC_GetPCLK1Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1379:10:HAL_RCC_GetPCLK2Freq 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1392:6:HAL_RCC_GetOscConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1455:6:HAL_RCC_GetClockConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1510:6:HAL_RCC_EnableCSS 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1520:6:HAL_RCC_NMI_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1537:13:HAL_RCC_CSSCallback 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1550:10:HAL_RCC_GetResetSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1583:26:RCC_SetFlashLatencyFromMSIRange 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c:1605:26:RCC_SetFlashLatency 64 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo new file mode 100644 index 0000000..e888961 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo @@ -0,0 +1,58 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1281:22:LL_RCC_LSE_EnableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1293:22:LL_RCC_LSE_DisableCSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1378:26:LL_RCC_LSI_GetPrediv 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1461:22:LL_RCC_MSI_EnablePLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1473:22:LL_RCC_MSI_DisablePLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1632:22:LL_RCC_LSCO_Disable 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2047:22:LL_RCC_SetUSARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2061:22:LL_RCC_SetI2SClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2076:22:LL_RCC_SetLPUARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2096:22:LL_RCC_SetI2CClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2119:22:LL_RCC_SetLPTIMClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2134:22:LL_RCC_SetRNGClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2149:22:LL_RCC_SetADCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2184:26:LL_RCC_GetI2SClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2222:26:LL_RCC_GetI2CClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2249:26:LL_RCC_GetLPTIMClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2265:26:LL_RCC_GetRNGClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2281:26:LL_RCC_GetADCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2307:22:LL_RCC_SetRTCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2321:26:LL_RCC_GetRTCClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2361:22:LL_RCC_ForceBackupDomainReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2371:22:LL_RCC_ReleaseBackupDomainReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2642:26:LL_RCC_PLL_GetP 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2660:26:LL_RCC_PLL_GetQ 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:113:19:HAL_RCCEx_PeriphCLKConfig 25 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:345:6:HAL_RCCEx_GetPeriphCLKConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:416:10:HAL_RCCEx_GetPeriphCLKFreq 103 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:928:6:HAL_RCCEx_WakeUpStopCLKConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:942:6:HAL_RCCEx_EnableLSECSS 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:952:6:HAL_RCCEx_DisableLSECSS 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:968:6:HAL_RCCEx_EnableLSECSS_IT 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:988:6:HAL_RCCEx_LSECSS_IRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1003:13:HAL_RCCEx_LSECSS_Callback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1018:6:HAL_RCCEx_EnableLSCO 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1031:6:HAL_RCCEx_DisableLSCO 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1043:6:HAL_RCCEx_EnableMSIPLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1053:6:HAL_RCCEx_DisableMSIPLLMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1075:17:RCC_PLL_GetFreqDomain_P 12 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1125:17:RCC_PLL_GetFreqDomain_Q 12 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d new file mode 100644 index 0000000..0d3fc3e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o new file mode 100644 index 0000000..410274a Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su new file mode 100644 index 0000000..eb53986 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su @@ -0,0 +1,58 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1019:26:LL_RCC_HSE_IsEnabledDiv2 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1128:26:LL_RCC_HSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1281:22:LL_RCC_LSE_EnableCSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1293:22:LL_RCC_LSE_DisableCSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1334:26:LL_RCC_LSE_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1378:26:LL_RCC_LSI_GetPrediv 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1409:26:LL_RCC_LSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1447:26:LL_RCC_MSI_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1461:22:LL_RCC_MSI_EnablePLLMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1473:22:LL_RCC_MSI_DisablePLLMode 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1496:26:LL_RCC_MSI_IsEnabledRangeSelect 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1541:26:LL_RCC_MSI_GetRange 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1570:26:LL_RCC_MSI_GetRangeAfterStandby 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1632:22:LL_RCC_LSCO_Disable 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1878:26:LL_RCC_GetAHBPrescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1943:26:LL_RCC_GetAPB1Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1958:26:LL_RCC_GetAPB2Prescaler 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1971:22:LL_RCC_SetClkAfterWakeFromStop 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2047:22:LL_RCC_SetUSARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2061:22:LL_RCC_SetI2SClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2076:22:LL_RCC_SetLPUARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2096:22:LL_RCC_SetI2CClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2119:22:LL_RCC_SetLPTIMClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2134:22:LL_RCC_SetRNGClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2149:22:LL_RCC_SetADCClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2184:26:LL_RCC_GetI2SClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2222:26:LL_RCC_GetI2CClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2249:26:LL_RCC_GetLPTIMClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2265:26:LL_RCC_GetRNGClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2281:26:LL_RCC_GetADCClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2307:22:LL_RCC_SetRTCClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2321:26:LL_RCC_GetRTCClockSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2361:22:LL_RCC_ForceBackupDomainReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2371:22:LL_RCC_ReleaseBackupDomainReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2411:26:LL_RCC_PLL_IsReady 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2601:26:LL_RCC_PLL_GetN 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2642:26:LL_RCC_PLL_GetP 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2660:26:LL_RCC_PLL_GetQ 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2696:26:LL_RCC_PLL_GetDivider 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2853:26:LL_RCC_PLL_GetMainSource 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:265:22:LL_EXTI_EnableIT_0_31 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:113:19:HAL_RCCEx_PeriphCLKConfig 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:345:6:HAL_RCCEx_GetPeriphCLKConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:416:10:HAL_RCCEx_GetPeriphCLKFreq 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:928:6:HAL_RCCEx_WakeUpStopCLKConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:942:6:HAL_RCCEx_EnableLSECSS 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:952:6:HAL_RCCEx_DisableLSECSS 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:968:6:HAL_RCCEx_EnableLSECSS_IT 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:988:6:HAL_RCCEx_LSECSS_IRQHandler 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1003:13:HAL_RCCEx_LSECSS_Callback 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1018:6:HAL_RCCEx_EnableLSCO 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1031:6:HAL_RCCEx_DisableLSCO 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1043:6:HAL_RCCEx_EnableMSIPLLMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1053:6:HAL_RCCEx_DisableMSIPLLMode 8 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1075:17:RCC_PLL_GetFreqDomain_P 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c:1125:17:RCC_PLL_GetFreqDomain_Q 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo new file mode 100644 index 0000000..d3793c3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo @@ -0,0 +1,26 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:242:19:HAL_RTC_Init 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:362:19:HAL_RTC_DeInit 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:693:13:HAL_RTC_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:708:13:HAL_RTC_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:749:19:HAL_RTC_SetTime 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:873:19:HAL_RTC_GetTime 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:921:19:HAL_RTC_SetDate 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1005:19:HAL_RTC_GetDate 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1039:6:HAL_RTC_DST_Add1Hour 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1053:6:HAL_RTC_DST_Sub1Hour 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1067:6:HAL_RTC_DST_SetStoreOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1080:6:HAL_RTC_DST_ClearStoreOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1093:10:HAL_RTC_DST_ReadStoreOperation 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1132:19:HAL_RTC_SetAlarm 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1337:19:HAL_RTC_SetAlarm_IT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1537:19:HAL_RTC_DeactivateAlarm 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1604:19:HAL_RTC_GetAlarm 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1666:6:HAL_RTC_AlarmIRQHandler 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1705:13:HAL_RTC_AlarmAEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1721:19:HAL_RTC_PollForAlarmAEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1779:19:HAL_RTC_WaitForSynchro 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1824:21:HAL_RTC_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1847:19:RTC_EnterInitMode 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1879:19:RTC_ExitInitMode 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1916:9:RTC_ByteToBcd2 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1935:9:RTC_Bcd2ToByte 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d new file mode 100644 index 0000000..11544af --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o new file mode 100644 index 0000000..4d2e573 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su new file mode 100644 index 0000000..1260a41 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su @@ -0,0 +1,26 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:242:19:HAL_RTC_Init 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:362:19:HAL_RTC_DeInit 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:693:13:HAL_RTC_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:708:13:HAL_RTC_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:749:19:HAL_RTC_SetTime 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:873:19:HAL_RTC_GetTime 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:921:19:HAL_RTC_SetDate 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1005:19:HAL_RTC_GetDate 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1039:6:HAL_RTC_DST_Add1Hour 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1053:6:HAL_RTC_DST_Sub1Hour 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1067:6:HAL_RTC_DST_SetStoreOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1080:6:HAL_RTC_DST_ClearStoreOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1093:10:HAL_RTC_DST_ReadStoreOperation 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1132:19:HAL_RTC_SetAlarm 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1337:19:HAL_RTC_SetAlarm_IT 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1537:19:HAL_RTC_DeactivateAlarm 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1604:19:HAL_RTC_GetAlarm 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1666:6:HAL_RTC_AlarmIRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1705:13:HAL_RTC_AlarmAEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1721:19:HAL_RTC_PollForAlarmAEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1779:19:HAL_RTC_WaitForSynchro 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1824:21:HAL_RTC_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1847:19:RTC_EnterInitMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1879:19:RTC_ExitInitMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1916:9:RTC_ByteToBcd2 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c:1935:9:RTC_Bcd2ToByte 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo new file mode 100644 index 0000000..7fac8b8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo @@ -0,0 +1,51 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:178:19:HAL_RTCEx_SetTimeStamp 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:229:19:HAL_RTCEx_SetTimeStamp_IT 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:272:19:HAL_RTCEx_DeactivateTimeStamp 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:308:19:HAL_RTCEx_SetInternalTimeStamp 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:338:19:HAL_RTCEx_DeactivateInternalTimeStamp 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:386:19:HAL_RTCEx_GetTimeStamp 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:441:6:HAL_RTCEx_TimeStampIRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:464:13:HAL_RTCEx_TimeStampEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:480:19:HAL_RTCEx_PollForTimeStampEvent 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:538:19:HAL_RTCEx_SetWakeUpTimer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:611:19:HAL_RTCEx_SetWakeUpTimer_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:695:19:HAL_RTCEx_DeactivateWakeUpTimer 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:748:10:HAL_RTCEx_GetWakeUpTimer 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:760:6:HAL_RTCEx_WakeUpTimerIRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:785:13:HAL_RTCEx_WakeUpTimerEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:802:19:HAL_RTCEx_PollForWakeUpTimerEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:880:19:HAL_RTCEx_SetSmoothCalib 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:945:19:HAL_RTCEx_SetLowPowerCalib 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:985:19:HAL_RTCEx_SetSynchroShift 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1078:19:HAL_RTCEx_SetCalibrationOutPut 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1114:19:HAL_RTCEx_DeactivateCalibrationOutPut 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1144:19:HAL_RTCEx_SetRefClock 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1186:19:HAL_RTCEx_DeactivateRefClock 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1230:19:HAL_RTCEx_EnableBypassShadow 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1262:19:HAL_RTCEx_DisableBypassShadow 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1295:19:HAL_RTCEx_MonotonicCounterIncrement 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1315:19:HAL_RTCEx_MonotonicCounterGet 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1332:19:HAL_RTCEx_SetSSRU_IT 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1364:19:HAL_RTCEx_DeactivateSSRU 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1396:6:HAL_RTCEx_SSRUIRQHandler 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1421:13:HAL_RTCEx_SSRUEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1455:13:HAL_RTCEx_AlarmBEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1471:19:HAL_RTCEx_PollForAlarmBEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1534:19:HAL_RTCEx_SetTamper 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1599:19:HAL_RTCEx_SetTamper_IT 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1673:19:HAL_RTCEx_DeactivateTamper 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1709:19:HAL_RTCEx_PollForTamperEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1741:19:HAL_RTCEx_SetInternalTamper 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1781:19:HAL_RTCEx_SetInternalTamper_IT 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1827:19:HAL_RTCEx_DeactivateInternalTamper 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1856:19:HAL_RTCEx_PollForInternalTamperEvent 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1887:6:HAL_RTCEx_TamperIRQHandler 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1985:13:HAL_RTCEx_Tamper1EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2001:13:HAL_RTCEx_Tamper2EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2016:13:HAL_RTCEx_Tamper3EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2031:13:HAL_RTCEx_InternalTamper3EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2047:13:HAL_RTCEx_InternalTamper5EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2062:13:HAL_RTCEx_InternalTamper6EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2077:13:HAL_RTCEx_InternalTamper8EventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2119:6:HAL_RTCEx_BKUPWrite 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2142:10:HAL_RTCEx_BKUPRead 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d new file mode 100644 index 0000000..8b4a6c4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o new file mode 100644 index 0000000..bdd4ffc Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su new file mode 100644 index 0000000..62ff823 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su @@ -0,0 +1,51 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:178:19:HAL_RTCEx_SetTimeStamp 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:229:19:HAL_RTCEx_SetTimeStamp_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:272:19:HAL_RTCEx_DeactivateTimeStamp 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:308:19:HAL_RTCEx_SetInternalTimeStamp 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:338:19:HAL_RTCEx_DeactivateInternalTimeStamp 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:386:19:HAL_RTCEx_GetTimeStamp 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:441:6:HAL_RTCEx_TimeStampIRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:464:13:HAL_RTCEx_TimeStampEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:480:19:HAL_RTCEx_PollForTimeStampEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:538:19:HAL_RTCEx_SetWakeUpTimer 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:611:19:HAL_RTCEx_SetWakeUpTimer_IT 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:695:19:HAL_RTCEx_DeactivateWakeUpTimer 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:748:10:HAL_RTCEx_GetWakeUpTimer 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:760:6:HAL_RTCEx_WakeUpTimerIRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:785:13:HAL_RTCEx_WakeUpTimerEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:802:19:HAL_RTCEx_PollForWakeUpTimerEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:880:19:HAL_RTCEx_SetSmoothCalib 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:945:19:HAL_RTCEx_SetLowPowerCalib 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:985:19:HAL_RTCEx_SetSynchroShift 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1078:19:HAL_RTCEx_SetCalibrationOutPut 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1114:19:HAL_RTCEx_DeactivateCalibrationOutPut 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1144:19:HAL_RTCEx_SetRefClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1186:19:HAL_RTCEx_DeactivateRefClock 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1230:19:HAL_RTCEx_EnableBypassShadow 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1262:19:HAL_RTCEx_DisableBypassShadow 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1295:19:HAL_RTCEx_MonotonicCounterIncrement 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1315:19:HAL_RTCEx_MonotonicCounterGet 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1332:19:HAL_RTCEx_SetSSRU_IT 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1364:19:HAL_RTCEx_DeactivateSSRU 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1396:6:HAL_RTCEx_SSRUIRQHandler 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1421:13:HAL_RTCEx_SSRUEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1455:13:HAL_RTCEx_AlarmBEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1471:19:HAL_RTCEx_PollForAlarmBEvent 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1534:19:HAL_RTCEx_SetTamper 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1599:19:HAL_RTCEx_SetTamper_IT 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1673:19:HAL_RTCEx_DeactivateTamper 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1709:19:HAL_RTCEx_PollForTamperEvent 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1741:19:HAL_RTCEx_SetInternalTamper 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1781:19:HAL_RTCEx_SetInternalTamper_IT 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1827:19:HAL_RTCEx_DeactivateInternalTamper 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1856:19:HAL_RTCEx_PollForInternalTamperEvent 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1887:6:HAL_RTCEx_TamperIRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:1985:13:HAL_RTCEx_Tamper1EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2001:13:HAL_RTCEx_Tamper2EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2016:13:HAL_RTCEx_Tamper3EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2031:13:HAL_RTCEx_InternalTamper3EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2047:13:HAL_RTCEx_InternalTamper5EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2062:13:HAL_RTCEx_InternalTamper6EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2077:13:HAL_RTCEx_InternalTamper8EventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2119:6:HAL_RTCEx_BKUPWrite 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c:2142:10:HAL_RTCEx_BKUPRead 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo new file mode 100644 index 0000000..ba23fa6 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo @@ -0,0 +1,42 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1375:22:LL_PWR_UnselectSUBGHZSPI_NSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1385:22:LL_PWR_SelectSUBGHZSPI_NSS 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2035:22:LL_PWR_ClearFlag_RFBUSY 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2048:26:LL_PWR_IsActiveFlag_RFBUSYS 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2061:26:LL_PWR_IsActiveFlag_RFBUSYMS 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1675:22:LL_RCC_RF_EnableReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1685:22:LL_RCC_RF_DisableReset 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1705:26:LL_RCC_IsRFUnderReset 2 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:218:19:HAL_SUBGHZ_Init 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:335:19:HAL_SUBGHZ_DeInit 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:418:13:HAL_SUBGHZ_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:434:13:HAL_SUBGHZ_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:799:19:HAL_SUBGHZ_WriteRegisters 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:863:19:HAL_SUBGHZ_ReadRegisters 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:927:19:HAL_SUBGHZ_WriteRegister 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:942:19:HAL_SUBGHZ_ReadRegister 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:958:19:HAL_SUBGHZ_ExecSetCmd 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1034:19:HAL_SUBGHZ_ExecGetCmd 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1099:19:HAL_SUBGHZ_WriteBuffer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1159:19:HAL_SUBGHZ_ReadBuffer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1220:6:HAL_SUBGHZ_IRQHandler 12 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1356:13:HAL_SUBGHZ_TxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1372:13:HAL_SUBGHZ_RxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1388:13:HAL_SUBGHZ_PreambleDetectedCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1404:13:HAL_SUBGHZ_SyncWordValidCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1420:13:HAL_SUBGHZ_HeaderValidCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1436:13:HAL_SUBGHZ_HeaderErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1452:13:HAL_SUBGHZ_CRCErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1470:13:HAL_SUBGHZ_CADStatusCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1488:13:HAL_SUBGHZ_RxTxTimeoutCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1504:13:HAL_SUBGHZ_LrFhssHopCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1538:25:HAL_SUBGHZ_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1550:10:HAL_SUBGHZ_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1574:6:SUBGHZSPI_Init 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1610:7:SUBGHZSPI_DeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1626:19:SUBGHZSPI_Transmit 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1685:19:SUBGHZSPI_Receive 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1743:19:SUBGHZ_CheckDeviceReady 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1774:19:SUBGHZ_WaitOnBusy 3 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d new file mode 100644 index 0000000..12db9a1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o new file mode 100644 index 0000000..eb6a513 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su new file mode 100644 index 0000000..fcf063f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su @@ -0,0 +1,42 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1300:22:LL_PWR_SetRadioBusyTrigger 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1375:22:LL_PWR_UnselectSUBGHZSPI_NSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:1385:22:LL_PWR_SelectSUBGHZSPI_NSS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2035:22:LL_PWR_ClearFlag_RFBUSY 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2048:26:LL_PWR_IsActiveFlag_RFBUSYS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h:2061:26:LL_PWR_IsActiveFlag_RFBUSYMS 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1675:22:LL_RCC_RF_EnableReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1685:22:LL_RCC_RF_DisableReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:1705:26:LL_RCC_IsRFUnderReset 4 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:336:22:LL_EXTI_EnableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h:478:22:LL_EXTI_DisableIT_32_63 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:218:19:HAL_SUBGHZ_Init 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:335:19:HAL_SUBGHZ_DeInit 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:418:13:HAL_SUBGHZ_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:434:13:HAL_SUBGHZ_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:799:19:HAL_SUBGHZ_WriteRegisters 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:863:19:HAL_SUBGHZ_ReadRegisters 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:927:19:HAL_SUBGHZ_WriteRegister 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:942:19:HAL_SUBGHZ_ReadRegister 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:958:19:HAL_SUBGHZ_ExecSetCmd 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1034:19:HAL_SUBGHZ_ExecGetCmd 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1099:19:HAL_SUBGHZ_WriteBuffer 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1159:19:HAL_SUBGHZ_ReadBuffer 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1220:6:HAL_SUBGHZ_IRQHandler 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1356:13:HAL_SUBGHZ_TxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1372:13:HAL_SUBGHZ_RxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1388:13:HAL_SUBGHZ_PreambleDetectedCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1404:13:HAL_SUBGHZ_SyncWordValidCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1420:13:HAL_SUBGHZ_HeaderValidCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1436:13:HAL_SUBGHZ_HeaderErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1452:13:HAL_SUBGHZ_CRCErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1470:13:HAL_SUBGHZ_CADStatusCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1488:13:HAL_SUBGHZ_RxTxTimeoutCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1504:13:HAL_SUBGHZ_LrFhssHopCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1538:25:HAL_SUBGHZ_GetState 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1550:10:HAL_SUBGHZ_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1574:6:SUBGHZSPI_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1610:7:SUBGHZSPI_DeInit 4 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1626:19:SUBGHZSPI_Transmit 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1685:19:SUBGHZSPI_Receive 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1743:19:SUBGHZ_CheckDeviceReady 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c:1774:19:SUBGHZ_WaitOnBusy 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.d new file mode 100644 index 0000000..a6563fa --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o new file mode 100644 index 0000000..0e56c43 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.d new file mode 100644 index 0000000..6ce0986 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o new file mode 100644 index 0000000..6959b8a Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo new file mode 100644 index 0000000..2ced357 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo @@ -0,0 +1,72 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:307:19:HAL_UART_Init 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:380:19:HAL_HalfDuplex_Init 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:453:19:HAL_LIN_Init 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:550:19:HAL_MultiProcessor_Init 6 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:624:19:HAL_UART_DeInit 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:671:13:HAL_UART_MspInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:686:13:HAL_UART_MspDeInit 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1126:19:HAL_UART_Transmit 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1230:19:HAL_UART_Receive 15 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1331:19:HAL_UART_Transmit_IT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1418:19:HAL_UART_Receive_IT 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1478:19:HAL_UART_Transmit_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1567:19:HAL_UART_Receive_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1616:19:HAL_UART_DMAPause 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1646:19:HAL_UART_DMAResume 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1677:19:HAL_UART_DMAStop 13 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1752:19:HAL_UART_Abort 16 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1855:19:HAL_UART_AbortTransmit 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1914:19:HAL_UART_AbortReceive 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1982:19:HAL_UART_Abort_IT 19 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2135:19:HAL_UART_AbortTransmit_IT 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2226:19:HAL_UART_AbortReceive_IT 9 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2319:6:HAL_UART_IRQHandler 59 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2649:13:HAL_UART_TxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2664:13:HAL_UART_TxHalfCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2679:13:HAL_UART_RxCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2694:13:HAL_UART_RxHalfCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2709:13:HAL_UART_ErrorCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2724:13:HAL_UART_AbortCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2739:13:HAL_UART_AbortTransmitCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2754:13:HAL_UART_AbortReceiveCpltCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2771:13:HAL_UARTEx_RxEventCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2819:6:HAL_UART_ReceiverTimeout_Config 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2834:19:HAL_UART_EnableReceiverTimeout 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2872:19:HAL_UART_DisableReceiverTimeout 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2910:19:HAL_MultiProcessor_EnableMuteMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2930:19:HAL_MultiProcessor_DisableMuteMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2950:6:HAL_MultiProcessor_EnterMuteMode 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2960:19:HAL_HalfDuplex_EnableTransmitter 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2983:19:HAL_HalfDuplex_EnableReceiver 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3007:19:HAL_LIN_SendBreak 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3052:23:HAL_UART_GetState 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3068:10:HAL_UART_GetError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3114:19:UART_SetConfig 46 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3331:6:UART_AdvFeatureConfig 10 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3405:19:UART_CheckIdleState 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3458:19:UART_WaitOnFlagUntilTimeout 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3522:19:UART_Start_Receive_IT 20 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3594:19:UART_Start_Receive_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3651:13:UART_EndTxTransfer 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3667:13:UART_EndRxTransfer 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3693:13:UART_DMATransmitCplt 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3727:13:UART_DMATxHalfCplt 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3745:13:UART_DMAReceiveCplt 8 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3806:13:UART_DMARxHalfCplt 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3844:13:UART_DMAError 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3884:13:UART_DMAAbortOnError 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3907:13:UART_DMATxAbortCallback 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3962:13:UART_DMARxAbortCallback 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4014:13:UART_DMATxOnlyAbortCallback 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4047:13:UART_DMARxOnlyAbortCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4080:13:UART_TxISR_8BIT 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4109:13:UART_TxISR_16BIT 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4141:13:UART_TxISR_8BIT_FIFOEN 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4181:13:UART_TxISR_16BIT_FIFOEN 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4222:13:UART_EndTransmit_IT 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4247:13:UART_RxISR_8BIT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4338:13:UART_RxISR_16BIT 11 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4431:13:UART_RxISR_8BIT_FIFOEN 25 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4593:13:UART_RxISR_16BIT_FIFOEN 25 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d new file mode 100644 index 0000000..912b287 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o new file mode 100644 index 0000000..41426f6 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su new file mode 100644 index 0000000..15344f3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su @@ -0,0 +1,72 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2169:26:LL_RCC_GetUSARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:2200:26:LL_RCC_GetLPUARTClockSource 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:307:19:HAL_UART_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:380:19:HAL_HalfDuplex_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:453:19:HAL_LIN_Init 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:550:19:HAL_MultiProcessor_Init 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:624:19:HAL_UART_DeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:671:13:HAL_UART_MspInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:686:13:HAL_UART_MspDeInit 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1126:19:HAL_UART_Transmit 48 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1230:19:HAL_UART_Receive 48 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1331:19:HAL_UART_Transmit_IT 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1418:19:HAL_UART_Receive_IT 48 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1478:19:HAL_UART_Transmit_DMA 48 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1567:19:HAL_UART_Receive_DMA 48 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1616:19:HAL_UART_DMAPause 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1646:19:HAL_UART_DMAResume 112 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1677:19:HAL_UART_DMAStop 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1752:19:HAL_UART_Abort 136 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1855:19:HAL_UART_AbortTransmit 88 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1914:19:HAL_UART_AbortReceive 112 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:1982:19:HAL_UART_Abort_IT 144 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2135:19:HAL_UART_AbortTransmit_IT 88 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2226:19:HAL_UART_AbortReceive_IT 112 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2319:6:HAL_UART_IRQHandler 240 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2649:13:HAL_UART_TxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2664:13:HAL_UART_TxHalfCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2679:13:HAL_UART_RxCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2694:13:HAL_UART_RxHalfCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2709:13:HAL_UART_ErrorCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2724:13:HAL_UART_AbortCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2739:13:HAL_UART_AbortTransmitCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2754:13:HAL_UART_AbortReceiveCpltCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2771:13:HAL_UARTEx_RxEventCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2819:6:HAL_UART_ReceiverTimeout_Config 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2834:19:HAL_UART_EnableReceiverTimeout 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2872:19:HAL_UART_DisableReceiverTimeout 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2910:19:HAL_MultiProcessor_EnableMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2930:19:HAL_MultiProcessor_DisableMuteMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2950:6:HAL_MultiProcessor_EnterMuteMode 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2960:19:HAL_HalfDuplex_EnableTransmitter 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:2983:19:HAL_HalfDuplex_EnableReceiver 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3007:19:HAL_LIN_SendBreak 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3052:23:HAL_UART_GetState 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3068:10:HAL_UART_GetError 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3114:19:UART_SetConfig 80 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3331:6:UART_AdvFeatureConfig 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3405:19:UART_CheckIdleState 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3458:19:UART_WaitOnFlagUntilTimeout 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3522:19:UART_Start_Receive_IT 144 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3594:19:UART_Start_Receive_DMA 96 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3651:13:UART_EndTxTransfer 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3667:13:UART_EndRxTransfer 88 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3693:13:UART_DMATransmitCplt 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3727:13:UART_DMATxHalfCplt 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3745:13:UART_DMAReceiveCplt 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3806:13:UART_DMARxHalfCplt 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3844:13:UART_DMAError 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3884:13:UART_DMAAbortOnError 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3907:13:UART_DMATxAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:3962:13:UART_DMARxAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4014:13:UART_DMATxOnlyAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4047:13:UART_DMARxOnlyAbortCallback 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4080:13:UART_TxISR_8BIT 64 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4109:13:UART_TxISR_16BIT 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4141:13:UART_TxISR_8BIT_FIFOEN 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4181:13:UART_TxISR_16BIT_FIFOEN 72 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4222:13:UART_EndTransmit_IT 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4247:13:UART_RxISR_8BIT 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4338:13:UART_RxISR_16BIT 120 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4431:13:UART_RxISR_8BIT_FIFOEN 184 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c:4593:13:UART_RxISR_16BIT_FIFOEN 192 static,ignoring_inline_asm diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo new file mode 100644 index 0000000..258d89b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo @@ -0,0 +1,18 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 5 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 4 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 3 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 2 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:714:19:HAL_UARTEx_ReceiveToIdle 20 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:853:19:HAL_UARTEx_ReceiveToIdle_IT 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:931:19:HAL_UARTEx_ReceiveToIdle_DMA 7 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1012:29:HAL_UARTEx_GetRxEventType 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1036:13:UARTEx_Wakeup_AddressConfig 1 +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1054:13:UARTEx_SetNbDataToProcess 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d new file mode 100644 index 0000000..b09c808 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d @@ -0,0 +1,82 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o new file mode 100644 index 0000000..6ecd521 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su new file mode 100644 index 0000000..7d7d5a3 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su @@ -0,0 +1,18 @@ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:166:19:HAL_RS485Ex_Init 32 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:272:13:HAL_UARTEx_WakeupCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:287:13:HAL_UARTEx_RxFifoFullCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:302:13:HAL_UARTEx_TxFifoEmptyCallback 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:387:19:HAL_MultiProcessorEx_AddressLength_Set 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:425:19:HAL_UARTEx_StopModeWakeUpSourceConfig 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:480:19:HAL_UARTEx_EnableStopMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:499:19:HAL_UARTEx_DisableStopMode 40 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:518:19:HAL_UARTEx_EnableFifoMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:559:19:HAL_UARTEx_DisableFifoMode 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:605:19:HAL_UARTEx_SetTxFifoThreshold 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:654:19:HAL_UARTEx_SetRxFifoThreshold 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:714:19:HAL_UARTEx_ReceiveToIdle 40 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:853:19:HAL_UARTEx_ReceiveToIdle_IT 56 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:931:19:HAL_UARTEx_ReceiveToIdle_DMA 56 static,ignoring_inline_asm +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1012:29:HAL_UARTEx_GetRxEventType 16 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1036:13:UARTEx_Wakeup_AddressConfig 24 static +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c:1054:13:UARTEx_SetNbDataToProcess 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.cyclo new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.d b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.d new file mode 100644 index 0000000..6c22231 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.d @@ -0,0 +1,2 @@ +Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o: \ + ../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.c diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o new file mode 100644 index 0000000..4b0bb24 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.su b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.su new file mode 100644 index 0000000..e69de29 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk new file mode 100644 index 0000000..812da17 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk @@ -0,0 +1,90 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.c \ +../Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.c + +OBJS += \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o + +C_DEPS += \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d \ +./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.d + + +# Each subdirectory must supply rules for building sources it contributes +Drivers/STM32WLxx_HAL_Driver/Src/%.o Drivers/STM32WLxx_HAL_Driver/Src/%.su Drivers/STM32WLxx_HAL_Driver/Src/%.cyclo: ../Drivers/STM32WLxx_HAL_Driver/Src/%.c Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Drivers-2f-STM32WLxx_HAL_Driver-2f-Src + +clean-Drivers-2f-STM32WLxx_HAL_Driver-2f-Src: + -$(RM) ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.su ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.cyclo ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.d ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o ./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.su + +.PHONY: clean-Drivers-2f-STM32WLxx_HAL_Driver-2f-Src + diff --git a/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.elf b/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.elf new file mode 100644 index 0000000..7cd8c92 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.elf differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.list b/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.list new file mode 100644 index 0000000..5ae9609 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.list @@ -0,0 +1,37694 @@ + +LoRa-GPS-Tracker.elf: file format elf32-littlearm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 .isr_vector 00000138 08000000 08000000 00010000 2**0 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 1 .text 0000deb8 08000140 08000140 00010140 2**4 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .rodata 0000063c 0800dff8 0800dff8 0001dff8 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 3 .ARM.extab 00000000 0800e634 0800e634 00020090 2**0 + CONTENTS + 4 .ARM 00000008 0800e634 0800e634 0001e634 2**2 + CONTENTS, ALLOC, LOAD, READONLY, DATA + 5 .preinit_array 00000000 0800e63c 0800e63c 00020090 2**0 + CONTENTS, ALLOC, LOAD, DATA + 6 .init_array 00000004 0800e63c 0800e63c 0001e63c 2**2 + CONTENTS, ALLOC, LOAD, DATA + 7 .fini_array 00000004 0800e640 0800e640 0001e640 2**2 + CONTENTS, ALLOC, LOAD, DATA + 8 .data 00000090 20000000 0800e644 00020000 2**2 + CONTENTS, ALLOC, LOAD, DATA + 9 .bss 000009b8 20000090 0800e6d4 00020090 2**2 + ALLOC + 10 ._user_heap_stack 00000800 20000a48 0800e6d4 00020a48 2**0 + ALLOC + 11 .ARM.attributes 0000002a 00000000 00000000 00020090 2**0 + CONTENTS, READONLY + 12 .comment 00000043 00000000 00000000 000200ba 2**0 + CONTENTS, READONLY + 13 .debug_info 00023c81 00000000 00000000 000200fd 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 14 .debug_abbrev 000065bc 00000000 00000000 00043d7e 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 15 .debug_aranges 00002218 00000000 00000000 0004a340 2**3 + CONTENTS, READONLY, DEBUGGING, OCTETS + 16 .debug_rnglists 00001993 00000000 00000000 0004c558 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 17 .debug_macro 0002310c 00000000 00000000 0004deeb 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 18 .debug_line 00027dcb 00000000 00000000 00070ff7 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 19 .debug_str 000bcf95 00000000 00000000 00098dc2 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + 20 .debug_frame 000093fc 00000000 00000000 00155d58 2**2 + CONTENTS, READONLY, DEBUGGING, OCTETS + 21 .debug_line_str 00000060 00000000 00000000 0015f154 2**0 + CONTENTS, READONLY, DEBUGGING, OCTETS + +Disassembly of section .text: + +08000140 <__do_global_dtors_aux>: + 8000140: b510 push {r4, lr} + 8000142: 4c05 ldr r4, [pc, #20] ; (8000158 <__do_global_dtors_aux+0x18>) + 8000144: 7823 ldrb r3, [r4, #0] + 8000146: b933 cbnz r3, 8000156 <__do_global_dtors_aux+0x16> + 8000148: 4b04 ldr r3, [pc, #16] ; (800015c <__do_global_dtors_aux+0x1c>) + 800014a: b113 cbz r3, 8000152 <__do_global_dtors_aux+0x12> + 800014c: 4804 ldr r0, [pc, #16] ; (8000160 <__do_global_dtors_aux+0x20>) + 800014e: f3af 8000 nop.w + 8000152: 2301 movs r3, #1 + 8000154: 7023 strb r3, [r4, #0] + 8000156: bd10 pop {r4, pc} + 8000158: 20000090 .word 0x20000090 + 800015c: 00000000 .word 0x00000000 + 8000160: 0800dfe0 .word 0x0800dfe0 + +08000164 : + 8000164: b508 push {r3, lr} + 8000166: 4b03 ldr r3, [pc, #12] ; (8000174 ) + 8000168: b11b cbz r3, 8000172 + 800016a: 4903 ldr r1, [pc, #12] ; (8000178 ) + 800016c: 4803 ldr r0, [pc, #12] ; (800017c ) + 800016e: f3af 8000 nop.w + 8000172: bd08 pop {r3, pc} + 8000174: 00000000 .word 0x00000000 + 8000178: 20000094 .word 0x20000094 + 800017c: 0800dfe0 .word 0x0800dfe0 + +08000180 : + 8000180: 4603 mov r3, r0 + 8000182: f813 2b01 ldrb.w r2, [r3], #1 + 8000186: 2a00 cmp r2, #0 + 8000188: d1fb bne.n 8000182 + 800018a: 1a18 subs r0, r3, r0 + 800018c: 3801 subs r0, #1 + 800018e: 4770 bx lr + +08000190 : + 8000190: f001 01ff and.w r1, r1, #255 ; 0xff + 8000194: 2a10 cmp r2, #16 + 8000196: db2b blt.n 80001f0 + 8000198: f010 0f07 tst.w r0, #7 + 800019c: d008 beq.n 80001b0 + 800019e: f810 3b01 ldrb.w r3, [r0], #1 + 80001a2: 3a01 subs r2, #1 + 80001a4: 428b cmp r3, r1 + 80001a6: d02d beq.n 8000204 + 80001a8: f010 0f07 tst.w r0, #7 + 80001ac: b342 cbz r2, 8000200 + 80001ae: d1f6 bne.n 800019e + 80001b0: b4f0 push {r4, r5, r6, r7} + 80001b2: ea41 2101 orr.w r1, r1, r1, lsl #8 + 80001b6: ea41 4101 orr.w r1, r1, r1, lsl #16 + 80001ba: f022 0407 bic.w r4, r2, #7 + 80001be: f07f 0700 mvns.w r7, #0 + 80001c2: 2300 movs r3, #0 + 80001c4: e8f0 5602 ldrd r5, r6, [r0], #8 + 80001c8: 3c08 subs r4, #8 + 80001ca: ea85 0501 eor.w r5, r5, r1 + 80001ce: ea86 0601 eor.w r6, r6, r1 + 80001d2: fa85 f547 uadd8 r5, r5, r7 + 80001d6: faa3 f587 sel r5, r3, r7 + 80001da: fa86 f647 uadd8 r6, r6, r7 + 80001de: faa5 f687 sel r6, r5, r7 + 80001e2: b98e cbnz r6, 8000208 + 80001e4: d1ee bne.n 80001c4 + 80001e6: bcf0 pop {r4, r5, r6, r7} + 80001e8: f001 01ff and.w r1, r1, #255 ; 0xff + 80001ec: f002 0207 and.w r2, r2, #7 + 80001f0: b132 cbz r2, 8000200 + 80001f2: f810 3b01 ldrb.w r3, [r0], #1 + 80001f6: 3a01 subs r2, #1 + 80001f8: ea83 0301 eor.w r3, r3, r1 + 80001fc: b113 cbz r3, 8000204 + 80001fe: d1f8 bne.n 80001f2 + 8000200: 2000 movs r0, #0 + 8000202: 4770 bx lr + 8000204: 3801 subs r0, #1 + 8000206: 4770 bx lr + 8000208: 2d00 cmp r5, #0 + 800020a: bf06 itte eq + 800020c: 4635 moveq r5, r6 + 800020e: 3803 subeq r0, #3 + 8000210: 3807 subne r0, #7 + 8000212: f015 0f01 tst.w r5, #1 + 8000216: d107 bne.n 8000228 + 8000218: 3001 adds r0, #1 + 800021a: f415 7f80 tst.w r5, #256 ; 0x100 + 800021e: bf02 ittt eq + 8000220: 3001 addeq r0, #1 + 8000222: f415 3fc0 tsteq.w r5, #98304 ; 0x18000 + 8000226: 3001 addeq r0, #1 + 8000228: bcf0 pop {r4, r5, r6, r7} + 800022a: 3801 subs r0, #1 + 800022c: 4770 bx lr + 800022e: bf00 nop + +08000230 <__aeabi_uldivmod>: + 8000230: b953 cbnz r3, 8000248 <__aeabi_uldivmod+0x18> + 8000232: b94a cbnz r2, 8000248 <__aeabi_uldivmod+0x18> + 8000234: 2900 cmp r1, #0 + 8000236: bf08 it eq + 8000238: 2800 cmpeq r0, #0 + 800023a: bf1c itt ne + 800023c: f04f 31ff movne.w r1, #4294967295 + 8000240: f04f 30ff movne.w r0, #4294967295 + 8000244: f000 b970 b.w 8000528 <__aeabi_idiv0> + 8000248: f1ad 0c08 sub.w ip, sp, #8 + 800024c: e96d ce04 strd ip, lr, [sp, #-16]! + 8000250: f000 f806 bl 8000260 <__udivmoddi4> + 8000254: f8dd e004 ldr.w lr, [sp, #4] + 8000258: e9dd 2302 ldrd r2, r3, [sp, #8] + 800025c: b004 add sp, #16 + 800025e: 4770 bx lr + +08000260 <__udivmoddi4>: + 8000260: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 8000264: 9e08 ldr r6, [sp, #32] + 8000266: 460d mov r5, r1 + 8000268: 4604 mov r4, r0 + 800026a: 460f mov r7, r1 + 800026c: 2b00 cmp r3, #0 + 800026e: d14a bne.n 8000306 <__udivmoddi4+0xa6> + 8000270: 428a cmp r2, r1 + 8000272: 4694 mov ip, r2 + 8000274: d965 bls.n 8000342 <__udivmoddi4+0xe2> + 8000276: fab2 f382 clz r3, r2 + 800027a: b143 cbz r3, 800028e <__udivmoddi4+0x2e> + 800027c: fa02 fc03 lsl.w ip, r2, r3 + 8000280: f1c3 0220 rsb r2, r3, #32 + 8000284: 409f lsls r7, r3 + 8000286: fa20 f202 lsr.w r2, r0, r2 + 800028a: 4317 orrs r7, r2 + 800028c: 409c lsls r4, r3 + 800028e: ea4f 4e1c mov.w lr, ip, lsr #16 + 8000292: fa1f f58c uxth.w r5, ip + 8000296: fbb7 f1fe udiv r1, r7, lr + 800029a: 0c22 lsrs r2, r4, #16 + 800029c: fb0e 7711 mls r7, lr, r1, r7 + 80002a0: ea42 4207 orr.w r2, r2, r7, lsl #16 + 80002a4: fb01 f005 mul.w r0, r1, r5 + 80002a8: 4290 cmp r0, r2 + 80002aa: d90a bls.n 80002c2 <__udivmoddi4+0x62> + 80002ac: eb1c 0202 adds.w r2, ip, r2 + 80002b0: f101 37ff add.w r7, r1, #4294967295 + 80002b4: f080 811b bcs.w 80004ee <__udivmoddi4+0x28e> + 80002b8: 4290 cmp r0, r2 + 80002ba: f240 8118 bls.w 80004ee <__udivmoddi4+0x28e> + 80002be: 3902 subs r1, #2 + 80002c0: 4462 add r2, ip + 80002c2: 1a12 subs r2, r2, r0 + 80002c4: b2a4 uxth r4, r4 + 80002c6: fbb2 f0fe udiv r0, r2, lr + 80002ca: fb0e 2210 mls r2, lr, r0, r2 + 80002ce: ea44 4402 orr.w r4, r4, r2, lsl #16 + 80002d2: fb00 f505 mul.w r5, r0, r5 + 80002d6: 42a5 cmp r5, r4 + 80002d8: d90a bls.n 80002f0 <__udivmoddi4+0x90> + 80002da: eb1c 0404 adds.w r4, ip, r4 + 80002de: f100 32ff add.w r2, r0, #4294967295 + 80002e2: f080 8106 bcs.w 80004f2 <__udivmoddi4+0x292> + 80002e6: 42a5 cmp r5, r4 + 80002e8: f240 8103 bls.w 80004f2 <__udivmoddi4+0x292> + 80002ec: 4464 add r4, ip + 80002ee: 3802 subs r0, #2 + 80002f0: ea40 4001 orr.w r0, r0, r1, lsl #16 + 80002f4: 1b64 subs r4, r4, r5 + 80002f6: 2100 movs r1, #0 + 80002f8: b11e cbz r6, 8000302 <__udivmoddi4+0xa2> + 80002fa: 40dc lsrs r4, r3 + 80002fc: 2300 movs r3, #0 + 80002fe: e9c6 4300 strd r4, r3, [r6] + 8000302: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 8000306: 428b cmp r3, r1 + 8000308: d908 bls.n 800031c <__udivmoddi4+0xbc> + 800030a: 2e00 cmp r6, #0 + 800030c: f000 80ec beq.w 80004e8 <__udivmoddi4+0x288> + 8000310: 2100 movs r1, #0 + 8000312: e9c6 0500 strd r0, r5, [r6] + 8000316: 4608 mov r0, r1 + 8000318: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800031c: fab3 f183 clz r1, r3 + 8000320: 2900 cmp r1, #0 + 8000322: d149 bne.n 80003b8 <__udivmoddi4+0x158> + 8000324: 42ab cmp r3, r5 + 8000326: d302 bcc.n 800032e <__udivmoddi4+0xce> + 8000328: 4282 cmp r2, r0 + 800032a: f200 80f7 bhi.w 800051c <__udivmoddi4+0x2bc> + 800032e: 1a84 subs r4, r0, r2 + 8000330: eb65 0203 sbc.w r2, r5, r3 + 8000334: 2001 movs r0, #1 + 8000336: 4617 mov r7, r2 + 8000338: 2e00 cmp r6, #0 + 800033a: d0e2 beq.n 8000302 <__udivmoddi4+0xa2> + 800033c: e9c6 4700 strd r4, r7, [r6] + 8000340: e7df b.n 8000302 <__udivmoddi4+0xa2> + 8000342: b902 cbnz r2, 8000346 <__udivmoddi4+0xe6> + 8000344: deff udf #255 ; 0xff + 8000346: fab2 f382 clz r3, r2 + 800034a: 2b00 cmp r3, #0 + 800034c: f040 808f bne.w 800046e <__udivmoddi4+0x20e> + 8000350: 1a8a subs r2, r1, r2 + 8000352: ea4f 471c mov.w r7, ip, lsr #16 + 8000356: fa1f fe8c uxth.w lr, ip + 800035a: 2101 movs r1, #1 + 800035c: fbb2 f5f7 udiv r5, r2, r7 + 8000360: fb07 2015 mls r0, r7, r5, r2 + 8000364: 0c22 lsrs r2, r4, #16 + 8000366: ea42 4200 orr.w r2, r2, r0, lsl #16 + 800036a: fb0e f005 mul.w r0, lr, r5 + 800036e: 4290 cmp r0, r2 + 8000370: d908 bls.n 8000384 <__udivmoddi4+0x124> + 8000372: eb1c 0202 adds.w r2, ip, r2 + 8000376: f105 38ff add.w r8, r5, #4294967295 + 800037a: d202 bcs.n 8000382 <__udivmoddi4+0x122> + 800037c: 4290 cmp r0, r2 + 800037e: f200 80ca bhi.w 8000516 <__udivmoddi4+0x2b6> + 8000382: 4645 mov r5, r8 + 8000384: 1a12 subs r2, r2, r0 + 8000386: b2a4 uxth r4, r4 + 8000388: fbb2 f0f7 udiv r0, r2, r7 + 800038c: fb07 2210 mls r2, r7, r0, r2 + 8000390: ea44 4402 orr.w r4, r4, r2, lsl #16 + 8000394: fb0e fe00 mul.w lr, lr, r0 + 8000398: 45a6 cmp lr, r4 + 800039a: d908 bls.n 80003ae <__udivmoddi4+0x14e> + 800039c: eb1c 0404 adds.w r4, ip, r4 + 80003a0: f100 32ff add.w r2, r0, #4294967295 + 80003a4: d202 bcs.n 80003ac <__udivmoddi4+0x14c> + 80003a6: 45a6 cmp lr, r4 + 80003a8: f200 80ba bhi.w 8000520 <__udivmoddi4+0x2c0> + 80003ac: 4610 mov r0, r2 + 80003ae: eba4 040e sub.w r4, r4, lr + 80003b2: ea40 4005 orr.w r0, r0, r5, lsl #16 + 80003b6: e79f b.n 80002f8 <__udivmoddi4+0x98> + 80003b8: f1c1 0720 rsb r7, r1, #32 + 80003bc: 408b lsls r3, r1 + 80003be: fa22 fc07 lsr.w ip, r2, r7 + 80003c2: ea4c 0c03 orr.w ip, ip, r3 + 80003c6: fa05 f401 lsl.w r4, r5, r1 + 80003ca: fa20 f307 lsr.w r3, r0, r7 + 80003ce: 40fd lsrs r5, r7 + 80003d0: 4323 orrs r3, r4 + 80003d2: fa00 f901 lsl.w r9, r0, r1 + 80003d6: ea4f 401c mov.w r0, ip, lsr #16 + 80003da: fa1f fe8c uxth.w lr, ip + 80003de: fbb5 f8f0 udiv r8, r5, r0 + 80003e2: 0c1c lsrs r4, r3, #16 + 80003e4: fb00 5518 mls r5, r0, r8, r5 + 80003e8: ea44 4405 orr.w r4, r4, r5, lsl #16 + 80003ec: fb08 f50e mul.w r5, r8, lr + 80003f0: 42a5 cmp r5, r4 + 80003f2: fa02 f201 lsl.w r2, r2, r1 + 80003f6: d90b bls.n 8000410 <__udivmoddi4+0x1b0> + 80003f8: eb1c 0404 adds.w r4, ip, r4 + 80003fc: f108 3aff add.w sl, r8, #4294967295 + 8000400: f080 8087 bcs.w 8000512 <__udivmoddi4+0x2b2> + 8000404: 42a5 cmp r5, r4 + 8000406: f240 8084 bls.w 8000512 <__udivmoddi4+0x2b2> + 800040a: f1a8 0802 sub.w r8, r8, #2 + 800040e: 4464 add r4, ip + 8000410: 1b64 subs r4, r4, r5 + 8000412: b29d uxth r5, r3 + 8000414: fbb4 f3f0 udiv r3, r4, r0 + 8000418: fb00 4413 mls r4, r0, r3, r4 + 800041c: ea45 4404 orr.w r4, r5, r4, lsl #16 + 8000420: fb03 fe0e mul.w lr, r3, lr + 8000424: 45a6 cmp lr, r4 + 8000426: d908 bls.n 800043a <__udivmoddi4+0x1da> + 8000428: eb1c 0404 adds.w r4, ip, r4 + 800042c: f103 30ff add.w r0, r3, #4294967295 + 8000430: d26b bcs.n 800050a <__udivmoddi4+0x2aa> + 8000432: 45a6 cmp lr, r4 + 8000434: d969 bls.n 800050a <__udivmoddi4+0x2aa> + 8000436: 3b02 subs r3, #2 + 8000438: 4464 add r4, ip + 800043a: ea43 4008 orr.w r0, r3, r8, lsl #16 + 800043e: fba0 8302 umull r8, r3, r0, r2 + 8000442: eba4 040e sub.w r4, r4, lr + 8000446: 429c cmp r4, r3 + 8000448: 46c6 mov lr, r8 + 800044a: 461d mov r5, r3 + 800044c: d355 bcc.n 80004fa <__udivmoddi4+0x29a> + 800044e: d052 beq.n 80004f6 <__udivmoddi4+0x296> + 8000450: b156 cbz r6, 8000468 <__udivmoddi4+0x208> + 8000452: ebb9 030e subs.w r3, r9, lr + 8000456: eb64 0405 sbc.w r4, r4, r5 + 800045a: fa04 f707 lsl.w r7, r4, r7 + 800045e: 40cb lsrs r3, r1 + 8000460: 40cc lsrs r4, r1 + 8000462: 431f orrs r7, r3 + 8000464: e9c6 7400 strd r7, r4, [r6] + 8000468: 2100 movs r1, #0 + 800046a: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800046e: f1c3 0120 rsb r1, r3, #32 + 8000472: fa02 fc03 lsl.w ip, r2, r3 + 8000476: fa20 f201 lsr.w r2, r0, r1 + 800047a: fa25 f101 lsr.w r1, r5, r1 + 800047e: 409d lsls r5, r3 + 8000480: 432a orrs r2, r5 + 8000482: ea4f 471c mov.w r7, ip, lsr #16 + 8000486: fa1f fe8c uxth.w lr, ip + 800048a: fbb1 f0f7 udiv r0, r1, r7 + 800048e: fb07 1510 mls r5, r7, r0, r1 + 8000492: 0c11 lsrs r1, r2, #16 + 8000494: ea41 4105 orr.w r1, r1, r5, lsl #16 + 8000498: fb00 f50e mul.w r5, r0, lr + 800049c: 428d cmp r5, r1 + 800049e: fa04 f403 lsl.w r4, r4, r3 + 80004a2: d908 bls.n 80004b6 <__udivmoddi4+0x256> + 80004a4: eb1c 0101 adds.w r1, ip, r1 + 80004a8: f100 38ff add.w r8, r0, #4294967295 + 80004ac: d22f bcs.n 800050e <__udivmoddi4+0x2ae> + 80004ae: 428d cmp r5, r1 + 80004b0: d92d bls.n 800050e <__udivmoddi4+0x2ae> + 80004b2: 3802 subs r0, #2 + 80004b4: 4461 add r1, ip + 80004b6: 1b49 subs r1, r1, r5 + 80004b8: b292 uxth r2, r2 + 80004ba: fbb1 f5f7 udiv r5, r1, r7 + 80004be: fb07 1115 mls r1, r7, r5, r1 + 80004c2: ea42 4201 orr.w r2, r2, r1, lsl #16 + 80004c6: fb05 f10e mul.w r1, r5, lr + 80004ca: 4291 cmp r1, r2 + 80004cc: d908 bls.n 80004e0 <__udivmoddi4+0x280> + 80004ce: eb1c 0202 adds.w r2, ip, r2 + 80004d2: f105 38ff add.w r8, r5, #4294967295 + 80004d6: d216 bcs.n 8000506 <__udivmoddi4+0x2a6> + 80004d8: 4291 cmp r1, r2 + 80004da: d914 bls.n 8000506 <__udivmoddi4+0x2a6> + 80004dc: 3d02 subs r5, #2 + 80004de: 4462 add r2, ip + 80004e0: 1a52 subs r2, r2, r1 + 80004e2: ea45 4100 orr.w r1, r5, r0, lsl #16 + 80004e6: e739 b.n 800035c <__udivmoddi4+0xfc> + 80004e8: 4631 mov r1, r6 + 80004ea: 4630 mov r0, r6 + 80004ec: e709 b.n 8000302 <__udivmoddi4+0xa2> + 80004ee: 4639 mov r1, r7 + 80004f0: e6e7 b.n 80002c2 <__udivmoddi4+0x62> + 80004f2: 4610 mov r0, r2 + 80004f4: e6fc b.n 80002f0 <__udivmoddi4+0x90> + 80004f6: 45c1 cmp r9, r8 + 80004f8: d2aa bcs.n 8000450 <__udivmoddi4+0x1f0> + 80004fa: ebb8 0e02 subs.w lr, r8, r2 + 80004fe: eb63 050c sbc.w r5, r3, ip + 8000502: 3801 subs r0, #1 + 8000504: e7a4 b.n 8000450 <__udivmoddi4+0x1f0> + 8000506: 4645 mov r5, r8 + 8000508: e7ea b.n 80004e0 <__udivmoddi4+0x280> + 800050a: 4603 mov r3, r0 + 800050c: e795 b.n 800043a <__udivmoddi4+0x1da> + 800050e: 4640 mov r0, r8 + 8000510: e7d1 b.n 80004b6 <__udivmoddi4+0x256> + 8000512: 46d0 mov r8, sl + 8000514: e77c b.n 8000410 <__udivmoddi4+0x1b0> + 8000516: 3d02 subs r5, #2 + 8000518: 4462 add r2, ip + 800051a: e733 b.n 8000384 <__udivmoddi4+0x124> + 800051c: 4608 mov r0, r1 + 800051e: e70b b.n 8000338 <__udivmoddi4+0xd8> + 8000520: 4464 add r4, ip + 8000522: 3802 subs r0, #2 + 8000524: e743 b.n 80003ae <__udivmoddi4+0x14e> + 8000526: bf00 nop + +08000528 <__aeabi_idiv0>: + 8000528: 4770 bx lr + 800052a: bf00 nop + +0800052c : + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC + * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH + * @retval None + */ +__STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) +{ + 800052c: b480 push {r7} + 800052e: b085 sub sp, #20 + 8000530: af00 add r7, sp, #0 + 8000532: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->AHB2ENR, Periphs); + 8000534: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000538: 6cda ldr r2, [r3, #76] ; 0x4c + 800053a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800053e: 687b ldr r3, [r7, #4] + 8000540: 4313 orrs r3, r2 + 8000542: 64cb str r3, [r1, #76] ; 0x4c + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8000544: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000548: 6cda ldr r2, [r3, #76] ; 0x4c + 800054a: 687b ldr r3, [r7, #4] + 800054c: 4013 ands r3, r2 + 800054e: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000550: 68fb ldr r3, [r7, #12] +} + 8000552: bf00 nop + 8000554: 3714 adds r7, #20 + 8000556: 46bd mov sp, r7 + 8000558: bc80 pop {r7} + 800055a: 4770 bx lr + +0800055c : + * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 + * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) +{ + 800055c: b480 push {r7} + 800055e: b085 sub sp, #20 + 8000560: af00 add r7, sp, #0 + 8000562: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB2ENR, Periphs); + 8000564: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000568: 6e1a ldr r2, [r3, #96] ; 0x60 + 800056a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800056e: 687b ldr r3, [r7, #4] + 8000570: 4313 orrs r3, r2 + 8000572: 660b str r3, [r1, #96] ; 0x60 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 8000574: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000578: 6e1a ldr r2, [r3, #96] ; 0x60 + 800057a: 687b ldr r3, [r7, #4] + 800057c: 4013 ands r3, r2 + 800057e: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000580: 68fb ldr r3, [r7, #12] +} + 8000582: bf00 nop + 8000584: 3714 adds r7, #20 + 8000586: 46bd mov sp, r7 + 8000588: bc80 pop {r7} + 800058a: 4770 bx lr + +0800058c : + +ADC_HandleTypeDef hadc; + +/* ADC init function */ +void MX_ADC_Init(void) +{ + 800058c: b580 push {r7, lr} + 800058e: af00 add r7, sp, #0 + + /* USER CODE END ADC_Init 1 */ + + /** Configure the global features of the ADC (Clock, Resolution, Data Alignment and number of conversion) + */ + hadc.Instance = ADC; + 8000590: 4b23 ldr r3, [pc, #140] ; (8000620 ) + 8000592: 4a24 ldr r2, [pc, #144] ; (8000624 ) + 8000594: 601a str r2, [r3, #0] + hadc.Init.ClockPrescaler = ADC_CLOCK_SYNC_PCLK_DIV1; + 8000596: 4b22 ldr r3, [pc, #136] ; (8000620 ) + 8000598: f04f 4240 mov.w r2, #3221225472 ; 0xc0000000 + 800059c: 605a str r2, [r3, #4] + hadc.Init.Resolution = ADC_RESOLUTION_12B; + 800059e: 4b20 ldr r3, [pc, #128] ; (8000620 ) + 80005a0: 2200 movs r2, #0 + 80005a2: 609a str r2, [r3, #8] + hadc.Init.DataAlign = ADC_DATAALIGN_RIGHT; + 80005a4: 4b1e ldr r3, [pc, #120] ; (8000620 ) + 80005a6: 2200 movs r2, #0 + 80005a8: 60da str r2, [r3, #12] + hadc.Init.ScanConvMode = ADC_SCAN_DISABLE; + 80005aa: 4b1d ldr r3, [pc, #116] ; (8000620 ) + 80005ac: 2200 movs r2, #0 + 80005ae: 611a str r2, [r3, #16] + hadc.Init.EOCSelection = ADC_EOC_SINGLE_CONV; + 80005b0: 4b1b ldr r3, [pc, #108] ; (8000620 ) + 80005b2: 2204 movs r2, #4 + 80005b4: 615a str r2, [r3, #20] + hadc.Init.LowPowerAutoWait = DISABLE; + 80005b6: 4b1a ldr r3, [pc, #104] ; (8000620 ) + 80005b8: 2200 movs r2, #0 + 80005ba: 761a strb r2, [r3, #24] + hadc.Init.LowPowerAutoPowerOff = DISABLE; + 80005bc: 4b18 ldr r3, [pc, #96] ; (8000620 ) + 80005be: 2200 movs r2, #0 + 80005c0: 765a strb r2, [r3, #25] + hadc.Init.ContinuousConvMode = DISABLE; + 80005c2: 4b17 ldr r3, [pc, #92] ; (8000620 ) + 80005c4: 2200 movs r2, #0 + 80005c6: 769a strb r2, [r3, #26] + hadc.Init.NbrOfConversion = 1; + 80005c8: 4b15 ldr r3, [pc, #84] ; (8000620 ) + 80005ca: 2201 movs r2, #1 + 80005cc: 61da str r2, [r3, #28] + hadc.Init.DiscontinuousConvMode = DISABLE; + 80005ce: 4b14 ldr r3, [pc, #80] ; (8000620 ) + 80005d0: 2200 movs r2, #0 + 80005d2: f883 2020 strb.w r2, [r3, #32] + hadc.Init.ExternalTrigConv = ADC_SOFTWARE_START; + 80005d6: 4b12 ldr r3, [pc, #72] ; (8000620 ) + 80005d8: 2200 movs r2, #0 + 80005da: 625a str r2, [r3, #36] ; 0x24 + hadc.Init.ExternalTrigConvEdge = ADC_EXTERNALTRIGCONVEDGE_NONE; + 80005dc: 4b10 ldr r3, [pc, #64] ; (8000620 ) + 80005de: 2200 movs r2, #0 + 80005e0: 629a str r2, [r3, #40] ; 0x28 + hadc.Init.DMAContinuousRequests = DISABLE; + 80005e2: 4b0f ldr r3, [pc, #60] ; (8000620 ) + 80005e4: 2200 movs r2, #0 + 80005e6: f883 202c strb.w r2, [r3, #44] ; 0x2c + hadc.Init.Overrun = ADC_OVR_DATA_PRESERVED; + 80005ea: 4b0d ldr r3, [pc, #52] ; (8000620 ) + 80005ec: 2200 movs r2, #0 + 80005ee: 631a str r2, [r3, #48] ; 0x30 + hadc.Init.SamplingTimeCommon1 = ADC_SAMPLETIME_1CYCLE_5; + 80005f0: 4b0b ldr r3, [pc, #44] ; (8000620 ) + 80005f2: 2200 movs r2, #0 + 80005f4: 635a str r2, [r3, #52] ; 0x34 + hadc.Init.SamplingTimeCommon2 = ADC_SAMPLETIME_1CYCLE_5; + 80005f6: 4b0a ldr r3, [pc, #40] ; (8000620 ) + 80005f8: 2200 movs r2, #0 + 80005fa: 639a str r2, [r3, #56] ; 0x38 + hadc.Init.OversamplingMode = DISABLE; + 80005fc: 4b08 ldr r3, [pc, #32] ; (8000620 ) + 80005fe: 2200 movs r2, #0 + 8000600: f883 203c strb.w r2, [r3, #60] ; 0x3c + hadc.Init.TriggerFrequencyMode = ADC_TRIGGER_FREQ_HIGH; + 8000604: 4b06 ldr r3, [pc, #24] ; (8000620 ) + 8000606: 2200 movs r2, #0 + 8000608: 64da str r2, [r3, #76] ; 0x4c + if (HAL_ADC_Init(&hadc) != HAL_OK) + 800060a: 4805 ldr r0, [pc, #20] ; (8000620 ) + 800060c: f001 fc6a bl 8001ee4 + 8000610: 4603 mov r3, r0 + 8000612: 2b00 cmp r3, #0 + 8000614: d001 beq.n 800061a + { + Error_Handler(); + 8000616: f000 f975 bl 8000904 + } + /* USER CODE BEGIN ADC_Init 2 */ + + /* USER CODE END ADC_Init 2 */ + +} + 800061a: bf00 nop + 800061c: bd80 pop {r7, pc} + 800061e: bf00 nop + 8000620: 200000ac .word 0x200000ac + 8000624: 40012400 .word 0x40012400 + +08000628 : + +void HAL_ADC_MspInit(ADC_HandleTypeDef* adcHandle) +{ + 8000628: b580 push {r7, lr} + 800062a: b088 sub sp, #32 + 800062c: af00 add r7, sp, #0 + 800062e: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 8000630: f107 030c add.w r3, r7, #12 + 8000634: 2200 movs r2, #0 + 8000636: 601a str r2, [r3, #0] + 8000638: 605a str r2, [r3, #4] + 800063a: 609a str r2, [r3, #8] + 800063c: 60da str r2, [r3, #12] + 800063e: 611a str r2, [r3, #16] + if(adcHandle->Instance==ADC) + 8000640: 687b ldr r3, [r7, #4] + 8000642: 681b ldr r3, [r3, #0] + 8000644: 4a0c ldr r2, [pc, #48] ; (8000678 ) + 8000646: 4293 cmp r3, r2 + 8000648: d112 bne.n 8000670 + { + /* USER CODE BEGIN ADC_MspInit 0 */ + + /* USER CODE END ADC_MspInit 0 */ + /* ADC clock enable */ + __HAL_RCC_ADC_CLK_ENABLE(); + 800064a: f44f 7000 mov.w r0, #512 ; 0x200 + 800064e: f7ff ff85 bl 800055c + + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000652: 2002 movs r0, #2 + 8000654: f7ff ff6a bl 800052c + /**ADC GPIO Configuration + PB4 ------> ADC_IN3 + */ + GPIO_InitStruct.Pin = V_BAT_Pin; + 8000658: 2310 movs r3, #16 + 800065a: 60fb str r3, [r7, #12] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 800065c: 2303 movs r3, #3 + 800065e: 613b str r3, [r7, #16] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000660: 2300 movs r3, #0 + 8000662: 617b str r3, [r7, #20] + HAL_GPIO_Init(V_BAT_GPIO_Port, &GPIO_InitStruct); + 8000664: f107 030c add.w r3, r7, #12 + 8000668: 4619 mov r1, r3 + 800066a: 4804 ldr r0, [pc, #16] ; (800067c ) + 800066c: f002 faf6 bl 8002c5c + + /* USER CODE BEGIN ADC_MspInit 1 */ + + /* USER CODE END ADC_MspInit 1 */ + } +} + 8000670: bf00 nop + 8000672: 3720 adds r7, #32 + 8000674: 46bd mov sp, r7 + 8000676: bd80 pop {r7, pc} + 8000678: 40012400 .word 0x40012400 + 800067c: 48000400 .word 0x48000400 + +08000680 : +{ + 8000680: b480 push {r7} + 8000682: b085 sub sp, #20 + 8000684: af00 add r7, sp, #0 + 8000686: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB1ENR, Periphs); + 8000688: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800068c: 6c9a ldr r2, [r3, #72] ; 0x48 + 800068e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8000692: 687b ldr r3, [r7, #4] + 8000694: 4313 orrs r3, r2 + 8000696: 648b str r3, [r1, #72] ; 0x48 + tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); + 8000698: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800069c: 6c9a ldr r2, [r3, #72] ; 0x48 + 800069e: 687b ldr r3, [r7, #4] + 80006a0: 4013 ands r3, r2 + 80006a2: 60fb str r3, [r7, #12] + (void)tmpreg; + 80006a4: 68fb ldr r3, [r7, #12] +} + 80006a6: bf00 nop + 80006a8: 3714 adds r7, #20 + 80006aa: 46bd mov sp, r7 + 80006ac: bc80 pop {r7} + 80006ae: 4770 bx lr + +080006b0 : + +/** + * Enable DMA controller clock + */ +void MX_DMA_Init(void) +{ + 80006b0: b580 push {r7, lr} + 80006b2: af00 add r7, sp, #0 + + /* DMA controller clock enable */ + __HAL_RCC_DMAMUX1_CLK_ENABLE(); + 80006b4: 2004 movs r0, #4 + 80006b6: f7ff ffe3 bl 8000680 + __HAL_RCC_DMA1_CLK_ENABLE(); + 80006ba: 2001 movs r0, #1 + 80006bc: f7ff ffe0 bl 8000680 + + /* DMA interrupt init */ + /* DMA1_Channel1_IRQn interrupt configuration */ + HAL_NVIC_SetPriority(DMA1_Channel1_IRQn, 0, 0); + 80006c0: 2200 movs r2, #0 + 80006c2: 2100 movs r1, #0 + 80006c4: 200b movs r0, #11 + 80006c6: f001 fe9c bl 8002402 + HAL_NVIC_EnableIRQ(DMA1_Channel1_IRQn); + 80006ca: 200b movs r0, #11 + 80006cc: f001 feb3 bl 8002436 + +} + 80006d0: bf00 nop + 80006d2: bd80 pop {r7, pc} + +080006d4 : +{ + 80006d4: b480 push {r7} + 80006d6: b085 sub sp, #20 + 80006d8: af00 add r7, sp, #0 + 80006da: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 80006dc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80006e0: 6cda ldr r2, [r3, #76] ; 0x4c + 80006e2: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80006e6: 687b ldr r3, [r7, #4] + 80006e8: 4313 orrs r3, r2 + 80006ea: 64cb str r3, [r1, #76] ; 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 80006ec: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80006f0: 6cda ldr r2, [r3, #76] ; 0x4c + 80006f2: 687b ldr r3, [r7, #4] + 80006f4: 4013 ands r3, r2 + 80006f6: 60fb str r3, [r7, #12] + (void)tmpreg; + 80006f8: 68fb ldr r3, [r7, #12] +} + 80006fa: bf00 nop + 80006fc: 3714 adds r7, #20 + 80006fe: 46bd mov sp, r7 + 8000700: bc80 pop {r7} + 8000702: 4770 bx lr + +08000704 : + * EXTI + * Free pins are configured automatically as Analog (this feature is enabled through + * the Code Generation settings) +*/ +void MX_GPIO_Init(void) +{ + 8000704: b580 push {r7, lr} + 8000706: b086 sub sp, #24 + 8000708: af00 add r7, sp, #0 + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 800070a: 1d3b adds r3, r7, #4 + 800070c: 2200 movs r2, #0 + 800070e: 601a str r2, [r3, #0] + 8000710: 605a str r2, [r3, #4] + 8000712: 609a str r2, [r3, #8] + 8000714: 60da str r2, [r3, #12] + 8000716: 611a str r2, [r3, #16] + + /* GPIO Ports Clock Enable */ + __HAL_RCC_GPIOB_CLK_ENABLE(); + 8000718: 2002 movs r0, #2 + 800071a: f7ff ffdb bl 80006d4 + __HAL_RCC_GPIOA_CLK_ENABLE(); + 800071e: 2001 movs r0, #1 + 8000720: f7ff ffd8 bl 80006d4 + __HAL_RCC_GPIOH_CLK_ENABLE(); + 8000724: 2080 movs r0, #128 ; 0x80 + 8000726: f7ff ffd5 bl 80006d4 + __HAL_RCC_GPIOC_CLK_ENABLE(); + 800072a: 2004 movs r0, #4 + 800072c: f7ff ffd2 bl 80006d4 + + /*Configure GPIO pin Output Level */ + HAL_GPIO_WritePin(GPIOB, BAT_E_Pin|STATUS_Pin, GPIO_PIN_RESET); + 8000730: 2200 movs r2, #0 + 8000732: f44f 5181 mov.w r1, #4128 ; 0x1020 + 8000736: 4829 ldr r0, [pc, #164] ; (80007dc ) + 8000738: f002 fcbe bl 80030b8 + + /*Configure GPIO pins : PB3 PB8 PB0 PB2 */ + GPIO_InitStruct.Pin = GPIO_PIN_3|GPIO_PIN_8|GPIO_PIN_0|GPIO_PIN_2; + 800073c: f240 130d movw r3, #269 ; 0x10d + 8000740: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8000742: 2303 movs r3, #3 + 8000744: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000746: 2300 movs r3, #0 + 8000748: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 800074a: 1d3b adds r3, r7, #4 + 800074c: 4619 mov r1, r3 + 800074e: 4823 ldr r0, [pc, #140] ; (80007dc ) + 8000750: f002 fa84 bl 8002c5c + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = BAT_E_Pin; + 8000754: 2320 movs r3, #32 + 8000756: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 8000758: 2301 movs r3, #1 + 800075a: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_PULLDOWN; + 800075c: 2302 movs r3, #2 + 800075e: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8000760: 2300 movs r3, #0 + 8000762: 613b str r3, [r7, #16] + HAL_GPIO_Init(BAT_E_GPIO_Port, &GPIO_InitStruct); + 8000764: 1d3b adds r3, r7, #4 + 8000766: 4619 mov r1, r3 + 8000768: 481c ldr r0, [pc, #112] ; (80007dc ) + 800076a: f002 fa77 bl 8002c5c + + /*Configure GPIO pins : PA0 PA1 PA4 PA5 + PA6 PA7 PA8 PA9 + PA10 PA11 PA12 PA15 */ + GPIO_InitStruct.Pin = GPIO_PIN_0|GPIO_PIN_1|GPIO_PIN_4|GPIO_PIN_5 + 800076e: f649 73f3 movw r3, #40947 ; 0x9ff3 + 8000772: 607b str r3, [r7, #4] + |GPIO_PIN_6|GPIO_PIN_7|GPIO_PIN_8|GPIO_PIN_9 + |GPIO_PIN_10|GPIO_PIN_11|GPIO_PIN_12|GPIO_PIN_15; + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 8000774: 2303 movs r3, #3 + 8000776: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000778: 2300 movs r3, #0 + 800077a: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800077c: 1d3b adds r3, r7, #4 + 800077e: 4619 mov r1, r3 + 8000780: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8000784: f002 fa6a bl 8002c5c + + /*Configure GPIO pin : PH3 */ + GPIO_InitStruct.Pin = GPIO_PIN_3; + 8000788: 2308 movs r3, #8 + 800078a: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 800078c: 2303 movs r3, #3 + 800078e: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8000790: 2300 movs r3, #0 + 8000792: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + 8000794: 1d3b adds r3, r7, #4 + 8000796: 4619 mov r1, r3 + 8000798: 4811 ldr r0, [pc, #68] ; (80007e0 ) + 800079a: f002 fa5f bl 8002c5c + + /*Configure GPIO pin : PtPin */ + GPIO_InitStruct.Pin = STATUS_Pin; + 800079e: f44f 5380 mov.w r3, #4096 ; 0x1000 + 80007a2: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP; + 80007a4: 2301 movs r3, #1 + 80007a6: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007a8: 2300 movs r3, #0 + 80007aa: 60fb str r3, [r7, #12] + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 80007ac: 2300 movs r3, #0 + 80007ae: 613b str r3, [r7, #16] + HAL_GPIO_Init(STATUS_GPIO_Port, &GPIO_InitStruct); + 80007b0: 1d3b adds r3, r7, #4 + 80007b2: 4619 mov r1, r3 + 80007b4: 4809 ldr r0, [pc, #36] ; (80007dc ) + 80007b6: f002 fa51 bl 8002c5c + + /*Configure GPIO pin : PC13 */ + GPIO_InitStruct.Pin = GPIO_PIN_13; + 80007ba: f44f 5300 mov.w r3, #8192 ; 0x2000 + 80007be: 607b str r3, [r7, #4] + GPIO_InitStruct.Mode = GPIO_MODE_ANALOG; + 80007c0: 2303 movs r3, #3 + 80007c2: 60bb str r3, [r7, #8] + GPIO_InitStruct.Pull = GPIO_NOPULL; + 80007c4: 2300 movs r3, #0 + 80007c6: 60fb str r3, [r7, #12] + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + 80007c8: 1d3b adds r3, r7, #4 + 80007ca: 4619 mov r1, r3 + 80007cc: 4805 ldr r0, [pc, #20] ; (80007e4 ) + 80007ce: f002 fa45 bl 8002c5c + +} + 80007d2: bf00 nop + 80007d4: 3718 adds r7, #24 + 80007d6: 46bd mov sp, r7 + 80007d8: bd80 pop {r7, pc} + 80007da: bf00 nop + 80007dc: 48000400 .word 0x48000400 + 80007e0: 48001c00 .word 0x48001c00 + 80007e4: 48000800 .word 0x48000800 + +080007e8 : + * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + 80007e8: b480 push {r7} + 80007ea: b083 sub sp, #12 + 80007ec: af00 add r7, sp, #0 + 80007ee: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive); + 80007f0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80007f4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80007f8: f023 0218 bic.w r2, r3, #24 + 80007fc: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8000800: 687b ldr r3, [r7, #4] + 8000802: 4313 orrs r3, r2 + 8000804: f8c1 3090 str.w r3, [r1, #144] ; 0x90 +} + 8000808: bf00 nop + 800080a: 370c adds r7, #12 + 800080c: 46bd mov sp, r7 + 800080e: bc80 pop {r7} + 8000810: 4770 bx lr + ... + +08000814
: +/** + * @brief The application entry point. + * @retval int + */ +int main(void) +{ + 8000814: b580 push {r7, lr} + 8000816: af00 add r7, sp, #0 + /* USER CODE END 1 */ + + /* MCU Configuration--------------------------------------------------------*/ + + /* Reset of all peripherals, Initializes the Flash interface and the Systick. */ + HAL_Init(); + 8000818: f001 fa4a bl 8001cb0 + /* USER CODE BEGIN Init */ + + /* USER CODE END Init */ + + /* Configure the system clock */ + SystemClock_Config(); + 800081c: f000 f818 bl 8000850 + /* USER CODE BEGIN SysInit */ + + /* USER CODE END SysInit */ + + /* Initialize all configured peripherals */ + MX_GPIO_Init(); + 8000820: f7ff ff70 bl 8000704 + MX_DMA_Init(); + 8000824: f7ff ff44 bl 80006b0 + MX_LPUART1_UART_Init(); + 8000828: f000 fe20 bl 800146c + MX_ADC_Init(); + 800082c: f7ff feae bl 800058c + MX_SubGHz_Phy_Init(); + 8000830: f00a feba bl 800b5a8 + + /* Infinite loop */ + /* USER CODE BEGIN WHILE */ + while (1) + { + HAL_GPIO_TogglePin(STATUS_GPIO_Port, STATUS_Pin); + 8000834: f44f 5180 mov.w r1, #4096 ; 0x1000 + 8000838: 4804 ldr r0, [pc, #16] ; (800084c ) + 800083a: f002 fc54 bl 80030e6 + HAL_Delay(500); + 800083e: f44f 70fa mov.w r0, #500 ; 0x1f4 + 8000842: f000 fa7f bl 8000d44 + /* USER CODE END WHILE */ + MX_SubGHz_Phy_Process(); + 8000846: f00a ff07 bl 800b658 + HAL_GPIO_TogglePin(STATUS_GPIO_Port, STATUS_Pin); + 800084a: e7f3 b.n 8000834 + 800084c: 48000400 .word 0x48000400 + +08000850 : +/** + * @brief System Clock Configuration + * @retval None + */ +void SystemClock_Config(void) +{ + 8000850: b580 push {r7, lr} + 8000852: b09a sub sp, #104 ; 0x68 + 8000854: af00 add r7, sp, #0 + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + 8000856: f107 0320 add.w r3, r7, #32 + 800085a: 2248 movs r2, #72 ; 0x48 + 800085c: 2100 movs r1, #0 + 800085e: 4618 mov r0, r3 + 8000860: f00c fca3 bl 800d1aa + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + 8000864: f107 0308 add.w r3, r7, #8 + 8000868: 2200 movs r2, #0 + 800086a: 601a str r2, [r3, #0] + 800086c: 605a str r2, [r3, #4] + 800086e: 609a str r2, [r3, #8] + 8000870: 60da str r2, [r3, #12] + 8000872: 611a str r2, [r3, #16] + 8000874: 615a str r2, [r3, #20] + + /** Configure LSE Drive Capability + */ + HAL_PWR_EnableBkUpAccess(); + 8000876: f002 fc4f bl 8003118 + __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW); + 800087a: 2000 movs r0, #0 + 800087c: f7ff ffb4 bl 80007e8 + + /** Configure the main internal regulator output voltage + */ + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); + 8000880: 4b1f ldr r3, [pc, #124] ; (8000900 ) + 8000882: 681b ldr r3, [r3, #0] + 8000884: f423 63c0 bic.w r3, r3, #1536 ; 0x600 + 8000888: 4a1d ldr r2, [pc, #116] ; (8000900 ) + 800088a: f443 7300 orr.w r3, r3, #512 ; 0x200 + 800088e: 6013 str r3, [r2, #0] + 8000890: 4b1b ldr r3, [pc, #108] ; (8000900 ) + 8000892: 681b ldr r3, [r3, #0] + 8000894: f403 63c0 and.w r3, r3, #1536 ; 0x600 + 8000898: 607b str r3, [r7, #4] + 800089a: 687b ldr r3, [r7, #4] + + /** Initializes the CPU, AHB and APB buses clocks + */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI; + 800089c: 2324 movs r3, #36 ; 0x24 + 800089e: 623b str r3, [r7, #32] + RCC_OscInitStruct.LSEState = RCC_LSE_ON; + 80008a0: 2381 movs r3, #129 ; 0x81 + 80008a2: 62fb str r3, [r7, #44] ; 0x2c + RCC_OscInitStruct.MSIState = RCC_MSI_ON; + 80008a4: 2301 movs r3, #1 + 80008a6: 643b str r3, [r7, #64] ; 0x40 + RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT; + 80008a8: 2300 movs r3, #0 + 80008aa: 647b str r3, [r7, #68] ; 0x44 + RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_10; + 80008ac: 23a0 movs r3, #160 ; 0xa0 + 80008ae: 64bb str r3, [r7, #72] ; 0x48 + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; + 80008b0: 2300 movs r3, #0 + 80008b2: 64fb str r3, [r7, #76] ; 0x4c + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + 80008b4: f107 0320 add.w r3, r7, #32 + 80008b8: 4618 mov r0, r3 + 80008ba: f002 ffe3 bl 8003884 + 80008be: 4603 mov r3, r0 + 80008c0: 2b00 cmp r3, #0 + 80008c2: d001 beq.n 80008c8 + { + Error_Handler(); + 80008c4: f000 f81e bl 8000904 + } + + /** Configure the SYSCLKSource, HCLK, PCLK1 and PCLK2 clocks dividers + */ + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK3|RCC_CLOCKTYPE_HCLK + 80008c8: 234f movs r3, #79 ; 0x4f + 80008ca: 60bb str r3, [r7, #8] + |RCC_CLOCKTYPE_SYSCLK|RCC_CLOCKTYPE_PCLK1 + |RCC_CLOCKTYPE_PCLK2; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_MSI; + 80008cc: 2300 movs r3, #0 + 80008ce: 60fb str r3, [r7, #12] + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + 80008d0: 2300 movs r3, #0 + 80008d2: 613b str r3, [r7, #16] + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + 80008d4: 2300 movs r3, #0 + 80008d6: 617b str r3, [r7, #20] + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + 80008d8: 2300 movs r3, #0 + 80008da: 61bb str r3, [r7, #24] + RCC_ClkInitStruct.AHBCLK3Divider = RCC_SYSCLK_DIV1; + 80008dc: 2300 movs r3, #0 + 80008de: 61fb str r3, [r7, #28] + + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) + 80008e0: f107 0308 add.w r3, r7, #8 + 80008e4: 2102 movs r1, #2 + 80008e6: 4618 mov r0, r3 + 80008e8: f003 fb4e bl 8003f88 + 80008ec: 4603 mov r3, r0 + 80008ee: 2b00 cmp r3, #0 + 80008f0: d001 beq.n 80008f6 + { + Error_Handler(); + 80008f2: f000 f807 bl 8000904 + } +} + 80008f6: bf00 nop + 80008f8: 3768 adds r7, #104 ; 0x68 + 80008fa: 46bd mov sp, r7 + 80008fc: bd80 pop {r7, pc} + 80008fe: bf00 nop + 8000900: 58000400 .word 0x58000400 + +08000904 : +/** + * @brief This function is executed in case of error occurrence. + * @retval None + */ +void Error_Handler(void) +{ + 8000904: b480 push {r7} + 8000906: af00 add r7, sp, #0 + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); + 8000908: b672 cpsid i +} + 800090a: bf00 nop + /* USER CODE BEGIN Error_Handler_Debug */ + /* User can add his own implementation to report the HAL error return state */ + __disable_irq(); + while (1) + 800090c: e7fe b.n 800090c + +0800090e : + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + 800090e: b480 push {r7} + 8000910: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); + 8000912: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000916: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800091a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800091e: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 8000922: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 8000926: bf00 nop + 8000928: 46bd mov sp, r7 + 800092a: bc80 pop {r7} + 800092c: 4770 bx lr + +0800092e : +{ + 800092e: b480 push {r7} + 8000930: b085 sub sp, #20 + 8000932: af00 add r7, sp, #0 + 8000934: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB1ENR1, Periphs); + 8000936: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800093a: 6d9a ldr r2, [r3, #88] ; 0x58 + 800093c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8000940: 687b ldr r3, [r7, #4] + 8000942: 4313 orrs r3, r2 + 8000944: 658b str r3, [r1, #88] ; 0x58 + tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); + 8000946: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800094a: 6d9a ldr r2, [r3, #88] ; 0x58 + 800094c: 687b ldr r3, [r7, #4] + 800094e: 4013 ands r3, r2 + 8000950: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000952: 68fb ldr r3, [r7, #12] +} + 8000954: bf00 nop + 8000956: 3714 adds r7, #20 + 8000958: 46bd mov sp, r7 + 800095a: bc80 pop {r7} + 800095c: 4770 bx lr + ... + +08000960 : + +RTC_HandleTypeDef hrtc; + +/* RTC init function */ +void MX_RTC_Init(void) +{ + 8000960: b580 push {r7, lr} + 8000962: af00 add r7, sp, #0 + + /* USER CODE END RTC_Init 1 */ + + /** Initialize RTC Only + */ + hrtc.Instance = RTC; + 8000964: 4b1b ldr r3, [pc, #108] ; (80009d4 ) + 8000966: 4a1c ldr r2, [pc, #112] ; (80009d8 ) + 8000968: 601a str r2, [r3, #0] + hrtc.Init.AsynchPrediv = RTC_PREDIV_A; + 800096a: 4b1a ldr r3, [pc, #104] ; (80009d4 ) + 800096c: 221f movs r2, #31 + 800096e: 609a str r2, [r3, #8] + hrtc.Init.OutPut = RTC_OUTPUT_DISABLE; + 8000970: 4b18 ldr r3, [pc, #96] ; (80009d4 ) + 8000972: 2200 movs r2, #0 + 8000974: 611a str r2, [r3, #16] + hrtc.Init.OutPutRemap = RTC_OUTPUT_REMAP_NONE; + 8000976: 4b17 ldr r3, [pc, #92] ; (80009d4 ) + 8000978: 2200 movs r2, #0 + 800097a: 615a str r2, [r3, #20] + hrtc.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH; + 800097c: 4b15 ldr r3, [pc, #84] ; (80009d4 ) + 800097e: 2200 movs r2, #0 + 8000980: 619a str r2, [r3, #24] + hrtc.Init.OutPutType = RTC_OUTPUT_TYPE_OPENDRAIN; + 8000982: 4b14 ldr r3, [pc, #80] ; (80009d4 ) + 8000984: f04f 4280 mov.w r2, #1073741824 ; 0x40000000 + 8000988: 61da str r2, [r3, #28] + hrtc.Init.OutPutPullUp = RTC_OUTPUT_PULLUP_NONE; + 800098a: 4b12 ldr r3, [pc, #72] ; (80009d4 ) + 800098c: 2200 movs r2, #0 + 800098e: 621a str r2, [r3, #32] + hrtc.Init.BinMode = RTC_BINARY_ONLY; + 8000990: 4b10 ldr r3, [pc, #64] ; (80009d4 ) + 8000992: f44f 7280 mov.w r2, #256 ; 0x100 + 8000996: 625a str r2, [r3, #36] ; 0x24 + if (HAL_RTC_Init(&hrtc) != HAL_OK) + 8000998: 480e ldr r0, [pc, #56] ; (80009d4 ) + 800099a: f003 ffb1 bl 8004900 + 800099e: 4603 mov r3, r0 + 80009a0: 2b00 cmp r3, #0 + 80009a2: d001 beq.n 80009a8 + { + Error_Handler(); + 80009a4: f7ff ffae bl 8000904 + + /* USER CODE END Check_RTC_BKUP */ + + /** Initialize RTC and set the Time and Date + */ + if (HAL_RTCEx_SetSSRU_IT(&hrtc) != HAL_OK) + 80009a8: 480a ldr r0, [pc, #40] ; (80009d4 ) + 80009aa: f004 fb27 bl 8004ffc + 80009ae: 4603 mov r3, r0 + 80009b0: 2b00 cmp r3, #0 + 80009b2: d001 beq.n 80009b8 + { + Error_Handler(); + 80009b4: f7ff ffa6 bl 8000904 + } + + /** Enable the WakeUp + */ + if (HAL_RTCEx_SetWakeUpTimer_IT(&hrtc, 10, RTC_WAKEUPCLOCK_CK_SPRE_16BITS, 0) != HAL_OK) + 80009b8: 2300 movs r3, #0 + 80009ba: 2204 movs r2, #4 + 80009bc: 210a movs r1, #10 + 80009be: 4805 ldr r0, [pc, #20] ; (80009d4 ) + 80009c0: f004 fa40 bl 8004e44 + 80009c4: 4603 mov r3, r0 + 80009c6: 2b00 cmp r3, #0 + 80009c8: d001 beq.n 80009ce + { + Error_Handler(); + 80009ca: f7ff ff9b bl 8000904 + } + /* USER CODE BEGIN RTC_Init 2 */ + + /* USER CODE END RTC_Init 2 */ + +} + 80009ce: bf00 nop + 80009d0: bd80 pop {r7, pc} + 80009d2: bf00 nop + 80009d4: 20000110 .word 0x20000110 + 80009d8: 40002800 .word 0x40002800 + +080009dc : + +void HAL_RTC_MspInit(RTC_HandleTypeDef* rtcHandle) +{ + 80009dc: b580 push {r7, lr} + 80009de: b090 sub sp, #64 ; 0x40 + 80009e0: af00 add r7, sp, #0 + 80009e2: 6078 str r0, [r7, #4] + + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 80009e4: f107 0308 add.w r3, r7, #8 + 80009e8: 2238 movs r2, #56 ; 0x38 + 80009ea: 2100 movs r1, #0 + 80009ec: 4618 mov r0, r3 + 80009ee: f00c fbdc bl 800d1aa + if(rtcHandle->Instance==RTC) + 80009f2: 687b ldr r3, [r7, #4] + 80009f4: 681b ldr r3, [r3, #0] + 80009f6: 4a16 ldr r2, [pc, #88] ; (8000a50 ) + 80009f8: 4293 cmp r3, r2 + 80009fa: d125 bne.n 8000a48 + + /* USER CODE END RTC_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_RTC; + 80009fc: f44f 3380 mov.w r3, #65536 ; 0x10000 + 8000a00: 60bb str r3, [r7, #8] + PeriphClkInitStruct.RTCClockSelection = RCC_RTCCLKSOURCE_LSE; + 8000a02: f44f 7380 mov.w r3, #256 ; 0x100 + 8000a06: 63fb str r3, [r7, #60] ; 0x3c + + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 8000a08: f107 0308 add.w r3, r7, #8 + 8000a0c: 4618 mov r0, r3 + 8000a0e: f003 fe5d bl 80046cc + 8000a12: 4603 mov r3, r0 + 8000a14: 2b00 cmp r3, #0 + 8000a16: d001 beq.n 8000a1c + { + Error_Handler(); + 8000a18: f7ff ff74 bl 8000904 + } + + /* RTC clock enable */ + __HAL_RCC_RTC_ENABLE(); + 8000a1c: f7ff ff77 bl 800090e + __HAL_RCC_RTCAPB_CLK_ENABLE(); + 8000a20: f44f 6080 mov.w r0, #1024 ; 0x400 + 8000a24: f7ff ff83 bl 800092e + + /* RTC interrupt Init */ + HAL_NVIC_SetPriority(TAMP_STAMP_LSECSS_SSRU_IRQn, 0, 0); + 8000a28: 2200 movs r2, #0 + 8000a2a: 2100 movs r1, #0 + 8000a2c: 2002 movs r0, #2 + 8000a2e: f001 fce8 bl 8002402 + HAL_NVIC_EnableIRQ(TAMP_STAMP_LSECSS_SSRU_IRQn); + 8000a32: 2002 movs r0, #2 + 8000a34: f001 fcff bl 8002436 + HAL_NVIC_SetPriority(RTC_WKUP_IRQn, 0, 0); + 8000a38: 2200 movs r2, #0 + 8000a3a: 2100 movs r1, #0 + 8000a3c: 2003 movs r0, #3 + 8000a3e: f001 fce0 bl 8002402 + HAL_NVIC_EnableIRQ(RTC_WKUP_IRQn); + 8000a42: 2003 movs r0, #3 + 8000a44: f001 fcf7 bl 8002436 + /* USER CODE BEGIN RTC_MspInit 1 */ + + /* USER CODE END RTC_MspInit 1 */ + } +} + 8000a48: bf00 nop + 8000a4a: 3740 adds r7, #64 ; 0x40 + 8000a4c: 46bd mov sp, r7 + 8000a4e: bd80 pop {r7, pc} + 8000a50: 40002800 .word 0x40002800 + +08000a54 : + * @brief Clear standby and stop flags for CPU1 + * @rmtoll EXTSCR C1CSSF LL_PWR_ClearFlag_C1STOP_C1STB + * @retval None + */ +__STATIC_INLINE void LL_PWR_ClearFlag_C1STOP_C1STB(void) +{ + 8000a54: b480 push {r7} + 8000a56: af00 add r7, sp, #0 + WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C1CSSF); + 8000a58: 4b03 ldr r3, [pc, #12] ; (8000a68 ) + 8000a5a: 2201 movs r2, #1 + 8000a5c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 +} + 8000a60: bf00 nop + 8000a62: 46bd mov sp, r7 + 8000a64: bc80 pop {r7} + 8000a66: 4770 bx lr + 8000a68: 58000400 .word 0x58000400 + +08000a6c : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +void PWR_EnterOffMode(void) +{ + 8000a6c: b480 push {r7} + 8000a6e: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterOffMode_1 */ + + /* USER CODE END EnterOffMode_1 */ +} + 8000a70: bf00 nop + 8000a72: 46bd mov sp, r7 + 8000a74: bc80 pop {r7} + 8000a76: 4770 bx lr + +08000a78 : + +void PWR_ExitOffMode(void) +{ + 8000a78: b480 push {r7} + 8000a7a: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitOffMode_1 */ + + /* USER CODE END ExitOffMode_1 */ +} + 8000a7c: bf00 nop + 8000a7e: 46bd mov sp, r7 + 8000a80: bc80 pop {r7} + 8000a82: 4770 bx lr + +08000a84 : + +void PWR_EnterStopMode(void) +{ + 8000a84: b580 push {r7, lr} + 8000a86: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterStopMode_1 */ + + /* USER CODE END EnterStopMode_1 */ + HAL_SuspendTick(); + 8000a88: f001 f97e bl 8001d88 + /* Clear Status Flag before entering STOP/STANDBY Mode */ + LL_PWR_ClearFlag_C1STOP_C1STB(); + 8000a8c: f7ff ffe2 bl 8000a54 + + /* USER CODE BEGIN EnterStopMode_2 */ + + /* USER CODE END EnterStopMode_2 */ + HAL_PWREx_EnterSTOP2Mode(PWR_STOPENTRY_WFI); + 8000a90: 2001 movs r0, #1 + 8000a92: f002 fc3d bl 8003310 + /* USER CODE BEGIN EnterStopMode_3 */ + + /* USER CODE END EnterStopMode_3 */ +} + 8000a96: bf00 nop + 8000a98: bd80 pop {r7, pc} + +08000a9a : + +void PWR_ExitStopMode(void) +{ + 8000a9a: b580 push {r7, lr} + 8000a9c: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitStopMode_1 */ + + /* USER CODE END ExitStopMode_1 */ + /* Resume sysTick : work around for debugger problem in dual core */ + HAL_ResumeTick(); + 8000a9e: f001 f981 bl 8001da4 + ADC interface + DAC interface USARTx, TIMx, i2Cx, SPIx + SRAM ctrls, DMAx, DMAMux, AES, RNG, HSEM */ + + /* Resume not retained USARTx and DMA */ + vcom_Resume(); + 8000aa2: f000 ff81 bl 80019a8 + /* USER CODE BEGIN ExitStopMode_2 */ + + /* USER CODE END ExitStopMode_2 */ +} + 8000aa6: bf00 nop + 8000aa8: bd80 pop {r7, pc} + +08000aaa : + +void PWR_EnterSleepMode(void) +{ + 8000aaa: b580 push {r7, lr} + 8000aac: af00 add r7, sp, #0 + /* USER CODE BEGIN EnterSleepMode_1 */ + + /* USER CODE END EnterSleepMode_1 */ + /* Suspend sysTick */ + HAL_SuspendTick(); + 8000aae: f001 f96b bl 8001d88 + /* USER CODE BEGIN EnterSleepMode_2 */ + + /* USER CODE END EnterSleepMode_2 */ + HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI); + 8000ab2: 2101 movs r1, #1 + 8000ab4: 2000 movs r0, #0 + 8000ab6: f002 fb3d bl 8003134 + /* USER CODE BEGIN EnterSleepMode_3 */ + + /* USER CODE END EnterSleepMode_3 */ +} + 8000aba: bf00 nop + 8000abc: bd80 pop {r7, pc} + +08000abe : + +void PWR_ExitSleepMode(void) +{ + 8000abe: b580 push {r7, lr} + 8000ac0: af00 add r7, sp, #0 + /* USER CODE BEGIN ExitSleepMode_1 */ + + /* USER CODE END ExitSleepMode_1 */ + /* Resume sysTick */ + HAL_ResumeTick(); + 8000ac2: f001 f96f bl 8001da4 + + /* USER CODE BEGIN ExitSleepMode_2 */ + + /* USER CODE END ExitSleepMode_2 */ +} + 8000ac6: bf00 nop + 8000ac8: bd80 pop {r7, pc} + +08000aca : +/* USER CODE END 0 */ +/** + * Initializes the Global MSP. + */ +void HAL_MspInit(void) +{ + 8000aca: b480 push {r7} + 8000acc: af00 add r7, sp, #0 + /* System interrupt init*/ + + /* USER CODE BEGIN MspInit 1 */ + + /* USER CODE END MspInit 1 */ +} + 8000ace: bf00 nop + 8000ad0: 46bd mov sp, r7 + 8000ad2: bc80 pop {r7} + 8000ad4: 4770 bx lr + +08000ad6 : +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ + 8000ad6: b480 push {r7} + 8000ad8: af00 add r7, sp, #0 + /* USER CODE BEGIN NonMaskableInt_IRQn 0 */ + + /* USER CODE END NonMaskableInt_IRQn 0 */ + /* USER CODE BEGIN NonMaskableInt_IRQn 1 */ + while (1) + 8000ada: e7fe b.n 8000ada + +08000adc : + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + 8000adc: b480 push {r7} + 8000ade: af00 add r7, sp, #0 + /* USER CODE BEGIN HardFault_IRQn 0 */ + + /* USER CODE END HardFault_IRQn 0 */ + while (1) + 8000ae0: e7fe b.n 8000ae0 + +08000ae2 : + +/** + * @brief This function handles Memory management fault. + */ +void MemManage_Handler(void) +{ + 8000ae2: b480 push {r7} + 8000ae4: af00 add r7, sp, #0 + /* USER CODE BEGIN MemoryManagement_IRQn 0 */ + + /* USER CODE END MemoryManagement_IRQn 0 */ + while (1) + 8000ae6: e7fe b.n 8000ae6 + +08000ae8 : + +/** + * @brief This function handles Prefetch fault, memory access fault. + */ +void BusFault_Handler(void) +{ + 8000ae8: b480 push {r7} + 8000aea: af00 add r7, sp, #0 + /* USER CODE BEGIN BusFault_IRQn 0 */ + + /* USER CODE END BusFault_IRQn 0 */ + while (1) + 8000aec: e7fe b.n 8000aec + +08000aee : + +/** + * @brief This function handles Undefined instruction or illegal state. + */ +void UsageFault_Handler(void) +{ + 8000aee: b480 push {r7} + 8000af0: af00 add r7, sp, #0 + /* USER CODE BEGIN UsageFault_IRQn 0 */ + + /* USER CODE END UsageFault_IRQn 0 */ + while (1) + 8000af2: e7fe b.n 8000af2 + +08000af4 : + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ + 8000af4: b480 push {r7} + 8000af6: af00 add r7, sp, #0 + + /* USER CODE END SVCall_IRQn 0 */ + /* USER CODE BEGIN SVCall_IRQn 1 */ + + /* USER CODE END SVCall_IRQn 1 */ +} + 8000af8: bf00 nop + 8000afa: 46bd mov sp, r7 + 8000afc: bc80 pop {r7} + 8000afe: 4770 bx lr + +08000b00 : + +/** + * @brief This function handles Debug monitor. + */ +void DebugMon_Handler(void) +{ + 8000b00: b480 push {r7} + 8000b02: af00 add r7, sp, #0 + + /* USER CODE END DebugMonitor_IRQn 0 */ + /* USER CODE BEGIN DebugMonitor_IRQn 1 */ + + /* USER CODE END DebugMonitor_IRQn 1 */ +} + 8000b04: bf00 nop + 8000b06: 46bd mov sp, r7 + 8000b08: bc80 pop {r7} + 8000b0a: 4770 bx lr + +08000b0c : + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ + 8000b0c: b480 push {r7} + 8000b0e: af00 add r7, sp, #0 + + /* USER CODE END PendSV_IRQn 0 */ + /* USER CODE BEGIN PendSV_IRQn 1 */ + + /* USER CODE END PendSV_IRQn 1 */ +} + 8000b10: bf00 nop + 8000b12: 46bd mov sp, r7 + 8000b14: bc80 pop {r7} + 8000b16: 4770 bx lr + +08000b18 : + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ + 8000b18: b580 push {r7, lr} + 8000b1a: af00 add r7, sp, #0 + /* USER CODE BEGIN SysTick_IRQn 0 */ + + /* USER CODE END SysTick_IRQn 0 */ + HAL_IncTick(); + 8000b1c: f001 f922 bl 8001d64 + /* USER CODE BEGIN SysTick_IRQn 1 */ + + /* USER CODE END SysTick_IRQn 1 */ +} + 8000b20: bf00 nop + 8000b22: bd80 pop {r7, pc} + +08000b24 : + +/** + * @brief This function handles RTC Tamper, RTC TimeStamp, LSECSS and RTC SSRU Interrupts. + */ +void TAMP_STAMP_LSECSS_SSRU_IRQHandler(void) +{ + 8000b24: b580 push {r7, lr} + 8000b26: af00 add r7, sp, #0 + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 0 */ + HAL_RTCEx_SSRUIRQHandler(&hrtc); + 8000b28: 4802 ldr r0, [pc, #8] ; (8000b34 ) + 8000b2a: f004 faa3 bl 8005074 + /* USER CODE BEGIN TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ + + /* USER CODE END TAMP_STAMP_LSECSS_SSRU_IRQn 1 */ +} + 8000b2e: bf00 nop + 8000b30: bd80 pop {r7, pc} + 8000b32: bf00 nop + 8000b34: 20000110 .word 0x20000110 + +08000b38 : + +/** + * @brief This function handles RTC Wakeup Interrupt. + */ +void RTC_WKUP_IRQHandler(void) +{ + 8000b38: b580 push {r7, lr} + 8000b3a: af00 add r7, sp, #0 + /* USER CODE BEGIN RTC_WKUP_IRQn 0 */ + + /* USER CODE END RTC_WKUP_IRQn 0 */ + HAL_RTCEx_WakeUpTimerIRQHandler(&hrtc); + 8000b3c: 4802 ldr r0, [pc, #8] ; (8000b48 ) + 8000b3e: f004 fa07 bl 8004f50 + /* USER CODE BEGIN RTC_WKUP_IRQn 1 */ + + /* USER CODE END RTC_WKUP_IRQn 1 */ +} + 8000b42: bf00 nop + 8000b44: bd80 pop {r7, pc} + 8000b46: bf00 nop + 8000b48: 20000110 .word 0x20000110 + +08000b4c : + +/** + * @brief This function handles DMA1 Channel 1 Interrupt. + */ +void DMA1_Channel1_IRQHandler(void) +{ + 8000b4c: b580 push {r7, lr} + 8000b4e: af00 add r7, sp, #0 + /* USER CODE BEGIN DMA1_Channel1_IRQn 0 */ + + /* USER CODE END DMA1_Channel1_IRQn 0 */ + HAL_DMA_IRQHandler(&hdma_usart1_tx); + 8000b50: 4802 ldr r0, [pc, #8] ; (8000b5c ) + 8000b52: f001 ff13 bl 800297c + /* USER CODE BEGIN DMA1_Channel1_IRQn 1 */ + + /* USER CODE END DMA1_Channel1_IRQn 1 */ +} + 8000b56: bf00 nop + 8000b58: bd80 pop {r7, pc} + 8000b5a: bf00 nop + 8000b5c: 2000028c .word 0x2000028c + +08000b60 : + +/** + * @brief This function handles USART1 Interrupt. + */ +void USART1_IRQHandler(void) +{ + 8000b60: b580 push {r7, lr} + 8000b62: af00 add r7, sp, #0 + /* USER CODE BEGIN USART1_IRQn 0 */ + + /* USER CODE END USART1_IRQn 0 */ + HAL_UART_IRQHandler(&huart1); + 8000b64: 4802 ldr r0, [pc, #8] ; (8000b70 ) + 8000b66: f005 f989 bl 8005e7c + /* USER CODE BEGIN USART1_IRQn 1 */ + + /* USER CODE END USART1_IRQn 1 */ +} + 8000b6a: bf00 nop + 8000b6c: bd80 pop {r7, pc} + 8000b6e: bf00 nop + 8000b70: 200001f8 .word 0x200001f8 + +08000b74 : + +/** + * @brief This function handles LPUART1 Interrupt. + */ +void LPUART1_IRQHandler(void) +{ + 8000b74: b580 push {r7, lr} + 8000b76: af00 add r7, sp, #0 + /* USER CODE BEGIN LPUART1_IRQn 0 */ + + /* USER CODE END LPUART1_IRQn 0 */ + HAL_UART_IRQHandler(&hlpuart1); + 8000b78: 4802 ldr r0, [pc, #8] ; (8000b84 ) + 8000b7a: f005 f97f bl 8005e7c + /* USER CODE BEGIN LPUART1_IRQn 1 */ + + /* USER CODE END LPUART1_IRQn 1 */ +} + 8000b7e: bf00 nop + 8000b80: bd80 pop {r7, pc} + 8000b82: bf00 nop + 8000b84: 20000164 .word 0x20000164 + +08000b88 : + +/** + * @brief This function handles SUBGHZ Radio Interrupt. + */ +void SUBGHZ_Radio_IRQHandler(void) +{ + 8000b88: b580 push {r7, lr} + 8000b8a: af00 add r7, sp, #0 + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 0 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 0 */ + HAL_SUBGHZ_IRQHandler(&hsubghz); + 8000b8c: 4802 ldr r0, [pc, #8] ; (8000b98 ) + 8000b8e: f004 fdd5 bl 800573c + /* USER CODE BEGIN SUBGHZ_Radio_IRQn 1 */ + + /* USER CODE END SUBGHZ_Radio_IRQn 1 */ +} + 8000b92: bf00 nop + 8000b94: bd80 pop {r7, pc} + 8000b96: bf00 nop + 8000b98: 20000148 .word 0x20000148 + +08000b9c : + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB3_GRP1_PERIPH_SUBGHZSPI + * @retval None + */ +__STATIC_INLINE void LL_APB3_GRP1_EnableClock(uint32_t Periphs) +{ + 8000b9c: b480 push {r7} + 8000b9e: b085 sub sp, #20 + 8000ba0: af00 add r7, sp, #0 + 8000ba2: 6078 str r0, [r7, #4] + __IO uint32_t tmpreg; + SET_BIT(RCC->APB3ENR, Periphs); + 8000ba4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000ba8: 6e5a ldr r2, [r3, #100] ; 0x64 + 8000baa: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8000bae: 687b ldr r3, [r7, #4] + 8000bb0: 4313 orrs r3, r2 + 8000bb2: 664b str r3, [r1, #100] ; 0x64 + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APB3ENR, Periphs); + 8000bb4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000bb8: 6e5a ldr r2, [r3, #100] ; 0x64 + 8000bba: 687b ldr r3, [r7, #4] + 8000bbc: 4013 ands r3, r2 + 8000bbe: 60fb str r3, [r7, #12] + (void)tmpreg; + 8000bc0: 68fb ldr r3, [r7, #12] +} + 8000bc2: bf00 nop + 8000bc4: 3714 adds r7, #20 + 8000bc6: 46bd mov sp, r7 + 8000bc8: bc80 pop {r7} + 8000bca: 4770 bx lr + +08000bcc : + +SUBGHZ_HandleTypeDef hsubghz; + +/* SUBGHZ init function */ +void MX_SUBGHZ_Init(void) +{ + 8000bcc: b580 push {r7, lr} + 8000bce: af00 add r7, sp, #0 + /* USER CODE END SUBGHZ_Init 0 */ + + /* USER CODE BEGIN SUBGHZ_Init 1 */ + + /* USER CODE END SUBGHZ_Init 1 */ + hsubghz.Init.BaudratePrescaler = SUBGHZSPI_BAUDRATEPRESCALER_8; + 8000bd0: 4b06 ldr r3, [pc, #24] ; (8000bec ) + 8000bd2: 2210 movs r2, #16 + 8000bd4: 601a str r2, [r3, #0] + if (HAL_SUBGHZ_Init(&hsubghz) != HAL_OK) + 8000bd6: 4805 ldr r0, [pc, #20] ; (8000bec ) + 8000bd8: f004 fb2e bl 8005238 + 8000bdc: 4603 mov r3, r0 + 8000bde: 2b00 cmp r3, #0 + 8000be0: d001 beq.n 8000be6 + { + Error_Handler(); + 8000be2: f7ff fe8f bl 8000904 + } + /* USER CODE BEGIN SUBGHZ_Init 2 */ + + /* USER CODE END SUBGHZ_Init 2 */ + +} + 8000be6: bf00 nop + 8000be8: bd80 pop {r7, pc} + 8000bea: bf00 nop + 8000bec: 20000148 .word 0x20000148 + +08000bf0 : + +void HAL_SUBGHZ_MspInit(SUBGHZ_HandleTypeDef* subghzHandle) +{ + 8000bf0: b580 push {r7, lr} + 8000bf2: b082 sub sp, #8 + 8000bf4: af00 add r7, sp, #0 + 8000bf6: 6078 str r0, [r7, #4] + + /* USER CODE BEGIN SUBGHZ_MspInit 0 */ + + /* USER CODE END SUBGHZ_MspInit 0 */ + /* SUBGHZ clock enable */ + __HAL_RCC_SUBGHZSPI_CLK_ENABLE(); + 8000bf8: 2001 movs r0, #1 + 8000bfa: f7ff ffcf bl 8000b9c + + /* SUBGHZ interrupt Init */ + HAL_NVIC_SetPriority(SUBGHZ_Radio_IRQn, 0, 0); + 8000bfe: 2200 movs r2, #0 + 8000c00: 2100 movs r1, #0 + 8000c02: 2032 movs r0, #50 ; 0x32 + 8000c04: f001 fbfd bl 8002402 + HAL_NVIC_EnableIRQ(SUBGHZ_Radio_IRQn); + 8000c08: 2032 movs r0, #50 ; 0x32 + 8000c0a: f001 fc14 bl 8002436 + /* USER CODE BEGIN SUBGHZ_MspInit 1 */ + + /* USER CODE END SUBGHZ_MspInit 1 */ +} + 8000c0e: bf00 nop + 8000c10: 3708 adds r7, #8 + 8000c12: 46bd mov sp, r7 + 8000c14: bd80 pop {r7, pc} + +08000c16 : +{ + 8000c16: b480 push {r7} + 8000c18: b083 sub sp, #12 + 8000c1a: af00 add r7, sp, #0 + 8000c1c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Clock); + 8000c1e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8000c22: 689b ldr r3, [r3, #8] + 8000c24: f423 4200 bic.w r2, r3, #32768 ; 0x8000 + 8000c28: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8000c2c: 687b ldr r3, [r7, #4] + 8000c2e: 4313 orrs r3, r2 + 8000c30: 608b str r3, [r1, #8] +} + 8000c32: bf00 nop + 8000c34: 370c adds r7, #12 + 8000c36: 46bd mov sp, r7 + 8000c38: bc80 pop {r7} + 8000c3a: 4770 bx lr + +08000c3c : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +void SystemApp_Init(void) +{ + 8000c3c: b580 push {r7, lr} + 8000c3e: af00 add r7, sp, #0 + /* USER CODE BEGIN SystemApp_Init_1 */ + + /* USER CODE END SystemApp_Init_1 */ + + /* Ensure that MSI is wake-up system clock */ + __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(RCC_STOP_WAKEUPCLOCK_MSI); + 8000c40: 2000 movs r0, #0 + 8000c42: f7ff ffe8 bl 8000c16 + + /*Initialize timer and RTC*/ + UTIL_TIMER_Init(); + 8000c46: f00b fd07 bl 800c658 + SYS_TimerInitialisedFlag = 1; + 8000c4a: 4b0c ldr r3, [pc, #48] ; (8000c7c ) + 8000c4c: 2201 movs r2, #1 + 8000c4e: 701a strb r2, [r3, #0] + /* Initializes the SW probes pins and the monitor RF pins via Alternate Function */ + DBG_Init(); + 8000c50: f000 f898 bl 8000d84 + + /*Initialize the terminal */ + UTIL_ADV_TRACE_Init(); + 8000c54: f00b ff10 bl 800ca78 + UTIL_ADV_TRACE_RegisterTimeStampFunction(TimestampNow); + 8000c58: 4809 ldr r0, [pc, #36] ; (8000c80 ) + 8000c5a: f00b ffa9 bl 800cbb0 + + /*Set verbose LEVEL*/ + UTIL_ADV_TRACE_SetVerboseLevel(VERBOSE_LEVEL); + 8000c5e: 2002 movs r0, #2 + 8000c60: f00b ffb4 bl 800cbcc + + /*Init low power manager*/ + UTIL_LPM_Init(); + 8000c64: f00a fffe bl 800bc64 + /* Disable Stand-by mode */ + UTIL_LPM_SetOffMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + 8000c68: 2101 movs r1, #1 + 8000c6a: 2001 movs r0, #1 + 8000c6c: f00b f83a bl 800bce4 + +#if defined (LOW_POWER_DISABLE) && (LOW_POWER_DISABLE == 1) + /* Disable Stop Mode */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_APPLI_Id), UTIL_LPM_DISABLE); + 8000c70: 2101 movs r1, #1 + 8000c72: 2001 movs r0, #1 + 8000c74: f00b f806 bl 800bc84 +#endif /* LOW_POWER_DISABLE */ + + /* USER CODE BEGIN SystemApp_Init_2 */ + + /* USER CODE END SystemApp_Init_2 */ +} + 8000c78: bf00 nop + 8000c7a: bd80 pop {r7, pc} + 8000c7c: 20000154 .word 0x20000154 + 8000c80: 08000c91 .word 0x08000c91 + +08000c84 : + +/** + * @brief redefines __weak function in stm32_seq.c such to enter low power + */ +void UTIL_SEQ_Idle(void) +{ + 8000c84: b580 push {r7, lr} + 8000c86: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_SEQ_Idle_1 */ + + /* USER CODE END UTIL_SEQ_Idle_1 */ + UTIL_LPM_EnterLowPower(); + 8000c88: f00b f85c bl 800bd44 + /* USER CODE BEGIN UTIL_SEQ_Idle_2 */ + + /* USER CODE END UTIL_SEQ_Idle_2 */ +} + 8000c8c: bf00 nop + 8000c8e: bd80 pop {r7, pc} + +08000c90 : +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ + +static void TimestampNow(uint8_t *buff, uint16_t *size) +{ + 8000c90: b580 push {r7, lr} + 8000c92: b086 sub sp, #24 + 8000c94: af02 add r7, sp, #8 + 8000c96: 6078 str r0, [r7, #4] + 8000c98: 6039 str r1, [r7, #0] + /* USER CODE BEGIN TimestampNow_1 */ + + /* USER CODE END TimestampNow_1 */ + SysTime_t curtime = SysTimeGet(); + 8000c9a: f107 0308 add.w r3, r7, #8 + 8000c9e: 4618 mov r0, r3 + 8000ca0: f00b f8fa bl 800be98 + tiny_snprintf_like((char *)buff, MAX_TS_SIZE, "%ds%03d:", curtime.Seconds, curtime.SubSeconds); + 8000ca4: 68bb ldr r3, [r7, #8] + 8000ca6: f9b7 200c ldrsh.w r2, [r7, #12] + 8000caa: 9200 str r2, [sp, #0] + 8000cac: 4a07 ldr r2, [pc, #28] ; (8000ccc ) + 8000cae: 2110 movs r1, #16 + 8000cb0: 6878 ldr r0, [r7, #4] + 8000cb2: f000 f81d bl 8000cf0 + *size = strlen((char *)buff); + 8000cb6: 6878 ldr r0, [r7, #4] + 8000cb8: f7ff fa62 bl 8000180 + 8000cbc: 4603 mov r3, r0 + 8000cbe: b29a uxth r2, r3 + 8000cc0: 683b ldr r3, [r7, #0] + 8000cc2: 801a strh r2, [r3, #0] + /* USER CODE BEGIN TimestampNow_2 */ + + /* USER CODE END TimestampNow_2 */ +} + 8000cc4: bf00 nop + 8000cc6: 3710 adds r7, #16 + 8000cc8: 46bd mov sp, r7 + 8000cca: bd80 pop {r7, pc} + 8000ccc: 0800dff8 .word 0x0800dff8 + +08000cd0 : + +/* Disable StopMode when traces need to be printed */ +void UTIL_ADV_TRACE_PreSendHook(void) +{ + 8000cd0: b580 push {r7, lr} + 8000cd2: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_1 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_DISABLE); + 8000cd4: 2101 movs r1, #1 + 8000cd6: 2002 movs r0, #2 + 8000cd8: f00a ffd4 bl 800bc84 + /* USER CODE BEGIN UTIL_ADV_TRACE_PreSendHook_2 */ + + /* USER CODE END UTIL_ADV_TRACE_PreSendHook_2 */ +} + 8000cdc: bf00 nop + 8000cde: bd80 pop {r7, pc} + +08000ce0 : +/* Re-enable StopMode when traces have been printed */ +void UTIL_ADV_TRACE_PostSendHook(void) +{ + 8000ce0: b580 push {r7, lr} + 8000ce2: af00 add r7, sp, #0 + /* USER CODE BEGIN UTIL_LPM_SetStopMode_1 */ + + /* USER CODE END UTIL_LPM_SetStopMode_1 */ + UTIL_LPM_SetStopMode((1 << CFG_LPM_UART_TX_Id), UTIL_LPM_ENABLE); + 8000ce4: 2100 movs r1, #0 + 8000ce6: 2002 movs r0, #2 + 8000ce8: f00a ffcc bl 800bc84 + /* USER CODE BEGIN UTIL_LPM_SetStopMode_2 */ + + /* USER CODE END UTIL_LPM_SetStopMode_2 */ +} + 8000cec: bf00 nop + 8000cee: bd80 pop {r7, pc} + +08000cf0 : + +static void tiny_snprintf_like(char *buf, uint32_t maxsize, const char *strFormat, ...) +{ + 8000cf0: b40c push {r2, r3} + 8000cf2: b580 push {r7, lr} + 8000cf4: b084 sub sp, #16 + 8000cf6: af00 add r7, sp, #0 + 8000cf8: 6078 str r0, [r7, #4] + 8000cfa: 6039 str r1, [r7, #0] + /* USER CODE BEGIN tiny_snprintf_like_1 */ + + /* USER CODE END tiny_snprintf_like_1 */ + va_list vaArgs; + va_start(vaArgs, strFormat); + 8000cfc: f107 031c add.w r3, r7, #28 + 8000d00: 60fb str r3, [r7, #12] + UTIL_ADV_TRACE_VSNPRINTF(buf, maxsize, strFormat, vaArgs); + 8000d02: 6839 ldr r1, [r7, #0] + 8000d04: 68fb ldr r3, [r7, #12] + 8000d06: 69ba ldr r2, [r7, #24] + 8000d08: 6878 ldr r0, [r7, #4] + 8000d0a: f00b fa11 bl 800c130 + va_end(vaArgs); + /* USER CODE BEGIN tiny_snprintf_like_2 */ + + /* USER CODE END tiny_snprintf_like_2 */ +} + 8000d0e: bf00 nop + 8000d10: 3710 adds r7, #16 + 8000d12: 46bd mov sp, r7 + 8000d14: e8bd 4080 ldmia.w sp!, {r7, lr} + 8000d18: b002 add sp, #8 + 8000d1a: 4770 bx lr + +08000d1c : + +/** + * @note This function overwrites the __weak one from HAL + */ +uint32_t HAL_GetTick(void) +{ + 8000d1c: b580 push {r7, lr} + 8000d1e: b082 sub sp, #8 + 8000d20: af00 add r7, sp, #0 + uint32_t ret = 0; + 8000d22: 2300 movs r3, #0 + 8000d24: 607b str r3, [r7, #4] + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_GetTick_1 */ + + /* USER CODE END HAL_GetTick_1 */ + if (SYS_TimerInitialisedFlag == 0) + 8000d26: 4b06 ldr r3, [pc, #24] ; (8000d40 ) + 8000d28: 781b ldrb r3, [r3, #0] + 8000d2a: 2b00 cmp r3, #0 + 8000d2c: d002 beq.n 8000d34 + + /* USER CODE END HAL_GetTick_EarlyCall */ + } + else + { + ret = TIMER_IF_GetTimerValue(); + 8000d2e: f000 f9b9 bl 80010a4 + 8000d32: 6078 str r0, [r7, #4] + } + /* USER CODE BEGIN HAL_GetTick_2 */ + + /* USER CODE END HAL_GetTick_2 */ + return ret; + 8000d34: 687b ldr r3, [r7, #4] +} + 8000d36: 4618 mov r0, r3 + 8000d38: 3708 adds r7, #8 + 8000d3a: 46bd mov sp, r7 + 8000d3c: bd80 pop {r7, pc} + 8000d3e: bf00 nop + 8000d40: 20000154 .word 0x20000154 + +08000d44 : + +/** + * @note This function overwrites the __weak one from HAL + */ +void HAL_Delay(__IO uint32_t Delay) +{ + 8000d44: b580 push {r7, lr} + 8000d46: b082 sub sp, #8 + 8000d48: af00 add r7, sp, #0 + 8000d4a: 6078 str r0, [r7, #4] + /* TIMER_IF can be based on other counter the SysTick e.g. RTC */ + /* USER CODE BEGIN HAL_Delay_1 */ + + /* USER CODE END HAL_Delay_1 */ + TIMER_IF_DelayMs(Delay); + 8000d4c: 687b ldr r3, [r7, #4] + 8000d4e: 4618 mov r0, r3 + 8000d50: f000 fa2f bl 80011b2 + /* USER CODE BEGIN HAL_Delay_2 */ + + /* USER CODE END HAL_Delay_2 */ +} + 8000d54: bf00 nop + 8000d56: 3708 adds r7, #8 + 8000d58: 46bd mov sp, r7 + 8000d5a: bd80 pop {r7, pc} + +08000d5c : + * @arg @ref LL_EXTI_LINE_ALL_32_63 + * (*) value not defined in all devices + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT_32_63(uint32_t ExtiLine) +{ + 8000d5c: b480 push {r7} + 8000d5e: b083 sub sp, #12 + 8000d60: af00 add r7, sp, #0 + 8000d62: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 8000d64: 4b06 ldr r3, [pc, #24] ; (8000d80 ) + 8000d66: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 + 8000d6a: 4905 ldr r1, [pc, #20] ; (8000d80 ) + 8000d6c: 687b ldr r3, [r7, #4] + 8000d6e: 4313 orrs r3, r2 + 8000d70: f8c1 3090 str.w r3, [r1, #144] ; 0x90 +} + 8000d74: bf00 nop + 8000d76: 370c adds r7, #12 + 8000d78: 46bd mov sp, r7 + 8000d7a: bc80 pop {r7} + 8000d7c: 4770 bx lr + 8000d7e: bf00 nop + 8000d80: 58000800 .word 0x58000800 + +08000d84 : + +/** + * @brief Initializes the SW probes pins and the monitor RF pins via Alternate Function + */ +void DBG_Init(void) +{ + 8000d84: b580 push {r7, lr} + 8000d86: af00 add r7, sp, #0 + HAL_DBGMCU_DisableDBGSleepMode(); + HAL_DBGMCU_DisableDBGStopMode(); + HAL_DBGMCU_DisableDBGStandbyMode(); +#elif defined (DEBUGGER_ENABLED) && ( DEBUGGER_ENABLED == 1 ) + /*Debug power up request wakeup CBDGPWRUPREQ*/ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_46); + 8000d88: f44f 4080 mov.w r0, #16384 ; 0x4000 + 8000d8c: f7ff ffe6 bl 8000d5c + /* Disabled HAL_DBGMCU_ */ + HAL_DBGMCU_EnableDBGSleepMode(); + 8000d90: f001 f816 bl 8001dc0 + HAL_DBGMCU_EnableDBGStopMode(); + 8000d94: f001 f81a bl 8001dcc + HAL_DBGMCU_EnableDBGStandbyMode(); + 8000d98: f001 f81e bl 8001dd8 +#endif /* DEBUG_RF_BUSY_ENABLED */ + + /* USER CODE BEGIN DBG_Init_3 */ + + /* USER CODE END DBG_Init_3 */ +} + 8000d9c: bf00 nop + 8000d9e: bd80 pop {r7, pc} + +08000da0 <_getpid>: +void initialise_monitor_handles() +{ +} + +int _getpid(void) +{ + 8000da0: b480 push {r7} + 8000da2: af00 add r7, sp, #0 + return 1; + 8000da4: 2301 movs r3, #1 +} + 8000da6: 4618 mov r0, r3 + 8000da8: 46bd mov sp, r7 + 8000daa: bc80 pop {r7} + 8000dac: 4770 bx lr + +08000dae <_kill>: + +int _kill(int pid, int sig) +{ + 8000dae: b580 push {r7, lr} + 8000db0: b082 sub sp, #8 + 8000db2: af00 add r7, sp, #0 + 8000db4: 6078 str r0, [r7, #4] + 8000db6: 6039 str r1, [r7, #0] + (void)pid; + (void)sig; + errno = EINVAL; + 8000db8: f00c fab8 bl 800d32c <__errno> + 8000dbc: 4603 mov r3, r0 + 8000dbe: 2216 movs r2, #22 + 8000dc0: 601a str r2, [r3, #0] + return -1; + 8000dc2: f04f 33ff mov.w r3, #4294967295 +} + 8000dc6: 4618 mov r0, r3 + 8000dc8: 3708 adds r7, #8 + 8000dca: 46bd mov sp, r7 + 8000dcc: bd80 pop {r7, pc} + +08000dce <_exit>: + +void _exit (int status) +{ + 8000dce: b580 push {r7, lr} + 8000dd0: b082 sub sp, #8 + 8000dd2: af00 add r7, sp, #0 + 8000dd4: 6078 str r0, [r7, #4] + _kill(status, -1); + 8000dd6: f04f 31ff mov.w r1, #4294967295 + 8000dda: 6878 ldr r0, [r7, #4] + 8000ddc: f7ff ffe7 bl 8000dae <_kill> + while (1) {} /* Make sure we hang here */ + 8000de0: e7fe b.n 8000de0 <_exit+0x12> + +08000de2 <_read>: +} + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + 8000de2: b580 push {r7, lr} + 8000de4: b086 sub sp, #24 + 8000de6: af00 add r7, sp, #0 + 8000de8: 60f8 str r0, [r7, #12] + 8000dea: 60b9 str r1, [r7, #8] + 8000dec: 607a str r2, [r7, #4] + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000dee: 2300 movs r3, #0 + 8000df0: 617b str r3, [r7, #20] + 8000df2: e00a b.n 8000e0a <_read+0x28> + { + *ptr++ = __io_getchar(); + 8000df4: f3af 8000 nop.w + 8000df8: 4601 mov r1, r0 + 8000dfa: 68bb ldr r3, [r7, #8] + 8000dfc: 1c5a adds r2, r3, #1 + 8000dfe: 60ba str r2, [r7, #8] + 8000e00: b2ca uxtb r2, r1 + 8000e02: 701a strb r2, [r3, #0] + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000e04: 697b ldr r3, [r7, #20] + 8000e06: 3301 adds r3, #1 + 8000e08: 617b str r3, [r7, #20] + 8000e0a: 697a ldr r2, [r7, #20] + 8000e0c: 687b ldr r3, [r7, #4] + 8000e0e: 429a cmp r2, r3 + 8000e10: dbf0 blt.n 8000df4 <_read+0x12> + } + + return len; + 8000e12: 687b ldr r3, [r7, #4] +} + 8000e14: 4618 mov r0, r3 + 8000e16: 3718 adds r7, #24 + 8000e18: 46bd mov sp, r7 + 8000e1a: bd80 pop {r7, pc} + +08000e1c <_write>: + +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + 8000e1c: b580 push {r7, lr} + 8000e1e: b086 sub sp, #24 + 8000e20: af00 add r7, sp, #0 + 8000e22: 60f8 str r0, [r7, #12] + 8000e24: 60b9 str r1, [r7, #8] + 8000e26: 607a str r2, [r7, #4] + (void)file; + int DataIdx; + + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000e28: 2300 movs r3, #0 + 8000e2a: 617b str r3, [r7, #20] + 8000e2c: e009 b.n 8000e42 <_write+0x26> + { + __io_putchar(*ptr++); + 8000e2e: 68bb ldr r3, [r7, #8] + 8000e30: 1c5a adds r2, r3, #1 + 8000e32: 60ba str r2, [r7, #8] + 8000e34: 781b ldrb r3, [r3, #0] + 8000e36: 4618 mov r0, r3 + 8000e38: f3af 8000 nop.w + for (DataIdx = 0; DataIdx < len; DataIdx++) + 8000e3c: 697b ldr r3, [r7, #20] + 8000e3e: 3301 adds r3, #1 + 8000e40: 617b str r3, [r7, #20] + 8000e42: 697a ldr r2, [r7, #20] + 8000e44: 687b ldr r3, [r7, #4] + 8000e46: 429a cmp r2, r3 + 8000e48: dbf1 blt.n 8000e2e <_write+0x12> + } + return len; + 8000e4a: 687b ldr r3, [r7, #4] +} + 8000e4c: 4618 mov r0, r3 + 8000e4e: 3718 adds r7, #24 + 8000e50: 46bd mov sp, r7 + 8000e52: bd80 pop {r7, pc} + +08000e54 <_close>: + +int _close(int file) +{ + 8000e54: b480 push {r7} + 8000e56: b083 sub sp, #12 + 8000e58: af00 add r7, sp, #0 + 8000e5a: 6078 str r0, [r7, #4] + (void)file; + return -1; + 8000e5c: f04f 33ff mov.w r3, #4294967295 +} + 8000e60: 4618 mov r0, r3 + 8000e62: 370c adds r7, #12 + 8000e64: 46bd mov sp, r7 + 8000e66: bc80 pop {r7} + 8000e68: 4770 bx lr + +08000e6a <_fstat>: + + +int _fstat(int file, struct stat *st) +{ + 8000e6a: b480 push {r7} + 8000e6c: b083 sub sp, #12 + 8000e6e: af00 add r7, sp, #0 + 8000e70: 6078 str r0, [r7, #4] + 8000e72: 6039 str r1, [r7, #0] + (void)file; + st->st_mode = S_IFCHR; + 8000e74: 683b ldr r3, [r7, #0] + 8000e76: f44f 5200 mov.w r2, #8192 ; 0x2000 + 8000e7a: 605a str r2, [r3, #4] + return 0; + 8000e7c: 2300 movs r3, #0 +} + 8000e7e: 4618 mov r0, r3 + 8000e80: 370c adds r7, #12 + 8000e82: 46bd mov sp, r7 + 8000e84: bc80 pop {r7} + 8000e86: 4770 bx lr + +08000e88 <_isatty>: + +int _isatty(int file) +{ + 8000e88: b480 push {r7} + 8000e8a: b083 sub sp, #12 + 8000e8c: af00 add r7, sp, #0 + 8000e8e: 6078 str r0, [r7, #4] + (void)file; + return 1; + 8000e90: 2301 movs r3, #1 +} + 8000e92: 4618 mov r0, r3 + 8000e94: 370c adds r7, #12 + 8000e96: 46bd mov sp, r7 + 8000e98: bc80 pop {r7} + 8000e9a: 4770 bx lr + +08000e9c <_lseek>: + +int _lseek(int file, int ptr, int dir) +{ + 8000e9c: b480 push {r7} + 8000e9e: b085 sub sp, #20 + 8000ea0: af00 add r7, sp, #0 + 8000ea2: 60f8 str r0, [r7, #12] + 8000ea4: 60b9 str r1, [r7, #8] + 8000ea6: 607a str r2, [r7, #4] + (void)file; + (void)ptr; + (void)dir; + return 0; + 8000ea8: 2300 movs r3, #0 +} + 8000eaa: 4618 mov r0, r3 + 8000eac: 3714 adds r7, #20 + 8000eae: 46bd mov sp, r7 + 8000eb0: bc80 pop {r7} + 8000eb2: 4770 bx lr + +08000eb4 <_sbrk>: + * + * @param incr Memory size + * @return Pointer to allocated memory + */ +void *_sbrk(ptrdiff_t incr) +{ + 8000eb4: b580 push {r7, lr} + 8000eb6: b086 sub sp, #24 + 8000eb8: af00 add r7, sp, #0 + 8000eba: 6078 str r0, [r7, #4] + extern uint8_t _end; /* Symbol defined in the linker script */ + extern uint8_t _estack; /* Symbol defined in the linker script */ + extern uint32_t _Min_Stack_Size; /* Symbol defined in the linker script */ + const uint32_t stack_limit = (uint32_t)&_estack - (uint32_t)&_Min_Stack_Size; + 8000ebc: 4a14 ldr r2, [pc, #80] ; (8000f10 <_sbrk+0x5c>) + 8000ebe: 4b15 ldr r3, [pc, #84] ; (8000f14 <_sbrk+0x60>) + 8000ec0: 1ad3 subs r3, r2, r3 + 8000ec2: 617b str r3, [r7, #20] + const uint8_t *max_heap = (uint8_t *)stack_limit; + 8000ec4: 697b ldr r3, [r7, #20] + 8000ec6: 613b str r3, [r7, #16] + uint8_t *prev_heap_end; + + /* Initialize heap end at first call */ + if (NULL == __sbrk_heap_end) + 8000ec8: 4b13 ldr r3, [pc, #76] ; (8000f18 <_sbrk+0x64>) + 8000eca: 681b ldr r3, [r3, #0] + 8000ecc: 2b00 cmp r3, #0 + 8000ece: d102 bne.n 8000ed6 <_sbrk+0x22> + { + __sbrk_heap_end = &_end; + 8000ed0: 4b11 ldr r3, [pc, #68] ; (8000f18 <_sbrk+0x64>) + 8000ed2: 4a12 ldr r2, [pc, #72] ; (8000f1c <_sbrk+0x68>) + 8000ed4: 601a str r2, [r3, #0] + } + + /* Protect heap from growing into the reserved MSP stack */ + if (__sbrk_heap_end + incr > max_heap) + 8000ed6: 4b10 ldr r3, [pc, #64] ; (8000f18 <_sbrk+0x64>) + 8000ed8: 681a ldr r2, [r3, #0] + 8000eda: 687b ldr r3, [r7, #4] + 8000edc: 4413 add r3, r2 + 8000ede: 693a ldr r2, [r7, #16] + 8000ee0: 429a cmp r2, r3 + 8000ee2: d207 bcs.n 8000ef4 <_sbrk+0x40> + { + errno = ENOMEM; + 8000ee4: f00c fa22 bl 800d32c <__errno> + 8000ee8: 4603 mov r3, r0 + 8000eea: 220c movs r2, #12 + 8000eec: 601a str r2, [r3, #0] + return (void *)-1; + 8000eee: f04f 33ff mov.w r3, #4294967295 + 8000ef2: e009 b.n 8000f08 <_sbrk+0x54> + } + + prev_heap_end = __sbrk_heap_end; + 8000ef4: 4b08 ldr r3, [pc, #32] ; (8000f18 <_sbrk+0x64>) + 8000ef6: 681b ldr r3, [r3, #0] + 8000ef8: 60fb str r3, [r7, #12] + __sbrk_heap_end += incr; + 8000efa: 4b07 ldr r3, [pc, #28] ; (8000f18 <_sbrk+0x64>) + 8000efc: 681a ldr r2, [r3, #0] + 8000efe: 687b ldr r3, [r7, #4] + 8000f00: 4413 add r3, r2 + 8000f02: 4a05 ldr r2, [pc, #20] ; (8000f18 <_sbrk+0x64>) + 8000f04: 6013 str r3, [r2, #0] + + return (void *)prev_heap_end; + 8000f06: 68fb ldr r3, [r7, #12] +} + 8000f08: 4618 mov r0, r3 + 8000f0a: 3718 adds r7, #24 + 8000f0c: 46bd mov sp, r7 + 8000f0e: bd80 pop {r7, pc} + 8000f10: 20010000 .word 0x20010000 + 8000f14: 00000800 .word 0x00000800 + 8000f18: 20000158 .word 0x20000158 + 8000f1c: 20000a48 .word 0x20000a48 + +08000f20 : + * @brief Setup the microcontroller system. + * @param None + * @retval None + */ +void SystemInit(void) +{ + 8000f20: b480 push {r7} + 8000f22: af00 add r7, sp, #0 + + /* FPU settings ------------------------------------------------------------*/ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << (10UL*2UL))|(3UL << (11UL*2UL))); /* set CP10 and CP11 Full Access */ +#endif +} + 8000f24: bf00 nop + 8000f26: 46bd mov sp, r7 + 8000f28: bc80 pop {r7} + 8000f2a: 4770 bx lr + +08000f2c : + * @param RTCx RTC Instance + * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF + * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +{ + 8000f2c: b480 push {r7} + 8000f2e: b083 sub sp, #12 + 8000f30: af00 add r7, sp, #0 + 8000f32: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); + 8000f34: 687b ldr r3, [r7, #4] + 8000f36: 689b ldr r3, [r3, #8] +} + 8000f38: 4618 mov r0, r3 + 8000f3a: 370c adds r7, #12 + 8000f3c: 46bd mov sp, r7 + 8000f3e: bc80 pop {r7} + 8000f40: 4770 bx lr + ... + +08000f44 : + +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +UTIL_TIMER_Status_t TIMER_IF_Init(void) +{ + 8000f44: b580 push {r7, lr} + 8000f46: b082 sub sp, #8 + 8000f48: af00 add r7, sp, #0 + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000f4a: 2300 movs r3, #0 + 8000f4c: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN TIMER_IF_Init */ + + /* USER CODE END TIMER_IF_Init */ + if (RTC_Initialized == false) + 8000f4e: 4b14 ldr r3, [pc, #80] ; (8000fa0 ) + 8000f50: 781b ldrb r3, [r3, #0] + 8000f52: f083 0301 eor.w r3, r3, #1 + 8000f56: b2db uxtb r3, r3 + 8000f58: 2b00 cmp r3, #0 + 8000f5a: d01b beq.n 8000f94 + { + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000f5c: 4b11 ldr r3, [pc, #68] ; (8000fa4 ) + 8000f5e: f04f 32ff mov.w r2, #4294967295 + 8000f62: 631a str r2, [r3, #48] ; 0x30 + /*Init RTC*/ + MX_RTC_Init(); + 8000f64: f7ff fcfc bl 8000960 + /*Stop Timer */ + TIMER_IF_StopTimer(); + 8000f68: f000 f856 bl 8001018 + /** DeActivate the Alarm A enabled by STM32CubeMX during MX_RTC_Init() */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + 8000f6c: f44f 7180 mov.w r1, #256 ; 0x100 + 8000f70: 480c ldr r0, [pc, #48] ; (8000fa4 ) + 8000f72: f003 fe53 bl 8004c1c + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8000f76: 4b0b ldr r3, [pc, #44] ; (8000fa4 ) + 8000f78: f04f 32ff mov.w r2, #4294967295 + 8000f7c: 631a str r2, [r3, #48] ; 0x30 + + /*Enable Direct Read of the calendar registers (not through Shadow) */ + HAL_RTCEx_EnableBypassShadow(&hrtc); + 8000f7e: 4809 ldr r0, [pc, #36] ; (8000fa4 ) + 8000f80: f004 f80a bl 8004f98 + /*Initialize MSB ticks*/ + TIMER_IF_BkUp_Write_MSBticks(0); + 8000f84: 2000 movs r0, #0 + 8000f86: f000 f9c9 bl 800131c + + TIMER_IF_SetTimerContext(); + 8000f8a: f000 f85f bl 800104c + + /* Register a task to associate to UTIL_TIMER_Irq() interrupt */ + UTIL_TIMER_IRQ_MAP_INIT(); + + RTC_Initialized = true; + 8000f8e: 4b04 ldr r3, [pc, #16] ; (8000fa0 ) + 8000f90: 2201 movs r2, #1 + 8000f92: 701a strb r2, [r3, #0] + } + + /* USER CODE BEGIN TIMER_IF_Init_Last */ + + /* USER CODE END TIMER_IF_Init_Last */ + return ret; + 8000f94: 79fb ldrb r3, [r7, #7] +} + 8000f96: 4618 mov r0, r3 + 8000f98: 3708 adds r7, #8 + 8000f9a: 46bd mov sp, r7 + 8000f9c: bd80 pop {r7, pc} + 8000f9e: bf00 nop + 8000fa0: 2000015c .word 0x2000015c + 8000fa4: 20000110 .word 0x20000110 + +08000fa8 : + +UTIL_TIMER_Status_t TIMER_IF_StartTimer(uint32_t timeout) +{ + 8000fa8: b580 push {r7, lr} + 8000faa: b08e sub sp, #56 ; 0x38 + 8000fac: af00 add r7, sp, #0 + 8000fae: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 8000fb0: 2300 movs r3, #0 + 8000fb2: f887 3037 strb.w r3, [r7, #55] ; 0x37 + /* USER CODE BEGIN TIMER_IF_StartTimer */ + + /* USER CODE END TIMER_IF_StartTimer */ + RTC_AlarmTypeDef sAlarm = {0}; + 8000fb6: f107 0308 add.w r3, r7, #8 + 8000fba: 222c movs r2, #44 ; 0x2c + 8000fbc: 2100 movs r1, #0 + 8000fbe: 4618 mov r0, r3 + 8000fc0: f00c f8f3 bl 800d1aa + /*Stop timer if one is already started*/ + TIMER_IF_StopTimer(); + 8000fc4: f000 f828 bl 8001018 + timeout += RtcTimerContext; + 8000fc8: 4b11 ldr r3, [pc, #68] ; (8001010 ) + 8000fca: 681b ldr r3, [r3, #0] + 8000fcc: 687a ldr r2, [r7, #4] + 8000fce: 4413 add r3, r2 + 8000fd0: 607b str r3, [r7, #4] + + TIMER_IF_DBG_PRINTF("Start timer: time=%d, alarm=%d\n\r", GetTimerTicks(), timeout); + /* starts timer*/ + sAlarm.BinaryAutoClr = RTC_ALARMSUBSECONDBIN_AUTOCLR_NO; + 8000fd2: 2300 movs r3, #0 + 8000fd4: 627b str r3, [r7, #36] ; 0x24 + sAlarm.AlarmTime.SubSeconds = UINT32_MAX - timeout; + 8000fd6: 687b ldr r3, [r7, #4] + 8000fd8: 43db mvns r3, r3 + 8000fda: 60fb str r3, [r7, #12] + sAlarm.AlarmMask = RTC_ALARMMASK_NONE; + 8000fdc: 2300 movs r3, #0 + 8000fde: 61fb str r3, [r7, #28] + sAlarm.AlarmSubSecondMask = RTC_ALARMSUBSECONDBINMASK_NONE; + 8000fe0: f04f 5300 mov.w r3, #536870912 ; 0x20000000 + 8000fe4: 623b str r3, [r7, #32] + sAlarm.Alarm = RTC_ALARM_A; + 8000fe6: f44f 7380 mov.w r3, #256 ; 0x100 + 8000fea: 633b str r3, [r7, #48] ; 0x30 + if (HAL_RTC_SetAlarm_IT(&hrtc, &sAlarm, RTC_FORMAT_BCD) != HAL_OK) + 8000fec: f107 0308 add.w r3, r7, #8 + 8000ff0: 2201 movs r2, #1 + 8000ff2: 4619 mov r1, r3 + 8000ff4: 4807 ldr r0, [pc, #28] ; (8001014 ) + 8000ff6: f003 fd05 bl 8004a04 + 8000ffa: 4603 mov r3, r0 + 8000ffc: 2b00 cmp r3, #0 + 8000ffe: d001 beq.n 8001004 + { + Error_Handler(); + 8001000: f7ff fc80 bl 8000904 + } + /* USER CODE BEGIN TIMER_IF_StartTimer_Last */ + + /* USER CODE END TIMER_IF_StartTimer_Last */ + return ret; + 8001004: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 +} + 8001008: 4618 mov r0, r3 + 800100a: 3738 adds r7, #56 ; 0x38 + 800100c: 46bd mov sp, r7 + 800100e: bd80 pop {r7, pc} + 8001010: 20000160 .word 0x20000160 + 8001014: 20000110 .word 0x20000110 + +08001018 : + +UTIL_TIMER_Status_t TIMER_IF_StopTimer(void) +{ + 8001018: b580 push {r7, lr} + 800101a: b082 sub sp, #8 + 800101c: af00 add r7, sp, #0 + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800101e: 2300 movs r3, #0 + 8001020: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN TIMER_IF_StopTimer */ + + /* USER CODE END TIMER_IF_StopTimer */ + /* Clear RTC Alarm Flag */ + __HAL_RTC_ALARM_CLEAR_FLAG(&hrtc, RTC_FLAG_ALRAF); + 8001022: 4b08 ldr r3, [pc, #32] ; (8001044 ) + 8001024: 2201 movs r2, #1 + 8001026: 65da str r2, [r3, #92] ; 0x5c + /* Disable the Alarm A interrupt */ + HAL_RTC_DeactivateAlarm(&hrtc, RTC_ALARM_A); + 8001028: f44f 7180 mov.w r1, #256 ; 0x100 + 800102c: 4806 ldr r0, [pc, #24] ; (8001048 ) + 800102e: f003 fdf5 bl 8004c1c + /*overload RTC feature enable*/ + hrtc.IsEnabled.RtcFeatures = UINT32_MAX; + 8001032: 4b05 ldr r3, [pc, #20] ; (8001048 ) + 8001034: f04f 32ff mov.w r2, #4294967295 + 8001038: 631a str r2, [r3, #48] ; 0x30 + /* USER CODE BEGIN TIMER_IF_StopTimer_Last */ + + /* USER CODE END TIMER_IF_StopTimer_Last */ + return ret; + 800103a: 79fb ldrb r3, [r7, #7] +} + 800103c: 4618 mov r0, r3 + 800103e: 3708 adds r7, #8 + 8001040: 46bd mov sp, r7 + 8001042: bd80 pop {r7, pc} + 8001044: 40002800 .word 0x40002800 + 8001048: 20000110 .word 0x20000110 + +0800104c : + +uint32_t TIMER_IF_SetTimerContext(void) +{ + 800104c: b580 push {r7, lr} + 800104e: af00 add r7, sp, #0 + /*store time context*/ + RtcTimerContext = GetTimerTicks(); + 8001050: f000 f984 bl 800135c + 8001054: 4603 mov r3, r0 + 8001056: 4a03 ldr r2, [pc, #12] ; (8001064 ) + 8001058: 6013 str r3, [r2, #0] + + /* USER CODE END TIMER_IF_SetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_SetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; + 800105a: 4b02 ldr r3, [pc, #8] ; (8001064 ) + 800105c: 681b ldr r3, [r3, #0] +} + 800105e: 4618 mov r0, r3 + 8001060: bd80 pop {r7, pc} + 8001062: bf00 nop + 8001064: 20000160 .word 0x20000160 + +08001068 : + +uint32_t TIMER_IF_GetTimerContext(void) +{ + 8001068: b480 push {r7} + 800106a: af00 add r7, sp, #0 + + /* USER CODE END TIMER_IF_GetTimerContext */ + + TIMER_IF_DBG_PRINTF("TIMER_IF_GetTimerContext=%d\n\r", RtcTimerContext); + /*return time context*/ + return RtcTimerContext; + 800106c: 4b02 ldr r3, [pc, #8] ; (8001078 ) + 800106e: 681b ldr r3, [r3, #0] +} + 8001070: 4618 mov r0, r3 + 8001072: 46bd mov sp, r7 + 8001074: bc80 pop {r7} + 8001076: 4770 bx lr + 8001078: 20000160 .word 0x20000160 + +0800107c : + +uint32_t TIMER_IF_GetTimerElapsedTime(void) +{ + 800107c: b580 push {r7, lr} + 800107e: b082 sub sp, #8 + 8001080: af00 add r7, sp, #0 + uint32_t ret = 0; + 8001082: 2300 movs r3, #0 + 8001084: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime */ + ret = ((uint32_t)(GetTimerTicks() - RtcTimerContext)); + 8001086: f000 f969 bl 800135c + 800108a: 4602 mov r2, r0 + 800108c: 4b04 ldr r3, [pc, #16] ; (80010a0 ) + 800108e: 681b ldr r3, [r3, #0] + 8001090: 1ad3 subs r3, r2, r3 + 8001092: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerElapsedTime_Last */ + + /* USER CODE END TIMER_IF_GetTimerElapsedTime_Last */ + return ret; + 8001094: 687b ldr r3, [r7, #4] +} + 8001096: 4618 mov r0, r3 + 8001098: 3708 adds r7, #8 + 800109a: 46bd mov sp, r7 + 800109c: bd80 pop {r7, pc} + 800109e: bf00 nop + 80010a0: 20000160 .word 0x20000160 + +080010a4 : + +uint32_t TIMER_IF_GetTimerValue(void) +{ + 80010a4: b580 push {r7, lr} + 80010a6: b082 sub sp, #8 + 80010a8: af00 add r7, sp, #0 + uint32_t ret = 0; + 80010aa: 2300 movs r3, #0 + 80010ac: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetTimerValue */ + + /* USER CODE END TIMER_IF_GetTimerValue */ + if (RTC_Initialized == true) + 80010ae: 4b06 ldr r3, [pc, #24] ; (80010c8 ) + 80010b0: 781b ldrb r3, [r3, #0] + 80010b2: 2b00 cmp r3, #0 + 80010b4: d002 beq.n 80010bc + { + ret = GetTimerTicks(); + 80010b6: f000 f951 bl 800135c + 80010ba: 6078 str r0, [r7, #4] + } + /* USER CODE BEGIN TIMER_IF_GetTimerValue_Last */ + + /* USER CODE END TIMER_IF_GetTimerValue_Last */ + return ret; + 80010bc: 687b ldr r3, [r7, #4] +} + 80010be: 4618 mov r0, r3 + 80010c0: 3708 adds r7, #8 + 80010c2: 46bd mov sp, r7 + 80010c4: bd80 pop {r7, pc} + 80010c6: bf00 nop + 80010c8: 2000015c .word 0x2000015c + +080010cc : + +uint32_t TIMER_IF_GetMinimumTimeout(void) +{ + 80010cc: b480 push {r7} + 80010ce: b083 sub sp, #12 + 80010d0: af00 add r7, sp, #0 + uint32_t ret = 0; + 80010d2: 2300 movs r3, #0 + 80010d4: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout */ + ret = (MIN_ALARM_DELAY); + 80010d6: 2303 movs r3, #3 + 80010d8: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_GetMinimumTimeout_Last */ + + /* USER CODE END TIMER_IF_GetMinimumTimeout_Last */ + return ret; + 80010da: 687b ldr r3, [r7, #4] +} + 80010dc: 4618 mov r0, r3 + 80010de: 370c adds r7, #12 + 80010e0: 46bd mov sp, r7 + 80010e2: bc80 pop {r7} + 80010e4: 4770 bx lr + +080010e6 : + +uint32_t TIMER_IF_Convert_ms2Tick(uint32_t timeMilliSec) +{ + 80010e6: b5b0 push {r4, r5, r7, lr} + 80010e8: b084 sub sp, #16 + 80010ea: af00 add r7, sp, #0 + 80010ec: 6078 str r0, [r7, #4] + uint32_t ret = 0; + 80010ee: 2100 movs r1, #0 + 80010f0: 60f9 str r1, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick */ + ret = ((uint32_t)((((uint64_t) timeMilliSec) << RTC_N_PREDIV_S) / 1000)); + 80010f2: 6879 ldr r1, [r7, #4] + 80010f4: 2000 movs r0, #0 + 80010f6: 460a mov r2, r1 + 80010f8: 4603 mov r3, r0 + 80010fa: 0d95 lsrs r5, r2, #22 + 80010fc: 0294 lsls r4, r2, #10 + 80010fe: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8001102: f04f 0300 mov.w r3, #0 + 8001106: 4620 mov r0, r4 + 8001108: 4629 mov r1, r5 + 800110a: f7ff f891 bl 8000230 <__aeabi_uldivmod> + 800110e: 4602 mov r2, r0 + 8001110: 460b mov r3, r1 + 8001112: 4613 mov r3, r2 + 8001114: 60fb str r3, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_ms2Tick_Last */ + + /* USER CODE END TIMER_IF_Convert_ms2Tick_Last */ + return ret; + 8001116: 68fb ldr r3, [r7, #12] +} + 8001118: 4618 mov r0, r3 + 800111a: 3710 adds r7, #16 + 800111c: 46bd mov sp, r7 + 800111e: bdb0 pop {r4, r5, r7, pc} + +08001120 : + +uint32_t TIMER_IF_Convert_Tick2ms(uint32_t tick) +{ + 8001120: e92d 0fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp} + 8001124: b085 sub sp, #20 + 8001126: af00 add r7, sp, #0 + 8001128: 6078 str r0, [r7, #4] + uint32_t ret = 0; + 800112a: 2100 movs r1, #0 + 800112c: 60f9 str r1, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms */ + ret = ((uint32_t)((((uint64_t)(tick)) * 1000) >> RTC_N_PREDIV_S)); + 800112e: 6879 ldr r1, [r7, #4] + 8001130: 2000 movs r0, #0 + 8001132: 460c mov r4, r1 + 8001134: 4605 mov r5, r0 + 8001136: 4620 mov r0, r4 + 8001138: 4629 mov r1, r5 + 800113a: f04f 0a00 mov.w sl, #0 + 800113e: f04f 0b00 mov.w fp, #0 + 8001142: ea4f 1b41 mov.w fp, r1, lsl #5 + 8001146: ea4b 6bd0 orr.w fp, fp, r0, lsr #27 + 800114a: ea4f 1a40 mov.w sl, r0, lsl #5 + 800114e: 4650 mov r0, sl + 8001150: 4659 mov r1, fp + 8001152: 1b02 subs r2, r0, r4 + 8001154: eb61 0305 sbc.w r3, r1, r5 + 8001158: f04f 0000 mov.w r0, #0 + 800115c: f04f 0100 mov.w r1, #0 + 8001160: 0099 lsls r1, r3, #2 + 8001162: ea41 7192 orr.w r1, r1, r2, lsr #30 + 8001166: 0090 lsls r0, r2, #2 + 8001168: 4602 mov r2, r0 + 800116a: 460b mov r3, r1 + 800116c: eb12 0804 adds.w r8, r2, r4 + 8001170: eb43 0905 adc.w r9, r3, r5 + 8001174: f04f 0200 mov.w r2, #0 + 8001178: f04f 0300 mov.w r3, #0 + 800117c: ea4f 03c9 mov.w r3, r9, lsl #3 + 8001180: ea43 7358 orr.w r3, r3, r8, lsr #29 + 8001184: ea4f 02c8 mov.w r2, r8, lsl #3 + 8001188: 4690 mov r8, r2 + 800118a: 4699 mov r9, r3 + 800118c: 4640 mov r0, r8 + 800118e: 4649 mov r1, r9 + 8001190: f04f 0200 mov.w r2, #0 + 8001194: f04f 0300 mov.w r3, #0 + 8001198: 0a82 lsrs r2, r0, #10 + 800119a: ea42 5281 orr.w r2, r2, r1, lsl #22 + 800119e: 0a8b lsrs r3, r1, #10 + 80011a0: 4613 mov r3, r2 + 80011a2: 60fb str r3, [r7, #12] + /* USER CODE BEGIN TIMER_IF_Convert_Tick2ms_Last */ + + /* USER CODE END TIMER_IF_Convert_Tick2ms_Last */ + return ret; + 80011a4: 68fb ldr r3, [r7, #12] +} + 80011a6: 4618 mov r0, r3 + 80011a8: 3714 adds r7, #20 + 80011aa: 46bd mov sp, r7 + 80011ac: e8bd 0fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp} + 80011b0: 4770 bx lr + +080011b2 : + +void TIMER_IF_DelayMs(uint32_t delay) +{ + 80011b2: b580 push {r7, lr} + 80011b4: b084 sub sp, #16 + 80011b6: af00 add r7, sp, #0 + 80011b8: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_DelayMs */ + + /* USER CODE END TIMER_IF_DelayMs */ + uint32_t delayTicks = TIMER_IF_Convert_ms2Tick(delay); + 80011ba: 6878 ldr r0, [r7, #4] + 80011bc: f7ff ff93 bl 80010e6 + 80011c0: 60f8 str r0, [r7, #12] + uint32_t timeout = GetTimerTicks(); + 80011c2: f000 f8cb bl 800135c + 80011c6: 60b8 str r0, [r7, #8] + + /* Wait delay ms */ + while (((GetTimerTicks() - timeout)) < delayTicks) + 80011c8: e000 b.n 80011cc + { + __NOP(); + 80011ca: bf00 nop + while (((GetTimerTicks() - timeout)) < delayTicks) + 80011cc: f000 f8c6 bl 800135c + 80011d0: 4602 mov r2, r0 + 80011d2: 68bb ldr r3, [r7, #8] + 80011d4: 1ad3 subs r3, r2, r3 + 80011d6: 68fa ldr r2, [r7, #12] + 80011d8: 429a cmp r2, r3 + 80011da: d8f6 bhi.n 80011ca + } + /* USER CODE BEGIN TIMER_IF_DelayMs_Last */ + + /* USER CODE END TIMER_IF_DelayMs_Last */ +} + 80011dc: bf00 nop + 80011de: bf00 nop + 80011e0: 3710 adds r7, #16 + 80011e2: 46bd mov sp, r7 + 80011e4: bd80 pop {r7, pc} + +080011e6 : + + /* USER CODE END HAL_RTC_AlarmAEventCallback_Last */ +} + +void HAL_RTCEx_SSRUEventCallback(RTC_HandleTypeDef *hrtc) +{ + 80011e6: b580 push {r7, lr} + 80011e8: b084 sub sp, #16 + 80011ea: af00 add r7, sp, #0 + 80011ec: 6078 str r0, [r7, #4] + + /* USER CODE END HAL_RTCEx_SSRUEventCallback */ + /*called every 48 days with 1024 ticks per seconds*/ + TIMER_IF_DBG_PRINTF(">>Handler SSRUnderflow at %d\n\r", GetTimerTicks()); + /*Increment MSBticks*/ + uint32_t MSB_ticks = TIMER_IF_BkUp_Read_MSBticks(); + 80011ee: f000 f8a5 bl 800133c + 80011f2: 60f8 str r0, [r7, #12] + TIMER_IF_BkUp_Write_MSBticks(MSB_ticks + 1); + 80011f4: 68fb ldr r3, [r7, #12] + 80011f6: 3301 adds r3, #1 + 80011f8: 4618 mov r0, r3 + 80011fa: f000 f88f bl 800131c + /* USER CODE BEGIN HAL_RTCEx_SSRUEventCallback_Last */ + + /* USER CODE END HAL_RTCEx_SSRUEventCallback_Last */ +} + 80011fe: bf00 nop + 8001200: 3710 adds r7, #16 + 8001202: 46bd mov sp, r7 + 8001204: bd80 pop {r7, pc} + +08001206 : + +uint32_t TIMER_IF_GetTime(uint16_t *mSeconds) +{ + 8001206: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 800120a: b08c sub sp, #48 ; 0x30 + 800120c: af00 add r7, sp, #0 + 800120e: 6178 str r0, [r7, #20] + uint32_t seconds = 0; + 8001210: 2300 movs r3, #0 + 8001212: 62fb str r3, [r7, #44] ; 0x2c + /* USER CODE BEGIN TIMER_IF_GetTime */ + + /* USER CODE END TIMER_IF_GetTime */ + uint64_t ticks; + uint32_t timerValueLsb = GetTimerTicks(); + 8001214: f000 f8a2 bl 800135c + 8001218: 62b8 str r0, [r7, #40] ; 0x28 + uint32_t timerValueMSB = TIMER_IF_BkUp_Read_MSBticks(); + 800121a: f000 f88f bl 800133c + 800121e: 6278 str r0, [r7, #36] ; 0x24 + + ticks = (((uint64_t) timerValueMSB) << 32) + timerValueLsb; + 8001220: 6a7b ldr r3, [r7, #36] ; 0x24 + 8001222: 2200 movs r2, #0 + 8001224: 60bb str r3, [r7, #8] + 8001226: 60fa str r2, [r7, #12] + 8001228: f04f 0200 mov.w r2, #0 + 800122c: f04f 0300 mov.w r3, #0 + 8001230: 68b9 ldr r1, [r7, #8] + 8001232: 000b movs r3, r1 + 8001234: 2200 movs r2, #0 + 8001236: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8001238: 2000 movs r0, #0 + 800123a: 460c mov r4, r1 + 800123c: 4605 mov r5, r0 + 800123e: eb12 0804 adds.w r8, r2, r4 + 8001242: eb43 0905 adc.w r9, r3, r5 + 8001246: e9c7 8906 strd r8, r9, [r7, #24] + + seconds = (uint32_t)(ticks >> RTC_N_PREDIV_S); + 800124a: e9d7 0106 ldrd r0, r1, [r7, #24] + 800124e: f04f 0200 mov.w r2, #0 + 8001252: f04f 0300 mov.w r3, #0 + 8001256: 0a82 lsrs r2, r0, #10 + 8001258: ea42 5281 orr.w r2, r2, r1, lsl #22 + 800125c: 0a8b lsrs r3, r1, #10 + 800125e: 4613 mov r3, r2 + 8001260: 62fb str r3, [r7, #44] ; 0x2c + + ticks = (uint32_t) ticks & RTC_PREDIV_S; + 8001262: 69bb ldr r3, [r7, #24] + 8001264: 2200 movs r2, #0 + 8001266: 603b str r3, [r7, #0] + 8001268: 607a str r2, [r7, #4] + 800126a: 683b ldr r3, [r7, #0] + 800126c: f3c3 0a09 ubfx sl, r3, #0, #10 + 8001270: f04f 0b00 mov.w fp, #0 + 8001274: e9c7 ab06 strd sl, fp, [r7, #24] + + *mSeconds = TIMER_IF_Convert_Tick2ms(ticks); + 8001278: 69bb ldr r3, [r7, #24] + 800127a: 4618 mov r0, r3 + 800127c: f7ff ff50 bl 8001120 + 8001280: 4603 mov r3, r0 + 8001282: b29a uxth r2, r3 + 8001284: 697b ldr r3, [r7, #20] + 8001286: 801a strh r2, [r3, #0] + + /* USER CODE BEGIN TIMER_IF_GetTime_Last */ + + /* USER CODE END TIMER_IF_GetTime_Last */ + return seconds; + 8001288: 6afb ldr r3, [r7, #44] ; 0x2c +} + 800128a: 4618 mov r0, r3 + 800128c: 3730 adds r7, #48 ; 0x30 + 800128e: 46bd mov sp, r7 + 8001290: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + +08001294 : + +void TIMER_IF_BkUp_Write_Seconds(uint32_t Seconds) +{ + 8001294: b580 push {r7, lr} + 8001296: b082 sub sp, #8 + 8001298: af00 add r7, sp, #0 + 800129a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SECONDS, Seconds); + 800129c: 687a ldr r2, [r7, #4] + 800129e: 2100 movs r1, #0 + 80012a0: 4803 ldr r0, [pc, #12] ; (80012b0 ) + 80012a2: f003 ff01 bl 80050a8 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_Seconds_Last */ +} + 80012a6: bf00 nop + 80012a8: 3708 adds r7, #8 + 80012aa: 46bd mov sp, r7 + 80012ac: bd80 pop {r7, pc} + 80012ae: bf00 nop + 80012b0: 20000110 .word 0x20000110 + +080012b4 : + +void TIMER_IF_BkUp_Write_SubSeconds(uint32_t SubSeconds) +{ + 80012b4: b580 push {r7, lr} + 80012b6: b082 sub sp, #8 + 80012b8: af00 add r7, sp, #0 + 80012ba: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_SUBSECONDS, SubSeconds); + 80012bc: 687a ldr r2, [r7, #4] + 80012be: 2101 movs r1, #1 + 80012c0: 4803 ldr r0, [pc, #12] ; (80012d0 ) + 80012c2: f003 fef1 bl 80050a8 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_SubSeconds_Last */ +} + 80012c6: bf00 nop + 80012c8: 3708 adds r7, #8 + 80012ca: 46bd mov sp, r7 + 80012cc: bd80 pop {r7, pc} + 80012ce: bf00 nop + 80012d0: 20000110 .word 0x20000110 + +080012d4 : + +uint32_t TIMER_IF_BkUp_Read_Seconds(void) +{ + 80012d4: b580 push {r7, lr} + 80012d6: b082 sub sp, #8 + 80012d8: af00 add r7, sp, #0 + uint32_t ret = 0; + 80012da: 2300 movs r3, #0 + 80012dc: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SECONDS); + 80012de: 2100 movs r1, #0 + 80012e0: 4804 ldr r0, [pc, #16] ; (80012f4 ) + 80012e2: f003 fef9 bl 80050d8 + 80012e6: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_Seconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_Seconds_Last */ + return ret; + 80012e8: 687b ldr r3, [r7, #4] +} + 80012ea: 4618 mov r0, r3 + 80012ec: 3708 adds r7, #8 + 80012ee: 46bd mov sp, r7 + 80012f0: bd80 pop {r7, pc} + 80012f2: bf00 nop + 80012f4: 20000110 .word 0x20000110 + +080012f8 : + +uint32_t TIMER_IF_BkUp_Read_SubSeconds(void) +{ + 80012f8: b580 push {r7, lr} + 80012fa: b082 sub sp, #8 + 80012fc: af00 add r7, sp, #0 + uint32_t ret = 0; + 80012fe: 2300 movs r3, #0 + 8001300: 607b str r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds */ + ret = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_SUBSECONDS); + 8001302: 2101 movs r1, #1 + 8001304: 4804 ldr r0, [pc, #16] ; (8001318 ) + 8001306: f003 fee7 bl 80050d8 + 800130a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_SubSeconds_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_SubSeconds_Last */ + return ret; + 800130c: 687b ldr r3, [r7, #4] +} + 800130e: 4618 mov r0, r3 + 8001310: 3708 adds r7, #8 + 8001312: 46bd mov sp, r7 + 8001314: bd80 pop {r7, pc} + 8001316: bf00 nop + 8001318: 20000110 .word 0x20000110 + +0800131c : + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ +static void TIMER_IF_BkUp_Write_MSBticks(uint32_t MSBticks) +{ + 800131c: b580 push {r7, lr} + 800131e: b082 sub sp, #8 + 8001320: af00 add r7, sp, #0 + 8001322: 6078 str r0, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks */ + HAL_RTCEx_BKUPWrite(&hrtc, RTC_BKP_MSBTICKS, MSBticks); + 8001324: 687a ldr r2, [r7, #4] + 8001326: 2102 movs r1, #2 + 8001328: 4803 ldr r0, [pc, #12] ; (8001338 ) + 800132a: f003 febd bl 80050a8 + /* USER CODE BEGIN TIMER_IF_BkUp_Write_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Write_MSBticks_Last */ +} + 800132e: bf00 nop + 8001330: 3708 adds r7, #8 + 8001332: 46bd mov sp, r7 + 8001334: bd80 pop {r7, pc} + 8001336: bf00 nop + 8001338: 20000110 .word 0x20000110 + +0800133c : + +static uint32_t TIMER_IF_BkUp_Read_MSBticks(void) +{ + 800133c: b580 push {r7, lr} + 800133e: b082 sub sp, #8 + 8001340: af00 add r7, sp, #0 + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks */ + uint32_t MSBticks; + MSBticks = HAL_RTCEx_BKUPRead(&hrtc, RTC_BKP_MSBTICKS); + 8001342: 2102 movs r1, #2 + 8001344: 4804 ldr r0, [pc, #16] ; (8001358 ) + 8001346: f003 fec7 bl 80050d8 + 800134a: 6078 str r0, [r7, #4] + return MSBticks; + 800134c: 687b ldr r3, [r7, #4] + /* USER CODE BEGIN TIMER_IF_BkUp_Read_MSBticks_Last */ + + /* USER CODE END TIMER_IF_BkUp_Read_MSBticks_Last */ +} + 800134e: 4618 mov r0, r3 + 8001350: 3708 adds r7, #8 + 8001352: 46bd mov sp, r7 + 8001354: bd80 pop {r7, pc} + 8001356: bf00 nop + 8001358: 20000110 .word 0x20000110 + +0800135c : + +static inline uint32_t GetTimerTicks(void) +{ + 800135c: b580 push {r7, lr} + 800135e: b082 sub sp, #8 + 8001360: af00 add r7, sp, #0 + /* USER CODE BEGIN GetTimerTicks */ + + /* USER CODE END GetTimerTicks */ + uint32_t ssr = LL_RTC_TIME_GetSubSecond(RTC); + 8001362: 480b ldr r0, [pc, #44] ; (8001390 ) + 8001364: f7ff fde2 bl 8000f2c + 8001368: 6078 str r0, [r7, #4] + /* read twice to make sure value it valid*/ + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + 800136a: e003 b.n 8001374 + { + ssr = LL_RTC_TIME_GetSubSecond(RTC); + 800136c: 4808 ldr r0, [pc, #32] ; (8001390 ) + 800136e: f7ff fddd bl 8000f2c + 8001372: 6078 str r0, [r7, #4] + while (ssr != LL_RTC_TIME_GetSubSecond(RTC)) + 8001374: 4806 ldr r0, [pc, #24] ; (8001390 ) + 8001376: f7ff fdd9 bl 8000f2c + 800137a: 4602 mov r2, r0 + 800137c: 687b ldr r3, [r7, #4] + 800137e: 4293 cmp r3, r2 + 8001380: d1f4 bne.n 800136c + } + return UINT32_MAX - ssr; + 8001382: 687b ldr r3, [r7, #4] + 8001384: 43db mvns r3, r3 + /* USER CODE BEGIN GetTimerTicks_Last */ + + /* USER CODE END GetTimerTicks_Last */ +} + 8001386: 4618 mov r0, r3 + 8001388: 3708 adds r7, #8 + 800138a: 46bd mov sp, r7 + 800138c: bd80 pop {r7, pc} + 800138e: bf00 nop + 8001390: 40002800 .word 0x40002800 + +08001394 : +{ + 8001394: b480 push {r7} + 8001396: b085 sub sp, #20 + 8001398: af00 add r7, sp, #0 + 800139a: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 800139c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013a0: 6cda ldr r2, [r3, #76] ; 0x4c + 80013a2: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80013a6: 687b ldr r3, [r7, #4] + 80013a8: 4313 orrs r3, r2 + 80013aa: 64cb str r3, [r1, #76] ; 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 80013ac: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013b0: 6cda ldr r2, [r3, #76] ; 0x4c + 80013b2: 687b ldr r3, [r7, #4] + 80013b4: 4013 ands r3, r2 + 80013b6: 60fb str r3, [r7, #12] + (void)tmpreg; + 80013b8: 68fb ldr r3, [r7, #12] +} + 80013ba: bf00 nop + 80013bc: 3714 adds r7, #20 + 80013be: 46bd mov sp, r7 + 80013c0: bc80 pop {r7} + 80013c2: 4770 bx lr + +080013c4 : +{ + 80013c4: b480 push {r7} + 80013c6: b085 sub sp, #20 + 80013c8: af00 add r7, sp, #0 + 80013ca: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB1ENR2, Periphs); + 80013cc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013d0: 6dda ldr r2, [r3, #92] ; 0x5c + 80013d2: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80013d6: 687b ldr r3, [r7, #4] + 80013d8: 4313 orrs r3, r2 + 80013da: 65cb str r3, [r1, #92] ; 0x5c + tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); + 80013dc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80013e0: 6dda ldr r2, [r3, #92] ; 0x5c + 80013e2: 687b ldr r3, [r7, #4] + 80013e4: 4013 ands r3, r2 + 80013e6: 60fb str r3, [r7, #12] + (void)tmpreg; + 80013e8: 68fb ldr r3, [r7, #12] +} + 80013ea: bf00 nop + 80013ec: 3714 adds r7, #20 + 80013ee: 46bd mov sp, r7 + 80013f0: bc80 pop {r7} + 80013f2: 4770 bx lr + +080013f4 : +{ + 80013f4: b480 push {r7} + 80013f6: b083 sub sp, #12 + 80013f8: af00 add r7, sp, #0 + 80013fa: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB1ENR2, Periphs); + 80013fc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001400: 6dda ldr r2, [r3, #92] ; 0x5c + 8001402: 687b ldr r3, [r7, #4] + 8001404: 43db mvns r3, r3 + 8001406: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800140a: 4013 ands r3, r2 + 800140c: 65cb str r3, [r1, #92] ; 0x5c +} + 800140e: bf00 nop + 8001410: 370c adds r7, #12 + 8001412: 46bd mov sp, r7 + 8001414: bc80 pop {r7} + 8001416: 4770 bx lr + +08001418 : +{ + 8001418: b480 push {r7} + 800141a: b085 sub sp, #20 + 800141c: af00 add r7, sp, #0 + 800141e: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB2ENR, Periphs); + 8001420: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001424: 6e1a ldr r2, [r3, #96] ; 0x60 + 8001426: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800142a: 687b ldr r3, [r7, #4] + 800142c: 4313 orrs r3, r2 + 800142e: 660b str r3, [r1, #96] ; 0x60 + tmpreg = READ_BIT(RCC->APB2ENR, Periphs); + 8001430: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001434: 6e1a ldr r2, [r3, #96] ; 0x60 + 8001436: 687b ldr r3, [r7, #4] + 8001438: 4013 ands r3, r2 + 800143a: 60fb str r3, [r7, #12] + (void)tmpreg; + 800143c: 68fb ldr r3, [r7, #12] +} + 800143e: bf00 nop + 8001440: 3714 adds r7, #20 + 8001442: 46bd mov sp, r7 + 8001444: bc80 pop {r7} + 8001446: 4770 bx lr + +08001448 : +{ + 8001448: b480 push {r7} + 800144a: b083 sub sp, #12 + 800144c: af00 add r7, sp, #0 + 800144e: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB2ENR, Periphs); + 8001450: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001454: 6e1a ldr r2, [r3, #96] ; 0x60 + 8001456: 687b ldr r3, [r7, #4] + 8001458: 43db mvns r3, r3 + 800145a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800145e: 4013 ands r3, r2 + 8001460: 660b str r3, [r1, #96] ; 0x60 +} + 8001462: bf00 nop + 8001464: 370c adds r7, #12 + 8001466: 46bd mov sp, r7 + 8001468: bc80 pop {r7} + 800146a: 4770 bx lr + +0800146c : +DMA_HandleTypeDef hdma_usart1_tx; + +/* LPUART1 init function */ + +void MX_LPUART1_UART_Init(void) +{ + 800146c: b580 push {r7, lr} + 800146e: af00 add r7, sp, #0 + /* USER CODE END LPUART1_Init 0 */ + + /* USER CODE BEGIN LPUART1_Init 1 */ + + /* USER CODE END LPUART1_Init 1 */ + hlpuart1.Instance = LPUART1; + 8001470: 4b26 ldr r3, [pc, #152] ; (800150c ) + 8001472: 4a27 ldr r2, [pc, #156] ; (8001510 ) + 8001474: 601a str r2, [r3, #0] + hlpuart1.Init.BaudRate = 9600; + 8001476: 4b25 ldr r3, [pc, #148] ; (800150c ) + 8001478: f44f 5216 mov.w r2, #9600 ; 0x2580 + 800147c: 605a str r2, [r3, #4] + hlpuart1.Init.WordLength = UART_WORDLENGTH_8B; + 800147e: 4b23 ldr r3, [pc, #140] ; (800150c ) + 8001480: 2200 movs r2, #0 + 8001482: 609a str r2, [r3, #8] + hlpuart1.Init.StopBits = UART_STOPBITS_1; + 8001484: 4b21 ldr r3, [pc, #132] ; (800150c ) + 8001486: 2200 movs r2, #0 + 8001488: 60da str r2, [r3, #12] + hlpuart1.Init.Parity = UART_PARITY_NONE; + 800148a: 4b20 ldr r3, [pc, #128] ; (800150c ) + 800148c: 2200 movs r2, #0 + 800148e: 611a str r2, [r3, #16] + hlpuart1.Init.Mode = UART_MODE_TX_RX; + 8001490: 4b1e ldr r3, [pc, #120] ; (800150c ) + 8001492: 220c movs r2, #12 + 8001494: 615a str r2, [r3, #20] + hlpuart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 8001496: 4b1d ldr r3, [pc, #116] ; (800150c ) + 8001498: 2200 movs r2, #0 + 800149a: 619a str r2, [r3, #24] + hlpuart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 800149c: 4b1b ldr r3, [pc, #108] ; (800150c ) + 800149e: 2200 movs r2, #0 + 80014a0: 621a str r2, [r3, #32] + hlpuart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 80014a2: 4b1a ldr r3, [pc, #104] ; (800150c ) + 80014a4: 2200 movs r2, #0 + 80014a6: 625a str r2, [r3, #36] ; 0x24 + hlpuart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT|UART_ADVFEATURE_DMADISABLEONERROR_INIT; + 80014a8: 4b18 ldr r3, [pc, #96] ; (800150c ) + 80014aa: 2230 movs r2, #48 ; 0x30 + 80014ac: 629a str r2, [r3, #40] ; 0x28 + hlpuart1.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE; + 80014ae: 4b17 ldr r3, [pc, #92] ; (800150c ) + 80014b0: f44f 5280 mov.w r2, #4096 ; 0x1000 + 80014b4: 63da str r2, [r3, #60] ; 0x3c + hlpuart1.AdvancedInit.DMADisableonRxError = UART_ADVFEATURE_DMA_DISABLEONRXERROR; + 80014b6: 4b15 ldr r3, [pc, #84] ; (800150c ) + 80014b8: f44f 5200 mov.w r2, #8192 ; 0x2000 + 80014bc: 641a str r2, [r3, #64] ; 0x40 + hlpuart1.FifoMode = UART_FIFOMODE_DISABLE; + 80014be: 4b13 ldr r3, [pc, #76] ; (800150c ) + 80014c0: 2200 movs r2, #0 + 80014c2: 665a str r2, [r3, #100] ; 0x64 + if (HAL_UART_Init(&hlpuart1) != HAL_OK) + 80014c4: 4811 ldr r0, [pc, #68] ; (800150c ) + 80014c6: f004 faf8 bl 8005aba + 80014ca: 4603 mov r3, r0 + 80014cc: 2b00 cmp r3, #0 + 80014ce: d001 beq.n 80014d4 + { + Error_Handler(); + 80014d0: f7ff fa18 bl 8000904 + } + if (HAL_UARTEx_SetTxFifoThreshold(&hlpuart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + 80014d4: 2100 movs r1, #0 + 80014d6: 480d ldr r0, [pc, #52] ; (800150c ) + 80014d8: f006 fd49 bl 8007f6e + 80014dc: 4603 mov r3, r0 + 80014de: 2b00 cmp r3, #0 + 80014e0: d001 beq.n 80014e6 + { + Error_Handler(); + 80014e2: f7ff fa0f bl 8000904 + } + if (HAL_UARTEx_SetRxFifoThreshold(&hlpuart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + 80014e6: 2100 movs r1, #0 + 80014e8: 4808 ldr r0, [pc, #32] ; (800150c ) + 80014ea: f006 fd7e bl 8007fea + 80014ee: 4603 mov r3, r0 + 80014f0: 2b00 cmp r3, #0 + 80014f2: d001 beq.n 80014f8 + { + Error_Handler(); + 80014f4: f7ff fa06 bl 8000904 + } + if (HAL_UARTEx_DisableFifoMode(&hlpuart1) != HAL_OK) + 80014f8: 4804 ldr r0, [pc, #16] ; (800150c ) + 80014fa: f006 fd00 bl 8007efe + 80014fe: 4603 mov r3, r0 + 8001500: 2b00 cmp r3, #0 + 8001502: d001 beq.n 8001508 + { + Error_Handler(); + 8001504: f7ff f9fe bl 8000904 + } + /* USER CODE BEGIN LPUART1_Init 2 */ + + /* USER CODE END LPUART1_Init 2 */ + +} + 8001508: bf00 nop + 800150a: bd80 pop {r7, pc} + 800150c: 20000164 .word 0x20000164 + 8001510: 40008000 .word 0x40008000 + +08001514 : +/* USART1 init function */ + +void MX_USART1_UART_Init(void) +{ + 8001514: b580 push {r7, lr} + 8001516: af00 add r7, sp, #0 + /* USER CODE END USART1_Init 0 */ + + /* USER CODE BEGIN USART1_Init 1 */ + + /* USER CODE END USART1_Init 1 */ + huart1.Instance = USART1; + 8001518: 4b22 ldr r3, [pc, #136] ; (80015a4 ) + 800151a: 4a23 ldr r2, [pc, #140] ; (80015a8 ) + 800151c: 601a str r2, [r3, #0] + huart1.Init.BaudRate = 115200; + 800151e: 4b21 ldr r3, [pc, #132] ; (80015a4 ) + 8001520: f44f 32e1 mov.w r2, #115200 ; 0x1c200 + 8001524: 605a str r2, [r3, #4] + huart1.Init.WordLength = UART_WORDLENGTH_8B; + 8001526: 4b1f ldr r3, [pc, #124] ; (80015a4 ) + 8001528: 2200 movs r2, #0 + 800152a: 609a str r2, [r3, #8] + huart1.Init.StopBits = UART_STOPBITS_1; + 800152c: 4b1d ldr r3, [pc, #116] ; (80015a4 ) + 800152e: 2200 movs r2, #0 + 8001530: 60da str r2, [r3, #12] + huart1.Init.Parity = UART_PARITY_NONE; + 8001532: 4b1c ldr r3, [pc, #112] ; (80015a4 ) + 8001534: 2200 movs r2, #0 + 8001536: 611a str r2, [r3, #16] + huart1.Init.Mode = UART_MODE_TX_RX; + 8001538: 4b1a ldr r3, [pc, #104] ; (80015a4 ) + 800153a: 220c movs r2, #12 + 800153c: 615a str r2, [r3, #20] + huart1.Init.HwFlowCtl = UART_HWCONTROL_NONE; + 800153e: 4b19 ldr r3, [pc, #100] ; (80015a4 ) + 8001540: 2200 movs r2, #0 + 8001542: 619a str r2, [r3, #24] + huart1.Init.OverSampling = UART_OVERSAMPLING_16; + 8001544: 4b17 ldr r3, [pc, #92] ; (80015a4 ) + 8001546: 2200 movs r2, #0 + 8001548: 61da str r2, [r3, #28] + huart1.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + 800154a: 4b16 ldr r3, [pc, #88] ; (80015a4 ) + 800154c: 2200 movs r2, #0 + 800154e: 621a str r2, [r3, #32] + huart1.Init.ClockPrescaler = UART_PRESCALER_DIV1; + 8001550: 4b14 ldr r3, [pc, #80] ; (80015a4 ) + 8001552: 2200 movs r2, #0 + 8001554: 625a str r2, [r3, #36] ; 0x24 + huart1.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + 8001556: 4b13 ldr r3, [pc, #76] ; (80015a4 ) + 8001558: 2200 movs r2, #0 + 800155a: 629a str r2, [r3, #40] ; 0x28 + if (HAL_UART_Init(&huart1) != HAL_OK) + 800155c: 4811 ldr r0, [pc, #68] ; (80015a4 ) + 800155e: f004 faac bl 8005aba + 8001562: 4603 mov r3, r0 + 8001564: 2b00 cmp r3, #0 + 8001566: d001 beq.n 800156c + { + Error_Handler(); + 8001568: f7ff f9cc bl 8000904 + } + if (HAL_UARTEx_SetTxFifoThreshold(&huart1, UART_TXFIFO_THRESHOLD_1_8) != HAL_OK) + 800156c: 2100 movs r1, #0 + 800156e: 480d ldr r0, [pc, #52] ; (80015a4 ) + 8001570: f006 fcfd bl 8007f6e + 8001574: 4603 mov r3, r0 + 8001576: 2b00 cmp r3, #0 + 8001578: d001 beq.n 800157e + { + Error_Handler(); + 800157a: f7ff f9c3 bl 8000904 + } + if (HAL_UARTEx_SetRxFifoThreshold(&huart1, UART_RXFIFO_THRESHOLD_1_8) != HAL_OK) + 800157e: 2100 movs r1, #0 + 8001580: 4808 ldr r0, [pc, #32] ; (80015a4 ) + 8001582: f006 fd32 bl 8007fea + 8001586: 4603 mov r3, r0 + 8001588: 2b00 cmp r3, #0 + 800158a: d001 beq.n 8001590 + { + Error_Handler(); + 800158c: f7ff f9ba bl 8000904 + } + if (HAL_UARTEx_EnableFifoMode(&huart1) != HAL_OK) + 8001590: 4804 ldr r0, [pc, #16] ; (80015a4 ) + 8001592: f006 fc79 bl 8007e88 + 8001596: 4603 mov r3, r0 + 8001598: 2b00 cmp r3, #0 + 800159a: d001 beq.n 80015a0 + { + Error_Handler(); + 800159c: f7ff f9b2 bl 8000904 + } + /* USER CODE BEGIN USART1_Init 2 */ + + /* USER CODE END USART1_Init 2 */ + +} + 80015a0: bf00 nop + 80015a2: bd80 pop {r7, pc} + 80015a4: 200001f8 .word 0x200001f8 + 80015a8: 40013800 .word 0x40013800 + +080015ac : + +void HAL_UART_MspInit(UART_HandleTypeDef* uartHandle) +{ + 80015ac: b580 push {r7, lr} + 80015ae: b096 sub sp, #88 ; 0x58 + 80015b0: af00 add r7, sp, #0 + 80015b2: 6078 str r0, [r7, #4] + + GPIO_InitTypeDef GPIO_InitStruct = {0}; + 80015b4: f107 0344 add.w r3, r7, #68 ; 0x44 + 80015b8: 2200 movs r2, #0 + 80015ba: 601a str r2, [r3, #0] + 80015bc: 605a str r2, [r3, #4] + 80015be: 609a str r2, [r3, #8] + 80015c0: 60da str r2, [r3, #12] + 80015c2: 611a str r2, [r3, #16] + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0}; + 80015c4: f107 030c add.w r3, r7, #12 + 80015c8: 2238 movs r2, #56 ; 0x38 + 80015ca: 2100 movs r1, #0 + 80015cc: 4618 mov r0, r3 + 80015ce: f00b fdec bl 800d1aa + if(uartHandle->Instance==LPUART1) + 80015d2: 687b ldr r3, [r7, #4] + 80015d4: 681b ldr r3, [r3, #0] + 80015d6: 4a49 ldr r2, [pc, #292] ; (80016fc ) + 80015d8: 4293 cmp r3, r2 + 80015da: d12e bne.n 800163a + + /* USER CODE END LPUART1_MspInit 0 */ + + /** Initializes the peripherals clocks + */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1; + 80015dc: 2320 movs r3, #32 + 80015de: 60fb str r3, [r7, #12] + PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE; + 80015e0: f44f 6340 mov.w r3, #3072 ; 0xc00 + 80015e4: 61fb str r3, [r7, #28] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 80015e6: f107 030c add.w r3, r7, #12 + 80015ea: 4618 mov r0, r3 + 80015ec: f003 f86e bl 80046cc + 80015f0: 4603 mov r3, r0 + 80015f2: 2b00 cmp r3, #0 + 80015f4: d001 beq.n 80015fa + { + Error_Handler(); + 80015f6: f7ff f985 bl 8000904 + } + + /* LPUART1 clock enable */ + __HAL_RCC_LPUART1_CLK_ENABLE(); + 80015fa: 2001 movs r0, #1 + 80015fc: f7ff fee2 bl 80013c4 + + __HAL_RCC_GPIOA_CLK_ENABLE(); + 8001600: 2001 movs r0, #1 + 8001602: f7ff fec7 bl 8001394 + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + GPIO_InitStruct.Pin = GPS_TX_Pin|GPS_RX_Pin; + 8001606: 230c movs r3, #12 + 8001608: 647b str r3, [r7, #68] ; 0x44 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 800160a: 2302 movs r3, #2 + 800160c: 64bb str r3, [r7, #72] ; 0x48 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 800160e: 2300 movs r3, #0 + 8001610: 64fb str r3, [r7, #76] ; 0x4c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 8001612: 2300 movs r3, #0 + 8001614: 653b str r3, [r7, #80] ; 0x50 + GPIO_InitStruct.Alternate = GPIO_AF8_LPUART1; + 8001616: 2308 movs r3, #8 + 8001618: 657b str r3, [r7, #84] ; 0x54 + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + 800161a: f107 0344 add.w r3, r7, #68 ; 0x44 + 800161e: 4619 mov r1, r3 + 8001620: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 8001624: f001 fb1a bl 8002c5c + + /* LPUART1 interrupt Init */ + HAL_NVIC_SetPriority(LPUART1_IRQn, 0, 0); + 8001628: 2200 movs r2, #0 + 800162a: 2100 movs r1, #0 + 800162c: 2026 movs r0, #38 ; 0x26 + 800162e: f000 fee8 bl 8002402 + HAL_NVIC_EnableIRQ(LPUART1_IRQn); + 8001632: 2026 movs r0, #38 ; 0x26 + 8001634: f000 feff bl 8002436 + HAL_NVIC_EnableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspInit 1 */ + + /* USER CODE END USART1_MspInit 1 */ + } +} + 8001638: e05b b.n 80016f2 + else if(uartHandle->Instance==USART1) + 800163a: 687b ldr r3, [r7, #4] + 800163c: 681b ldr r3, [r3, #0] + 800163e: 4a30 ldr r2, [pc, #192] ; (8001700 ) + 8001640: 4293 cmp r3, r2 + 8001642: d156 bne.n 80016f2 + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USART1; + 8001644: 2301 movs r3, #1 + 8001646: 60fb str r3, [r7, #12] + PeriphClkInitStruct.Usart1ClockSelection = RCC_USART1CLKSOURCE_PCLK2; + 8001648: f44f 3340 mov.w r3, #196608 ; 0x30000 + 800164c: 613b str r3, [r7, #16] + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) + 800164e: f107 030c add.w r3, r7, #12 + 8001652: 4618 mov r0, r3 + 8001654: f003 f83a bl 80046cc + 8001658: 4603 mov r3, r0 + 800165a: 2b00 cmp r3, #0 + 800165c: d001 beq.n 8001662 + Error_Handler(); + 800165e: f7ff f951 bl 8000904 + __HAL_RCC_USART1_CLK_ENABLE(); + 8001662: f44f 4080 mov.w r0, #16384 ; 0x4000 + 8001666: f7ff fed7 bl 8001418 + __HAL_RCC_GPIOB_CLK_ENABLE(); + 800166a: 2002 movs r0, #2 + 800166c: f7ff fe92 bl 8001394 + GPIO_InitStruct.Pin = SERIAL_TX_Pin|SERIAL_RX_Pin; + 8001670: 23c0 movs r3, #192 ; 0xc0 + 8001672: 647b str r3, [r7, #68] ; 0x44 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + 8001674: 2302 movs r3, #2 + 8001676: 64bb str r3, [r7, #72] ; 0x48 + GPIO_InitStruct.Pull = GPIO_NOPULL; + 8001678: 2300 movs r3, #0 + 800167a: 64fb str r3, [r7, #76] ; 0x4c + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_LOW; + 800167c: 2300 movs r3, #0 + 800167e: 653b str r3, [r7, #80] ; 0x50 + GPIO_InitStruct.Alternate = GPIO_AF7_USART1; + 8001680: 2307 movs r3, #7 + 8001682: 657b str r3, [r7, #84] ; 0x54 + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + 8001684: f107 0344 add.w r3, r7, #68 ; 0x44 + 8001688: 4619 mov r1, r3 + 800168a: 481e ldr r0, [pc, #120] ; (8001704 ) + 800168c: f001 fae6 bl 8002c5c + hdma_usart1_tx.Instance = DMA1_Channel1; + 8001690: 4b1d ldr r3, [pc, #116] ; (8001708 ) + 8001692: 4a1e ldr r2, [pc, #120] ; (800170c ) + 8001694: 601a str r2, [r3, #0] + hdma_usart1_tx.Init.Request = DMA_REQUEST_USART1_TX; + 8001696: 4b1c ldr r3, [pc, #112] ; (8001708 ) + 8001698: 2212 movs r2, #18 + 800169a: 605a str r2, [r3, #4] + hdma_usart1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; + 800169c: 4b1a ldr r3, [pc, #104] ; (8001708 ) + 800169e: 2210 movs r2, #16 + 80016a0: 609a str r2, [r3, #8] + hdma_usart1_tx.Init.PeriphInc = DMA_PINC_DISABLE; + 80016a2: 4b19 ldr r3, [pc, #100] ; (8001708 ) + 80016a4: 2200 movs r2, #0 + 80016a6: 60da str r2, [r3, #12] + hdma_usart1_tx.Init.MemInc = DMA_MINC_ENABLE; + 80016a8: 4b17 ldr r3, [pc, #92] ; (8001708 ) + 80016aa: 2280 movs r2, #128 ; 0x80 + 80016ac: 611a str r2, [r3, #16] + hdma_usart1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; + 80016ae: 4b16 ldr r3, [pc, #88] ; (8001708 ) + 80016b0: 2200 movs r2, #0 + 80016b2: 615a str r2, [r3, #20] + hdma_usart1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; + 80016b4: 4b14 ldr r3, [pc, #80] ; (8001708 ) + 80016b6: 2200 movs r2, #0 + 80016b8: 619a str r2, [r3, #24] + hdma_usart1_tx.Init.Mode = DMA_NORMAL; + 80016ba: 4b13 ldr r3, [pc, #76] ; (8001708 ) + 80016bc: 2200 movs r2, #0 + 80016be: 61da str r2, [r3, #28] + hdma_usart1_tx.Init.Priority = DMA_PRIORITY_LOW; + 80016c0: 4b11 ldr r3, [pc, #68] ; (8001708 ) + 80016c2: 2200 movs r2, #0 + 80016c4: 621a str r2, [r3, #32] + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + 80016c6: 4810 ldr r0, [pc, #64] ; (8001708 ) + 80016c8: f000 fede bl 8002488 + 80016cc: 4603 mov r3, r0 + 80016ce: 2b00 cmp r3, #0 + 80016d0: d001 beq.n 80016d6 + Error_Handler(); + 80016d2: f7ff f917 bl 8000904 + __HAL_LINKDMA(uartHandle,hdmatx,hdma_usart1_tx); + 80016d6: 687b ldr r3, [r7, #4] + 80016d8: 4a0b ldr r2, [pc, #44] ; (8001708 ) + 80016da: 67da str r2, [r3, #124] ; 0x7c + 80016dc: 4a0a ldr r2, [pc, #40] ; (8001708 ) + 80016de: 687b ldr r3, [r7, #4] + 80016e0: 6293 str r3, [r2, #40] ; 0x28 + HAL_NVIC_SetPriority(USART1_IRQn, 0, 0); + 80016e2: 2200 movs r2, #0 + 80016e4: 2100 movs r1, #0 + 80016e6: 2024 movs r0, #36 ; 0x24 + 80016e8: f000 fe8b bl 8002402 + HAL_NVIC_EnableIRQ(USART1_IRQn); + 80016ec: 2024 movs r0, #36 ; 0x24 + 80016ee: f000 fea2 bl 8002436 +} + 80016f2: bf00 nop + 80016f4: 3758 adds r7, #88 ; 0x58 + 80016f6: 46bd mov sp, r7 + 80016f8: bd80 pop {r7, pc} + 80016fa: bf00 nop + 80016fc: 40008000 .word 0x40008000 + 8001700: 40013800 .word 0x40013800 + 8001704: 48000400 .word 0x48000400 + 8001708: 2000028c .word 0x2000028c + 800170c: 40020008 .word 0x40020008 + +08001710 : + +void HAL_UART_MspDeInit(UART_HandleTypeDef* uartHandle) +{ + 8001710: b580 push {r7, lr} + 8001712: b082 sub sp, #8 + 8001714: af00 add r7, sp, #0 + 8001716: 6078 str r0, [r7, #4] + + if(uartHandle->Instance==LPUART1) + 8001718: 687b ldr r3, [r7, #4] + 800171a: 681b ldr r3, [r3, #0] + 800171c: 4a13 ldr r2, [pc, #76] ; (800176c ) + 800171e: 4293 cmp r3, r2 + 8001720: d10b bne.n 800173a + { + /* USER CODE BEGIN LPUART1_MspDeInit 0 */ + + /* USER CODE END LPUART1_MspDeInit 0 */ + /* Peripheral clock disable */ + __HAL_RCC_LPUART1_CLK_DISABLE(); + 8001722: 2001 movs r0, #1 + 8001724: f7ff fe66 bl 80013f4 + + /**LPUART1 GPIO Configuration + PA2 ------> LPUART1_TX + PA3 ------> LPUART1_RX + */ + HAL_GPIO_DeInit(GPIOA, GPS_TX_Pin|GPS_RX_Pin); + 8001728: 210c movs r1, #12 + 800172a: f04f 4090 mov.w r0, #1207959552 ; 0x48000000 + 800172e: f001 fbf5 bl 8002f1c + + /* LPUART1 interrupt Deinit */ + HAL_NVIC_DisableIRQ(LPUART1_IRQn); + 8001732: 2026 movs r0, #38 ; 0x26 + 8001734: f000 fe8d bl 8002452 + HAL_NVIC_DisableIRQ(USART1_IRQn); + /* USER CODE BEGIN USART1_MspDeInit 1 */ + + /* USER CODE END USART1_MspDeInit 1 */ + } +} + 8001738: e014 b.n 8001764 + else if(uartHandle->Instance==USART1) + 800173a: 687b ldr r3, [r7, #4] + 800173c: 681b ldr r3, [r3, #0] + 800173e: 4a0c ldr r2, [pc, #48] ; (8001770 ) + 8001740: 4293 cmp r3, r2 + 8001742: d10f bne.n 8001764 + __HAL_RCC_USART1_CLK_DISABLE(); + 8001744: f44f 4080 mov.w r0, #16384 ; 0x4000 + 8001748: f7ff fe7e bl 8001448 + HAL_GPIO_DeInit(GPIOB, SERIAL_TX_Pin|SERIAL_RX_Pin); + 800174c: 21c0 movs r1, #192 ; 0xc0 + 800174e: 4809 ldr r0, [pc, #36] ; (8001774 ) + 8001750: f001 fbe4 bl 8002f1c + HAL_DMA_DeInit(uartHandle->hdmatx); + 8001754: 687b ldr r3, [r7, #4] + 8001756: 6fdb ldr r3, [r3, #124] ; 0x7c + 8001758: 4618 mov r0, r3 + 800175a: f000 ff3d bl 80025d8 + HAL_NVIC_DisableIRQ(USART1_IRQn); + 800175e: 2024 movs r0, #36 ; 0x24 + 8001760: f000 fe77 bl 8002452 +} + 8001764: bf00 nop + 8001766: 3708 adds r7, #8 + 8001768: 46bd mov sp, r7 + 800176a: bd80 pop {r7, pc} + 800176c: 40008000 .word 0x40008000 + 8001770: 40013800 .word 0x40013800 + 8001774: 48000400 .word 0x48000400 + +08001778 : + + return HAL_OK; +} + +void MX_USART1_GPS_Sleep(void) +{ + 8001778: b580 push {r7, lr} + 800177a: af00 add r7, sp, #0 + // Make sure that no LPUART transfer is on-going + while (__HAL_UART_GET_FLAG(&hlpuart1, USART_ISR_BUSY) == SET); + 800177c: bf00 nop + 800177e: 4b0f ldr r3, [pc, #60] ; (80017bc ) + 8001780: 681b ldr r3, [r3, #0] + 8001782: 69db ldr r3, [r3, #28] + 8001784: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8001788: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800178c: d0f7 beq.n 800177e + + // Make sure that LPUART is ready to receive + while (__HAL_UART_GET_FLAG(&hlpuart1, USART_ISR_REACK) == RESET); + 800178e: bf00 nop + 8001790: 4b0a ldr r3, [pc, #40] ; (80017bc ) + 8001792: 681b ldr r3, [r3, #0] + 8001794: 69db ldr r3, [r3, #28] + 8001796: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800179a: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 800179e: d1f7 bne.n 8001790 + + __HAL_UART_ENABLE_IT(&hlpuart1, UART_IT_WUF); + 80017a0: 4b06 ldr r3, [pc, #24] ; (80017bc ) + 80017a2: 681b ldr r3, [r3, #0] + 80017a4: 689a ldr r2, [r3, #8] + 80017a6: 4b05 ldr r3, [pc, #20] ; (80017bc ) + 80017a8: 681b ldr r3, [r3, #0] + 80017aa: f442 0280 orr.w r2, r2, #4194304 ; 0x400000 + 80017ae: 609a str r2, [r3, #8] + + HAL_UARTEx_EnableStopMode(&hlpuart1); + 80017b0: 4802 ldr r0, [pc, #8] ; (80017bc ) + 80017b2: f006 fb05 bl 8007dc0 +} + 80017b6: bf00 nop + 80017b8: bd80 pop {r7, pc} + 80017ba: bf00 nop + 80017bc: 20000164 .word 0x20000164 + +080017c0 : + +void MX_USART1_GPS_WakeUp(void) +{ + 80017c0: b580 push {r7, lr} + 80017c2: af00 add r7, sp, #0 + HAL_UARTEx_DisableStopMode(&hlpuart1); + 80017c4: 4802 ldr r0, [pc, #8] ; (80017d0 ) + 80017c6: f006 fb2d bl 8007e24 +} + 80017ca: bf00 nop + 80017cc: bd80 pop {r7, pc} + 80017ce: bf00 nop + 80017d0: 20000164 .word 0x20000164 + +080017d4 : + +int32_t MX_USART1_GPS_GetNMEA(char* p_LineBuffer, uint32_t Length) +{ + 80017d4: b580 push {r7, lr} + 80017d6: b084 sub sp, #16 + 80017d8: af00 add r7, sp, #0 + 80017da: 6078 str r0, [r7, #4] + 80017dc: 6039 str r1, [r7, #0] + uint8_t Temp; + uint32_t BytesReceived = 0; + 80017de: 2300 movs r3, #0 + 80017e0: 60fb str r3, [r7, #12] + + if (Length == 0) + 80017e2: 683b ldr r3, [r7, #0] + 80017e4: 2b00 cmp r3, #0 + 80017e6: d101 bne.n 80017ec + { + return HAL_ERROR; + 80017e8: 2301 movs r3, #1 + 80017ea: e020 b.n 800182e + } + + memset(p_LineBuffer, 0, Length); + 80017ec: 683a ldr r2, [r7, #0] + 80017ee: 2100 movs r1, #0 + 80017f0: 6878 ldr r0, [r7, #4] + 80017f2: f00b fcda bl 800d1aa + + do + { + if (HAL_UART_Receive(&hlpuart1, &Temp, 1, 10) != HAL_OK) + 80017f6: f107 010b add.w r1, r7, #11 + 80017fa: 230a movs r3, #10 + 80017fc: 2201 movs r2, #1 + 80017fe: 480e ldr r0, [pc, #56] ; (8001838 ) + 8001800: f004 f9ab bl 8005b5a + 8001804: 4603 mov r3, r0 + 8001806: 2b00 cmp r3, #0 + 8001808: d001 beq.n 800180e + { + return HAL_ERROR; + 800180a: 2301 movs r3, #1 + 800180c: e00f b.n 800182e + } + + *p_LineBuffer++ = Temp; + 800180e: 687b ldr r3, [r7, #4] + 8001810: 1c5a adds r2, r3, #1 + 8001812: 607a str r2, [r7, #4] + 8001814: 7afa ldrb r2, [r7, #11] + 8001816: 701a strb r2, [r3, #0] + BytesReceived++; + 8001818: 68fb ldr r3, [r7, #12] + 800181a: 3301 adds r3, #1 + 800181c: 60fb str r3, [r7, #12] + } while ((Temp != '\n') || (BytesReceived == Length)); + 800181e: 7afb ldrb r3, [r7, #11] + 8001820: 2b0a cmp r3, #10 + 8001822: d1e8 bne.n 80017f6 + 8001824: 68fa ldr r2, [r7, #12] + 8001826: 683b ldr r3, [r7, #0] + 8001828: 429a cmp r2, r3 + 800182a: d0e4 beq.n 80017f6 + + return HAL_OK; + 800182c: 2300 movs r3, #0 +} + 800182e: 4618 mov r0, r3 + 8001830: 3710 adds r7, #16 + 8001832: 46bd mov sp, r7 + 8001834: bd80 pop {r7, pc} + 8001836: bf00 nop + 8001838: 20000164 .word 0x20000164 + +0800183c : +{ + 800183c: b480 push {r7} + 800183e: b083 sub sp, #12 + 8001840: af00 add r7, sp, #0 + 8001842: 6078 str r0, [r7, #4] + SET_BIT(RCC->APB2RSTR, Periphs); + 8001844: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001848: 6c1a ldr r2, [r3, #64] ; 0x40 + 800184a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800184e: 687b ldr r3, [r7, #4] + 8001850: 4313 orrs r3, r2 + 8001852: 640b str r3, [r1, #64] ; 0x40 +} + 8001854: bf00 nop + 8001856: 370c adds r7, #12 + 8001858: 46bd mov sp, r7 + 800185a: bc80 pop {r7} + 800185c: 4770 bx lr + +0800185e : +{ + 800185e: b480 push {r7} + 8001860: b083 sub sp, #12 + 8001862: af00 add r7, sp, #0 + 8001864: 6078 str r0, [r7, #4] + CLEAR_BIT(RCC->APB2RSTR, Periphs); + 8001866: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800186a: 6c1a ldr r2, [r3, #64] ; 0x40 + 800186c: 687b ldr r3, [r7, #4] + 800186e: 43db mvns r3, r3 + 8001870: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8001874: 4013 ands r3, r2 + 8001876: 640b str r3, [r1, #64] ; 0x40 +} + 8001878: bf00 nop + 800187a: 370c adds r7, #12 + 800187c: 46bd mov sp, r7 + 800187e: bc80 pop {r7} + 8001880: 4770 bx lr + ... + +08001884 : +{ + 8001884: b480 push {r7} + 8001886: b083 sub sp, #12 + 8001888: af00 add r7, sp, #0 + 800188a: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR1, ExtiLine); + 800188c: 4b06 ldr r3, [pc, #24] ; (80018a8 ) + 800188e: f8d3 2080 ldr.w r2, [r3, #128] ; 0x80 + 8001892: 4905 ldr r1, [pc, #20] ; (80018a8 ) + 8001894: 687b ldr r3, [r7, #4] + 8001896: 4313 orrs r3, r2 + 8001898: f8c1 3080 str.w r3, [r1, #128] ; 0x80 +} + 800189c: bf00 nop + 800189e: 370c adds r7, #12 + 80018a0: 46bd mov sp, r7 + 80018a2: bc80 pop {r7} + 80018a4: 4770 bx lr + 80018a6: bf00 nop + 80018a8: 58000800 .word 0x58000800 + +080018ac : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +UTIL_ADV_TRACE_Status_t vcom_Init(void (*cb)(void *)) +{ + 80018ac: b580 push {r7, lr} + 80018ae: b082 sub sp, #8 + 80018b0: af00 add r7, sp, #0 + 80018b2: 6078 str r0, [r7, #4] + /* USER CODE BEGIN vcom_Init_1 */ + + /* USER CODE END vcom_Init_1 */ + TxCpltCallback = cb; + 80018b4: 4a07 ldr r2, [pc, #28] ; (80018d4 ) + 80018b6: 687b ldr r3, [r7, #4] + 80018b8: 6013 str r3, [r2, #0] + MX_DMA_Init(); + 80018ba: f7fe fef9 bl 80006b0 + MX_USART1_UART_Init(); + 80018be: f7ff fe29 bl 8001514 + LL_EXTI_EnableIT_0_31(LL_EXTI_LINE_26); + 80018c2: f04f 6080 mov.w r0, #67108864 ; 0x4000000 + 80018c6: f7ff ffdd bl 8001884 + return UTIL_ADV_TRACE_OK; + 80018ca: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_Init_2 */ + + /* USER CODE END vcom_Init_2 */ +} + 80018cc: 4618 mov r0, r3 + 80018ce: 3708 adds r7, #8 + 80018d0: 46bd mov sp, r7 + 80018d2: bd80 pop {r7, pc} + 80018d4: 200002f0 .word 0x200002f0 + +080018d8 : + +UTIL_ADV_TRACE_Status_t vcom_DeInit(void) +{ + 80018d8: b580 push {r7, lr} + 80018da: af00 add r7, sp, #0 + /* USER CODE BEGIN vcom_DeInit_1 */ + + /* USER CODE END vcom_DeInit_1 */ + /* ##-1- Reset peripherals ################################################## */ + __HAL_RCC_USART1_FORCE_RESET(); + 80018dc: f44f 4080 mov.w r0, #16384 ; 0x4000 + 80018e0: f7ff ffac bl 800183c + __HAL_RCC_USART1_RELEASE_RESET(); + 80018e4: f44f 4080 mov.w r0, #16384 ; 0x4000 + 80018e8: f7ff ffb9 bl 800185e + + /* ##-2- MspDeInit ################################################## */ + HAL_UART_MspDeInit(&huart1); + 80018ec: 4804 ldr r0, [pc, #16] ; (8001900 ) + 80018ee: f7ff ff0f bl 8001710 + + /* ##-3- Disable the NVIC for DMA ########################################### */ + /* USER CODE BEGIN 1 */ + HAL_NVIC_DisableIRQ(DMA1_Channel5_IRQn); + 80018f2: 200f movs r0, #15 + 80018f4: f000 fdad bl 8002452 + + return UTIL_ADV_TRACE_OK; + 80018f8: 2300 movs r3, #0 + /* USER CODE END 1 */ + /* USER CODE BEGIN vcom_DeInit_2 */ + + /* USER CODE END vcom_DeInit_2 */ +} + 80018fa: 4618 mov r0, r3 + 80018fc: bd80 pop {r7, pc} + 80018fe: bf00 nop + 8001900: 200001f8 .word 0x200001f8 + +08001904 : + + /* USER CODE END vcom_Trace_2 */ +} + +UTIL_ADV_TRACE_Status_t vcom_Trace_DMA(uint8_t *p_data, uint16_t size) +{ + 8001904: b580 push {r7, lr} + 8001906: b082 sub sp, #8 + 8001908: af00 add r7, sp, #0 + 800190a: 6078 str r0, [r7, #4] + 800190c: 460b mov r3, r1 + 800190e: 807b strh r3, [r7, #2] + /* USER CODE BEGIN vcom_Trace_DMA_1 */ + + /* USER CODE END vcom_Trace_DMA_1 */ + HAL_UART_Transmit_DMA(&huart1, p_data, size); + 8001910: 887b ldrh r3, [r7, #2] + 8001912: 461a mov r2, r3 + 8001914: 6879 ldr r1, [r7, #4] + 8001916: 4804 ldr r0, [pc, #16] ; (8001928 ) + 8001918: f004 fa30 bl 8005d7c + return UTIL_ADV_TRACE_OK; + 800191c: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_Trace_DMA_2 */ + + /* USER CODE END vcom_Trace_DMA_2 */ +} + 800191e: 4618 mov r0, r3 + 8001920: 3708 adds r7, #8 + 8001922: 46bd mov sp, r7 + 8001924: bd80 pop {r7, pc} + 8001926: bf00 nop + 8001928: 200001f8 .word 0x200001f8 + +0800192c : + +UTIL_ADV_TRACE_Status_t vcom_ReceiveInit(void (*RxCb)(uint8_t *rxChar, uint16_t size, uint8_t error)) +{ + 800192c: b580 push {r7, lr} + 800192e: b084 sub sp, #16 + 8001930: af00 add r7, sp, #0 + 8001932: 6078 str r0, [r7, #4] + + /* USER CODE END vcom_ReceiveInit_1 */ + UART_WakeUpTypeDef WakeUpSelection; + + /*record call back*/ + RxCpltCallback = RxCb; + 8001934: 4a19 ldr r2, [pc, #100] ; (800199c ) + 8001936: 687b ldr r3, [r7, #4] + 8001938: 6013 str r3, [r2, #0] + + /*Set wakeUp event on start bit*/ + WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_STARTBIT; + 800193a: f44f 1300 mov.w r3, #2097152 ; 0x200000 + 800193e: 60bb str r3, [r7, #8] + + HAL_UARTEx_StopModeWakeUpSourceConfig(&huart1, WakeUpSelection); + 8001940: f107 0308 add.w r3, r7, #8 + 8001944: e893 0006 ldmia.w r3, {r1, r2} + 8001948: 4815 ldr r0, [pc, #84] ; (80019a0 ) + 800194a: f006 f9de bl 8007d0a + + /* Make sure that no UART transfer is on-going */ + while (__HAL_UART_GET_FLAG(&huart1, USART_ISR_BUSY) == SET); + 800194e: bf00 nop + 8001950: 4b13 ldr r3, [pc, #76] ; (80019a0 ) + 8001952: 681b ldr r3, [r3, #0] + 8001954: 69db ldr r3, [r3, #28] + 8001956: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800195a: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800195e: d0f7 beq.n 8001950 + + /* Make sure that UART is ready to receive) */ + while (__HAL_UART_GET_FLAG(&huart1, USART_ISR_REACK) == RESET); + 8001960: bf00 nop + 8001962: 4b0f ldr r3, [pc, #60] ; (80019a0 ) + 8001964: 681b ldr r3, [r3, #0] + 8001966: 69db ldr r3, [r3, #28] + 8001968: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 800196c: f5b3 0f80 cmp.w r3, #4194304 ; 0x400000 + 8001970: d1f7 bne.n 8001962 + + /* Enable USART interrupt */ + __HAL_UART_ENABLE_IT(&huart1, UART_IT_WUF); + 8001972: 4b0b ldr r3, [pc, #44] ; (80019a0 ) + 8001974: 681b ldr r3, [r3, #0] + 8001976: 689a ldr r2, [r3, #8] + 8001978: 4b09 ldr r3, [pc, #36] ; (80019a0 ) + 800197a: 681b ldr r3, [r3, #0] + 800197c: f442 0280 orr.w r2, r2, #4194304 ; 0x400000 + 8001980: 609a str r2, [r3, #8] + + /*Enable wakeup from stop mode*/ + HAL_UARTEx_EnableStopMode(&huart1); + 8001982: 4807 ldr r0, [pc, #28] ; (80019a0 ) + 8001984: f006 fa1c bl 8007dc0 + + /*Start LPUART receive on IT*/ + HAL_UART_Receive_IT(&huart1, &charRx, 1); + 8001988: 2201 movs r2, #1 + 800198a: 4906 ldr r1, [pc, #24] ; (80019a4 ) + 800198c: 4804 ldr r0, [pc, #16] ; (80019a0 ) + 800198e: f004 f9a9 bl 8005ce4 + + return UTIL_ADV_TRACE_OK; + 8001992: 2300 movs r3, #0 + /* USER CODE BEGIN vcom_ReceiveInit_2 */ + + /* USER CODE END vcom_ReceiveInit_2 */ +} + 8001994: 4618 mov r0, r3 + 8001996: 3710 adds r7, #16 + 8001998: 46bd mov sp, r7 + 800199a: bd80 pop {r7, pc} + 800199c: 200002f4 .word 0x200002f4 + 80019a0: 200001f8 .word 0x200001f8 + 80019a4: 200002ec .word 0x200002ec + +080019a8 : + +void vcom_Resume(void) +{ + 80019a8: b580 push {r7, lr} + 80019aa: af00 add r7, sp, #0 + /* USER CODE BEGIN vcom_Resume_1 */ + + /* USER CODE END vcom_Resume_1 */ + /*to re-enable lost UART settings*/ + if (HAL_UART_Init(&huart1) != HAL_OK) + 80019ac: 4808 ldr r0, [pc, #32] ; (80019d0 ) + 80019ae: f004 f884 bl 8005aba + 80019b2: 4603 mov r3, r0 + 80019b4: 2b00 cmp r3, #0 + 80019b6: d001 beq.n 80019bc + { + Error_Handler(); + 80019b8: f7fe ffa4 bl 8000904 + } + + /*to re-enable lost DMA settings*/ + if (HAL_DMA_Init(&hdma_usart1_tx) != HAL_OK) + 80019bc: 4805 ldr r0, [pc, #20] ; (80019d4 ) + 80019be: f000 fd63 bl 8002488 + 80019c2: 4603 mov r3, r0 + 80019c4: 2b00 cmp r3, #0 + 80019c6: d001 beq.n 80019cc + { + Error_Handler(); + 80019c8: f7fe ff9c bl 8000904 + } + /* USER CODE BEGIN vcom_Resume_2 */ + + /* USER CODE END vcom_Resume_2 */ +} + 80019cc: bf00 nop + 80019ce: bd80 pop {r7, pc} + 80019d0: 200001f8 .word 0x200001f8 + 80019d4: 2000028c .word 0x2000028c + +080019d8 : + +void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) +{ + 80019d8: b580 push {r7, lr} + 80019da: b082 sub sp, #8 + 80019dc: af00 add r7, sp, #0 + 80019de: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_UART_TxCpltCallback_1 */ + + /* USER CODE END HAL_UART_TxCpltCallback_1 */ + /* buffer transmission complete*/ + if (huart->Instance == USART1) + 80019e0: 687b ldr r3, [r7, #4] + 80019e2: 681b ldr r3, [r3, #0] + 80019e4: 4a05 ldr r2, [pc, #20] ; (80019fc ) + 80019e6: 4293 cmp r3, r2 + 80019e8: d103 bne.n 80019f2 + { + TxCpltCallback(NULL); + 80019ea: 4b05 ldr r3, [pc, #20] ; (8001a00 ) + 80019ec: 681b ldr r3, [r3, #0] + 80019ee: 2000 movs r0, #0 + 80019f0: 4798 blx r3 + } + /* USER CODE BEGIN HAL_UART_TxCpltCallback_2 */ + + /* USER CODE END HAL_UART_TxCpltCallback_2 */ +} + 80019f2: bf00 nop + 80019f4: 3708 adds r7, #8 + 80019f6: 46bd mov sp, r7 + 80019f8: bd80 pop {r7, pc} + 80019fa: bf00 nop + 80019fc: 40013800 .word 0x40013800 + 8001a00: 200002f0 .word 0x200002f0 + +08001a04 : + +void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) +{ + 8001a04: b580 push {r7, lr} + 8001a06: b082 sub sp, #8 + 8001a08: af00 add r7, sp, #0 + 8001a0a: 6078 str r0, [r7, #4] + /* USER CODE BEGIN HAL_UART_RxCpltCallback_1 */ + + /* USER CODE END HAL_UART_RxCpltCallback_1 */ + if (huart->Instance == USART1) + 8001a0c: 687b ldr r3, [r7, #4] + 8001a0e: 681b ldr r3, [r3, #0] + 8001a10: 4a0d ldr r2, [pc, #52] ; (8001a48 ) + 8001a12: 4293 cmp r3, r2 + 8001a14: d113 bne.n 8001a3e + { + if ((NULL != RxCpltCallback) && (HAL_UART_ERROR_NONE == huart->ErrorCode)) + 8001a16: 4b0d ldr r3, [pc, #52] ; (8001a4c ) + 8001a18: 681b ldr r3, [r3, #0] + 8001a1a: 2b00 cmp r3, #0 + 8001a1c: d00a beq.n 8001a34 + 8001a1e: 687b ldr r3, [r7, #4] + 8001a20: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8001a24: 2b00 cmp r3, #0 + 8001a26: d105 bne.n 8001a34 + { + RxCpltCallback(&charRx, 1, 0); + 8001a28: 4b08 ldr r3, [pc, #32] ; (8001a4c ) + 8001a2a: 681b ldr r3, [r3, #0] + 8001a2c: 2200 movs r2, #0 + 8001a2e: 2101 movs r1, #1 + 8001a30: 4807 ldr r0, [pc, #28] ; (8001a50 ) + 8001a32: 4798 blx r3 + } + HAL_UART_Receive_IT(huart, &charRx, 1); + 8001a34: 2201 movs r2, #1 + 8001a36: 4906 ldr r1, [pc, #24] ; (8001a50 ) + 8001a38: 6878 ldr r0, [r7, #4] + 8001a3a: f004 f953 bl 8005ce4 + } + /* USER CODE BEGIN HAL_UART_RxCpltCallback_2 */ + + /* USER CODE END HAL_UART_RxCpltCallback_2 */ +} + 8001a3e: bf00 nop + 8001a40: 3708 adds r7, #8 + 8001a42: 46bd mov sp, r7 + 8001a44: bd80 pop {r7, pc} + 8001a46: bf00 nop + 8001a48: 40013800 .word 0x40013800 + 8001a4c: 200002f4 .word 0x200002f4 + 8001a50: 200002ec .word 0x200002ec + +08001a54 : + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + 8001a54: 480d ldr r0, [pc, #52] ; (8001a8c ) + mov sp, r0 /* set stack pointer */ + 8001a56: 4685 mov sp, r0 + +/* Call the clock system initialization function.*/ + bl SystemInit + 8001a58: f7ff fa62 bl 8000f20 + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + 8001a5c: 480c ldr r0, [pc, #48] ; (8001a90 ) + ldr r1, =_edata + 8001a5e: 490d ldr r1, [pc, #52] ; (8001a94 ) + ldr r2, =_sidata + 8001a60: 4a0d ldr r2, [pc, #52] ; (8001a98 ) + movs r3, #0 + 8001a62: 2300 movs r3, #0 + b LoopCopyDataInit + 8001a64: e002 b.n 8001a6c + +08001a66 : + +CopyDataInit: + ldr r4, [r2, r3] + 8001a66: 58d4 ldr r4, [r2, r3] + str r4, [r0, r3] + 8001a68: 50c4 str r4, [r0, r3] + adds r3, r3, #4 + 8001a6a: 3304 adds r3, #4 + +08001a6c : + +LoopCopyDataInit: + adds r4, r0, r3 + 8001a6c: 18c4 adds r4, r0, r3 + cmp r4, r1 + 8001a6e: 428c cmp r4, r1 + bcc CopyDataInit + 8001a70: d3f9 bcc.n 8001a66 + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + 8001a72: 4a0a ldr r2, [pc, #40] ; (8001a9c ) + ldr r4, =_ebss + 8001a74: 4c0a ldr r4, [pc, #40] ; (8001aa0 ) + movs r3, #0 + 8001a76: 2300 movs r3, #0 + b LoopFillZerobss + 8001a78: e001 b.n 8001a7e + +08001a7a : + +FillZerobss: + str r3, [r2] + 8001a7a: 6013 str r3, [r2, #0] + adds r2, r2, #4 + 8001a7c: 3204 adds r2, #4 + +08001a7e : + +LoopFillZerobss: + cmp r2, r4 + 8001a7e: 42a2 cmp r2, r4 + bcc FillZerobss + 8001a80: d3fb bcc.n 8001a7a + +/* Call static constructors */ + bl __libc_init_array + 8001a82: f00b fc59 bl 800d338 <__libc_init_array> +/* Call the application's entry point.*/ + bl main + 8001a86: f7fe fec5 bl 8000814
+ +08001a8a : + +LoopForever: + b LoopForever + 8001a8a: e7fe b.n 8001a8a + ldr r0, =_estack + 8001a8c: 20010000 .word 0x20010000 + ldr r0, =_sdata + 8001a90: 20000000 .word 0x20000000 + ldr r1, =_edata + 8001a94: 20000090 .word 0x20000090 + ldr r2, =_sidata + 8001a98: 0800e644 .word 0x0800e644 + ldr r2, =_sbss + 8001a9c: 20000090 .word 0x20000090 + ldr r4, =_ebss + 8001aa0: 20000a48 .word 0x20000a48 + +08001aa4 : + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + 8001aa4: e7fe b.n 8001aa4 + +08001aa6 : +{ + 8001aa6: b480 push {r7} + 8001aa8: b085 sub sp, #20 + 8001aaa: af00 add r7, sp, #0 + 8001aac: 6078 str r0, [r7, #4] + SET_BIT(RCC->AHB2ENR, Periphs); + 8001aae: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001ab2: 6cda ldr r2, [r3, #76] ; 0x4c + 8001ab4: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8001ab8: 687b ldr r3, [r7, #4] + 8001aba: 4313 orrs r3, r2 + 8001abc: 64cb str r3, [r1, #76] ; 0x4c + tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); + 8001abe: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8001ac2: 6cda ldr r2, [r3, #76] ; 0x4c + 8001ac4: 687b ldr r3, [r7, #4] + 8001ac6: 4013 ands r3, r2 + 8001ac8: 60fb str r3, [r7, #12] + (void)tmpreg; + 8001aca: 68fb ldr r3, [r7, #12] +} + 8001acc: bf00 nop + 8001ace: 3714 adds r7, #20 + 8001ad0: 46bd mov sp, r7 + 8001ad2: bc80 pop {r7} + 8001ad4: 4770 bx lr + ... + +08001ad8 : +/** + * @brief Init Radio Switch + * @retval BSP status + */ +int32_t BSP_RADIO_Init(void) +{ + 8001ad8: b580 push {r7, lr} + 8001ada: b086 sub sp, #24 + 8001adc: af00 add r7, sp, #0 + GPIO_InitTypeDef gpio_init_structure = {0}; + 8001ade: 1d3b adds r3, r7, #4 + 8001ae0: 2200 movs r2, #0 + 8001ae2: 601a str r2, [r3, #0] + 8001ae4: 605a str r2, [r3, #4] + 8001ae6: 609a str r2, [r3, #8] + 8001ae8: 60da str r2, [r3, #12] + 8001aea: 611a str r2, [r3, #16] + + /* Enable the Radio Switch Clock */ + RF_SW_CTRL3_GPIO_CLK_ENABLE(); + 8001aec: 2004 movs r0, #4 + 8001aee: f7ff ffda bl 8001aa6 + + /* Configure the Radio Switch pin */ + gpio_init_structure.Pin = RF_SW_CTRL1_PIN; + 8001af2: 2310 movs r3, #16 + 8001af4: 607b str r3, [r7, #4] + gpio_init_structure.Mode = GPIO_MODE_OUTPUT_PP; + 8001af6: 2301 movs r3, #1 + 8001af8: 60bb str r3, [r7, #8] + gpio_init_structure.Pull = GPIO_NOPULL; + 8001afa: 2300 movs r3, #0 + 8001afc: 60fb str r3, [r7, #12] + gpio_init_structure.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + 8001afe: 2303 movs r3, #3 + 8001b00: 613b str r3, [r7, #16] + + HAL_GPIO_Init(RF_SW_CTRL1_GPIO_PORT, &gpio_init_structure); + 8001b02: 1d3b adds r3, r7, #4 + 8001b04: 4619 mov r1, r3 + 8001b06: 4812 ldr r0, [pc, #72] ; (8001b50 ) + 8001b08: f001 f8a8 bl 8002c5c + + gpio_init_structure.Pin = RF_SW_CTRL2_PIN; + 8001b0c: 2320 movs r3, #32 + 8001b0e: 607b str r3, [r7, #4] + HAL_GPIO_Init(RF_SW_CTRL2_GPIO_PORT, &gpio_init_structure); + 8001b10: 1d3b adds r3, r7, #4 + 8001b12: 4619 mov r1, r3 + 8001b14: 480e ldr r0, [pc, #56] ; (8001b50 ) + 8001b16: f001 f8a1 bl 8002c5c + + gpio_init_structure.Pin = RF_SW_CTRL3_PIN; + 8001b1a: 2308 movs r3, #8 + 8001b1c: 607b str r3, [r7, #4] + HAL_GPIO_Init(RF_SW_CTRL3_GPIO_PORT, &gpio_init_structure); + 8001b1e: 1d3b adds r3, r7, #4 + 8001b20: 4619 mov r1, r3 + 8001b22: 480b ldr r0, [pc, #44] ; (8001b50 ) + 8001b24: f001 f89a bl 8002c5c + + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 8001b28: 2200 movs r2, #0 + 8001b2a: 2120 movs r1, #32 + 8001b2c: 4808 ldr r0, [pc, #32] ; (8001b50 ) + 8001b2e: f001 fac3 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 8001b32: 2200 movs r2, #0 + 8001b34: 2110 movs r1, #16 + 8001b36: 4806 ldr r0, [pc, #24] ; (8001b50 ) + 8001b38: f001 fabe bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + 8001b3c: 2200 movs r2, #0 + 8001b3e: 2108 movs r1, #8 + 8001b40: 4803 ldr r0, [pc, #12] ; (8001b50 ) + 8001b42: f001 fab9 bl 80030b8 + + return BSP_ERROR_NONE; + 8001b46: 2300 movs r3, #0 +} + 8001b48: 4618 mov r0, r3 + 8001b4a: 3718 adds r7, #24 + 8001b4c: 46bd mov sp, r7 + 8001b4e: bd80 pop {r7, pc} + 8001b50: 48000800 .word 0x48000800 + +08001b54 : + * @arg RADIO_SWITCH_RFO_LP + * @arg RADIO_SWITCH_RFO_HP + * @retval BSP status + */ +int32_t BSP_RADIO_ConfigRFSwitch(BSP_RADIO_Switch_TypeDef Config) +{ + 8001b54: b580 push {r7, lr} + 8001b56: b082 sub sp, #8 + 8001b58: af00 add r7, sp, #0 + 8001b5a: 4603 mov r3, r0 + 8001b5c: 71fb strb r3, [r7, #7] + switch (Config) + 8001b5e: 79fb ldrb r3, [r7, #7] + 8001b60: 2b03 cmp r3, #3 + 8001b62: d84b bhi.n 8001bfc + 8001b64: a201 add r2, pc, #4 ; (adr r2, 8001b6c ) + 8001b66: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8001b6a: bf00 nop + 8001b6c: 08001b7d .word 0x08001b7d + 8001b70: 08001b9d .word 0x08001b9d + 8001b74: 08001bbd .word 0x08001bbd + 8001b78: 08001bdd .word 0x08001bdd + { + case RADIO_SWITCH_OFF: + { + /* Turn off switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_RESET); + 8001b7c: 2200 movs r2, #0 + 8001b7e: 2108 movs r1, #8 + 8001b80: 4821 ldr r0, [pc, #132] ; (8001c08 ) + 8001b82: f001 fa99 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 8001b86: 2200 movs r2, #0 + 8001b88: 2110 movs r1, #16 + 8001b8a: 481f ldr r0, [pc, #124] ; (8001c08 ) + 8001b8c: f001 fa94 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 8001b90: 2200 movs r2, #0 + 8001b92: 2120 movs r1, #32 + 8001b94: 481c ldr r0, [pc, #112] ; (8001c08 ) + 8001b96: f001 fa8f bl 80030b8 + break; + 8001b9a: e030 b.n 8001bfe + } + case RADIO_SWITCH_RX: + { + /*Turns On in Rx Mode the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 8001b9c: 2201 movs r2, #1 + 8001b9e: 2108 movs r1, #8 + 8001ba0: 4819 ldr r0, [pc, #100] ; (8001c08 ) + 8001ba2: f001 fa89 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + 8001ba6: 2201 movs r2, #1 + 8001ba8: 2110 movs r1, #16 + 8001baa: 4817 ldr r0, [pc, #92] ; (8001c08 ) + 8001bac: f001 fa84 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_RESET); + 8001bb0: 2200 movs r2, #0 + 8001bb2: 2120 movs r1, #32 + 8001bb4: 4814 ldr r0, [pc, #80] ; (8001c08 ) + 8001bb6: f001 fa7f bl 80030b8 + break; + 8001bba: e020 b.n 8001bfe + } + case RADIO_SWITCH_RFO_LP: + { + /*Turns On in Tx Low Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 8001bbc: 2201 movs r2, #1 + 8001bbe: 2108 movs r1, #8 + 8001bc0: 4811 ldr r0, [pc, #68] ; (8001c08 ) + 8001bc2: f001 fa79 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_SET); + 8001bc6: 2201 movs r2, #1 + 8001bc8: 2110 movs r1, #16 + 8001bca: 480f ldr r0, [pc, #60] ; (8001c08 ) + 8001bcc: f001 fa74 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + 8001bd0: 2201 movs r2, #1 + 8001bd2: 2120 movs r1, #32 + 8001bd4: 480c ldr r0, [pc, #48] ; (8001c08 ) + 8001bd6: f001 fa6f bl 80030b8 + break; + 8001bda: e010 b.n 8001bfe + } + case RADIO_SWITCH_RFO_HP: + { + /*Turns On in Tx High Power the RF Switch */ + HAL_GPIO_WritePin(RF_SW_CTRL3_GPIO_PORT, RF_SW_CTRL3_PIN, GPIO_PIN_SET); + 8001bdc: 2201 movs r2, #1 + 8001bde: 2108 movs r1, #8 + 8001be0: 4809 ldr r0, [pc, #36] ; (8001c08 ) + 8001be2: f001 fa69 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL1_GPIO_PORT, RF_SW_CTRL1_PIN, GPIO_PIN_RESET); + 8001be6: 2200 movs r2, #0 + 8001be8: 2110 movs r1, #16 + 8001bea: 4807 ldr r0, [pc, #28] ; (8001c08 ) + 8001bec: f001 fa64 bl 80030b8 + HAL_GPIO_WritePin(RF_SW_CTRL2_GPIO_PORT, RF_SW_CTRL2_PIN, GPIO_PIN_SET); + 8001bf0: 2201 movs r2, #1 + 8001bf2: 2120 movs r1, #32 + 8001bf4: 4804 ldr r0, [pc, #16] ; (8001c08 ) + 8001bf6: f001 fa5f bl 80030b8 + break; + 8001bfa: e000 b.n 8001bfe + } + default: + break; + 8001bfc: bf00 nop + } + + return BSP_ERROR_NONE; + 8001bfe: 2300 movs r3, #0 +} + 8001c00: 4618 mov r0, r3 + 8001c02: 3708 adds r7, #8 + 8001c04: 46bd mov sp, r7 + 8001c06: bd80 pop {r7, pc} + 8001c08: 48000800 .word 0x48000800 + +08001c0c : + * RADIO_CONF_RFO_LP_HP + * RADIO_CONF_RFO_LP + * RADIO_CONF_RFO_HP + */ +int32_t BSP_RADIO_GetTxConfig(void) +{ + 8001c0c: b480 push {r7} + 8001c0e: af00 add r7, sp, #0 + return RADIO_CONF_RFO_LP_HP; + 8001c10: 2300 movs r3, #0 +} + 8001c12: 4618 mov r0, r3 + 8001c14: 46bd mov sp, r7 + 8001c16: bc80 pop {r7} + 8001c18: 4770 bx lr + +08001c1a : + * @retval + * RADIO_CONF_TCXO_NOT_SUPPORTED + * RADIO_CONF_TCXO_SUPPORTED + */ +int32_t BSP_RADIO_IsTCXO(void) +{ + 8001c1a: b480 push {r7} + 8001c1c: af00 add r7, sp, #0 + return RADIO_CONF_TCXO_SUPPORTED; + 8001c1e: 2301 movs r3, #1 +} + 8001c20: 4618 mov r0, r3 + 8001c22: 46bd mov sp, r7 + 8001c24: bc80 pop {r7} + 8001c26: 4770 bx lr + +08001c28 : + * @retval + * RADIO_CONF_DCDC_NOT_SUPPORTED + * RADIO_CONF_DCDC_SUPPORTED + */ +int32_t BSP_RADIO_IsDCDC(void) +{ + 8001c28: b480 push {r7} + 8001c2a: af00 add r7, sp, #0 + return RADIO_CONF_DCDC_SUPPORTED; + 8001c2c: 2301 movs r3, #1 +} + 8001c2e: 4618 mov r0, r3 + 8001c30: 46bd mov sp, r7 + 8001c32: bc80 pop {r7} + 8001c34: 4770 bx lr + +08001c36 : + * @retval + * RADIO_CONF_RFO_LP_MAX_15_dBm for LP mode + * RADIO_CONF_RFO_HP_MAX_22_dBm for HP mode + */ +int32_t BSP_RADIO_GetRFOMaxPowerConfig(BSP_RADIO_RFOMaxPowerConfig_TypeDef Config) +{ + 8001c36: b480 push {r7} + 8001c38: b085 sub sp, #20 + 8001c3a: af00 add r7, sp, #0 + 8001c3c: 4603 mov r3, r0 + 8001c3e: 71fb strb r3, [r7, #7] + int32_t ret; + + if(Config == RADIO_RFO_LP_MAXPOWER) + 8001c40: 79fb ldrb r3, [r7, #7] + 8001c42: 2b00 cmp r3, #0 + 8001c44: d102 bne.n 8001c4c + { + ret = RADIO_CONF_RFO_LP_MAX_15_dBm; + 8001c46: 230f movs r3, #15 + 8001c48: 60fb str r3, [r7, #12] + 8001c4a: e001 b.n 8001c50 + } + else + { + ret = RADIO_CONF_RFO_HP_MAX_22_dBm; + 8001c4c: 2316 movs r3, #22 + 8001c4e: 60fb str r3, [r7, #12] + } + + return ret; + 8001c50: 68fb ldr r3, [r7, #12] +} + 8001c52: 4618 mov r0, r3 + 8001c54: 3714 adds r7, #20 + 8001c56: 46bd mov sp, r7 + 8001c58: bc80 pop {r7} + 8001c5a: 4770 bx lr + +08001c5c : + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGSleepMode(void) +{ + 8001c5c: b480 push {r7} + 8001c5e: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP); + 8001c60: 4b04 ldr r3, [pc, #16] ; (8001c74 ) + 8001c62: 685b ldr r3, [r3, #4] + 8001c64: 4a03 ldr r2, [pc, #12] ; (8001c74 ) + 8001c66: f043 0301 orr.w r3, r3, #1 + 8001c6a: 6053 str r3, [r2, #4] +} + 8001c6c: bf00 nop + 8001c6e: 46bd mov sp, r7 + 8001c70: bc80 pop {r7} + 8001c72: 4770 bx lr + 8001c74: e0042000 .word 0xe0042000 + +08001c78 : + * in Stop mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + 8001c78: b480 push {r7} + 8001c7a: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); + 8001c7c: 4b04 ldr r3, [pc, #16] ; (8001c90 ) + 8001c7e: 685b ldr r3, [r3, #4] + 8001c80: 4a03 ldr r2, [pc, #12] ; (8001c90 ) + 8001c82: f043 0302 orr.w r3, r3, #2 + 8001c86: 6053 str r3, [r2, #4] +} + 8001c88: bf00 nop + 8001c8a: 46bd mov sp, r7 + 8001c8c: bc80 pop {r7} + 8001c8e: 4770 bx lr + 8001c90: e0042000 .word 0xe0042000 + +08001c94 : + * in Standby mode even when this bit is enabled + * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStandbyMode(void) +{ + 8001c94: b480 push {r7} + 8001c96: af00 add r7, sp, #0 + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY); + 8001c98: 4b04 ldr r3, [pc, #16] ; (8001cac ) + 8001c9a: 685b ldr r3, [r3, #4] + 8001c9c: 4a03 ldr r2, [pc, #12] ; (8001cac ) + 8001c9e: f043 0304 orr.w r3, r3, #4 + 8001ca2: 6053 str r3, [r2, #4] +} + 8001ca4: bf00 nop + 8001ca6: 46bd mov sp, r7 + 8001ca8: bc80 pop {r7} + 8001caa: 4770 bx lr + 8001cac: e0042000 .word 0xe0042000 + +08001cb0 : + * need to ensure that the SysTick time base is always set to 1 millisecond + * to have correct HAL operation. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_Init(void) +{ + 8001cb0: b580 push {r7, lr} + 8001cb2: b082 sub sp, #8 + 8001cb4: af00 add r7, sp, #0 + HAL_StatusTypeDef status = HAL_OK; + 8001cb6: 2300 movs r3, #0 + 8001cb8: 71fb strb r3, [r7, #7] +#endif /* PREFETCH_ENABLE */ + +#ifdef CORE_CM0PLUS +#else + /* Set Interrupt Group Priority */ + HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); + 8001cba: 2003 movs r0, #3 + 8001cbc: f000 fb96 bl 80023ec + + /* Update the SystemCoreClock global variable */ +#if defined(DUAL_CORE) && defined(CORE_CM0PLUS) + SystemCoreClock = HAL_RCC_GetHCLK2Freq(); +#else + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8001cc0: f002 fb26 bl 8004310 + 8001cc4: 4603 mov r3, r0 + 8001cc6: 4a09 ldr r2, [pc, #36] ; (8001cec ) + 8001cc8: 6013 str r3, [r2, #0] +#endif + + /* Use SysTick as time base source and configure 1ms tick (default clock after Reset is MSI) */ + if (HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK) + 8001cca: 200f movs r0, #15 + 8001ccc: f000 f810 bl 8001cf0 + 8001cd0: 4603 mov r3, r0 + 8001cd2: 2b00 cmp r3, #0 + 8001cd4: d002 beq.n 8001cdc + { + status = HAL_ERROR; + 8001cd6: 2301 movs r3, #1 + 8001cd8: 71fb strb r3, [r7, #7] + 8001cda: e001 b.n 8001ce0 + } + else + { + /* Init the low level hardware */ + HAL_MspInit(); + 8001cdc: f7fe fef5 bl 8000aca + } + + /* Return function status */ + return status; + 8001ce0: 79fb ldrb r3, [r7, #7] +} + 8001ce2: 4618 mov r0, r3 + 8001ce4: 3708 adds r7, #8 + 8001ce6: 46bd mov sp, r7 + 8001ce8: bd80 pop {r7, pc} + 8001cea: bf00 nop + 8001cec: 20000000 .word 0x20000000 + +08001cf0 : + * implementation in user file. + * @param TickPriority Tick interrupt priority. + * @retval HAL status + */ +__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) +{ + 8001cf0: b580 push {r7, lr} + 8001cf2: b084 sub sp, #16 + 8001cf4: af00 add r7, sp, #0 + 8001cf6: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8001cf8: 2300 movs r3, #0 + 8001cfa: 73fb strb r3, [r7, #15] + + /* Check uwTickFreq for MisraC 2012 (even if uwTickFreq is a enum type that don't take the value zero)*/ + if ((uint32_t)uwTickFreq != 0U) + 8001cfc: 4b17 ldr r3, [pc, #92] ; (8001d5c ) + 8001cfe: 781b ldrb r3, [r3, #0] + 8001d00: 2b00 cmp r3, #0 + 8001d02: d024 beq.n 8001d4e + { + /*Configure the SysTick to have interrupt in 1ms time basis*/ +#ifdef CORE_CM0PLUS + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLK2Freq() / (1000U / (uint32_t)uwTickFreq)) == 0U) +#else + if (HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / (1000U / (uint32_t)uwTickFreq)) == 0U) + 8001d04: f002 fb04 bl 8004310 + 8001d08: 4602 mov r2, r0 + 8001d0a: 4b14 ldr r3, [pc, #80] ; (8001d5c ) + 8001d0c: 781b ldrb r3, [r3, #0] + 8001d0e: 4619 mov r1, r3 + 8001d10: f44f 737a mov.w r3, #1000 ; 0x3e8 + 8001d14: fbb3 f3f1 udiv r3, r3, r1 + 8001d18: fbb2 f3f3 udiv r3, r2, r3 + 8001d1c: 4618 mov r0, r3 + 8001d1e: f000 fba6 bl 800246e + 8001d22: 4603 mov r3, r0 + 8001d24: 2b00 cmp r3, #0 + 8001d26: d10f bne.n 8001d48 +#endif + { + /* Configure the SysTick IRQ priority */ + if (TickPriority < (1UL << __NVIC_PRIO_BITS)) + 8001d28: 687b ldr r3, [r7, #4] + 8001d2a: 2b0f cmp r3, #15 + 8001d2c: d809 bhi.n 8001d42 + { + HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U); + 8001d2e: 2200 movs r2, #0 + 8001d30: 6879 ldr r1, [r7, #4] + 8001d32: f04f 30ff mov.w r0, #4294967295 + 8001d36: f000 fb64 bl 8002402 + uwTickPrio = TickPriority; + 8001d3a: 4a09 ldr r2, [pc, #36] ; (8001d60 ) + 8001d3c: 687b ldr r3, [r7, #4] + 8001d3e: 6013 str r3, [r2, #0] + 8001d40: e007 b.n 8001d52 + } + else + { + status = HAL_ERROR; + 8001d42: 2301 movs r3, #1 + 8001d44: 73fb strb r3, [r7, #15] + 8001d46: e004 b.n 8001d52 + } + } + else + { + status = HAL_ERROR; + 8001d48: 2301 movs r3, #1 + 8001d4a: 73fb strb r3, [r7, #15] + 8001d4c: e001 b.n 8001d52 + } + } + else + { + status = HAL_ERROR; + 8001d4e: 2301 movs r3, #1 + 8001d50: 73fb strb r3, [r7, #15] + } + + /* Return function status */ + return status; + 8001d52: 7bfb ldrb r3, [r7, #15] +} + 8001d54: 4618 mov r0, r3 + 8001d56: 3710 adds r7, #16 + 8001d58: 46bd mov sp, r7 + 8001d5a: bd80 pop {r7, pc} + 8001d5c: 20000008 .word 0x20000008 + 8001d60: 20000004 .word 0x20000004 + +08001d64 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_IncTick(void) +{ + 8001d64: b480 push {r7} + 8001d66: af00 add r7, sp, #0 + uwTick += (uint32_t)uwTickFreq; + 8001d68: 4b05 ldr r3, [pc, #20] ; (8001d80 ) + 8001d6a: 781b ldrb r3, [r3, #0] + 8001d6c: 461a mov r2, r3 + 8001d6e: 4b05 ldr r3, [pc, #20] ; (8001d84 ) + 8001d70: 681b ldr r3, [r3, #0] + 8001d72: 4413 add r3, r2 + 8001d74: 4a03 ldr r2, [pc, #12] ; (8001d84 ) + 8001d76: 6013 str r3, [r2, #0] +} + 8001d78: bf00 nop + 8001d7a: 46bd mov sp, r7 + 8001d7c: bc80 pop {r7} + 8001d7e: 4770 bx lr + 8001d80: 20000008 .word 0x20000008 + 8001d84: 200002f8 .word 0x200002f8 + +08001d88 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_SuspendTick(void) +{ + 8001d88: b480 push {r7} + 8001d8a: af00 add r7, sp, #0 + /* Disable SysTick Interrupt */ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 8001d8c: 4b04 ldr r3, [pc, #16] ; (8001da0 ) + 8001d8e: 681b ldr r3, [r3, #0] + 8001d90: 4a03 ldr r2, [pc, #12] ; (8001da0 ) + 8001d92: f023 0302 bic.w r3, r3, #2 + 8001d96: 6013 str r3, [r2, #0] +} + 8001d98: bf00 nop + 8001d9a: 46bd mov sp, r7 + 8001d9c: bc80 pop {r7} + 8001d9e: 4770 bx lr + 8001da0: e000e010 .word 0xe000e010 + +08001da4 : + * @note This function is declared as __weak to be overwritten in case of other + * implementations in user file. + * @retval None + */ +__weak void HAL_ResumeTick(void) +{ + 8001da4: b480 push {r7} + 8001da6: af00 add r7, sp, #0 + /* Enable SysTick Interrupt */ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); + 8001da8: 4b04 ldr r3, [pc, #16] ; (8001dbc ) + 8001daa: 681b ldr r3, [r3, #0] + 8001dac: 4a03 ldr r2, [pc, #12] ; (8001dbc ) + 8001dae: f043 0302 orr.w r3, r3, #2 + 8001db2: 6013 str r3, [r2, #0] +} + 8001db4: bf00 nop + 8001db6: 46bd mov sp, r7 + 8001db8: bc80 pop {r7} + 8001dba: 4770 bx lr + 8001dbc: e000e010 .word 0xe000e010 + +08001dc0 : +/** + * @brief Enable the CPU1 Debug Module during SLEEP mode + * @retval None + */ +void HAL_DBGMCU_EnableDBGSleepMode(void) +{ + 8001dc0: b580 push {r7, lr} + 8001dc2: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGSleepMode(); + 8001dc4: f7ff ff4a bl 8001c5c +} + 8001dc8: bf00 nop + 8001dca: bd80 pop {r7, pc} + +08001dcc : + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Stop mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStopMode(void) +{ + 8001dcc: b580 push {r7, lr} + 8001dce: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGStopMode(); + 8001dd0: f7ff ff52 bl 8001c78 +} + 8001dd4: bf00 nop + 8001dd6: bd80 pop {r7, pc} + +08001dd8 : + * @note This functionality does not influence CPU2 operation, CPU2 cannot be debugged + * in Standby mode even when this bit is enabled + * @retval None + */ +void HAL_DBGMCU_EnableDBGStandbyMode(void) +{ + 8001dd8: b580 push {r7, lr} + 8001dda: af00 add r7, sp, #0 + LL_DBGMCU_EnableDBGStandbyMode(); + 8001ddc: f7ff ff5a bl 8001c94 +} + 8001de0: bf00 nop + 8001de2: bd80 pop {r7, pc} + +08001de4 : + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY, + uint32_t SamplingTime) +{ + 8001de4: b480 push {r7} + 8001de6: b085 sub sp, #20 + 8001de8: af00 add r7, sp, #0 + 8001dea: 60f8 str r0, [r7, #12] + 8001dec: 60b9 str r1, [r7, #8] + 8001dee: 607a str r2, [r7, #4] + MODIFY_REG(ADCx->SMPR, + 8001df0: 68fb ldr r3, [r7, #12] + 8001df2: 695a ldr r2, [r3, #20] + 8001df4: 68bb ldr r3, [r7, #8] + 8001df6: f003 0304 and.w r3, r3, #4 + 8001dfa: 2107 movs r1, #7 + 8001dfc: fa01 f303 lsl.w r3, r1, r3 + 8001e00: 43db mvns r3, r3 + 8001e02: 401a ands r2, r3 + 8001e04: 68bb ldr r3, [r7, #8] + 8001e06: f003 0304 and.w r3, r3, #4 + 8001e0a: 6879 ldr r1, [r7, #4] + 8001e0c: fa01 f303 lsl.w r3, r1, r3 + 8001e10: 431a orrs r2, r3 + 8001e12: 68fb ldr r3, [r7, #12] + 8001e14: 615a str r2, [r3, #20] + ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK), + SamplingTime << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); +} + 8001e16: bf00 nop + 8001e18: 3714 adds r7, #20 + 8001e1a: 46bd mov sp, r7 + 8001e1c: bc80 pop {r7} + 8001e1e: 4770 bx lr + +08001e20 : + * @arg @ref LL_ADC_SAMPLINGTIME_39CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +{ + 8001e20: b480 push {r7} + 8001e22: b083 sub sp, #12 + 8001e24: af00 add r7, sp, #0 + 8001e26: 6078 str r0, [r7, #4] + 8001e28: 6039 str r1, [r7, #0] + return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) + 8001e2a: 687b ldr r3, [r7, #4] + 8001e2c: 695a ldr r2, [r3, #20] + 8001e2e: 683b ldr r3, [r7, #0] + 8001e30: f003 0304 and.w r3, r3, #4 + 8001e34: 2107 movs r1, #7 + 8001e36: fa01 f303 lsl.w r3, r1, r3 + 8001e3a: 401a ands r2, r3 + >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); + 8001e3c: 683b ldr r3, [r7, #0] + 8001e3e: f003 0304 and.w r3, r3, #4 + return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) + 8001e42: fa22 f303 lsr.w r3, r2, r3 +} + 8001e46: 4618 mov r0, r3 + 8001e48: 370c adds r7, #12 + 8001e4a: 46bd mov sp, r7 + 8001e4c: bc80 pop {r7} + 8001e4e: 4770 bx lr + +08001e50 : + * @rmtoll CR ADVREGEN LL_ADC_EnableInternalRegulator + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableInternalRegulator(ADC_TypeDef *ADCx) +{ + 8001e50: b480 push {r7} + 8001e52: b083 sub sp, #12 + 8001e54: af00 add r7, sp, #0 + 8001e56: 6078 str r0, [r7, #4] + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, + 8001e58: 687b ldr r3, [r7, #4] + 8001e5a: 689b ldr r3, [r3, #8] + 8001e5c: f023 4310 bic.w r3, r3, #2415919104 ; 0x90000000 + 8001e60: f023 0317 bic.w r3, r3, #23 + 8001e64: f043 5280 orr.w r2, r3, #268435456 ; 0x10000000 + 8001e68: 687b ldr r3, [r7, #4] + 8001e6a: 609a str r2, [r3, #8] + ADC_CR_BITS_PROPERTY_RS, + ADC_CR_ADVREGEN); +} + 8001e6c: bf00 nop + 8001e6e: 370c adds r7, #12 + 8001e70: 46bd mov sp, r7 + 8001e72: bc80 pop {r7} + 8001e74: 4770 bx lr + +08001e76 : + * @rmtoll CR ADVREGEN LL_ADC_IsInternalRegulatorEnabled + * @param ADCx ADC instance + * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +{ + 8001e76: b480 push {r7} + 8001e78: b083 sub sp, #12 + 8001e7a: af00 add r7, sp, #0 + 8001e7c: 6078 str r0, [r7, #4] + return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); + 8001e7e: 687b ldr r3, [r7, #4] + 8001e80: 689b ldr r3, [r3, #8] + 8001e82: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8001e86: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 8001e8a: d101 bne.n 8001e90 + 8001e8c: 2301 movs r3, #1 + 8001e8e: e000 b.n 8001e92 + 8001e90: 2300 movs r3, #0 +} + 8001e92: 4618 mov r0, r3 + 8001e94: 370c adds r7, #12 + 8001e96: 46bd mov sp, r7 + 8001e98: bc80 pop {r7} + 8001e9a: 4770 bx lr + +08001e9c : + * @rmtoll CR ADEN LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + 8001e9c: b480 push {r7} + 8001e9e: b083 sub sp, #12 + 8001ea0: af00 add r7, sp, #0 + 8001ea2: 6078 str r0, [r7, #4] + return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); + 8001ea4: 687b ldr r3, [r7, #4] + 8001ea6: 689b ldr r3, [r3, #8] + 8001ea8: f003 0301 and.w r3, r3, #1 + 8001eac: 2b01 cmp r3, #1 + 8001eae: d101 bne.n 8001eb4 + 8001eb0: 2301 movs r3, #1 + 8001eb2: e000 b.n 8001eb6 + 8001eb4: 2300 movs r3, #0 +} + 8001eb6: 4618 mov r0, r3 + 8001eb8: 370c adds r7, #12 + 8001eba: 46bd mov sp, r7 + 8001ebc: bc80 pop {r7} + 8001ebe: 4770 bx lr + +08001ec0 : + * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +{ + 8001ec0: b480 push {r7} + 8001ec2: b083 sub sp, #12 + 8001ec4: af00 add r7, sp, #0 + 8001ec6: 6078 str r0, [r7, #4] + return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); + 8001ec8: 687b ldr r3, [r7, #4] + 8001eca: 689b ldr r3, [r3, #8] + 8001ecc: f003 0304 and.w r3, r3, #4 + 8001ed0: 2b04 cmp r3, #4 + 8001ed2: d101 bne.n 8001ed8 + 8001ed4: 2301 movs r3, #1 + 8001ed6: e000 b.n 8001eda + 8001ed8: 2300 movs r3, #0 +} + 8001eda: 4618 mov r0, r3 + 8001edc: 370c adds r7, #12 + 8001ede: 46bd mov sp, r7 + 8001ee0: bc80 pop {r7} + 8001ee2: 4770 bx lr + +08001ee4 : + * of structure "ADC_InitTypeDef". + * @param hadc ADC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef *hadc) +{ + 8001ee4: b580 push {r7, lr} + 8001ee6: b088 sub sp, #32 + 8001ee8: af00 add r7, sp, #0 + 8001eea: 6078 str r0, [r7, #4] + HAL_StatusTypeDef tmp_hal_status = HAL_OK; + 8001eec: 2300 movs r3, #0 + 8001eee: 77fb strb r3, [r7, #31] + uint32_t tmpCFGR1 = 0UL; + 8001ef0: 2300 movs r3, #0 + 8001ef2: 61bb str r3, [r7, #24] + uint32_t tmpCFGR2 = 0UL; + 8001ef4: 2300 movs r3, #0 + 8001ef6: 617b str r3, [r7, #20] + uint32_t tmp_adc_reg_is_conversion_on_going; + __IO uint32_t wait_loop_index = 0UL; + 8001ef8: 2300 movs r3, #0 + 8001efa: 60fb str r3, [r7, #12] + + /* Check ADC handle */ + if (hadc == NULL) + 8001efc: 687b ldr r3, [r7, #4] + 8001efe: 2b00 cmp r3, #0 + 8001f00: d101 bne.n 8001f06 + { + return HAL_ERROR; + 8001f02: 2301 movs r3, #1 + 8001f04: e17e b.n 8002204 + assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); + assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); + } + assert_param(IS_ADC_TRIGGER_FREQ(hadc->Init.TriggerFrequencyMode)); + + if (hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) + 8001f06: 687b ldr r3, [r7, #4] + 8001f08: 691b ldr r3, [r3, #16] + 8001f0a: 2b00 cmp r3, #0 + /* continuous mode is disabled. */ + assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); + + /* Actions performed only if ADC is coming from state reset: */ + /* - Initialization of ADC MSP */ + if (hadc->State == HAL_ADC_STATE_RESET) + 8001f0c: 687b ldr r3, [r7, #4] + 8001f0e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001f10: 2b00 cmp r3, #0 + 8001f12: d109 bne.n 8001f28 + + /* Init the low level hardware */ + hadc->MspInitCallback(hadc); +#else + /* Init the low level hardware */ + HAL_ADC_MspInit(hadc); + 8001f14: 6878 ldr r0, [r7, #4] + 8001f16: f7fe fb87 bl 8000628 +#endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ + + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + 8001f1a: 687b ldr r3, [r7, #4] + 8001f1c: 2200 movs r2, #0 + 8001f1e: 65da str r2, [r3, #92] ; 0x5c + + /* Initialize Lock */ + hadc->Lock = HAL_UNLOCKED; + 8001f20: 687b ldr r3, [r7, #4] + 8001f22: 2200 movs r2, #0 + 8001f24: f883 2054 strb.w r2, [r3, #84] ; 0x54 + } + + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + 8001f28: 687b ldr r3, [r7, #4] + 8001f2a: 681b ldr r3, [r3, #0] + 8001f2c: 4618 mov r0, r3 + 8001f2e: f7ff ffa2 bl 8001e76 + 8001f32: 4603 mov r3, r0 + 8001f34: 2b00 cmp r3, #0 + 8001f36: d115 bne.n 8001f64 + { + /* Enable ADC internal voltage regulator */ + LL_ADC_EnableInternalRegulator(hadc->Instance); + 8001f38: 687b ldr r3, [r7, #4] + 8001f3a: 681b ldr r3, [r3, #0] + 8001f3c: 4618 mov r0, r3 + 8001f3e: f7ff ff87 bl 8001e50 + /* Delay for ADC stabilization time */ + /* Wait loop initialization and execution */ + /* Note: Variable divided by 2 to compensate partially */ + /* CPU processing cycles, scaling in us split to not */ + /* exceed 32 bits register capacity and handle low frequency. */ + wait_loop_index = ((LL_ADC_DELAY_INTERNAL_REGUL_STAB_US / 10UL) * ((SystemCoreClock / (100000UL * 2UL)) + 1UL)); + 8001f42: 4b9e ldr r3, [pc, #632] ; (80021bc ) + 8001f44: 681b ldr r3, [r3, #0] + 8001f46: 099b lsrs r3, r3, #6 + 8001f48: 4a9d ldr r2, [pc, #628] ; (80021c0 ) + 8001f4a: fba2 2303 umull r2, r3, r2, r3 + 8001f4e: 099b lsrs r3, r3, #6 + 8001f50: 3301 adds r3, #1 + 8001f52: 005b lsls r3, r3, #1 + 8001f54: 60fb str r3, [r7, #12] + while (wait_loop_index != 0UL) + 8001f56: e002 b.n 8001f5e + { + wait_loop_index--; + 8001f58: 68fb ldr r3, [r7, #12] + 8001f5a: 3b01 subs r3, #1 + 8001f5c: 60fb str r3, [r7, #12] + while (wait_loop_index != 0UL) + 8001f5e: 68fb ldr r3, [r7, #12] + 8001f60: 2b00 cmp r3, #0 + 8001f62: d1f9 bne.n 8001f58 + } + + /* Verification that ADC voltage regulator is correctly enabled, whether */ + /* or not ADC is coming from state reset (if any potential problem of */ + /* clocking, voltage regulator would not be enabled). */ + if (LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0UL) + 8001f64: 687b ldr r3, [r7, #4] + 8001f66: 681b ldr r3, [r3, #0] + 8001f68: 4618 mov r0, r3 + 8001f6a: f7ff ff84 bl 8001e76 + 8001f6e: 4603 mov r3, r0 + 8001f70: 2b00 cmp r3, #0 + 8001f72: d10d bne.n 8001f90 + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 8001f74: 687b ldr r3, [r7, #4] + 8001f76: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001f78: f043 0210 orr.w r2, r3, #16 + 8001f7c: 687b ldr r3, [r7, #4] + 8001f7e: 659a str r2, [r3, #88] ; 0x58 + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 8001f80: 687b ldr r3, [r7, #4] + 8001f82: 6ddb ldr r3, [r3, #92] ; 0x5c + 8001f84: f043 0201 orr.w r2, r3, #1 + 8001f88: 687b ldr r3, [r7, #4] + 8001f8a: 65da str r2, [r3, #92] ; 0x5c + + tmp_hal_status = HAL_ERROR; + 8001f8c: 2301 movs r3, #1 + 8001f8e: 77fb strb r3, [r7, #31] + + /* Configuration of ADC parameters if previous preliminary actions are */ + /* correctly completed and if there is no conversion on going on regular */ + /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ + /* called to update a parameter on the fly). */ + tmp_adc_reg_is_conversion_on_going = LL_ADC_REG_IsConversionOngoing(hadc->Instance); + 8001f90: 687b ldr r3, [r7, #4] + 8001f92: 681b ldr r3, [r3, #0] + 8001f94: 4618 mov r0, r3 + 8001f96: f7ff ff93 bl 8001ec0 + 8001f9a: 6138 str r0, [r7, #16] + + if (((hadc->State & HAL_ADC_STATE_ERROR_INTERNAL) == 0UL) + 8001f9c: 687b ldr r3, [r7, #4] + 8001f9e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001fa0: f003 0310 and.w r3, r3, #16 + 8001fa4: 2b00 cmp r3, #0 + 8001fa6: f040 8124 bne.w 80021f2 + && (tmp_adc_reg_is_conversion_on_going == 0UL) + 8001faa: 693b ldr r3, [r7, #16] + 8001fac: 2b00 cmp r3, #0 + 8001fae: f040 8120 bne.w 80021f2 + ) + { + /* Set ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 8001fb2: 687b ldr r3, [r7, #4] + 8001fb4: 6d9b ldr r3, [r3, #88] ; 0x58 + 8001fb6: f423 7381 bic.w r3, r3, #258 ; 0x102 + 8001fba: f043 0202 orr.w r2, r3, #2 + 8001fbe: 687b ldr r3, [r7, #4] + 8001fc0: 659a str r2, [r3, #88] ; 0x58 + /* - DMA continuous request */ + /* - Trigger frequency mode */ + /* Note: If low power mode AutoPowerOff is enabled, ADC enable */ + /* and disable phases are performed automatically by hardware */ + /* (in this case, flag ADC_FLAG_RDY is not set). */ + if (LL_ADC_IsEnabled(hadc->Instance) == 0UL) + 8001fc2: 687b ldr r3, [r7, #4] + 8001fc4: 681b ldr r3, [r3, #0] + 8001fc6: 4618 mov r0, r3 + 8001fc8: f7ff ff68 bl 8001e9c + 8001fcc: 4603 mov r3, r0 + 8001fce: 2b00 cmp r3, #0 + 8001fd0: f040 80a7 bne.w 8002122 + /* without needing to reconfigure all other ADC groups/channels */ + /* parameters): */ + /* - internal measurement paths (VrefInt, ...) */ + /* (set into HAL_ADC_ConfigChannel() ) */ + + tmpCFGR1 |= (hadc->Init.Resolution | + 8001fd4: 687b ldr r3, [r7, #4] + 8001fd6: 689a ldr r2, [r3, #8] + ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + 8001fd8: 687b ldr r3, [r7, #4] + 8001fda: 7e1b ldrb r3, [r3, #24] + 8001fdc: 039b lsls r3, r3, #14 + tmpCFGR1 |= (hadc->Init.Resolution | + 8001fde: 431a orrs r2, r3 + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + 8001fe0: 687b ldr r3, [r7, #4] + 8001fe2: 7e5b ldrb r3, [r3, #25] + 8001fe4: 03db lsls r3, r3, #15 + ADC_CFGR1_AUTOWAIT((uint32_t)hadc->Init.LowPowerAutoWait) | + 8001fe6: 431a orrs r2, r3 + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + 8001fe8: 687b ldr r3, [r7, #4] + 8001fea: 7e9b ldrb r3, [r3, #26] + 8001fec: 035b lsls r3, r3, #13 + ADC_CFGR1_AUTOOFF((uint32_t)hadc->Init.LowPowerAutoPowerOff) | + 8001fee: 4313 orrs r3, r2 + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + 8001ff0: 687a ldr r2, [r7, #4] + 8001ff2: 6b12 ldr r2, [r2, #48] ; 0x30 + 8001ff4: 2a00 cmp r2, #0 + 8001ff6: d002 beq.n 8001ffe + 8001ff8: f44f 5280 mov.w r2, #4096 ; 0x1000 + 8001ffc: e000 b.n 8002000 + 8001ffe: 2200 movs r2, #0 + ADC_CFGR1_CONTINUOUS((uint32_t)hadc->Init.ContinuousConvMode) | + 8002000: 431a orrs r2, r3 + hadc->Init.DataAlign | + 8002002: 687b ldr r3, [r7, #4] + 8002004: 68db ldr r3, [r3, #12] + ADC_CFGR1_OVERRUN(hadc->Init.Overrun) | + 8002006: 431a orrs r2, r3 + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + 8002008: 687b ldr r3, [r7, #4] + 800200a: 691b ldr r3, [r3, #16] + 800200c: 2b00 cmp r3, #0 + 800200e: da04 bge.n 800201a + 8002010: 687b ldr r3, [r7, #4] + 8002012: 691b ldr r3, [r3, #16] + 8002014: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8002018: e001 b.n 800201e + 800201a: f44f 1300 mov.w r3, #2097152 ; 0x200000 + hadc->Init.DataAlign | + 800201e: 431a orrs r2, r3 + ADC_CFGR1_DMACONTREQ((uint32_t)hadc->Init.DMAContinuousRequests)); + 8002020: 687b ldr r3, [r7, #4] + 8002022: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8002026: 005b lsls r3, r3, #1 + ADC_SCAN_SEQ_MODE(hadc->Init.ScanConvMode) | + 8002028: 4313 orrs r3, r2 + tmpCFGR1 |= (hadc->Init.Resolution | + 800202a: 69ba ldr r2, [r7, #24] + 800202c: 4313 orrs r3, r2 + 800202e: 61bb str r3, [r7, #24] + + /* Update setting of discontinuous mode only if continuous mode is disabled */ + if (hadc->Init.DiscontinuousConvMode == ENABLE) + 8002030: 687b ldr r3, [r7, #4] + 8002032: f893 3020 ldrb.w r3, [r3, #32] + 8002036: 2b01 cmp r3, #1 + 8002038: d114 bne.n 8002064 + { + if (hadc->Init.ContinuousConvMode == DISABLE) + 800203a: 687b ldr r3, [r7, #4] + 800203c: 7e9b ldrb r3, [r3, #26] + 800203e: 2b00 cmp r3, #0 + 8002040: d104 bne.n 800204c + { + /* Enable the selected ADC group regular discontinuous mode */ + tmpCFGR1 |= ADC_CFGR1_DISCEN; + 8002042: 69bb ldr r3, [r7, #24] + 8002044: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 8002048: 61bb str r3, [r7, #24] + 800204a: e00b b.n 8002064 + /* ADC regular group discontinuous was intended to be enabled, */ + /* but ADC regular group modes continuous and sequencer discontinuous */ + /* cannot be enabled simultaneously. */ + + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); + 800204c: 687b ldr r3, [r7, #4] + 800204e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8002050: f043 0220 orr.w r2, r3, #32 + 8002054: 687b ldr r3, [r7, #4] + 8002056: 659a str r2, [r3, #88] ; 0x58 + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 8002058: 687b ldr r3, [r7, #4] + 800205a: 6ddb ldr r3, [r3, #92] ; 0x5c + 800205c: f043 0201 orr.w r2, r3, #1 + 8002060: 687b ldr r3, [r7, #4] + 8002062: 65da str r2, [r3, #92] ; 0x5c + /* Enable external trigger if trigger selection is different of software */ + /* start. */ + /* Note: This configuration keeps the hardware feature of parameter */ + /* ExternalTrigConvEdge "trigger edge none" equivalent to */ + /* software start. */ + if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) + 8002064: 687b ldr r3, [r7, #4] + 8002066: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002068: 2b00 cmp r3, #0 + 800206a: d009 beq.n 8002080 + { + tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + 800206c: 687b ldr r3, [r7, #4] + 800206e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8002070: f403 72e0 and.w r2, r3, #448 ; 0x1c0 + hadc->Init.ExternalTrigConvEdge); + 8002074: 687b ldr r3, [r7, #4] + 8002076: 6a9b ldr r3, [r3, #40] ; 0x28 + tmpCFGR1 |= ((hadc->Init.ExternalTrigConv & ADC_CFGR1_EXTSEL) | + 8002078: 4313 orrs r3, r2 + 800207a: 69ba ldr r2, [r7, #24] + 800207c: 4313 orrs r3, r2 + 800207e: 61bb str r3, [r7, #24] + } + + /* Update ADC configuration register with previous settings */ + MODIFY_REG(hadc->Instance->CFGR1, + 8002080: 687b ldr r3, [r7, #4] + 8002082: 681b ldr r3, [r3, #0] + 8002084: 68db ldr r3, [r3, #12] + 8002086: f423 33fe bic.w r3, r3, #130048 ; 0x1fc00 + 800208a: f423 73ff bic.w r3, r3, #510 ; 0x1fe + 800208e: 687a ldr r2, [r7, #4] + 8002090: 6812 ldr r2, [r2, #0] + 8002092: 69b9 ldr r1, [r7, #24] + 8002094: 430b orrs r3, r1 + 8002096: 60d3 str r3, [r2, #12] + ADC_CFGR1_ALIGN | + ADC_CFGR1_SCANDIR | + ADC_CFGR1_DMACFG, + tmpCFGR1); + + tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + 8002098: 687b ldr r3, [r7, #4] + 800209a: 685b ldr r3, [r3, #4] + 800209c: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000 + hadc->Init.TriggerFrequencyMode + 80020a0: 687b ldr r3, [r7, #4] + 80020a2: 6cdb ldr r3, [r3, #76] ; 0x4c + tmpCFGR2 |= ((hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + 80020a4: 4313 orrs r3, r2 + 80020a6: 697a ldr r2, [r7, #20] + 80020a8: 4313 orrs r3, r2 + 80020aa: 617b str r3, [r7, #20] + ); + + if (hadc->Init.OversamplingMode == ENABLE) + 80020ac: 687b ldr r3, [r7, #4] + 80020ae: f893 303c ldrb.w r3, [r3, #60] ; 0x3c + 80020b2: 2b01 cmp r3, #1 + 80020b4: d111 bne.n 80020da + { + tmpCFGR2 |= (ADC_CFGR2_OVSE | + (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + 80020b6: 687b ldr r3, [r7, #4] + 80020b8: 685b ldr r3, [r3, #4] + 80020ba: f003 4240 and.w r2, r3, #3221225472 ; 0xc0000000 + hadc->Init.Oversampling.Ratio | + 80020be: 687b ldr r3, [r7, #4] + 80020c0: 6c1b ldr r3, [r3, #64] ; 0x40 + (hadc->Init.ClockPrescaler & ADC_CFGR2_CKMODE) | + 80020c2: 431a orrs r2, r3 + hadc->Init.Oversampling.RightBitShift | + 80020c4: 687b ldr r3, [r7, #4] + 80020c6: 6c5b ldr r3, [r3, #68] ; 0x44 + hadc->Init.Oversampling.Ratio | + 80020c8: 431a orrs r2, r3 + hadc->Init.Oversampling.TriggeredMode + 80020ca: 687b ldr r3, [r7, #4] + 80020cc: 6c9b ldr r3, [r3, #72] ; 0x48 + hadc->Init.Oversampling.RightBitShift | + 80020ce: 431a orrs r2, r3 + tmpCFGR2 |= (ADC_CFGR2_OVSE | + 80020d0: 697b ldr r3, [r7, #20] + 80020d2: 4313 orrs r3, r2 + 80020d4: f043 0301 orr.w r3, r3, #1 + 80020d8: 617b str r3, [r7, #20] + ); + } + + MODIFY_REG(hadc->Instance->CFGR2, + 80020da: 687b ldr r3, [r7, #4] + 80020dc: 681b ldr r3, [r3, #0] + 80020de: 691a ldr r2, [r3, #16] + 80020e0: 4b38 ldr r3, [pc, #224] ; (80021c4 ) + 80020e2: 4013 ands r3, r2 + 80020e4: 687a ldr r2, [r7, #4] + 80020e6: 6812 ldr r2, [r2, #0] + 80020e8: 6979 ldr r1, [r7, #20] + 80020ea: 430b orrs r3, r1 + 80020ec: 6113 str r3, [r2, #16] + ADC_CFGR2_TOVS, + tmpCFGR2); + + /* Configuration of ADC clock mode: asynchronous clock source */ + /* with selectable prescaler. */ + if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && + 80020ee: 687b ldr r3, [r7, #4] + 80020f0: 685b ldr r3, [r3, #4] + 80020f2: f1b3 4f40 cmp.w r3, #3221225472 ; 0xc0000000 + 80020f6: d014 beq.n 8002122 + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && + 80020f8: 687b ldr r3, [r7, #4] + 80020fa: 685b ldr r3, [r3, #4] + if (((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV1) && + 80020fc: f1b3 4f80 cmp.w r3, #1073741824 ; 0x40000000 + 8002100: d00f beq.n 8002122 + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV4)) + 8002102: 687b ldr r3, [r7, #4] + 8002104: 685b ldr r3, [r3, #4] + ((hadc->Init.ClockPrescaler) != ADC_CLOCK_SYNC_PCLK_DIV2) && + 8002106: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + 800210a: d00a beq.n 8002122 + { + MODIFY_REG(ADC_COMMON->CCR, + 800210c: 4b2e ldr r3, [pc, #184] ; (80021c8 ) + 800210e: 681b ldr r3, [r3, #0] + 8002110: f423 1270 bic.w r2, r3, #3932160 ; 0x3c0000 + 8002114: 687b ldr r3, [r7, #4] + 8002116: 685b ldr r3, [r3, #4] + 8002118: f403 1370 and.w r3, r3, #3932160 ; 0x3c0000 + 800211c: 492a ldr r1, [pc, #168] ; (80021c8 ) + 800211e: 4313 orrs r3, r2 + 8002120: 600b str r3, [r1, #0] + hadc->Init.ClockPrescaler & ADC_CCR_PRESC); + } + } + + /* Channel sampling time configuration */ + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1, hadc->Init.SamplingTimeCommon1); + 8002122: 687b ldr r3, [r7, #4] + 8002124: 6818 ldr r0, [r3, #0] + 8002126: 687b ldr r3, [r7, #4] + 8002128: 6b5b ldr r3, [r3, #52] ; 0x34 + 800212a: 461a mov r2, r3 + 800212c: 2100 movs r1, #0 + 800212e: f7ff fe59 bl 8001de4 + LL_ADC_SetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_2, hadc->Init.SamplingTimeCommon2); + 8002132: 687b ldr r3, [r7, #4] + 8002134: 6818 ldr r0, [r3, #0] + 8002136: 687b ldr r3, [r7, #4] + 8002138: 6b9b ldr r3, [r3, #56] ; 0x38 + 800213a: 461a mov r2, r3 + 800213c: 4923 ldr r1, [pc, #140] ; (80021cc ) + 800213e: f7ff fe51 bl 8001de4 + /* emulated by software for alignment over all STM32 devices. */ + /* - if scan mode is enabled, regular channels sequence length is set to */ + /* parameter "NbrOfConversion". */ + /* Channels must be configured into each rank using function */ + /* "HAL_ADC_ConfigChannel()". */ + if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) + 8002142: 687b ldr r3, [r7, #4] + 8002144: 691b ldr r3, [r3, #16] + 8002146: 2b00 cmp r3, #0 + 8002148: d108 bne.n 800215c + { + /* Set sequencer scan length by clearing ranks above rank 1 */ + /* and do not modify rank 1 value. */ + SET_BIT(hadc->Instance->CHSELR, + 800214a: 687b ldr r3, [r7, #4] + 800214c: 681b ldr r3, [r3, #0] + 800214e: 6a9a ldr r2, [r3, #40] ; 0x28 + 8002150: 687b ldr r3, [r7, #4] + 8002152: 681b ldr r3, [r3, #0] + 8002154: f062 020f orn r2, r2, #15 + 8002158: 629a str r2, [r3, #40] ; 0x28 + 800215a: e017 b.n 800218c + ADC_CHSELR_SQ2_TO_SQ8); + } + else if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) + 800215c: 687b ldr r3, [r7, #4] + 800215e: 691b ldr r3, [r3, #16] + 8002160: f5b3 1f00 cmp.w r3, #2097152 ; 0x200000 + 8002164: d112 bne.n 800218c + /* therefore after the first call of "HAL_ADC_Init()", */ + /* each rank corresponding to parameter "NbrOfConversion" */ + /* must be set using "HAL_ADC_ConfigChannel()". */ + /* - Set sequencer scan length by clearing ranks above maximum rank */ + /* and do not modify other ranks value. */ + MODIFY_REG(hadc->Instance->CHSELR, + 8002166: 687b ldr r3, [r7, #4] + 8002168: 681b ldr r3, [r3, #0] + 800216a: 6a9b ldr r3, [r3, #40] ; 0x28 + 800216c: 687b ldr r3, [r7, #4] + 800216e: 69db ldr r3, [r3, #28] + 8002170: 3b01 subs r3, #1 + 8002172: 009b lsls r3, r3, #2 + 8002174: f003 031c and.w r3, r3, #28 + 8002178: f06f 020f mvn.w r2, #15 + 800217c: fa02 f103 lsl.w r1, r2, r3 + 8002180: 687b ldr r3, [r7, #4] + 8002182: 6e1a ldr r2, [r3, #96] ; 0x60 + 8002184: 687b ldr r3, [r7, #4] + 8002186: 681b ldr r3, [r3, #0] + 8002188: 430a orrs r2, r1 + 800218a: 629a str r2, [r3, #40] ; 0x28 + ); + } + + /* Check back that ADC registers have effectively been configured to */ + /* ensure of no potential problem of ADC core peripheral clocking. */ + if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + 800218c: 687b ldr r3, [r7, #4] + 800218e: 681b ldr r3, [r3, #0] + 8002190: 2100 movs r1, #0 + 8002192: 4618 mov r0, r3 + 8002194: f7ff fe44 bl 8001e20 + 8002198: 4602 mov r2, r0 + == hadc->Init.SamplingTimeCommon1) + 800219a: 687b ldr r3, [r7, #4] + 800219c: 6b5b ldr r3, [r3, #52] ; 0x34 + if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + 800219e: 429a cmp r2, r3 + 80021a0: d116 bne.n 80021d0 + { + /* Set ADC error code to none */ + ADC_CLEAR_ERRORCODE(hadc); + 80021a2: 687b ldr r3, [r7, #4] + 80021a4: 2200 movs r2, #0 + 80021a6: 65da str r2, [r3, #92] ; 0x5c + + /* Set the ADC state */ + ADC_STATE_CLR_SET(hadc->State, + 80021a8: 687b ldr r3, [r7, #4] + 80021aa: 6d9b ldr r3, [r3, #88] ; 0x58 + 80021ac: f023 0303 bic.w r3, r3, #3 + 80021b0: f043 0201 orr.w r2, r3, #1 + 80021b4: 687b ldr r3, [r7, #4] + 80021b6: 659a str r2, [r3, #88] ; 0x58 + if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + 80021b8: e023 b.n 8002202 + 80021ba: bf00 nop + 80021bc: 20000000 .word 0x20000000 + 80021c0: 053e2d63 .word 0x053e2d63 + 80021c4: 1ffffc02 .word 0x1ffffc02 + 80021c8: 40012708 .word 0x40012708 + 80021cc: 03ffff04 .word 0x03ffff04 + HAL_ADC_STATE_READY); + } + else + { + /* Update ADC state machine to error */ + ADC_STATE_CLR_SET(hadc->State, + 80021d0: 687b ldr r3, [r7, #4] + 80021d2: 6d9b ldr r3, [r3, #88] ; 0x58 + 80021d4: f023 0312 bic.w r3, r3, #18 + 80021d8: f043 0210 orr.w r2, r3, #16 + 80021dc: 687b ldr r3, [r7, #4] + 80021de: 659a str r2, [r3, #88] ; 0x58 + HAL_ADC_STATE_BUSY_INTERNAL, + HAL_ADC_STATE_ERROR_INTERNAL); + + /* Set ADC error code to ADC peripheral internal error */ + SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); + 80021e0: 687b ldr r3, [r7, #4] + 80021e2: 6ddb ldr r3, [r3, #92] ; 0x5c + 80021e4: f043 0201 orr.w r2, r3, #1 + 80021e8: 687b ldr r3, [r7, #4] + 80021ea: 65da str r2, [r3, #92] ; 0x5c + + tmp_hal_status = HAL_ERROR; + 80021ec: 2301 movs r3, #1 + 80021ee: 77fb strb r3, [r7, #31] + if(LL_ADC_GetSamplingTimeCommonChannels(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_1) + 80021f0: e007 b.n 8002202 + + } + else + { + /* Update ADC state machine to error */ + SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); + 80021f2: 687b ldr r3, [r7, #4] + 80021f4: 6d9b ldr r3, [r3, #88] ; 0x58 + 80021f6: f043 0210 orr.w r2, r3, #16 + 80021fa: 687b ldr r3, [r7, #4] + 80021fc: 659a str r2, [r3, #88] ; 0x58 + + tmp_hal_status = HAL_ERROR; + 80021fe: 2301 movs r3, #1 + 8002200: 77fb strb r3, [r7, #31] + } + + return tmp_hal_status; + 8002202: 7ffb ldrb r3, [r7, #31] +} + 8002204: 4618 mov r0, r3 + 8002206: 3720 adds r7, #32 + 8002208: 46bd mov sp, r7 + 800220a: bd80 pop {r7, pc} + +0800220c <__NVIC_SetPriorityGrouping>: + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 800220c: b480 push {r7} + 800220e: b085 sub sp, #20 + 8002210: af00 add r7, sp, #0 + 8002212: 6078 str r0, [r7, #4] + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8002214: 687b ldr r3, [r7, #4] + 8002216: f003 0307 and.w r3, r3, #7 + 800221a: 60fb str r3, [r7, #12] + + reg_value = SCB->AIRCR; /* read old register configuration */ + 800221c: 4b0c ldr r3, [pc, #48] ; (8002250 <__NVIC_SetPriorityGrouping+0x44>) + 800221e: 68db ldr r3, [r3, #12] + 8002220: 60bb str r3, [r7, #8] + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + 8002222: 68ba ldr r2, [r7, #8] + 8002224: f64f 03ff movw r3, #63743 ; 0xf8ff + 8002228: 4013 ands r3, r2 + 800222a: 60bb str r3, [r7, #8] + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + 800222c: 68fb ldr r3, [r7, #12] + 800222e: 021a lsls r2, r3, #8 + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + 8002230: 68bb ldr r3, [r7, #8] + 8002232: 4313 orrs r3, r2 + reg_value = (reg_value | + 8002234: f043 63bf orr.w r3, r3, #100139008 ; 0x5f80000 + 8002238: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 800223c: 60bb str r3, [r7, #8] + SCB->AIRCR = reg_value; + 800223e: 4a04 ldr r2, [pc, #16] ; (8002250 <__NVIC_SetPriorityGrouping+0x44>) + 8002240: 68bb ldr r3, [r7, #8] + 8002242: 60d3 str r3, [r2, #12] +} + 8002244: bf00 nop + 8002246: 3714 adds r7, #20 + 8002248: 46bd mov sp, r7 + 800224a: bc80 pop {r7} + 800224c: 4770 bx lr + 800224e: bf00 nop + 8002250: e000ed00 .word 0xe000ed00 + +08002254 <__NVIC_GetPriorityGrouping>: + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + 8002254: b480 push {r7} + 8002256: af00 add r7, sp, #0 + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); + 8002258: 4b04 ldr r3, [pc, #16] ; (800226c <__NVIC_GetPriorityGrouping+0x18>) + 800225a: 68db ldr r3, [r3, #12] + 800225c: 0a1b lsrs r3, r3, #8 + 800225e: f003 0307 and.w r3, r3, #7 +} + 8002262: 4618 mov r0, r3 + 8002264: 46bd mov sp, r7 + 8002266: bc80 pop {r7} + 8002268: 4770 bx lr + 800226a: bf00 nop + 800226c: e000ed00 .word 0xe000ed00 + +08002270 <__NVIC_EnableIRQ>: + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8002270: b480 push {r7} + 8002272: b083 sub sp, #12 + 8002274: af00 add r7, sp, #0 + 8002276: 4603 mov r3, r0 + 8002278: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 800227a: f997 3007 ldrsb.w r3, [r7, #7] + 800227e: 2b00 cmp r3, #0 + 8002280: db0b blt.n 800229a <__NVIC_EnableIRQ+0x2a> + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 8002282: 79fb ldrb r3, [r7, #7] + 8002284: f003 021f and.w r2, r3, #31 + 8002288: 4906 ldr r1, [pc, #24] ; (80022a4 <__NVIC_EnableIRQ+0x34>) + 800228a: f997 3007 ldrsb.w r3, [r7, #7] + 800228e: 095b lsrs r3, r3, #5 + 8002290: 2001 movs r0, #1 + 8002292: fa00 f202 lsl.w r2, r0, r2 + 8002296: f841 2023 str.w r2, [r1, r3, lsl #2] + __COMPILER_BARRIER(); + } +} + 800229a: bf00 nop + 800229c: 370c adds r7, #12 + 800229e: 46bd mov sp, r7 + 80022a0: bc80 pop {r7} + 80022a2: 4770 bx lr + 80022a4: e000e100 .word 0xe000e100 + +080022a8 <__NVIC_DisableIRQ>: + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 80022a8: b480 push {r7} + 80022aa: b083 sub sp, #12 + 80022ac: af00 add r7, sp, #0 + 80022ae: 4603 mov r3, r0 + 80022b0: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80022b2: f997 3007 ldrsb.w r3, [r7, #7] + 80022b6: 2b00 cmp r3, #0 + 80022b8: db12 blt.n 80022e0 <__NVIC_DisableIRQ+0x38> + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + 80022ba: 79fb ldrb r3, [r7, #7] + 80022bc: f003 021f and.w r2, r3, #31 + 80022c0: 490a ldr r1, [pc, #40] ; (80022ec <__NVIC_DisableIRQ+0x44>) + 80022c2: f997 3007 ldrsb.w r3, [r7, #7] + 80022c6: 095b lsrs r3, r3, #5 + 80022c8: 2001 movs r0, #1 + 80022ca: fa00 f202 lsl.w r2, r0, r2 + 80022ce: 3320 adds r3, #32 + 80022d0: f841 2023 str.w r2, [r1, r3, lsl #2] + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); + 80022d4: f3bf 8f4f dsb sy +} + 80022d8: bf00 nop + __ASM volatile ("isb 0xF":::"memory"); + 80022da: f3bf 8f6f isb sy +} + 80022de: bf00 nop + __DSB(); + __ISB(); + } +} + 80022e0: bf00 nop + 80022e2: 370c adds r7, #12 + 80022e4: 46bd mov sp, r7 + 80022e6: bc80 pop {r7} + 80022e8: 4770 bx lr + 80022ea: bf00 nop + 80022ec: e000e100 .word 0xe000e100 + +080022f0 <__NVIC_SetPriority>: + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + 80022f0: b480 push {r7} + 80022f2: b083 sub sp, #12 + 80022f4: af00 add r7, sp, #0 + 80022f6: 4603 mov r3, r0 + 80022f8: 6039 str r1, [r7, #0] + 80022fa: 71fb strb r3, [r7, #7] + if ((int32_t)(IRQn) >= 0) + 80022fc: f997 3007 ldrsb.w r3, [r7, #7] + 8002300: 2b00 cmp r3, #0 + 8002302: db0a blt.n 800231a <__NVIC_SetPriority+0x2a> + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 8002304: 683b ldr r3, [r7, #0] + 8002306: b2da uxtb r2, r3 + 8002308: 490c ldr r1, [pc, #48] ; (800233c <__NVIC_SetPriority+0x4c>) + 800230a: f997 3007 ldrsb.w r3, [r7, #7] + 800230e: 0112 lsls r2, r2, #4 + 8002310: b2d2 uxtb r2, r2 + 8002312: 440b add r3, r1 + 8002314: f883 2300 strb.w r2, [r3, #768] ; 0x300 + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + 8002318: e00a b.n 8002330 <__NVIC_SetPriority+0x40> + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + 800231a: 683b ldr r3, [r7, #0] + 800231c: b2da uxtb r2, r3 + 800231e: 4908 ldr r1, [pc, #32] ; (8002340 <__NVIC_SetPriority+0x50>) + 8002320: 79fb ldrb r3, [r7, #7] + 8002322: f003 030f and.w r3, r3, #15 + 8002326: 3b04 subs r3, #4 + 8002328: 0112 lsls r2, r2, #4 + 800232a: b2d2 uxtb r2, r2 + 800232c: 440b add r3, r1 + 800232e: 761a strb r2, [r3, #24] +} + 8002330: bf00 nop + 8002332: 370c adds r7, #12 + 8002334: 46bd mov sp, r7 + 8002336: bc80 pop {r7} + 8002338: 4770 bx lr + 800233a: bf00 nop + 800233c: e000e100 .word 0xe000e100 + 8002340: e000ed00 .word 0xe000ed00 + +08002344 : + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8002344: b480 push {r7} + 8002346: b089 sub sp, #36 ; 0x24 + 8002348: af00 add r7, sp, #0 + 800234a: 60f8 str r0, [r7, #12] + 800234c: 60b9 str r1, [r7, #8] + 800234e: 607a str r2, [r7, #4] + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + 8002350: 68fb ldr r3, [r7, #12] + 8002352: f003 0307 and.w r3, r3, #7 + 8002356: 61fb str r3, [r7, #28] + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + 8002358: 69fb ldr r3, [r7, #28] + 800235a: f1c3 0307 rsb r3, r3, #7 + 800235e: 2b04 cmp r3, #4 + 8002360: bf28 it cs + 8002362: 2304 movcs r3, #4 + 8002364: 61bb str r3, [r7, #24] + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + 8002366: 69fb ldr r3, [r7, #28] + 8002368: 3304 adds r3, #4 + 800236a: 2b06 cmp r3, #6 + 800236c: d902 bls.n 8002374 + 800236e: 69fb ldr r3, [r7, #28] + 8002370: 3b03 subs r3, #3 + 8002372: e000 b.n 8002376 + 8002374: 2300 movs r3, #0 + 8002376: 617b str r3, [r7, #20] + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 8002378: f04f 32ff mov.w r2, #4294967295 + 800237c: 69bb ldr r3, [r7, #24] + 800237e: fa02 f303 lsl.w r3, r2, r3 + 8002382: 43da mvns r2, r3 + 8002384: 68bb ldr r3, [r7, #8] + 8002386: 401a ands r2, r3 + 8002388: 697b ldr r3, [r7, #20] + 800238a: 409a lsls r2, r3 + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + 800238c: f04f 31ff mov.w r1, #4294967295 + 8002390: 697b ldr r3, [r7, #20] + 8002392: fa01 f303 lsl.w r3, r1, r3 + 8002396: 43d9 mvns r1, r3 + 8002398: 687b ldr r3, [r7, #4] + 800239a: 400b ands r3, r1 + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + 800239c: 4313 orrs r3, r2 + ); +} + 800239e: 4618 mov r0, r3 + 80023a0: 3724 adds r7, #36 ; 0x24 + 80023a2: 46bd mov sp, r7 + 80023a4: bc80 pop {r7} + 80023a6: 4770 bx lr + +080023a8 : + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + 80023a8: b580 push {r7, lr} + 80023aa: b082 sub sp, #8 + 80023ac: af00 add r7, sp, #0 + 80023ae: 6078 str r0, [r7, #4] + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + 80023b0: 687b ldr r3, [r7, #4] + 80023b2: 3b01 subs r3, #1 + 80023b4: f1b3 7f80 cmp.w r3, #16777216 ; 0x1000000 + 80023b8: d301 bcc.n 80023be + { + return (1UL); /* Reload value impossible */ + 80023ba: 2301 movs r3, #1 + 80023bc: e00f b.n 80023de + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + 80023be: 4a0a ldr r2, [pc, #40] ; (80023e8 ) + 80023c0: 687b ldr r3, [r7, #4] + 80023c2: 3b01 subs r3, #1 + 80023c4: 6053 str r3, [r2, #4] + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + 80023c6: 210f movs r1, #15 + 80023c8: f04f 30ff mov.w r0, #4294967295 + 80023cc: f7ff ff90 bl 80022f0 <__NVIC_SetPriority> + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + 80023d0: 4b05 ldr r3, [pc, #20] ; (80023e8 ) + 80023d2: 2200 movs r2, #0 + 80023d4: 609a str r2, [r3, #8] + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + 80023d6: 4b04 ldr r3, [pc, #16] ; (80023e8 ) + 80023d8: 2207 movs r2, #7 + 80023da: 601a str r2, [r3, #0] + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ + 80023dc: 2300 movs r3, #0 +} + 80023de: 4618 mov r0, r3 + 80023e0: 3708 adds r7, #8 + 80023e2: 46bd mov sp, r7 + 80023e4: bd80 pop {r7, pc} + 80023e6: bf00 nop + 80023e8: e000e010 .word 0xe000e010 + +080023ec : + * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. + * The pending IRQ priority will be managed only by the subpriority. + * @retval None + */ +void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + 80023ec: b580 push {r7, lr} + 80023ee: b082 sub sp, #8 + 80023f0: af00 add r7, sp, #0 + 80023f2: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); + + /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ + NVIC_SetPriorityGrouping(PriorityGroup); + 80023f4: 6878 ldr r0, [r7, #4] + 80023f6: f7ff ff09 bl 800220c <__NVIC_SetPriorityGrouping> +} + 80023fa: bf00 nop + 80023fc: 3708 adds r7, #8 + 80023fe: 46bd mov sp, r7 + 8002400: bd80 pop {r7, pc} + +08002402 : + * This parameter can be a value between 0 and 15 + * A lower priority value indicates a higher priority. + * @retval None + */ +void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) +{ + 8002402: b580 push {r7, lr} + 8002404: b086 sub sp, #24 + 8002406: af00 add r7, sp, #0 + 8002408: 4603 mov r3, r0 + 800240a: 60b9 str r1, [r7, #8] + 800240c: 607a str r2, [r7, #4] + 800240e: 73fb strb r3, [r7, #15] + + /* Check the parameters */ + assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); + assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); + + prioritygroup = NVIC_GetPriorityGrouping(); + 8002410: f7ff ff20 bl 8002254 <__NVIC_GetPriorityGrouping> + 8002414: 6178 str r0, [r7, #20] + + NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); + 8002416: 687a ldr r2, [r7, #4] + 8002418: 68b9 ldr r1, [r7, #8] + 800241a: 6978 ldr r0, [r7, #20] + 800241c: f7ff ff92 bl 8002344 + 8002420: 4602 mov r2, r0 + 8002422: f997 300f ldrsb.w r3, [r7, #15] + 8002426: 4611 mov r1, r2 + 8002428: 4618 mov r0, r3 + 800242a: f7ff ff61 bl 80022f0 <__NVIC_SetPriority> +} + 800242e: bf00 nop + 8002430: 3718 adds r7, #24 + 8002432: 46bd mov sp, r7 + 8002434: bd80 pop {r7, pc} + +08002436 : + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) +{ + 8002436: b580 push {r7, lr} + 8002438: b082 sub sp, #8 + 800243a: af00 add r7, sp, #0 + 800243c: 4603 mov r3, r0 + 800243e: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Enable interrupt */ + NVIC_EnableIRQ(IRQn); + 8002440: f997 3007 ldrsb.w r3, [r7, #7] + 8002444: 4618 mov r0, r3 + 8002446: f7ff ff13 bl 8002270 <__NVIC_EnableIRQ> +} + 800244a: bf00 nop + 800244c: 3708 adds r7, #8 + 800244e: 46bd mov sp, r7 + 8002450: bd80 pop {r7, pc} + +08002452 : + * (For the complete STM32 Devices IRQ Channels list, please refer + * to the appropriate CMSIS device file (stm32wlxxxx.h)) + * @retval None + */ +void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) +{ + 8002452: b580 push {r7, lr} + 8002454: b082 sub sp, #8 + 8002456: af00 add r7, sp, #0 + 8002458: 4603 mov r3, r0 + 800245a: 71fb strb r3, [r7, #7] + /* Check the parameters */ + assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); + + /* Disable interrupt */ + NVIC_DisableIRQ(IRQn); + 800245c: f997 3007 ldrsb.w r3, [r7, #7] + 8002460: 4618 mov r0, r3 + 8002462: f7ff ff21 bl 80022a8 <__NVIC_DisableIRQ> +} + 8002466: bf00 nop + 8002468: 3708 adds r7, #8 + 800246a: 46bd mov sp, r7 + 800246c: bd80 pop {r7, pc} + +0800246e : + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. + * @retval status: - 0 Function succeeded. + * - 1 Function failed. + */ +uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) +{ + 800246e: b580 push {r7, lr} + 8002470: b082 sub sp, #8 + 8002472: af00 add r7, sp, #0 + 8002474: 6078 str r0, [r7, #4] + return SysTick_Config(TicksNumb); + 8002476: 6878 ldr r0, [r7, #4] + 8002478: f7ff ff96 bl 80023a8 + 800247c: 4603 mov r3, r0 +} + 800247e: 4618 mov r0, r3 + 8002480: 3708 adds r7, #8 + 8002482: 46bd mov sp, r7 + 8002484: bd80 pop {r7, pc} + ... + +08002488 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) +{ + 8002488: b580 push {r7, lr} + 800248a: b082 sub sp, #8 + 800248c: af00 add r7, sp, #0 + 800248e: 6078 str r0, [r7, #4] + /* Check the DMA handle allocation */ + if (hdma == NULL) + 8002490: 687b ldr r3, [r7, #4] + 8002492: 2b00 cmp r3, #0 + 8002494: d101 bne.n 800249a + { + return HAL_ERROR; + 8002496: 2301 movs r3, #1 + 8002498: e08e b.n 80025b8 + assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); + + assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 800249a: 687b ldr r3, [r7, #4] + 800249c: 681b ldr r3, [r3, #0] + 800249e: 461a mov r2, r3 + 80024a0: 4b47 ldr r3, [pc, #284] ; (80025c0 ) + 80024a2: 429a cmp r2, r3 + 80024a4: d80f bhi.n 80024c6 + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + 80024a6: 687b ldr r3, [r7, #4] + 80024a8: 681b ldr r3, [r3, #0] + 80024aa: 461a mov r2, r3 + 80024ac: 4b45 ldr r3, [pc, #276] ; (80025c4 ) + 80024ae: 4413 add r3, r2 + 80024b0: 4a45 ldr r2, [pc, #276] ; (80025c8 ) + 80024b2: fba2 2303 umull r2, r3, r2, r3 + 80024b6: 091b lsrs r3, r3, #4 + 80024b8: 009a lsls r2, r3, #2 + 80024ba: 687b ldr r3, [r7, #4] + 80024bc: 645a str r2, [r3, #68] ; 0x44 + hdma->DmaBaseAddress = DMA1; + 80024be: 687b ldr r3, [r7, #4] + 80024c0: 4a42 ldr r2, [pc, #264] ; (80025cc ) + 80024c2: 641a str r2, [r3, #64] ; 0x40 + 80024c4: e00e b.n 80024e4 + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + 80024c6: 687b ldr r3, [r7, #4] + 80024c8: 681b ldr r3, [r3, #0] + 80024ca: 461a mov r2, r3 + 80024cc: 4b40 ldr r3, [pc, #256] ; (80025d0 ) + 80024ce: 4413 add r3, r2 + 80024d0: 4a3d ldr r2, [pc, #244] ; (80025c8 ) + 80024d2: fba2 2303 umull r2, r3, r2, r3 + 80024d6: 091b lsrs r3, r3, #4 + 80024d8: 009a lsls r2, r3, #2 + 80024da: 687b ldr r3, [r7, #4] + 80024dc: 645a str r2, [r3, #68] ; 0x44 + hdma->DmaBaseAddress = DMA2; + 80024de: 687b ldr r3, [r7, #4] + 80024e0: 4a3c ldr r2, [pc, #240] ; (80025d4 ) + 80024e2: 641a str r2, [r3, #64] ; 0x40 + } + + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 80024e4: 687b ldr r3, [r7, #4] + 80024e6: 2202 movs r2, #2 + 80024e8: f883 2025 strb.w r2, [r3, #37] ; 0x25 + + /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ + CLEAR_BIT(hdma->Instance->CCR, (DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | \ + 80024ec: 687b ldr r3, [r7, #4] + 80024ee: 681b ldr r3, [r3, #0] + 80024f0: 681b ldr r3, [r3, #0] + 80024f2: 687a ldr r2, [r7, #4] + 80024f4: 6812 ldr r2, [r2, #0] + 80024f6: f423 43ff bic.w r3, r3, #32640 ; 0x7f80 + 80024fa: f023 0370 bic.w r3, r3, #112 ; 0x70 + 80024fe: 6013 str r3, [r2, #0] + DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | \ + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); + + /* Set the DMA Channel configuration */ + SET_BIT(hdma->Instance->CCR, (hdma->Init.Direction | \ + 8002500: 687b ldr r3, [r7, #4] + 8002502: 681b ldr r3, [r3, #0] + 8002504: 6819 ldr r1, [r3, #0] + 8002506: 687b ldr r3, [r7, #4] + 8002508: 689a ldr r2, [r3, #8] + 800250a: 687b ldr r3, [r7, #4] + 800250c: 68db ldr r3, [r3, #12] + 800250e: 431a orrs r2, r3 + 8002510: 687b ldr r3, [r7, #4] + 8002512: 691b ldr r3, [r3, #16] + 8002514: 431a orrs r2, r3 + 8002516: 687b ldr r3, [r7, #4] + 8002518: 695b ldr r3, [r3, #20] + 800251a: 431a orrs r2, r3 + 800251c: 687b ldr r3, [r7, #4] + 800251e: 699b ldr r3, [r3, #24] + 8002520: 431a orrs r2, r3 + 8002522: 687b ldr r3, [r7, #4] + 8002524: 69db ldr r3, [r3, #28] + 8002526: 431a orrs r2, r3 + 8002528: 687b ldr r3, [r7, #4] + 800252a: 6a1b ldr r3, [r3, #32] + 800252c: 431a orrs r2, r3 + 800252e: 687b ldr r3, [r7, #4] + 8002530: 681b ldr r3, [r3, #0] + 8002532: 430a orrs r2, r1 + 8002534: 601a str r2, [r3, #0] + hdma->Init.Mode | hdma->Init.Priority)); + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask + */ + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 8002536: 6878 ldr r0, [r7, #4] + 8002538: f000 fb24 bl 8002b84 + + if (hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) + 800253c: 687b ldr r3, [r7, #4] + 800253e: 689b ldr r3, [r3, #8] + 8002540: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8002544: d102 bne.n 800254c + { + /* if memory to memory force the request to 0*/ + hdma->Init.Request = DMA_REQUEST_MEM2MEM; + 8002546: 687b ldr r3, [r7, #4] + 8002548: 2200 movs r2, #0 + 800254a: 605a str r2, [r3, #4] + } + + /* Set peripheral request to DMAMUX channel */ + hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); + 800254c: 687b ldr r3, [r7, #4] + 800254e: 685a ldr r2, [r3, #4] + 8002550: 687b ldr r3, [r7, #4] + 8002552: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002554: f002 027f and.w r2, r2, #127 ; 0x7f + 8002558: 601a str r2, [r3, #0] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 800255a: 687b ldr r3, [r7, #4] + 800255c: 6cdb ldr r3, [r3, #76] ; 0x4c + 800255e: 687a ldr r2, [r7, #4] + 8002560: 6d12 ldr r2, [r2, #80] ; 0x50 + 8002562: 605a str r2, [r3, #4] + + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 8002564: 687b ldr r3, [r7, #4] + 8002566: 685b ldr r3, [r3, #4] + 8002568: 2b00 cmp r3, #0 + 800256a: d010 beq.n 800258e + 800256c: 687b ldr r3, [r7, #4] + 800256e: 685b ldr r3, [r3, #4] + 8002570: 2b04 cmp r3, #4 + 8002572: d80c bhi.n 800258e + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 8002574: 6878 ldr r0, [r7, #4] + 8002576: f000 fb4d bl 8002c14 + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + 800257a: 687b ldr r3, [r7, #4] + 800257c: 6d5b ldr r3, [r3, #84] ; 0x54 + 800257e: 2200 movs r2, #0 + 8002580: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8002582: 687b ldr r3, [r7, #4] + 8002584: 6d9b ldr r3, [r3, #88] ; 0x58 + 8002586: 687a ldr r2, [r7, #4] + 8002588: 6dd2 ldr r2, [r2, #92] ; 0x5c + 800258a: 605a str r2, [r3, #4] + 800258c: e008 b.n 80025a0 + } + else + { + hdma->DMAmuxRequestGen = NULL; + 800258e: 687b ldr r3, [r7, #4] + 8002590: 2200 movs r2, #0 + 8002592: 655a str r2, [r3, #84] ; 0x54 + hdma->DMAmuxRequestGenStatus = NULL; + 8002594: 687b ldr r3, [r7, #4] + 8002596: 2200 movs r2, #0 + 8002598: 659a str r2, [r3, #88] ; 0x58 + hdma->DMAmuxRequestGenStatusMask = 0U; + 800259a: 687b ldr r3, [r7, #4] + 800259c: 2200 movs r2, #0 + 800259e: 65da str r2, [r3, #92] ; 0x5c + } + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 80025a0: 687b ldr r3, [r7, #4] + 80025a2: 2200 movs r2, #0 + 80025a4: 63da str r2, [r3, #60] ; 0x3c + + /* Initialize the DMA state*/ + hdma->State = HAL_DMA_STATE_READY; + 80025a6: 687b ldr r3, [r7, #4] + 80025a8: 2201 movs r2, #1 + 80025aa: f883 2025 strb.w r2, [r3, #37] ; 0x25 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 80025ae: 687b ldr r3, [r7, #4] + 80025b0: 2200 movs r2, #0 + 80025b2: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + return HAL_OK; + 80025b6: 2300 movs r3, #0 +} + 80025b8: 4618 mov r0, r3 + 80025ba: 3708 adds r7, #8 + 80025bc: 46bd mov sp, r7 + 80025be: bd80 pop {r7, pc} + 80025c0: 40020407 .word 0x40020407 + 80025c4: bffdfff8 .word 0xbffdfff8 + 80025c8: cccccccd .word 0xcccccccd + 80025cc: 40020000 .word 0x40020000 + 80025d0: bffdfbf8 .word 0xbffdfbf8 + 80025d4: 40020400 .word 0x40020400 + +080025d8 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) +{ + 80025d8: b580 push {r7, lr} + 80025da: b082 sub sp, #8 + 80025dc: af00 add r7, sp, #0 + 80025de: 6078 str r0, [r7, #4] + /* Check the DMA handle allocation */ + if (NULL == hdma) + 80025e0: 687b ldr r3, [r7, #4] + 80025e2: 2b00 cmp r3, #0 + 80025e4: d101 bne.n 80025ea + { + return HAL_ERROR; + 80025e6: 2301 movs r3, #1 + 80025e8: e07b b.n 80026e2 + + /* Check the parameters */ + assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); + + /* Disable the selected DMA Channelx */ + __HAL_DMA_DISABLE(hdma); + 80025ea: 687b ldr r3, [r7, #4] + 80025ec: 681b ldr r3, [r3, #0] + 80025ee: 681a ldr r2, [r3, #0] + 80025f0: 687b ldr r3, [r7, #4] + 80025f2: 681b ldr r3, [r3, #0] + 80025f4: f022 0201 bic.w r2, r2, #1 + 80025f8: 601a str r2, [r3, #0] + + /* Compute the channel index */ + if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) + 80025fa: 687b ldr r3, [r7, #4] + 80025fc: 681b ldr r3, [r3, #0] + 80025fe: 461a mov r2, r3 + 8002600: 4b3a ldr r3, [pc, #232] ; (80026ec ) + 8002602: 429a cmp r2, r3 + 8002604: d80f bhi.n 8002626 + { + /* DMA1 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2U; + 8002606: 687b ldr r3, [r7, #4] + 8002608: 681b ldr r3, [r3, #0] + 800260a: 461a mov r2, r3 + 800260c: 4b38 ldr r3, [pc, #224] ; (80026f0 ) + 800260e: 4413 add r3, r2 + 8002610: 4a38 ldr r2, [pc, #224] ; (80026f4 ) + 8002612: fba2 2303 umull r2, r3, r2, r3 + 8002616: 091b lsrs r3, r3, #4 + 8002618: 009a lsls r2, r3, #2 + 800261a: 687b ldr r3, [r7, #4] + 800261c: 645a str r2, [r3, #68] ; 0x44 + hdma->DmaBaseAddress = DMA1; + 800261e: 687b ldr r3, [r7, #4] + 8002620: 4a35 ldr r2, [pc, #212] ; (80026f8 ) + 8002622: 641a str r2, [r3, #64] ; 0x40 + 8002624: e00e b.n 8002644 + } + else + { + /* DMA2 */ + hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2U; + 8002626: 687b ldr r3, [r7, #4] + 8002628: 681b ldr r3, [r3, #0] + 800262a: 461a mov r2, r3 + 800262c: 4b33 ldr r3, [pc, #204] ; (80026fc ) + 800262e: 4413 add r3, r2 + 8002630: 4a30 ldr r2, [pc, #192] ; (80026f4 ) + 8002632: fba2 2303 umull r2, r3, r2, r3 + 8002636: 091b lsrs r3, r3, #4 + 8002638: 009a lsls r2, r3, #2 + 800263a: 687b ldr r3, [r7, #4] + 800263c: 645a str r2, [r3, #68] ; 0x44 + hdma->DmaBaseAddress = DMA2; + 800263e: 687b ldr r3, [r7, #4] + 8002640: 4a2f ldr r2, [pc, #188] ; (8002700 ) + 8002642: 641a str r2, [r3, #64] ; 0x40 + } + + /* Reset DMA Channel control register */ + hdma->Instance->CCR = 0U; + 8002644: 687b ldr r3, [r7, #4] + 8002646: 681b ldr r3, [r3, #0] + 8002648: 2200 movs r2, #0 + 800264a: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 800264c: 687b ldr r3, [r7, #4] + 800264e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002650: f003 021c and.w r2, r3, #28 + 8002654: 687b ldr r3, [r7, #4] + 8002656: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002658: 2101 movs r1, #1 + 800265a: fa01 f202 lsl.w r2, r1, r2 + 800265e: 605a str r2, [r3, #4] + + /* Initialize parameters for DMAMUX channel : + DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ + + DMA_CalcDMAMUXChannelBaseAndMask(hdma); + 8002660: 6878 ldr r0, [r7, #4] + 8002662: f000 fa8f bl 8002b84 + + /* Reset the DMAMUX channel that corresponds to the DMA channel */ + hdma->DMAmuxChannel->CCR = 0U; + 8002666: 687b ldr r3, [r7, #4] + 8002668: 6c9b ldr r3, [r3, #72] ; 0x48 + 800266a: 2200 movs r2, #0 + 800266c: 601a str r2, [r3, #0] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 800266e: 687b ldr r3, [r7, #4] + 8002670: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002672: 687a ldr r2, [r7, #4] + 8002674: 6d12 ldr r2, [r2, #80] ; 0x50 + 8002676: 605a str r2, [r3, #4] + + /* Reset Request generator parameters if any */ + if (((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) + 8002678: 687b ldr r3, [r7, #4] + 800267a: 685b ldr r3, [r3, #4] + 800267c: 2b00 cmp r3, #0 + 800267e: d00f beq.n 80026a0 + 8002680: 687b ldr r3, [r7, #4] + 8002682: 685b ldr r3, [r3, #4] + 8002684: 2b04 cmp r3, #4 + 8002686: d80b bhi.n 80026a0 + { + /* Initialize parameters for DMAMUX request generator : + DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask + */ + DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); + 8002688: 6878 ldr r0, [r7, #4] + 800268a: f000 fac3 bl 8002c14 + + /* Reset the DMAMUX request generator register*/ + hdma->DMAmuxRequestGen->RGCR = 0U; + 800268e: 687b ldr r3, [r7, #4] + 8002690: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002692: 2200 movs r2, #0 + 8002694: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8002696: 687b ldr r3, [r7, #4] + 8002698: 6d9b ldr r3, [r3, #88] ; 0x58 + 800269a: 687a ldr r2, [r7, #4] + 800269c: 6dd2 ldr r2, [r2, #92] ; 0x5c + 800269e: 605a str r2, [r3, #4] + } + + hdma->DMAmuxRequestGen = NULL; + 80026a0: 687b ldr r3, [r7, #4] + 80026a2: 2200 movs r2, #0 + 80026a4: 655a str r2, [r3, #84] ; 0x54 + hdma->DMAmuxRequestGenStatus = NULL; + 80026a6: 687b ldr r3, [r7, #4] + 80026a8: 2200 movs r2, #0 + 80026aa: 659a str r2, [r3, #88] ; 0x58 + hdma->DMAmuxRequestGenStatusMask = 0U; + 80026ac: 687b ldr r3, [r7, #4] + 80026ae: 2200 movs r2, #0 + 80026b0: 65da str r2, [r3, #92] ; 0x5c + + /* Clean callbacks */ + hdma->XferCpltCallback = NULL; + 80026b2: 687b ldr r3, [r7, #4] + 80026b4: 2200 movs r2, #0 + 80026b6: 62da str r2, [r3, #44] ; 0x2c + hdma->XferHalfCpltCallback = NULL; + 80026b8: 687b ldr r3, [r7, #4] + 80026ba: 2200 movs r2, #0 + 80026bc: 631a str r2, [r3, #48] ; 0x30 + hdma->XferErrorCallback = NULL; + 80026be: 687b ldr r3, [r7, #4] + 80026c0: 2200 movs r2, #0 + 80026c2: 635a str r2, [r3, #52] ; 0x34 + hdma->XferAbortCallback = NULL; + 80026c4: 687b ldr r3, [r7, #4] + 80026c6: 2200 movs r2, #0 + 80026c8: 639a str r2, [r3, #56] ; 0x38 + + /* Initialize the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 80026ca: 687b ldr r3, [r7, #4] + 80026cc: 2200 movs r2, #0 + 80026ce: 63da str r2, [r3, #60] ; 0x3c + + /* Initialize the DMA state */ + hdma->State = HAL_DMA_STATE_RESET; + 80026d0: 687b ldr r3, [r7, #4] + 80026d2: 2200 movs r2, #0 + 80026d4: f883 2025 strb.w r2, [r3, #37] ; 0x25 + + /* Release Lock */ + __HAL_UNLOCK(hdma); + 80026d8: 687b ldr r3, [r7, #4] + 80026da: 2200 movs r2, #0 + 80026dc: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + return HAL_OK; + 80026e0: 2300 movs r3, #0 +} + 80026e2: 4618 mov r0, r3 + 80026e4: 3708 adds r7, #8 + 80026e6: 46bd mov sp, r7 + 80026e8: bd80 pop {r7, pc} + 80026ea: bf00 nop + 80026ec: 40020407 .word 0x40020407 + 80026f0: bffdfff8 .word 0xbffdfff8 + 80026f4: cccccccd .word 0xcccccccd + 80026f8: 40020000 .word 0x40020000 + 80026fc: bffdfbf8 .word 0xbffdfbf8 + 8002700: 40020400 .word 0x40020400 + +08002704 : + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + 8002704: b580 push {r7, lr} + 8002706: b086 sub sp, #24 + 8002708: af00 add r7, sp, #0 + 800270a: 60f8 str r0, [r7, #12] + 800270c: 60b9 str r1, [r7, #8] + 800270e: 607a str r2, [r7, #4] + 8002710: 603b str r3, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 8002712: 2300 movs r3, #0 + 8002714: 75fb strb r3, [r7, #23] + + /* Check the parameters */ + assert_param(IS_DMA_BUFFER_SIZE(DataLength)); + + /* Process locked */ + __HAL_LOCK(hdma); + 8002716: 68fb ldr r3, [r7, #12] + 8002718: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 800271c: 2b01 cmp r3, #1 + 800271e: d101 bne.n 8002724 + 8002720: 2302 movs r3, #2 + 8002722: e069 b.n 80027f8 + 8002724: 68fb ldr r3, [r7, #12] + 8002726: 2201 movs r2, #1 + 8002728: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + if (hdma->State == HAL_DMA_STATE_READY) + 800272c: 68fb ldr r3, [r7, #12] + 800272e: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 8002732: b2db uxtb r3, r3 + 8002734: 2b01 cmp r3, #1 + 8002736: d155 bne.n 80027e4 + { + /* Change DMA peripheral state */ + hdma->State = HAL_DMA_STATE_BUSY; + 8002738: 68fb ldr r3, [r7, #12] + 800273a: 2202 movs r2, #2 + 800273c: f883 2025 strb.w r2, [r3, #37] ; 0x25 + hdma->ErrorCode = HAL_DMA_ERROR_NONE; + 8002740: 68fb ldr r3, [r7, #12] + 8002742: 2200 movs r2, #0 + 8002744: 63da str r2, [r3, #60] ; 0x3c + + /* Disable the peripheral */ + __HAL_DMA_DISABLE(hdma); + 8002746: 68fb ldr r3, [r7, #12] + 8002748: 681b ldr r3, [r3, #0] + 800274a: 681a ldr r2, [r3, #0] + 800274c: 68fb ldr r3, [r7, #12] + 800274e: 681b ldr r3, [r3, #0] + 8002750: f022 0201 bic.w r2, r2, #1 + 8002754: 601a str r2, [r3, #0] + + /* Configure the source, destination address and the data length & clear flags*/ + DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); + 8002756: 683b ldr r3, [r7, #0] + 8002758: 687a ldr r2, [r7, #4] + 800275a: 68b9 ldr r1, [r7, #8] + 800275c: 68f8 ldr r0, [r7, #12] + 800275e: f000 f9d3 bl 8002b08 + + /* Enable the transfer complete interrupt */ + /* Enable the transfer Error interrupt */ + if (NULL != hdma->XferHalfCpltCallback) + 8002762: 68fb ldr r3, [r7, #12] + 8002764: 6b1b ldr r3, [r3, #48] ; 0x30 + 8002766: 2b00 cmp r3, #0 + 8002768: d008 beq.n 800277c + { + /* Enable the Half transfer complete interrupt as well */ + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 800276a: 68fb ldr r3, [r7, #12] + 800276c: 681b ldr r3, [r3, #0] + 800276e: 681a ldr r2, [r3, #0] + 8002770: 68fb ldr r3, [r7, #12] + 8002772: 681b ldr r3, [r3, #0] + 8002774: f042 020e orr.w r2, r2, #14 + 8002778: 601a str r2, [r3, #0] + 800277a: e00f b.n 800279c + } + else + { + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 800277c: 68fb ldr r3, [r7, #12] + 800277e: 681b ldr r3, [r3, #0] + 8002780: 681a ldr r2, [r3, #0] + 8002782: 68fb ldr r3, [r7, #12] + 8002784: 681b ldr r3, [r3, #0] + 8002786: f022 0204 bic.w r2, r2, #4 + 800278a: 601a str r2, [r3, #0] + __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); + 800278c: 68fb ldr r3, [r7, #12] + 800278e: 681b ldr r3, [r3, #0] + 8002790: 681a ldr r2, [r3, #0] + 8002792: 68fb ldr r3, [r7, #12] + 8002794: 681b ldr r3, [r3, #0] + 8002796: f042 020a orr.w r2, r2, #10 + 800279a: 601a str r2, [r3, #0] + } + + /* Check if DMAMUX Synchronization is enabled*/ + if ((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) + 800279c: 68fb ldr r3, [r7, #12] + 800279e: 6c9b ldr r3, [r3, #72] ; 0x48 + 80027a0: 681b ldr r3, [r3, #0] + 80027a2: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80027a6: 2b00 cmp r3, #0 + 80027a8: d007 beq.n 80027ba + { + /* Enable DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; + 80027aa: 68fb ldr r3, [r7, #12] + 80027ac: 6c9b ldr r3, [r3, #72] ; 0x48 + 80027ae: 681a ldr r2, [r3, #0] + 80027b0: 68fb ldr r3, [r7, #12] + 80027b2: 6c9b ldr r3, [r3, #72] ; 0x48 + 80027b4: f442 7280 orr.w r2, r2, #256 ; 0x100 + 80027b8: 601a str r2, [r3, #0] + } + + if (hdma->DMAmuxRequestGen != NULL) + 80027ba: 68fb ldr r3, [r7, #12] + 80027bc: 6d5b ldr r3, [r3, #84] ; 0x54 + 80027be: 2b00 cmp r3, #0 + 80027c0: d007 beq.n 80027d2 + { + /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ + /* enable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; + 80027c2: 68fb ldr r3, [r7, #12] + 80027c4: 6d5b ldr r3, [r3, #84] ; 0x54 + 80027c6: 681a ldr r2, [r3, #0] + 80027c8: 68fb ldr r3, [r7, #12] + 80027ca: 6d5b ldr r3, [r3, #84] ; 0x54 + 80027cc: f442 7280 orr.w r2, r2, #256 ; 0x100 + 80027d0: 601a str r2, [r3, #0] + } + + /* Enable the Peripheral */ + __HAL_DMA_ENABLE(hdma); + 80027d2: 68fb ldr r3, [r7, #12] + 80027d4: 681b ldr r3, [r3, #0] + 80027d6: 681a ldr r2, [r3, #0] + 80027d8: 68fb ldr r3, [r7, #12] + 80027da: 681b ldr r3, [r3, #0] + 80027dc: f042 0201 orr.w r2, r2, #1 + 80027e0: 601a str r2, [r3, #0] + 80027e2: e008 b.n 80027f6 + } + else + { + /* Change the error code */ + hdma->ErrorCode = HAL_DMA_ERROR_BUSY; + 80027e4: 68fb ldr r3, [r7, #12] + 80027e6: 2280 movs r2, #128 ; 0x80 + 80027e8: 63da str r2, [r3, #60] ; 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 80027ea: 68fb ldr r3, [r7, #12] + 80027ec: 2200 movs r2, #0 + 80027ee: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + /* Return error status */ + status = HAL_ERROR; + 80027f2: 2301 movs r3, #1 + 80027f4: 75fb strb r3, [r7, #23] + } + + return status; + 80027f6: 7dfb ldrb r3, [r7, #23] +} + 80027f8: 4618 mov r0, r3 + 80027fa: 3718 adds r7, #24 + 80027fc: 46bd mov sp, r7 + 80027fe: bd80 pop {r7, pc} + +08002800 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) +{ + 8002800: b480 push {r7} + 8002802: b083 sub sp, #12 + 8002804: af00 add r7, sp, #0 + 8002806: 6078 str r0, [r7, #4] + /* Check the DMA peripheral handle */ + if (NULL == hdma) + 8002808: 687b ldr r3, [r7, #4] + 800280a: 2b00 cmp r3, #0 + 800280c: d101 bne.n 8002812 + { + return HAL_ERROR; + 800280e: 2301 movs r3, #1 + 8002810: e04f b.n 80028b2 + } + + /* Check the DMA peripheral state */ + if (hdma->State != HAL_DMA_STATE_BUSY) + 8002812: 687b ldr r3, [r7, #4] + 8002814: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 8002818: b2db uxtb r3, r3 + 800281a: 2b02 cmp r3, #2 + 800281c: d008 beq.n 8002830 + { + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 800281e: 687b ldr r3, [r7, #4] + 8002820: 2204 movs r2, #4 + 8002822: 63da str r2, [r3, #60] ; 0x3c + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002824: 687b ldr r3, [r7, #4] + 8002826: 2200 movs r2, #0 + 8002828: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + return HAL_ERROR; + 800282c: 2301 movs r3, #1 + 800282e: e040 b.n 80028b2 + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8002830: 687b ldr r3, [r7, #4] + 8002832: 681b ldr r3, [r3, #0] + 8002834: 681a ldr r2, [r3, #0] + 8002836: 687b ldr r3, [r7, #4] + 8002838: 681b ldr r3, [r3, #0] + 800283a: f022 020e bic.w r2, r2, #14 + 800283e: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 8002840: 687b ldr r3, [r7, #4] + 8002842: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002844: 681a ldr r2, [r3, #0] + 8002846: 687b ldr r3, [r7, #4] + 8002848: 6c9b ldr r3, [r3, #72] ; 0x48 + 800284a: f422 7280 bic.w r2, r2, #256 ; 0x100 + 800284e: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 8002850: 687b ldr r3, [r7, #4] + 8002852: 681b ldr r3, [r3, #0] + 8002854: 681a ldr r2, [r3, #0] + 8002856: 687b ldr r3, [r7, #4] + 8002858: 681b ldr r3, [r3, #0] + 800285a: f022 0201 bic.w r2, r2, #1 + 800285e: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8002860: 687b ldr r3, [r7, #4] + 8002862: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002864: f003 021c and.w r2, r3, #28 + 8002868: 687b ldr r3, [r7, #4] + 800286a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800286c: 2101 movs r1, #1 + 800286e: fa01 f202 lsl.w r2, r1, r2 + 8002872: 605a str r2, [r3, #4] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8002874: 687b ldr r3, [r7, #4] + 8002876: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002878: 687a ldr r2, [r7, #4] + 800287a: 6d12 ldr r2, [r2, #80] ; 0x50 + 800287c: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 800287e: 687b ldr r3, [r7, #4] + 8002880: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002882: 2b00 cmp r3, #0 + 8002884: d00c beq.n 80028a0 + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 8002886: 687b ldr r3, [r7, #4] + 8002888: 6d5b ldr r3, [r3, #84] ; 0x54 + 800288a: 681a ldr r2, [r3, #0] + 800288c: 687b ldr r3, [r7, #4] + 800288e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002890: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8002894: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8002896: 687b ldr r3, [r7, #4] + 8002898: 6d9b ldr r3, [r3, #88] ; 0x58 + 800289a: 687a ldr r2, [r7, #4] + 800289c: 6dd2 ldr r2, [r2, #92] ; 0x5c + 800289e: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 80028a0: 687b ldr r3, [r7, #4] + 80028a2: 2201 movs r2, #1 + 80028a4: f883 2025 strb.w r2, [r3, #37] ; 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 80028a8: 687b ldr r3, [r7, #4] + 80028aa: 2200 movs r2, #0 + 80028ac: f883 2024 strb.w r2, [r3, #36] ; 0x24 + } + + return HAL_OK; + 80028b0: 2300 movs r3, #0 +} + 80028b2: 4618 mov r0, r3 + 80028b4: 370c adds r7, #12 + 80028b6: 46bd mov sp, r7 + 80028b8: bc80 pop {r7} + 80028ba: 4770 bx lr + +080028bc : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) +{ + 80028bc: b580 push {r7, lr} + 80028be: b084 sub sp, #16 + 80028c0: af00 add r7, sp, #0 + 80028c2: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 80028c4: 2300 movs r3, #0 + 80028c6: 73fb strb r3, [r7, #15] + + if (hdma->State != HAL_DMA_STATE_BUSY) + 80028c8: 687b ldr r3, [r7, #4] + 80028ca: f893 3025 ldrb.w r3, [r3, #37] ; 0x25 + 80028ce: b2db uxtb r3, r3 + 80028d0: 2b02 cmp r3, #2 + 80028d2: d005 beq.n 80028e0 + { + /* no transfer ongoing */ + hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; + 80028d4: 687b ldr r3, [r7, #4] + 80028d6: 2204 movs r2, #4 + 80028d8: 63da str r2, [r3, #60] ; 0x3c + + status = HAL_ERROR; + 80028da: 2301 movs r3, #1 + 80028dc: 73fb strb r3, [r7, #15] + 80028de: e047 b.n 8002970 + } + else + { + /* Disable DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 80028e0: 687b ldr r3, [r7, #4] + 80028e2: 681b ldr r3, [r3, #0] + 80028e4: 681a ldr r2, [r3, #0] + 80028e6: 687b ldr r3, [r7, #4] + 80028e8: 681b ldr r3, [r3, #0] + 80028ea: f022 020e bic.w r2, r2, #14 + 80028ee: 601a str r2, [r3, #0] + + /* Disable the channel */ + __HAL_DMA_DISABLE(hdma); + 80028f0: 687b ldr r3, [r7, #4] + 80028f2: 681b ldr r3, [r3, #0] + 80028f4: 681a ldr r2, [r3, #0] + 80028f6: 687b ldr r3, [r7, #4] + 80028f8: 681b ldr r3, [r3, #0] + 80028fa: f022 0201 bic.w r2, r2, #1 + 80028fe: 601a str r2, [r3, #0] + + /* disable the DMAMUX sync overrun IT*/ + hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; + 8002900: 687b ldr r3, [r7, #4] + 8002902: 6c9b ldr r3, [r3, #72] ; 0x48 + 8002904: 681a ldr r2, [r3, #0] + 8002906: 687b ldr r3, [r7, #4] + 8002908: 6c9b ldr r3, [r3, #72] ; 0x48 + 800290a: f422 7280 bic.w r2, r2, #256 ; 0x100 + 800290e: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8002910: 687b ldr r3, [r7, #4] + 8002912: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002914: f003 021c and.w r2, r3, #28 + 8002918: 687b ldr r3, [r7, #4] + 800291a: 6c1b ldr r3, [r3, #64] ; 0x40 + 800291c: 2101 movs r1, #1 + 800291e: fa01 f202 lsl.w r2, r1, r2 + 8002922: 605a str r2, [r3, #4] + + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8002924: 687b ldr r3, [r7, #4] + 8002926: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002928: 687a ldr r2, [r7, #4] + 800292a: 6d12 ldr r2, [r2, #80] ; 0x50 + 800292c: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 800292e: 687b ldr r3, [r7, #4] + 8002930: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002932: 2b00 cmp r3, #0 + 8002934: d00c beq.n 8002950 + { + /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ + /* disable the request gen overrun IT*/ + hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; + 8002936: 687b ldr r3, [r7, #4] + 8002938: 6d5b ldr r3, [r3, #84] ; 0x54 + 800293a: 681a ldr r2, [r3, #0] + 800293c: 687b ldr r3, [r7, #4] + 800293e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002940: f422 7280 bic.w r2, r2, #256 ; 0x100 + 8002944: 601a str r2, [r3, #0] + + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8002946: 687b ldr r3, [r7, #4] + 8002948: 6d9b ldr r3, [r3, #88] ; 0x58 + 800294a: 687a ldr r2, [r7, #4] + 800294c: 6dd2 ldr r2, [r2, #92] ; 0x5c + 800294e: 605a str r2, [r3, #4] + } + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002950: 687b ldr r3, [r7, #4] + 8002952: 2201 movs r2, #1 + 8002954: f883 2025 strb.w r2, [r3, #37] ; 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002958: 687b ldr r3, [r7, #4] + 800295a: 2200 movs r2, #0 + 800295c: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + /* Call User Abort callback */ + if (hdma->XferAbortCallback != NULL) + 8002960: 687b ldr r3, [r7, #4] + 8002962: 6b9b ldr r3, [r3, #56] ; 0x38 + 8002964: 2b00 cmp r3, #0 + 8002966: d003 beq.n 8002970 + { + hdma->XferAbortCallback(hdma); + 8002968: 687b ldr r3, [r7, #4] + 800296a: 6b9b ldr r3, [r3, #56] ; 0x38 + 800296c: 6878 ldr r0, [r7, #4] + 800296e: 4798 blx r3 + } + } + return status; + 8002970: 7bfb ldrb r3, [r7, #15] +} + 8002972: 4618 mov r0, r3 + 8002974: 3710 adds r7, #16 + 8002976: 46bd mov sp, r7 + 8002978: bd80 pop {r7, pc} + ... + +0800297c : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) +{ + 800297c: b580 push {r7, lr} + 800297e: b084 sub sp, #16 + 8002980: af00 add r7, sp, #0 + 8002982: 6078 str r0, [r7, #4] + uint32_t flag_it = hdma->DmaBaseAddress->ISR; + 8002984: 687b ldr r3, [r7, #4] + 8002986: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002988: 681b ldr r3, [r3, #0] + 800298a: 60fb str r3, [r7, #12] + uint32_t source_it = hdma->Instance->CCR; + 800298c: 687b ldr r3, [r7, #4] + 800298e: 681b ldr r3, [r3, #0] + 8002990: 681b ldr r3, [r3, #0] + 8002992: 60bb str r3, [r7, #8] + + /* Half Transfer Complete Interrupt management ******************************/ + if (((flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_HT) != 0U)) + 8002994: 687b ldr r3, [r7, #4] + 8002996: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002998: f003 031c and.w r3, r3, #28 + 800299c: 2204 movs r2, #4 + 800299e: 409a lsls r2, r3 + 80029a0: 68fb ldr r3, [r7, #12] + 80029a2: 4013 ands r3, r2 + 80029a4: 2b00 cmp r3, #0 + 80029a6: d027 beq.n 80029f8 + 80029a8: 68bb ldr r3, [r7, #8] + 80029aa: f003 0304 and.w r3, r3, #4 + 80029ae: 2b00 cmp r3, #0 + 80029b0: d022 beq.n 80029f8 + { + /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 80029b2: 687b ldr r3, [r7, #4] + 80029b4: 681b ldr r3, [r3, #0] + 80029b6: 681b ldr r3, [r3, #0] + 80029b8: f003 0320 and.w r3, r3, #32 + 80029bc: 2b00 cmp r3, #0 + 80029be: d107 bne.n 80029d0 + { + /* Disable the half transfer interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); + 80029c0: 687b ldr r3, [r7, #4] + 80029c2: 681b ldr r3, [r3, #0] + 80029c4: 681a ldr r2, [r3, #0] + 80029c6: 687b ldr r3, [r7, #4] + 80029c8: 681b ldr r3, [r3, #0] + 80029ca: f022 0204 bic.w r2, r2, #4 + 80029ce: 601a str r2, [r3, #0] + } + /* Clear the half transfer complete flag */ + hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1CU); + 80029d0: 687b ldr r3, [r7, #4] + 80029d2: 6c5b ldr r3, [r3, #68] ; 0x44 + 80029d4: f003 021c and.w r2, r3, #28 + 80029d8: 687b ldr r3, [r7, #4] + 80029da: 6c1b ldr r3, [r3, #64] ; 0x40 + 80029dc: 2104 movs r1, #4 + 80029de: fa01 f202 lsl.w r2, r1, r2 + 80029e2: 605a str r2, [r3, #4] + + /* DMA peripheral state is not updated in Half Transfer */ + /* but in Transfer Complete case */ + + if (hdma->XferHalfCpltCallback != NULL) + 80029e4: 687b ldr r3, [r7, #4] + 80029e6: 6b1b ldr r3, [r3, #48] ; 0x30 + 80029e8: 2b00 cmp r3, #0 + 80029ea: f000 8081 beq.w 8002af0 + { + /* Half transfer callback */ + hdma->XferHalfCpltCallback(hdma); + 80029ee: 687b ldr r3, [r7, #4] + 80029f0: 6b1b ldr r3, [r3, #48] ; 0x30 + 80029f2: 6878 ldr r0, [r7, #4] + 80029f4: 4798 blx r3 + if (hdma->XferHalfCpltCallback != NULL) + 80029f6: e07b b.n 8002af0 + } + } + + /* Transfer Complete Interrupt management ***********************************/ + else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU)))) && (0U != (source_it & DMA_IT_TC))) + 80029f8: 687b ldr r3, [r7, #4] + 80029fa: 6c5b ldr r3, [r3, #68] ; 0x44 + 80029fc: f003 031c and.w r3, r3, #28 + 8002a00: 2202 movs r2, #2 + 8002a02: 409a lsls r2, r3 + 8002a04: 68fb ldr r3, [r7, #12] + 8002a06: 4013 ands r3, r2 + 8002a08: 2b00 cmp r3, #0 + 8002a0a: d03d beq.n 8002a88 + 8002a0c: 68bb ldr r3, [r7, #8] + 8002a0e: f003 0302 and.w r3, r3, #2 + 8002a12: 2b00 cmp r3, #0 + 8002a14: d038 beq.n 8002a88 + { + if ((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) + 8002a16: 687b ldr r3, [r7, #4] + 8002a18: 681b ldr r3, [r3, #0] + 8002a1a: 681b ldr r3, [r3, #0] + 8002a1c: f003 0320 and.w r3, r3, #32 + 8002a20: 2b00 cmp r3, #0 + 8002a22: d10b bne.n 8002a3c + { + /* Disable the transfer complete and error interrupt */ + __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); + 8002a24: 687b ldr r3, [r7, #4] + 8002a26: 681b ldr r3, [r3, #0] + 8002a28: 681a ldr r2, [r3, #0] + 8002a2a: 687b ldr r3, [r7, #4] + 8002a2c: 681b ldr r3, [r3, #0] + 8002a2e: f022 020a bic.w r2, r2, #10 + 8002a32: 601a str r2, [r3, #0] + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002a34: 687b ldr r3, [r7, #4] + 8002a36: 2201 movs r2, #1 + 8002a38: f883 2025 strb.w r2, [r3, #37] ; 0x25 + } + /* Clear the transfer complete flag */ + __HAL_DMA_CLEAR_FLAG(hdma, (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1CU))); + 8002a3c: 687b ldr r3, [r7, #4] + 8002a3e: 681b ldr r3, [r3, #0] + 8002a40: 461a mov r2, r3 + 8002a42: 4b2e ldr r3, [pc, #184] ; (8002afc ) + 8002a44: 429a cmp r2, r3 + 8002a46: d909 bls.n 8002a5c + 8002a48: 687b ldr r3, [r7, #4] + 8002a4a: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002a4c: f003 031c and.w r3, r3, #28 + 8002a50: 4a2b ldr r2, [pc, #172] ; (8002b00 ) + 8002a52: 2102 movs r1, #2 + 8002a54: fa01 f303 lsl.w r3, r1, r3 + 8002a58: 6053 str r3, [r2, #4] + 8002a5a: e008 b.n 8002a6e + 8002a5c: 687b ldr r3, [r7, #4] + 8002a5e: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002a60: f003 031c and.w r3, r3, #28 + 8002a64: 4a27 ldr r2, [pc, #156] ; (8002b04 ) + 8002a66: 2102 movs r1, #2 + 8002a68: fa01 f303 lsl.w r3, r1, r3 + 8002a6c: 6053 str r3, [r2, #4] + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002a6e: 687b ldr r3, [r7, #4] + 8002a70: 2200 movs r2, #0 + 8002a72: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + if (hdma->XferCpltCallback != NULL) + 8002a76: 687b ldr r3, [r7, #4] + 8002a78: 6adb ldr r3, [r3, #44] ; 0x2c + 8002a7a: 2b00 cmp r3, #0 + 8002a7c: d038 beq.n 8002af0 + { + /* Transfer complete callback */ + hdma->XferCpltCallback(hdma); + 8002a7e: 687b ldr r3, [r7, #4] + 8002a80: 6adb ldr r3, [r3, #44] ; 0x2c + 8002a82: 6878 ldr r0, [r7, #4] + 8002a84: 4798 blx r3 + if (hdma->XferCpltCallback != NULL) + 8002a86: e033 b.n 8002af0 + } + } + + /* Transfer Error Interrupt management **************************************/ + else if (((flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1CU))) != 0U) && ((source_it & DMA_IT_TE) != 0U)) + 8002a88: 687b ldr r3, [r7, #4] + 8002a8a: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002a8c: f003 031c and.w r3, r3, #28 + 8002a90: 2208 movs r2, #8 + 8002a92: 409a lsls r2, r3 + 8002a94: 68fb ldr r3, [r7, #12] + 8002a96: 4013 ands r3, r2 + 8002a98: 2b00 cmp r3, #0 + 8002a9a: d02a beq.n 8002af2 + 8002a9c: 68bb ldr r3, [r7, #8] + 8002a9e: f003 0308 and.w r3, r3, #8 + 8002aa2: 2b00 cmp r3, #0 + 8002aa4: d025 beq.n 8002af2 + { + /* When a DMA transfer error occurs */ + /* A hardware clear of its EN bits is performed */ + /* Disable ALL DMA IT */ + __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); + 8002aa6: 687b ldr r3, [r7, #4] + 8002aa8: 681b ldr r3, [r3, #0] + 8002aaa: 681a ldr r2, [r3, #0] + 8002aac: 687b ldr r3, [r7, #4] + 8002aae: 681b ldr r3, [r3, #0] + 8002ab0: f022 020e bic.w r2, r2, #14 + 8002ab4: 601a str r2, [r3, #0] + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8002ab6: 687b ldr r3, [r7, #4] + 8002ab8: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002aba: f003 021c and.w r2, r3, #28 + 8002abe: 687b ldr r3, [r7, #4] + 8002ac0: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002ac2: 2101 movs r1, #1 + 8002ac4: fa01 f202 lsl.w r2, r1, r2 + 8002ac8: 605a str r2, [r3, #4] + + /* Update error code */ + hdma->ErrorCode = HAL_DMA_ERROR_TE; + 8002aca: 687b ldr r3, [r7, #4] + 8002acc: 2201 movs r2, #1 + 8002ace: 63da str r2, [r3, #60] ; 0x3c + + /* Change the DMA state */ + hdma->State = HAL_DMA_STATE_READY; + 8002ad0: 687b ldr r3, [r7, #4] + 8002ad2: 2201 movs r2, #1 + 8002ad4: f883 2025 strb.w r2, [r3, #37] ; 0x25 + + /* Process Unlocked */ + __HAL_UNLOCK(hdma); + 8002ad8: 687b ldr r3, [r7, #4] + 8002ada: 2200 movs r2, #0 + 8002adc: f883 2024 strb.w r2, [r3, #36] ; 0x24 + + if (hdma->XferErrorCallback != NULL) + 8002ae0: 687b ldr r3, [r7, #4] + 8002ae2: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002ae4: 2b00 cmp r3, #0 + 8002ae6: d004 beq.n 8002af2 + { + /* Transfer error callback */ + hdma->XferErrorCallback(hdma); + 8002ae8: 687b ldr r3, [r7, #4] + 8002aea: 6b5b ldr r3, [r3, #52] ; 0x34 + 8002aec: 6878 ldr r0, [r7, #4] + 8002aee: 4798 blx r3 + } + else + { + /* Nothing To Do */ + } + return; + 8002af0: bf00 nop + 8002af2: bf00 nop +} + 8002af4: 3710 adds r7, #16 + 8002af6: 46bd mov sp, r7 + 8002af8: bd80 pop {r7, pc} + 8002afa: bf00 nop + 8002afc: 40020080 .word 0x40020080 + 8002b00: 40020400 .word 0x40020400 + 8002b04: 40020000 .word 0x40020000 + +08002b08 : + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination + * @retval HAL status + */ +static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) +{ + 8002b08: b480 push {r7} + 8002b0a: b085 sub sp, #20 + 8002b0c: af00 add r7, sp, #0 + 8002b0e: 60f8 str r0, [r7, #12] + 8002b10: 60b9 str r1, [r7, #8] + 8002b12: 607a str r2, [r7, #4] + 8002b14: 603b str r3, [r7, #0] + /* Clear the DMAMUX synchro overrun flag */ + hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; + 8002b16: 68fb ldr r3, [r7, #12] + 8002b18: 6cdb ldr r3, [r3, #76] ; 0x4c + 8002b1a: 68fa ldr r2, [r7, #12] + 8002b1c: 6d12 ldr r2, [r2, #80] ; 0x50 + 8002b1e: 605a str r2, [r3, #4] + + if (hdma->DMAmuxRequestGen != NULL) + 8002b20: 68fb ldr r3, [r7, #12] + 8002b22: 6d5b ldr r3, [r3, #84] ; 0x54 + 8002b24: 2b00 cmp r3, #0 + 8002b26: d004 beq.n 8002b32 + { + /* Clear the DMAMUX request generator overrun flag */ + hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; + 8002b28: 68fb ldr r3, [r7, #12] + 8002b2a: 6d9b ldr r3, [r3, #88] ; 0x58 + 8002b2c: 68fa ldr r2, [r7, #12] + 8002b2e: 6dd2 ldr r2, [r2, #92] ; 0x5c + 8002b30: 605a str r2, [r3, #4] + } + + /* Clear all flags */ + hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1CU)); + 8002b32: 68fb ldr r3, [r7, #12] + 8002b34: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002b36: f003 021c and.w r2, r3, #28 + 8002b3a: 68fb ldr r3, [r7, #12] + 8002b3c: 6c1b ldr r3, [r3, #64] ; 0x40 + 8002b3e: 2101 movs r1, #1 + 8002b40: fa01 f202 lsl.w r2, r1, r2 + 8002b44: 605a str r2, [r3, #4] + + /* Configure DMA Channel data length */ + hdma->Instance->CNDTR = DataLength; + 8002b46: 68fb ldr r3, [r7, #12] + 8002b48: 681b ldr r3, [r3, #0] + 8002b4a: 683a ldr r2, [r7, #0] + 8002b4c: 605a str r2, [r3, #4] + + /* Memory to Peripheral */ + if ((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) + 8002b4e: 68fb ldr r3, [r7, #12] + 8002b50: 689b ldr r3, [r3, #8] + 8002b52: 2b10 cmp r3, #16 + 8002b54: d108 bne.n 8002b68 + { + /* Configure DMA Channel destination address */ + hdma->Instance->CPAR = DstAddress; + 8002b56: 68fb ldr r3, [r7, #12] + 8002b58: 681b ldr r3, [r3, #0] + 8002b5a: 687a ldr r2, [r7, #4] + 8002b5c: 609a str r2, [r3, #8] + + /* Configure DMA Channel source address */ + hdma->Instance->CMAR = SrcAddress; + 8002b5e: 68fb ldr r3, [r7, #12] + 8002b60: 681b ldr r3, [r3, #0] + 8002b62: 68ba ldr r2, [r7, #8] + 8002b64: 60da str r2, [r3, #12] + hdma->Instance->CPAR = SrcAddress; + + /* Configure DMA Channel destination address */ + hdma->Instance->CMAR = DstAddress; + } +} + 8002b66: e007 b.n 8002b78 + hdma->Instance->CPAR = SrcAddress; + 8002b68: 68fb ldr r3, [r7, #12] + 8002b6a: 681b ldr r3, [r3, #0] + 8002b6c: 68ba ldr r2, [r7, #8] + 8002b6e: 609a str r2, [r3, #8] + hdma->Instance->CMAR = DstAddress; + 8002b70: 68fb ldr r3, [r7, #12] + 8002b72: 681b ldr r3, [r3, #0] + 8002b74: 687a ldr r2, [r7, #4] + 8002b76: 60da str r2, [r3, #12] +} + 8002b78: bf00 nop + 8002b7a: 3714 adds r7, #20 + 8002b7c: 46bd mov sp, r7 + 8002b7e: bc80 pop {r7} + 8002b80: 4770 bx lr + ... + +08002b84 : + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains + * the configuration information for the specified DMA Channel. + * @retval None + */ +static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) +{ + 8002b84: b480 push {r7} + 8002b86: b085 sub sp, #20 + 8002b88: af00 add r7, sp, #0 + 8002b8a: 6078 str r0, [r7, #4] + uint32_t channel_number; + + /* check if instance is not outside the DMA channel range */ + if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) + 8002b8c: 687b ldr r3, [r7, #4] + 8002b8e: 681b ldr r3, [r3, #0] + 8002b90: 461a mov r2, r3 + 8002b92: 4b1c ldr r3, [pc, #112] ; (8002c04 ) + 8002b94: 429a cmp r2, r3 + 8002b96: d813 bhi.n 8002bc0 + { + /* DMA1 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel0 + (hdma->ChannelIndex >> 2U)); + 8002b98: 687b ldr r3, [r7, #4] + 8002b9a: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002b9c: 089b lsrs r3, r3, #2 + 8002b9e: 009b lsls r3, r3, #2 + 8002ba0: f103 4380 add.w r3, r3, #1073741824 ; 0x40000000 + 8002ba4: f503 3302 add.w r3, r3, #133120 ; 0x20800 + 8002ba8: 687a ldr r2, [r7, #4] + 8002baa: 6493 str r3, [r2, #72] ; 0x48 + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; + 8002bac: 687b ldr r3, [r7, #4] + 8002bae: 681b ldr r3, [r3, #0] + 8002bb0: b2db uxtb r3, r3 + 8002bb2: 3b08 subs r3, #8 + 8002bb4: 4a14 ldr r2, [pc, #80] ; (8002c08 ) + 8002bb6: fba2 2303 umull r2, r3, r2, r3 + 8002bba: 091b lsrs r3, r3, #4 + 8002bbc: 60fb str r3, [r7, #12] + 8002bbe: e011 b.n 8002be4 + } + else + { + /* DMA2 */ + /* Associate a DMA Channel to a DMAMUX channel */ + hdma->DMAmuxChannel = (DMAMUX1_Channel7 + (hdma->ChannelIndex >> 2U)); + 8002bc0: 687b ldr r3, [r7, #4] + 8002bc2: 6c5b ldr r3, [r3, #68] ; 0x44 + 8002bc4: 089b lsrs r3, r3, #2 + 8002bc6: 009a lsls r2, r3, #2 + 8002bc8: 4b10 ldr r3, [pc, #64] ; (8002c0c ) + 8002bca: 4413 add r3, r2 + 8002bcc: 687a ldr r2, [r7, #4] + 8002bce: 6493 str r3, [r2, #72] ; 0x48 + + /* Prepare channel_number used for DMAmuxChannelStatusMask computation */ + channel_number = (((((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U) + 7U); + 8002bd0: 687b ldr r3, [r7, #4] + 8002bd2: 681b ldr r3, [r3, #0] + 8002bd4: b2db uxtb r3, r3 + 8002bd6: 3b08 subs r3, #8 + 8002bd8: 4a0b ldr r2, [pc, #44] ; (8002c08 ) + 8002bda: fba2 2303 umull r2, r3, r2, r3 + 8002bde: 091b lsrs r3, r3, #4 + 8002be0: 3307 adds r3, #7 + 8002be2: 60fb str r3, [r7, #12] + } + + /* Initialize the field DMAmuxChannelStatus to DMAMUX1_ChannelStatus base */ + hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; + 8002be4: 687b ldr r3, [r7, #4] + 8002be6: 4a0a ldr r2, [pc, #40] ; (8002c10 ) + 8002be8: 64da str r2, [r3, #76] ; 0x4c + + /* Initialize the field DMAmuxChannelStatusMask with the corresponding index of the DMAMUX channel selected for the current ChannelIndex */ + hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1FU); + 8002bea: 68fb ldr r3, [r7, #12] + 8002bec: f003 031f and.w r3, r3, #31 + 8002bf0: 2201 movs r2, #1 + 8002bf2: 409a lsls r2, r3 + 8002bf4: 687b ldr r3, [r7, #4] + 8002bf6: 651a str r2, [r3, #80] ; 0x50 +} + 8002bf8: bf00 nop + 8002bfa: 3714 adds r7, #20 + 8002bfc: 46bd mov sp, r7 + 8002bfe: bc80 pop {r7} + 8002c00: 4770 bx lr + 8002c02: bf00 nop + 8002c04: 40020407 .word 0x40020407 + 8002c08: cccccccd .word 0xcccccccd + 8002c0c: 4002081c .word 0x4002081c + 8002c10: 40020880 .word 0x40020880 + +08002c14 : + * the configuration information for the specified DMA Channel. + * @retval None + */ + +static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) +{ + 8002c14: b480 push {r7} + 8002c16: b085 sub sp, #20 + 8002c18: af00 add r7, sp, #0 + 8002c1a: 6078 str r0, [r7, #4] + uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; + 8002c1c: 687b ldr r3, [r7, #4] + 8002c1e: 685b ldr r3, [r3, #4] + 8002c20: f003 037f and.w r3, r3, #127 ; 0x7f + 8002c24: 60fb str r3, [r7, #12] + + /* DMA Channels are connected to DMAMUX1 request generator blocks*/ + hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); + 8002c26: 68fa ldr r2, [r7, #12] + 8002c28: 4b0a ldr r3, [pc, #40] ; (8002c54 ) + 8002c2a: 4413 add r3, r2 + 8002c2c: 009b lsls r3, r3, #2 + 8002c2e: 461a mov r2, r3 + 8002c30: 687b ldr r3, [r7, #4] + 8002c32: 655a str r2, [r3, #84] ; 0x54 + + hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; + 8002c34: 687b ldr r3, [r7, #4] + 8002c36: 4a08 ldr r2, [pc, #32] ; (8002c58 ) + 8002c38: 659a str r2, [r3, #88] ; 0x58 + + /* here "Request" is either DMA_REQUEST_GENERATOR0 to DMA_REQUEST_GENERATOR3, i.e. <= 4*/ + hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); + 8002c3a: 68fb ldr r3, [r7, #12] + 8002c3c: 3b01 subs r3, #1 + 8002c3e: f003 0303 and.w r3, r3, #3 + 8002c42: 2201 movs r2, #1 + 8002c44: 409a lsls r2, r3 + 8002c46: 687b ldr r3, [r7, #4] + 8002c48: 65da str r2, [r3, #92] ; 0x5c +} + 8002c4a: bf00 nop + 8002c4c: 3714 adds r7, #20 + 8002c4e: 46bd mov sp, r7 + 8002c50: bc80 pop {r7} + 8002c52: 4770 bx lr + 8002c54: 1000823f .word 0x1000823f + 8002c58: 40020940 .word 0x40020940 + +08002c5c : + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains + * the configuration information for the specified GPIO peripheral. + * @retval None + */ +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +{ + 8002c5c: b480 push {r7} + 8002c5e: b087 sub sp, #28 + 8002c60: af00 add r7, sp, #0 + 8002c62: 6078 str r0, [r7, #4] + 8002c64: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 8002c66: 2300 movs r3, #0 + 8002c68: 617b str r3, [r7, #20] + assert_param(IS_GPIO_PIN(GPIO_Init->Pin)); + assert_param(IS_GPIO_MODE(GPIO_Init->Mode)); + assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); + + /* Configure the port pins */ + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8002c6a: e140 b.n 8002eee + { + /* Get current io position */ + iocurrent = (GPIO_Init->Pin) & (1uL << position); + 8002c6c: 683b ldr r3, [r7, #0] + 8002c6e: 681a ldr r2, [r3, #0] + 8002c70: 2101 movs r1, #1 + 8002c72: 697b ldr r3, [r7, #20] + 8002c74: fa01 f303 lsl.w r3, r1, r3 + 8002c78: 4013 ands r3, r2 + 8002c7a: 60fb str r3, [r7, #12] + + if (iocurrent != 0x00u) + 8002c7c: 68fb ldr r3, [r7, #12] + 8002c7e: 2b00 cmp r3, #0 + 8002c80: f000 8132 beq.w 8002ee8 + { + /*--------------------- GPIO Mode Configuration ------------------------*/ + /* In case of Output or Alternate function mode selection */ + if (((GPIO_Init->Mode & GPIO_MODE) == MODE_OUTPUT) || ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF)) + 8002c84: 683b ldr r3, [r7, #0] + 8002c86: 685b ldr r3, [r3, #4] + 8002c88: f003 0303 and.w r3, r3, #3 + 8002c8c: 2b01 cmp r3, #1 + 8002c8e: d005 beq.n 8002c9c + 8002c90: 683b ldr r3, [r7, #0] + 8002c92: 685b ldr r3, [r3, #4] + 8002c94: f003 0303 and.w r3, r3, #3 + 8002c98: 2b02 cmp r3, #2 + 8002c9a: d130 bne.n 8002cfe + { + /* Check the Speed parameter */ + assert_param(IS_GPIO_SPEED(GPIO_Init->Speed)); + /* Configure the IO Speed */ + temp = GPIOx->OSPEEDR; + 8002c9c: 687b ldr r3, [r7, #4] + 8002c9e: 689b ldr r3, [r3, #8] + 8002ca0: 613b str r3, [r7, #16] + temp &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 8002ca2: 697b ldr r3, [r7, #20] + 8002ca4: 005b lsls r3, r3, #1 + 8002ca6: 2203 movs r2, #3 + 8002ca8: fa02 f303 lsl.w r3, r2, r3 + 8002cac: 43db mvns r3, r3 + 8002cae: 693a ldr r2, [r7, #16] + 8002cb0: 4013 ands r3, r2 + 8002cb2: 613b str r3, [r7, #16] + temp |= (GPIO_Init->Speed << (position * 2U)); + 8002cb4: 683b ldr r3, [r7, #0] + 8002cb6: 68da ldr r2, [r3, #12] + 8002cb8: 697b ldr r3, [r7, #20] + 8002cba: 005b lsls r3, r3, #1 + 8002cbc: fa02 f303 lsl.w r3, r2, r3 + 8002cc0: 693a ldr r2, [r7, #16] + 8002cc2: 4313 orrs r3, r2 + 8002cc4: 613b str r3, [r7, #16] + GPIOx->OSPEEDR = temp; + 8002cc6: 687b ldr r3, [r7, #4] + 8002cc8: 693a ldr r2, [r7, #16] + 8002cca: 609a str r2, [r3, #8] + + /* Configure the IO Output Type */ + temp = GPIOx->OTYPER; + 8002ccc: 687b ldr r3, [r7, #4] + 8002cce: 685b ldr r3, [r3, #4] + 8002cd0: 613b str r3, [r7, #16] + temp &= ~(GPIO_OTYPER_OT0 << position) ; + 8002cd2: 2201 movs r2, #1 + 8002cd4: 697b ldr r3, [r7, #20] + 8002cd6: fa02 f303 lsl.w r3, r2, r3 + 8002cda: 43db mvns r3, r3 + 8002cdc: 693a ldr r2, [r7, #16] + 8002cde: 4013 ands r3, r2 + 8002ce0: 613b str r3, [r7, #16] + temp |= (((GPIO_Init->Mode & OUTPUT_TYPE) >> OUTPUT_TYPE_Pos) << position); + 8002ce2: 683b ldr r3, [r7, #0] + 8002ce4: 685b ldr r3, [r3, #4] + 8002ce6: 091b lsrs r3, r3, #4 + 8002ce8: f003 0201 and.w r2, r3, #1 + 8002cec: 697b ldr r3, [r7, #20] + 8002cee: fa02 f303 lsl.w r3, r2, r3 + 8002cf2: 693a ldr r2, [r7, #16] + 8002cf4: 4313 orrs r3, r2 + 8002cf6: 613b str r3, [r7, #16] + GPIOx->OTYPER = temp; + 8002cf8: 687b ldr r3, [r7, #4] + 8002cfa: 693a ldr r2, [r7, #16] + 8002cfc: 605a str r2, [r3, #4] + } + + /* Activate the Pull-up or Pull down resistor for the current IO */ + if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + 8002cfe: 683b ldr r3, [r7, #0] + 8002d00: 685b ldr r3, [r3, #4] + 8002d02: f003 0303 and.w r3, r3, #3 + 8002d06: 2b03 cmp r3, #3 + 8002d08: d017 beq.n 8002d3a + { + temp = GPIOx->PUPDR; + 8002d0a: 687b ldr r3, [r7, #4] + 8002d0c: 68db ldr r3, [r3, #12] + 8002d0e: 613b str r3, [r7, #16] + temp &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 8002d10: 697b ldr r3, [r7, #20] + 8002d12: 005b lsls r3, r3, #1 + 8002d14: 2203 movs r2, #3 + 8002d16: fa02 f303 lsl.w r3, r2, r3 + 8002d1a: 43db mvns r3, r3 + 8002d1c: 693a ldr r2, [r7, #16] + 8002d1e: 4013 ands r3, r2 + 8002d20: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Pull) << (position * 2U)); + 8002d22: 683b ldr r3, [r7, #0] + 8002d24: 689a ldr r2, [r3, #8] + 8002d26: 697b ldr r3, [r7, #20] + 8002d28: 005b lsls r3, r3, #1 + 8002d2a: fa02 f303 lsl.w r3, r2, r3 + 8002d2e: 693a ldr r2, [r7, #16] + 8002d30: 4313 orrs r3, r2 + 8002d32: 613b str r3, [r7, #16] + GPIOx->PUPDR = temp; + 8002d34: 687b ldr r3, [r7, #4] + 8002d36: 693a ldr r2, [r7, #16] + 8002d38: 60da str r2, [r3, #12] + } + + /* In case of Alternate function mode selection */ + if ((GPIO_Init->Mode & GPIO_MODE) == MODE_AF) + 8002d3a: 683b ldr r3, [r7, #0] + 8002d3c: 685b ldr r3, [r3, #4] + 8002d3e: f003 0303 and.w r3, r3, #3 + 8002d42: 2b02 cmp r3, #2 + 8002d44: d123 bne.n 8002d8e + /* Check the Alternate function parameters */ + assert_param(IS_GPIO_AF_INSTANCE(GPIOx)); + assert_param(IS_GPIO_AF(GPIO_Init->Alternate)); + + /* Configure Alternate function mapped with the current IO */ + temp = GPIOx->AFR[position >> 3U]; + 8002d46: 697b ldr r3, [r7, #20] + 8002d48: 08da lsrs r2, r3, #3 + 8002d4a: 687b ldr r3, [r7, #4] + 8002d4c: 3208 adds r2, #8 + 8002d4e: f853 3022 ldr.w r3, [r3, r2, lsl #2] + 8002d52: 613b str r3, [r7, #16] + temp &= ~(0xFU << ((position & 0x07U) * 4U)); + 8002d54: 697b ldr r3, [r7, #20] + 8002d56: f003 0307 and.w r3, r3, #7 + 8002d5a: 009b lsls r3, r3, #2 + 8002d5c: 220f movs r2, #15 + 8002d5e: fa02 f303 lsl.w r3, r2, r3 + 8002d62: 43db mvns r3, r3 + 8002d64: 693a ldr r2, [r7, #16] + 8002d66: 4013 ands r3, r2 + 8002d68: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Alternate) << ((position & 0x07U) * 4U)); + 8002d6a: 683b ldr r3, [r7, #0] + 8002d6c: 691a ldr r2, [r3, #16] + 8002d6e: 697b ldr r3, [r7, #20] + 8002d70: f003 0307 and.w r3, r3, #7 + 8002d74: 009b lsls r3, r3, #2 + 8002d76: fa02 f303 lsl.w r3, r2, r3 + 8002d7a: 693a ldr r2, [r7, #16] + 8002d7c: 4313 orrs r3, r2 + 8002d7e: 613b str r3, [r7, #16] + GPIOx->AFR[position >> 3u] = temp; + 8002d80: 697b ldr r3, [r7, #20] + 8002d82: 08da lsrs r2, r3, #3 + 8002d84: 687b ldr r3, [r7, #4] + 8002d86: 3208 adds r2, #8 + 8002d88: 6939 ldr r1, [r7, #16] + 8002d8a: f843 1022 str.w r1, [r3, r2, lsl #2] + } + + /* Configure IO Direction mode (Input, Output, Alternate or Analog) */ + temp = GPIOx->MODER; + 8002d8e: 687b ldr r3, [r7, #4] + 8002d90: 681b ldr r3, [r3, #0] + 8002d92: 613b str r3, [r7, #16] + temp &= ~(GPIO_MODER_MODE0 << (position * 2U)); + 8002d94: 697b ldr r3, [r7, #20] + 8002d96: 005b lsls r3, r3, #1 + 8002d98: 2203 movs r2, #3 + 8002d9a: fa02 f303 lsl.w r3, r2, r3 + 8002d9e: 43db mvns r3, r3 + 8002da0: 693a ldr r2, [r7, #16] + 8002da2: 4013 ands r3, r2 + 8002da4: 613b str r3, [r7, #16] + temp |= ((GPIO_Init->Mode & GPIO_MODE) << (position * 2U)); + 8002da6: 683b ldr r3, [r7, #0] + 8002da8: 685b ldr r3, [r3, #4] + 8002daa: f003 0203 and.w r2, r3, #3 + 8002dae: 697b ldr r3, [r7, #20] + 8002db0: 005b lsls r3, r3, #1 + 8002db2: fa02 f303 lsl.w r3, r2, r3 + 8002db6: 693a ldr r2, [r7, #16] + 8002db8: 4313 orrs r3, r2 + 8002dba: 613b str r3, [r7, #16] + GPIOx->MODER = temp; + 8002dbc: 687b ldr r3, [r7, #4] + 8002dbe: 693a ldr r2, [r7, #16] + 8002dc0: 601a str r2, [r3, #0] + + /*--------------------- EXTI Mode Configuration ------------------------*/ + /* Configure the External Interrupt or event for the current IO */ + if ((GPIO_Init->Mode & EXTI_MODE) != 0x00u) + 8002dc2: 683b ldr r3, [r7, #0] + 8002dc4: 685b ldr r3, [r3, #4] + 8002dc6: f403 3340 and.w r3, r3, #196608 ; 0x30000 + 8002dca: 2b00 cmp r3, #0 + 8002dcc: f000 808c beq.w 8002ee8 + { + temp = SYSCFG->EXTICR[position >> 2u]; + 8002dd0: 4a4e ldr r2, [pc, #312] ; (8002f0c ) + 8002dd2: 697b ldr r3, [r7, #20] + 8002dd4: 089b lsrs r3, r3, #2 + 8002dd6: 3302 adds r3, #2 + 8002dd8: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002ddc: 613b str r3, [r7, #16] + temp &= ~(0x07uL << (4U * (position & 0x03U))); + 8002dde: 697b ldr r3, [r7, #20] + 8002de0: f003 0303 and.w r3, r3, #3 + 8002de4: 009b lsls r3, r3, #2 + 8002de6: 2207 movs r2, #7 + 8002de8: fa02 f303 lsl.w r3, r2, r3 + 8002dec: 43db mvns r3, r3 + 8002dee: 693a ldr r2, [r7, #16] + 8002df0: 4013 ands r3, r2 + 8002df2: 613b str r3, [r7, #16] + temp |= (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U))); + 8002df4: 687b ldr r3, [r7, #4] + 8002df6: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 + 8002dfa: d00d beq.n 8002e18 + 8002dfc: 687b ldr r3, [r7, #4] + 8002dfe: 4a44 ldr r2, [pc, #272] ; (8002f10 ) + 8002e00: 4293 cmp r3, r2 + 8002e02: d007 beq.n 8002e14 + 8002e04: 687b ldr r3, [r7, #4] + 8002e06: 4a43 ldr r2, [pc, #268] ; (8002f14 ) + 8002e08: 4293 cmp r3, r2 + 8002e0a: d101 bne.n 8002e10 + 8002e0c: 2302 movs r3, #2 + 8002e0e: e004 b.n 8002e1a + 8002e10: 2307 movs r3, #7 + 8002e12: e002 b.n 8002e1a + 8002e14: 2301 movs r3, #1 + 8002e16: e000 b.n 8002e1a + 8002e18: 2300 movs r3, #0 + 8002e1a: 697a ldr r2, [r7, #20] + 8002e1c: f002 0203 and.w r2, r2, #3 + 8002e20: 0092 lsls r2, r2, #2 + 8002e22: 4093 lsls r3, r2 + 8002e24: 693a ldr r2, [r7, #16] + 8002e26: 4313 orrs r3, r2 + 8002e28: 613b str r3, [r7, #16] + SYSCFG->EXTICR[position >> 2u] = temp; + 8002e2a: 4938 ldr r1, [pc, #224] ; (8002f0c ) + 8002e2c: 697b ldr r3, [r7, #20] + 8002e2e: 089b lsrs r3, r3, #2 + 8002e30: 3302 adds r3, #2 + 8002e32: 693a ldr r2, [r7, #16] + 8002e34: f841 2023 str.w r2, [r1, r3, lsl #2] + + /* Clear Rising Falling edge configuration */ + temp = EXTI->RTSR1; + 8002e38: 4b37 ldr r3, [pc, #220] ; (8002f18 ) + 8002e3a: 681b ldr r3, [r3, #0] + 8002e3c: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8002e3e: 68fb ldr r3, [r7, #12] + 8002e40: 43db mvns r3, r3 + 8002e42: 693a ldr r2, [r7, #16] + 8002e44: 4013 ands r3, r2 + 8002e46: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_RISING) != 0x00u) + 8002e48: 683b ldr r3, [r7, #0] + 8002e4a: 685b ldr r3, [r3, #4] + 8002e4c: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 8002e50: 2b00 cmp r3, #0 + 8002e52: d003 beq.n 8002e5c + { + temp |= iocurrent; + 8002e54: 693a ldr r2, [r7, #16] + 8002e56: 68fb ldr r3, [r7, #12] + 8002e58: 4313 orrs r3, r2 + 8002e5a: 613b str r3, [r7, #16] + } + EXTI->RTSR1 = temp; + 8002e5c: 4a2e ldr r2, [pc, #184] ; (8002f18 ) + 8002e5e: 693b ldr r3, [r7, #16] + 8002e60: 6013 str r3, [r2, #0] + + temp = EXTI->FTSR1; + 8002e62: 4b2d ldr r3, [pc, #180] ; (8002f18 ) + 8002e64: 685b ldr r3, [r3, #4] + 8002e66: 613b str r3, [r7, #16] + temp &= ~(iocurrent); + 8002e68: 68fb ldr r3, [r7, #12] + 8002e6a: 43db mvns r3, r3 + 8002e6c: 693a ldr r2, [r7, #16] + 8002e6e: 4013 ands r3, r2 + 8002e70: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & TRIGGER_FALLING) != 0x00u) + 8002e72: 683b ldr r3, [r7, #0] + 8002e74: 685b ldr r3, [r3, #4] + 8002e76: f403 1300 and.w r3, r3, #2097152 ; 0x200000 + 8002e7a: 2b00 cmp r3, #0 + 8002e7c: d003 beq.n 8002e86 + { + temp |= iocurrent; + 8002e7e: 693a ldr r2, [r7, #16] + 8002e80: 68fb ldr r3, [r7, #12] + 8002e82: 4313 orrs r3, r2 + 8002e84: 613b str r3, [r7, #16] + } + EXTI->FTSR1 = temp; + 8002e86: 4a24 ldr r2, [pc, #144] ; (8002f18 ) + 8002e88: 693b ldr r3, [r7, #16] + 8002e8a: 6053 str r3, [r2, #4] + + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + temp = EXTI->C2IMR1; +#else + temp = EXTI->IMR1; + 8002e8c: 4b22 ldr r3, [pc, #136] ; (8002f18 ) + 8002e8e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8002e92: 613b str r3, [r7, #16] +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + 8002e94: 68fb ldr r3, [r7, #12] + 8002e96: 43db mvns r3, r3 + 8002e98: 693a ldr r2, [r7, #16] + 8002e9a: 4013 ands r3, r2 + 8002e9c: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_IT) != 0x00u) + 8002e9e: 683b ldr r3, [r7, #0] + 8002ea0: 685b ldr r3, [r3, #4] + 8002ea2: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8002ea6: 2b00 cmp r3, #0 + 8002ea8: d003 beq.n 8002eb2 + { + temp |= iocurrent; + 8002eaa: 693a ldr r2, [r7, #16] + 8002eac: 68fb ldr r3, [r7, #12] + 8002eae: 4313 orrs r3, r2 + 8002eb0: 613b str r3, [r7, #16] + } +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 = temp; +#else + EXTI->IMR1 = temp; + 8002eb2: 4a19 ldr r2, [pc, #100] ; (8002f18 ) + 8002eb4: 693b ldr r3, [r7, #16] + 8002eb6: f8c2 3080 str.w r3, [r2, #128] ; 0x80 +#endif /* CORE_CM0PLUS */ + +#ifdef CORE_CM0PLUS + temp = EXTI->C2EMR1; +#else + temp = EXTI->EMR1; + 8002eba: 4b17 ldr r3, [pc, #92] ; (8002f18 ) + 8002ebc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8002ec0: 613b str r3, [r7, #16] +#endif /* CORE_CM0PLUS */ + temp &= ~(iocurrent); + 8002ec2: 68fb ldr r3, [r7, #12] + 8002ec4: 43db mvns r3, r3 + 8002ec6: 693a ldr r2, [r7, #16] + 8002ec8: 4013 ands r3, r2 + 8002eca: 613b str r3, [r7, #16] + if ((GPIO_Init->Mode & EXTI_EVT) != 0x00u) + 8002ecc: 683b ldr r3, [r7, #0] + 8002ece: 685b ldr r3, [r3, #4] + 8002ed0: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8002ed4: 2b00 cmp r3, #0 + 8002ed6: d003 beq.n 8002ee0 + { + temp |= iocurrent; + 8002ed8: 693a ldr r2, [r7, #16] + 8002eda: 68fb ldr r3, [r7, #12] + 8002edc: 4313 orrs r3, r2 + 8002ede: 613b str r3, [r7, #16] + } +#ifdef CORE_CM0PLUS + EXTI->C2EMR1 = temp; +#else + EXTI->EMR1 = temp; + 8002ee0: 4a0d ldr r2, [pc, #52] ; (8002f18 ) + 8002ee2: 693b ldr r3, [r7, #16] + 8002ee4: f8c2 3084 str.w r3, [r2, #132] ; 0x84 +#endif /* CORE_CM0PLUS */ + } + } + + position++; + 8002ee8: 697b ldr r3, [r7, #20] + 8002eea: 3301 adds r3, #1 + 8002eec: 617b str r3, [r7, #20] + while (((GPIO_Init->Pin) >> position) != 0x00u) + 8002eee: 683b ldr r3, [r7, #0] + 8002ef0: 681a ldr r2, [r3, #0] + 8002ef2: 697b ldr r3, [r7, #20] + 8002ef4: fa22 f303 lsr.w r3, r2, r3 + 8002ef8: 2b00 cmp r3, #0 + 8002efa: f47f aeb7 bne.w 8002c6c + } +} + 8002efe: bf00 nop + 8002f00: bf00 nop + 8002f02: 371c adds r7, #28 + 8002f04: 46bd mov sp, r7 + 8002f06: bc80 pop {r7} + 8002f08: 4770 bx lr + 8002f0a: bf00 nop + 8002f0c: 40010000 .word 0x40010000 + 8002f10: 48000400 .word 0x48000400 + 8002f14: 48000800 .word 0x48000800 + 8002f18: 58000800 .word 0x58000800 + +08002f1c : + * @param GPIO_Pin specifies the port bit to be written. + * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) +{ + 8002f1c: b480 push {r7} + 8002f1e: b087 sub sp, #28 + 8002f20: af00 add r7, sp, #0 + 8002f22: 6078 str r0, [r7, #4] + 8002f24: 6039 str r1, [r7, #0] + uint32_t position = 0x00u; + 8002f26: 2300 movs r3, #0 + 8002f28: 617b str r3, [r7, #20] + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* Configure the port pins */ + while ((GPIO_Pin >> position) != 0x00u) + 8002f2a: e0af b.n 800308c + { + /* Get current io position */ + iocurrent = (GPIO_Pin) & (1uL << position); + 8002f2c: 2201 movs r2, #1 + 8002f2e: 697b ldr r3, [r7, #20] + 8002f30: fa02 f303 lsl.w r3, r2, r3 + 8002f34: 683a ldr r2, [r7, #0] + 8002f36: 4013 ands r3, r2 + 8002f38: 613b str r3, [r7, #16] + + if (iocurrent != 0x00u) + 8002f3a: 693b ldr r3, [r7, #16] + 8002f3c: 2b00 cmp r3, #0 + 8002f3e: f000 80a2 beq.w 8003086 + { + /*------------------------- EXTI Mode Configuration --------------------*/ + /* Clear the External Interrupt or Event for the current IO */ + + tmp = SYSCFG->EXTICR[position >> 2u]; + 8002f42: 4a59 ldr r2, [pc, #356] ; (80030a8 ) + 8002f44: 697b ldr r3, [r7, #20] + 8002f46: 089b lsrs r3, r3, #2 + 8002f48: 3302 adds r3, #2 + 8002f4a: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8002f4e: 60fb str r3, [r7, #12] + tmp &= (0x07uL << (4U * (position & 0x03U))); + 8002f50: 697b ldr r3, [r7, #20] + 8002f52: f003 0303 and.w r3, r3, #3 + 8002f56: 009b lsls r3, r3, #2 + 8002f58: 2207 movs r2, #7 + 8002f5a: fa02 f303 lsl.w r3, r2, r3 + 8002f5e: 68fa ldr r2, [r7, #12] + 8002f60: 4013 ands r3, r2 + 8002f62: 60fb str r3, [r7, #12] + if (tmp == (GPIO_GET_INDEX(GPIOx) << (4U * (position & 0x03U)))) + 8002f64: 687b ldr r3, [r7, #4] + 8002f66: f1b3 4f90 cmp.w r3, #1207959552 ; 0x48000000 + 8002f6a: d00d beq.n 8002f88 + 8002f6c: 687b ldr r3, [r7, #4] + 8002f6e: 4a4f ldr r2, [pc, #316] ; (80030ac ) + 8002f70: 4293 cmp r3, r2 + 8002f72: d007 beq.n 8002f84 + 8002f74: 687b ldr r3, [r7, #4] + 8002f76: 4a4e ldr r2, [pc, #312] ; (80030b0 ) + 8002f78: 4293 cmp r3, r2 + 8002f7a: d101 bne.n 8002f80 + 8002f7c: 2302 movs r3, #2 + 8002f7e: e004 b.n 8002f8a + 8002f80: 2307 movs r3, #7 + 8002f82: e002 b.n 8002f8a + 8002f84: 2301 movs r3, #1 + 8002f86: e000 b.n 8002f8a + 8002f88: 2300 movs r3, #0 + 8002f8a: 697a ldr r2, [r7, #20] + 8002f8c: f002 0203 and.w r2, r2, #3 + 8002f90: 0092 lsls r2, r2, #2 + 8002f92: 4093 lsls r3, r2 + 8002f94: 68fa ldr r2, [r7, #12] + 8002f96: 429a cmp r2, r3 + 8002f98: d136 bne.n 8003008 + /* Clear EXTI line configuration */ +#ifdef CORE_CM0PLUS + EXTI->C2IMR1 &= ~(iocurrent); + EXTI->C2EMR1 &= ~(iocurrent); +#else + EXTI->IMR1 &= ~(iocurrent); + 8002f9a: 4b46 ldr r3, [pc, #280] ; (80030b4 ) + 8002f9c: f8d3 2080 ldr.w r2, [r3, #128] ; 0x80 + 8002fa0: 693b ldr r3, [r7, #16] + 8002fa2: 43db mvns r3, r3 + 8002fa4: 4943 ldr r1, [pc, #268] ; (80030b4 ) + 8002fa6: 4013 ands r3, r2 + 8002fa8: f8c1 3080 str.w r3, [r1, #128] ; 0x80 + EXTI->EMR1 &= ~(iocurrent); + 8002fac: 4b41 ldr r3, [pc, #260] ; (80030b4 ) + 8002fae: f8d3 2084 ldr.w r2, [r3, #132] ; 0x84 + 8002fb2: 693b ldr r3, [r7, #16] + 8002fb4: 43db mvns r3, r3 + 8002fb6: 493f ldr r1, [pc, #252] ; (80030b4 ) + 8002fb8: 4013 ands r3, r2 + 8002fba: f8c1 3084 str.w r3, [r1, #132] ; 0x84 +#endif /* CORE_CM0PLUS */ + + /* Clear Rising Falling edge configuration */ + EXTI->RTSR1 &= ~(iocurrent); + 8002fbe: 4b3d ldr r3, [pc, #244] ; (80030b4 ) + 8002fc0: 681a ldr r2, [r3, #0] + 8002fc2: 693b ldr r3, [r7, #16] + 8002fc4: 43db mvns r3, r3 + 8002fc6: 493b ldr r1, [pc, #236] ; (80030b4 ) + 8002fc8: 4013 ands r3, r2 + 8002fca: 600b str r3, [r1, #0] + EXTI->FTSR1 &= ~(iocurrent); + 8002fcc: 4b39 ldr r3, [pc, #228] ; (80030b4 ) + 8002fce: 685a ldr r2, [r3, #4] + 8002fd0: 693b ldr r3, [r7, #16] + 8002fd2: 43db mvns r3, r3 + 8002fd4: 4937 ldr r1, [pc, #220] ; (80030b4 ) + 8002fd6: 4013 ands r3, r2 + 8002fd8: 604b str r3, [r1, #4] + + /* Clear EXTICR configuration */ + tmp = 0x07uL << (4u * (position & 0x03U)); + 8002fda: 697b ldr r3, [r7, #20] + 8002fdc: f003 0303 and.w r3, r3, #3 + 8002fe0: 009b lsls r3, r3, #2 + 8002fe2: 2207 movs r2, #7 + 8002fe4: fa02 f303 lsl.w r3, r2, r3 + 8002fe8: 60fb str r3, [r7, #12] + SYSCFG->EXTICR[position >> 2u] &= ~tmp; + 8002fea: 4a2f ldr r2, [pc, #188] ; (80030a8 ) + 8002fec: 697b ldr r3, [r7, #20] + 8002fee: 089b lsrs r3, r3, #2 + 8002ff0: 3302 adds r3, #2 + 8002ff2: f852 1023 ldr.w r1, [r2, r3, lsl #2] + 8002ff6: 68fb ldr r3, [r7, #12] + 8002ff8: 43da mvns r2, r3 + 8002ffa: 482b ldr r0, [pc, #172] ; (80030a8 ) + 8002ffc: 697b ldr r3, [r7, #20] + 8002ffe: 089b lsrs r3, r3, #2 + 8003000: 400a ands r2, r1 + 8003002: 3302 adds r3, #2 + 8003004: f840 2023 str.w r2, [r0, r3, lsl #2] + } + + /*------------------------- GPIO Mode Configuration --------------------*/ + /* Configure IO in Analog Mode */ + GPIOx->MODER |= (GPIO_MODER_MODE0 << (position * 2U)); + 8003008: 687b ldr r3, [r7, #4] + 800300a: 681a ldr r2, [r3, #0] + 800300c: 697b ldr r3, [r7, #20] + 800300e: 005b lsls r3, r3, #1 + 8003010: 2103 movs r1, #3 + 8003012: fa01 f303 lsl.w r3, r1, r3 + 8003016: 431a orrs r2, r3 + 8003018: 687b ldr r3, [r7, #4] + 800301a: 601a str r2, [r3, #0] + + /* Configure the default Alternate Function in current IO */ + GPIOx->AFR[position >> 3U] &= ~(0xFU << ((position & 0x07U) * 4U)) ; + 800301c: 697b ldr r3, [r7, #20] + 800301e: 08da lsrs r2, r3, #3 + 8003020: 687b ldr r3, [r7, #4] + 8003022: 3208 adds r2, #8 + 8003024: f853 1022 ldr.w r1, [r3, r2, lsl #2] + 8003028: 697b ldr r3, [r7, #20] + 800302a: f003 0307 and.w r3, r3, #7 + 800302e: 009b lsls r3, r3, #2 + 8003030: 220f movs r2, #15 + 8003032: fa02 f303 lsl.w r3, r2, r3 + 8003036: 43db mvns r3, r3 + 8003038: 697a ldr r2, [r7, #20] + 800303a: 08d2 lsrs r2, r2, #3 + 800303c: 4019 ands r1, r3 + 800303e: 687b ldr r3, [r7, #4] + 8003040: 3208 adds r2, #8 + 8003042: f843 1022 str.w r1, [r3, r2, lsl #2] + + /* Configure the default value for IO Speed */ + GPIOx->OSPEEDR &= ~(GPIO_OSPEEDR_OSPEED0 << (position * 2U)); + 8003046: 687b ldr r3, [r7, #4] + 8003048: 689a ldr r2, [r3, #8] + 800304a: 697b ldr r3, [r7, #20] + 800304c: 005b lsls r3, r3, #1 + 800304e: 2103 movs r1, #3 + 8003050: fa01 f303 lsl.w r3, r1, r3 + 8003054: 43db mvns r3, r3 + 8003056: 401a ands r2, r3 + 8003058: 687b ldr r3, [r7, #4] + 800305a: 609a str r2, [r3, #8] + + /* Configure the default value IO Output Type */ + GPIOx->OTYPER &= ~(GPIO_OTYPER_OT0 << position) ; + 800305c: 687b ldr r3, [r7, #4] + 800305e: 685a ldr r2, [r3, #4] + 8003060: 2101 movs r1, #1 + 8003062: 697b ldr r3, [r7, #20] + 8003064: fa01 f303 lsl.w r3, r1, r3 + 8003068: 43db mvns r3, r3 + 800306a: 401a ands r2, r3 + 800306c: 687b ldr r3, [r7, #4] + 800306e: 605a str r2, [r3, #4] + + /* Deactivate the Pull-up and Pull-down resistor for the current IO */ + GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPD0 << (position * 2U)); + 8003070: 687b ldr r3, [r7, #4] + 8003072: 68da ldr r2, [r3, #12] + 8003074: 697b ldr r3, [r7, #20] + 8003076: 005b lsls r3, r3, #1 + 8003078: 2103 movs r1, #3 + 800307a: fa01 f303 lsl.w r3, r1, r3 + 800307e: 43db mvns r3, r3 + 8003080: 401a ands r2, r3 + 8003082: 687b ldr r3, [r7, #4] + 8003084: 60da str r2, [r3, #12] + } + + position++; + 8003086: 697b ldr r3, [r7, #20] + 8003088: 3301 adds r3, #1 + 800308a: 617b str r3, [r7, #20] + while ((GPIO_Pin >> position) != 0x00u) + 800308c: 683a ldr r2, [r7, #0] + 800308e: 697b ldr r3, [r7, #20] + 8003090: fa22 f303 lsr.w r3, r2, r3 + 8003094: 2b00 cmp r3, #0 + 8003096: f47f af49 bne.w 8002f2c + } +} + 800309a: bf00 nop + 800309c: bf00 nop + 800309e: 371c adds r7, #28 + 80030a0: 46bd mov sp, r7 + 80030a2: bc80 pop {r7} + 80030a4: 4770 bx lr + 80030a6: bf00 nop + 80030a8: 40010000 .word 0x40010000 + 80030ac: 48000400 .word 0x48000400 + 80030b0: 48000800 .word 0x48000800 + 80030b4: 58000800 .word 0x58000800 + +080030b8 : + * @arg GPIO_PIN_RESET: to clear the port pin + * @arg GPIO_PIN_SET: to set the port pin + * @retval None + */ +void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState) +{ + 80030b8: b480 push {r7} + 80030ba: b083 sub sp, #12 + 80030bc: af00 add r7, sp, #0 + 80030be: 6078 str r0, [r7, #4] + 80030c0: 460b mov r3, r1 + 80030c2: 807b strh r3, [r7, #2] + 80030c4: 4613 mov r3, r2 + 80030c6: 707b strb r3, [r7, #1] + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + assert_param(IS_GPIO_PIN_ACTION(PinState)); + + if (PinState != GPIO_PIN_RESET) + 80030c8: 787b ldrb r3, [r7, #1] + 80030ca: 2b00 cmp r3, #0 + 80030cc: d003 beq.n 80030d6 + { + GPIOx->BSRR = (uint32_t)GPIO_Pin; + 80030ce: 887a ldrh r2, [r7, #2] + 80030d0: 687b ldr r3, [r7, #4] + 80030d2: 619a str r2, [r3, #24] + } + else + { + GPIOx->BRR = (uint32_t)GPIO_Pin; + } +} + 80030d4: e002 b.n 80030dc + GPIOx->BRR = (uint32_t)GPIO_Pin; + 80030d6: 887a ldrh r2, [r7, #2] + 80030d8: 687b ldr r3, [r7, #4] + 80030da: 629a str r2, [r3, #40] ; 0x28 +} + 80030dc: bf00 nop + 80030de: 370c adds r7, #12 + 80030e0: 46bd mov sp, r7 + 80030e2: bc80 pop {r7} + 80030e4: 4770 bx lr + +080030e6 : + * @param GPIO_Pin specifies the pin to be toggled. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * @retval None + */ +void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + 80030e6: b480 push {r7} + 80030e8: b085 sub sp, #20 + 80030ea: af00 add r7, sp, #0 + 80030ec: 6078 str r0, [r7, #4] + 80030ee: 460b mov r3, r1 + 80030f0: 807b strh r3, [r7, #2] + + /* Check the parameters */ + assert_param(IS_GPIO_PIN(GPIO_Pin)); + + /* get current Output Data Register value */ + odr = GPIOx->ODR; + 80030f2: 687b ldr r3, [r7, #4] + 80030f4: 695b ldr r3, [r3, #20] + 80030f6: 60fb str r3, [r7, #12] + + /* Set selected pins that were at low level, and reset ones that were high */ + GPIOx->BSRR = ((odr & GPIO_Pin) << GPIO_NUMBER) | (~odr & GPIO_Pin); + 80030f8: 887a ldrh r2, [r7, #2] + 80030fa: 68fb ldr r3, [r7, #12] + 80030fc: 4013 ands r3, r2 + 80030fe: 041a lsls r2, r3, #16 + 8003100: 68fb ldr r3, [r7, #12] + 8003102: 43d9 mvns r1, r3 + 8003104: 887b ldrh r3, [r7, #2] + 8003106: 400b ands r3, r1 + 8003108: 431a orrs r2, r3 + 800310a: 687b ldr r3, [r7, #4] + 800310c: 619a str r2, [r3, #24] +} + 800310e: bf00 nop + 8003110: 3714 adds r7, #20 + 8003112: 46bd mov sp, r7 + 8003114: bc80 pop {r7} + 8003116: 4770 bx lr + +08003118 : + * @note LSEON bit that switches on and off the LSE crystal belongs as well to the + * backup domain. + * @retval None + */ +void HAL_PWR_EnableBkUpAccess(void) +{ + 8003118: b480 push {r7} + 800311a: af00 add r7, sp, #0 + SET_BIT(PWR->CR1, PWR_CR1_DBP); + 800311c: 4b04 ldr r3, [pc, #16] ; (8003130 ) + 800311e: 681b ldr r3, [r3, #0] + 8003120: 4a03 ldr r2, [pc, #12] ; (8003130 ) + 8003122: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8003126: 6013 str r3, [r2, #0] +} + 8003128: bf00 nop + 800312a: 46bd mov sp, r7 + 800312c: bc80 pop {r7} + 800312e: 4770 bx lr + 8003130: 58000400 .word 0x58000400 + +08003134 : + * @note When WFI entry is used, tick interrupt have to be disabled if not desired as + * the interrupt wake up source. + * @retval None + */ +void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry) +{ + 8003134: b580 push {r7, lr} + 8003136: b082 sub sp, #8 + 8003138: af00 add r7, sp, #0 + 800313a: 6078 str r0, [r7, #4] + 800313c: 460b mov r3, r1 + 800313e: 70fb strb r3, [r7, #3] + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry)); + + /* Set Regulator parameter */ + if (Regulator == PWR_MAINREGULATOR_ON) + 8003140: 687b ldr r3, [r7, #4] + 8003142: 2b00 cmp r3, #0 + 8003144: d10c bne.n 8003160 + { + /* If in low-power run mode at this point, exit it */ + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + 8003146: 4b13 ldr r3, [pc, #76] ; (8003194 ) + 8003148: 695b ldr r3, [r3, #20] + 800314a: f403 7300 and.w r3, r3, #512 ; 0x200 + 800314e: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8003152: d10d bne.n 8003170 + { + if (HAL_PWREx_DisableLowPowerRunMode() != HAL_OK) + 8003154: f000 f854 bl 8003200 + 8003158: 4603 mov r3, r0 + 800315a: 2b00 cmp r3, #0 + 800315c: d008 beq.n 8003170 + { + return ; + 800315e: e015 b.n 800318c + } + else + { + /* If in run mode, first move to low-power run mode. + The system clock frequency must be below 2 MHz at this point. */ + if (HAL_IS_BIT_CLR(PWR->SR2, (PWR_SR2_REGLPF))) + 8003160: 4b0c ldr r3, [pc, #48] ; (8003194 ) + 8003162: 695b ldr r3, [r3, #20] + 8003164: f403 7300 and.w r3, r3, #512 ; 0x200 + 8003168: 2b00 cmp r3, #0 + 800316a: d101 bne.n 8003170 + { + HAL_PWREx_EnableLowPowerRunMode(); + 800316c: f000 f83a bl 80031e4 + } + } + + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8003170: 4b09 ldr r3, [pc, #36] ; (8003198 ) + 8003172: 691b ldr r3, [r3, #16] + 8003174: 4a08 ldr r2, [pc, #32] ; (8003198 ) + 8003176: f023 0304 bic.w r3, r3, #4 + 800317a: 6113 str r3, [r2, #16] + + /* Select SLEEP mode entry -------------------------------------------------*/ + if (SLEEPEntry == PWR_SLEEPENTRY_WFI) + 800317c: 78fb ldrb r3, [r7, #3] + 800317e: 2b01 cmp r3, #1 + 8003180: d101 bne.n 8003186 + { + /* Request Wait For Interrupt */ + __WFI(); + 8003182: bf30 wfi + 8003184: e002 b.n 800318c + } + else + { + /* Request Wait For Event */ + __SEV(); + 8003186: bf40 sev + __WFE(); + 8003188: bf20 wfe + __WFE(); + 800318a: bf20 wfe + } +} + 800318c: 3708 adds r7, #8 + 800318e: 46bd mov sp, r7 + 8003190: bd80 pop {r7, pc} + 8003192: bf00 nop + 8003194: 58000400 .word 0x58000400 + 8003198: e000ed00 .word 0xe000ed00 + +0800319c : + * @arg @ref PWR_STOPENTRY_WFI Enter Stop 0 or Stop 1 mode with WFI instruction. + * @arg @ref PWR_STOPENTRY_WFE Enter Stop 0 or Stop 1 mode with WFE instruction. + * @retval None + */ +void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry) +{ + 800319c: b580 push {r7, lr} + 800319e: b082 sub sp, #8 + 80031a0: af00 add r7, sp, #0 + 80031a2: 6078 str r0, [r7, #4] + 80031a4: 460b mov r3, r1 + 80031a6: 70fb strb r3, [r7, #3] + /* Check the parameters */ + assert_param(IS_PWR_REGULATOR(Regulator)); + + if (Regulator == PWR_LOWPOWERREGULATOR_ON) + 80031a8: 687b ldr r3, [r7, #4] + 80031aa: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 80031ae: d104 bne.n 80031ba + { + HAL_PWREx_EnterSTOP1Mode(STOPEntry); + 80031b0: 78fb ldrb r3, [r7, #3] + 80031b2: 4618 mov r0, r3 + 80031b4: f000 f882 bl 80032bc + } + else + { + HAL_PWREx_EnterSTOP0Mode(STOPEntry); + } +} + 80031b8: e003 b.n 80031c2 + HAL_PWREx_EnterSTOP0Mode(STOPEntry); + 80031ba: 78fb ldrb r3, [r7, #3] + 80031bc: 4618 mov r0, r3 + 80031be: f000 f855 bl 800326c +} + 80031c2: bf00 nop + 80031c4: 3708 adds r7, #8 + 80031c6: 46bd mov sp, r7 + 80031c8: bd80 pop {r7, pc} + ... + +080031cc : +/** + * @brief Return Voltage Scaling Range. + * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_SCALE1 or PWPWR_REGULATOR_VOLTAGE_SCALE2) + */ +uint32_t HAL_PWREx_GetVoltageRange(void) +{ + 80031cc: b480 push {r7} + 80031ce: af00 add r7, sp, #0 + return (PWR->CR1 & PWR_CR1_VOS); + 80031d0: 4b03 ldr r3, [pc, #12] ; (80031e0 ) + 80031d2: 681b ldr r3, [r3, #0] + 80031d4: f403 63c0 and.w r3, r3, #1536 ; 0x600 +} + 80031d8: 4618 mov r0, r3 + 80031da: 46bd mov sp, r7 + 80031dc: bc80 pop {r7} + 80031de: 4770 bx lr + 80031e0: 58000400 .word 0x58000400 + +080031e4 : + * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. + * @note Clock frequency must be reduced below 2 MHz. + * @retval None + */ +void HAL_PWREx_EnableLowPowerRunMode(void) +{ + 80031e4: b480 push {r7} + 80031e6: af00 add r7, sp, #0 + /* Set Regulator parameter */ + SET_BIT(PWR->CR1, PWR_CR1_LPR); + 80031e8: 4b04 ldr r3, [pc, #16] ; (80031fc ) + 80031ea: 681b ldr r3, [r3, #0] + 80031ec: 4a03 ldr r2, [pc, #12] ; (80031fc ) + 80031ee: f443 4380 orr.w r3, r3, #16384 ; 0x4000 + 80031f2: 6013 str r3, [r2, #0] +} + 80031f4: bf00 nop + 80031f6: 46bd mov sp, r7 + 80031f8: bc80 pop {r7} + 80031fa: 4770 bx lr + 80031fc: 58000400 .word 0x58000400 + +08003200 : + * returns HAL_TIMEOUT status). The system clock frequency can then be + * increased above 2 MHz. + * @retval HAL Status + */ +HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) +{ + 8003200: b480 push {r7} + 8003202: b083 sub sp, #12 + 8003204: af00 add r7, sp, #0 + uint32_t wait_loop_index; + + /* Clear LPR bit */ + CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); + 8003206: 4b16 ldr r3, [pc, #88] ; (8003260 ) + 8003208: 681b ldr r3, [r3, #0] + 800320a: 4a15 ldr r2, [pc, #84] ; (8003260 ) + 800320c: f423 4380 bic.w r3, r3, #16384 ; 0x4000 + 8003210: 6013 str r3, [r2, #0] + + /* Wait until REGLPF is reset */ + wait_loop_index = ((PWR_FLAG_SETTING_DELAY_US * SystemCoreClock) / 1000000UL); + 8003212: 4b14 ldr r3, [pc, #80] ; (8003264 ) + 8003214: 681b ldr r3, [r3, #0] + 8003216: 2232 movs r2, #50 ; 0x32 + 8003218: fb02 f303 mul.w r3, r2, r3 + 800321c: 4a12 ldr r2, [pc, #72] ; (8003268 ) + 800321e: fba2 2303 umull r2, r3, r2, r3 + 8003222: 0c9b lsrs r3, r3, #18 + 8003224: 607b str r3, [r7, #4] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + 8003226: e002 b.n 800322e + { + wait_loop_index--; + 8003228: 687b ldr r3, [r7, #4] + 800322a: 3b01 subs r3, #1 + 800322c: 607b str r3, [r7, #4] + while ((HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) && (wait_loop_index != 0U)) + 800322e: 4b0c ldr r3, [pc, #48] ; (8003260 ) + 8003230: 695b ldr r3, [r3, #20] + 8003232: f403 7300 and.w r3, r3, #512 ; 0x200 + 8003236: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800323a: d102 bne.n 8003242 + 800323c: 687b ldr r3, [r7, #4] + 800323e: 2b00 cmp r3, #0 + 8003240: d1f2 bne.n 8003228 + } + if (HAL_IS_BIT_SET(PWR->SR2, (PWR_SR2_REGLPF))) + 8003242: 4b07 ldr r3, [pc, #28] ; (8003260 ) + 8003244: 695b ldr r3, [r3, #20] + 8003246: f403 7300 and.w r3, r3, #512 ; 0x200 + 800324a: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800324e: d101 bne.n 8003254 + { + return HAL_TIMEOUT; + 8003250: 2303 movs r3, #3 + 8003252: e000 b.n 8003256 + } + + return HAL_OK; + 8003254: 2300 movs r3, #0 +} + 8003256: 4618 mov r0, r3 + 8003258: 370c adds r7, #12 + 800325a: 46bd mov sp, r7 + 800325c: bc80 pop {r7} + 800325e: 4770 bx lr + 8003260: 58000400 .word 0x58000400 + 8003264: 20000000 .word 0x20000000 + 8003268: 431bde83 .word 0x431bde83 + +0800326c : + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) +{ + 800326c: b480 push {r7} + 800326e: b083 sub sp, #12 + 8003270: af00 add r7, sp, #0 + 8003272: 4603 mov r3, r0 + 8003274: 71fb strb r3, [r7, #7] + /* Stop 0 mode with Main Regulator */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + +#else + /* Stop 0 mode with Main Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP0); + 8003276: 4b0f ldr r3, [pc, #60] ; (80032b4 ) + 8003278: 681b ldr r3, [r3, #0] + 800327a: 4a0e ldr r2, [pc, #56] ; (80032b4 ) + 800327c: f023 0307 bic.w r3, r3, #7 + 8003280: 6013 str r3, [r2, #0] + +#endif + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8003282: 4b0d ldr r3, [pc, #52] ; (80032b8 ) + 8003284: 691b ldr r3, [r3, #16] + 8003286: 4a0c ldr r2, [pc, #48] ; (80032b8 ) + 8003288: f043 0304 orr.w r3, r3, #4 + 800328c: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 800328e: 79fb ldrb r3, [r7, #7] + 8003290: 2b01 cmp r3, #1 + 8003292: d101 bne.n 8003298 + { + /* Request Wait For Interrupt */ + __WFI(); + 8003294: bf30 wfi + 8003296: e002 b.n 800329e + } + else + { + /* Request Wait For Event */ + __SEV(); + 8003298: bf40 sev + __WFE(); + 800329a: bf20 wfe + __WFE(); + 800329c: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 800329e: 4b06 ldr r3, [pc, #24] ; (80032b8 ) + 80032a0: 691b ldr r3, [r3, #16] + 80032a2: 4a05 ldr r2, [pc, #20] ; (80032b8 ) + 80032a4: f023 0304 bic.w r3, r3, #4 + 80032a8: 6113 str r3, [r2, #16] +} + 80032aa: bf00 nop + 80032ac: 370c adds r7, #12 + 80032ae: 46bd mov sp, r7 + 80032b0: bc80 pop {r7} + 80032b2: 4770 bx lr + 80032b4: 58000400 .word 0x58000400 + 80032b8: e000ed00 .word 0xe000ed00 + +080032bc : + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) +{ + 80032bc: b480 push {r7} + 80032be: b083 sub sp, #12 + 80032c0: af00 add r7, sp, #0 + 80032c2: 4603 mov r3, r0 + 80032c4: 71fb strb r3, [r7, #7] +#ifdef CORE_CM0PLUS + /* Stop 1 mode with Low-Power Regulator */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP1); +#else + /* Stop 1 mode with Low-Power Regulator */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP1); + 80032c6: 4b10 ldr r3, [pc, #64] ; (8003308 ) + 80032c8: 681b ldr r3, [r3, #0] + 80032ca: f023 0307 bic.w r3, r3, #7 + 80032ce: 4a0e ldr r2, [pc, #56] ; (8003308 ) + 80032d0: f043 0301 orr.w r3, r3, #1 + 80032d4: 6013 str r3, [r2, #0] +#endif + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80032d6: 4b0d ldr r3, [pc, #52] ; (800330c ) + 80032d8: 691b ldr r3, [r3, #16] + 80032da: 4a0c ldr r2, [pc, #48] ; (800330c ) + 80032dc: f043 0304 orr.w r3, r3, #4 + 80032e0: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 80032e2: 79fb ldrb r3, [r7, #7] + 80032e4: 2b01 cmp r3, #1 + 80032e6: d101 bne.n 80032ec + { + /* Request Wait For Interrupt */ + __WFI(); + 80032e8: bf30 wfi + 80032ea: e002 b.n 80032f2 + } + else + { + /* Request Wait For Event */ + __SEV(); + 80032ec: bf40 sev + __WFE(); + 80032ee: bf20 wfe + __WFE(); + 80032f0: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 80032f2: 4b06 ldr r3, [pc, #24] ; (800330c ) + 80032f4: 691b ldr r3, [r3, #16] + 80032f6: 4a05 ldr r2, [pc, #20] ; (800330c ) + 80032f8: f023 0304 bic.w r3, r3, #4 + 80032fc: 6113 str r3, [r2, #16] +} + 80032fe: bf00 nop + 8003300: 370c adds r7, #12 + 8003302: 46bd mov sp, r7 + 8003304: bc80 pop {r7} + 8003306: 4770 bx lr + 8003308: 58000400 .word 0x58000400 + 800330c: e000ed00 .word 0xe000ed00 + +08003310 : + * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction + * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction + * @retval None + */ +void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) +{ + 8003310: b480 push {r7} + 8003312: b083 sub sp, #12 + 8003314: af00 add r7, sp, #0 + 8003316: 4603 mov r3, r0 + 8003318: 71fb strb r3, [r7, #7] +#ifdef CORE_CM0PLUS + /* Set Stop mode 2 */ + MODIFY_REG(PWR->C2CR1, PWR_C2CR1_LPMS, PWR_LOWPOWERMODE_STOP2); +#else + /* Set Stop mode 2 */ + MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_LOWPOWERMODE_STOP2); + 800331a: 4b10 ldr r3, [pc, #64] ; (800335c ) + 800331c: 681b ldr r3, [r3, #0] + 800331e: f023 0307 bic.w r3, r3, #7 + 8003322: 4a0e ldr r2, [pc, #56] ; (800335c ) + 8003324: f043 0302 orr.w r3, r3, #2 + 8003328: 6013 str r3, [r2, #0] +#endif + + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 800332a: 4b0d ldr r3, [pc, #52] ; (8003360 ) + 800332c: 691b ldr r3, [r3, #16] + 800332e: 4a0c ldr r2, [pc, #48] ; (8003360 ) + 8003330: f043 0304 orr.w r3, r3, #4 + 8003334: 6113 str r3, [r2, #16] + + /* Select Stop mode entry --------------------------------------------------*/ + if (STOPEntry == PWR_STOPENTRY_WFI) + 8003336: 79fb ldrb r3, [r7, #7] + 8003338: 2b01 cmp r3, #1 + 800333a: d101 bne.n 8003340 + { + /* Request Wait For Interrupt */ + __WFI(); + 800333c: bf30 wfi + 800333e: e002 b.n 8003346 + } + else + { + /* Request Wait For Event */ + __SEV(); + 8003340: bf40 sev + __WFE(); + 8003342: bf20 wfe + __WFE(); + 8003344: bf20 wfe + } + + /* Reset SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); + 8003346: 4b06 ldr r3, [pc, #24] ; (8003360 ) + 8003348: 691b ldr r3, [r3, #16] + 800334a: 4a05 ldr r2, [pc, #20] ; (8003360 ) + 800334c: f023 0304 bic.w r3, r3, #4 + 8003350: 6113 str r3, [r2, #16] +} + 8003352: bf00 nop + 8003354: 370c adds r7, #12 + 8003356: 46bd mov sp, r7 + 8003358: bc80 pop {r7} + 800335a: 4770 bx lr + 800335c: 58000400 .word 0x58000400 + 8003360: e000ed00 .word 0xe000ed00 + +08003364 : +{ + 8003364: b480 push {r7} + 8003366: af00 add r7, sp, #0 + return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL); + 8003368: 4b06 ldr r3, [pc, #24] ; (8003384 ) + 800336a: 681b ldr r3, [r3, #0] + 800336c: f403 7380 and.w r3, r3, #256 ; 0x100 + 8003370: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8003374: d101 bne.n 800337a + 8003376: 2301 movs r3, #1 + 8003378: e000 b.n 800337c + 800337a: 2300 movs r3, #0 +} + 800337c: 4618 mov r0, r3 + 800337e: 46bd mov sp, r7 + 8003380: bc80 pop {r7} + 8003382: 4770 bx lr + 8003384: 58000400 .word 0x58000400 + +08003388 : +{ + 8003388: b480 push {r7} + 800338a: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEBYPPWR); + 800338c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003390: 681b ldr r3, [r3, #0] + 8003392: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003396: f443 1300 orr.w r3, r3, #2097152 ; 0x200000 + 800339a: 6013 str r3, [r2, #0] +} + 800339c: bf00 nop + 800339e: 46bd mov sp, r7 + 80033a0: bc80 pop {r7} + 80033a2: 4770 bx lr + +080033a4 : +{ + 80033a4: b480 push {r7} + 80033a6: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYPPWR); + 80033a8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80033ac: 681b ldr r3, [r3, #0] + 80033ae: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80033b2: f423 1300 bic.w r3, r3, #2097152 ; 0x200000 + 80033b6: 6013 str r3, [r2, #0] +} + 80033b8: bf00 nop + 80033ba: 46bd mov sp, r7 + 80033bc: bc80 pop {r7} + 80033be: 4770 bx lr + +080033c0 : +{ + 80033c0: b480 push {r7} + 80033c2: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSEPRE) == (RCC_CR_HSEPRE)) ? 1UL : 0UL); + 80033c4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80033c8: 681b ldr r3, [r3, #0] + 80033ca: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80033ce: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 80033d2: d101 bne.n 80033d8 + 80033d4: 2301 movs r3, #1 + 80033d6: e000 b.n 80033da + 80033d8: 2300 movs r3, #0 +} + 80033da: 4618 mov r0, r3 + 80033dc: 46bd mov sp, r7 + 80033de: bc80 pop {r7} + 80033e0: 4770 bx lr + +080033e2 : +{ + 80033e2: b480 push {r7} + 80033e4: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSEON); + 80033e6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80033ea: 681b ldr r3, [r3, #0] + 80033ec: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80033f0: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80033f4: 6013 str r3, [r2, #0] +} + 80033f6: bf00 nop + 80033f8: 46bd mov sp, r7 + 80033fa: bc80 pop {r7} + 80033fc: 4770 bx lr + +080033fe : +{ + 80033fe: b480 push {r7} + 8003400: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); + 8003402: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003406: 681b ldr r3, [r3, #0] + 8003408: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800340c: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 8003410: 6013 str r3, [r2, #0] +} + 8003412: bf00 nop + 8003414: 46bd mov sp, r7 + 8003416: bc80 pop {r7} + 8003418: 4770 bx lr + +0800341a : +{ + 800341a: b480 push {r7} + 800341c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); + 800341e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003422: 681b ldr r3, [r3, #0] + 8003424: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 8003428: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 + 800342c: d101 bne.n 8003432 + 800342e: 2301 movs r3, #1 + 8003430: e000 b.n 8003434 + 8003432: 2300 movs r3, #0 +} + 8003434: 4618 mov r0, r3 + 8003436: 46bd mov sp, r7 + 8003438: bc80 pop {r7} + 800343a: 4770 bx lr + +0800343c : +{ + 800343c: b480 push {r7} + 800343e: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_HSION); + 8003440: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003444: 681b ldr r3, [r3, #0] + 8003446: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800344a: f443 7380 orr.w r3, r3, #256 ; 0x100 + 800344e: 6013 str r3, [r2, #0] +} + 8003450: bf00 nop + 8003452: 46bd mov sp, r7 + 8003454: bc80 pop {r7} + 8003456: 4770 bx lr + +08003458 : +{ + 8003458: b480 push {r7} + 800345a: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_HSION); + 800345c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003460: 681b ldr r3, [r3, #0] + 8003462: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003466: f423 7380 bic.w r3, r3, #256 ; 0x100 + 800346a: 6013 str r3, [r2, #0] +} + 800346c: bf00 nop + 800346e: 46bd mov sp, r7 + 8003470: bc80 pop {r7} + 8003472: 4770 bx lr + +08003474 : +{ + 8003474: b480 push {r7} + 8003476: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); + 8003478: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800347c: 681b ldr r3, [r3, #0] + 800347e: f403 6380 and.w r3, r3, #1024 ; 0x400 + 8003482: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 8003486: d101 bne.n 800348c + 8003488: 2301 movs r3, #1 + 800348a: e000 b.n 800348e + 800348c: 2300 movs r3, #0 +} + 800348e: 4618 mov r0, r3 + 8003490: 46bd mov sp, r7 + 8003492: bc80 pop {r7} + 8003494: 4770 bx lr + +08003496 : +{ + 8003496: b480 push {r7} + 8003498: b083 sub sp, #12 + 800349a: af00 add r7, sp, #0 + 800349c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, Value << RCC_ICSCR_HSITRIM_Pos); + 800349e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80034a2: 685b ldr r3, [r3, #4] + 80034a4: f023 42fe bic.w r2, r3, #2130706432 ; 0x7f000000 + 80034a8: 687b ldr r3, [r7, #4] + 80034aa: 061b lsls r3, r3, #24 + 80034ac: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80034b0: 4313 orrs r3, r2 + 80034b2: 604b str r3, [r1, #4] +} + 80034b4: bf00 nop + 80034b6: 370c adds r7, #12 + 80034b8: 46bd mov sp, r7 + 80034ba: bc80 pop {r7} + 80034bc: 4770 bx lr + +080034be : +{ + 80034be: b480 push {r7} + 80034c0: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 80034c2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80034c6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80034ca: f003 0302 and.w r3, r3, #2 + 80034ce: 2b02 cmp r3, #2 + 80034d0: d101 bne.n 80034d6 + 80034d2: 2301 movs r3, #1 + 80034d4: e000 b.n 80034d8 + 80034d6: 2300 movs r3, #0 +} + 80034d8: 4618 mov r0, r3 + 80034da: 46bd mov sp, r7 + 80034dc: bc80 pop {r7} + 80034de: 4770 bx lr + +080034e0 : +{ + 80034e0: b480 push {r7} + 80034e2: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_LSION); + 80034e4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80034e8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80034ec: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80034f0: f043 0301 orr.w r3, r3, #1 + 80034f4: f8c2 3094 str.w r3, [r2, #148] ; 0x94 +} + 80034f8: bf00 nop + 80034fa: 46bd mov sp, r7 + 80034fc: bc80 pop {r7} + 80034fe: 4770 bx lr + +08003500 : +{ + 8003500: b480 push {r7} + 8003502: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); + 8003504: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003508: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800350c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003510: f023 0301 bic.w r3, r3, #1 + 8003514: f8c2 3094 str.w r3, [r2, #148] ; 0x94 +} + 8003518: bf00 nop + 800351a: 46bd mov sp, r7 + 800351c: bc80 pop {r7} + 800351e: 4770 bx lr + +08003520 : +{ + 8003520: b480 push {r7} + 8003522: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); + 8003524: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003528: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800352c: f003 0302 and.w r3, r3, #2 + 8003530: 2b02 cmp r3, #2 + 8003532: d101 bne.n 8003538 + 8003534: 2301 movs r3, #1 + 8003536: e000 b.n 800353a + 8003538: 2300 movs r3, #0 +} + 800353a: 4618 mov r0, r3 + 800353c: 46bd mov sp, r7 + 800353e: bc80 pop {r7} + 8003540: 4770 bx lr + +08003542 : +{ + 8003542: b480 push {r7} + 8003544: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_MSION); + 8003546: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800354a: 681b ldr r3, [r3, #0] + 800354c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003550: f043 0301 orr.w r3, r3, #1 + 8003554: 6013 str r3, [r2, #0] +} + 8003556: bf00 nop + 8003558: 46bd mov sp, r7 + 800355a: bc80 pop {r7} + 800355c: 4770 bx lr + +0800355e : +{ + 800355e: b480 push {r7} + 8003560: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_MSION); + 8003562: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003566: 681b ldr r3, [r3, #0] + 8003568: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800356c: f023 0301 bic.w r3, r3, #1 + 8003570: 6013 str r3, [r2, #0] +} + 8003572: bf00 nop + 8003574: 46bd mov sp, r7 + 8003576: bc80 pop {r7} + 8003578: 4770 bx lr + +0800357a : +{ + 800357a: b480 push {r7} + 800357c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRDY) == (RCC_CR_MSIRDY)) ? 1UL : 0UL); + 800357e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003582: 681b ldr r3, [r3, #0] + 8003584: f003 0302 and.w r3, r3, #2 + 8003588: 2b02 cmp r3, #2 + 800358a: d101 bne.n 8003590 + 800358c: 2301 movs r3, #1 + 800358e: e000 b.n 8003592 + 8003590: 2300 movs r3, #0 +} + 8003592: 4618 mov r0, r3 + 8003594: 46bd mov sp, r7 + 8003596: bc80 pop {r7} + 8003598: 4770 bx lr + +0800359a : +{ + 800359a: b480 push {r7} + 800359c: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_MSIRGSEL) == (RCC_CR_MSIRGSEL)) ? 1UL : 0UL); + 800359e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80035a2: 681b ldr r3, [r3, #0] + 80035a4: f003 0308 and.w r3, r3, #8 + 80035a8: 2b08 cmp r3, #8 + 80035aa: d101 bne.n 80035b0 + 80035ac: 2301 movs r3, #1 + 80035ae: e000 b.n 80035b2 + 80035b0: 2300 movs r3, #0 +} + 80035b2: 4618 mov r0, r3 + 80035b4: 46bd mov sp, r7 + 80035b6: bc80 pop {r7} + 80035b8: 4770 bx lr + +080035ba : +{ + 80035ba: b480 push {r7} + 80035bc: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_MSIRANGE)); + 80035be: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80035c2: 681b ldr r3, [r3, #0] + 80035c4: f003 03f0 and.w r3, r3, #240 ; 0xf0 +} + 80035c8: 4618 mov r0, r3 + 80035ca: 46bd mov sp, r7 + 80035cc: bc80 pop {r7} + 80035ce: 4770 bx lr + +080035d0 : +{ + 80035d0: b480 push {r7} + 80035d2: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CSR, RCC_CSR_MSISRANGE)); + 80035d4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80035d8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80035dc: f403 6370 and.w r3, r3, #3840 ; 0xf00 +} + 80035e0: 4618 mov r0, r3 + 80035e2: 46bd mov sp, r7 + 80035e4: bc80 pop {r7} + 80035e6: 4770 bx lr + +080035e8 : +{ + 80035e8: b480 push {r7} + 80035ea: b083 sub sp, #12 + 80035ec: af00 add r7, sp, #0 + 80035ee: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, Value << RCC_ICSCR_MSITRIM_Pos); + 80035f0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80035f4: 685b ldr r3, [r3, #4] + 80035f6: f423 427f bic.w r2, r3, #65280 ; 0xff00 + 80035fa: 687b ldr r3, [r7, #4] + 80035fc: 021b lsls r3, r3, #8 + 80035fe: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003602: 4313 orrs r3, r2 + 8003604: 604b str r3, [r1, #4] +} + 8003606: bf00 nop + 8003608: 370c adds r7, #12 + 800360a: 46bd mov sp, r7 + 800360c: bc80 pop {r7} + 800360e: 4770 bx lr + +08003610 : +{ + 8003610: b480 push {r7} + 8003612: b083 sub sp, #12 + 8003614: af00 add r7, sp, #0 + 8003616: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); + 8003618: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800361c: 689b ldr r3, [r3, #8] + 800361e: f023 0203 bic.w r2, r3, #3 + 8003622: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003626: 687b ldr r3, [r7, #4] + 8003628: 4313 orrs r3, r2 + 800362a: 608b str r3, [r1, #8] +} + 800362c: bf00 nop + 800362e: 370c adds r7, #12 + 8003630: 46bd mov sp, r7 + 8003632: bc80 pop {r7} + 8003634: 4770 bx lr + +08003636 : +{ + 8003636: b480 push {r7} + 8003638: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); + 800363a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800363e: 689b ldr r3, [r3, #8] + 8003640: f003 030c and.w r3, r3, #12 +} + 8003644: 4618 mov r0, r3 + 8003646: 46bd mov sp, r7 + 8003648: bc80 pop {r7} + 800364a: 4770 bx lr + +0800364c : +{ + 800364c: b480 push {r7} + 800364e: b083 sub sp, #12 + 8003650: af00 add r7, sp, #0 + 8003652: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); + 8003654: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003658: 689b ldr r3, [r3, #8] + 800365a: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800365e: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003662: 687b ldr r3, [r7, #4] + 8003664: 4313 orrs r3, r2 + 8003666: 608b str r3, [r1, #8] +} + 8003668: bf00 nop + 800366a: 370c adds r7, #12 + 800366c: 46bd mov sp, r7 + 800366e: bc80 pop {r7} + 8003670: 4770 bx lr + +08003672 : +{ + 8003672: b480 push {r7} + 8003674: b083 sub sp, #12 + 8003676: af00 add r7, sp, #0 + 8003678: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE, Prescaler >> 4); + 800367a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800367e: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 8003682: f023 020f bic.w r2, r3, #15 + 8003686: 687b ldr r3, [r7, #4] + 8003688: 091b lsrs r3, r3, #4 + 800368a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800368e: 4313 orrs r3, r2 + 8003690: f8c1 3108 str.w r3, [r1, #264] ; 0x108 +} + 8003694: bf00 nop + 8003696: 370c adds r7, #12 + 8003698: 46bd mov sp, r7 + 800369a: bc80 pop {r7} + 800369c: 4770 bx lr + +0800369e : +{ + 800369e: b480 push {r7} + 80036a0: b083 sub sp, #12 + 80036a2: af00 add r7, sp, #0 + 80036a4: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler); + 80036a6: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80036aa: 689b ldr r3, [r3, #8] + 80036ac: f423 62e0 bic.w r2, r3, #1792 ; 0x700 + 80036b0: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80036b4: 687b ldr r3, [r7, #4] + 80036b6: 4313 orrs r3, r2 + 80036b8: 608b str r3, [r1, #8] +} + 80036ba: bf00 nop + 80036bc: 370c adds r7, #12 + 80036be: 46bd mov sp, r7 + 80036c0: bc80 pop {r7} + 80036c2: 4770 bx lr + +080036c4 : +{ + 80036c4: b480 push {r7} + 80036c6: b083 sub sp, #12 + 80036c8: af00 add r7, sp, #0 + 80036ca: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler); + 80036cc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80036d0: 689b ldr r3, [r3, #8] + 80036d2: f423 5260 bic.w r2, r3, #14336 ; 0x3800 + 80036d6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80036da: 687b ldr r3, [r7, #4] + 80036dc: 4313 orrs r3, r2 + 80036de: 608b str r3, [r1, #8] +} + 80036e0: bf00 nop + 80036e2: 370c adds r7, #12 + 80036e4: 46bd mov sp, r7 + 80036e6: bc80 pop {r7} + 80036e8: 4770 bx lr + +080036ea : +{ + 80036ea: b480 push {r7} + 80036ec: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); + 80036ee: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80036f2: 689b ldr r3, [r3, #8] + 80036f4: f003 03f0 and.w r3, r3, #240 ; 0xf0 +} + 80036f8: 4618 mov r0, r3 + 80036fa: 46bd mov sp, r7 + 80036fc: bc80 pop {r7} + 80036fe: 4770 bx lr + +08003700 : +{ + 8003700: b480 push {r7} + 8003702: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPRE) << 4); + 8003704: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003708: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 800370c: 011b lsls r3, r3, #4 + 800370e: f003 03f0 and.w r3, r3, #240 ; 0xf0 +} + 8003712: 4618 mov r0, r3 + 8003714: 46bd mov sp, r7 + 8003716: bc80 pop {r7} + 8003718: 4770 bx lr + +0800371a : +{ + 800371a: b480 push {r7} + 800371c: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1)); + 800371e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003722: 689b ldr r3, [r3, #8] + 8003724: f403 63e0 and.w r3, r3, #1792 ; 0x700 +} + 8003728: 4618 mov r0, r3 + 800372a: 46bd mov sp, r7 + 800372c: bc80 pop {r7} + 800372e: 4770 bx lr + +08003730 : +{ + 8003730: b480 push {r7} + 8003732: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2)); + 8003734: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003738: 689b ldr r3, [r3, #8] + 800373a: f403 5360 and.w r3, r3, #14336 ; 0x3800 +} + 800373e: 4618 mov r0, r3 + 8003740: 46bd mov sp, r7 + 8003742: bc80 pop {r7} + 8003744: 4770 bx lr + +08003746 : + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + 8003746: b480 push {r7} + 8003748: af00 add r7, sp, #0 + SET_BIT(RCC->CR, RCC_CR_PLLON); + 800374a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800374e: 681b ldr r3, [r3, #0] + 8003750: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003754: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8003758: 6013 str r3, [r2, #0] +} + 800375a: bf00 nop + 800375c: 46bd mov sp, r7 + 800375e: bc80 pop {r7} + 8003760: 4770 bx lr + +08003762 : + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + 8003762: b480 push {r7} + 8003764: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); + 8003766: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800376a: 681b ldr r3, [r3, #0] + 800376c: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003770: f023 7380 bic.w r3, r3, #16777216 ; 0x1000000 + 8003774: 6013 str r3, [r2, #0] +} + 8003776: bf00 nop + 8003778: 46bd mov sp, r7 + 800377a: bc80 pop {r7} + 800377c: 4770 bx lr + +0800377e : + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + 800377e: b480 push {r7} + 8003780: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); + 8003782: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003786: 681b ldr r3, [r3, #0] + 8003788: f003 7300 and.w r3, r3, #33554432 ; 0x2000000 + 800378c: f1b3 7f00 cmp.w r3, #33554432 ; 0x2000000 + 8003790: d101 bne.n 8003796 + 8003792: 2301 movs r3, #1 + 8003794: e000 b.n 8003798 + 8003796: 2300 movs r3, #0 +} + 8003798: 4618 mov r0, r3 + 800379a: 46bd mov sp, r7 + 800379c: bc80 pop {r7} + 800379e: 4770 bx lr + +080037a0 : + * @brief Get Main PLL multiplication factor for VCO + * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN + * @retval Between 6 and 127 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void) +{ + 80037a0: b480 push {r7} + 80037a2: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos); + 80037a4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80037a8: 68db ldr r3, [r3, #12] + 80037aa: 0a1b lsrs r3, r3, #8 + 80037ac: f003 037f and.w r3, r3, #127 ; 0x7f +} + 80037b0: 4618 mov r0, r3 + 80037b2: 46bd mov sp, r7 + 80037b4: bc80 pop {r7} + 80037b6: 4770 bx lr + +080037b8 : + * @arg @ref LL_RCC_PLLR_DIV_6 + * @arg @ref LL_RCC_PLLR_DIV_7 + * @arg @ref LL_RCC_PLLR_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void) +{ + 80037b8: b480 push {r7} + 80037ba: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR)); + 80037bc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80037c0: 68db ldr r3, [r3, #12] + 80037c2: f003 4360 and.w r3, r3, #3758096384 ; 0xe0000000 +} + 80037c6: 4618 mov r0, r3 + 80037c8: 46bd mov sp, r7 + 80037ca: bc80 pop {r7} + 80037cc: 4770 bx lr + +080037ce : + * @arg @ref LL_RCC_PLLM_DIV_6 + * @arg @ref LL_RCC_PLLM_DIV_7 + * @arg @ref LL_RCC_PLLM_DIV_8 + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void) +{ + 80037ce: b480 push {r7} + 80037d0: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM)); + 80037d2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80037d6: 68db ldr r3, [r3, #12] + 80037d8: f003 0370 and.w r3, r3, #112 ; 0x70 +} + 80037dc: 4618 mov r0, r3 + 80037de: 46bd mov sp, r7 + 80037e0: bc80 pop {r7} + 80037e2: 4770 bx lr + +080037e4 : + * @arg @ref LL_RCC_PLLSOURCE_MSI + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + 80037e4: b480 push {r7} + 80037e6: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); + 80037e8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80037ec: 68db ldr r3, [r3, #12] + 80037ee: f003 0303 and.w r3, r3, #3 +} + 80037f2: 4618 mov r0, r3 + 80037f4: 46bd mov sp, r7 + 80037f6: bc80 pop {r7} + 80037f8: 4770 bx lr + +080037fa : + * @brief Check if HCLK1 prescaler flag value has been applied or not + * @rmtoll CFGR HPREF LL_RCC_IsActiveFlag_HPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HPRE(void) +{ + 80037fa: b480 push {r7} + 80037fc: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_HPREF) == (RCC_CFGR_HPREF)) ? 1UL : 0UL); + 80037fe: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003802: 689b ldr r3, [r3, #8] + 8003804: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 8003808: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 800380c: d101 bne.n 8003812 + 800380e: 2301 movs r3, #1 + 8003810: e000 b.n 8003814 + 8003812: 2300 movs r3, #0 +} + 8003814: 4618 mov r0, r3 + 8003816: 46bd mov sp, r7 + 8003818: bc80 pop {r7} + 800381a: 4770 bx lr + +0800381c : + * @brief Check if HCLK3 prescaler flag value has been applied or not + * @rmtoll EXTCFGR SHDHPREF LL_RCC_IsActiveFlag_SHDHPRE + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SHDHPRE(void) +{ + 800381c: b480 push {r7} + 800381e: af00 add r7, sp, #0 + return ((READ_BIT(RCC->EXTCFGR, RCC_EXTCFGR_SHDHPREF) == (RCC_EXTCFGR_SHDHPREF)) ? 1UL : 0UL); + 8003820: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003824: f8d3 3108 ldr.w r3, [r3, #264] ; 0x108 + 8003828: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 800382c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8003830: d101 bne.n 8003836 + 8003832: 2301 movs r3, #1 + 8003834: e000 b.n 8003838 + 8003836: 2300 movs r3, #0 +} + 8003838: 4618 mov r0, r3 + 800383a: 46bd mov sp, r7 + 800383c: bc80 pop {r7} + 800383e: 4770 bx lr + +08003840 : + * @brief Check if PLCK1 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE1F LL_RCC_IsActiveFlag_PPRE1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE1(void) +{ + 8003840: b480 push {r7} + 8003842: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1F) == (RCC_CFGR_PPRE1F)) ? 1UL : 0UL); + 8003844: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003848: 689b ldr r3, [r3, #8] + 800384a: f403 3300 and.w r3, r3, #131072 ; 0x20000 + 800384e: f5b3 3f00 cmp.w r3, #131072 ; 0x20000 + 8003852: d101 bne.n 8003858 + 8003854: 2301 movs r3, #1 + 8003856: e000 b.n 800385a + 8003858: 2300 movs r3, #0 +} + 800385a: 4618 mov r0, r3 + 800385c: 46bd mov sp, r7 + 800385e: bc80 pop {r7} + 8003860: 4770 bx lr + +08003862 : + * @brief Check if PLCK2 prescaler flag value has been applied or not + * @rmtoll CFGR PPRE2F LL_RCC_IsActiveFlag_PPRE2 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PPRE2(void) +{ + 8003862: b480 push {r7} + 8003864: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2F) == (RCC_CFGR_PPRE2F)) ? 1UL : 0UL); + 8003866: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800386a: 689b ldr r3, [r3, #8] + 800386c: f403 2380 and.w r3, r3, #262144 ; 0x40000 + 8003870: f5b3 2f80 cmp.w r3, #262144 ; 0x40000 + 8003874: d101 bne.n 800387a + 8003876: 2301 movs r3, #1 + 8003878: e000 b.n 800387c + 800387a: 2300 movs r3, #0 +} + 800387c: 4618 mov r0, r3 + 800387e: 46bd mov sp, r7 + 8003880: bc80 pop {r7} + 8003882: 4770 bx lr + +08003884 : + * contains the configuration information for the RCC Oscillators. + * @note The PLL is not disabled when used as system clock. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) +{ + 8003884: b580 push {r7, lr} + 8003886: b088 sub sp, #32 + 8003888: af00 add r7, sp, #0 + 800388a: 6078 str r0, [r7, #4] + uint32_t sysclk_source; + uint32_t pll_config; + HAL_StatusTypeDef status; + + /* Check Null pointer */ + if (RCC_OscInitStruct == NULL) + 800388c: 687b ldr r3, [r7, #4] + 800388e: 2b00 cmp r3, #0 + 8003890: d101 bne.n 8003896 + { + return HAL_ERROR; + 8003892: 2301 movs r3, #1 + 8003894: e36f b.n 8003f76 + } + + /* Check the parameters */ + assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType)); + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 8003896: f7ff fece bl 8003636 + 800389a: 61f8 str r0, [r7, #28] + pll_config = __HAL_RCC_GET_PLL_OSCSOURCE(); + 800389c: f7ff ffa2 bl 80037e4 + 80038a0: 61b8 str r0, [r7, #24] + + /*----------------------------- MSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI) + 80038a2: 687b ldr r3, [r7, #4] + 80038a4: 681b ldr r3, [r3, #0] + 80038a6: f003 0320 and.w r3, r3, #32 + 80038aa: 2b00 cmp r3, #0 + 80038ac: f000 80c4 beq.w 8003a38 + assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState)); + assert_param(IS_RCC_MSI_CALIBRATION_VALUE(RCC_OscInitStruct->MSICalibrationValue)); + assert_param(IS_RCC_MSI_CLOCK_RANGE(RCC_OscInitStruct->MSIClockRange)); + + /* When the MSI is used as system clock it will not be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + 80038b0: 69fb ldr r3, [r7, #28] + 80038b2: 2b00 cmp r3, #0 + 80038b4: d005 beq.n 80038c2 + 80038b6: 69fb ldr r3, [r7, #28] + 80038b8: 2b0c cmp r3, #12 + 80038ba: d176 bne.n 80039aa + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_MSI))) + 80038bc: 69bb ldr r3, [r7, #24] + 80038be: 2b01 cmp r3, #1 + 80038c0: d173 bne.n 80039aa + { + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 80038c2: 687b ldr r3, [r7, #4] + 80038c4: 6a1b ldr r3, [r3, #32] + 80038c6: 2b00 cmp r3, #0 + 80038c8: d101 bne.n 80038ce + { + return HAL_ERROR; + 80038ca: 2301 movs r3, #1 + 80038cc: e353 b.n 8003f76 + else + { + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the AHB3 clock + and the supply voltage of the device. */ + if (RCC_OscInitStruct->MSIClockRange > __HAL_RCC_GET_MSI_RANGE()) + 80038ce: 687b ldr r3, [r7, #4] + 80038d0: 6a9a ldr r2, [r3, #40] ; 0x28 + 80038d2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80038d6: 681b ldr r3, [r3, #0] + 80038d8: f003 0308 and.w r3, r3, #8 + 80038dc: 2b00 cmp r3, #0 + 80038de: d005 beq.n 80038ec + 80038e0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80038e4: 681b ldr r3, [r3, #0] + 80038e6: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 80038ea: e006 b.n 80038fa + 80038ec: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80038f0: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80038f4: 091b lsrs r3, r3, #4 + 80038f6: f003 03f0 and.w r3, r3, #240 ; 0xf0 + 80038fa: 4293 cmp r3, r2 + 80038fc: d222 bcs.n 8003944 + { + /* First increase number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 80038fe: 687b ldr r3, [r7, #4] + 8003900: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003902: 4618 mov r0, r3 + 8003904: f000 fd3c bl 8004380 + 8003908: 4603 mov r3, r0 + 800390a: 2b00 cmp r3, #0 + 800390c: d001 beq.n 8003912 + { + return HAL_ERROR; + 800390e: 2301 movs r3, #1 + 8003910: e331 b.n 8003f76 + } + + /* Selects the Multiple Speed oscillator (MSI) clock range .*/ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8003912: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003916: 681b ldr r3, [r3, #0] + 8003918: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800391c: f043 0308 orr.w r3, r3, #8 + 8003920: 6013 str r3, [r2, #0] + 8003922: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003926: 681b ldr r3, [r3, #0] + 8003928: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800392c: 687b ldr r3, [r7, #4] + 800392e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003930: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003934: 4313 orrs r3, r2 + 8003936: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8003938: 687b ldr r3, [r7, #4] + 800393a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800393c: 4618 mov r0, r3 + 800393e: f7ff fe53 bl 80035e8 + 8003942: e021 b.n 8003988 + } + else + { + /* Else, keep current flash latency while decreasing applies */ + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 8003944: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003948: 681b ldr r3, [r3, #0] + 800394a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800394e: f043 0308 orr.w r3, r3, #8 + 8003952: 6013 str r3, [r2, #0] + 8003954: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003958: 681b ldr r3, [r3, #0] + 800395a: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 800395e: 687b ldr r3, [r7, #4] + 8003960: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003962: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003966: 4313 orrs r3, r2 + 8003968: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value.*/ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 800396a: 687b ldr r3, [r7, #4] + 800396c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800396e: 4618 mov r0, r3 + 8003970: f7ff fe3a bl 80035e8 + + /* Decrease number of wait states update if necessary */ + if (RCC_SetFlashLatencyFromMSIRange(RCC_OscInitStruct->MSIClockRange) != HAL_OK) + 8003974: 687b ldr r3, [r7, #4] + 8003976: 6a9b ldr r3, [r3, #40] ; 0x28 + 8003978: 4618 mov r0, r3 + 800397a: f000 fd01 bl 8004380 + 800397e: 4603 mov r3, r0 + 8003980: 2b00 cmp r3, #0 + 8003982: d001 beq.n 8003988 + { + return HAL_ERROR; + 8003984: 2301 movs r3, #1 + 8003986: e2f6 b.n 8003f76 + } + } + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 8003988: f000 fcc2 bl 8004310 + 800398c: 4603 mov r3, r0 + 800398e: 4aa7 ldr r2, [pc, #668] ; (8003c2c ) + 8003990: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + status = HAL_InitTick(uwTickPrio); + 8003992: 4ba7 ldr r3, [pc, #668] ; (8003c30 ) + 8003994: 681b ldr r3, [r3, #0] + 8003996: 4618 mov r0, r3 + 8003998: f7fe f9aa bl 8001cf0 + 800399c: 4603 mov r3, r0 + 800399e: 74fb strb r3, [r7, #19] + if (status != HAL_OK) + 80039a0: 7cfb ldrb r3, [r7, #19] + 80039a2: 2b00 cmp r3, #0 + 80039a4: d047 beq.n 8003a36 + { + return status; + 80039a6: 7cfb ldrb r3, [r7, #19] + 80039a8: e2e5 b.n 8003f76 + } + } + else + { + /* Check the MSI State */ + if (RCC_OscInitStruct->MSIState != RCC_MSI_OFF) + 80039aa: 687b ldr r3, [r7, #4] + 80039ac: 6a1b ldr r3, [r3, #32] + 80039ae: 2b00 cmp r3, #0 + 80039b0: d02c beq.n 8003a0c + { + /* Enable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_ENABLE(); + 80039b2: f7ff fdc6 bl 8003542 + + /* Get timeout */ + tickstart = HAL_GetTick(); + 80039b6: f7fd f9b1 bl 8000d1c + 80039ba: 6178 str r0, [r7, #20] + + /* Wait till MSI is ready */ + while (LL_RCC_MSI_IsReady() == 0U) + 80039bc: e008 b.n 80039d0 + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 80039be: f7fd f9ad bl 8000d1c + 80039c2: 4602 mov r2, r0 + 80039c4: 697b ldr r3, [r7, #20] + 80039c6: 1ad3 subs r3, r2, r3 + 80039c8: 2b02 cmp r3, #2 + 80039ca: d901 bls.n 80039d0 + { + return HAL_TIMEOUT; + 80039cc: 2303 movs r3, #3 + 80039ce: e2d2 b.n 8003f76 + while (LL_RCC_MSI_IsReady() == 0U) + 80039d0: f7ff fdd3 bl 800357a + 80039d4: 4603 mov r3, r0 + 80039d6: 2b00 cmp r3, #0 + 80039d8: d0f1 beq.n 80039be + } + } + + /* Selects the Multiple Speed oscillator (MSI) clock range. */ + __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange); + 80039da: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80039de: 681b ldr r3, [r3, #0] + 80039e0: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80039e4: f043 0308 orr.w r3, r3, #8 + 80039e8: 6013 str r3, [r2, #0] + 80039ea: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80039ee: 681b ldr r3, [r3, #0] + 80039f0: f023 02f0 bic.w r2, r3, #240 ; 0xf0 + 80039f4: 687b ldr r3, [r7, #4] + 80039f6: 6a9b ldr r3, [r3, #40] ; 0x28 + 80039f8: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80039fc: 4313 orrs r3, r2 + 80039fe: 600b str r3, [r1, #0] + /* Adjusts the Multiple Speed oscillator (MSI) calibration value. */ + __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue); + 8003a00: 687b ldr r3, [r7, #4] + 8003a02: 6a5b ldr r3, [r3, #36] ; 0x24 + 8003a04: 4618 mov r0, r3 + 8003a06: f7ff fdef bl 80035e8 + 8003a0a: e015 b.n 8003a38 + + } + else + { + /* Disable the Internal High Speed oscillator (MSI). */ + __HAL_RCC_MSI_DISABLE(); + 8003a0c: f7ff fda7 bl 800355e + + /* Get timeout */ + tickstart = HAL_GetTick(); + 8003a10: f7fd f984 bl 8000d1c + 8003a14: 6178 str r0, [r7, #20] + + /* Wait till MSI is disabled */ + while (LL_RCC_MSI_IsReady() != 0U) + 8003a16: e008 b.n 8003a2a + { + if ((HAL_GetTick() - tickstart) > MSI_TIMEOUT_VALUE) + 8003a18: f7fd f980 bl 8000d1c + 8003a1c: 4602 mov r2, r0 + 8003a1e: 697b ldr r3, [r7, #20] + 8003a20: 1ad3 subs r3, r2, r3 + 8003a22: 2b02 cmp r3, #2 + 8003a24: d901 bls.n 8003a2a + { + return HAL_TIMEOUT; + 8003a26: 2303 movs r3, #3 + 8003a28: e2a5 b.n 8003f76 + while (LL_RCC_MSI_IsReady() != 0U) + 8003a2a: f7ff fda6 bl 800357a + 8003a2e: 4603 mov r3, r0 + 8003a30: 2b00 cmp r3, #0 + 8003a32: d1f1 bne.n 8003a18 + 8003a34: e000 b.n 8003a38 + if (RCC_OscInitStruct->MSIState == RCC_MSI_OFF) + 8003a36: bf00 nop + } + } + } + + /*------------------------------- HSE Configuration ------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) + 8003a38: 687b ldr r3, [r7, #4] + 8003a3a: 681b ldr r3, [r3, #0] + 8003a3c: f003 0301 and.w r3, r3, #1 + 8003a40: 2b00 cmp r3, #0 + 8003a42: d058 beq.n 8003af6 + { + /* Check the parameters */ + assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState)); + + /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) || + 8003a44: 69fb ldr r3, [r7, #28] + 8003a46: 2b08 cmp r3, #8 + 8003a48: d005 beq.n 8003a56 + 8003a4a: 69fb ldr r3, [r7, #28] + 8003a4c: 2b0c cmp r3, #12 + 8003a4e: d108 bne.n 8003a62 + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSE))) + 8003a50: 69bb ldr r3, [r7, #24] + 8003a52: 2b03 cmp r3, #3 + 8003a54: d105 bne.n 8003a62 + { + if (RCC_OscInitStruct->HSEState == RCC_HSE_OFF) + 8003a56: 687b ldr r3, [r7, #4] + 8003a58: 685b ldr r3, [r3, #4] + 8003a5a: 2b00 cmp r3, #0 + 8003a5c: d14b bne.n 8003af6 + { + return HAL_ERROR; + 8003a5e: 2301 movs r3, #1 + 8003a60: e289 b.n 8003f76 + /* Set the new HSE configuration ---------------------------------------*/ + /* Check HSE division factor */ + assert_param(IS_RCC_HSEDIV(RCC_OscInitStruct->HSEDiv)); + + /* Set HSE division factor */ + MODIFY_REG(RCC->CR, RCC_CR_HSEPRE, RCC_OscInitStruct->HSEDiv); + 8003a62: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003a66: 681b ldr r3, [r3, #0] + 8003a68: f423 1280 bic.w r2, r3, #1048576 ; 0x100000 + 8003a6c: 687b ldr r3, [r7, #4] + 8003a6e: 689b ldr r3, [r3, #8] + 8003a70: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003a74: 4313 orrs r3, r2 + 8003a76: 600b str r3, [r1, #0] + + __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState); + 8003a78: 687b ldr r3, [r7, #4] + 8003a7a: 685b ldr r3, [r3, #4] + 8003a7c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 8003a80: d102 bne.n 8003a88 + 8003a82: f7ff fcae bl 80033e2 + 8003a86: e00d b.n 8003aa4 + 8003a88: 687b ldr r3, [r7, #4] + 8003a8a: 685b ldr r3, [r3, #4] + 8003a8c: f5b3 1f04 cmp.w r3, #2162688 ; 0x210000 + 8003a90: d104 bne.n 8003a9c + 8003a92: f7ff fc79 bl 8003388 + 8003a96: f7ff fca4 bl 80033e2 + 8003a9a: e003 b.n 8003aa4 + 8003a9c: f7ff fcaf bl 80033fe + 8003aa0: f7ff fc80 bl 80033a4 + + /* Check the HSE State */ + if (RCC_OscInitStruct->HSEState != RCC_HSE_OFF) + 8003aa4: 687b ldr r3, [r7, #4] + 8003aa6: 685b ldr r3, [r3, #4] + 8003aa8: 2b00 cmp r3, #0 + 8003aaa: d012 beq.n 8003ad2 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003aac: f7fd f936 bl 8000d1c + 8003ab0: 6178 str r0, [r7, #20] + + /* Wait till HSE is ready */ + while (LL_RCC_HSE_IsReady() == 0U) + 8003ab2: e008 b.n 8003ac6 + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8003ab4: f7fd f932 bl 8000d1c + 8003ab8: 4602 mov r2, r0 + 8003aba: 697b ldr r3, [r7, #20] + 8003abc: 1ad3 subs r3, r2, r3 + 8003abe: 2b64 cmp r3, #100 ; 0x64 + 8003ac0: d901 bls.n 8003ac6 + { + return HAL_TIMEOUT; + 8003ac2: 2303 movs r3, #3 + 8003ac4: e257 b.n 8003f76 + while (LL_RCC_HSE_IsReady() == 0U) + 8003ac6: f7ff fca8 bl 800341a + 8003aca: 4603 mov r3, r0 + 8003acc: 2b00 cmp r3, #0 + 8003ace: d0f1 beq.n 8003ab4 + 8003ad0: e011 b.n 8003af6 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003ad2: f7fd f923 bl 8000d1c + 8003ad6: 6178 str r0, [r7, #20] + + /* Wait till HSE is disabled */ + while (LL_RCC_HSE_IsReady() != 0U) + 8003ad8: e008 b.n 8003aec + { + if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE) + 8003ada: f7fd f91f bl 8000d1c + 8003ade: 4602 mov r2, r0 + 8003ae0: 697b ldr r3, [r7, #20] + 8003ae2: 1ad3 subs r3, r2, r3 + 8003ae4: 2b64 cmp r3, #100 ; 0x64 + 8003ae6: d901 bls.n 8003aec + { + return HAL_TIMEOUT; + 8003ae8: 2303 movs r3, #3 + 8003aea: e244 b.n 8003f76 + while (LL_RCC_HSE_IsReady() != 0U) + 8003aec: f7ff fc95 bl 800341a + 8003af0: 4603 mov r3, r0 + 8003af2: 2b00 cmp r3, #0 + 8003af4: d1f1 bne.n 8003ada + } + } + } + + /*----------------------------- HSI Configuration --------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) + 8003af6: 687b ldr r3, [r7, #4] + 8003af8: 681b ldr r3, [r3, #0] + 8003afa: f003 0302 and.w r3, r3, #2 + 8003afe: 2b00 cmp r3, #0 + 8003b00: d046 beq.n 8003b90 + /* Check the parameters */ + assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState)); + assert_param(IS_RCC_HSI_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue)); + + /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) || + 8003b02: 69fb ldr r3, [r7, #28] + 8003b04: 2b04 cmp r3, #4 + 8003b06: d005 beq.n 8003b14 + 8003b08: 69fb ldr r3, [r7, #28] + 8003b0a: 2b0c cmp r3, #12 + 8003b0c: d10e bne.n 8003b2c + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pll_config == RCC_PLLSOURCE_HSI))) + 8003b0e: 69bb ldr r3, [r7, #24] + 8003b10: 2b02 cmp r3, #2 + 8003b12: d10b bne.n 8003b2c + { + /* When HSI is used as system clock it will not be disabled */ + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8003b14: 687b ldr r3, [r7, #4] + 8003b16: 691b ldr r3, [r3, #16] + 8003b18: 2b00 cmp r3, #0 + 8003b1a: d101 bne.n 8003b20 + { + return HAL_ERROR; + 8003b1c: 2301 movs r3, #1 + 8003b1e: e22a b.n 8003f76 + } + /* Otherwise, just the calibration is allowed */ + else + { + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8003b20: 687b ldr r3, [r7, #4] + 8003b22: 695b ldr r3, [r3, #20] + 8003b24: 4618 mov r0, r3 + 8003b26: f7ff fcb6 bl 8003496 + if (RCC_OscInitStruct->HSIState == RCC_HSI_OFF) + 8003b2a: e031 b.n 8003b90 + } + } + else + { + /* Check the HSI State */ + if (RCC_OscInitStruct->HSIState != RCC_HSI_OFF) + 8003b2c: 687b ldr r3, [r7, #4] + 8003b2e: 691b ldr r3, [r3, #16] + 8003b30: 2b00 cmp r3, #0 + 8003b32: d019 beq.n 8003b68 + { + /* Enable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_ENABLE(); + 8003b34: f7ff fc82 bl 800343c + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003b38: f7fd f8f0 bl 8000d1c + 8003b3c: 6178 str r0, [r7, #20] + + /* Wait till HSI is ready */ + while (LL_RCC_HSI_IsReady() == 0U) + 8003b3e: e008 b.n 8003b52 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8003b40: f7fd f8ec bl 8000d1c + 8003b44: 4602 mov r2, r0 + 8003b46: 697b ldr r3, [r7, #20] + 8003b48: 1ad3 subs r3, r2, r3 + 8003b4a: 2b02 cmp r3, #2 + 8003b4c: d901 bls.n 8003b52 + { + return HAL_TIMEOUT; + 8003b4e: 2303 movs r3, #3 + 8003b50: e211 b.n 8003f76 + while (LL_RCC_HSI_IsReady() == 0U) + 8003b52: f7ff fc8f bl 8003474 + 8003b56: 4603 mov r3, r0 + 8003b58: 2b00 cmp r3, #0 + 8003b5a: d0f1 beq.n 8003b40 + } + } + + /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */ + __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue); + 8003b5c: 687b ldr r3, [r7, #4] + 8003b5e: 695b ldr r3, [r3, #20] + 8003b60: 4618 mov r0, r3 + 8003b62: f7ff fc98 bl 8003496 + 8003b66: e013 b.n 8003b90 + } + else + { + /* Disable the Internal High Speed oscillator (HSI). */ + __HAL_RCC_HSI_DISABLE(); + 8003b68: f7ff fc76 bl 8003458 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003b6c: f7fd f8d6 bl 8000d1c + 8003b70: 6178 str r0, [r7, #20] + + /* Wait till HSI is disabled */ + while (LL_RCC_HSI_IsReady() != 0U) + 8003b72: e008 b.n 8003b86 + { + if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE) + 8003b74: f7fd f8d2 bl 8000d1c + 8003b78: 4602 mov r2, r0 + 8003b7a: 697b ldr r3, [r7, #20] + 8003b7c: 1ad3 subs r3, r2, r3 + 8003b7e: 2b02 cmp r3, #2 + 8003b80: d901 bls.n 8003b86 + { + return HAL_TIMEOUT; + 8003b82: 2303 movs r3, #3 + 8003b84: e1f7 b.n 8003f76 + while (LL_RCC_HSI_IsReady() != 0U) + 8003b86: f7ff fc75 bl 8003474 + 8003b8a: 4603 mov r3, r0 + 8003b8c: 2b00 cmp r3, #0 + 8003b8e: d1f1 bne.n 8003b74 + } + } + } + + /*------------------------------ LSI Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) + 8003b90: 687b ldr r3, [r7, #4] + 8003b92: 681b ldr r3, [r3, #0] + 8003b94: f003 0308 and.w r3, r3, #8 + 8003b98: 2b00 cmp r3, #0 + 8003b9a: d06e beq.n 8003c7a + { + /* Check the parameters */ + assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState)); + + /* Check the LSI State */ + if (RCC_OscInitStruct->LSIState != RCC_LSI_OFF) + 8003b9c: 687b ldr r3, [r7, #4] + 8003b9e: 699b ldr r3, [r3, #24] + 8003ba0: 2b00 cmp r3, #0 + 8003ba2: d056 beq.n 8003c52 + { + uint32_t csr_temp = RCC->CSR; + 8003ba4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003ba8: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8003bac: 60fb str r3, [r7, #12] + + /* Check LSI division factor */ + assert_param(IS_RCC_LSIDIV(RCC_OscInitStruct->LSIDiv)); + + if (RCC_OscInitStruct->LSIDiv != (csr_temp & RCC_CSR_LSIPRE)) + 8003bae: 687b ldr r3, [r7, #4] + 8003bb0: 69da ldr r2, [r3, #28] + 8003bb2: 68fb ldr r3, [r7, #12] + 8003bb4: f003 0310 and.w r3, r3, #16 + 8003bb8: 429a cmp r2, r3 + 8003bba: d031 beq.n 8003c20 + { + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + 8003bbc: 68fb ldr r3, [r7, #12] + 8003bbe: f003 0302 and.w r3, r3, #2 + 8003bc2: 2b00 cmp r3, #0 + 8003bc4: d006 beq.n 8003bd4 + ((csr_temp & RCC_CSR_LSION) != RCC_CSR_LSION)) + 8003bc6: 68fb ldr r3, [r7, #12] + 8003bc8: f003 0301 and.w r3, r3, #1 + if (((csr_temp & RCC_CSR_LSIRDY) == RCC_CSR_LSIRDY) && \ + 8003bcc: 2b00 cmp r3, #0 + 8003bce: d101 bne.n 8003bd4 + { + /* If LSIRDY is set while LSION is not enabled, + LSIPRE can't be updated */ + return HAL_ERROR; + 8003bd0: 2301 movs r3, #1 + 8003bd2: e1d0 b.n 8003f76 + } + + /* Turn off LSI before changing RCC_CSR_LSIPRE */ + if ((csr_temp & RCC_CSR_LSION) == RCC_CSR_LSION) + 8003bd4: 68fb ldr r3, [r7, #12] + 8003bd6: f003 0301 and.w r3, r3, #1 + 8003bda: 2b00 cmp r3, #0 + 8003bdc: d013 beq.n 8003c06 + { + __HAL_RCC_LSI_DISABLE(); + 8003bde: f7ff fc8f bl 8003500 + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8003be2: f7fd f89b bl 8000d1c + 8003be6: 6178 str r0, [r7, #20] + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + 8003be8: e008 b.n 8003bfc + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8003bea: f7fd f897 bl 8000d1c + 8003bee: 4602 mov r2, r0 + 8003bf0: 697b ldr r3, [r7, #20] + 8003bf2: 1ad3 subs r3, r2, r3 + 8003bf4: 2b11 cmp r3, #17 + 8003bf6: d901 bls.n 8003bfc + { + return HAL_TIMEOUT; + 8003bf8: 2303 movs r3, #3 + 8003bfa: e1bc b.n 8003f76 + while (LL_RCC_LSI_IsReady() != 0U) + 8003bfc: f7ff fc90 bl 8003520 + 8003c00: 4603 mov r3, r0 + 8003c02: 2b00 cmp r3, #0 + 8003c04: d1f1 bne.n 8003bea + } + } + } + + /* Set LSI division factor */ + MODIFY_REG(RCC->CSR, RCC_CSR_LSIPRE, RCC_OscInitStruct->LSIDiv); + 8003c06: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003c0a: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 8003c0e: f023 0210 bic.w r2, r3, #16 + 8003c12: 687b ldr r3, [r7, #4] + 8003c14: 69db ldr r3, [r3, #28] + 8003c16: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003c1a: 4313 orrs r3, r2 + 8003c1c: f8c1 3094 str.w r3, [r1, #148] ; 0x94 + } + + /* Enable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_ENABLE(); + 8003c20: f7ff fc5e bl 80034e0 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003c24: f7fd f87a bl 8000d1c + 8003c28: 6178 str r0, [r7, #20] + + /* Wait till LSI is ready */ + while (LL_RCC_LSI_IsReady() == 0U) + 8003c2a: e00c b.n 8003c46 + 8003c2c: 20000000 .word 0x20000000 + 8003c30: 20000004 .word 0x20000004 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8003c34: f7fd f872 bl 8000d1c + 8003c38: 4602 mov r2, r0 + 8003c3a: 697b ldr r3, [r7, #20] + 8003c3c: 1ad3 subs r3, r2, r3 + 8003c3e: 2b11 cmp r3, #17 + 8003c40: d901 bls.n 8003c46 + { + return HAL_TIMEOUT; + 8003c42: 2303 movs r3, #3 + 8003c44: e197 b.n 8003f76 + while (LL_RCC_LSI_IsReady() == 0U) + 8003c46: f7ff fc6b bl 8003520 + 8003c4a: 4603 mov r3, r0 + 8003c4c: 2b00 cmp r3, #0 + 8003c4e: d0f1 beq.n 8003c34 + 8003c50: e013 b.n 8003c7a + } + } + else + { + /* Disable the Internal Low Speed oscillator (LSI). */ + __HAL_RCC_LSI_DISABLE(); + 8003c52: f7ff fc55 bl 8003500 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003c56: f7fd f861 bl 8000d1c + 8003c5a: 6178 str r0, [r7, #20] + + /* Wait till LSI is disabled */ + while (LL_RCC_LSI_IsReady() != 0U) + 8003c5c: e008 b.n 8003c70 + { + if ((HAL_GetTick() - tickstart) > LSI_TIMEOUT_VALUE) + 8003c5e: f7fd f85d bl 8000d1c + 8003c62: 4602 mov r2, r0 + 8003c64: 697b ldr r3, [r7, #20] + 8003c66: 1ad3 subs r3, r2, r3 + 8003c68: 2b11 cmp r3, #17 + 8003c6a: d901 bls.n 8003c70 + { + return HAL_TIMEOUT; + 8003c6c: 2303 movs r3, #3 + 8003c6e: e182 b.n 8003f76 + while (LL_RCC_LSI_IsReady() != 0U) + 8003c70: f7ff fc56 bl 8003520 + 8003c74: 4603 mov r3, r0 + 8003c76: 2b00 cmp r3, #0 + 8003c78: d1f1 bne.n 8003c5e + } + } + } + + /*------------------------------ LSE Configuration -------------------------*/ + if (((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) + 8003c7a: 687b ldr r3, [r7, #4] + 8003c7c: 681b ldr r3, [r3, #0] + 8003c7e: f003 0304 and.w r3, r3, #4 + 8003c82: 2b00 cmp r3, #0 + 8003c84: f000 80d8 beq.w 8003e38 + assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState)); + + /* Update LSE configuration in Backup Domain control register */ + /* Requires to enable write access to Backup Domain of necessary */ + + if (LL_PWR_IsEnabledBkUpAccess() == 0U) + 8003c88: f7ff fb6c bl 8003364 + 8003c8c: 4603 mov r3, r0 + 8003c8e: 2b00 cmp r3, #0 + 8003c90: d113 bne.n 8003cba + { + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 8003c92: f7ff fa41 bl 8003118 + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 8003c96: f7fd f841 bl 8000d1c + 8003c9a: 6178 str r0, [r7, #20] + + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + 8003c9c: e008 b.n 8003cb0 + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 8003c9e: f7fd f83d bl 8000d1c + 8003ca2: 4602 mov r2, r0 + 8003ca4: 697b ldr r3, [r7, #20] + 8003ca6: 1ad3 subs r3, r2, r3 + 8003ca8: 2b02 cmp r3, #2 + 8003caa: d901 bls.n 8003cb0 + { + return HAL_TIMEOUT; + 8003cac: 2303 movs r3, #3 + 8003cae: e162 b.n 8003f76 + while (LL_PWR_IsEnabledBkUpAccess() == 0U) + 8003cb0: f7ff fb58 bl 8003364 + 8003cb4: 4603 mov r3, r0 + 8003cb6: 2b00 cmp r3, #0 + 8003cb8: d0f1 beq.n 8003c9e + } + } + } + + /* Set the new LSE configuration -----------------------------------------*/ + if (RCC_OscInitStruct->LSEState != RCC_LSE_OFF) + 8003cba: 687b ldr r3, [r7, #4] + 8003cbc: 68db ldr r3, [r3, #12] + 8003cbe: 2b00 cmp r3, #0 + 8003cc0: d07b beq.n 8003dba + { + /* Enable LSE bypasss (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS) + 8003cc2: 687b ldr r3, [r7, #4] + 8003cc4: 68db ldr r3, [r3, #12] + 8003cc6: 2b85 cmp r3, #133 ; 0x85 + 8003cc8: d003 beq.n 8003cd2 + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS_RTC_ONLY)) + 8003cca: 687b ldr r3, [r7, #4] + 8003ccc: 68db ldr r3, [r3, #12] + 8003cce: 2b05 cmp r3, #5 + 8003cd0: d109 bne.n 8003ce6 + { + /* LSE oscillator bypass enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); + 8003cd2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003cd6: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003cda: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003cde: f043 0304 orr.w r3, r3, #4 + 8003ce2: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003ce6: f7fd f819 bl 8000d1c + 8003cea: 6178 str r0, [r7, #20] + + /* LSE oscillator enable */ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 8003cec: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003cf0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003cf4: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003cf8: f043 0301 orr.w r3, r3, #1 + 8003cfc: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() == 0U) + 8003d00: e00a b.n 8003d18 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003d02: f7fd f80b bl 8000d1c + 8003d06: 4602 mov r2, r0 + 8003d08: 697b ldr r3, [r7, #20] + 8003d0a: 1ad3 subs r3, r2, r3 + 8003d0c: f241 3288 movw r2, #5000 ; 0x1388 + 8003d10: 4293 cmp r3, r2 + 8003d12: d901 bls.n 8003d18 + { + return HAL_TIMEOUT; + 8003d14: 2303 movs r3, #3 + 8003d16: e12e b.n 8003f76 + while (LL_RCC_LSE_IsReady() == 0U) + 8003d18: f7ff fbd1 bl 80034be + 8003d1c: 4603 mov r3, r0 + 8003d1e: 2b00 cmp r3, #0 + 8003d20: d0ef beq.n 8003d02 + } + } + + /* Enable LSE system clock (if requested) */ + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + 8003d22: 687b ldr r3, [r7, #4] + 8003d24: 68db ldr r3, [r3, #12] + 8003d26: 2b81 cmp r3, #129 ; 0x81 + 8003d28: d003 beq.n 8003d32 + || (RCC_OscInitStruct->LSEState == RCC_LSE_BYPASS)) + 8003d2a: 687b ldr r3, [r7, #4] + 8003d2c: 68db ldr r3, [r3, #12] + 8003d2e: 2b85 cmp r3, #133 ; 0x85 + 8003d30: d121 bne.n 8003d76 + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003d32: f7fc fff3 bl 8000d1c + 8003d36: 6178 str r0, [r7, #20] + + SET_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 8003d38: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003d3c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003d40: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003d44: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8003d48: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + + /* Wait till LSESYS is ready */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + 8003d4c: e00a b.n 8003d64 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003d4e: f7fc ffe5 bl 8000d1c + 8003d52: 4602 mov r2, r0 + 8003d54: 697b ldr r3, [r7, #20] + 8003d56: 1ad3 subs r3, r2, r3 + 8003d58: f241 3288 movw r2, #5000 ; 0x1388 + 8003d5c: 4293 cmp r3, r2 + 8003d5e: d901 bls.n 8003d64 + { + return HAL_TIMEOUT; + 8003d60: 2303 movs r3, #3 + 8003d62: e108 b.n 8003f76 + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) == 0U) + 8003d64: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003d68: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003d6c: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8003d70: 2b00 cmp r3, #0 + 8003d72: d0ec beq.n 8003d4e + if ((RCC_OscInitStruct->LSEState == RCC_LSE_ON) + 8003d74: e060 b.n 8003e38 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003d76: f7fc ffd1 bl 8000d1c + 8003d7a: 6178 str r0, [r7, #20] + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 8003d7c: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003d80: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003d84: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003d88: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8003d8c: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003d90: e00a b.n 8003da8 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003d92: f7fc ffc3 bl 8000d1c + 8003d96: 4602 mov r2, r0 + 8003d98: 697b ldr r3, [r7, #20] + 8003d9a: 1ad3 subs r3, r2, r3 + 8003d9c: f241 3288 movw r2, #5000 ; 0x1388 + 8003da0: 4293 cmp r3, r2 + 8003da2: d901 bls.n 8003da8 + { + return HAL_TIMEOUT; + 8003da4: 2303 movs r3, #3 + 8003da6: e0e6 b.n 8003f76 + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003da8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003dac: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003db0: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8003db4: 2b00 cmp r3, #0 + 8003db6: d1ec bne.n 8003d92 + 8003db8: e03e b.n 8003e38 + } + } + else + { + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003dba: f7fc ffaf bl 8000d1c + 8003dbe: 6178 str r0, [r7, #20] + + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSESYSEN); + 8003dc0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003dc4: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003dc8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003dcc: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8003dd0: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + + /* Wait till LSESYSRDY is cleared */ + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003dd4: e00a b.n 8003dec + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003dd6: f7fc ffa1 bl 8000d1c + 8003dda: 4602 mov r2, r0 + 8003ddc: 697b ldr r3, [r7, #20] + 8003dde: 1ad3 subs r3, r2, r3 + 8003de0: f241 3288 movw r2, #5000 ; 0x1388 + 8003de4: 4293 cmp r3, r2 + 8003de6: d901 bls.n 8003dec + { + return HAL_TIMEOUT; + 8003de8: 2303 movs r3, #3 + 8003dea: e0c4 b.n 8003f76 + while (READ_BIT(RCC->BDCR, RCC_BDCR_LSESYSRDY) != 0U) + 8003dec: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003df0: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003df4: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8003df8: 2b00 cmp r3, #0 + 8003dfa: d1ec bne.n 8003dd6 + } + } + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003dfc: f7fc ff8e bl 8000d1c + 8003e00: 6178 str r0, [r7, #20] + + /* LSE oscillator disable */ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); + 8003e02: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003e06: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8003e0a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003e0e: f023 0301 bic.w r3, r3, #1 + 8003e12: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + + /* Wait till LSE is disabled */ + while (LL_RCC_LSE_IsReady() != 0U) + 8003e16: e00a b.n 8003e2e + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8003e18: f7fc ff80 bl 8000d1c + 8003e1c: 4602 mov r2, r0 + 8003e1e: 697b ldr r3, [r7, #20] + 8003e20: 1ad3 subs r3, r2, r3 + 8003e22: f241 3288 movw r2, #5000 ; 0x1388 + 8003e26: 4293 cmp r3, r2 + 8003e28: d901 bls.n 8003e2e + { + return HAL_TIMEOUT; + 8003e2a: 2303 movs r3, #3 + 8003e2c: e0a3 b.n 8003f76 + while (LL_RCC_LSE_IsReady() != 0U) + 8003e2e: f7ff fb46 bl 80034be + 8003e32: 4603 mov r3, r0 + 8003e34: 2b00 cmp r3, #0 + 8003e36: d1ef bne.n 8003e18 + + /*-------------------------------- PLL Configuration -----------------------*/ + /* Check the parameters */ + assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState)); + + if (RCC_OscInitStruct->PLL.PLLState != RCC_PLL_NONE) + 8003e38: 687b ldr r3, [r7, #4] + 8003e3a: 6adb ldr r3, [r3, #44] ; 0x2c + 8003e3c: 2b00 cmp r3, #0 + 8003e3e: f000 8099 beq.w 8003f74 + { + /* Check if the PLL is used as system clock or not */ + if (sysclk_source != RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8003e42: 69fb ldr r3, [r7, #28] + 8003e44: 2b0c cmp r3, #12 + 8003e46: d06c beq.n 8003f22 + { + if (RCC_OscInitStruct->PLL.PLLState == RCC_PLL_ON) + 8003e48: 687b ldr r3, [r7, #4] + 8003e4a: 6adb ldr r3, [r3, #44] ; 0x2c + 8003e4c: 2b02 cmp r3, #2 + 8003e4e: d14b bne.n 8003ee8 + assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP)); + assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ)); + assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR)); + + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8003e50: f7ff fc87 bl 8003762 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003e54: f7fc ff62 bl 8000d1c + 8003e58: 6178 str r0, [r7, #20] + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() != 0U) + 8003e5a: e008 b.n 8003e6e + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8003e5c: f7fc ff5e bl 8000d1c + 8003e60: 4602 mov r2, r0 + 8003e62: 697b ldr r3, [r7, #20] + 8003e64: 1ad3 subs r3, r2, r3 + 8003e66: 2b0a cmp r3, #10 + 8003e68: d901 bls.n 8003e6e + { + return HAL_TIMEOUT; + 8003e6a: 2303 movs r3, #3 + 8003e6c: e083 b.n 8003f76 + while (LL_RCC_PLL_IsReady() != 0U) + 8003e6e: f7ff fc86 bl 800377e + 8003e72: 4603 mov r3, r0 + 8003e74: 2b00 cmp r3, #0 + 8003e76: d1f1 bne.n 8003e5c + } + } + + /* Configure the main PLL clock source, multiplication and division factors. */ + __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource, + 8003e78: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003e7c: 68da ldr r2, [r3, #12] + 8003e7e: 4b40 ldr r3, [pc, #256] ; (8003f80 ) + 8003e80: 4013 ands r3, r2 + 8003e82: 687a ldr r2, [r7, #4] + 8003e84: 6b11 ldr r1, [r2, #48] ; 0x30 + 8003e86: 687a ldr r2, [r7, #4] + 8003e88: 6b52 ldr r2, [r2, #52] ; 0x34 + 8003e8a: 4311 orrs r1, r2 + 8003e8c: 687a ldr r2, [r7, #4] + 8003e8e: 6b92 ldr r2, [r2, #56] ; 0x38 + 8003e90: 0212 lsls r2, r2, #8 + 8003e92: 4311 orrs r1, r2 + 8003e94: 687a ldr r2, [r7, #4] + 8003e96: 6bd2 ldr r2, [r2, #60] ; 0x3c + 8003e98: 4311 orrs r1, r2 + 8003e9a: 687a ldr r2, [r7, #4] + 8003e9c: 6c12 ldr r2, [r2, #64] ; 0x40 + 8003e9e: 4311 orrs r1, r2 + 8003ea0: 687a ldr r2, [r7, #4] + 8003ea2: 6c52 ldr r2, [r2, #68] ; 0x44 + 8003ea4: 430a orrs r2, r1 + 8003ea6: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003eaa: 4313 orrs r3, r2 + 8003eac: 60cb str r3, [r1, #12] + RCC_OscInitStruct->PLL.PLLP, + RCC_OscInitStruct->PLL.PLLQ, + RCC_OscInitStruct->PLL.PLLR); + + /* Enable the main PLL. */ + __HAL_RCC_PLL_ENABLE(); + 8003eae: f7ff fc4a bl 8003746 + + /* Enable PLL System Clock output. */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_SYSCLK); + 8003eb2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003eb6: 68db ldr r3, [r3, #12] + 8003eb8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8003ebc: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8003ec0: 60d3 str r3, [r2, #12] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003ec2: f7fc ff2b bl 8000d1c + 8003ec6: 6178 str r0, [r7, #20] + + /* Wait till PLL is ready */ + while (LL_RCC_PLL_IsReady() == 0U) + 8003ec8: e008 b.n 8003edc + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8003eca: f7fc ff27 bl 8000d1c + 8003ece: 4602 mov r2, r0 + 8003ed0: 697b ldr r3, [r7, #20] + 8003ed2: 1ad3 subs r3, r2, r3 + 8003ed4: 2b0a cmp r3, #10 + 8003ed6: d901 bls.n 8003edc + { + return HAL_TIMEOUT; + 8003ed8: 2303 movs r3, #3 + 8003eda: e04c b.n 8003f76 + while (LL_RCC_PLL_IsReady() == 0U) + 8003edc: f7ff fc4f bl 800377e + 8003ee0: 4603 mov r3, r0 + 8003ee2: 2b00 cmp r3, #0 + 8003ee4: d0f1 beq.n 8003eca + 8003ee6: e045 b.n 8003f74 + } + } + else + { + /* Disable the main PLL. */ + __HAL_RCC_PLL_DISABLE(); + 8003ee8: f7ff fc3b bl 8003762 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003eec: f7fc ff16 bl 8000d1c + 8003ef0: 6178 str r0, [r7, #20] + + /* Wait till PLL is disabled */ + while (LL_RCC_PLL_IsReady() != 0U) + 8003ef2: e008 b.n 8003f06 + { + if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE) + 8003ef4: f7fc ff12 bl 8000d1c + 8003ef8: 4602 mov r2, r0 + 8003efa: 697b ldr r3, [r7, #20] + 8003efc: 1ad3 subs r3, r2, r3 + 8003efe: 2b0a cmp r3, #10 + 8003f00: d901 bls.n 8003f06 + { + return HAL_TIMEOUT; + 8003f02: 2303 movs r3, #3 + 8003f04: e037 b.n 8003f76 + while (LL_RCC_PLL_IsReady() != 0U) + 8003f06: f7ff fc3a bl 800377e + 8003f0a: 4603 mov r3, r0 + 8003f0c: 2b00 cmp r3, #0 + 8003f0e: d1f1 bne.n 8003ef4 + } + } + + /* Disable the PLL source and outputs to save power when PLL is off */ + CLEAR_BIT(RCC->PLLCFGR, (RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLPEN | RCC_PLLCFGR_PLLQEN | RCC_PLLCFGR_PLLREN)); + 8003f10: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003f14: 68da ldr r2, [r3, #12] + 8003f16: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8003f1a: 4b1a ldr r3, [pc, #104] ; (8003f84 ) + 8003f1c: 4013 ands r3, r2 + 8003f1e: 60cb str r3, [r1, #12] + 8003f20: e028 b.n 8003f74 + } + } + else + { + /* Check if there is a request to disable the PLL used as System clock source */ + if ((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_OFF) + 8003f22: 687b ldr r3, [r7, #4] + 8003f24: 6adb ldr r3, [r3, #44] ; 0x2c + 8003f26: 2b01 cmp r3, #1 + 8003f28: d101 bne.n 8003f2e + { + return HAL_ERROR; + 8003f2a: 2301 movs r3, #1 + 8003f2c: e023 b.n 8003f76 + } + else + { + /* Do not return HAL_ERROR if request repeats the current configuration */ + pll_config = RCC->PLLCFGR; + 8003f2e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8003f32: 68db ldr r3, [r3, #12] + 8003f34: 61bb str r3, [r7, #24] + if ((READ_BIT(pll_config, RCC_PLLCFGR_PLLSRC) != RCC_OscInitStruct->PLL.PLLSource) + 8003f36: 69bb ldr r3, [r7, #24] + 8003f38: f003 0203 and.w r2, r3, #3 + 8003f3c: 687b ldr r3, [r7, #4] + 8003f3e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8003f40: 429a cmp r2, r3 + 8003f42: d115 bne.n 8003f70 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLM) != RCC_OscInitStruct->PLL.PLLM) + 8003f44: 69bb ldr r3, [r7, #24] + 8003f46: f003 0270 and.w r2, r3, #112 ; 0x70 + 8003f4a: 687b ldr r3, [r7, #4] + 8003f4c: 6b5b ldr r3, [r3, #52] ; 0x34 + 8003f4e: 429a cmp r2, r3 + 8003f50: d10e bne.n 8003f70 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLN) != (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos)) + 8003f52: 69bb ldr r3, [r7, #24] + 8003f54: f403 42fe and.w r2, r3, #32512 ; 0x7f00 + 8003f58: 687b ldr r3, [r7, #4] + 8003f5a: 6b9b ldr r3, [r3, #56] ; 0x38 + 8003f5c: 021b lsls r3, r3, #8 + 8003f5e: 429a cmp r2, r3 + 8003f60: d106 bne.n 8003f70 + || (READ_BIT(pll_config, RCC_PLLCFGR_PLLR) != RCC_OscInitStruct->PLL.PLLR)) + 8003f62: 69bb ldr r3, [r7, #24] + 8003f64: f003 4260 and.w r2, r3, #3758096384 ; 0xe0000000 + 8003f68: 687b ldr r3, [r7, #4] + 8003f6a: 6c5b ldr r3, [r3, #68] ; 0x44 + 8003f6c: 429a cmp r2, r3 + 8003f6e: d001 beq.n 8003f74 + { + return HAL_ERROR; + 8003f70: 2301 movs r3, #1 + 8003f72: e000 b.n 8003f76 + } + } + } + } + return HAL_OK; + 8003f74: 2300 movs r3, #0 +} + 8003f76: 4618 mov r0, r3 + 8003f78: 3720 adds r7, #32 + 8003f7a: 46bd mov sp, r7 + 8003f7c: bd80 pop {r7, pc} + 8003f7e: bf00 nop + 8003f80: 11c1808c .word 0x11c1808c + 8003f84: eefefffc .word 0xeefefffc + +08003f88 : + * HPRE[3:0] bits to ensure that HCLK1 not exceed the maximum allowed frequency + * (for more details refer to section above "Initialization/de-initialization functions") + * @retval None + */ +HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +{ + 8003f88: b580 push {r7, lr} + 8003f8a: b084 sub sp, #16 + 8003f8c: af00 add r7, sp, #0 + 8003f8e: 6078 str r0, [r7, #4] + 8003f90: 6039 str r1, [r7, #0] + uint32_t tickstart; + + /* Check Null pointer */ + if (RCC_ClkInitStruct == NULL) + 8003f92: 687b ldr r3, [r7, #4] + 8003f94: 2b00 cmp r3, #0 + 8003f96: d101 bne.n 8003f9c + { + return HAL_ERROR; + 8003f98: 2301 movs r3, #1 + 8003f9a: e10f b.n 80041bc + /* To correctly read data from FLASH memory, the number of wait states (LATENCY) + must be correctly programmed according to the frequency of the FLASH clock + (HCLK3) and the supply voltage of the device. */ + + /* Increasing the number of wait states because of higher CPU frequency */ + if (FLatency > __HAL_FLASH_GET_LATENCY()) + 8003f9c: 4b89 ldr r3, [pc, #548] ; (80041c4 ) + 8003f9e: 681b ldr r3, [r3, #0] + 8003fa0: f003 0307 and.w r3, r3, #7 + 8003fa4: 683a ldr r2, [r7, #0] + 8003fa6: 429a cmp r2, r3 + 8003fa8: d91b bls.n 8003fe2 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 8003faa: 4b86 ldr r3, [pc, #536] ; (80041c4 ) + 8003fac: 681b ldr r3, [r3, #0] + 8003fae: f023 0207 bic.w r2, r3, #7 + 8003fb2: 4984 ldr r1, [pc, #528] ; (80041c4 ) + 8003fb4: 683b ldr r3, [r7, #0] + 8003fb6: 4313 orrs r3, r2 + 8003fb8: 600b str r3, [r1, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8003fba: f7fc feaf bl 8000d1c + 8003fbe: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003fc0: e008 b.n 8003fd4 + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8003fc2: f7fc feab bl 8000d1c + 8003fc6: 4602 mov r2, r0 + 8003fc8: 68fb ldr r3, [r7, #12] + 8003fca: 1ad3 subs r3, r2, r3 + 8003fcc: 2b02 cmp r3, #2 + 8003fce: d901 bls.n 8003fd4 + { + return HAL_TIMEOUT; + 8003fd0: 2303 movs r3, #3 + 8003fd2: e0f3 b.n 80041bc + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8003fd4: 4b7b ldr r3, [pc, #492] ; (80041c4 ) + 8003fd6: 681b ldr r3, [r3, #0] + 8003fd8: f003 0307 and.w r3, r3, #7 + 8003fdc: 683a ldr r2, [r7, #0] + 8003fde: 429a cmp r2, r3 + 8003fe0: d1ef bne.n 8003fc2 + } + } + } + + /*-------------------------- HCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) + 8003fe2: 687b ldr r3, [r7, #4] + 8003fe4: 681b ldr r3, [r3, #0] + 8003fe6: f003 0302 and.w r3, r3, #2 + 8003fea: 2b00 cmp r3, #0 + 8003fec: d016 beq.n 800401c + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLKDivider)); + LL_RCC_SetAHBPrescaler(RCC_ClkInitStruct->AHBCLKDivider); + 8003fee: 687b ldr r3, [r7, #4] + 8003ff0: 689b ldr r3, [r3, #8] + 8003ff2: 4618 mov r0, r3 + 8003ff4: f7ff fb2a bl 800364c + + /* HCLK1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8003ff8: f7fc fe90 bl 8000d1c + 8003ffc: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8003ffe: e008 b.n 8004012 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8004000: f7fc fe8c bl 8000d1c + 8004004: 4602 mov r2, r0 + 8004006: 68fb ldr r3, [r7, #12] + 8004008: 1ad3 subs r3, r2, r3 + 800400a: 2b02 cmp r3, #2 + 800400c: d901 bls.n 8004012 + { + return HAL_TIMEOUT; + 800400e: 2303 movs r3, #3 + 8004010: e0d4 b.n 80041bc + while (LL_RCC_IsActiveFlag_HPRE() == 0U) + 8004012: f7ff fbf2 bl 80037fa + 8004016: 4603 mov r3, r0 + 8004018: 2b00 cmp r3, #0 + 800401a: d0f1 beq.n 8004000 + } + } +#endif /* DUAL_CORE */ + + /*-------------------------- HCLK3 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK3) == RCC_CLOCKTYPE_HCLK3) + 800401c: 687b ldr r3, [r7, #4] + 800401e: 681b ldr r3, [r3, #0] + 8004020: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004024: 2b00 cmp r3, #0 + 8004026: d016 beq.n 8004056 + { + assert_param(IS_RCC_HCLKx(RCC_ClkInitStruct->AHBCLK3Divider)); + LL_RCC_SetAHB3Prescaler(RCC_ClkInitStruct->AHBCLK3Divider); + 8004028: 687b ldr r3, [r7, #4] + 800402a: 695b ldr r3, [r3, #20] + 800402c: 4618 mov r0, r3 + 800402e: f7ff fb20 bl 8003672 + + /* AHB shared prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 8004032: f7fc fe73 bl 8000d1c + 8004036: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 8004038: e008 b.n 800404c + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 800403a: f7fc fe6f bl 8000d1c + 800403e: 4602 mov r2, r0 + 8004040: 68fb ldr r3, [r7, #12] + 8004042: 1ad3 subs r3, r2, r3 + 8004044: 2b02 cmp r3, #2 + 8004046: d901 bls.n 800404c + { + return HAL_TIMEOUT; + 8004048: 2303 movs r3, #3 + 800404a: e0b7 b.n 80041bc + while (LL_RCC_IsActiveFlag_SHDHPRE() == 0U) + 800404c: f7ff fbe6 bl 800381c + 8004050: 4603 mov r3, r0 + 8004052: 2b00 cmp r3, #0 + 8004054: d0f1 beq.n 800403a + } + } + } + + /*-------------------------- PCLK1 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) + 8004056: 687b ldr r3, [r7, #4] + 8004058: 681b ldr r3, [r3, #0] + 800405a: f003 0304 and.w r3, r3, #4 + 800405e: 2b00 cmp r3, #0 + 8004060: d016 beq.n 8004090 + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB1CLKDivider)); + LL_RCC_SetAPB1Prescaler(RCC_ClkInitStruct->APB1CLKDivider); + 8004062: 687b ldr r3, [r7, #4] + 8004064: 68db ldr r3, [r3, #12] + 8004066: 4618 mov r0, r3 + 8004068: f7ff fb19 bl 800369e + + /* APB1 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 800406c: f7fc fe56 bl 8000d1c + 8004070: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8004072: e008 b.n 8004086 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 8004074: f7fc fe52 bl 8000d1c + 8004078: 4602 mov r2, r0 + 800407a: 68fb ldr r3, [r7, #12] + 800407c: 1ad3 subs r3, r2, r3 + 800407e: 2b02 cmp r3, #2 + 8004080: d901 bls.n 8004086 + { + return HAL_TIMEOUT; + 8004082: 2303 movs r3, #3 + 8004084: e09a b.n 80041bc + while (LL_RCC_IsActiveFlag_PPRE1() == 0U) + 8004086: f7ff fbdb bl 8003840 + 800408a: 4603 mov r3, r0 + 800408c: 2b00 cmp r3, #0 + 800408e: d0f1 beq.n 8004074 + } + } + } + + /*-------------------------- PCLK2 Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2) + 8004090: 687b ldr r3, [r7, #4] + 8004092: 681b ldr r3, [r3, #0] + 8004094: f003 0308 and.w r3, r3, #8 + 8004098: 2b00 cmp r3, #0 + 800409a: d017 beq.n 80040cc + { + assert_param(IS_RCC_PCLKx(RCC_ClkInitStruct->APB2CLKDivider)); + LL_RCC_SetAPB2Prescaler((RCC_ClkInitStruct->APB2CLKDivider) << 3U); + 800409c: 687b ldr r3, [r7, #4] + 800409e: 691b ldr r3, [r3, #16] + 80040a0: 00db lsls r3, r3, #3 + 80040a2: 4618 mov r0, r3 + 80040a4: f7ff fb0e bl 80036c4 + + /* APB2 prescaler flag when value applied */ + tickstart = HAL_GetTick(); + 80040a8: f7fc fe38 bl 8000d1c + 80040ac: 60f8 str r0, [r7, #12] + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 80040ae: e008 b.n 80040c2 + { + if ((HAL_GetTick() - tickstart) > PRESCALER_TIMEOUT_VALUE) + 80040b0: f7fc fe34 bl 8000d1c + 80040b4: 4602 mov r2, r0 + 80040b6: 68fb ldr r3, [r7, #12] + 80040b8: 1ad3 subs r3, r2, r3 + 80040ba: 2b02 cmp r3, #2 + 80040bc: d901 bls.n 80040c2 + { + return HAL_TIMEOUT; + 80040be: 2303 movs r3, #3 + 80040c0: e07c b.n 80041bc + while (LL_RCC_IsActiveFlag_PPRE2() == 0U) + 80040c2: f7ff fbce bl 8003862 + 80040c6: 4603 mov r3, r0 + 80040c8: 2b00 cmp r3, #0 + 80040ca: d0f1 beq.n 80040b0 + } + } + } + + /*------------------------- SYSCLK Configuration ---------------------------*/ + if (((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) + 80040cc: 687b ldr r3, [r7, #4] + 80040ce: 681b ldr r3, [r3, #0] + 80040d0: f003 0301 and.w r3, r3, #1 + 80040d4: 2b00 cmp r3, #0 + 80040d6: d043 beq.n 8004160 + { + assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource)); + + /* HSE is selected as System Clock Source */ + if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE) + 80040d8: 687b ldr r3, [r7, #4] + 80040da: 685b ldr r3, [r3, #4] + 80040dc: 2b02 cmp r3, #2 + 80040de: d106 bne.n 80040ee + { + /* Check the HSE ready flag */ + if (LL_RCC_HSE_IsReady() == 0U) + 80040e0: f7ff f99b bl 800341a + 80040e4: 4603 mov r3, r0 + 80040e6: 2b00 cmp r3, #0 + 80040e8: d11e bne.n 8004128 + { + return HAL_ERROR; + 80040ea: 2301 movs r3, #1 + 80040ec: e066 b.n 80041bc + } + } + /* PLL is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) + 80040ee: 687b ldr r3, [r7, #4] + 80040f0: 685b ldr r3, [r3, #4] + 80040f2: 2b03 cmp r3, #3 + 80040f4: d106 bne.n 8004104 + { + /* Check the PLL ready flag */ + if (LL_RCC_PLL_IsReady() == 0U) + 80040f6: f7ff fb42 bl 800377e + 80040fa: 4603 mov r3, r0 + 80040fc: 2b00 cmp r3, #0 + 80040fe: d113 bne.n 8004128 + { + return HAL_ERROR; + 8004100: 2301 movs r3, #1 + 8004102: e05b b.n 80041bc + } + } + /* MSI is selected as System Clock Source */ + else if (RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_MSI) + 8004104: 687b ldr r3, [r7, #4] + 8004106: 685b ldr r3, [r3, #4] + 8004108: 2b00 cmp r3, #0 + 800410a: d106 bne.n 800411a + { + /* Check the MSI ready flag */ + if (LL_RCC_MSI_IsReady() == 0U) + 800410c: f7ff fa35 bl 800357a + 8004110: 4603 mov r3, r0 + 8004112: 2b00 cmp r3, #0 + 8004114: d108 bne.n 8004128 + { + return HAL_ERROR; + 8004116: 2301 movs r3, #1 + 8004118: e050 b.n 80041bc + } + /* HSI is selected as System Clock Source */ + else + { + /* Check the HSI ready flag */ + if (LL_RCC_HSI_IsReady() == 0U) + 800411a: f7ff f9ab bl 8003474 + 800411e: 4603 mov r3, r0 + 8004120: 2b00 cmp r3, #0 + 8004122: d101 bne.n 8004128 + { + return HAL_ERROR; + 8004124: 2301 movs r3, #1 + 8004126: e049 b.n 80041bc + } + + } + + /* apply system clock switch */ + LL_RCC_SetSysClkSource(RCC_ClkInitStruct->SYSCLKSource); + 8004128: 687b ldr r3, [r7, #4] + 800412a: 685b ldr r3, [r3, #4] + 800412c: 4618 mov r0, r3 + 800412e: f7ff fa6f bl 8003610 + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 8004132: f7fc fdf3 bl 8000d1c + 8004136: 60f8 str r0, [r7, #12] + + /* check system clock source switch status */ + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8004138: e00a b.n 8004150 + { + if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE) + 800413a: f7fc fdef bl 8000d1c + 800413e: 4602 mov r2, r0 + 8004140: 68fb ldr r3, [r7, #12] + 8004142: 1ad3 subs r3, r2, r3 + 8004144: f241 3288 movw r2, #5000 ; 0x1388 + 8004148: 4293 cmp r3, r2 + 800414a: d901 bls.n 8004150 + { + return HAL_TIMEOUT; + 800414c: 2303 movs r3, #3 + 800414e: e035 b.n 80041bc + while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos)) + 8004150: f7ff fa71 bl 8003636 + 8004154: 4602 mov r2, r0 + 8004156: 687b ldr r3, [r7, #4] + 8004158: 685b ldr r3, [r3, #4] + 800415a: 009b lsls r3, r3, #2 + 800415c: 429a cmp r2, r3 + 800415e: d1ec bne.n 800413a + } + } + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (FLatency < __HAL_FLASH_GET_LATENCY()) + 8004160: 4b18 ldr r3, [pc, #96] ; (80041c4 ) + 8004162: 681b ldr r3, [r3, #0] + 8004164: f003 0307 and.w r3, r3, #7 + 8004168: 683a ldr r2, [r7, #0] + 800416a: 429a cmp r2, r3 + 800416c: d21b bcs.n 80041a6 + { + /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ + __HAL_FLASH_SET_LATENCY(FLatency); + 800416e: 4b15 ldr r3, [pc, #84] ; (80041c4 ) + 8004170: 681b ldr r3, [r3, #0] + 8004172: f023 0207 bic.w r2, r3, #7 + 8004176: 4913 ldr r1, [pc, #76] ; (80041c4 ) + 8004178: 683b ldr r3, [r7, #0] + 800417a: 4313 orrs r3, r2 + 800417c: 600b str r3, [r1, #0] + + /* Get Start Tick */ + tickstart = HAL_GetTick(); + 800417e: f7fc fdcd bl 8000d1c + 8004182: 60f8 str r0, [r7, #12] + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8004184: e008 b.n 8004198 + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 8004186: f7fc fdc9 bl 8000d1c + 800418a: 4602 mov r2, r0 + 800418c: 68fb ldr r3, [r7, #12] + 800418e: 1ad3 subs r3, r2, r3 + 8004190: 2b02 cmp r3, #2 + 8004192: d901 bls.n 8004198 + { + return HAL_TIMEOUT; + 8004194: 2303 movs r3, #3 + 8004196: e011 b.n 80041bc + while (__HAL_FLASH_GET_LATENCY() != FLatency) + 8004198: 4b0a ldr r3, [pc, #40] ; (80041c4 ) + 800419a: 681b ldr r3, [r3, #0] + 800419c: f003 0307 and.w r3, r3, #7 + 80041a0: 683a ldr r2, [r7, #0] + 80041a2: 429a cmp r2, r3 + 80041a4: d1ef bne.n 8004186 + } + + /*--------------------------------------------------------------------------*/ + + /* Update the SystemCoreClock global variable */ + SystemCoreClock = HAL_RCC_GetHCLKFreq(); + 80041a6: f000 f8b3 bl 8004310 + 80041aa: 4603 mov r3, r0 + 80041ac: 4a06 ldr r2, [pc, #24] ; (80041c8 ) + 80041ae: 6013 str r3, [r2, #0] + + /* Configure the source of time base considering new system clocks settings */ + return HAL_InitTick(uwTickPrio); + 80041b0: 4b06 ldr r3, [pc, #24] ; (80041cc ) + 80041b2: 681b ldr r3, [r3, #0] + 80041b4: 4618 mov r0, r3 + 80041b6: f7fd fd9b bl 8001cf0 + 80041ba: 4603 mov r3, r0 +} + 80041bc: 4618 mov r0, r3 + 80041be: 3710 adds r7, #16 + 80041c0: 46bd mov sp, r7 + 80041c2: bd80 pop {r7, pc} + 80041c4: 58004000 .word 0x58004000 + 80041c8: 20000000 .word 0x20000000 + 80041cc: 20000004 .word 0x20000004 + +080041d0 : + * + * + * @retval SYSCLK frequency + */ +uint32_t HAL_RCC_GetSysClockFreq(void) +{ + 80041d0: b590 push {r4, r7, lr} + 80041d2: b087 sub sp, #28 + 80041d4: af00 add r7, sp, #0 + uint32_t sysclk_source; + uint32_t pllsource; + uint32_t sysclockfreq = 0U; + 80041d6: 2300 movs r3, #0 + 80041d8: 617b str r3, [r7, #20] + uint32_t msifreq = 0U; + 80041da: 2300 movs r3, #0 + 80041dc: 613b str r3, [r7, #16] + uint32_t pllinputfreq; + + sysclk_source = __HAL_RCC_GET_SYSCLK_SOURCE(); + 80041de: f7ff fa2a bl 8003636 + 80041e2: 60b8 str r0, [r7, #8] + pllsource = __HAL_RCC_GET_PLL_OSCSOURCE(); + 80041e4: f7ff fafe bl 80037e4 + 80041e8: 6078 str r0, [r7, #4] + + if ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) || + 80041ea: 68bb ldr r3, [r7, #8] + 80041ec: 2b00 cmp r3, #0 + 80041ee: d005 beq.n 80041fc + 80041f0: 68bb ldr r3, [r7, #8] + 80041f2: 2b0c cmp r3, #12 + 80041f4: d139 bne.n 800426a + ((sysclk_source == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && (pllsource == RCC_PLLSOURCE_MSI))) + 80041f6: 687b ldr r3, [r7, #4] + 80041f8: 2b01 cmp r3, #1 + 80041fa: d136 bne.n 800426a + { + /* MSI or PLL with MSI source used as system clock source */ + /* Retrieve MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSI_IsEnabledRangeSelect(), + 80041fc: f7ff f9cd bl 800359a + 8004200: 4603 mov r3, r0 + 8004202: 2b00 cmp r3, #0 + 8004204: d115 bne.n 8004232 + 8004206: f7ff f9c8 bl 800359a + 800420a: 4603 mov r3, r0 + 800420c: 2b01 cmp r3, #1 + 800420e: d106 bne.n 800421e + 8004210: f7ff f9d3 bl 80035ba + 8004214: 4603 mov r3, r0 + 8004216: 0a1b lsrs r3, r3, #8 + 8004218: f003 030f and.w r3, r3, #15 + 800421c: e005 b.n 800422a + 800421e: f7ff f9d7 bl 80035d0 + 8004222: 4603 mov r3, r0 + 8004224: 0a1b lsrs r3, r3, #8 + 8004226: f003 030f and.w r3, r3, #15 + 800422a: 4a36 ldr r2, [pc, #216] ; (8004304 ) + 800422c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8004230: e014 b.n 800425c + 8004232: f7ff f9b2 bl 800359a + 8004236: 4603 mov r3, r0 + 8004238: 2b01 cmp r3, #1 + 800423a: d106 bne.n 800424a + 800423c: f7ff f9bd bl 80035ba + 8004240: 4603 mov r3, r0 + 8004242: 091b lsrs r3, r3, #4 + 8004244: f003 030f and.w r3, r3, #15 + 8004248: e005 b.n 8004256 + 800424a: f7ff f9c1 bl 80035d0 + 800424e: 4603 mov r3, r0 + 8004250: 091b lsrs r3, r3, #4 + 8004252: f003 030f and.w r3, r3, #15 + 8004256: 4a2b ldr r2, [pc, #172] ; (8004304 ) + 8004258: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800425c: 613b str r3, [r7, #16] + ((LL_RCC_MSI_IsEnabledRangeSelect() == 1U) ? + LL_RCC_MSI_GetRange() : + LL_RCC_MSI_GetRangeAfterStandby())); + + /* Get SYSCLK source */ + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + 800425e: 68bb ldr r3, [r7, #8] + 8004260: 2b00 cmp r3, #0 + 8004262: d115 bne.n 8004290 + { + /* MSI used as system clock source */ + sysclockfreq = msifreq; + 8004264: 693b ldr r3, [r7, #16] + 8004266: 617b str r3, [r7, #20] + if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_MSI) + 8004268: e012 b.n 8004290 + } + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSI) + 800426a: 68bb ldr r3, [r7, #8] + 800426c: 2b04 cmp r3, #4 + 800426e: d102 bne.n 8004276 + { + /* HSI used as system clock source */ + sysclockfreq = HSI_VALUE; + 8004270: 4b25 ldr r3, [pc, #148] ; (8004308 ) + 8004272: 617b str r3, [r7, #20] + 8004274: e00c b.n 8004290 + } + else if (sysclk_source == RCC_SYSCLKSOURCE_STATUS_HSE) + 8004276: 68bb ldr r3, [r7, #8] + 8004278: 2b08 cmp r3, #8 + 800427a: d109 bne.n 8004290 + { + /* HSE used as system clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 800427c: f7ff f8a0 bl 80033c0 + 8004280: 4603 mov r3, r0 + 8004282: 2b01 cmp r3, #1 + 8004284: d102 bne.n 800428c + { + sysclockfreq = HSE_VALUE / 2U; + 8004286: 4b20 ldr r3, [pc, #128] ; (8004308 ) + 8004288: 617b str r3, [r7, #20] + 800428a: e001 b.n 8004290 + } + else + { + sysclockfreq = HSE_VALUE; + 800428c: 4b1f ldr r3, [pc, #124] ; (800430c ) + 800428e: 617b str r3, [r7, #20] + else + { + /* Nothing to do */ + } + + if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) + 8004290: f7ff f9d1 bl 8003636 + 8004294: 4603 mov r3, r0 + 8004296: 2b0c cmp r3, #12 + 8004298: d12f bne.n 80042fa + { + /* PLL used as system clock source */ + pllsource = LL_RCC_PLL_GetMainSource(); + 800429a: f7ff faa3 bl 80037e4 + 800429e: 6078 str r0, [r7, #4] + + switch (pllsource) + 80042a0: 687b ldr r3, [r7, #4] + 80042a2: 2b02 cmp r3, #2 + 80042a4: d003 beq.n 80042ae + 80042a6: 687b ldr r3, [r7, #4] + 80042a8: 2b03 cmp r3, #3 + 80042aa: d003 beq.n 80042b4 + 80042ac: e00d b.n 80042ca + { + case RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + pllinputfreq = HSI_VALUE; + 80042ae: 4b16 ldr r3, [pc, #88] ; (8004308 ) + 80042b0: 60fb str r3, [r7, #12] + break; + 80042b2: e00d b.n 80042d0 + case RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + if (LL_RCC_HSE_IsEnabledDiv2() == 1U) + 80042b4: f7ff f884 bl 80033c0 + 80042b8: 4603 mov r3, r0 + 80042ba: 2b01 cmp r3, #1 + 80042bc: d102 bne.n 80042c4 + { + pllinputfreq = HSE_VALUE / 2U; + 80042be: 4b12 ldr r3, [pc, #72] ; (8004308 ) + 80042c0: 60fb str r3, [r7, #12] + } + else + { + pllinputfreq = HSE_VALUE; + } + break; + 80042c2: e005 b.n 80042d0 + pllinputfreq = HSE_VALUE; + 80042c4: 4b11 ldr r3, [pc, #68] ; (800430c ) + 80042c6: 60fb str r3, [r7, #12] + break; + 80042c8: e002 b.n 80042d0 + case RCC_PLLSOURCE_MSI: /* MSI used as PLL clock source */ + default: + pllinputfreq = msifreq; + 80042ca: 693b ldr r3, [r7, #16] + 80042cc: 60fb str r3, [r7, #12] + break; + 80042ce: bf00 nop + } + sysclockfreq = __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq, LL_RCC_PLL_GetDivider(), + 80042d0: f7ff fa66 bl 80037a0 + 80042d4: 4602 mov r2, r0 + 80042d6: 68fb ldr r3, [r7, #12] + 80042d8: fb03 f402 mul.w r4, r3, r2 + 80042dc: f7ff fa77 bl 80037ce + 80042e0: 4603 mov r3, r0 + 80042e2: 091b lsrs r3, r3, #4 + 80042e4: 3301 adds r3, #1 + 80042e6: fbb4 f4f3 udiv r4, r4, r3 + 80042ea: f7ff fa65 bl 80037b8 + 80042ee: 4603 mov r3, r0 + 80042f0: 0f5b lsrs r3, r3, #29 + 80042f2: 3301 adds r3, #1 + 80042f4: fbb4 f3f3 udiv r3, r4, r3 + 80042f8: 617b str r3, [r7, #20] + LL_RCC_PLL_GetN(), LL_RCC_PLL_GetR()); + } + + return sysclockfreq; + 80042fa: 697b ldr r3, [r7, #20] +} + 80042fc: 4618 mov r0, r3 + 80042fe: 371c adds r7, #28 + 8004300: 46bd mov sp, r7 + 8004302: bd90 pop {r4, r7, pc} + 8004304: 0800e34c .word 0x0800e34c + 8004308: 00f42400 .word 0x00f42400 + 800430c: 01e84800 .word 0x01e84800 + +08004310 : +/** + * @brief Return the HCLK frequency. + * @retval HCLK frequency in Hz + */ +uint32_t HAL_RCC_GetHCLKFreq(void) +{ + 8004310: b598 push {r3, r4, r7, lr} + 8004312: af00 add r7, sp, #0 + /* Get SysClock and Compute HCLK1 frequency --------------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_HCLK1_FREQ(HAL_RCC_GetSysClockFreq(), LL_RCC_GetAHBPrescaler()))); + 8004314: f7ff ff5c bl 80041d0 + 8004318: 4604 mov r4, r0 + 800431a: f7ff f9e6 bl 80036ea + 800431e: 4603 mov r3, r0 + 8004320: 091b lsrs r3, r3, #4 + 8004322: f003 030f and.w r3, r3, #15 + 8004326: 4a03 ldr r2, [pc, #12] ; (8004334 ) + 8004328: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800432c: fbb4 f3f3 udiv r3, r4, r3 +} + 8004330: 4618 mov r0, r3 + 8004332: bd98 pop {r3, r4, r7, pc} + 8004334: 0800e2ec .word 0x0800e2ec + +08004338 : +/** + * @brief Return the PCLK1 frequency. + * @retval PCLK1 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK1Freq(void) +{ + 8004338: b598 push {r3, r4, r7, lr} + 800433a: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK1 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK1_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB1Prescaler()))); + 800433c: f7ff ffe8 bl 8004310 + 8004340: 4604 mov r4, r0 + 8004342: f7ff f9ea bl 800371a + 8004346: 4603 mov r3, r0 + 8004348: 0a1b lsrs r3, r3, #8 + 800434a: 4a03 ldr r2, [pc, #12] ; (8004358 ) + 800434c: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8004350: fa24 f303 lsr.w r3, r4, r3 +} + 8004354: 4618 mov r0, r3 + 8004356: bd98 pop {r3, r4, r7, pc} + 8004358: 0800e32c .word 0x0800e32c + +0800435c : +/** + * @brief Return the PCLK2 frequency. + * @retval PCLK2 frequency in Hz + */ +uint32_t HAL_RCC_GetPCLK2Freq(void) +{ + 800435c: b598 push {r3, r4, r7, lr} + 800435e: af00 add r7, sp, #0 + /* Get HCLK source and Compute PCLK2 frequency -----------------------------*/ + return ((uint32_t)(__LL_RCC_CALC_PCLK2_FREQ(HAL_RCC_GetHCLKFreq(), LL_RCC_GetAPB2Prescaler()))); + 8004360: f7ff ffd6 bl 8004310 + 8004364: 4604 mov r4, r0 + 8004366: f7ff f9e3 bl 8003730 + 800436a: 4603 mov r3, r0 + 800436c: 0adb lsrs r3, r3, #11 + 800436e: 4a03 ldr r2, [pc, #12] ; (800437c ) + 8004370: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8004374: fa24 f303 lsr.w r3, r4, r3 +} + 8004378: 4618 mov r0, r3 + 800437a: bd98 pop {r3, r4, r7, pc} + 800437c: 0800e32c .word 0x0800e32c + +08004380 : + voltage range. + * @param MSI_Range MSI range value from @ref RCC_MSIRANGE_0 to @ref RCC_MSIRANGE_11 + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatencyFromMSIRange(uint32_t MSI_Range) +{ + 8004380: b590 push {r4, r7, lr} + 8004382: b085 sub sp, #20 + 8004384: af00 add r7, sp, #0 + 8004386: 6078 str r0, [r7, #4] + uint32_t flash_clksrcfreq; + uint32_t msifreq; + + /* MSI frequency range in Hz */ + msifreq = __LL_RCC_CALC_MSI_FREQ(LL_RCC_MSIRANGESEL_RUN, MSI_Range); + 8004388: 687b ldr r3, [r7, #4] + 800438a: 091b lsrs r3, r3, #4 + 800438c: f003 030f and.w r3, r3, #15 + 8004390: 4a10 ldr r2, [pc, #64] ; (80043d4 ) + 8004392: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 8004396: 60fb str r3, [r7, #12] + flash_clksrcfreq = __LL_RCC_CALC_HCLK3_FREQ(msifreq, LL_RCC_GetAHB3Prescaler()); + 8004398: f7ff f9b2 bl 8003700 + 800439c: 4603 mov r3, r0 + 800439e: 091b lsrs r3, r3, #4 + 80043a0: f003 030f and.w r3, r3, #15 + 80043a4: 4a0c ldr r2, [pc, #48] ; (80043d8 ) + 80043a6: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 80043aa: 68fa ldr r2, [r7, #12] + 80043ac: fbb2 f3f3 udiv r3, r2, r3 + 80043b0: 60bb str r3, [r7, #8] + + return RCC_SetFlashLatency((flash_clksrcfreq / MEGA_HZ), HAL_PWREx_GetVoltageRange()); + 80043b2: 68bb ldr r3, [r7, #8] + 80043b4: 4a09 ldr r2, [pc, #36] ; (80043dc ) + 80043b6: fba2 2303 umull r2, r3, r2, r3 + 80043ba: 0c9c lsrs r4, r3, #18 + 80043bc: f7fe ff06 bl 80031cc + 80043c0: 4603 mov r3, r0 + 80043c2: 4619 mov r1, r3 + 80043c4: 4620 mov r0, r4 + 80043c6: f000 f80b bl 80043e0 + 80043ca: 4603 mov r3, r0 +} + 80043cc: 4618 mov r0, r3 + 80043ce: 3714 adds r7, #20 + 80043d0: 46bd mov sp, r7 + 80043d2: bd90 pop {r4, r7, pc} + 80043d4: 0800e34c .word 0x0800e34c + 80043d8: 0800e2ec .word 0x0800e2ec + 80043dc: 431bde83 .word 0x431bde83 + +080043e0 : + * @arg PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode + * @arg PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode + * @retval HAL status + */ +static HAL_StatusTypeDef RCC_SetFlashLatency(uint32_t Flash_ClkSrcFreq, uint32_t VCORE_Voltage) +{ + 80043e0: b580 push {r7, lr} + 80043e2: b08e sub sp, #56 ; 0x38 + 80043e4: af00 add r7, sp, #0 + 80043e6: 6078 str r0, [r7, #4] + 80043e8: 6039 str r1, [r7, #0] + /* Flash Clock source (HCLK3) range in MHz for VCORE range1 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS1[] = {18, 36, 48}; + 80043ea: 4a3a ldr r2, [pc, #232] ; (80044d4 ) + 80043ec: f107 0320 add.w r3, r7, #32 + 80043f0: e892 0003 ldmia.w r2, {r0, r1} + 80043f4: 6018 str r0, [r3, #0] + 80043f6: 3304 adds r3, #4 + 80043f8: 8019 strh r1, [r3, #0] + + /* Flash Clock source (HCLK3) range in MHz for VCORE range2 */ + const uint16_t FLASH_CLK_SRC_RANGE_VOS2[] = {6, 12, 16}; + 80043fa: 4a37 ldr r2, [pc, #220] ; (80044d8 ) + 80043fc: f107 0318 add.w r3, r7, #24 + 8004400: e892 0003 ldmia.w r2, {r0, r1} + 8004404: 6018 str r0, [r3, #0] + 8004406: 3304 adds r3, #4 + 8004408: 8019 strh r1, [r3, #0] + + /* Flash Latency range */ + const uint32_t FLASH_LATENCY_RANGE[] = {FLASH_LATENCY_0, FLASH_LATENCY_1, FLASH_LATENCY_2}; + 800440a: 4a34 ldr r2, [pc, #208] ; (80044dc ) + 800440c: f107 030c add.w r3, r7, #12 + 8004410: ca07 ldmia r2, {r0, r1, r2} + 8004412: e883 0007 stmia.w r3, {r0, r1, r2} + + uint32_t latency = FLASH_LATENCY_0; /* default value 0WS */ + 8004416: 2300 movs r3, #0 + 8004418: 637b str r3, [r7, #52] ; 0x34 + uint32_t tickstart; + + if (VCORE_Voltage == PWR_REGULATOR_VOLTAGE_SCALE1) + 800441a: 683b ldr r3, [r7, #0] + 800441c: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8004420: d11b bne.n 800445a + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 8004422: 2300 movs r3, #0 + 8004424: 633b str r3, [r7, #48] ; 0x30 + 8004426: e014 b.n 8004452 + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS1[index]) + 8004428: 6b3b ldr r3, [r7, #48] ; 0x30 + 800442a: 005b lsls r3, r3, #1 + 800442c: 3338 adds r3, #56 ; 0x38 + 800442e: 443b add r3, r7 + 8004430: f833 3c18 ldrh.w r3, [r3, #-24] + 8004434: 461a mov r2, r3 + 8004436: 687b ldr r3, [r7, #4] + 8004438: 4293 cmp r3, r2 + 800443a: d807 bhi.n 800444c + { + latency = FLASH_LATENCY_RANGE[index]; + 800443c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800443e: 009b lsls r3, r3, #2 + 8004440: 3338 adds r3, #56 ; 0x38 + 8004442: 443b add r3, r7 + 8004444: f853 3c2c ldr.w r3, [r3, #-44] + 8004448: 637b str r3, [r7, #52] ; 0x34 + break; + 800444a: e021 b.n 8004490 + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS1); index++) + 800444c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800444e: 3301 adds r3, #1 + 8004450: 633b str r3, [r7, #48] ; 0x30 + 8004452: 6b3b ldr r3, [r7, #48] ; 0x30 + 8004454: 2b02 cmp r3, #2 + 8004456: d9e7 bls.n 8004428 + 8004458: e01a b.n 8004490 + } + } + } + else /* PWR_REGULATOR_VOLTAGE_SCALE2 */ + { + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 800445a: 2300 movs r3, #0 + 800445c: 62fb str r3, [r7, #44] ; 0x2c + 800445e: e014 b.n 800448a + { + if (Flash_ClkSrcFreq <= FLASH_CLK_SRC_RANGE_VOS2[index]) + 8004460: 6afb ldr r3, [r7, #44] ; 0x2c + 8004462: 005b lsls r3, r3, #1 + 8004464: 3338 adds r3, #56 ; 0x38 + 8004466: 443b add r3, r7 + 8004468: f833 3c20 ldrh.w r3, [r3, #-32] + 800446c: 461a mov r2, r3 + 800446e: 687b ldr r3, [r7, #4] + 8004470: 4293 cmp r3, r2 + 8004472: d807 bhi.n 8004484 + { + latency = FLASH_LATENCY_RANGE[index]; + 8004474: 6afb ldr r3, [r7, #44] ; 0x2c + 8004476: 009b lsls r3, r3, #2 + 8004478: 3338 adds r3, #56 ; 0x38 + 800447a: 443b add r3, r7 + 800447c: f853 3c2c ldr.w r3, [r3, #-44] + 8004480: 637b str r3, [r7, #52] ; 0x34 + break; + 8004482: e005 b.n 8004490 + for (uint32_t index = 0; index < __COUNTOF(FLASH_CLK_SRC_RANGE_VOS2); index++) + 8004484: 6afb ldr r3, [r7, #44] ; 0x2c + 8004486: 3301 adds r3, #1 + 8004488: 62fb str r3, [r7, #44] ; 0x2c + 800448a: 6afb ldr r3, [r7, #44] ; 0x2c + 800448c: 2b02 cmp r3, #2 + 800448e: d9e7 bls.n 8004460 + } + } + } + + __HAL_FLASH_SET_LATENCY(latency); + 8004490: 4b13 ldr r3, [pc, #76] ; (80044e0 ) + 8004492: 681b ldr r3, [r3, #0] + 8004494: f023 0207 bic.w r2, r3, #7 + 8004498: 4911 ldr r1, [pc, #68] ; (80044e0 ) + 800449a: 6b7b ldr r3, [r7, #52] ; 0x34 + 800449c: 4313 orrs r3, r2 + 800449e: 600b str r3, [r1, #0] + + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 80044a0: f7fc fc3c bl 8000d1c + 80044a4: 62b8 str r0, [r7, #40] ; 0x28 + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + while (__HAL_FLASH_GET_LATENCY() != latency) + 80044a6: e008 b.n 80044ba + { + if ((HAL_GetTick() - tickstart) > LATENCY_TIMEOUT_VALUE) + 80044a8: f7fc fc38 bl 8000d1c + 80044ac: 4602 mov r2, r0 + 80044ae: 6abb ldr r3, [r7, #40] ; 0x28 + 80044b0: 1ad3 subs r3, r2, r3 + 80044b2: 2b02 cmp r3, #2 + 80044b4: d901 bls.n 80044ba + { + return HAL_TIMEOUT; + 80044b6: 2303 movs r3, #3 + 80044b8: e007 b.n 80044ca + while (__HAL_FLASH_GET_LATENCY() != latency) + 80044ba: 4b09 ldr r3, [pc, #36] ; (80044e0 ) + 80044bc: 681b ldr r3, [r3, #0] + 80044be: f003 0307 and.w r3, r3, #7 + 80044c2: 6b7a ldr r2, [r7, #52] ; 0x34 + 80044c4: 429a cmp r2, r3 + 80044c6: d1ef bne.n 80044a8 + } + } + return HAL_OK; + 80044c8: 2300 movs r3, #0 +} + 80044ca: 4618 mov r0, r3 + 80044cc: 3738 adds r7, #56 ; 0x38 + 80044ce: 46bd mov sp, r7 + 80044d0: bd80 pop {r7, pc} + 80044d2: bf00 nop + 80044d4: 0800e004 .word 0x0800e004 + 80044d8: 0800e00c .word 0x0800e00c + 80044dc: 0800e014 .word 0x0800e014 + 80044e0: 58004000 .word 0x58004000 + +080044e4 : +{ + 80044e4: b480 push {r7} + 80044e6: af00 add r7, sp, #0 + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); + 80044e8: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80044ec: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80044f0: f003 0302 and.w r3, r3, #2 + 80044f4: 2b02 cmp r3, #2 + 80044f6: d101 bne.n 80044fc + 80044f8: 2301 movs r3, #1 + 80044fa: e000 b.n 80044fe + 80044fc: 2300 movs r3, #0 +} + 80044fe: 4618 mov r0, r3 + 8004500: 46bd mov sp, r7 + 8004502: bc80 pop {r7} + 8004504: 4770 bx lr + +08004506 : +{ + 8004506: b480 push {r7} + 8004508: b083 sub sp, #12 + 800450a: af00 add r7, sp, #0 + 800450c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (USARTxSource >> 16), (USARTxSource & 0x0000FFFFU)); + 800450e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004512: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 8004516: 687b ldr r3, [r7, #4] + 8004518: 0c1b lsrs r3, r3, #16 + 800451a: 43db mvns r3, r3 + 800451c: 401a ands r2, r3 + 800451e: 687b ldr r3, [r7, #4] + 8004520: b29b uxth r3, r3 + 8004522: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8004526: 4313 orrs r3, r2 + 8004528: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 800452c: bf00 nop + 800452e: 370c adds r7, #12 + 8004530: 46bd mov sp, r7 + 8004532: bc80 pop {r7} + 8004534: 4770 bx lr + +08004536 : +{ + 8004536: b480 push {r7} + 8004538: b083 sub sp, #12 + 800453a: af00 add r7, sp, #0 + 800453c: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2S2SEL, I2SxSource); + 800453e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004542: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8004546: f423 7240 bic.w r2, r3, #768 ; 0x300 + 800454a: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800454e: 687b ldr r3, [r7, #4] + 8004550: 4313 orrs r3, r2 + 8004552: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 8004556: bf00 nop + 8004558: 370c adds r7, #12 + 800455a: 46bd mov sp, r7 + 800455c: bc80 pop {r7} + 800455e: 4770 bx lr + +08004560 : +{ + 8004560: b480 push {r7} + 8004562: b083 sub sp, #12 + 8004564: af00 add r7, sp, #0 + 8004566: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, LPUARTxSource); + 8004568: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800456c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8004570: f423 6240 bic.w r2, r3, #3072 ; 0xc00 + 8004574: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8004578: 687b ldr r3, [r7, #4] + 800457a: 4313 orrs r3, r2 + 800457c: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 8004580: bf00 nop + 8004582: 370c adds r7, #12 + 8004584: 46bd mov sp, r7 + 8004586: bc80 pop {r7} + 8004588: 4770 bx lr + +0800458a : +{ + 800458a: b480 push {r7} + 800458c: b083 sub sp, #12 + 800458e: af00 add r7, sp, #0 + 8004590: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, ((I2CxSource >> 4) & 0x000FF000U), ((I2CxSource << 4) & 0x000FF000U)); + 8004592: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004596: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 800459a: 687b ldr r3, [r7, #4] + 800459c: 091b lsrs r3, r3, #4 + 800459e: f403 237f and.w r3, r3, #1044480 ; 0xff000 + 80045a2: 43db mvns r3, r3 + 80045a4: 401a ands r2, r3 + 80045a6: 687b ldr r3, [r7, #4] + 80045a8: 011b lsls r3, r3, #4 + 80045aa: f403 237f and.w r3, r3, #1044480 ; 0xff000 + 80045ae: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80045b2: 4313 orrs r3, r2 + 80045b4: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 80045b8: bf00 nop + 80045ba: 370c adds r7, #12 + 80045bc: 46bd mov sp, r7 + 80045be: bc80 pop {r7} + 80045c0: 4770 bx lr + +080045c2 : +{ + 80045c2: b480 push {r7} + 80045c4: b083 sub sp, #12 + 80045c6: af00 add r7, sp, #0 + 80045c8: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16)); + 80045ca: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80045ce: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 80045d2: 687b ldr r3, [r7, #4] + 80045d4: 0c1b lsrs r3, r3, #16 + 80045d6: 041b lsls r3, r3, #16 + 80045d8: 43db mvns r3, r3 + 80045da: 401a ands r2, r3 + 80045dc: 687b ldr r3, [r7, #4] + 80045de: 041b lsls r3, r3, #16 + 80045e0: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 80045e4: 4313 orrs r3, r2 + 80045e6: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 80045ea: bf00 nop + 80045ec: 370c adds r7, #12 + 80045ee: 46bd mov sp, r7 + 80045f0: bc80 pop {r7} + 80045f2: 4770 bx lr + +080045f4 : +{ + 80045f4: b480 push {r7} + 80045f6: b083 sub sp, #12 + 80045f8: af00 add r7, sp, #0 + 80045fa: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_RNGSEL, RNGxSource); + 80045fc: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004600: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8004604: f023 4240 bic.w r2, r3, #3221225472 ; 0xc0000000 + 8004608: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 800460c: 687b ldr r3, [r7, #4] + 800460e: 4313 orrs r3, r2 + 8004610: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 8004614: bf00 nop + 8004616: 370c adds r7, #12 + 8004618: 46bd mov sp, r7 + 800461a: bc80 pop {r7} + 800461c: 4770 bx lr + +0800461e : +{ + 800461e: b480 push {r7} + 8004620: b083 sub sp, #12 + 8004622: af00 add r7, sp, #0 + 8004624: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_ADCSEL, ADCxSource); + 8004626: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800462a: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 800462e: f023 5240 bic.w r2, r3, #805306368 ; 0x30000000 + 8004632: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8004636: 687b ldr r3, [r7, #4] + 8004638: 4313 orrs r3, r2 + 800463a: f8c1 3088 str.w r3, [r1, #136] ; 0x88 +} + 800463e: bf00 nop + 8004640: 370c adds r7, #12 + 8004642: 46bd mov sp, r7 + 8004644: bc80 pop {r7} + 8004646: 4770 bx lr + +08004648 : +{ + 8004648: b480 push {r7} + 800464a: b083 sub sp, #12 + 800464c: af00 add r7, sp, #0 + 800464e: 6078 str r0, [r7, #4] + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); + 8004650: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004654: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004658: f423 7240 bic.w r2, r3, #768 ; 0x300 + 800465c: f04f 41b0 mov.w r1, #1476395008 ; 0x58000000 + 8004660: 687b ldr r3, [r7, #4] + 8004662: 4313 orrs r3, r2 + 8004664: f8c1 3090 str.w r3, [r1, #144] ; 0x90 +} + 8004668: bf00 nop + 800466a: 370c adds r7, #12 + 800466c: 46bd mov sp, r7 + 800466e: bc80 pop {r7} + 8004670: 4770 bx lr + +08004672 : +{ + 8004672: b480 push {r7} + 8004674: af00 add r7, sp, #0 + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); + 8004676: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800467a: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800467e: f403 7340 and.w r3, r3, #768 ; 0x300 +} + 8004682: 4618 mov r0, r3 + 8004684: 46bd mov sp, r7 + 8004686: bc80 pop {r7} + 8004688: 4770 bx lr + +0800468a : +{ + 800468a: b480 push {r7} + 800468c: af00 add r7, sp, #0 + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 800468e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004692: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004696: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800469a: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 800469e: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 80046a2: bf00 nop + 80046a4: 46bd mov sp, r7 + 80046a6: bc80 pop {r7} + 80046a8: 4770 bx lr + +080046aa : +{ + 80046aa: b480 push {r7} + 80046ac: af00 add r7, sp, #0 + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); + 80046ae: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80046b2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80046b6: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80046ba: f423 3380 bic.w r3, r3, #65536 ; 0x10000 + 80046be: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 80046c2: bf00 nop + 80046c4: 46bd mov sp, r7 + 80046c6: bc80 pop {r7} + 80046c8: 4770 bx lr + ... + +080046cc : + * the RTC clock source: in this case the access to Backup domain is enabled. + * + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit) +{ + 80046cc: b580 push {r7, lr} + 80046ce: b086 sub sp, #24 + 80046d0: af00 add r7, sp, #0 + 80046d2: 6078 str r0, [r7, #4] + uint32_t tmpregister = 0; + 80046d4: 2300 movs r3, #0 + 80046d6: 617b str r3, [r7, #20] + uint32_t tickstart; + HAL_StatusTypeDef ret = HAL_OK; /* Intermediate status */ + 80046d8: 2300 movs r3, #0 + 80046da: 74fb strb r3, [r7, #19] + HAL_StatusTypeDef status = HAL_OK; /* Final status */ + 80046dc: 2300 movs r3, #0 + 80046de: 74bb strb r3, [r7, #18] + + /* Check the parameters */ + assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection)); + + /*-------------------------- RTC clock source configuration ----------------------*/ + if ((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) + 80046e0: 687b ldr r3, [r7, #4] + 80046e2: 681b ldr r3, [r3, #0] + 80046e4: f403 3380 and.w r3, r3, #65536 ; 0x10000 + 80046e8: 2b00 cmp r3, #0 + 80046ea: d058 beq.n 800479e + /* Check for RTC Parameters used to output RTCCLK */ + assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection)); + + + /* Enable write access to Backup domain */ + HAL_PWR_EnableBkUpAccess(); + 80046ec: f7fe fd14 bl 8003118 + + /* Wait for Backup domain Write protection disable */ + tickstart = HAL_GetTick(); + 80046f0: f7fc fb14 bl 8000d1c + 80046f4: 60f8 str r0, [r7, #12] + + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + 80046f6: e009 b.n 800470c + { + if ((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE) + 80046f8: f7fc fb10 bl 8000d1c + 80046fc: 4602 mov r2, r0 + 80046fe: 68fb ldr r3, [r7, #12] + 8004700: 1ad3 subs r3, r2, r3 + 8004702: 2b02 cmp r3, #2 + 8004704: d902 bls.n 800470c + { + ret = HAL_TIMEOUT; + 8004706: 2303 movs r3, #3 + 8004708: 74fb strb r3, [r7, #19] + break; + 800470a: e006 b.n 800471a + while (!(READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP))) + 800470c: 4b7b ldr r3, [pc, #492] ; (80048fc ) + 800470e: 681b ldr r3, [r3, #0] + 8004710: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004714: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004718: d1ee bne.n 80046f8 + } + } + + if (ret == HAL_OK) + 800471a: 7cfb ldrb r3, [r7, #19] + 800471c: 2b00 cmp r3, #0 + 800471e: d13c bne.n 800479a + { + /* Reset the Backup domain only if the RTC Clock source selection is modified */ + if (LL_RCC_GetRTCClockSource() != PeriphClkInit->RTCClockSelection) + 8004720: f7ff ffa7 bl 8004672 + 8004724: 4602 mov r2, r0 + 8004726: 687b ldr r3, [r7, #4] + 8004728: 6b5b ldr r3, [r3, #52] ; 0x34 + 800472a: 429a cmp r2, r3 + 800472c: d00f beq.n 800474e + { + /* Store the content of BDCR register before the reset of Backup Domain */ + tmpregister = READ_BIT(RCC->BDCR, ~(RCC_BDCR_RTCSEL)); + 800472e: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004732: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8004736: f423 7340 bic.w r3, r3, #768 ; 0x300 + 800473a: 617b str r3, [r7, #20] + + /* RTC Clock selection can be changed only if the Backup Domain is reset */ + __HAL_RCC_BACKUPRESET_FORCE(); + 800473c: f7ff ffa5 bl 800468a + __HAL_RCC_BACKUPRESET_RELEASE(); + 8004740: f7ff ffb3 bl 80046aa + + /* Restore the Content of BDCR register */ + RCC->BDCR = tmpregister; + 8004744: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 8004748: 697b ldr r3, [r7, #20] + 800474a: f8c2 3090 str.w r3, [r2, #144] ; 0x90 + } + + /* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */ + if (HAL_IS_BIT_SET(tmpregister, RCC_BDCR_LSERDY)) + 800474e: 697b ldr r3, [r7, #20] + 8004750: f003 0302 and.w r3, r3, #2 + 8004754: 2b00 cmp r3, #0 + 8004756: d014 beq.n 8004782 + { + /* Get Start Tick*/ + tickstart = HAL_GetTick(); + 8004758: f7fc fae0 bl 8000d1c + 800475c: 60f8 str r0, [r7, #12] + + /* Wait till LSE is ready */ + while (LL_RCC_LSE_IsReady() != 1U) + 800475e: e00b b.n 8004778 + { + if ((HAL_GetTick() - tickstart) > RCC_LSE_TIMEOUT_VALUE) + 8004760: f7fc fadc bl 8000d1c + 8004764: 4602 mov r2, r0 + 8004766: 68fb ldr r3, [r7, #12] + 8004768: 1ad3 subs r3, r2, r3 + 800476a: f241 3288 movw r2, #5000 ; 0x1388 + 800476e: 4293 cmp r3, r2 + 8004770: d902 bls.n 8004778 + { + ret = HAL_TIMEOUT; + 8004772: 2303 movs r3, #3 + 8004774: 74fb strb r3, [r7, #19] + break; + 8004776: e004 b.n 8004782 + while (LL_RCC_LSE_IsReady() != 1U) + 8004778: f7ff feb4 bl 80044e4 + 800477c: 4603 mov r3, r0 + 800477e: 2b01 cmp r3, #1 + 8004780: d1ee bne.n 8004760 + } + } + } + + if (ret == HAL_OK) + 8004782: 7cfb ldrb r3, [r7, #19] + 8004784: 2b00 cmp r3, #0 + 8004786: d105 bne.n 8004794 + { + /* Apply new RTC clock source selection */ + __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection); + 8004788: 687b ldr r3, [r7, #4] + 800478a: 6b5b ldr r3, [r3, #52] ; 0x34 + 800478c: 4618 mov r0, r3 + 800478e: f7ff ff5b bl 8004648 + 8004792: e004 b.n 800479e + } + else + { + /* set overall return value */ + status = ret; + 8004794: 7cfb ldrb r3, [r7, #19] + 8004796: 74bb strb r3, [r7, #18] + 8004798: e001 b.n 800479e + } + } + else + { + /* set overall return value */ + status = ret; + 800479a: 7cfb ldrb r3, [r7, #19] + 800479c: 74bb strb r3, [r7, #18] + } + + } + + /*-------------------- USART1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) + 800479e: 687b ldr r3, [r7, #4] + 80047a0: 681b ldr r3, [r3, #0] + 80047a2: f003 0301 and.w r3, r3, #1 + 80047a6: 2b00 cmp r3, #0 + 80047a8: d004 beq.n 80047b4 + { + /* Check the parameters */ + assert_param(IS_RCC_USART1CLKSOURCE(PeriphClkInit->Usart1ClockSelection)); + + /* Configure the USART1 clock source */ + __HAL_RCC_USART1_CONFIG(PeriphClkInit->Usart1ClockSelection); + 80047aa: 687b ldr r3, [r7, #4] + 80047ac: 685b ldr r3, [r3, #4] + 80047ae: 4618 mov r0, r3 + 80047b0: f7ff fea9 bl 8004506 + } + + /*-------------------- USART2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) + 80047b4: 687b ldr r3, [r7, #4] + 80047b6: 681b ldr r3, [r3, #0] + 80047b8: f003 0302 and.w r3, r3, #2 + 80047bc: 2b00 cmp r3, #0 + 80047be: d004 beq.n 80047ca + { + /* Check the parameters */ + assert_param(IS_RCC_USART2CLKSOURCE(PeriphClkInit->Usart2ClockSelection)); + + /* Configure the USART2 clock source */ + __HAL_RCC_USART2_CONFIG(PeriphClkInit->Usart2ClockSelection); + 80047c0: 687b ldr r3, [r7, #4] + 80047c2: 689b ldr r3, [r3, #8] + 80047c4: 4618 mov r0, r3 + 80047c6: f7ff fe9e bl 8004506 + } + + /*-------------------- LPUART1 clock source configuration ------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPUART1) == RCC_PERIPHCLK_LPUART1) + 80047ca: 687b ldr r3, [r7, #4] + 80047cc: 681b ldr r3, [r3, #0] + 80047ce: f003 0320 and.w r3, r3, #32 + 80047d2: 2b00 cmp r3, #0 + 80047d4: d004 beq.n 80047e0 + { + /* Check the parameters */ + assert_param(IS_RCC_LPUART1CLKSOURCE(PeriphClkInit->Lpuart1ClockSelection)); + + /* Configure the LPUAR1 clock source */ + __HAL_RCC_LPUART1_CONFIG(PeriphClkInit->Lpuart1ClockSelection); + 80047d6: 687b ldr r3, [r7, #4] + 80047d8: 691b ldr r3, [r3, #16] + 80047da: 4618 mov r0, r3 + 80047dc: f7ff fec0 bl 8004560 + } + + /*-------------------- LPTIM1 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == (RCC_PERIPHCLK_LPTIM1)) + 80047e0: 687b ldr r3, [r7, #4] + 80047e2: 681b ldr r3, [r3, #0] + 80047e4: f403 7300 and.w r3, r3, #512 ; 0x200 + 80047e8: 2b00 cmp r3, #0 + 80047ea: d004 beq.n 80047f6 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection)); + + /* Configure the LPTIM1 clock source */ + __HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection); + 80047ec: 687b ldr r3, [r7, #4] + 80047ee: 6a1b ldr r3, [r3, #32] + 80047f0: 4618 mov r0, r3 + 80047f2: f7ff fee6 bl 80045c2 + } + + /*-------------------- LPTIM2 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM2) == (RCC_PERIPHCLK_LPTIM2)) + 80047f6: 687b ldr r3, [r7, #4] + 80047f8: 681b ldr r3, [r3, #0] + 80047fa: f403 6380 and.w r3, r3, #1024 ; 0x400 + 80047fe: 2b00 cmp r3, #0 + 8004800: d004 beq.n 800480c + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM2CLKSOURCE(PeriphClkInit->Lptim2ClockSelection)); + + /* Configure the LPTIM2 clock source */ + __HAL_RCC_LPTIM2_CONFIG(PeriphClkInit->Lptim2ClockSelection); + 8004802: 687b ldr r3, [r7, #4] + 8004804: 6a5b ldr r3, [r3, #36] ; 0x24 + 8004806: 4618 mov r0, r3 + 8004808: f7ff fedb bl 80045c2 + } + + /*-------------------- LPTIM3 clock source configuration -------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM3) == (RCC_PERIPHCLK_LPTIM3)) + 800480c: 687b ldr r3, [r7, #4] + 800480e: 681b ldr r3, [r3, #0] + 8004810: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8004814: 2b00 cmp r3, #0 + 8004816: d004 beq.n 8004822 + { + /* Check the parameters */ + assert_param(IS_RCC_LPTIM3CLKSOURCE(PeriphClkInit->Lptim3ClockSelection)); + + /* Configure the LPTIM3 clock source */ + __HAL_RCC_LPTIM3_CONFIG(PeriphClkInit->Lptim3ClockSelection); + 8004818: 687b ldr r3, [r7, #4] + 800481a: 6a9b ldr r3, [r3, #40] ; 0x28 + 800481c: 4618 mov r0, r3 + 800481e: f7ff fed0 bl 80045c2 + } + + /*-------------------- I2C1 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) + 8004822: 687b ldr r3, [r7, #4] + 8004824: 681b ldr r3, [r3, #0] + 8004826: f003 0340 and.w r3, r3, #64 ; 0x40 + 800482a: 2b00 cmp r3, #0 + 800482c: d004 beq.n 8004838 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C1CLKSOURCE(PeriphClkInit->I2c1ClockSelection)); + + /* Configure the I2C1 clock source */ + __HAL_RCC_I2C1_CONFIG(PeriphClkInit->I2c1ClockSelection); + 800482e: 687b ldr r3, [r7, #4] + 8004830: 695b ldr r3, [r3, #20] + 8004832: 4618 mov r0, r3 + 8004834: f7ff fea9 bl 800458a + } + + /*-------------------- I2C2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) + 8004838: 687b ldr r3, [r7, #4] + 800483a: 681b ldr r3, [r3, #0] + 800483c: f003 0380 and.w r3, r3, #128 ; 0x80 + 8004840: 2b00 cmp r3, #0 + 8004842: d004 beq.n 800484e + { + /* Check the parameters */ + assert_param(IS_RCC_I2C2CLKSOURCE(PeriphClkInit->I2c2ClockSelection)); + + /* Configure the I2C2 clock source */ + __HAL_RCC_I2C2_CONFIG(PeriphClkInit->I2c2ClockSelection); + 8004844: 687b ldr r3, [r7, #4] + 8004846: 699b ldr r3, [r3, #24] + 8004848: 4618 mov r0, r3 + 800484a: f7ff fe9e bl 800458a + } + + /*-------------------- I2C3 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) + 800484e: 687b ldr r3, [r7, #4] + 8004850: 681b ldr r3, [r3, #0] + 8004852: f403 7380 and.w r3, r3, #256 ; 0x100 + 8004856: 2b00 cmp r3, #0 + 8004858: d004 beq.n 8004864 + { + /* Check the parameters */ + assert_param(IS_RCC_I2C3CLKSOURCE(PeriphClkInit->I2c3ClockSelection)); + + /* Configure the I2C3 clock source */ + __HAL_RCC_I2C3_CONFIG(PeriphClkInit->I2c3ClockSelection); + 800485a: 687b ldr r3, [r7, #4] + 800485c: 69db ldr r3, [r3, #28] + 800485e: 4618 mov r0, r3 + 8004860: f7ff fe93 bl 800458a + } + + /*-------------------- I2S2 clock source configuration ---------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S2) == (RCC_PERIPHCLK_I2S2)) + 8004864: 687b ldr r3, [r7, #4] + 8004866: 681b ldr r3, [r3, #0] + 8004868: f003 0310 and.w r3, r3, #16 + 800486c: 2b00 cmp r3, #0 + 800486e: d011 beq.n 8004894 + { + /* Check the parameters */ + assert_param(IS_RCC_I2S2CLKSOURCE(PeriphClkInit->I2s2ClockSelection)); + + /* Configure the I2S2 clock source */ + __HAL_RCC_I2S2_CONFIG(PeriphClkInit->I2s2ClockSelection); + 8004870: 687b ldr r3, [r7, #4] + 8004872: 68db ldr r3, [r3, #12] + 8004874: 4618 mov r0, r3 + 8004876: f7ff fe5e bl 8004536 + + if (PeriphClkInit->I2s2ClockSelection == RCC_I2S2CLKSOURCE_PLL) + 800487a: 687b ldr r3, [r7, #4] + 800487c: 68db ldr r3, [r3, #12] + 800487e: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004882: d107 bne.n 8004894 + { + /* Enable RCC_PLL_I2S2CLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_I2S2CLK); + 8004884: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8004888: 68db ldr r3, [r3, #12] + 800488a: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800488e: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 8004892: 60d3 str r3, [r2, #12] + } + } + + /*-------------------- RNG clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RNG) == (RCC_PERIPHCLK_RNG)) + 8004894: 687b ldr r3, [r7, #4] + 8004896: 681b ldr r3, [r3, #0] + 8004898: f403 4300 and.w r3, r3, #32768 ; 0x8000 + 800489c: 2b00 cmp r3, #0 + 800489e: d010 beq.n 80048c2 + { + assert_param(IS_RCC_RNGCLKSOURCE(PeriphClkInit->RngClockSelection)); + __HAL_RCC_RNG_CONFIG(PeriphClkInit->RngClockSelection); + 80048a0: 687b ldr r3, [r7, #4] + 80048a2: 6b1b ldr r3, [r3, #48] ; 0x30 + 80048a4: 4618 mov r0, r3 + 80048a6: f7ff fea5 bl 80045f4 + + if (PeriphClkInit->RngClockSelection == RCC_RNGCLKSOURCE_PLL) + 80048aa: 687b ldr r3, [r7, #4] + 80048ac: 6b1b ldr r3, [r3, #48] ; 0x30 + 80048ae: 2b00 cmp r3, #0 + 80048b0: d107 bne.n 80048c2 + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_RNGCLK); + 80048b2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80048b6: 68db ldr r3, [r3, #12] + 80048b8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80048bc: f043 7380 orr.w r3, r3, #16777216 ; 0x1000000 + 80048c0: 60d3 str r3, [r2, #12] + } + } + + /*-------------------- ADC clock source configuration ----------------------*/ + if (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_ADC) == RCC_PERIPHCLK_ADC) + 80048c2: 687b ldr r3, [r7, #4] + 80048c4: 681b ldr r3, [r3, #0] + 80048c6: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80048ca: 2b00 cmp r3, #0 + 80048cc: d011 beq.n 80048f2 + { + /* Check the parameters */ + assert_param(IS_RCC_ADCCLKSOURCE(PeriphClkInit->AdcClockSelection)); + + /* Configure the ADC interface clock source */ + __HAL_RCC_ADC_CONFIG(PeriphClkInit->AdcClockSelection); + 80048ce: 687b ldr r3, [r7, #4] + 80048d0: 6adb ldr r3, [r3, #44] ; 0x2c + 80048d2: 4618 mov r0, r3 + 80048d4: f7ff fea3 bl 800461e + + if (PeriphClkInit->AdcClockSelection == RCC_ADCCLKSOURCE_PLL) + 80048d8: 687b ldr r3, [r7, #4] + 80048da: 6adb ldr r3, [r3, #44] ; 0x2c + 80048dc: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 80048e0: d107 bne.n 80048f2 + { + /* Enable RCC_PLL_RNGCLK output */ + __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL_ADCCLK); + 80048e2: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80048e6: 68db ldr r3, [r3, #12] + 80048e8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80048ec: f443 3380 orr.w r3, r3, #65536 ; 0x10000 + 80048f0: 60d3 str r3, [r2, #12] + } + } + + return status; + 80048f2: 7cbb ldrb r3, [r7, #18] +} + 80048f4: 4618 mov r0, r3 + 80048f6: 3718 adds r7, #24 + 80048f8: 46bd mov sp, r7 + 80048fa: bd80 pop {r7, pc} + 80048fc: 58000400 .word 0x58000400 + +08004900 : + * @brief Initialize the RTC peripheral + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc) +{ + 8004900: b580 push {r7, lr} + 8004902: b084 sub sp, #16 + 8004904: af00 add r7, sp, #0 + 8004906: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_ERROR; + 8004908: 2301 movs r3, #1 + 800490a: 73fb strb r3, [r7, #15] + + /* Check the RTC peripheral state */ + if (hrtc != NULL) + 800490c: 687b ldr r3, [r7, #4] + 800490e: 2b00 cmp r3, #0 + 8004910: d071 beq.n 80049f6 + { + hrtc->MspDeInitCallback = HAL_RTC_MspDeInit; + } + } +#else + if (hrtc->State == HAL_RTC_STATE_RESET) + 8004912: 687b ldr r3, [r7, #4] + 8004914: f893 302d ldrb.w r3, [r3, #45] ; 0x2d + 8004918: b2db uxtb r3, r3 + 800491a: 2b00 cmp r3, #0 + 800491c: d106 bne.n 800492c + { + /* Allocate lock resource and initialize it */ + hrtc->Lock = HAL_UNLOCKED; + 800491e: 687b ldr r3, [r7, #4] + 8004920: 2200 movs r2, #0 + 8004922: f883 202c strb.w r2, [r3, #44] ; 0x2c + + /* Initialize RTC MSP */ + HAL_RTC_MspInit(hrtc); + 8004926: 6878 ldr r0, [r7, #4] + 8004928: f7fc f858 bl 80009dc + } +#endif /* (USE_HAL_RTC_REGISTER_CALLBACKS) */ + + /* Set RTC state */ + hrtc->State = HAL_RTC_STATE_BUSY; + 800492c: 687b ldr r3, [r7, #4] + 800492e: 2202 movs r2, #2 + 8004930: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Check if the calendar has been not initialized */ + if (__HAL_RTC_IS_CALENDAR_INITIALIZED(hrtc) == 0U) + 8004934: 4b32 ldr r3, [pc, #200] ; (8004a00 ) + 8004936: 68db ldr r3, [r3, #12] + 8004938: f003 0310 and.w r3, r3, #16 + 800493c: 2b10 cmp r3, #16 + 800493e: d051 beq.n 80049e4 + { + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004940: 4b2f ldr r3, [pc, #188] ; (8004a00 ) + 8004942: 22ca movs r2, #202 ; 0xca + 8004944: 625a str r2, [r3, #36] ; 0x24 + 8004946: 4b2e ldr r3, [pc, #184] ; (8004a00 ) + 8004948: 2253 movs r2, #83 ; 0x53 + 800494a: 625a str r2, [r3, #36] ; 0x24 + + /* Enter Initialization mode */ + status = RTC_EnterInitMode(hrtc); + 800494c: 6878 ldr r0, [r7, #4] + 800494e: f000 f9e7 bl 8004d20 + 8004952: 4603 mov r3, r0 + 8004954: 73fb strb r3, [r7, #15] + if (status == HAL_OK) + 8004956: 7bfb ldrb r3, [r7, #15] + 8004958: 2b00 cmp r3, #0 + 800495a: d13f bne.n 80049dc + { + /* Clear RTC_CR FMT, OSEL and POL Bits */ + CLEAR_BIT(RTC->CR, (RTC_CR_FMT | RTC_CR_POL | RTC_CR_OSEL | RTC_CR_TAMPOE)); + 800495c: 4b28 ldr r3, [pc, #160] ; (8004a00 ) + 800495e: 699b ldr r3, [r3, #24] + 8004960: 4a27 ldr r2, [pc, #156] ; (8004a00 ) + 8004962: f023 638e bic.w r3, r3, #74448896 ; 0x4700000 + 8004966: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800496a: 6193 str r3, [r2, #24] + /* Set RTC_CR register */ + SET_BIT(RTC->CR, (hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity)); + 800496c: 4b24 ldr r3, [pc, #144] ; (8004a00 ) + 800496e: 699a ldr r2, [r3, #24] + 8004970: 687b ldr r3, [r7, #4] + 8004972: 6859 ldr r1, [r3, #4] + 8004974: 687b ldr r3, [r7, #4] + 8004976: 691b ldr r3, [r3, #16] + 8004978: 4319 orrs r1, r3 + 800497a: 687b ldr r3, [r7, #4] + 800497c: 699b ldr r3, [r3, #24] + 800497e: 430b orrs r3, r1 + 8004980: 491f ldr r1, [pc, #124] ; (8004a00 ) + 8004982: 4313 orrs r3, r2 + 8004984: 618b str r3, [r1, #24] + + /* Configure the RTC PRER */ + WRITE_REG(RTC->PRER, ((hrtc->Init.SynchPrediv) | (hrtc->Init.AsynchPrediv << RTC_PRER_PREDIV_A_Pos))); + 8004986: 687b ldr r3, [r7, #4] + 8004988: 68da ldr r2, [r3, #12] + 800498a: 687b ldr r3, [r7, #4] + 800498c: 689b ldr r3, [r3, #8] + 800498e: 041b lsls r3, r3, #16 + 8004990: 491b ldr r1, [pc, #108] ; (8004a00 ) + 8004992: 4313 orrs r3, r2 + 8004994: 610b str r3, [r1, #16] + + /* Configure the Binary mode */ + MODIFY_REG(RTC->ICSR, RTC_ICSR_BIN | RTC_ICSR_BCDU, hrtc->Init.BinMode | hrtc->Init.BinMixBcdU); + 8004996: 4b1a ldr r3, [pc, #104] ; (8004a00 ) + 8004998: 68db ldr r3, [r3, #12] + 800499a: f423 52f8 bic.w r2, r3, #7936 ; 0x1f00 + 800499e: 687b ldr r3, [r7, #4] + 80049a0: 6a59 ldr r1, [r3, #36] ; 0x24 + 80049a2: 687b ldr r3, [r7, #4] + 80049a4: 6a9b ldr r3, [r3, #40] ; 0x28 + 80049a6: 430b orrs r3, r1 + 80049a8: 4915 ldr r1, [pc, #84] ; (8004a00 ) + 80049aa: 4313 orrs r3, r2 + 80049ac: 60cb str r3, [r1, #12] + + /* Exit Initialization mode */ + status = RTC_ExitInitMode(hrtc); + 80049ae: 6878 ldr r0, [r7, #4] + 80049b0: f000 f9ea bl 8004d88 + 80049b4: 4603 mov r3, r0 + 80049b6: 73fb strb r3, [r7, #15] + if (status == HAL_OK) + 80049b8: 7bfb ldrb r3, [r7, #15] + 80049ba: 2b00 cmp r3, #0 + 80049bc: d10e bne.n 80049dc + { + MODIFY_REG(RTC->CR, \ + 80049be: 4b10 ldr r3, [pc, #64] ; (8004a00 ) + 80049c0: 699b ldr r3, [r3, #24] + 80049c2: f023 4260 bic.w r2, r3, #3758096384 ; 0xe0000000 + 80049c6: 687b ldr r3, [r7, #4] + 80049c8: 6a19 ldr r1, [r3, #32] + 80049ca: 687b ldr r3, [r7, #4] + 80049cc: 69db ldr r3, [r3, #28] + 80049ce: 4319 orrs r1, r3 + 80049d0: 687b ldr r3, [r7, #4] + 80049d2: 695b ldr r3, [r3, #20] + 80049d4: 430b orrs r3, r1 + 80049d6: 490a ldr r1, [pc, #40] ; (8004a00 ) + 80049d8: 4313 orrs r3, r2 + 80049da: 618b str r3, [r1, #24] + hrtc->Init.OutPutPullUp | hrtc->Init.OutPutType | hrtc->Init.OutPutRemap); + } + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 80049dc: 4b08 ldr r3, [pc, #32] ; (8004a00 ) + 80049de: 22ff movs r2, #255 ; 0xff + 80049e0: 625a str r2, [r3, #36] ; 0x24 + 80049e2: e001 b.n 80049e8 + } + else + { + /* Calendar is already initialized */ + /* Set flag to OK */ + status = HAL_OK; + 80049e4: 2300 movs r3, #0 + 80049e6: 73fb strb r3, [r7, #15] + } + + if (status == HAL_OK) + 80049e8: 7bfb ldrb r3, [r7, #15] + 80049ea: 2b00 cmp r3, #0 + 80049ec: d103 bne.n 80049f6 + { + hrtc->State = HAL_RTC_STATE_READY; + 80049ee: 687b ldr r3, [r7, #4] + 80049f0: 2201 movs r2, #1 + 80049f2: f883 202d strb.w r2, [r3, #45] ; 0x2d + } + } + + return status; + 80049f6: 7bfb ldrb r3, [r7, #15] +} + 80049f8: 4618 mov r0, r3 + 80049fa: 3710 adds r7, #16 + 80049fc: 46bd mov sp, r7 + 80049fe: bd80 pop {r7, pc} + 8004a00: 40002800 .word 0x40002800 + +08004a04 : + * @arg RTC_FORMAT_BIN: Binary format + * @arg RTC_FORMAT_BCD: BCD format + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format) +{ + 8004a04: b590 push {r4, r7, lr} + 8004a06: b087 sub sp, #28 + 8004a08: af00 add r7, sp, #0 + 8004a0a: 60f8 str r0, [r7, #12] + 8004a0c: 60b9 str r1, [r7, #8] + 8004a0e: 607a str r2, [r7, #4] + uint32_t tmpreg = 0; + 8004a10: 2300 movs r3, #0 + 8004a12: 617b str r3, [r7, #20] + uint32_t binaryMode; + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004a14: 68fb ldr r3, [r7, #12] + 8004a16: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8004a1a: 2b01 cmp r3, #1 + 8004a1c: d101 bne.n 8004a22 + 8004a1e: 2302 movs r3, #2 + 8004a20: e0f3 b.n 8004c0a + 8004a22: 68fb ldr r3, [r7, #12] + 8004a24: 2201 movs r2, #1 + 8004a26: f883 202c strb.w r2, [r3, #44] ; 0x2c + hrtc->State = HAL_RTC_STATE_BUSY; + 8004a2a: 68fb ldr r3, [r7, #12] + 8004a2c: 2202 movs r2, #2 + 8004a2e: f883 202d strb.w r2, [r3, #45] ; 0x2d + assert_param((sAlarm->AlarmSubSecondMask >> RTC_ALRMASSR_MASKSS_Pos) <= (8U + (READ_BIT(RTC->ICSR, RTC_ICSR_BCDU) >> RTC_ICSR_BCDU_Pos))); + } +#endif + + /* Get Binary mode (32-bit free-running counter configuration) */ + binaryMode = READ_BIT(RTC->ICSR, RTC_ICSR_BIN); + 8004a32: 4b78 ldr r3, [pc, #480] ; (8004c14 ) + 8004a34: 68db ldr r3, [r3, #12] + 8004a36: f403 7340 and.w r3, r3, #768 ; 0x300 + 8004a3a: 613b str r3, [r7, #16] + + if (binaryMode != RTC_BINARY_ONLY) + 8004a3c: 693b ldr r3, [r7, #16] + 8004a3e: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004a42: d06a beq.n 8004b1a + { + if (Format == RTC_FORMAT_BIN) + 8004a44: 687b ldr r3, [r7, #4] + 8004a46: 2b00 cmp r3, #0 + 8004a48: d13a bne.n 8004ac0 + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + 8004a4a: 4b72 ldr r3, [pc, #456] ; (8004c14 ) + 8004a4c: 699b ldr r3, [r3, #24] + 8004a4e: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004a52: 2b00 cmp r3, #0 + 8004a54: d102 bne.n 8004a5c + assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours)); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 8004a56: 68bb ldr r3, [r7, #8] + 8004a58: 2200 movs r2, #0 + 8004a5a: 70da strb r2, [r3, #3] + assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours)); + } + assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes)); + assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds)); + + if( sAlarm->AlarmMask != RTC_ALARMMASK_DATEWEEKDAY ) + 8004a5c: 68bb ldr r3, [r7, #8] + 8004a5e: 695b ldr r3, [r3, #20] + 8004a60: f1b3 4f00 cmp.w r3, #2147483648 ; 0x80000000 + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay)); + } + } + + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004a64: 68bb ldr r3, [r7, #8] + 8004a66: 781b ldrb r3, [r3, #0] + 8004a68: 4618 mov r0, r3 + 8004a6a: f000 f9cb bl 8004e04 + 8004a6e: 4603 mov r3, r0 + 8004a70: 041c lsls r4, r3, #16 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004a72: 68bb ldr r3, [r7, #8] + 8004a74: 785b ldrb r3, [r3, #1] + 8004a76: 4618 mov r0, r3 + 8004a78: f000 f9c4 bl 8004e04 + 8004a7c: 4603 mov r3, r0 + 8004a7e: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004a80: 431c orrs r4, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 8004a82: 68bb ldr r3, [r7, #8] + 8004a84: 789b ldrb r3, [r3, #2] + 8004a86: 4618 mov r0, r3 + 8004a88: f000 f9bc bl 8004e04 + 8004a8c: 4603 mov r3, r0 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004a8e: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004a92: 68bb ldr r3, [r7, #8] + 8004a94: 78db ldrb r3, [r3, #3] + 8004a96: 059b lsls r3, r3, #22 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 8004a98: ea42 0403 orr.w r4, r2, r3 + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 8004a9c: 68bb ldr r3, [r7, #8] + 8004a9e: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8004aa2: 4618 mov r0, r3 + 8004aa4: f000 f9ae bl 8004e04 + 8004aa8: 4603 mov r3, r0 + 8004aaa: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004aac: ea44 0203 orr.w r2, r4, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 8004ab0: 68bb ldr r3, [r7, #8] + 8004ab2: 6a1b ldr r3, [r3, #32] + ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 8004ab4: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 8004ab6: 68bb ldr r3, [r7, #8] + 8004ab8: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004aba: 4313 orrs r3, r2 + 8004abc: 617b str r3, [r7, #20] + 8004abe: e02c b.n 8004b1a + } + else /* Format BCD */ + { + if( sAlarm->AlarmMask != RTC_ALARMMASK_ALL ) + 8004ac0: 68bb ldr r3, [r7, #8] + 8004ac2: 695b ldr r3, [r3, #20] + 8004ac4: f1b3 3f80 cmp.w r3, #2155905152 ; 0x80808080 + 8004ac8: d00d beq.n 8004ae6 + { + if( sAlarm->AlarmMask != RTC_ALARMMASK_HOURS ) + 8004aca: 68bb ldr r3, [r7, #8] + 8004acc: 695b ldr r3, [r3, #20] + 8004ace: f5b3 0f00 cmp.w r3, #8388608 ; 0x800000 + 8004ad2: d008 beq.n 8004ae6 + { + if (READ_BIT(RTC->CR, RTC_CR_FMT) != 0U) + 8004ad4: 4b4f ldr r3, [pc, #316] ; (8004c14 ) + 8004ad6: 699b ldr r3, [r3, #24] + 8004ad8: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004adc: 2b00 cmp r3, #0 + 8004ade: d102 bne.n 8004ae6 + assert_param(IS_RTC_HOUR12(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours))); + assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat)); + } + else + { + sAlarm->AlarmTime.TimeFormat = 0x00U; + 8004ae0: 68bb ldr r3, [r7, #8] + 8004ae2: 2200 movs r2, #0 + 8004ae4: 70da strb r2, [r3, #3] + { + assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay))); + } + } +#endif /* USE_FULL_ASSERT */ + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004ae6: 68bb ldr r3, [r7, #8] + 8004ae8: 781b ldrb r3, [r3, #0] + 8004aea: 041a lsls r2, r3, #16 + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004aec: 68bb ldr r3, [r7, #8] + 8004aee: 785b ldrb r3, [r3, #1] + 8004af0: 021b lsls r3, r3, #8 + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004af2: 4313 orrs r3, r2 + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 8004af4: 68ba ldr r2, [r7, #8] + 8004af6: 7892 ldrb r2, [r2, #2] + ((uint32_t)(sAlarm->AlarmTime.Minutes) << RTC_ALRMAR_MNU_Pos) | \ + 8004af8: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004afa: 68bb ldr r3, [r7, #8] + 8004afc: 78db ldrb r3, [r3, #3] + 8004afe: 059b lsls r3, r3, #22 + ((uint32_t)(sAlarm->AlarmTime.Seconds) << RTC_ALRMAR_SU_Pos) | \ + 8004b00: 431a orrs r2, r3 + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 8004b02: 68bb ldr r3, [r7, #8] + 8004b04: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 8004b08: 061b lsls r3, r3, #24 + ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << RTC_ALRMAR_PM_Pos) | \ + 8004b0a: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \ + 8004b0c: 68bb ldr r3, [r7, #8] + 8004b0e: 6a1b ldr r3, [r3, #32] + ((uint32_t)(sAlarm->AlarmDateWeekDay) << RTC_ALRMAR_DU_Pos) | \ + 8004b10: 431a orrs r2, r3 + ((uint32_t)sAlarm->AlarmMask)); + 8004b12: 68bb ldr r3, [r7, #8] + 8004b14: 695b ldr r3, [r3, #20] + tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << RTC_ALRMAR_HU_Pos) | \ + 8004b16: 4313 orrs r3, r2 + 8004b18: 617b str r3, [r7, #20] + + } + } + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004b1a: 4b3e ldr r3, [pc, #248] ; (8004c14 ) + 8004b1c: 22ca movs r2, #202 ; 0xca + 8004b1e: 625a str r2, [r3, #36] ; 0x24 + 8004b20: 4b3c ldr r3, [pc, #240] ; (8004c14 ) + 8004b22: 2253 movs r2, #83 ; 0x53 + 8004b24: 625a str r2, [r3, #36] ; 0x24 + + /* Configure the Alarm register */ + if (sAlarm->Alarm == RTC_ALARM_A) + 8004b26: 68bb ldr r3, [r7, #8] + 8004b28: 6a9b ldr r3, [r3, #40] ; 0x28 + 8004b2a: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004b2e: d12c bne.n 8004b8a + { + /* Disable the Alarm A interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 8004b30: 4b38 ldr r3, [pc, #224] ; (8004c14 ) + 8004b32: 699b ldr r3, [r3, #24] + 8004b34: 4a37 ldr r2, [pc, #220] ; (8004c14 ) + 8004b36: f423 5388 bic.w r3, r3, #4352 ; 0x1100 + 8004b3a: 6193 str r3, [r2, #24] + /* Clear flag alarm A */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 8004b3c: 4b35 ldr r3, [pc, #212] ; (8004c14 ) + 8004b3e: 2201 movs r2, #1 + 8004b40: 65da str r2, [r3, #92] ; 0x5c + + if (binaryMode == RTC_BINARY_ONLY) + 8004b42: 693b ldr r3, [r7, #16] + 8004b44: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004b48: d107 bne.n 8004b5a + { + RTC->ALRMASSR = sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr; + 8004b4a: 68bb ldr r3, [r7, #8] + 8004b4c: 699a ldr r2, [r3, #24] + 8004b4e: 68bb ldr r3, [r7, #8] + 8004b50: 69db ldr r3, [r3, #28] + 8004b52: 4930 ldr r1, [pc, #192] ; (8004c14 ) + 8004b54: 4313 orrs r3, r2 + 8004b56: 644b str r3, [r1, #68] ; 0x44 + 8004b58: e006 b.n 8004b68 + } + else + { + WRITE_REG(RTC->ALRMAR, tmpreg); + 8004b5a: 4a2e ldr r2, [pc, #184] ; (8004c14 ) + 8004b5c: 697b ldr r3, [r7, #20] + 8004b5e: 6413 str r3, [r2, #64] ; 0x40 + WRITE_REG(RTC->ALRMASSR, sAlarm->AlarmSubSecondMask); + 8004b60: 4a2c ldr r2, [pc, #176] ; (8004c14 ) + 8004b62: 68bb ldr r3, [r7, #8] + 8004b64: 699b ldr r3, [r3, #24] + 8004b66: 6453 str r3, [r2, #68] ; 0x44 + } + + WRITE_REG(RTC->ALRABINR, sAlarm->AlarmTime.SubSeconds); + 8004b68: 4a2a ldr r2, [pc, #168] ; (8004c14 ) + 8004b6a: 68bb ldr r3, [r7, #8] + 8004b6c: 685b ldr r3, [r3, #4] + 8004b6e: 6713 str r3, [r2, #112] ; 0x70 + + /* Store in the handle the Alarm A enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + 8004b70: 68fb ldr r3, [r7, #12] + 8004b72: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004b74: f043 0201 orr.w r2, r3, #1 + 8004b78: 68fb ldr r3, [r7, #12] + 8004b7a: 631a str r2, [r3, #48] ; 0x30 + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 8004b7c: 4b25 ldr r3, [pc, #148] ; (8004c14 ) + 8004b7e: 699b ldr r3, [r3, #24] + 8004b80: 4a24 ldr r2, [pc, #144] ; (8004c14 ) + 8004b82: f443 5388 orr.w r3, r3, #4352 ; 0x1100 + 8004b86: 6193 str r3, [r2, #24] + 8004b88: e02b b.n 8004be2 + } + else + { + /* Disable the Alarm B interrupt */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 8004b8a: 4b22 ldr r3, [pc, #136] ; (8004c14 ) + 8004b8c: 699b ldr r3, [r3, #24] + 8004b8e: 4a21 ldr r2, [pc, #132] ; (8004c14 ) + 8004b90: f423 5308 bic.w r3, r3, #8704 ; 0x2200 + 8004b94: 6193 str r3, [r2, #24] + /* Clear flag alarm B */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 8004b96: 4b1f ldr r3, [pc, #124] ; (8004c14 ) + 8004b98: 2202 movs r2, #2 + 8004b9a: 65da str r2, [r3, #92] ; 0x5c + + if (binaryMode == RTC_BINARY_ONLY) + 8004b9c: 693b ldr r3, [r7, #16] + 8004b9e: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004ba2: d107 bne.n 8004bb4 + { + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask | sAlarm->BinaryAutoClr); + 8004ba4: 68bb ldr r3, [r7, #8] + 8004ba6: 699a ldr r2, [r3, #24] + 8004ba8: 68bb ldr r3, [r7, #8] + 8004baa: 69db ldr r3, [r3, #28] + 8004bac: 4919 ldr r1, [pc, #100] ; (8004c14 ) + 8004bae: 4313 orrs r3, r2 + 8004bb0: 64cb str r3, [r1, #76] ; 0x4c + 8004bb2: e006 b.n 8004bc2 + } + else + { + WRITE_REG(RTC->ALRMBR, tmpreg); + 8004bb4: 4a17 ldr r2, [pc, #92] ; (8004c14 ) + 8004bb6: 697b ldr r3, [r7, #20] + 8004bb8: 6493 str r3, [r2, #72] ; 0x48 + WRITE_REG(RTC->ALRMBSSR, sAlarm->AlarmSubSecondMask); + 8004bba: 4a16 ldr r2, [pc, #88] ; (8004c14 ) + 8004bbc: 68bb ldr r3, [r7, #8] + 8004bbe: 699b ldr r3, [r3, #24] + 8004bc0: 64d3 str r3, [r2, #76] ; 0x4c + } + + WRITE_REG(RTC->ALRBBINR, sAlarm->AlarmTime.SubSeconds); + 8004bc2: 4a14 ldr r2, [pc, #80] ; (8004c14 ) + 8004bc4: 68bb ldr r3, [r7, #8] + 8004bc6: 685b ldr r3, [r3, #4] + 8004bc8: 6753 str r3, [r2, #116] ; 0x74 + + /* Store in the handle the Alarm B enabled */ + SET_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + 8004bca: 68fb ldr r3, [r7, #12] + 8004bcc: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004bce: f043 0202 orr.w r2, r3, #2 + 8004bd2: 68fb ldr r3, [r7, #12] + 8004bd4: 631a str r2, [r3, #48] ; 0x30 + + /* Configure the Alarm interrupt */ + SET_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 8004bd6: 4b0f ldr r3, [pc, #60] ; (8004c14 ) + 8004bd8: 699b ldr r3, [r3, #24] + 8004bda: 4a0e ldr r2, [pc, #56] ; (8004c14 ) + 8004bdc: f443 5308 orr.w r3, r3, #8704 ; 0x2200 + 8004be0: 6193 str r3, [r2, #24] + } + + /* RTC Alarm Interrupt Configuration: EXTI configuration */ + __HAL_RTC_ALARM_EXTI_ENABLE_IT(); + 8004be2: 4b0d ldr r3, [pc, #52] ; (8004c18 ) + 8004be4: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8004be8: 4a0b ldr r2, [pc, #44] ; (8004c18 ) + 8004bea: f443 3300 orr.w r3, r3, #131072 ; 0x20000 + 8004bee: f8c2 3080 str.w r3, [r2, #128] ; 0x80 + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004bf2: 4b08 ldr r3, [pc, #32] ; (8004c14 ) + 8004bf4: 22ff movs r2, #255 ; 0xff + 8004bf6: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004bf8: 68fb ldr r3, [r7, #12] + 8004bfa: 2201 movs r2, #1 + 8004bfc: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004c00: 68fb ldr r3, [r7, #12] + 8004c02: 2200 movs r2, #0 + 8004c04: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8004c08: 2300 movs r3, #0 +} + 8004c0a: 4618 mov r0, r3 + 8004c0c: 371c adds r7, #28 + 8004c0e: 46bd mov sp, r7 + 8004c10: bd90 pop {r4, r7, pc} + 8004c12: bf00 nop + 8004c14: 40002800 .word 0x40002800 + 8004c18: 58000800 .word 0x58000800 + +08004c1c : + * @arg RTC_ALARM_A: AlarmA + * @arg RTC_ALARM_B: AlarmB + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm) +{ + 8004c1c: b480 push {r7} + 8004c1e: b083 sub sp, #12 + 8004c20: af00 add r7, sp, #0 + 8004c22: 6078 str r0, [r7, #4] + 8004c24: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_RTC_ALARM(Alarm)); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004c26: 687b ldr r3, [r7, #4] + 8004c28: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8004c2c: 2b01 cmp r3, #1 + 8004c2e: d101 bne.n 8004c34 + 8004c30: 2302 movs r3, #2 + 8004c32: e048 b.n 8004cc6 + 8004c34: 687b ldr r3, [r7, #4] + 8004c36: 2201 movs r2, #1 + 8004c38: f883 202c strb.w r2, [r3, #44] ; 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 8004c3c: 687b ldr r3, [r7, #4] + 8004c3e: 2202 movs r2, #2 + 8004c40: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004c44: 4b22 ldr r3, [pc, #136] ; (8004cd0 ) + 8004c46: 22ca movs r2, #202 ; 0xca + 8004c48: 625a str r2, [r3, #36] ; 0x24 + 8004c4a: 4b21 ldr r3, [pc, #132] ; (8004cd0 ) + 8004c4c: 2253 movs r2, #83 ; 0x53 + 8004c4e: 625a str r2, [r3, #36] ; 0x24 + + if (Alarm == RTC_ALARM_A) + 8004c50: 683b ldr r3, [r7, #0] + 8004c52: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8004c56: d115 bne.n 8004c84 + { + /* AlarmA, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRAE | RTC_CR_ALRAIE); + 8004c58: 4b1d ldr r3, [pc, #116] ; (8004cd0 ) + 8004c5a: 699b ldr r3, [r3, #24] + 8004c5c: 4a1c ldr r2, [pc, #112] ; (8004cd0 ) + 8004c5e: f423 5388 bic.w r3, r3, #4352 ; 0x1100 + 8004c62: 6193 str r3, [r2, #24] + + /* AlarmA, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMASSR, RTC_ALRMASSR_SSCLR); + 8004c64: 4b1a ldr r3, [pc, #104] ; (8004cd0 ) + 8004c66: 6c5b ldr r3, [r3, #68] ; 0x44 + 8004c68: 4a19 ldr r2, [pc, #100] ; (8004cd0 ) + 8004c6a: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8004c6e: 6453 str r3, [r2, #68] ; 0x44 + + /* Store in the handle the Alarm A disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRAMF); + 8004c70: 687b ldr r3, [r7, #4] + 8004c72: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004c74: f023 0201 bic.w r2, r3, #1 + 8004c78: 687b ldr r3, [r7, #4] + 8004c7a: 631a str r2, [r3, #48] ; 0x30 + + /* Clear AlarmA flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRAF); + 8004c7c: 4b14 ldr r3, [pc, #80] ; (8004cd0 ) + 8004c7e: 2201 movs r2, #1 + 8004c80: 65da str r2, [r3, #92] ; 0x5c + 8004c82: e014 b.n 8004cae + } + else + { + /* AlarmB, In case of interrupt mode is used, the interrupt source must disabled */ + CLEAR_BIT(RTC->CR, RTC_CR_ALRBE | RTC_CR_ALRBIE); + 8004c84: 4b12 ldr r3, [pc, #72] ; (8004cd0 ) + 8004c86: 699b ldr r3, [r3, #24] + 8004c88: 4a11 ldr r2, [pc, #68] ; (8004cd0 ) + 8004c8a: f423 5308 bic.w r3, r3, #8704 ; 0x2200 + 8004c8e: 6193 str r3, [r2, #24] + + /* AlarmB, Clear SSCLR */ + CLEAR_BIT(RTC->ALRMBSSR, RTC_ALRMBSSR_SSCLR); + 8004c90: 4b0f ldr r3, [pc, #60] ; (8004cd0 ) + 8004c92: 6cdb ldr r3, [r3, #76] ; 0x4c + 8004c94: 4a0e ldr r2, [pc, #56] ; (8004cd0 ) + 8004c96: f023 4300 bic.w r3, r3, #2147483648 ; 0x80000000 + 8004c9a: 64d3 str r3, [r2, #76] ; 0x4c + + /* Store in the handle the Alarm B disabled */ + CLEAR_BIT(hrtc->IsEnabled.RtcFeatures, RTC_MISR_ALRBMF); + 8004c9c: 687b ldr r3, [r7, #4] + 8004c9e: 6b1b ldr r3, [r3, #48] ; 0x30 + 8004ca0: f023 0202 bic.w r2, r3, #2 + 8004ca4: 687b ldr r3, [r7, #4] + 8004ca6: 631a str r2, [r3, #48] ; 0x30 + + /* Clear AlarmB flag */ + WRITE_REG(RTC->SCR, RTC_SCR_CALRBF); + 8004ca8: 4b09 ldr r3, [pc, #36] ; (8004cd0 ) + 8004caa: 2202 movs r2, #2 + 8004cac: 65da str r2, [r3, #92] ; 0x5c + } + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004cae: 4b08 ldr r3, [pc, #32] ; (8004cd0 ) + 8004cb0: 22ff movs r2, #255 ; 0xff + 8004cb2: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004cb4: 687b ldr r3, [r7, #4] + 8004cb6: 2201 movs r2, #1 + 8004cb8: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004cbc: 687b ldr r3, [r7, #4] + 8004cbe: 2200 movs r2, #0 + 8004cc0: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8004cc4: 2300 movs r3, #0 +} + 8004cc6: 4618 mov r0, r3 + 8004cc8: 370c adds r7, #12 + 8004cca: 46bd mov sp, r7 + 8004ccc: bc80 pop {r7} + 8004cce: 4770 bx lr + 8004cd0: 40002800 .word 0x40002800 + +08004cd4 : + * correctly copied into the RTC_TR and RTC_DR shadow registers. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +{ + 8004cd4: b580 push {r7, lr} + 8004cd6: b084 sub sp, #16 + 8004cd8: af00 add r7, sp, #0 + 8004cda: 6078 str r0, [r7, #4] + uint32_t tickstart; + + UNUSED(hrtc); + /* Clear RSF flag */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_RSF); + 8004cdc: 4b0f ldr r3, [pc, #60] ; (8004d1c ) + 8004cde: 68db ldr r3, [r3, #12] + 8004ce0: 4a0e ldr r2, [pc, #56] ; (8004d1c ) + 8004ce2: f023 0320 bic.w r3, r3, #32 + 8004ce6: 60d3 str r3, [r2, #12] + + tickstart = HAL_GetTick(); + 8004ce8: f7fc f818 bl 8000d1c + 8004cec: 60f8 str r0, [r7, #12] + + /* Wait the registers to be synchronised */ + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + 8004cee: e009 b.n 8004d04 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8004cf0: f7fc f814 bl 8000d1c + 8004cf4: 4602 mov r2, r0 + 8004cf6: 68fb ldr r3, [r7, #12] + 8004cf8: 1ad3 subs r3, r2, r3 + 8004cfa: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8004cfe: d901 bls.n 8004d04 + { + return HAL_TIMEOUT; + 8004d00: 2303 movs r3, #3 + 8004d02: e006 b.n 8004d12 + while (READ_BIT(RTC->ICSR, RTC_ICSR_RSF) == 0U) + 8004d04: 4b05 ldr r3, [pc, #20] ; (8004d1c ) + 8004d06: 68db ldr r3, [r3, #12] + 8004d08: f003 0320 and.w r3, r3, #32 + 8004d0c: 2b00 cmp r3, #0 + 8004d0e: d0ef beq.n 8004cf0 + } + } + + return HAL_OK; + 8004d10: 2300 movs r3, #0 +} + 8004d12: 4618 mov r0, r3 + 8004d14: 3710 adds r7, #16 + 8004d16: 46bd mov sp, r7 + 8004d18: bd80 pop {r7, pc} + 8004d1a: bf00 nop + 8004d1c: 40002800 .word 0x40002800 + +08004d20 : + * __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef *hrtc) +{ + 8004d20: b580 push {r7, lr} + 8004d22: b084 sub sp, #16 + 8004d24: af00 add r7, sp, #0 + 8004d26: 6078 str r0, [r7, #4] + uint32_t tickstart; + HAL_StatusTypeDef status = HAL_OK; + 8004d28: 2300 movs r3, #0 + 8004d2a: 73fb strb r3, [r7, #15] + + UNUSED(hrtc); + /* Check if the Initialization mode is set */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + 8004d2c: 4b15 ldr r3, [pc, #84] ; (8004d84 ) + 8004d2e: 68db ldr r3, [r3, #12] + 8004d30: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004d34: 2b00 cmp r3, #0 + 8004d36: d120 bne.n 8004d7a + { + /* Set the Initialization mode */ + SET_BIT(RTC->ICSR, RTC_ICSR_INIT); + 8004d38: 4b12 ldr r3, [pc, #72] ; (8004d84 ) + 8004d3a: 68db ldr r3, [r3, #12] + 8004d3c: 4a11 ldr r2, [pc, #68] ; (8004d84 ) + 8004d3e: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8004d42: 60d3 str r3, [r2, #12] + + tickstart = HAL_GetTick(); + 8004d44: f7fb ffea bl 8000d1c + 8004d48: 60b8 str r0, [r7, #8] + /* Wait till RTC is in INIT state and if Time out is reached exit */ + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + 8004d4a: e00d b.n 8004d68 + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8004d4c: f7fb ffe6 bl 8000d1c + 8004d50: 4602 mov r2, r0 + 8004d52: 68bb ldr r3, [r7, #8] + 8004d54: 1ad3 subs r3, r2, r3 + 8004d56: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8004d5a: d905 bls.n 8004d68 + { + status = HAL_TIMEOUT; + 8004d5c: 2303 movs r3, #3 + 8004d5e: 73fb strb r3, [r7, #15] + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8004d60: 687b ldr r3, [r7, #4] + 8004d62: 2203 movs r2, #3 + 8004d64: f883 202d strb.w r2, [r3, #45] ; 0x2d + while ((READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) && (status != HAL_TIMEOUT)) + 8004d68: 4b06 ldr r3, [pc, #24] ; (8004d84 ) + 8004d6a: 68db ldr r3, [r3, #12] + 8004d6c: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004d70: 2b00 cmp r3, #0 + 8004d72: d102 bne.n 8004d7a + 8004d74: 7bfb ldrb r3, [r7, #15] + 8004d76: 2b03 cmp r3, #3 + 8004d78: d1e8 bne.n 8004d4c + } + } + } + + return status; + 8004d7a: 7bfb ldrb r3, [r7, #15] +} + 8004d7c: 4618 mov r0, r3 + 8004d7e: 3710 adds r7, #16 + 8004d80: 46bd mov sp, r7 + 8004d82: bd80 pop {r7, pc} + 8004d84: 40002800 .word 0x40002800 + +08004d88 : + * @brief Exit the RTC Initialization mode. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef RTC_ExitInitMode(RTC_HandleTypeDef *hrtc) +{ + 8004d88: b580 push {r7, lr} + 8004d8a: b084 sub sp, #16 + 8004d8c: af00 add r7, sp, #0 + 8004d8e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status = HAL_OK; + 8004d90: 2300 movs r3, #0 + 8004d92: 73fb strb r3, [r7, #15] + + /* Exit Initialization mode */ + CLEAR_BIT(RTC->ICSR, RTC_ICSR_INIT); + 8004d94: 4b1a ldr r3, [pc, #104] ; (8004e00 ) + 8004d96: 68db ldr r3, [r3, #12] + 8004d98: 4a19 ldr r2, [pc, #100] ; (8004e00 ) + 8004d9a: f023 0380 bic.w r3, r3, #128 ; 0x80 + 8004d9e: 60d3 str r3, [r2, #12] + + /* If CR_BYPSHAD bit = 0, wait for synchro */ + if (READ_BIT(RTC->CR, RTC_CR_BYPSHAD) == 0U) + 8004da0: 4b17 ldr r3, [pc, #92] ; (8004e00 ) + 8004da2: 699b ldr r3, [r3, #24] + 8004da4: f003 0320 and.w r3, r3, #32 + 8004da8: 2b00 cmp r3, #0 + 8004daa: d10c bne.n 8004dc6 + { + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8004dac: 6878 ldr r0, [r7, #4] + 8004dae: f7ff ff91 bl 8004cd4 + 8004db2: 4603 mov r3, r0 + 8004db4: 2b00 cmp r3, #0 + 8004db6: d01e beq.n 8004df6 + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8004db8: 687b ldr r3, [r7, #4] + 8004dba: 2203 movs r2, #3 + 8004dbc: f883 202d strb.w r2, [r3, #45] ; 0x2d + status = HAL_TIMEOUT; + 8004dc0: 2303 movs r3, #3 + 8004dc2: 73fb strb r3, [r7, #15] + 8004dc4: e017 b.n 8004df6 + } + } + else /* WA 2.9.6 Calendar initialization may fail in case of consecutive INIT mode entry. */ + { + /* Clear BYPSHAD bit */ + CLEAR_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004dc6: 4b0e ldr r3, [pc, #56] ; (8004e00 ) + 8004dc8: 699b ldr r3, [r3, #24] + 8004dca: 4a0d ldr r2, [pc, #52] ; (8004e00 ) + 8004dcc: f023 0320 bic.w r3, r3, #32 + 8004dd0: 6193 str r3, [r2, #24] + if (HAL_RTC_WaitForSynchro(hrtc) != HAL_OK) + 8004dd2: 6878 ldr r0, [r7, #4] + 8004dd4: f7ff ff7e bl 8004cd4 + 8004dd8: 4603 mov r3, r0 + 8004dda: 2b00 cmp r3, #0 + 8004ddc: d005 beq.n 8004dea + { + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8004dde: 687b ldr r3, [r7, #4] + 8004de0: 2203 movs r2, #3 + 8004de2: f883 202d strb.w r2, [r3, #45] ; 0x2d + status = HAL_TIMEOUT; + 8004de6: 2303 movs r3, #3 + 8004de8: 73fb strb r3, [r7, #15] + } + /* Restore BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004dea: 4b05 ldr r3, [pc, #20] ; (8004e00 ) + 8004dec: 699b ldr r3, [r3, #24] + 8004dee: 4a04 ldr r2, [pc, #16] ; (8004e00 ) + 8004df0: f043 0320 orr.w r3, r3, #32 + 8004df4: 6193 str r3, [r2, #24] + } + + return status; + 8004df6: 7bfb ldrb r3, [r7, #15] +} + 8004df8: 4618 mov r0, r3 + 8004dfa: 3710 adds r7, #16 + 8004dfc: 46bd mov sp, r7 + 8004dfe: bd80 pop {r7, pc} + 8004e00: 40002800 .word 0x40002800 + +08004e04 : + * @brief Convert a 2 digit decimal to BCD format. + * @param Value Byte to be converted + * @retval Converted byte + */ +uint8_t RTC_ByteToBcd2(uint8_t Value) +{ + 8004e04: b480 push {r7} + 8004e06: b085 sub sp, #20 + 8004e08: af00 add r7, sp, #0 + 8004e0a: 4603 mov r3, r0 + 8004e0c: 71fb strb r3, [r7, #7] + uint32_t bcdhigh = 0U; + 8004e0e: 2300 movs r3, #0 + 8004e10: 60fb str r3, [r7, #12] + uint8_t tmp_Value = Value; + 8004e12: 79fb ldrb r3, [r7, #7] + 8004e14: 72fb strb r3, [r7, #11] + + while (tmp_Value >= 10U) + 8004e16: e005 b.n 8004e24 + { + bcdhigh++; + 8004e18: 68fb ldr r3, [r7, #12] + 8004e1a: 3301 adds r3, #1 + 8004e1c: 60fb str r3, [r7, #12] + tmp_Value -= 10U; + 8004e1e: 7afb ldrb r3, [r7, #11] + 8004e20: 3b0a subs r3, #10 + 8004e22: 72fb strb r3, [r7, #11] + while (tmp_Value >= 10U) + 8004e24: 7afb ldrb r3, [r7, #11] + 8004e26: 2b09 cmp r3, #9 + 8004e28: d8f6 bhi.n 8004e18 + } + + return ((uint8_t)(bcdhigh << 4U) | tmp_Value); + 8004e2a: 68fb ldr r3, [r7, #12] + 8004e2c: b2db uxtb r3, r3 + 8004e2e: 011b lsls r3, r3, #4 + 8004e30: b2da uxtb r2, r3 + 8004e32: 7afb ldrb r3, [r7, #11] + 8004e34: 4313 orrs r3, r2 + 8004e36: b2db uxtb r3, r3 +} + 8004e38: 4618 mov r0, r3 + 8004e3a: 3714 adds r7, #20 + 8004e3c: 46bd mov sp, r7 + 8004e3e: bc80 pop {r7} + 8004e40: 4770 bx lr + ... + +08004e44 : + * - This feature is meaningful in case of Low power mode to avoid any RTC software execution after Wake Up. + * That is why when WakeUpAutoClr is set, EXTI is configured as EVENT instead of Interrupt to avoid useless IRQ handler execution. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr) +{ + 8004e44: b580 push {r7, lr} + 8004e46: b086 sub sp, #24 + 8004e48: af00 add r7, sp, #0 + 8004e4a: 60f8 str r0, [r7, #12] + 8004e4c: 60b9 str r1, [r7, #8] + 8004e4e: 607a str r2, [r7, #4] + 8004e50: 603b str r3, [r7, #0] + assert_param(IS_RTC_WAKEUP_COUNTER(WakeUpCounter)); + /* (0x0000<=WUTOCLR<=WUT) */ + assert_param(WakeUpAutoClr <= WakeUpCounter); + + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004e52: 68fb ldr r3, [r7, #12] + 8004e54: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8004e58: 2b01 cmp r3, #1 + 8004e5a: d101 bne.n 8004e60 + 8004e5c: 2302 movs r3, #2 + 8004e5e: e06f b.n 8004f40 + 8004e60: 68fb ldr r3, [r7, #12] + 8004e62: 2201 movs r2, #1 + 8004e64: f883 202c strb.w r2, [r3, #44] ; 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 8004e68: 68fb ldr r3, [r7, #12] + 8004e6a: 2202 movs r2, #2 + 8004e6c: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004e70: 4b35 ldr r3, [pc, #212] ; (8004f48 ) + 8004e72: 22ca movs r2, #202 ; 0xca + 8004e74: 625a str r2, [r3, #36] ; 0x24 + 8004e76: 4b34 ldr r3, [pc, #208] ; (8004f48 ) + 8004e78: 2253 movs r2, #83 ; 0x53 + 8004e7a: 625a str r2, [r3, #36] ; 0x24 + + /* Clear WUTE in RTC_CR to disable the wakeup timer */ + CLEAR_BIT(RTC->CR, RTC_CR_WUTE); + 8004e7c: 4b32 ldr r3, [pc, #200] ; (8004f48 ) + 8004e7e: 699b ldr r3, [r3, #24] + 8004e80: 4a31 ldr r2, [pc, #196] ; (8004f48 ) + 8004e82: f423 6380 bic.w r3, r3, #1024 ; 0x400 + 8004e86: 6193 str r3, [r2, #24] + + /* Clear flag Wake-Up */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + 8004e88: 4b2f ldr r3, [pc, #188] ; (8004f48 ) + 8004e8a: 2204 movs r2, #4 + 8004e8c: 65da str r2, [r3, #92] ; 0x5c + + /* Poll WUTWF until it is set in RTC_ICSR to make sure the access to wakeup autoreload + counter and to WUCKSEL[2:0] bits is allowed. This step must be skipped in + calendar initialization mode. */ + if (READ_BIT(RTC->ICSR, RTC_ICSR_INITF) == 0U) + 8004e8e: 4b2e ldr r3, [pc, #184] ; (8004f48 ) + 8004e90: 68db ldr r3, [r3, #12] + 8004e92: f003 0340 and.w r3, r3, #64 ; 0x40 + 8004e96: 2b00 cmp r3, #0 + 8004e98: d11e bne.n 8004ed8 + { + tickstart = HAL_GetTick(); + 8004e9a: f7fb ff3f bl 8000d1c + 8004e9e: 6178 str r0, [r7, #20] + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + 8004ea0: e014 b.n 8004ecc + { + if ((HAL_GetTick() - tickstart) > RTC_TIMEOUT_VALUE) + 8004ea2: f7fb ff3b bl 8000d1c + 8004ea6: 4602 mov r2, r0 + 8004ea8: 697b ldr r3, [r7, #20] + 8004eaa: 1ad3 subs r3, r2, r3 + 8004eac: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 8004eb0: d90c bls.n 8004ecc + { + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004eb2: 4b25 ldr r3, [pc, #148] ; (8004f48 ) + 8004eb4: 22ff movs r2, #255 ; 0xff + 8004eb6: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_TIMEOUT; + 8004eb8: 68fb ldr r3, [r7, #12] + 8004eba: 2203 movs r2, #3 + 8004ebc: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004ec0: 68fb ldr r3, [r7, #12] + 8004ec2: 2200 movs r2, #0 + 8004ec4: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_TIMEOUT; + 8004ec8: 2303 movs r3, #3 + 8004eca: e039 b.n 8004f40 + while (READ_BIT(RTC->ICSR, RTC_ICSR_WUTWF) == 0U) + 8004ecc: 4b1e ldr r3, [pc, #120] ; (8004f48 ) + 8004ece: 68db ldr r3, [r3, #12] + 8004ed0: f003 0304 and.w r3, r3, #4 + 8004ed4: 2b00 cmp r3, #0 + 8004ed6: d0e4 beq.n 8004ea2 + } + } + } + + /* Configure the Wakeup Timer counter and auto clear value */ + WRITE_REG(RTC->WUTR, (uint32_t)(WakeUpCounter | (WakeUpAutoClr << RTC_WUTR_WUTOCLR_Pos))); + 8004ed8: 683b ldr r3, [r7, #0] + 8004eda: 041a lsls r2, r3, #16 + 8004edc: 491a ldr r1, [pc, #104] ; (8004f48 ) + 8004ede: 68bb ldr r3, [r7, #8] + 8004ee0: 4313 orrs r3, r2 + 8004ee2: 614b str r3, [r1, #20] + + /* Configure the clock source */ + MODIFY_REG(RTC->CR, RTC_CR_WUCKSEL, (uint32_t)WakeUpClock); + 8004ee4: 4b18 ldr r3, [pc, #96] ; (8004f48 ) + 8004ee6: 699b ldr r3, [r3, #24] + 8004ee8: f023 0207 bic.w r2, r3, #7 + 8004eec: 4916 ldr r1, [pc, #88] ; (8004f48 ) + 8004eee: 687b ldr r3, [r7, #4] + 8004ef0: 4313 orrs r3, r2 + 8004ef2: 618b str r3, [r1, #24] + + /* In case of WUT autoclr, the IRQ handler should not be called */ + if (WakeUpAutoClr != 0U) + 8004ef4: 683b ldr r3, [r7, #0] + 8004ef6: 2b00 cmp r3, #0 + 8004ef8: d008 beq.n 8004f0c + { + /* RTC WakeUpTimer EXTI Configuration: Event configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT(); + 8004efa: 4b14 ldr r3, [pc, #80] ; (8004f4c ) + 8004efc: f8d3 3084 ldr.w r3, [r3, #132] ; 0x84 + 8004f00: 4a12 ldr r2, [pc, #72] ; (8004f4c ) + 8004f02: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8004f06: f8c2 3084 str.w r3, [r2, #132] ; 0x84 + 8004f0a: e007 b.n 8004f1c + } + else + { + /* RTC WakeUpTimer EXTI Configuration: Interrupt configuration */ + __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_IT(); + 8004f0c: 4b0f ldr r3, [pc, #60] ; (8004f4c ) + 8004f0e: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8004f12: 4a0e ldr r2, [pc, #56] ; (8004f4c ) + 8004f14: f443 1380 orr.w r3, r3, #1048576 ; 0x100000 + 8004f18: f8c2 3080 str.w r3, [r2, #128] ; 0x80 + } + + /* Configure the Interrupt in the RTC_CR register and Enable the Wakeup Timer*/ + SET_BIT(RTC->CR, (RTC_CR_WUTIE | RTC_CR_WUTE)); + 8004f1c: 4b0a ldr r3, [pc, #40] ; (8004f48 ) + 8004f1e: 699b ldr r3, [r3, #24] + 8004f20: 4a09 ldr r2, [pc, #36] ; (8004f48 ) + 8004f22: f443 4388 orr.w r3, r3, #17408 ; 0x4400 + 8004f26: 6193 str r3, [r2, #24] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004f28: 4b07 ldr r3, [pc, #28] ; (8004f48 ) + 8004f2a: 22ff movs r2, #255 ; 0xff + 8004f2c: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8004f2e: 68fb ldr r3, [r7, #12] + 8004f30: 2201 movs r2, #1 + 8004f32: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004f36: 68fb ldr r3, [r7, #12] + 8004f38: 2200 movs r2, #0 + 8004f3a: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8004f3e: 2300 movs r3, #0 +} + 8004f40: 4618 mov r0, r3 + 8004f42: 3718 adds r7, #24 + 8004f44: 46bd mov sp, r7 + 8004f46: bd80 pop {r7, pc} + 8004f48: 40002800 .word 0x40002800 + 8004f4c: 58000800 .word 0x58000800 + +08004f50 : + * @brief Handle Wake Up Timer interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 8004f50: b580 push {r7, lr} + 8004f52: b082 sub sp, #8 + 8004f54: af00 add r7, sp, #0 + 8004f56: 6078 str r0, [r7, #4] + if (READ_BIT(RTC->MISR, RTC_MISR_WUTMF) != 0U) + 8004f58: 4b09 ldr r3, [pc, #36] ; (8004f80 ) + 8004f5a: 6d5b ldr r3, [r3, #84] ; 0x54 + 8004f5c: f003 0304 and.w r3, r3, #4 + 8004f60: 2b00 cmp r3, #0 + 8004f62: d005 beq.n 8004f70 + { + /* Clear the WAKEUPTIMER interrupt pending bit */ + WRITE_REG(RTC->SCR, RTC_SCR_CWUTF); + 8004f64: 4b06 ldr r3, [pc, #24] ; (8004f80 ) + 8004f66: 2204 movs r2, #4 + 8004f68: 65da str r2, [r3, #92] ; 0x5c +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call WakeUpTimerEvent registered Callback */ + hrtc->WakeUpTimerEventCallback(hrtc); +#else + /* WAKEUPTIMER callback */ + HAL_RTCEx_WakeUpTimerEventCallback(hrtc); + 8004f6a: 6878 ldr r0, [r7, #4] + 8004f6c: f000 f80a bl 8004f84 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8004f70: 687b ldr r3, [r7, #4] + 8004f72: 2201 movs r2, #1 + 8004f74: f883 202d strb.w r2, [r3, #45] ; 0x2d +} + 8004f78: bf00 nop + 8004f7a: 3708 adds r7, #8 + 8004f7c: 46bd mov sp, r7 + 8004f7e: bd80 pop {r7, pc} + 8004f80: 40002800 .word 0x40002800 + +08004f84 : + * @brief Wake Up Timer callback. + * @param hrtc RTC handle + * @retval None + */ +__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc) +{ + 8004f84: b480 push {r7} + 8004f86: b083 sub sp, #12 + 8004f88: af00 add r7, sp, #0 + 8004f8a: 6078 str r0, [r7, #4] + UNUSED(hrtc); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file + */ +} + 8004f8c: bf00 nop + 8004f8e: 370c adds r7, #12 + 8004f90: 46bd mov sp, r7 + 8004f92: bc80 pop {r7} + 8004f94: 4770 bx lr + ... + +08004f98 : + * directly from the Calendar counter. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc) +{ + 8004f98: b480 push {r7} + 8004f9a: b083 sub sp, #12 + 8004f9c: af00 add r7, sp, #0 + 8004f9e: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(hrtc); + 8004fa0: 687b ldr r3, [r7, #4] + 8004fa2: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8004fa6: 2b01 cmp r3, #1 + 8004fa8: d101 bne.n 8004fae + 8004faa: 2302 movs r3, #2 + 8004fac: e01f b.n 8004fee + 8004fae: 687b ldr r3, [r7, #4] + 8004fb0: 2201 movs r2, #1 + 8004fb2: f883 202c strb.w r2, [r3, #44] ; 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 8004fb6: 687b ldr r3, [r7, #4] + 8004fb8: 2202 movs r2, #2 + 8004fba: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8004fbe: 4b0e ldr r3, [pc, #56] ; (8004ff8 ) + 8004fc0: 22ca movs r2, #202 ; 0xca + 8004fc2: 625a str r2, [r3, #36] ; 0x24 + 8004fc4: 4b0c ldr r3, [pc, #48] ; (8004ff8 ) + 8004fc6: 2253 movs r2, #83 ; 0x53 + 8004fc8: 625a str r2, [r3, #36] ; 0x24 + + /* Set the BYPSHAD bit */ + SET_BIT(RTC->CR, RTC_CR_BYPSHAD); + 8004fca: 4b0b ldr r3, [pc, #44] ; (8004ff8 ) + 8004fcc: 699b ldr r3, [r3, #24] + 8004fce: 4a0a ldr r2, [pc, #40] ; (8004ff8 ) + 8004fd0: f043 0320 orr.w r3, r3, #32 + 8004fd4: 6193 str r3, [r2, #24] + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 8004fd6: 4b08 ldr r3, [pc, #32] ; (8004ff8 ) + 8004fd8: 22ff movs r2, #255 ; 0xff + 8004fda: 625a str r2, [r3, #36] ; 0x24 + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8004fdc: 687b ldr r3, [r7, #4] + 8004fde: 2201 movs r2, #1 + 8004fe0: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8004fe4: 687b ldr r3, [r7, #4] + 8004fe6: 2200 movs r2, #0 + 8004fe8: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8004fec: 2300 movs r3, #0 +} + 8004fee: 4618 mov r0, r3 + 8004ff0: 370c adds r7, #12 + 8004ff2: 46bd mov sp, r7 + 8004ff4: bc80 pop {r7} + 8004ff6: 4770 bx lr + 8004ff8: 40002800 .word 0x40002800 + +08004ffc : + * @brief Set SSR Underflow detection with Interrupt. + * @param hrtc RTC handle + * @retval HAL status + */ +HAL_StatusTypeDef HAL_RTCEx_SetSSRU_IT(RTC_HandleTypeDef *hrtc) +{ + 8004ffc: b480 push {r7} + 8004ffe: b083 sub sp, #12 + 8005000: af00 add r7, sp, #0 + 8005002: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(hrtc); + 8005004: 687b ldr r3, [r7, #4] + 8005006: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 800500a: 2b01 cmp r3, #1 + 800500c: d101 bne.n 8005012 + 800500e: 2302 movs r3, #2 + 8005010: e027 b.n 8005062 + 8005012: 687b ldr r3, [r7, #4] + 8005014: 2201 movs r2, #1 + 8005016: f883 202c strb.w r2, [r3, #44] ; 0x2c + + hrtc->State = HAL_RTC_STATE_BUSY; + 800501a: 687b ldr r3, [r7, #4] + 800501c: 2202 movs r2, #2 + 800501e: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Disable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); + 8005022: 4b12 ldr r3, [pc, #72] ; (800506c ) + 8005024: 22ca movs r2, #202 ; 0xca + 8005026: 625a str r2, [r3, #36] ; 0x24 + 8005028: 4b10 ldr r3, [pc, #64] ; (800506c ) + 800502a: 2253 movs r2, #83 ; 0x53 + 800502c: 625a str r2, [r3, #36] ; 0x24 + + /* Enable IT SSRU */ + __HAL_RTC_SSRU_ENABLE_IT(hrtc, RTC_IT_SSRU); + 800502e: 4b0f ldr r3, [pc, #60] ; (800506c ) + 8005030: 699b ldr r3, [r3, #24] + 8005032: 4a0e ldr r2, [pc, #56] ; (800506c ) + 8005034: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8005038: 6193 str r3, [r2, #24] + + /* RTC SSRU Interrupt Configuration: EXTI configuration */ + __HAL_RTC_SSRU_EXTI_ENABLE_IT(); + 800503a: 4b0d ldr r3, [pc, #52] ; (8005070 ) + 800503c: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8005040: 4a0b ldr r2, [pc, #44] ; (8005070 ) + 8005042: f443 2380 orr.w r3, r3, #262144 ; 0x40000 + 8005046: f8c2 3080 str.w r3, [r2, #128] ; 0x80 + + /* Enable the write protection for RTC registers */ + __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); + 800504a: 4b08 ldr r3, [pc, #32] ; (800506c ) + 800504c: 22ff movs r2, #255 ; 0xff + 800504e: 625a str r2, [r3, #36] ; 0x24 + + hrtc->State = HAL_RTC_STATE_READY; + 8005050: 687b ldr r3, [r7, #4] + 8005052: 2201 movs r2, #1 + 8005054: f883 202d strb.w r2, [r3, #45] ; 0x2d + + /* Process Unlocked */ + __HAL_UNLOCK(hrtc); + 8005058: 687b ldr r3, [r7, #4] + 800505a: 2200 movs r2, #0 + 800505c: f883 202c strb.w r2, [r3, #44] ; 0x2c + + return HAL_OK; + 8005060: 2300 movs r3, #0 +} + 8005062: 4618 mov r0, r3 + 8005064: 370c adds r7, #12 + 8005066: 46bd mov sp, r7 + 8005068: bc80 pop {r7} + 800506a: 4770 bx lr + 800506c: 40002800 .word 0x40002800 + 8005070: 58000800 .word 0x58000800 + +08005074 : + * @brief Handle SSR underflow interrupt request. + * @param hrtc RTC handle + * @retval None + */ +void HAL_RTCEx_SSRUIRQHandler(RTC_HandleTypeDef *hrtc) +{ + 8005074: b580 push {r7, lr} + 8005076: b082 sub sp, #8 + 8005078: af00 add r7, sp, #0 + 800507a: 6078 str r0, [r7, #4] + if ((RTC->MISR & RTC_MISR_SSRUMF) != 0u) + 800507c: 4b09 ldr r3, [pc, #36] ; (80050a4 ) + 800507e: 6d5b ldr r3, [r3, #84] ; 0x54 + 8005080: f003 0340 and.w r3, r3, #64 ; 0x40 + 8005084: 2b00 cmp r3, #0 + 8005086: d005 beq.n 8005094 + { + /* Immediately clear flags */ + RTC->SCR = RTC_SCR_CSSRUF; + 8005088: 4b06 ldr r3, [pc, #24] ; (80050a4 ) + 800508a: 2240 movs r2, #64 ; 0x40 + 800508c: 65da str r2, [r3, #92] ; 0x5c + /* SSRU callback */ +#if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) + /* Call SSRUEvent registered Callback */ + hrtc->SSRUEventCallback(hrtc); +#else + HAL_RTCEx_SSRUEventCallback(hrtc); + 800508e: 6878 ldr r0, [r7, #4] + 8005090: f7fc f8a9 bl 80011e6 +#endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ + } + + /* Change RTC state */ + hrtc->State = HAL_RTC_STATE_READY; + 8005094: 687b ldr r3, [r7, #4] + 8005096: 2201 movs r2, #1 + 8005098: f883 202d strb.w r2, [r3, #45] ; 0x2d +} + 800509c: bf00 nop + 800509e: 3708 adds r7, #8 + 80050a0: 46bd mov sp, r7 + 80050a2: bd80 pop {r7, pc} + 80050a4: 40002800 .word 0x40002800 + +080050a8 : + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @param Data Data to be written in the specified Backup data register. + * @retval None + */ +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +{ + 80050a8: b480 push {r7} + 80050aa: b087 sub sp, #28 + 80050ac: af00 add r7, sp, #0 + 80050ae: 60f8 str r0, [r7, #12] + 80050b0: 60b9 str r1, [r7, #8] + 80050b2: 607a str r2, [r7, #4] + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (TAMP->BKP0R); + 80050b4: 4b07 ldr r3, [pc, #28] ; (80050d4 ) + 80050b6: 617b str r3, [r7, #20] + tmp += (BackupRegister * 4U); + 80050b8: 68bb ldr r3, [r7, #8] + 80050ba: 009b lsls r3, r3, #2 + 80050bc: 697a ldr r2, [r7, #20] + 80050be: 4413 add r3, r2 + 80050c0: 617b str r3, [r7, #20] + + /* Write the specified register */ + *(__IO uint32_t *)tmp = (uint32_t)Data; + 80050c2: 697b ldr r3, [r7, #20] + 80050c4: 687a ldr r2, [r7, #4] + 80050c6: 601a str r2, [r3, #0] +} + 80050c8: bf00 nop + 80050ca: 371c adds r7, #28 + 80050cc: 46bd mov sp, r7 + 80050ce: bc80 pop {r7} + 80050d0: 4770 bx lr + 80050d2: bf00 nop + 80050d4: 4000b100 .word 0x4000b100 + +080050d8 : + * @param BackupRegister RTC Backup data Register number. + * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB + * @retval Read value + */ +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +{ + 80050d8: b480 push {r7} + 80050da: b085 sub sp, #20 + 80050dc: af00 add r7, sp, #0 + 80050de: 6078 str r0, [r7, #4] + 80050e0: 6039 str r1, [r7, #0] + + UNUSED(hrtc); + /* Check the parameters */ + assert_param(IS_RTC_BKP(BackupRegister)); + + tmp = (uint32_t) & (TAMP->BKP0R); + 80050e2: 4b07 ldr r3, [pc, #28] ; (8005100 ) + 80050e4: 60fb str r3, [r7, #12] + tmp += (BackupRegister * 4U); + 80050e6: 683b ldr r3, [r7, #0] + 80050e8: 009b lsls r3, r3, #2 + 80050ea: 68fa ldr r2, [r7, #12] + 80050ec: 4413 add r3, r2 + 80050ee: 60fb str r3, [r7, #12] + + /* Read the specified register */ + return (*(__IO uint32_t *)tmp); + 80050f0: 68fb ldr r3, [r7, #12] + 80050f2: 681b ldr r3, [r3, #0] +} + 80050f4: 4618 mov r0, r3 + 80050f6: 3714 adds r7, #20 + 80050f8: 46bd mov sp, r7 + 80050fa: bc80 pop {r7} + 80050fc: 4770 bx lr + 80050fe: bf00 nop + 8005100: 4000b100 .word 0x4000b100 + +08005104 : +{ + 8005104: b480 push {r7} + 8005106: b083 sub sp, #12 + 8005108: af00 add r7, sp, #0 + 800510a: 6078 str r0, [r7, #4] + MODIFY_REG(PWR->CR3, PWR_CR3_EWRFBUSY, RadioBusyTrigger); + 800510c: 4b06 ldr r3, [pc, #24] ; (8005128 ) + 800510e: 689b ldr r3, [r3, #8] + 8005110: f423 6200 bic.w r2, r3, #2048 ; 0x800 + 8005114: 4904 ldr r1, [pc, #16] ; (8005128 ) + 8005116: 687b ldr r3, [r7, #4] + 8005118: 4313 orrs r3, r2 + 800511a: 608b str r3, [r1, #8] +} + 800511c: bf00 nop + 800511e: 370c adds r7, #12 + 8005120: 46bd mov sp, r7 + 8005122: bc80 pop {r7} + 8005124: 4770 bx lr + 8005126: bf00 nop + 8005128: 58000400 .word 0x58000400 + +0800512c : +{ + 800512c: b480 push {r7} + 800512e: af00 add r7, sp, #0 + SET_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); + 8005130: 4b05 ldr r3, [pc, #20] ; (8005148 ) + 8005132: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8005136: 4a04 ldr r2, [pc, #16] ; (8005148 ) + 8005138: f443 4300 orr.w r3, r3, #32768 ; 0x8000 + 800513c: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 8005140: bf00 nop + 8005142: 46bd mov sp, r7 + 8005144: bc80 pop {r7} + 8005146: 4770 bx lr + 8005148: 58000400 .word 0x58000400 + +0800514c : +{ + 800514c: b480 push {r7} + 800514e: af00 add r7, sp, #0 + CLEAR_BIT(PWR->SUBGHZSPICR, PWR_SUBGHZSPICR_NSS); + 8005150: 4b05 ldr r3, [pc, #20] ; (8005168 ) + 8005152: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8005156: 4a04 ldr r2, [pc, #16] ; (8005168 ) + 8005158: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 800515c: f8c2 3090 str.w r3, [r2, #144] ; 0x90 +} + 8005160: bf00 nop + 8005162: 46bd mov sp, r7 + 8005164: bc80 pop {r7} + 8005166: 4770 bx lr + 8005168: 58000400 .word 0x58000400 + +0800516c : +{ + 800516c: b480 push {r7} + 800516e: af00 add r7, sp, #0 + WRITE_REG(PWR->SCR, PWR_SCR_CWRFBUSYF); + 8005170: 4b03 ldr r3, [pc, #12] ; (8005180 ) + 8005172: f44f 6200 mov.w r2, #2048 ; 0x800 + 8005176: 619a str r2, [r3, #24] +} + 8005178: bf00 nop + 800517a: 46bd mov sp, r7 + 800517c: bc80 pop {r7} + 800517e: 4770 bx lr + 8005180: 58000400 .word 0x58000400 + +08005184 : +{ + 8005184: b480 push {r7} + 8005186: af00 add r7, sp, #0 + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYS) == (PWR_SR2_RFBUSYS)) ? 1UL : 0UL); + 8005188: 4b06 ldr r3, [pc, #24] ; (80051a4 ) + 800518a: 695b ldr r3, [r3, #20] + 800518c: f003 0302 and.w r3, r3, #2 + 8005190: 2b02 cmp r3, #2 + 8005192: d101 bne.n 8005198 + 8005194: 2301 movs r3, #1 + 8005196: e000 b.n 800519a + 8005198: 2300 movs r3, #0 +} + 800519a: 4618 mov r0, r3 + 800519c: 46bd mov sp, r7 + 800519e: bc80 pop {r7} + 80051a0: 4770 bx lr + 80051a2: bf00 nop + 80051a4: 58000400 .word 0x58000400 + +080051a8 : +{ + 80051a8: b480 push {r7} + 80051aa: af00 add r7, sp, #0 + return ((READ_BIT(PWR->SR2, PWR_SR2_RFBUSYMS) == (PWR_SR2_RFBUSYMS)) ? 1UL : 0UL); + 80051ac: 4b06 ldr r3, [pc, #24] ; (80051c8 ) + 80051ae: 695b ldr r3, [r3, #20] + 80051b0: f003 0304 and.w r3, r3, #4 + 80051b4: 2b04 cmp r3, #4 + 80051b6: d101 bne.n 80051bc + 80051b8: 2301 movs r3, #1 + 80051ba: e000 b.n 80051be + 80051bc: 2300 movs r3, #0 +} + 80051be: 4618 mov r0, r3 + 80051c0: 46bd mov sp, r7 + 80051c2: bc80 pop {r7} + 80051c4: 4770 bx lr + 80051c6: bf00 nop + 80051c8: 58000400 .word 0x58000400 + +080051cc : +{ + 80051cc: b480 push {r7} + 80051ce: af00 add r7, sp, #0 + CLEAR_BIT(RCC->CSR, RCC_CSR_RFRST); + 80051d0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80051d4: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80051d8: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 80051dc: f423 4300 bic.w r3, r3, #32768 ; 0x8000 + 80051e0: f8c2 3094 str.w r3, [r2, #148] ; 0x94 +} + 80051e4: bf00 nop + 80051e6: 46bd mov sp, r7 + 80051e8: bc80 pop {r7} + 80051ea: 4770 bx lr + +080051ec : +{ + 80051ec: b480 push {r7} + 80051ee: af00 add r7, sp, #0 + return ((READ_BIT(RCC->CSR, RCC_CSR_RFRSTF) == (RCC_CSR_RFRSTF)) ? 1UL : 0UL); + 80051f0: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 80051f4: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 80051f8: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 80051fc: f5b3 4f80 cmp.w r3, #16384 ; 0x4000 + 8005200: d101 bne.n 8005206 + 8005202: 2301 movs r3, #1 + 8005204: e000 b.n 8005208 + 8005206: 2300 movs r3, #0 +} + 8005208: 4618 mov r0, r3 + 800520a: 46bd mov sp, r7 + 800520c: bc80 pop {r7} + 800520e: 4770 bx lr + +08005210 : +{ + 8005210: b480 push {r7} + 8005212: b083 sub sp, #12 + 8005214: af00 add r7, sp, #0 + 8005216: 6078 str r0, [r7, #4] + SET_BIT(EXTI->IMR2, ExtiLine); + 8005218: 4b06 ldr r3, [pc, #24] ; (8005234 ) + 800521a: f8d3 2090 ldr.w r2, [r3, #144] ; 0x90 + 800521e: 4905 ldr r1, [pc, #20] ; (8005234 ) + 8005220: 687b ldr r3, [r7, #4] + 8005222: 4313 orrs r3, r2 + 8005224: f8c1 3090 str.w r3, [r1, #144] ; 0x90 +} + 8005228: bf00 nop + 800522a: 370c adds r7, #12 + 800522c: 46bd mov sp, r7 + 800522e: bc80 pop {r7} + 8005230: 4770 bx lr + 8005232: bf00 nop + 8005234: 58000800 .word 0x58000800 + +08005238 : + * set the state to HAL_SUBGHZ_STATE_RESET_RF_READY with __HAL_SUBGHZ_RESET_HANDLE_STATE_RF_READY + * to avoid the reset of Radio peripheral. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_SUBGHZ_Init(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8005238: b580 push {r7, lr} + 800523a: b084 sub sp, #16 + 800523c: af00 add r7, sp, #0 + 800523e: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + __IO uint32_t count; + HAL_SUBGHZ_StateTypeDef subghz_state; + + /* Check the hsubghz handle allocation */ + if (hsubghz == NULL) + 8005240: 687b ldr r3, [r7, #4] + 8005242: 2b00 cmp r3, #0 + 8005244: d103 bne.n 800524e + { + status = HAL_ERROR; + 8005246: 2301 movs r3, #1 + 8005248: 73fb strb r3, [r7, #15] + return status; + 800524a: 7bfb ldrb r3, [r7, #15] + 800524c: e052 b.n 80052f4 + } + else + { + status = HAL_OK; + 800524e: 2300 movs r3, #0 + 8005250: 73fb strb r3, [r7, #15] + } + + assert_param(IS_SUBGHZSPI_BAUDRATE_PRESCALER(hsubghz->Init.BaudratePrescaler)); + + subghz_state = hsubghz->State; + 8005252: 687b ldr r3, [r7, #4] + 8005254: 799b ldrb r3, [r3, #6] + 8005256: 73bb strb r3, [r7, #14] + if ((subghz_state == HAL_SUBGHZ_STATE_RESET) || + 8005258: 7bbb ldrb r3, [r7, #14] + 800525a: 2b00 cmp r3, #0 + 800525c: d002 beq.n 8005264 + 800525e: 7bbb ldrb r3, [r7, #14] + 8005260: 2b03 cmp r3, #3 + 8005262: d109 bne.n 8005278 + (subghz_state == HAL_SUBGHZ_STATE_RESET_RF_READY)) + { + /* Allocate lock resource and initialize it */ + hsubghz->Lock = HAL_UNLOCKED; + 8005264: 687b ldr r3, [r7, #4] + 8005266: 2200 movs r2, #0 + 8005268: 715a strb r2, [r3, #5] + + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + hsubghz->MspInitCallback(hsubghz); +#else + /* Init the low level hardware : GPIO, CLOCK, NVIC... */ + HAL_SUBGHZ_MspInit(hsubghz); + 800526a: 6878 ldr r0, [r7, #4] + 800526c: f7fb fcc0 bl 8000bf0 +#if defined(CM0PLUS) + /* Enable EXTI 44 : Radio IRQ ITs for CPU2 */ + LL_C2_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); +#else + /* Enable EXTI 44 : Radio IRQ ITs for CPU1 */ + LL_EXTI_EnableIT_32_63(LL_EXTI_LINE_44); + 8005270: f44f 5080 mov.w r0, #4096 ; 0x1000 + 8005274: f7ff ffcc bl 8005210 +#endif /* CM0PLUS */ + } + + if (subghz_state == HAL_SUBGHZ_STATE_RESET) + 8005278: 7bbb ldrb r3, [r7, #14] + 800527a: 2b00 cmp r3, #0 + 800527c: d126 bne.n 80052cc + { + /* Reinitialize Radio peripheral only if SUBGHZ is in full RESET state */ + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + 800527e: 687b ldr r3, [r7, #4] + 8005280: 2202 movs r2, #2 + 8005282: 719a strb r2, [r3, #6] + + /* De-asserts the reset signal of the Radio peripheral */ + LL_RCC_RF_DisableReset(); + 8005284: f7ff ffa2 bl 80051cc + + /* Verify that Radio in reset status flag is set */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8005288: 4b1c ldr r3, [pc, #112] ; (80052fc ) + 800528a: 681a ldr r2, [r3, #0] + 800528c: 4613 mov r3, r2 + 800528e: 00db lsls r3, r3, #3 + 8005290: 1a9b subs r3, r3, r2 + 8005292: 009b lsls r3, r3, #2 + 8005294: 0cdb lsrs r3, r3, #19 + 8005296: 2264 movs r2, #100 ; 0x64 + 8005298: fb02 f303 mul.w r3, r2, r3 + 800529c: 60bb str r3, [r7, #8] + + do + { + if (count == 0U) + 800529e: 68bb ldr r3, [r7, #8] + 80052a0: 2b00 cmp r3, #0 + 80052a2: d105 bne.n 80052b0 + { + status = HAL_ERROR; + 80052a4: 2301 movs r3, #1 + 80052a6: 73fb strb r3, [r7, #15] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 80052a8: 687b ldr r3, [r7, #4] + 80052aa: 2201 movs r2, #1 + 80052ac: 609a str r2, [r3, #8] + break; + 80052ae: e007 b.n 80052c0 + } + count--; + 80052b0: 68bb ldr r3, [r7, #8] + 80052b2: 3b01 subs r3, #1 + 80052b4: 60bb str r3, [r7, #8] + } while (LL_RCC_IsRFUnderReset() != 0UL); + 80052b6: f7ff ff99 bl 80051ec + 80052ba: 4603 mov r3, r0 + 80052bc: 2b00 cmp r3, #0 + 80052be: d1ee bne.n 800529e + + /* Asserts the reset signal of the Radio peripheral */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 80052c0: f7ff ff34 bl 800512c +#if defined(CM0PLUS) + /* Enable wakeup signal of the Radio peripheral */ + LL_C2_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); +#else + /* Enable wakeup signal of the Radio peripheral */ + LL_PWR_SetRadioBusyTrigger(LL_PWR_RADIO_BUSY_TRIGGER_WU_IT); + 80052c4: f44f 6000 mov.w r0, #2048 ; 0x800 + 80052c8: f7ff ff1c bl 8005104 +#endif /* CM0PLUS */ + } + + /* Clear Pending Flag */ + LL_PWR_ClearFlag_RFBUSY(); + 80052cc: f7ff ff4e bl 800516c + + if (status == HAL_OK) + 80052d0: 7bfb ldrb r3, [r7, #15] + 80052d2: 2b00 cmp r3, #0 + 80052d4: d10a bne.n 80052ec + { + /* Initialize SUBGHZSPI Peripheral */ + SUBGHZSPI_Init(hsubghz->Init.BaudratePrescaler); + 80052d6: 687b ldr r3, [r7, #4] + 80052d8: 681b ldr r3, [r3, #0] + 80052da: 4618 mov r0, r3 + 80052dc: f000 faac bl 8005838 + + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + 80052e0: 687b ldr r3, [r7, #4] + 80052e2: 2201 movs r2, #1 + 80052e4: 711a strb r2, [r3, #4] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_NONE; + 80052e6: 687b ldr r3, [r7, #4] + 80052e8: 2200 movs r2, #0 + 80052ea: 609a str r2, [r3, #8] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 80052ec: 687b ldr r3, [r7, #4] + 80052ee: 2201 movs r2, #1 + 80052f0: 719a strb r2, [r3, #6] + + return status; + 80052f2: 7bfb ldrb r3, [r7, #15] +} + 80052f4: 4618 mov r0, r3 + 80052f6: 3710 adds r7, #16 + 80052f8: 46bd mov sp, r7 + 80052fa: bd80 pop {r7, pc} + 80052fc: 20000000 .word 0x20000000 + +08005300 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + 8005300: b580 push {r7, lr} + 8005302: b086 sub sp, #24 + 8005304: af00 add r7, sp, #0 + 8005306: 60f8 str r0, [r7, #12] + 8005308: 607a str r2, [r7, #4] + 800530a: 461a mov r2, r3 + 800530c: 460b mov r3, r1 + 800530e: 817b strh r3, [r7, #10] + 8005310: 4613 mov r3, r2 + 8005312: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8005314: 68fb ldr r3, [r7, #12] + 8005316: 799b ldrb r3, [r3, #6] + 8005318: b2db uxtb r3, r3 + 800531a: 2b01 cmp r3, #1 + 800531c: d14a bne.n 80053b4 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 800531e: 68fb ldr r3, [r7, #12] + 8005320: 795b ldrb r3, [r3, #5] + 8005322: 2b01 cmp r3, #1 + 8005324: d101 bne.n 800532a + 8005326: 2302 movs r3, #2 + 8005328: e045 b.n 80053b6 + 800532a: 68fb ldr r3, [r7, #12] + 800532c: 2201 movs r2, #1 + 800532e: 715a strb r2, [r3, #5] + + hsubghz->State = HAL_SUBGHZ_STATE_BUSY; + 8005330: 68fb ldr r3, [r7, #12] + 8005332: 2202 movs r2, #2 + 8005334: 719a strb r2, [r3, #6] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8005336: 68f8 ldr r0, [r7, #12] + 8005338: f000 fb4c bl 80059d4 + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 800533c: f7ff ff06 bl 800514c + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_REGISTER); + 8005340: 210d movs r1, #13 + 8005342: 68f8 ldr r0, [r7, #12] + 8005344: f000 fa98 bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + 8005348: 897b ldrh r3, [r7, #10] + 800534a: 0a1b lsrs r3, r3, #8 + 800534c: b29b uxth r3, r3 + 800534e: b2db uxtb r3, r3 + 8005350: 4619 mov r1, r3 + 8005352: 68f8 ldr r0, [r7, #12] + 8005354: f000 fa90 bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + 8005358: 897b ldrh r3, [r7, #10] + 800535a: b2db uxtb r3, r3 + 800535c: 4619 mov r1, r3 + 800535e: 68f8 ldr r0, [r7, #12] + 8005360: f000 fa8a bl 8005878 + + for (uint16_t i = 0U; i < Size; i++) + 8005364: 2300 movs r3, #0 + 8005366: 82bb strh r3, [r7, #20] + 8005368: e00a b.n 8005380 + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 800536a: 8abb ldrh r3, [r7, #20] + 800536c: 687a ldr r2, [r7, #4] + 800536e: 4413 add r3, r2 + 8005370: 781b ldrb r3, [r3, #0] + 8005372: 4619 mov r1, r3 + 8005374: 68f8 ldr r0, [r7, #12] + 8005376: f000 fa7f bl 8005878 + for (uint16_t i = 0U; i < Size; i++) + 800537a: 8abb ldrh r3, [r7, #20] + 800537c: 3301 adds r3, #1 + 800537e: 82bb strh r3, [r7, #20] + 8005380: 8aba ldrh r2, [r7, #20] + 8005382: 893b ldrh r3, [r7, #8] + 8005384: 429a cmp r2, r3 + 8005386: d3f0 bcc.n 800536a + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8005388: f7ff fed0 bl 800512c + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 800538c: 68f8 ldr r0, [r7, #12] + 800538e: f000 fb45 bl 8005a1c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8005392: 68fb ldr r3, [r7, #12] + 8005394: 689b ldr r3, [r3, #8] + 8005396: 2b00 cmp r3, #0 + 8005398: d002 beq.n 80053a0 + { + status = HAL_ERROR; + 800539a: 2301 movs r3, #1 + 800539c: 75fb strb r3, [r7, #23] + 800539e: e001 b.n 80053a4 + } + else + { + status = HAL_OK; + 80053a0: 2300 movs r3, #0 + 80053a2: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 80053a4: 68fb ldr r3, [r7, #12] + 80053a6: 2201 movs r2, #1 + 80053a8: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 80053aa: 68fb ldr r3, [r7, #12] + 80053ac: 2200 movs r2, #0 + 80053ae: 715a strb r2, [r3, #5] + + return status; + 80053b0: 7dfb ldrb r3, [r7, #23] + 80053b2: e000 b.n 80053b6 + } + else + { + return HAL_BUSY; + 80053b4: 2302 movs r3, #2 + } +} + 80053b6: 4618 mov r0, r3 + 80053b8: 3718 adds r7, #24 + 80053ba: 46bd mov sp, r7 + 80053bc: bd80 pop {r7, pc} + +080053be : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadRegisters(SUBGHZ_HandleTypeDef *hsubghz, + uint16_t Address, + uint8_t *pBuffer, + uint16_t Size) +{ + 80053be: b580 push {r7, lr} + 80053c0: b088 sub sp, #32 + 80053c2: af00 add r7, sp, #0 + 80053c4: 60f8 str r0, [r7, #12] + 80053c6: 607a str r2, [r7, #4] + 80053c8: 461a mov r2, r3 + 80053ca: 460b mov r3, r1 + 80053cc: 817b strh r3, [r7, #10] + 80053ce: 4613 mov r3, r2 + 80053d0: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 80053d2: 687b ldr r3, [r7, #4] + 80053d4: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 80053d6: 68fb ldr r3, [r7, #12] + 80053d8: 799b ldrb r3, [r3, #6] + 80053da: b2db uxtb r3, r3 + 80053dc: 2b01 cmp r3, #1 + 80053de: d14a bne.n 8005476 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 80053e0: 68fb ldr r3, [r7, #12] + 80053e2: 795b ldrb r3, [r3, #5] + 80053e4: 2b01 cmp r3, #1 + 80053e6: d101 bne.n 80053ec + 80053e8: 2302 movs r3, #2 + 80053ea: e045 b.n 8005478 + 80053ec: 68fb ldr r3, [r7, #12] + 80053ee: 2201 movs r2, #1 + 80053f0: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 80053f2: 68f8 ldr r0, [r7, #12] + 80053f4: f000 faee bl 80059d4 + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 80053f8: f7ff fea8 bl 800514c + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_REGISTER); + 80053fc: 211d movs r1, #29 + 80053fe: 68f8 ldr r0, [r7, #12] + 8005400: f000 fa3a bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)((Address & 0xFF00U) >> 8U)); + 8005404: 897b ldrh r3, [r7, #10] + 8005406: 0a1b lsrs r3, r3, #8 + 8005408: b29b uxth r3, r3 + 800540a: b2db uxtb r3, r3 + 800540c: 4619 mov r1, r3 + 800540e: 68f8 ldr r0, [r7, #12] + 8005410: f000 fa32 bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)(Address & 0x00FFU)); + 8005414: 897b ldrh r3, [r7, #10] + 8005416: b2db uxtb r3, r3 + 8005418: 4619 mov r1, r3 + 800541a: 68f8 ldr r0, [r7, #12] + 800541c: f000 fa2c bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, 0U); + 8005420: 2100 movs r1, #0 + 8005422: 68f8 ldr r0, [r7, #12] + 8005424: f000 fa28 bl 8005878 + + for (uint16_t i = 0U; i < Size; i++) + 8005428: 2300 movs r3, #0 + 800542a: 82fb strh r3, [r7, #22] + 800542c: e009 b.n 8005442 + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 800542e: 69b9 ldr r1, [r7, #24] + 8005430: 68f8 ldr r0, [r7, #12] + 8005432: f000 fa77 bl 8005924 + pData++; + 8005436: 69bb ldr r3, [r7, #24] + 8005438: 3301 adds r3, #1 + 800543a: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 800543c: 8afb ldrh r3, [r7, #22] + 800543e: 3301 adds r3, #1 + 8005440: 82fb strh r3, [r7, #22] + 8005442: 8afa ldrh r2, [r7, #22] + 8005444: 893b ldrh r3, [r7, #8] + 8005446: 429a cmp r2, r3 + 8005448: d3f1 bcc.n 800542e + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 800544a: f7ff fe6f bl 800512c + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 800544e: 68f8 ldr r0, [r7, #12] + 8005450: f000 fae4 bl 8005a1c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8005454: 68fb ldr r3, [r7, #12] + 8005456: 689b ldr r3, [r3, #8] + 8005458: 2b00 cmp r3, #0 + 800545a: d002 beq.n 8005462 + { + status = HAL_ERROR; + 800545c: 2301 movs r3, #1 + 800545e: 77fb strb r3, [r7, #31] + 8005460: e001 b.n 8005466 + } + else + { + status = HAL_OK; + 8005462: 2300 movs r3, #0 + 8005464: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8005466: 68fb ldr r3, [r7, #12] + 8005468: 2201 movs r2, #1 + 800546a: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 800546c: 68fb ldr r3, [r7, #12] + 800546e: 2200 movs r2, #0 + 8005470: 715a strb r2, [r3, #5] + + return status; + 8005472: 7ffb ldrb r3, [r7, #31] + 8005474: e000 b.n 8005478 + } + else + { + return HAL_BUSY; + 8005476: 2302 movs r3, #2 + } +} + 8005478: 4618 mov r0, r3 + 800547a: 3720 adds r7, #32 + 800547c: 46bd mov sp, r7 + 800547e: bd80 pop {r7, pc} + +08005480 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecSetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioSetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + 8005480: b580 push {r7, lr} + 8005482: b086 sub sp, #24 + 8005484: af00 add r7, sp, #0 + 8005486: 60f8 str r0, [r7, #12] + 8005488: 607a str r2, [r7, #4] + 800548a: 461a mov r2, r3 + 800548c: 460b mov r3, r1 + 800548e: 72fb strb r3, [r7, #11] + 8005490: 4613 mov r3, r2 + 8005492: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + /* LORA Modulation not available on STM32WLx4xx devices */ + assert_param(IS_SUBGHZ_MODULATION_SUPPORTED(Command, pBuffer[0U])); + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8005494: 68fb ldr r3, [r7, #12] + 8005496: 799b ldrb r3, [r3, #6] + 8005498: b2db uxtb r3, r3 + 800549a: 2b01 cmp r3, #1 + 800549c: d14a bne.n 8005534 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 800549e: 68fb ldr r3, [r7, #12] + 80054a0: 795b ldrb r3, [r3, #5] + 80054a2: 2b01 cmp r3, #1 + 80054a4: d101 bne.n 80054aa + 80054a6: 2302 movs r3, #2 + 80054a8: e045 b.n 8005536 + 80054aa: 68fb ldr r3, [r7, #12] + 80054ac: 2201 movs r2, #1 + 80054ae: 715a strb r2, [r3, #5] + + /* Need to wakeup Radio if already in Sleep at startup */ + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 80054b0: 68f8 ldr r0, [r7, #12] + 80054b2: f000 fa8f bl 80059d4 + + if ((Command == RADIO_SET_SLEEP) || (Command == RADIO_SET_RXDUTYCYCLE)) + 80054b6: 7afb ldrb r3, [r7, #11] + 80054b8: 2b84 cmp r3, #132 ; 0x84 + 80054ba: d002 beq.n 80054c2 + 80054bc: 7afb ldrb r3, [r7, #11] + 80054be: 2b94 cmp r3, #148 ; 0x94 + 80054c0: d103 bne.n 80054ca + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_ENABLE; + 80054c2: 68fb ldr r3, [r7, #12] + 80054c4: 2201 movs r2, #1 + 80054c6: 711a strb r2, [r3, #4] + 80054c8: e002 b.n 80054d0 + } + else + { + hsubghz->DeepSleep = SUBGHZ_DEEP_SLEEP_DISABLE; + 80054ca: 68fb ldr r3, [r7, #12] + 80054cc: 2200 movs r2, #0 + 80054ce: 711a strb r2, [r3, #4] + } + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 80054d0: f7ff fe3c bl 800514c + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + 80054d4: 7afb ldrb r3, [r7, #11] + 80054d6: 4619 mov r1, r3 + 80054d8: 68f8 ldr r0, [r7, #12] + 80054da: f000 f9cd bl 8005878 + + for (uint16_t i = 0U; i < Size; i++) + 80054de: 2300 movs r3, #0 + 80054e0: 82bb strh r3, [r7, #20] + 80054e2: e00a b.n 80054fa + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 80054e4: 8abb ldrh r3, [r7, #20] + 80054e6: 687a ldr r2, [r7, #4] + 80054e8: 4413 add r3, r2 + 80054ea: 781b ldrb r3, [r3, #0] + 80054ec: 4619 mov r1, r3 + 80054ee: 68f8 ldr r0, [r7, #12] + 80054f0: f000 f9c2 bl 8005878 + for (uint16_t i = 0U; i < Size; i++) + 80054f4: 8abb ldrh r3, [r7, #20] + 80054f6: 3301 adds r3, #1 + 80054f8: 82bb strh r3, [r7, #20] + 80054fa: 8aba ldrh r2, [r7, #20] + 80054fc: 893b ldrh r3, [r7, #8] + 80054fe: 429a cmp r2, r3 + 8005500: d3f0 bcc.n 80054e4 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8005502: f7ff fe13 bl 800512c + + if (Command != RADIO_SET_SLEEP) + 8005506: 7afb ldrb r3, [r7, #11] + 8005508: 2b84 cmp r3, #132 ; 0x84 + 800550a: d002 beq.n 8005512 + { + (void)SUBGHZ_WaitOnBusy(hsubghz); + 800550c: 68f8 ldr r0, [r7, #12] + 800550e: f000 fa85 bl 8005a1c + } + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8005512: 68fb ldr r3, [r7, #12] + 8005514: 689b ldr r3, [r3, #8] + 8005516: 2b00 cmp r3, #0 + 8005518: d002 beq.n 8005520 + { + status = HAL_ERROR; + 800551a: 2301 movs r3, #1 + 800551c: 75fb strb r3, [r7, #23] + 800551e: e001 b.n 8005524 + } + else + { + status = HAL_OK; + 8005520: 2300 movs r3, #0 + 8005522: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8005524: 68fb ldr r3, [r7, #12] + 8005526: 2201 movs r2, #1 + 8005528: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 800552a: 68fb ldr r3, [r7, #12] + 800552c: 2200 movs r2, #0 + 800552e: 715a strb r2, [r3, #5] + + return status; + 8005530: 7dfb ldrb r3, [r7, #23] + 8005532: e000 b.n 8005536 + } + else + { + return HAL_BUSY; + 8005534: 2302 movs r3, #2 + } +} + 8005536: 4618 mov r0, r3 + 8005538: 3718 adds r7, #24 + 800553a: 46bd mov sp, r7 + 800553c: bd80 pop {r7, pc} + +0800553e : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ExecGetCmd(SUBGHZ_HandleTypeDef *hsubghz, + SUBGHZ_RadioGetCmd_t Command, + uint8_t *pBuffer, + uint16_t Size) +{ + 800553e: b580 push {r7, lr} + 8005540: b088 sub sp, #32 + 8005542: af00 add r7, sp, #0 + 8005544: 60f8 str r0, [r7, #12] + 8005546: 607a str r2, [r7, #4] + 8005548: 461a mov r2, r3 + 800554a: 460b mov r3, r1 + 800554c: 72fb strb r3, [r7, #11] + 800554e: 4613 mov r3, r2 + 8005550: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 8005552: 687b ldr r3, [r7, #4] + 8005554: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 8005556: 68fb ldr r3, [r7, #12] + 8005558: 799b ldrb r3, [r3, #6] + 800555a: b2db uxtb r3, r3 + 800555c: 2b01 cmp r3, #1 + 800555e: d13d bne.n 80055dc + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8005560: 68fb ldr r3, [r7, #12] + 8005562: 795b ldrb r3, [r3, #5] + 8005564: 2b01 cmp r3, #1 + 8005566: d101 bne.n 800556c + 8005568: 2302 movs r3, #2 + 800556a: e038 b.n 80055de + 800556c: 68fb ldr r3, [r7, #12] + 800556e: 2201 movs r2, #1 + 8005570: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8005572: 68f8 ldr r0, [r7, #12] + 8005574: f000 fa2e bl 80059d4 + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 8005578: f7ff fde8 bl 800514c + + (void)SUBGHZSPI_Transmit(hsubghz, (uint8_t)Command); + 800557c: 7afb ldrb r3, [r7, #11] + 800557e: 4619 mov r1, r3 + 8005580: 68f8 ldr r0, [r7, #12] + 8005582: f000 f979 bl 8005878 + + /* Use to flush the Status (First byte) receive from SUBGHZ as not use */ + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + 8005586: 2100 movs r1, #0 + 8005588: 68f8 ldr r0, [r7, #12] + 800558a: f000 f975 bl 8005878 + + for (uint16_t i = 0U; i < Size; i++) + 800558e: 2300 movs r3, #0 + 8005590: 82fb strh r3, [r7, #22] + 8005592: e009 b.n 80055a8 + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 8005594: 69b9 ldr r1, [r7, #24] + 8005596: 68f8 ldr r0, [r7, #12] + 8005598: f000 f9c4 bl 8005924 + pData++; + 800559c: 69bb ldr r3, [r7, #24] + 800559e: 3301 adds r3, #1 + 80055a0: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 80055a2: 8afb ldrh r3, [r7, #22] + 80055a4: 3301 adds r3, #1 + 80055a6: 82fb strh r3, [r7, #22] + 80055a8: 8afa ldrh r2, [r7, #22] + 80055aa: 893b ldrh r3, [r7, #8] + 80055ac: 429a cmp r2, r3 + 80055ae: d3f1 bcc.n 8005594 + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 80055b0: f7ff fdbc bl 800512c + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 80055b4: 68f8 ldr r0, [r7, #12] + 80055b6: f000 fa31 bl 8005a1c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 80055ba: 68fb ldr r3, [r7, #12] + 80055bc: 689b ldr r3, [r3, #8] + 80055be: 2b00 cmp r3, #0 + 80055c0: d002 beq.n 80055c8 + { + status = HAL_ERROR; + 80055c2: 2301 movs r3, #1 + 80055c4: 77fb strb r3, [r7, #31] + 80055c6: e001 b.n 80055cc + } + else + { + status = HAL_OK; + 80055c8: 2300 movs r3, #0 + 80055ca: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 80055cc: 68fb ldr r3, [r7, #12] + 80055ce: 2201 movs r2, #1 + 80055d0: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 80055d2: 68fb ldr r3, [r7, #12] + 80055d4: 2200 movs r2, #0 + 80055d6: 715a strb r2, [r3, #5] + + return status; + 80055d8: 7ffb ldrb r3, [r7, #31] + 80055da: e000 b.n 80055de + } + else + { + return HAL_BUSY; + 80055dc: 2302 movs r3, #2 + } +} + 80055de: 4618 mov r0, r3 + 80055e0: 3720 adds r7, #32 + 80055e2: 46bd mov sp, r7 + 80055e4: bd80 pop {r7, pc} + +080055e6 : + */ +HAL_StatusTypeDef HAL_SUBGHZ_WriteBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + 80055e6: b580 push {r7, lr} + 80055e8: b086 sub sp, #24 + 80055ea: af00 add r7, sp, #0 + 80055ec: 60f8 str r0, [r7, #12] + 80055ee: 607a str r2, [r7, #4] + 80055f0: 461a mov r2, r3 + 80055f2: 460b mov r3, r1 + 80055f4: 72fb strb r3, [r7, #11] + 80055f6: 4613 mov r3, r2 + 80055f8: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 80055fa: 68fb ldr r3, [r7, #12] + 80055fc: 799b ldrb r3, [r3, #6] + 80055fe: b2db uxtb r3, r3 + 8005600: 2b01 cmp r3, #1 + 8005602: d13e bne.n 8005682 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 8005604: 68fb ldr r3, [r7, #12] + 8005606: 795b ldrb r3, [r3, #5] + 8005608: 2b01 cmp r3, #1 + 800560a: d101 bne.n 8005610 + 800560c: 2302 movs r3, #2 + 800560e: e039 b.n 8005684 + 8005610: 68fb ldr r3, [r7, #12] + 8005612: 2201 movs r2, #1 + 8005614: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 8005616: 68f8 ldr r0, [r7, #12] + 8005618: f000 f9dc bl 80059d4 + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 800561c: f7ff fd96 bl 800514c + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_WRITE_BUFFER); + 8005620: 210e movs r1, #14 + 8005622: 68f8 ldr r0, [r7, #12] + 8005624: f000 f928 bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + 8005628: 7afb ldrb r3, [r7, #11] + 800562a: 4619 mov r1, r3 + 800562c: 68f8 ldr r0, [r7, #12] + 800562e: f000 f923 bl 8005878 + + for (uint16_t i = 0U; i < Size; i++) + 8005632: 2300 movs r3, #0 + 8005634: 82bb strh r3, [r7, #20] + 8005636: e00a b.n 800564e + { + (void)SUBGHZSPI_Transmit(hsubghz, pBuffer[i]); + 8005638: 8abb ldrh r3, [r7, #20] + 800563a: 687a ldr r2, [r7, #4] + 800563c: 4413 add r3, r2 + 800563e: 781b ldrb r3, [r3, #0] + 8005640: 4619 mov r1, r3 + 8005642: 68f8 ldr r0, [r7, #12] + 8005644: f000 f918 bl 8005878 + for (uint16_t i = 0U; i < Size; i++) + 8005648: 8abb ldrh r3, [r7, #20] + 800564a: 3301 adds r3, #1 + 800564c: 82bb strh r3, [r7, #20] + 800564e: 8aba ldrh r2, [r7, #20] + 8005650: 893b ldrh r3, [r7, #8] + 8005652: 429a cmp r2, r3 + 8005654: d3f0 bcc.n 8005638 + } + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8005656: f7ff fd69 bl 800512c + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 800565a: 68f8 ldr r0, [r7, #12] + 800565c: f000 f9de bl 8005a1c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8005660: 68fb ldr r3, [r7, #12] + 8005662: 689b ldr r3, [r3, #8] + 8005664: 2b00 cmp r3, #0 + 8005666: d002 beq.n 800566e + { + status = HAL_ERROR; + 8005668: 2301 movs r3, #1 + 800566a: 75fb strb r3, [r7, #23] + 800566c: e001 b.n 8005672 + } + else + { + status = HAL_OK; + 800566e: 2300 movs r3, #0 + 8005670: 75fb strb r3, [r7, #23] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8005672: 68fb ldr r3, [r7, #12] + 8005674: 2201 movs r2, #1 + 8005676: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8005678: 68fb ldr r3, [r7, #12] + 800567a: 2200 movs r2, #0 + 800567c: 715a strb r2, [r3, #5] + + return status; + 800567e: 7dfb ldrb r3, [r7, #23] + 8005680: e000 b.n 8005684 + } + else + { + return HAL_BUSY; + 8005682: 2302 movs r3, #2 + } +} + 8005684: 4618 mov r0, r3 + 8005686: 3718 adds r7, #24 + 8005688: 46bd mov sp, r7 + 800568a: bd80 pop {r7, pc} + +0800568c : + */ +HAL_StatusTypeDef HAL_SUBGHZ_ReadBuffer(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Offset, + uint8_t *pBuffer, + uint16_t Size) +{ + 800568c: b580 push {r7, lr} + 800568e: b088 sub sp, #32 + 8005690: af00 add r7, sp, #0 + 8005692: 60f8 str r0, [r7, #12] + 8005694: 607a str r2, [r7, #4] + 8005696: 461a mov r2, r3 + 8005698: 460b mov r3, r1 + 800569a: 72fb strb r3, [r7, #11] + 800569c: 4613 mov r3, r2 + 800569e: 813b strh r3, [r7, #8] + HAL_StatusTypeDef status; + uint8_t *pData = pBuffer; + 80056a0: 687b ldr r3, [r7, #4] + 80056a2: 61bb str r3, [r7, #24] + + if (hsubghz->State == HAL_SUBGHZ_STATE_READY) + 80056a4: 68fb ldr r3, [r7, #12] + 80056a6: 799b ldrb r3, [r3, #6] + 80056a8: b2db uxtb r3, r3 + 80056aa: 2b01 cmp r3, #1 + 80056ac: d141 bne.n 8005732 + { + /* Process Locked */ + __HAL_LOCK(hsubghz); + 80056ae: 68fb ldr r3, [r7, #12] + 80056b0: 795b ldrb r3, [r3, #5] + 80056b2: 2b01 cmp r3, #1 + 80056b4: d101 bne.n 80056ba + 80056b6: 2302 movs r3, #2 + 80056b8: e03c b.n 8005734 + 80056ba: 68fb ldr r3, [r7, #12] + 80056bc: 2201 movs r2, #1 + 80056be: 715a strb r2, [r3, #5] + + (void)SUBGHZ_CheckDeviceReady(hsubghz); + 80056c0: 68f8 ldr r0, [r7, #12] + 80056c2: f000 f987 bl 80059d4 + + /* NSS = 0 */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 80056c6: f7ff fd41 bl 800514c + + (void)SUBGHZSPI_Transmit(hsubghz, SUBGHZ_RADIO_READ_BUFFER); + 80056ca: 211e movs r1, #30 + 80056cc: 68f8 ldr r0, [r7, #12] + 80056ce: f000 f8d3 bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, Offset); + 80056d2: 7afb ldrb r3, [r7, #11] + 80056d4: 4619 mov r1, r3 + 80056d6: 68f8 ldr r0, [r7, #12] + 80056d8: f000 f8ce bl 8005878 + (void)SUBGHZSPI_Transmit(hsubghz, 0x00U); + 80056dc: 2100 movs r1, #0 + 80056de: 68f8 ldr r0, [r7, #12] + 80056e0: f000 f8ca bl 8005878 + + for (uint16_t i = 0U; i < Size; i++) + 80056e4: 2300 movs r3, #0 + 80056e6: 82fb strh r3, [r7, #22] + 80056e8: e009 b.n 80056fe + { + (void)SUBGHZSPI_Receive(hsubghz, (pData)); + 80056ea: 69b9 ldr r1, [r7, #24] + 80056ec: 68f8 ldr r0, [r7, #12] + 80056ee: f000 f919 bl 8005924 + pData++; + 80056f2: 69bb ldr r3, [r7, #24] + 80056f4: 3301 adds r3, #1 + 80056f6: 61bb str r3, [r7, #24] + for (uint16_t i = 0U; i < Size; i++) + 80056f8: 8afb ldrh r3, [r7, #22] + 80056fa: 3301 adds r3, #1 + 80056fc: 82fb strh r3, [r7, #22] + 80056fe: 8afa ldrh r2, [r7, #22] + 8005700: 893b ldrh r3, [r7, #8] + 8005702: 429a cmp r2, r3 + 8005704: d3f1 bcc.n 80056ea + } + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8005706: f7ff fd11 bl 800512c + + (void)SUBGHZ_WaitOnBusy(hsubghz); + 800570a: 68f8 ldr r0, [r7, #12] + 800570c: f000 f986 bl 8005a1c + + if (hsubghz->ErrorCode != HAL_SUBGHZ_ERROR_NONE) + 8005710: 68fb ldr r3, [r7, #12] + 8005712: 689b ldr r3, [r3, #8] + 8005714: 2b00 cmp r3, #0 + 8005716: d002 beq.n 800571e + { + status = HAL_ERROR; + 8005718: 2301 movs r3, #1 + 800571a: 77fb strb r3, [r7, #31] + 800571c: e001 b.n 8005722 + } + else + { + status = HAL_OK; + 800571e: 2300 movs r3, #0 + 8005720: 77fb strb r3, [r7, #31] + } + + hsubghz->State = HAL_SUBGHZ_STATE_READY; + 8005722: 68fb ldr r3, [r7, #12] + 8005724: 2201 movs r2, #1 + 8005726: 719a strb r2, [r3, #6] + + /* Process Unlocked */ + __HAL_UNLOCK(hsubghz); + 8005728: 68fb ldr r3, [r7, #12] + 800572a: 2200 movs r2, #0 + 800572c: 715a strb r2, [r3, #5] + + return status; + 800572e: 7ffb ldrb r3, [r7, #31] + 8005730: e000 b.n 8005734 + } + else + { + return HAL_BUSY; + 8005732: 2302 movs r3, #2 + } +} + 8005734: 4618 mov r0, r3 + 8005736: 3720 adds r7, #32 + 8005738: 46bd mov sp, r7 + 800573a: bd80 pop {r7, pc} + +0800573c : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the configuration information for the specified SUBGHZ module. + * @retval None + */ +void HAL_SUBGHZ_IRQHandler(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800573c: b580 push {r7, lr} + 800573e: b084 sub sp, #16 + 8005740: af00 add r7, sp, #0 + 8005742: 6078 str r0, [r7, #4] + uint8_t tmpisr[2U] = {0U}; + 8005744: 2300 movs r3, #0 + 8005746: 81bb strh r3, [r7, #12] + uint16_t itsource; + + /* Retrieve Interrupts from SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecGetCmd(hsubghz, RADIO_GET_IRQSTATUS, tmpisr, 2U); + 8005748: f107 020c add.w r2, r7, #12 + 800574c: 2302 movs r3, #2 + 800574e: 2112 movs r1, #18 + 8005750: 6878 ldr r0, [r7, #4] + 8005752: f7ff fef4 bl 800553e + itsource = tmpisr[0U]; + 8005756: 7b3b ldrb r3, [r7, #12] + 8005758: 81fb strh r3, [r7, #14] + itsource = (itsource << 8U) | tmpisr[1U]; + 800575a: 89fb ldrh r3, [r7, #14] + 800575c: 021b lsls r3, r3, #8 + 800575e: b21a sxth r2, r3 + 8005760: 7b7b ldrb r3, [r7, #13] + 8005762: b21b sxth r3, r3 + 8005764: 4313 orrs r3, r2 + 8005766: b21b sxth r3, r3 + 8005768: 81fb strh r3, [r7, #14] + + /* Clear SUBGHZ Irq Register */ + (void)HAL_SUBGHZ_ExecSetCmd(hsubghz, RADIO_CLR_IRQSTATUS, tmpisr, 2U); + 800576a: f107 020c add.w r2, r7, #12 + 800576e: 2302 movs r3, #2 + 8005770: 2102 movs r1, #2 + 8005772: 6878 ldr r0, [r7, #4] + 8005774: f7ff fe84 bl 8005480 + + /* Packet transmission completed Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_TX_CPLT) != RESET) + 8005778: 89fb ldrh r3, [r7, #14] + 800577a: f003 0301 and.w r3, r3, #1 + 800577e: 2b00 cmp r3, #0 + 8005780: d002 beq.n 8005788 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->TxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_TxCpltCallback(hsubghz); + 8005782: 6878 ldr r0, [r7, #4] + 8005784: f005 fd24 bl 800b1d0 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Packet received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_CPLT) != RESET) + 8005788: 89fb ldrh r3, [r7, #14] + 800578a: f003 0302 and.w r3, r3, #2 + 800578e: 2b00 cmp r3, #0 + 8005790: d002 beq.n 8005798 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxCpltCallback(hsubghz); +#else + HAL_SUBGHZ_RxCpltCallback(hsubghz); + 8005792: 6878 ldr r0, [r7, #4] + 8005794: f005 fd2a bl 800b1ec +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Preamble Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_PREAMBLE_DETECTED) != RESET) + 8005798: 89fb ldrh r3, [r7, #14] + 800579a: f003 0304 and.w r3, r3, #4 + 800579e: 2b00 cmp r3, #0 + 80057a0: d002 beq.n 80057a8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->PreambleDetectedCallback(hsubghz); +#else + HAL_SUBGHZ_PreambleDetectedCallback(hsubghz); + 80057a2: 6878 ldr r0, [r7, #4] + 80057a4: f005 fd7a bl 800b29c +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid sync word detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_SYNCWORD_VALID) != RESET) + 80057a8: 89fb ldrh r3, [r7, #14] + 80057aa: f003 0308 and.w r3, r3, #8 + 80057ae: 2b00 cmp r3, #0 + 80057b0: d002 beq.n 80057b8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->SyncWordValidCallback(hsubghz); +#else + HAL_SUBGHZ_SyncWordValidCallback(hsubghz); + 80057b2: 6878 ldr r0, [r7, #4] + 80057b4: f005 fd80 bl 800b2b8 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Valid LoRa header received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_VALID) != RESET) + 80057b8: 89fb ldrh r3, [r7, #14] + 80057ba: f003 0310 and.w r3, r3, #16 + 80057be: 2b00 cmp r3, #0 + 80057c0: d002 beq.n 80057c8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderValidCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderValidCallback(hsubghz); + 80057c2: 6878 ldr r0, [r7, #4] + 80057c4: f005 fd86 bl 800b2d4 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LoRa header CRC error Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_HEADER_ERROR) != RESET) + 80057c8: 89fb ldrh r3, [r7, #14] + 80057ca: f003 0320 and.w r3, r3, #32 + 80057ce: 2b00 cmp r3, #0 + 80057d0: d002 beq.n 80057d8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->HeaderErrorCallback(hsubghz); +#else + HAL_SUBGHZ_HeaderErrorCallback(hsubghz); + 80057d2: 6878 ldr r0, [r7, #4] + 80057d4: f005 fd54 bl 800b280 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Wrong CRC received Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CRC_ERROR) != RESET) + 80057d8: 89fb ldrh r3, [r7, #14] + 80057da: f003 0340 and.w r3, r3, #64 ; 0x40 + 80057de: 2b00 cmp r3, #0 + 80057e0: d002 beq.n 80057e8 + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->CRCErrorCallback(hsubghz); +#else + HAL_SUBGHZ_CRCErrorCallback(hsubghz); + 80057e2: 6878 ldr r0, [r7, #4] + 80057e4: f005 fd10 bl 800b208 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Channel activity detection finished Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_DONE) != RESET) + 80057e8: 89fb ldrh r3, [r7, #14] + 80057ea: f003 0380 and.w r3, r3, #128 ; 0x80 + 80057ee: 2b00 cmp r3, #0 + 80057f0: d00d beq.n 800580e + { + hsubghz->CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + } +#else + /* Channel activity Detected Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_CAD_ACTIVITY_DETECTED) != RESET) + 80057f2: 89fb ldrh r3, [r7, #14] + 80057f4: f403 7380 and.w r3, r3, #256 ; 0x100 + 80057f8: 2b00 cmp r3, #0 + 80057fa: d004 beq.n 8005806 + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_DETECTED); + 80057fc: 2101 movs r1, #1 + 80057fe: 6878 ldr r0, [r7, #4] + 8005800: f005 fd10 bl 800b224 + 8005804: e003 b.n 800580e + } + else + { + HAL_SUBGHZ_CADStatusCallback(hsubghz, HAL_SUBGHZ_CAD_CLEAR); + 8005806: 2100 movs r1, #0 + 8005808: 6878 ldr r0, [r7, #4] + 800580a: f005 fd0b bl 800b224 + } +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* Rx or Tx Timeout Interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_RX_TX_TIMEOUT) != RESET) + 800580e: 89fb ldrh r3, [r7, #14] + 8005810: f403 7300 and.w r3, r3, #512 ; 0x200 + 8005814: 2b00 cmp r3, #0 + 8005816: d002 beq.n 800581e + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->RxTxTimeoutCallback(hsubghz); +#else + HAL_SUBGHZ_RxTxTimeoutCallback(hsubghz); + 8005818: 6878 ldr r0, [r7, #4] + 800581a: f005 fd21 bl 800b260 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } + + /* LR_FHSS Hop interrupt */ + if (SUBGHZ_CHECK_IT_SOURCE(itsource, SUBGHZ_IT_LR_FHSS_HOP) != RESET) + 800581e: 89fb ldrh r3, [r7, #14] + 8005820: f403 4380 and.w r3, r3, #16384 ; 0x4000 + 8005824: 2b00 cmp r3, #0 + 8005826: d002 beq.n 800582e + { +#if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1U) + hsubghz->LrFhssHopCallback(hsubghz); +#else + HAL_SUBGHZ_LrFhssHopCallback(hsubghz); + 8005828: 6878 ldr r0, [r7, #4] + 800582a: f005 fd61 bl 800b2f0 +#endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ + } +} + 800582e: bf00 nop + 8005830: 3710 adds r7, #16 + 8005832: 46bd mov sp, r7 + 8005834: bd80 pop {r7, pc} + ... + +08005838 : + * @brief Initializes the SUBGHZSPI peripheral + * @param BaudratePrescaler SPI Baudrate prescaler + * @retval None + */ +void SUBGHZSPI_Init(uint32_t BaudratePrescaler) +{ + 8005838: b480 push {r7} + 800583a: b083 sub sp, #12 + 800583c: af00 add r7, sp, #0 + 800583e: 6078 str r0, [r7, #4] + /* Check the parameters */ + assert_param(IS_SUBGHZ_ALL_INSTANCE(SUBGHZSPI)); + + /* Disable SUBGHZSPI Peripheral */ + CLEAR_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + 8005840: 4b0c ldr r3, [pc, #48] ; (8005874 ) + 8005842: 681b ldr r3, [r3, #0] + 8005844: 4a0b ldr r2, [pc, #44] ; (8005874 ) + 8005846: f023 0340 bic.w r3, r3, #64 ; 0x40 + 800584a: 6013 str r3, [r2, #0] + * NSS management: Internal (Done with External bit inside PWR * + * Communication speed: BaudratePrescaler * + * First bit: MSB * + * CRC calculation: Disable * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR1, (SPI_CR1_MSTR | SPI_CR1_SSI | BaudratePrescaler | SPI_CR1_SSM)); + 800584c: 4a09 ldr r2, [pc, #36] ; (8005874 ) + 800584e: 687b ldr r3, [r7, #4] + 8005850: f443 7341 orr.w r3, r3, #772 ; 0x304 + 8005854: 6013 str r3, [r2, #0] + * Data Size: 8bits * + * TI Mode: Disable * + * NSS Pulse: Disable * + * Rx FIFO Threshold: 8bits * + *--------------------------------------------------------------------------*/ + WRITE_REG(SUBGHZSPI->CR2, (SPI_CR2_FRXTH | SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2)); + 8005856: 4b07 ldr r3, [pc, #28] ; (8005874 ) + 8005858: f44f 52b8 mov.w r2, #5888 ; 0x1700 + 800585c: 605a str r2, [r3, #4] + + /* Enable SUBGHZSPI Peripheral */ + SET_BIT(SUBGHZSPI->CR1, SPI_CR1_SPE); + 800585e: 4b05 ldr r3, [pc, #20] ; (8005874 ) + 8005860: 681b ldr r3, [r3, #0] + 8005862: 4a04 ldr r2, [pc, #16] ; (8005874 ) + 8005864: f043 0340 orr.w r3, r3, #64 ; 0x40 + 8005868: 6013 str r3, [r2, #0] +} + 800586a: bf00 nop + 800586c: 370c adds r7, #12 + 800586e: 46bd mov sp, r7 + 8005870: bc80 pop {r7} + 8005872: 4770 bx lr + 8005874: 58010000 .word 0x58010000 + +08005878 : + * @param Data data to transmit + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Transmit(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t Data) +{ + 8005878: b480 push {r7} + 800587a: b087 sub sp, #28 + 800587c: af00 add r7, sp, #0 + 800587e: 6078 str r0, [r7, #4] + 8005880: 460b mov r3, r1 + 8005882: 70fb strb r3, [r7, #3] + HAL_StatusTypeDef status = HAL_OK; + 8005884: 2300 movs r3, #0 + 8005886: 75fb strb r3, [r7, #23] + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8005888: 4b23 ldr r3, [pc, #140] ; (8005918 ) + 800588a: 681a ldr r2, [r3, #0] + 800588c: 4613 mov r3, r2 + 800588e: 00db lsls r3, r3, #3 + 8005890: 1a9b subs r3, r3, r2 + 8005892: 009b lsls r3, r3, #2 + 8005894: 0cdb lsrs r3, r3, #19 + 8005896: 2264 movs r2, #100 ; 0x64 + 8005898: fb02 f303 mul.w r3, r2, r3 + 800589c: 60fb str r3, [r7, #12] + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + 800589e: 68fb ldr r3, [r7, #12] + 80058a0: 2b00 cmp r3, #0 + 80058a2: d105 bne.n 80058b0 + { + status = HAL_ERROR; + 80058a4: 2301 movs r3, #1 + 80058a6: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 80058a8: 687b ldr r3, [r7, #4] + 80058aa: 2201 movs r2, #1 + 80058ac: 609a str r2, [r3, #8] + break; + 80058ae: e008 b.n 80058c2 + } + count--; + 80058b0: 68fb ldr r3, [r7, #12] + 80058b2: 3b01 subs r3, #1 + 80058b4: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + 80058b6: 4b19 ldr r3, [pc, #100] ; (800591c ) + 80058b8: 689b ldr r3, [r3, #8] + 80058ba: f003 0302 and.w r3, r3, #2 + 80058be: 2b02 cmp r3, #2 + 80058c0: d1ed bne.n 800589e + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + 80058c2: 4b17 ldr r3, [pc, #92] ; (8005920 ) + 80058c4: 613b str r3, [r7, #16] + *spidr = Data; + 80058c6: 693b ldr r3, [r7, #16] + 80058c8: 78fa ldrb r2, [r7, #3] + 80058ca: 701a strb r2, [r3, #0] + *((__IO uint8_t *)&SUBGHZSPI->DR) = Data; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 80058cc: 4b12 ldr r3, [pc, #72] ; (8005918 ) + 80058ce: 681a ldr r2, [r3, #0] + 80058d0: 4613 mov r3, r2 + 80058d2: 00db lsls r3, r3, #3 + 80058d4: 1a9b subs r3, r3, r2 + 80058d6: 009b lsls r3, r3, #2 + 80058d8: 0cdb lsrs r3, r3, #19 + 80058da: 2264 movs r2, #100 ; 0x64 + 80058dc: fb02 f303 mul.w r3, r2, r3 + 80058e0: 60fb str r3, [r7, #12] + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + 80058e2: 68fb ldr r3, [r7, #12] + 80058e4: 2b00 cmp r3, #0 + 80058e6: d105 bne.n 80058f4 + { + status = HAL_ERROR; + 80058e8: 2301 movs r3, #1 + 80058ea: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 80058ec: 687b ldr r3, [r7, #4] + 80058ee: 2201 movs r2, #1 + 80058f0: 609a str r2, [r3, #8] + break; + 80058f2: e008 b.n 8005906 + } + count--; + 80058f4: 68fb ldr r3, [r7, #12] + 80058f6: 3b01 subs r3, #1 + 80058f8: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + 80058fa: 4b08 ldr r3, [pc, #32] ; (800591c ) + 80058fc: 689b ldr r3, [r3, #8] + 80058fe: f003 0301 and.w r3, r3, #1 + 8005902: 2b01 cmp r3, #1 + 8005904: d1ed bne.n 80058e2 + + /* Flush Rx data */ + READ_REG(SUBGHZSPI->DR); + 8005906: 4b05 ldr r3, [pc, #20] ; (800591c ) + 8005908: 68db ldr r3, [r3, #12] + + return status; + 800590a: 7dfb ldrb r3, [r7, #23] +} + 800590c: 4618 mov r0, r3 + 800590e: 371c adds r7, #28 + 8005910: 46bd mov sp, r7 + 8005912: bc80 pop {r7} + 8005914: 4770 bx lr + 8005916: bf00 nop + 8005918: 20000000 .word 0x20000000 + 800591c: 58010000 .word 0x58010000 + 8005920: 5801000c .word 0x5801000c + +08005924 : + * @param pData pointer on data to receive + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZSPI_Receive(SUBGHZ_HandleTypeDef *hsubghz, + uint8_t *pData) +{ + 8005924: b480 push {r7} + 8005926: b087 sub sp, #28 + 8005928: af00 add r7, sp, #0 + 800592a: 6078 str r0, [r7, #4] + 800592c: 6039 str r1, [r7, #0] + HAL_StatusTypeDef status = HAL_OK; + 800592e: 2300 movs r3, #0 + 8005930: 75fb strb r3, [r7, #23] + __IO uint32_t count; + + /* Handle Tx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8005932: 4b25 ldr r3, [pc, #148] ; (80059c8 ) + 8005934: 681a ldr r2, [r3, #0] + 8005936: 4613 mov r3, r2 + 8005938: 00db lsls r3, r3, #3 + 800593a: 1a9b subs r3, r3, r2 + 800593c: 009b lsls r3, r3, #2 + 800593e: 0cdb lsrs r3, r3, #19 + 8005940: 2264 movs r2, #100 ; 0x64 + 8005942: fb02 f303 mul.w r3, r2, r3 + 8005946: 60fb str r3, [r7, #12] + + /* Wait until TXE flag is set */ + do + { + if (count == 0U) + 8005948: 68fb ldr r3, [r7, #12] + 800594a: 2b00 cmp r3, #0 + 800594c: d105 bne.n 800595a + { + status = HAL_ERROR; + 800594e: 2301 movs r3, #1 + 8005950: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8005952: 687b ldr r3, [r7, #4] + 8005954: 2201 movs r2, #1 + 8005956: 609a str r2, [r3, #8] + break; + 8005958: e008 b.n 800596c + } + count--; + 800595a: 68fb ldr r3, [r7, #12] + 800595c: 3b01 subs r3, #1 + 800595e: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_TXE) != (SPI_SR_TXE)); + 8005960: 4b1a ldr r3, [pc, #104] ; (80059cc ) + 8005962: 689b ldr r3, [r3, #8] + 8005964: f003 0302 and.w r3, r3, #2 + 8005968: 2b02 cmp r3, #2 + 800596a: d1ed bne.n 8005948 + + /* Transmit Data*/ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SUBGHZSPI->DR); + 800596c: 4b18 ldr r3, [pc, #96] ; (80059d0 ) + 800596e: 613b str r3, [r7, #16] + *spidr = SUBGHZ_DUMMY_DATA; + 8005970: 693b ldr r3, [r7, #16] + 8005972: 22ff movs r2, #255 ; 0xff + 8005974: 701a strb r2, [r3, #0] + *((__IO uint8_t *)&SUBGHZSPI->DR) = SUBGHZ_DUMMY_DATA; +#endif /* __GNUC__ */ + + /* Handle Rx transmission from SUBGHZSPI peripheral to Radio ****************/ + /* Initialize Timeout */ + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_DEFAULT_LOOP_TIME; + 8005976: 4b14 ldr r3, [pc, #80] ; (80059c8 ) + 8005978: 681a ldr r2, [r3, #0] + 800597a: 4613 mov r3, r2 + 800597c: 00db lsls r3, r3, #3 + 800597e: 1a9b subs r3, r3, r2 + 8005980: 009b lsls r3, r3, #2 + 8005982: 0cdb lsrs r3, r3, #19 + 8005984: 2264 movs r2, #100 ; 0x64 + 8005986: fb02 f303 mul.w r3, r2, r3 + 800598a: 60fb str r3, [r7, #12] + + /* Wait until RXNE flag is set */ + do + { + if (count == 0U) + 800598c: 68fb ldr r3, [r7, #12] + 800598e: 2b00 cmp r3, #0 + 8005990: d105 bne.n 800599e + { + status = HAL_ERROR; + 8005992: 2301 movs r3, #1 + 8005994: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_TIMEOUT; + 8005996: 687b ldr r3, [r7, #4] + 8005998: 2201 movs r2, #1 + 800599a: 609a str r2, [r3, #8] + break; + 800599c: e008 b.n 80059b0 + } + count--; + 800599e: 68fb ldr r3, [r7, #12] + 80059a0: 3b01 subs r3, #1 + 80059a2: 60fb str r3, [r7, #12] + } while (READ_BIT(SUBGHZSPI->SR, SPI_SR_RXNE) != (SPI_SR_RXNE)); + 80059a4: 4b09 ldr r3, [pc, #36] ; (80059cc ) + 80059a6: 689b ldr r3, [r3, #8] + 80059a8: f003 0301 and.w r3, r3, #1 + 80059ac: 2b01 cmp r3, #1 + 80059ae: d1ed bne.n 800598c + + /* Retrieve pData */ + *pData = (uint8_t)(READ_REG(SUBGHZSPI->DR)); + 80059b0: 4b06 ldr r3, [pc, #24] ; (80059cc ) + 80059b2: 68db ldr r3, [r3, #12] + 80059b4: b2da uxtb r2, r3 + 80059b6: 683b ldr r3, [r7, #0] + 80059b8: 701a strb r2, [r3, #0] + + return status; + 80059ba: 7dfb ldrb r3, [r7, #23] +} + 80059bc: 4618 mov r0, r3 + 80059be: 371c adds r7, #28 + 80059c0: 46bd mov sp, r7 + 80059c2: bc80 pop {r7} + 80059c4: 4770 bx lr + 80059c6: bf00 nop + 80059c8: 20000000 .word 0x20000000 + 80059cc: 58010000 .word 0x58010000 + 80059d0: 5801000c .word 0x5801000c + +080059d4 : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_CheckDeviceReady(SUBGHZ_HandleTypeDef *hsubghz) +{ + 80059d4: b580 push {r7, lr} + 80059d6: b084 sub sp, #16 + 80059d8: af00 add r7, sp, #0 + 80059da: 6078 str r0, [r7, #4] + __IO uint32_t count; + + /* Wakeup radio in case of sleep mode: Select-Unselect radio */ + if (hsubghz->DeepSleep == SUBGHZ_DEEP_SLEEP_ENABLE) + 80059dc: 687b ldr r3, [r7, #4] + 80059de: 791b ldrb r3, [r3, #4] + 80059e0: 2b01 cmp r3, #1 + 80059e2: d111 bne.n 8005a08 + { + /* Initialize NSS switch Delay */ + count = SUBGHZ_NSS_LOOP_TIME; + 80059e4: 4b0c ldr r3, [pc, #48] ; (8005a18 ) + 80059e6: 681a ldr r2, [r3, #0] + 80059e8: 4613 mov r3, r2 + 80059ea: 005b lsls r3, r3, #1 + 80059ec: 4413 add r3, r2 + 80059ee: 00db lsls r3, r3, #3 + 80059f0: 0c1b lsrs r3, r3, #16 + 80059f2: 60fb str r3, [r7, #12] + + /* NSS = 0; */ + LL_PWR_SelectSUBGHZSPI_NSS(); + 80059f4: f7ff fbaa bl 800514c + + /* Wait Radio wakeup */ + do + { + count--; + 80059f8: 68fb ldr r3, [r7, #12] + 80059fa: 3b01 subs r3, #1 + 80059fc: 60fb str r3, [r7, #12] + } while (count != 0UL); + 80059fe: 68fb ldr r3, [r7, #12] + 8005a00: 2b00 cmp r3, #0 + 8005a02: d1f9 bne.n 80059f8 + + /* NSS = 1 */ + LL_PWR_UnselectSUBGHZSPI_NSS(); + 8005a04: f7ff fb92 bl 800512c + } + return (SUBGHZ_WaitOnBusy(hsubghz)); + 8005a08: 6878 ldr r0, [r7, #4] + 8005a0a: f000 f807 bl 8005a1c + 8005a0e: 4603 mov r3, r0 +} + 8005a10: 4618 mov r0, r3 + 8005a12: 3710 adds r7, #16 + 8005a14: 46bd mov sp, r7 + 8005a16: bd80 pop {r7, pc} + 8005a18: 20000000 .word 0x20000000 + +08005a1c : + * @param hsubghz pointer to a SUBGHZ_HandleTypeDef structure that contains + * the handle information for SUBGHZ module. + * @retval HAL status + */ +HAL_StatusTypeDef SUBGHZ_WaitOnBusy(SUBGHZ_HandleTypeDef *hsubghz) +{ + 8005a1c: b580 push {r7, lr} + 8005a1e: b086 sub sp, #24 + 8005a20: af00 add r7, sp, #0 + 8005a22: 6078 str r0, [r7, #4] + HAL_StatusTypeDef status; + __IO uint32_t count; + uint32_t mask; + + status = HAL_OK; + 8005a24: 2300 movs r3, #0 + 8005a26: 75fb strb r3, [r7, #23] + count = SUBGHZ_DEFAULT_TIMEOUT * SUBGHZ_RFBUSY_LOOP_TIME; + 8005a28: 4b12 ldr r3, [pc, #72] ; (8005a74 ) + 8005a2a: 681a ldr r2, [r3, #0] + 8005a2c: 4613 mov r3, r2 + 8005a2e: 005b lsls r3, r3, #1 + 8005a30: 4413 add r3, r2 + 8005a32: 00db lsls r3, r3, #3 + 8005a34: 0d1b lsrs r3, r3, #20 + 8005a36: 2264 movs r2, #100 ; 0x64 + 8005a38: fb02 f303 mul.w r3, r2, r3 + 8005a3c: 60fb str r3, [r7, #12] + + /* Wait until Busy signal is set */ + do + { + mask = LL_PWR_IsActiveFlag_RFBUSYMS(); + 8005a3e: f7ff fbb3 bl 80051a8 + 8005a42: 6138 str r0, [r7, #16] + + if (count == 0U) + 8005a44: 68fb ldr r3, [r7, #12] + 8005a46: 2b00 cmp r3, #0 + 8005a48: d105 bne.n 8005a56 + { + status = HAL_ERROR; + 8005a4a: 2301 movs r3, #1 + 8005a4c: 75fb strb r3, [r7, #23] + hsubghz->ErrorCode = HAL_SUBGHZ_ERROR_RF_BUSY; + 8005a4e: 687b ldr r3, [r7, #4] + 8005a50: 2202 movs r2, #2 + 8005a52: 609a str r2, [r3, #8] + break; + 8005a54: e009 b.n 8005a6a + } + count--; + 8005a56: 68fb ldr r3, [r7, #12] + 8005a58: 3b01 subs r3, #1 + 8005a5a: 60fb str r3, [r7, #12] + } while ((LL_PWR_IsActiveFlag_RFBUSYS()& mask) == 1UL); + 8005a5c: f7ff fb92 bl 8005184 + 8005a60: 4602 mov r2, r0 + 8005a62: 693b ldr r3, [r7, #16] + 8005a64: 4013 ands r3, r2 + 8005a66: 2b01 cmp r3, #1 + 8005a68: d0e9 beq.n 8005a3e + + return status; + 8005a6a: 7dfb ldrb r3, [r7, #23] +} + 8005a6c: 4618 mov r0, r3 + 8005a6e: 3718 adds r7, #24 + 8005a70: 46bd mov sp, r7 + 8005a72: bd80 pop {r7, pc} + 8005a74: 20000000 .word 0x20000000 + +08005a78 : +{ + 8005a78: b480 push {r7} + 8005a7a: b083 sub sp, #12 + 8005a7c: af00 add r7, sp, #0 + 8005a7e: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RCC->CCIPR, USARTx) | (USARTx << 16)); + 8005a80: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8005a84: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 8005a88: 687b ldr r3, [r7, #4] + 8005a8a: 401a ands r2, r3 + 8005a8c: 687b ldr r3, [r7, #4] + 8005a8e: 041b lsls r3, r3, #16 + 8005a90: 4313 orrs r3, r2 +} + 8005a92: 4618 mov r0, r3 + 8005a94: 370c adds r7, #12 + 8005a96: 46bd mov sp, r7 + 8005a98: bc80 pop {r7} + 8005a9a: 4770 bx lr + +08005a9c : +{ + 8005a9c: b480 push {r7} + 8005a9e: b083 sub sp, #12 + 8005aa0: af00 add r7, sp, #0 + 8005aa2: 6078 str r0, [r7, #4] + return (uint32_t)(READ_BIT(RCC->CCIPR, LPUARTx)); + 8005aa4: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 8005aa8: f8d3 2088 ldr.w r2, [r3, #136] ; 0x88 + 8005aac: 687b ldr r3, [r7, #4] + 8005aae: 4013 ands r3, r2 +} + 8005ab0: 4618 mov r0, r3 + 8005ab2: 370c adds r7, #12 + 8005ab4: 46bd mov sp, r7 + 8005ab6: bc80 pop {r7} + 8005ab8: 4770 bx lr + +08005aba : + * parameters in the UART_InitTypeDef and initialize the associated handle. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) +{ + 8005aba: b580 push {r7, lr} + 8005abc: b082 sub sp, #8 + 8005abe: af00 add r7, sp, #0 + 8005ac0: 6078 str r0, [r7, #4] + /* Check the UART handle allocation */ + if (huart == NULL) + 8005ac2: 687b ldr r3, [r7, #4] + 8005ac4: 2b00 cmp r3, #0 + 8005ac6: d101 bne.n 8005acc + { + return HAL_ERROR; + 8005ac8: 2301 movs r3, #1 + 8005aca: e042 b.n 8005b52 + { + /* Check the parameters */ + assert_param((IS_UART_INSTANCE(huart->Instance)) || (IS_LPUART_INSTANCE(huart->Instance))); + } + + if (huart->gState == HAL_UART_STATE_RESET) + 8005acc: 687b ldr r3, [r7, #4] + 8005ace: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8005ad2: 2b00 cmp r3, #0 + 8005ad4: d106 bne.n 8005ae4 + { + /* Allocate lock resource and initialize it */ + huart->Lock = HAL_UNLOCKED; + 8005ad6: 687b ldr r3, [r7, #4] + 8005ad8: 2200 movs r2, #0 + 8005ada: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + /* Init the low level hardware */ + huart->MspInitCallback(huart); +#else + /* Init the low level hardware : GPIO, CLOCK */ + HAL_UART_MspInit(huart); + 8005ade: 6878 ldr r0, [r7, #4] + 8005ae0: f7fb fd64 bl 80015ac +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + + huart->gState = HAL_UART_STATE_BUSY; + 8005ae4: 687b ldr r3, [r7, #4] + 8005ae6: 2224 movs r2, #36 ; 0x24 + 8005ae8: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + __HAL_UART_DISABLE(huart); + 8005aec: 687b ldr r3, [r7, #4] + 8005aee: 681b ldr r3, [r3, #0] + 8005af0: 681a ldr r2, [r3, #0] + 8005af2: 687b ldr r3, [r7, #4] + 8005af4: 681b ldr r3, [r3, #0] + 8005af6: f022 0201 bic.w r2, r2, #1 + 8005afa: 601a str r2, [r3, #0] + + /* Set the UART Communication parameters */ + if (UART_SetConfig(huart) == HAL_ERROR) + 8005afc: 6878 ldr r0, [r7, #4] + 8005afe: f000 fcff bl 8006500 + 8005b02: 4603 mov r3, r0 + 8005b04: 2b01 cmp r3, #1 + 8005b06: d101 bne.n 8005b0c + { + return HAL_ERROR; + 8005b08: 2301 movs r3, #1 + 8005b0a: e022 b.n 8005b52 + } + + if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT) + 8005b0c: 687b ldr r3, [r7, #4] + 8005b0e: 6a9b ldr r3, [r3, #40] ; 0x28 + 8005b10: 2b00 cmp r3, #0 + 8005b12: d002 beq.n 8005b1a + { + UART_AdvFeatureConfig(huart); + 8005b14: 6878 ldr r0, [r7, #4] + 8005b16: f000 ff67 bl 80069e8 + } + + /* In asynchronous mode, the following bits must be kept cleared: + - LINEN and CLKEN bits in the USART_CR2 register, + - SCEN, HDSEL and IREN bits in the USART_CR3 register.*/ + CLEAR_BIT(huart->Instance->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); + 8005b1a: 687b ldr r3, [r7, #4] + 8005b1c: 681b ldr r3, [r3, #0] + 8005b1e: 685a ldr r2, [r3, #4] + 8005b20: 687b ldr r3, [r7, #4] + 8005b22: 681b ldr r3, [r3, #0] + 8005b24: f422 4290 bic.w r2, r2, #18432 ; 0x4800 + 8005b28: 605a str r2, [r3, #4] + CLEAR_BIT(huart->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); + 8005b2a: 687b ldr r3, [r7, #4] + 8005b2c: 681b ldr r3, [r3, #0] + 8005b2e: 689a ldr r2, [r3, #8] + 8005b30: 687b ldr r3, [r7, #4] + 8005b32: 681b ldr r3, [r3, #0] + 8005b34: f022 022a bic.w r2, r2, #42 ; 0x2a + 8005b38: 609a str r2, [r3, #8] + + __HAL_UART_ENABLE(huart); + 8005b3a: 687b ldr r3, [r7, #4] + 8005b3c: 681b ldr r3, [r3, #0] + 8005b3e: 681a ldr r2, [r3, #0] + 8005b40: 687b ldr r3, [r7, #4] + 8005b42: 681b ldr r3, [r3, #0] + 8005b44: f042 0201 orr.w r2, r2, #1 + 8005b48: 601a str r2, [r3, #0] + + /* TEACK and/or REACK to check before moving huart->gState and huart->RxState to Ready */ + return (UART_CheckIdleState(huart)); + 8005b4a: 6878 ldr r0, [r7, #4] + 8005b4c: f000 ffed bl 8006b2a + 8005b50: 4603 mov r3, r0 +} + 8005b52: 4618 mov r0, r3 + 8005b54: 3708 adds r7, #8 + 8005b56: 46bd mov sp, r7 + 8005b58: bd80 pop {r7, pc} + +08005b5a : + * @param Size Amount of data elements (u8 or u16) to be received. + * @param Timeout Timeout duration. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) +{ + 8005b5a: b580 push {r7, lr} + 8005b5c: b08a sub sp, #40 ; 0x28 + 8005b5e: af02 add r7, sp, #8 + 8005b60: 60f8 str r0, [r7, #12] + 8005b62: 60b9 str r1, [r7, #8] + 8005b64: 603b str r3, [r7, #0] + 8005b66: 4613 mov r3, r2 + 8005b68: 80fb strh r3, [r7, #6] + uint16_t *pdata16bits; + uint16_t uhMask; + uint32_t tickstart; + + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 8005b6a: 68fb ldr r3, [r7, #12] + 8005b6c: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8005b70: 2b20 cmp r3, #32 + 8005b72: f040 80b1 bne.w 8005cd8 + { + if ((pData == NULL) || (Size == 0U)) + 8005b76: 68bb ldr r3, [r7, #8] + 8005b78: 2b00 cmp r3, #0 + 8005b7a: d002 beq.n 8005b82 + 8005b7c: 88fb ldrh r3, [r7, #6] + 8005b7e: 2b00 cmp r3, #0 + 8005b80: d101 bne.n 8005b86 + { + return HAL_ERROR; + 8005b82: 2301 movs r3, #1 + 8005b84: e0a9 b.n 8005cda + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005b86: 68fb ldr r3, [r7, #12] + 8005b88: 2200 movs r2, #0 + 8005b8a: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8005b8e: 68fb ldr r3, [r7, #12] + 8005b90: 2222 movs r2, #34 ; 0x22 + 8005b92: f8c3 208c str.w r2, [r3, #140] ; 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005b96: 68fb ldr r3, [r7, #12] + 8005b98: 2200 movs r2, #0 + 8005b9a: 66da str r2, [r3, #108] ; 0x6c + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8005b9c: f7fb f8be bl 8000d1c + 8005ba0: 6178 str r0, [r7, #20] + + huart->RxXferSize = Size; + 8005ba2: 68fb ldr r3, [r7, #12] + 8005ba4: 88fa ldrh r2, [r7, #6] + 8005ba6: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + huart->RxXferCount = Size; + 8005baa: 68fb ldr r3, [r7, #12] + 8005bac: 88fa ldrh r2, [r7, #6] + 8005bae: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 8005bb2: 68fb ldr r3, [r7, #12] + 8005bb4: 689b ldr r3, [r3, #8] + 8005bb6: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8005bba: d10e bne.n 8005bda + 8005bbc: 68fb ldr r3, [r7, #12] + 8005bbe: 691b ldr r3, [r3, #16] + 8005bc0: 2b00 cmp r3, #0 + 8005bc2: d105 bne.n 8005bd0 + 8005bc4: 68fb ldr r3, [r7, #12] + 8005bc6: f240 12ff movw r2, #511 ; 0x1ff + 8005bca: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8005bce: e02d b.n 8005c2c + 8005bd0: 68fb ldr r3, [r7, #12] + 8005bd2: 22ff movs r2, #255 ; 0xff + 8005bd4: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8005bd8: e028 b.n 8005c2c + 8005bda: 68fb ldr r3, [r7, #12] + 8005bdc: 689b ldr r3, [r3, #8] + 8005bde: 2b00 cmp r3, #0 + 8005be0: d10d bne.n 8005bfe + 8005be2: 68fb ldr r3, [r7, #12] + 8005be4: 691b ldr r3, [r3, #16] + 8005be6: 2b00 cmp r3, #0 + 8005be8: d104 bne.n 8005bf4 + 8005bea: 68fb ldr r3, [r7, #12] + 8005bec: 22ff movs r2, #255 ; 0xff + 8005bee: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8005bf2: e01b b.n 8005c2c + 8005bf4: 68fb ldr r3, [r7, #12] + 8005bf6: 227f movs r2, #127 ; 0x7f + 8005bf8: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8005bfc: e016 b.n 8005c2c + 8005bfe: 68fb ldr r3, [r7, #12] + 8005c00: 689b ldr r3, [r3, #8] + 8005c02: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 8005c06: d10d bne.n 8005c24 + 8005c08: 68fb ldr r3, [r7, #12] + 8005c0a: 691b ldr r3, [r3, #16] + 8005c0c: 2b00 cmp r3, #0 + 8005c0e: d104 bne.n 8005c1a + 8005c10: 68fb ldr r3, [r7, #12] + 8005c12: 227f movs r2, #127 ; 0x7f + 8005c14: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8005c18: e008 b.n 8005c2c + 8005c1a: 68fb ldr r3, [r7, #12] + 8005c1c: 223f movs r2, #63 ; 0x3f + 8005c1e: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8005c22: e003 b.n 8005c2c + 8005c24: 68fb ldr r3, [r7, #12] + 8005c26: 2200 movs r2, #0 + 8005c28: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + uhMask = huart->Mask; + 8005c2c: 68fb ldr r3, [r7, #12] + 8005c2e: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8005c32: 827b strh r3, [r7, #18] + + /* In case of 9bits/No Parity transfer, pRxData needs to be handled as a uint16_t pointer */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8005c34: 68fb ldr r3, [r7, #12] + 8005c36: 689b ldr r3, [r3, #8] + 8005c38: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8005c3c: d108 bne.n 8005c50 + 8005c3e: 68fb ldr r3, [r7, #12] + 8005c40: 691b ldr r3, [r3, #16] + 8005c42: 2b00 cmp r3, #0 + 8005c44: d104 bne.n 8005c50 + { + pdata8bits = NULL; + 8005c46: 2300 movs r3, #0 + 8005c48: 61fb str r3, [r7, #28] + pdata16bits = (uint16_t *) pData; + 8005c4a: 68bb ldr r3, [r7, #8] + 8005c4c: 61bb str r3, [r7, #24] + 8005c4e: e003 b.n 8005c58 + } + else + { + pdata8bits = pData; + 8005c50: 68bb ldr r3, [r7, #8] + 8005c52: 61fb str r3, [r7, #28] + pdata16bits = NULL; + 8005c54: 2300 movs r3, #0 + 8005c56: 61bb str r3, [r7, #24] + } + + /* as long as data have to be received */ + while (huart->RxXferCount > 0U) + 8005c58: e032 b.n 8005cc0 + { + if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, tickstart, Timeout) != HAL_OK) + 8005c5a: 683b ldr r3, [r7, #0] + 8005c5c: 9300 str r3, [sp, #0] + 8005c5e: 697b ldr r3, [r7, #20] + 8005c60: 2200 movs r2, #0 + 8005c62: 2120 movs r1, #32 + 8005c64: 68f8 ldr r0, [r7, #12] + 8005c66: f000 ffae bl 8006bc6 + 8005c6a: 4603 mov r3, r0 + 8005c6c: 2b00 cmp r3, #0 + 8005c6e: d001 beq.n 8005c74 + { + return HAL_TIMEOUT; + 8005c70: 2303 movs r3, #3 + 8005c72: e032 b.n 8005cda + } + if (pdata8bits == NULL) + 8005c74: 69fb ldr r3, [r7, #28] + 8005c76: 2b00 cmp r3, #0 + 8005c78: d10c bne.n 8005c94 + { + *pdata16bits = (uint16_t)(huart->Instance->RDR & uhMask); + 8005c7a: 68fb ldr r3, [r7, #12] + 8005c7c: 681b ldr r3, [r3, #0] + 8005c7e: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005c80: b29a uxth r2, r3 + 8005c82: 8a7b ldrh r3, [r7, #18] + 8005c84: 4013 ands r3, r2 + 8005c86: b29a uxth r2, r3 + 8005c88: 69bb ldr r3, [r7, #24] + 8005c8a: 801a strh r2, [r3, #0] + pdata16bits++; + 8005c8c: 69bb ldr r3, [r7, #24] + 8005c8e: 3302 adds r3, #2 + 8005c90: 61bb str r3, [r7, #24] + 8005c92: e00c b.n 8005cae + } + else + { + *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); + 8005c94: 68fb ldr r3, [r7, #12] + 8005c96: 681b ldr r3, [r3, #0] + 8005c98: 6a5b ldr r3, [r3, #36] ; 0x24 + 8005c9a: b2da uxtb r2, r3 + 8005c9c: 8a7b ldrh r3, [r7, #18] + 8005c9e: b2db uxtb r3, r3 + 8005ca0: 4013 ands r3, r2 + 8005ca2: b2da uxtb r2, r3 + 8005ca4: 69fb ldr r3, [r7, #28] + 8005ca6: 701a strb r2, [r3, #0] + pdata8bits++; + 8005ca8: 69fb ldr r3, [r7, #28] + 8005caa: 3301 adds r3, #1 + 8005cac: 61fb str r3, [r7, #28] + } + huart->RxXferCount--; + 8005cae: 68fb ldr r3, [r7, #12] + 8005cb0: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8005cb4: b29b uxth r3, r3 + 8005cb6: 3b01 subs r3, #1 + 8005cb8: b29a uxth r2, r3 + 8005cba: 68fb ldr r3, [r7, #12] + 8005cbc: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + while (huart->RxXferCount > 0U) + 8005cc0: 68fb ldr r3, [r7, #12] + 8005cc2: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8005cc6: b29b uxth r3, r3 + 8005cc8: 2b00 cmp r3, #0 + 8005cca: d1c6 bne.n 8005c5a + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8005ccc: 68fb ldr r3, [r7, #12] + 8005cce: 2220 movs r2, #32 + 8005cd0: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + return HAL_OK; + 8005cd4: 2300 movs r3, #0 + 8005cd6: e000 b.n 8005cda + } + else + { + return HAL_BUSY; + 8005cd8: 2302 movs r3, #2 + } +} + 8005cda: 4618 mov r0, r3 + 8005cdc: 3720 adds r7, #32 + 8005cde: 46bd mov sp, r7 + 8005ce0: bd80 pop {r7, pc} + ... + +08005ce4 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8005ce4: b580 push {r7, lr} + 8005ce6: b08a sub sp, #40 ; 0x28 + 8005ce8: af00 add r7, sp, #0 + 8005cea: 60f8 str r0, [r7, #12] + 8005cec: 60b9 str r1, [r7, #8] + 8005cee: 4613 mov r3, r2 + 8005cf0: 80fb strh r3, [r7, #6] + /* Check that a Rx process is not already ongoing */ + if (huart->RxState == HAL_UART_STATE_READY) + 8005cf2: 68fb ldr r3, [r7, #12] + 8005cf4: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8005cf8: 2b20 cmp r3, #32 + 8005cfa: d137 bne.n 8005d6c + { + if ((pData == NULL) || (Size == 0U)) + 8005cfc: 68bb ldr r3, [r7, #8] + 8005cfe: 2b00 cmp r3, #0 + 8005d00: d002 beq.n 8005d08 + 8005d02: 88fb ldrh r3, [r7, #6] + 8005d04: 2b00 cmp r3, #0 + 8005d06: d101 bne.n 8005d0c + { + return HAL_ERROR; + 8005d08: 2301 movs r3, #1 + 8005d0a: e030 b.n 8005d6e + } + } + +#endif /* CORE_CM0PLUS */ + /* Set Reception type to Standard reception */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8005d0c: 68fb ldr r3, [r7, #12] + 8005d0e: 2200 movs r2, #0 + 8005d10: 66da str r2, [r3, #108] ; 0x6c + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8005d12: 68fb ldr r3, [r7, #12] + 8005d14: 681b ldr r3, [r3, #0] + 8005d16: 4a18 ldr r2, [pc, #96] ; (8005d78 ) + 8005d18: 4293 cmp r3, r2 + 8005d1a: d01f beq.n 8005d5c + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8005d1c: 68fb ldr r3, [r7, #12] + 8005d1e: 681b ldr r3, [r3, #0] + 8005d20: 685b ldr r3, [r3, #4] + 8005d22: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8005d26: 2b00 cmp r3, #0 + 8005d28: d018 beq.n 8005d5c + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8005d2a: 68fb ldr r3, [r7, #12] + 8005d2c: 681b ldr r3, [r3, #0] + 8005d2e: 617b str r3, [r7, #20] + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005d30: 697b ldr r3, [r7, #20] + 8005d32: e853 3f00 ldrex r3, [r3] + 8005d36: 613b str r3, [r7, #16] + return(result); + 8005d38: 693b ldr r3, [r7, #16] + 8005d3a: f043 6380 orr.w r3, r3, #67108864 ; 0x4000000 + 8005d3e: 627b str r3, [r7, #36] ; 0x24 + 8005d40: 68fb ldr r3, [r7, #12] + 8005d42: 681b ldr r3, [r3, #0] + 8005d44: 461a mov r2, r3 + 8005d46: 6a7b ldr r3, [r7, #36] ; 0x24 + 8005d48: 623b str r3, [r7, #32] + 8005d4a: 61fa str r2, [r7, #28] + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005d4c: 69f9 ldr r1, [r7, #28] + 8005d4e: 6a3a ldr r2, [r7, #32] + 8005d50: e841 2300 strex r3, r2, [r1] + 8005d54: 61bb str r3, [r7, #24] + return(result); + 8005d56: 69bb ldr r3, [r7, #24] + 8005d58: 2b00 cmp r3, #0 + 8005d5a: d1e6 bne.n 8005d2a + } + } + + return (UART_Start_Receive_IT(huart, pData, Size)); + 8005d5c: 88fb ldrh r3, [r7, #6] + 8005d5e: 461a mov r2, r3 + 8005d60: 68b9 ldr r1, [r7, #8] + 8005d62: 68f8 ldr r0, [r7, #12] + 8005d64: f000 fff8 bl 8006d58 + 8005d68: 4603 mov r3, r0 + 8005d6a: e000 b.n 8005d6e + } + else + { + return HAL_BUSY; + 8005d6c: 2302 movs r3, #2 + } +} + 8005d6e: 4618 mov r0, r3 + 8005d70: 3728 adds r7, #40 ; 0x28 + 8005d72: 46bd mov sp, r7 + 8005d74: bd80 pop {r7, pc} + 8005d76: bf00 nop + 8005d78: 40008000 .word 0x40008000 + +08005d7c : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be sent. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, const uint8_t *pData, uint16_t Size) +{ + 8005d7c: b580 push {r7, lr} + 8005d7e: b08a sub sp, #40 ; 0x28 + 8005d80: af00 add r7, sp, #0 + 8005d82: 60f8 str r0, [r7, #12] + 8005d84: 60b9 str r1, [r7, #8] + 8005d86: 4613 mov r3, r2 + 8005d88: 80fb strh r3, [r7, #6] + /* Check that a Tx process is not already ongoing */ + if (huart->gState == HAL_UART_STATE_READY) + 8005d8a: 68fb ldr r3, [r7, #12] + 8005d8c: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 8005d90: 2b20 cmp r3, #32 + 8005d92: d167 bne.n 8005e64 + { + if ((pData == NULL) || (Size == 0U)) + 8005d94: 68bb ldr r3, [r7, #8] + 8005d96: 2b00 cmp r3, #0 + 8005d98: d002 beq.n 8005da0 + 8005d9a: 88fb ldrh r3, [r7, #6] + 8005d9c: 2b00 cmp r3, #0 + 8005d9e: d101 bne.n 8005da4 + { + return HAL_ERROR; + 8005da0: 2301 movs r3, #1 + 8005da2: e060 b.n 8005e66 + return HAL_ERROR; + } + } + +#endif /* CORE_CM0PLUS */ + huart->pTxBuffPtr = pData; + 8005da4: 68fb ldr r3, [r7, #12] + 8005da6: 68ba ldr r2, [r7, #8] + 8005da8: 651a str r2, [r3, #80] ; 0x50 + huart->TxXferSize = Size; + 8005daa: 68fb ldr r3, [r7, #12] + 8005dac: 88fa ldrh r2, [r7, #6] + 8005dae: f8a3 2054 strh.w r2, [r3, #84] ; 0x54 + huart->TxXferCount = Size; + 8005db2: 68fb ldr r3, [r7, #12] + 8005db4: 88fa ldrh r2, [r7, #6] + 8005db6: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8005dba: 68fb ldr r3, [r7, #12] + 8005dbc: 2200 movs r2, #0 + 8005dbe: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + huart->gState = HAL_UART_STATE_BUSY_TX; + 8005dc2: 68fb ldr r3, [r7, #12] + 8005dc4: 2221 movs r2, #33 ; 0x21 + 8005dc6: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + if (huart->hdmatx != NULL) + 8005dca: 68fb ldr r3, [r7, #12] + 8005dcc: 6fdb ldr r3, [r3, #124] ; 0x7c + 8005dce: 2b00 cmp r3, #0 + 8005dd0: d028 beq.n 8005e24 + { + /* Set the UART DMA transfer complete callback */ + huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt; + 8005dd2: 68fb ldr r3, [r7, #12] + 8005dd4: 6fdb ldr r3, [r3, #124] ; 0x7c + 8005dd6: 4a26 ldr r2, [pc, #152] ; (8005e70 ) + 8005dd8: 62da str r2, [r3, #44] ; 0x2c + + /* Set the UART DMA Half transfer complete callback */ + huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt; + 8005dda: 68fb ldr r3, [r7, #12] + 8005ddc: 6fdb ldr r3, [r3, #124] ; 0x7c + 8005dde: 4a25 ldr r2, [pc, #148] ; (8005e74 ) + 8005de0: 631a str r2, [r3, #48] ; 0x30 + + /* Set the DMA error callback */ + huart->hdmatx->XferErrorCallback = UART_DMAError; + 8005de2: 68fb ldr r3, [r7, #12] + 8005de4: 6fdb ldr r3, [r3, #124] ; 0x7c + 8005de6: 4a24 ldr r2, [pc, #144] ; (8005e78 ) + 8005de8: 635a str r2, [r3, #52] ; 0x34 + + /* Set the DMA abort callback */ + huart->hdmatx->XferAbortCallback = NULL; + 8005dea: 68fb ldr r3, [r7, #12] + 8005dec: 6fdb ldr r3, [r3, #124] ; 0x7c + 8005dee: 2200 movs r2, #0 + 8005df0: 639a str r2, [r3, #56] ; 0x38 + + /* Enable the UART transmit DMA channel */ + if (HAL_DMA_Start_IT(huart->hdmatx, (uint32_t)huart->pTxBuffPtr, (uint32_t)&huart->Instance->TDR, Size) != HAL_OK) + 8005df2: 68fb ldr r3, [r7, #12] + 8005df4: 6fd8 ldr r0, [r3, #124] ; 0x7c + 8005df6: 68fb ldr r3, [r7, #12] + 8005df8: 6d1b ldr r3, [r3, #80] ; 0x50 + 8005dfa: 4619 mov r1, r3 + 8005dfc: 68fb ldr r3, [r7, #12] + 8005dfe: 681b ldr r3, [r3, #0] + 8005e00: 3328 adds r3, #40 ; 0x28 + 8005e02: 461a mov r2, r3 + 8005e04: 88fb ldrh r3, [r7, #6] + 8005e06: f7fc fc7d bl 8002704 + 8005e0a: 4603 mov r3, r0 + 8005e0c: 2b00 cmp r3, #0 + 8005e0e: d009 beq.n 8005e24 + { + /* Set error code to DMA */ + huart->ErrorCode = HAL_UART_ERROR_DMA; + 8005e10: 68fb ldr r3, [r7, #12] + 8005e12: 2210 movs r2, #16 + 8005e14: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + + /* Restore huart->gState to ready */ + huart->gState = HAL_UART_STATE_READY; + 8005e18: 68fb ldr r3, [r7, #12] + 8005e1a: 2220 movs r2, #32 + 8005e1c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + return HAL_ERROR; + 8005e20: 2301 movs r3, #1 + 8005e22: e020 b.n 8005e66 + } + } + /* Clear the TC flag in the ICR register */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_TCF); + 8005e24: 68fb ldr r3, [r7, #12] + 8005e26: 681b ldr r3, [r3, #0] + 8005e28: 2240 movs r2, #64 ; 0x40 + 8005e2a: 621a str r2, [r3, #32] + + /* Enable the DMA transfer for transmit request by setting the DMAT bit + in the UART CR3 register */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 8005e2c: 68fb ldr r3, [r7, #12] + 8005e2e: 681b ldr r3, [r3, #0] + 8005e30: 3308 adds r3, #8 + 8005e32: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8005e34: 697b ldr r3, [r7, #20] + 8005e36: e853 3f00 ldrex r3, [r3] + 8005e3a: 613b str r3, [r7, #16] + return(result); + 8005e3c: 693b ldr r3, [r7, #16] + 8005e3e: f043 0380 orr.w r3, r3, #128 ; 0x80 + 8005e42: 627b str r3, [r7, #36] ; 0x24 + 8005e44: 68fb ldr r3, [r7, #12] + 8005e46: 681b ldr r3, [r3, #0] + 8005e48: 3308 adds r3, #8 + 8005e4a: 6a7a ldr r2, [r7, #36] ; 0x24 + 8005e4c: 623a str r2, [r7, #32] + 8005e4e: 61fb str r3, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8005e50: 69f9 ldr r1, [r7, #28] + 8005e52: 6a3a ldr r2, [r7, #32] + 8005e54: e841 2300 strex r3, r2, [r1] + 8005e58: 61bb str r3, [r7, #24] + return(result); + 8005e5a: 69bb ldr r3, [r7, #24] + 8005e5c: 2b00 cmp r3, #0 + 8005e5e: d1e5 bne.n 8005e2c + + return HAL_OK; + 8005e60: 2300 movs r3, #0 + 8005e62: e000 b.n 8005e66 + } + else + { + return HAL_BUSY; + 8005e64: 2302 movs r3, #2 + } +} + 8005e66: 4618 mov r0, r3 + 8005e68: 3728 adds r7, #40 ; 0x28 + 8005e6a: 46bd mov sp, r7 + 8005e6c: bd80 pop {r7, pc} + 8005e6e: bf00 nop + 8005e70: 080070e3 .word 0x080070e3 + 8005e74: 0800717d .word 0x0800717d + 8005e78: 08007199 .word 0x08007199 + +08005e7c : + * @brief Handle UART interrupt request. + * @param huart UART handle. + * @retval None + */ +void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) +{ + 8005e7c: b580 push {r7, lr} + 8005e7e: b0ba sub sp, #232 ; 0xe8 + 8005e80: af00 add r7, sp, #0 + 8005e82: 6078 str r0, [r7, #4] + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 8005e84: 687b ldr r3, [r7, #4] + 8005e86: 681b ldr r3, [r3, #0] + 8005e88: 69db ldr r3, [r3, #28] + 8005e8a: f8c7 30e4 str.w r3, [r7, #228] ; 0xe4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8005e8e: 687b ldr r3, [r7, #4] + 8005e90: 681b ldr r3, [r3, #0] + 8005e92: 681b ldr r3, [r3, #0] + 8005e94: f8c7 30e0 str.w r3, [r7, #224] ; 0xe0 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8005e98: 687b ldr r3, [r7, #4] + 8005e9a: 681b ldr r3, [r3, #0] + 8005e9c: 689b ldr r3, [r3, #8] + 8005e9e: f8c7 30dc str.w r3, [r7, #220] ; 0xdc + + uint32_t errorflags; + uint32_t errorcode; + + /* If no error occurs */ + errorflags = (isrflags & (uint32_t)(USART_ISR_PE | USART_ISR_FE | USART_ISR_ORE | USART_ISR_NE | USART_ISR_RTOF)); + 8005ea2: f8d7 20e4 ldr.w r2, [r7, #228] ; 0xe4 + 8005ea6: f640 030f movw r3, #2063 ; 0x80f + 8005eaa: 4013 ands r3, r2 + 8005eac: f8c7 30d8 str.w r3, [r7, #216] ; 0xd8 + if (errorflags == 0U) + 8005eb0: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 8005eb4: 2b00 cmp r3, #0 + 8005eb6: d11b bne.n 8005ef0 + { + /* UART in mode Receiver ---------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + 8005eb8: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8005ebc: f003 0320 and.w r3, r3, #32 + 8005ec0: 2b00 cmp r3, #0 + 8005ec2: d015 beq.n 8005ef0 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 8005ec4: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 8005ec8: f003 0320 and.w r3, r3, #32 + 8005ecc: 2b00 cmp r3, #0 + 8005ece: d105 bne.n 8005edc + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 8005ed0: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 8005ed4: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 8005ed8: 2b00 cmp r3, #0 + 8005eda: d009 beq.n 8005ef0 + { + if (huart->RxISR != NULL) + 8005edc: 687b ldr r3, [r7, #4] + 8005ede: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005ee0: 2b00 cmp r3, #0 + 8005ee2: f000 82e3 beq.w 80064ac + { + huart->RxISR(huart); + 8005ee6: 687b ldr r3, [r7, #4] + 8005ee8: 6f5b ldr r3, [r3, #116] ; 0x74 + 8005eea: 6878 ldr r0, [r7, #4] + 8005eec: 4798 blx r3 + } + return; + 8005eee: e2dd b.n 80064ac + } + } + + /* If some errors occur */ + if ((errorflags != 0U) + 8005ef0: f8d7 30d8 ldr.w r3, [r7, #216] ; 0xd8 + 8005ef4: 2b00 cmp r3, #0 + 8005ef6: f000 8123 beq.w 8006140 + && ((((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U) + 8005efa: f8d7 20dc ldr.w r2, [r7, #220] ; 0xdc + 8005efe: 4b8d ldr r3, [pc, #564] ; (8006134 ) + 8005f00: 4013 ands r3, r2 + 8005f02: 2b00 cmp r3, #0 + 8005f04: d106 bne.n 8005f14 + || ((cr1its & (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | USART_CR1_RTOIE)) != 0U)))) + 8005f06: f8d7 20e0 ldr.w r2, [r7, #224] ; 0xe0 + 8005f0a: 4b8b ldr r3, [pc, #556] ; (8006138 ) + 8005f0c: 4013 ands r3, r2 + 8005f0e: 2b00 cmp r3, #0 + 8005f10: f000 8116 beq.w 8006140 + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8005f14: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8005f18: f003 0301 and.w r3, r3, #1 + 8005f1c: 2b00 cmp r3, #0 + 8005f1e: d011 beq.n 8005f44 + 8005f20: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 8005f24: f403 7380 and.w r3, r3, #256 ; 0x100 + 8005f28: 2b00 cmp r3, #0 + 8005f2a: d00b beq.n 8005f44 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8005f2c: 687b ldr r3, [r7, #4] + 8005f2e: 681b ldr r3, [r3, #0] + 8005f30: 2201 movs r2, #1 + 8005f32: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8005f34: 687b ldr r3, [r7, #4] + 8005f36: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8005f3a: f043 0201 orr.w r2, r3, #1 + 8005f3e: 687b ldr r3, [r7, #4] + 8005f40: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8005f44: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8005f48: f003 0302 and.w r3, r3, #2 + 8005f4c: 2b00 cmp r3, #0 + 8005f4e: d011 beq.n 8005f74 + 8005f50: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 8005f54: f003 0301 and.w r3, r3, #1 + 8005f58: 2b00 cmp r3, #0 + 8005f5a: d00b beq.n 8005f74 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8005f5c: 687b ldr r3, [r7, #4] + 8005f5e: 681b ldr r3, [r3, #0] + 8005f60: 2202 movs r2, #2 + 8005f62: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8005f64: 687b ldr r3, [r7, #4] + 8005f66: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8005f6a: f043 0204 orr.w r2, r3, #4 + 8005f6e: 687b ldr r3, [r7, #4] + 8005f70: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8005f74: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8005f78: f003 0304 and.w r3, r3, #4 + 8005f7c: 2b00 cmp r3, #0 + 8005f7e: d011 beq.n 8005fa4 + 8005f80: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 8005f84: f003 0301 and.w r3, r3, #1 + 8005f88: 2b00 cmp r3, #0 + 8005f8a: d00b beq.n 8005fa4 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8005f8c: 687b ldr r3, [r7, #4] + 8005f8e: 681b ldr r3, [r3, #0] + 8005f90: 2204 movs r2, #4 + 8005f92: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8005f94: 687b ldr r3, [r7, #4] + 8005f96: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8005f9a: f043 0202 orr.w r2, r3, #2 + 8005f9e: 687b ldr r3, [r7, #4] + 8005fa0: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART Over-Run interrupt occurred -----------------------------------------*/ + if (((isrflags & USART_ISR_ORE) != 0U) + 8005fa4: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8005fa8: f003 0308 and.w r3, r3, #8 + 8005fac: 2b00 cmp r3, #0 + 8005fae: d017 beq.n 8005fe0 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 8005fb0: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 8005fb4: f003 0320 and.w r3, r3, #32 + 8005fb8: 2b00 cmp r3, #0 + 8005fba: d105 bne.n 8005fc8 + ((cr3its & (USART_CR3_RXFTIE | USART_CR3_EIE)) != 0U))) + 8005fbc: f8d7 20dc ldr.w r2, [r7, #220] ; 0xdc + 8005fc0: 4b5c ldr r3, [pc, #368] ; (8006134 ) + 8005fc2: 4013 ands r3, r2 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) || + 8005fc4: 2b00 cmp r3, #0 + 8005fc6: d00b beq.n 8005fe0 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF); + 8005fc8: 687b ldr r3, [r7, #4] + 8005fca: 681b ldr r3, [r3, #0] + 8005fcc: 2208 movs r2, #8 + 8005fce: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_ORE; + 8005fd0: 687b ldr r3, [r7, #4] + 8005fd2: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8005fd6: f043 0208 orr.w r2, r3, #8 + 8005fda: 687b ldr r3, [r7, #4] + 8005fdc: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART Receiver Timeout interrupt occurred ---------------------------------*/ + if (((isrflags & USART_ISR_RTOF) != 0U) && ((cr1its & USART_CR1_RTOIE) != 0U)) + 8005fe0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8005fe4: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8005fe8: 2b00 cmp r3, #0 + 8005fea: d012 beq.n 8006012 + 8005fec: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 8005ff0: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 8005ff4: 2b00 cmp r3, #0 + 8005ff6: d00c beq.n 8006012 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8005ff8: 687b ldr r3, [r7, #4] + 8005ffa: 681b ldr r3, [r3, #0] + 8005ffc: f44f 6200 mov.w r2, #2048 ; 0x800 + 8006000: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_RTO; + 8006002: 687b ldr r3, [r7, #4] + 8006004: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006008: f043 0220 orr.w r2, r3, #32 + 800600c: 687b ldr r3, [r7, #4] + 800600e: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8006012: 687b ldr r3, [r7, #4] + 8006014: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006018: 2b00 cmp r3, #0 + 800601a: f000 8249 beq.w 80064b0 + { + /* UART in mode Receiver --------------------------------------------------*/ + if (((isrflags & USART_ISR_RXNE_RXFNE) != 0U) + 800601e: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8006022: f003 0320 and.w r3, r3, #32 + 8006026: 2b00 cmp r3, #0 + 8006028: d013 beq.n 8006052 + && (((cr1its & USART_CR1_RXNEIE_RXFNEIE) != 0U) + 800602a: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800602e: f003 0320 and.w r3, r3, #32 + 8006032: 2b00 cmp r3, #0 + 8006034: d105 bne.n 8006042 + || ((cr3its & USART_CR3_RXFTIE) != 0U))) + 8006036: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 800603a: f003 5380 and.w r3, r3, #268435456 ; 0x10000000 + 800603e: 2b00 cmp r3, #0 + 8006040: d007 beq.n 8006052 + { + if (huart->RxISR != NULL) + 8006042: 687b ldr r3, [r7, #4] + 8006044: 6f5b ldr r3, [r3, #116] ; 0x74 + 8006046: 2b00 cmp r3, #0 + 8006048: d003 beq.n 8006052 + { + huart->RxISR(huart); + 800604a: 687b ldr r3, [r7, #4] + 800604c: 6f5b ldr r3, [r3, #116] ; 0x74 + 800604e: 6878 ldr r0, [r7, #4] + 8006050: 4798 blx r3 + /* If Error is to be considered as blocking : + - Receiver Timeout error in Reception + - Overrun error in Reception + - any error occurs in DMA mode reception + */ + errorcode = huart->ErrorCode; + 8006052: 687b ldr r3, [r7, #4] + 8006054: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8006058: f8c7 30d4 str.w r3, [r7, #212] ; 0xd4 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 800605c: 687b ldr r3, [r7, #4] + 800605e: 681b ldr r3, [r3, #0] + 8006060: 689b ldr r3, [r3, #8] + 8006062: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006066: 2b40 cmp r3, #64 ; 0x40 + 8006068: d005 beq.n 8006076 + ((errorcode & (HAL_UART_ERROR_RTO | HAL_UART_ERROR_ORE)) != 0U)) + 800606a: f8d7 30d4 ldr.w r3, [r7, #212] ; 0xd4 + 800606e: f003 0328 and.w r3, r3, #40 ; 0x28 + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) || + 8006072: 2b00 cmp r3, #0 + 8006074: d054 beq.n 8006120 + { + /* Blocking error : transfer is aborted + Set the UART state ready to be able to start again the process, + Disable Rx Interrupts, and disable Rx DMA request, if ongoing */ + UART_EndRxTransfer(huart); + 8006076: 6878 ldr r0, [r7, #4] + 8006078: f000 ffce bl 8007018 + + /* Abort the UART DMA Rx channel if enabled */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800607c: 687b ldr r3, [r7, #4] + 800607e: 681b ldr r3, [r3, #0] + 8006080: 689b ldr r3, [r3, #8] + 8006082: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006086: 2b40 cmp r3, #64 ; 0x40 + 8006088: d146 bne.n 8006118 + { + /* Disable the UART DMA Rx request if enabled */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 800608a: 687b ldr r3, [r7, #4] + 800608c: 681b ldr r3, [r3, #0] + 800608e: 3308 adds r3, #8 + 8006090: f8c7 309c str.w r3, [r7, #156] ; 0x9c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006094: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 8006098: e853 3f00 ldrex r3, [r3] + 800609c: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + return(result); + 80060a0: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 80060a4: f023 0340 bic.w r3, r3, #64 ; 0x40 + 80060a8: f8c7 30d0 str.w r3, [r7, #208] ; 0xd0 + 80060ac: 687b ldr r3, [r7, #4] + 80060ae: 681b ldr r3, [r3, #0] + 80060b0: 3308 adds r3, #8 + 80060b2: f8d7 20d0 ldr.w r2, [r7, #208] ; 0xd0 + 80060b6: f8c7 20a8 str.w r2, [r7, #168] ; 0xa8 + 80060ba: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80060be: f8d7 10a4 ldr.w r1, [r7, #164] ; 0xa4 + 80060c2: f8d7 20a8 ldr.w r2, [r7, #168] ; 0xa8 + 80060c6: e841 2300 strex r3, r2, [r1] + 80060ca: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + return(result); + 80060ce: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 80060d2: 2b00 cmp r3, #0 + 80060d4: d1d9 bne.n 800608a + + /* Abort the UART DMA Rx channel */ + if (huart->hdmarx != NULL) + 80060d6: 687b ldr r3, [r7, #4] + 80060d8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80060dc: 2b00 cmp r3, #0 + 80060de: d017 beq.n 8006110 + { + /* Set the UART DMA Abort callback : + will lead to call HAL_UART_ErrorCallback() at end of DMA abort procedure */ + huart->hdmarx->XferAbortCallback = UART_DMAAbortOnError; + 80060e0: 687b ldr r3, [r7, #4] + 80060e2: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80060e6: 4a15 ldr r2, [pc, #84] ; (800613c ) + 80060e8: 639a str r2, [r3, #56] ; 0x38 + + /* Abort DMA RX */ + if (HAL_DMA_Abort_IT(huart->hdmarx) != HAL_OK) + 80060ea: 687b ldr r3, [r7, #4] + 80060ec: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80060f0: 4618 mov r0, r3 + 80060f2: f7fc fbe3 bl 80028bc + 80060f6: 4603 mov r3, r0 + 80060f8: 2b00 cmp r3, #0 + 80060fa: d019 beq.n 8006130 + { + /* Call Directly huart->hdmarx->XferAbortCallback function in case of error */ + huart->hdmarx->XferAbortCallback(huart->hdmarx); + 80060fc: 687b ldr r3, [r7, #4] + 80060fe: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8006102: 6b9b ldr r3, [r3, #56] ; 0x38 + 8006104: 687a ldr r2, [r7, #4] + 8006106: f8d2 2080 ldr.w r2, [r2, #128] ; 0x80 + 800610a: 4610 mov r0, r2 + 800610c: 4798 blx r3 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800610e: e00f b.n 8006130 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006110: 6878 ldr r0, [r7, #4] + 8006112: f000 f9e0 bl 80064d6 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8006116: e00b b.n 8006130 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006118: 6878 ldr r0, [r7, #4] + 800611a: f000 f9dc bl 80064d6 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800611e: e007 b.n 8006130 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8006120: 6878 ldr r0, [r7, #4] + 8006122: f000 f9d8 bl 80064d6 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006126: 687b ldr r3, [r7, #4] + 8006128: 2200 movs r2, #0 + 800612a: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + } + return; + 800612e: e1bf b.n 80064b0 + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 8006130: bf00 nop + return; + 8006132: e1bd b.n 80064b0 + 8006134: 10000001 .word 0x10000001 + 8006138: 04000120 .word 0x04000120 + 800613c: 08007219 .word 0x08007219 + + } /* End if some error occurs */ + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if ((huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8006140: 687b ldr r3, [r7, #4] + 8006142: 6edb ldr r3, [r3, #108] ; 0x6c + 8006144: 2b01 cmp r3, #1 + 8006146: f040 8153 bne.w 80063f0 + && ((isrflags & USART_ISR_IDLE) != 0U) + 800614a: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800614e: f003 0310 and.w r3, r3, #16 + 8006152: 2b00 cmp r3, #0 + 8006154: f000 814c beq.w 80063f0 + && ((cr1its & USART_ISR_IDLE) != 0U)) + 8006158: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800615c: f003 0310 and.w r3, r3, #16 + 8006160: 2b00 cmp r3, #0 + 8006162: f000 8145 beq.w 80063f0 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8006166: 687b ldr r3, [r7, #4] + 8006168: 681b ldr r3, [r3, #0] + 800616a: 2210 movs r2, #16 + 800616c: 621a str r2, [r3, #32] + + /* Check if DMA mode is enabled in UART */ + if (HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) + 800616e: 687b ldr r3, [r7, #4] + 8006170: 681b ldr r3, [r3, #0] + 8006172: 689b ldr r3, [r3, #8] + 8006174: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006178: 2b40 cmp r3, #64 ; 0x40 + 800617a: f040 80bb bne.w 80062f4 + { + /* DMA mode enabled */ + /* Check received length : If all expected data are received, do nothing, + (DMA cplt callback will be called). + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(huart->hdmarx); + 800617e: 687b ldr r3, [r7, #4] + 8006180: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 8006184: 681b ldr r3, [r3, #0] + 8006186: 685b ldr r3, [r3, #4] + 8006188: f8a7 30be strh.w r3, [r7, #190] ; 0xbe + if ((nb_remaining_rx_data > 0U) + 800618c: f8b7 30be ldrh.w r3, [r7, #190] ; 0xbe + 8006190: 2b00 cmp r3, #0 + 8006192: f000 818f beq.w 80064b4 + && (nb_remaining_rx_data < huart->RxXferSize)) + 8006196: 687b ldr r3, [r7, #4] + 8006198: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 800619c: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe + 80061a0: 429a cmp r2, r3 + 80061a2: f080 8187 bcs.w 80064b4 + { + /* Reception is not complete */ + huart->RxXferCount = nb_remaining_rx_data; + 80061a6: 687b ldr r3, [r7, #4] + 80061a8: f8b7 20be ldrh.w r2, [r7, #190] ; 0xbe + 80061ac: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + + /* In Normal mode, end DMA xfer and HAL UART Rx process*/ + if (HAL_IS_BIT_CLR(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + 80061b0: 687b ldr r3, [r7, #4] + 80061b2: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80061b6: 681b ldr r3, [r3, #0] + 80061b8: 681b ldr r3, [r3, #0] + 80061ba: f003 0320 and.w r3, r3, #32 + 80061be: 2b00 cmp r3, #0 + 80061c0: f040 8087 bne.w 80062d2 + { + /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 80061c4: 687b ldr r3, [r7, #4] + 80061c6: 681b ldr r3, [r3, #0] + 80061c8: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80061cc: f8d7 3088 ldr.w r3, [r7, #136] ; 0x88 + 80061d0: e853 3f00 ldrex r3, [r3] + 80061d4: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + return(result); + 80061d8: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 80061dc: f423 7380 bic.w r3, r3, #256 ; 0x100 + 80061e0: f8c7 30b8 str.w r3, [r7, #184] ; 0xb8 + 80061e4: 687b ldr r3, [r7, #4] + 80061e6: 681b ldr r3, [r3, #0] + 80061e8: 461a mov r2, r3 + 80061ea: f8d7 30b8 ldr.w r3, [r7, #184] ; 0xb8 + 80061ee: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 80061f2: f8c7 2090 str.w r2, [r7, #144] ; 0x90 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80061f6: f8d7 1090 ldr.w r1, [r7, #144] ; 0x90 + 80061fa: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94 + 80061fe: e841 2300 strex r3, r2, [r1] + 8006202: f8c7 308c str.w r3, [r7, #140] ; 0x8c + return(result); + 8006206: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 800620a: 2b00 cmp r3, #0 + 800620c: d1da bne.n 80061c4 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 800620e: 687b ldr r3, [r7, #4] + 8006210: 681b ldr r3, [r3, #0] + 8006212: 3308 adds r3, #8 + 8006214: 677b str r3, [r7, #116] ; 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006216: 6f7b ldr r3, [r7, #116] ; 0x74 + 8006218: e853 3f00 ldrex r3, [r3] + 800621c: 673b str r3, [r7, #112] ; 0x70 + return(result); + 800621e: 6f3b ldr r3, [r7, #112] ; 0x70 + 8006220: f023 0301 bic.w r3, r3, #1 + 8006224: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + 8006228: 687b ldr r3, [r7, #4] + 800622a: 681b ldr r3, [r3, #0] + 800622c: 3308 adds r3, #8 + 800622e: f8d7 20b4 ldr.w r2, [r7, #180] ; 0xb4 + 8006232: f8c7 2080 str.w r2, [r7, #128] ; 0x80 + 8006236: 67fb str r3, [r7, #124] ; 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006238: 6ff9 ldr r1, [r7, #124] ; 0x7c + 800623a: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80 + 800623e: e841 2300 strex r3, r2, [r1] + 8006242: 67bb str r3, [r7, #120] ; 0x78 + return(result); + 8006244: 6fbb ldr r3, [r7, #120] ; 0x78 + 8006246: 2b00 cmp r3, #0 + 8006248: d1e1 bne.n 800620e + + /* Disable the DMA transfer for the receiver request by resetting the DMAR bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAR); + 800624a: 687b ldr r3, [r7, #4] + 800624c: 681b ldr r3, [r3, #0] + 800624e: 3308 adds r3, #8 + 8006250: 663b str r3, [r7, #96] ; 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006252: 6e3b ldr r3, [r7, #96] ; 0x60 + 8006254: e853 3f00 ldrex r3, [r3] + 8006258: 65fb str r3, [r7, #92] ; 0x5c + return(result); + 800625a: 6dfb ldr r3, [r7, #92] ; 0x5c + 800625c: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8006260: f8c7 30b0 str.w r3, [r7, #176] ; 0xb0 + 8006264: 687b ldr r3, [r7, #4] + 8006266: 681b ldr r3, [r3, #0] + 8006268: 3308 adds r3, #8 + 800626a: f8d7 20b0 ldr.w r2, [r7, #176] ; 0xb0 + 800626e: 66fa str r2, [r7, #108] ; 0x6c + 8006270: 66bb str r3, [r7, #104] ; 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006272: 6eb9 ldr r1, [r7, #104] ; 0x68 + 8006274: 6efa ldr r2, [r7, #108] ; 0x6c + 8006276: e841 2300 strex r3, r2, [r1] + 800627a: 667b str r3, [r7, #100] ; 0x64 + return(result); + 800627c: 6e7b ldr r3, [r7, #100] ; 0x64 + 800627e: 2b00 cmp r3, #0 + 8006280: d1e3 bne.n 800624a + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006282: 687b ldr r3, [r7, #4] + 8006284: 2220 movs r2, #32 + 8006286: f8c3 208c str.w r2, [r3, #140] ; 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 800628a: 687b ldr r3, [r7, #4] + 800628c: 2200 movs r2, #0 + 800628e: 66da str r2, [r3, #108] ; 0x6c + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8006290: 687b ldr r3, [r7, #4] + 8006292: 681b ldr r3, [r3, #0] + 8006294: 64fb str r3, [r7, #76] ; 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006296: 6cfb ldr r3, [r7, #76] ; 0x4c + 8006298: e853 3f00 ldrex r3, [r3] + 800629c: 64bb str r3, [r7, #72] ; 0x48 + return(result); + 800629e: 6cbb ldr r3, [r7, #72] ; 0x48 + 80062a0: f023 0310 bic.w r3, r3, #16 + 80062a4: f8c7 30ac str.w r3, [r7, #172] ; 0xac + 80062a8: 687b ldr r3, [r7, #4] + 80062aa: 681b ldr r3, [r3, #0] + 80062ac: 461a mov r2, r3 + 80062ae: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 80062b2: 65bb str r3, [r7, #88] ; 0x58 + 80062b4: 657a str r2, [r7, #84] ; 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80062b6: 6d79 ldr r1, [r7, #84] ; 0x54 + 80062b8: 6dba ldr r2, [r7, #88] ; 0x58 + 80062ba: e841 2300 strex r3, r2, [r1] + 80062be: 653b str r3, [r7, #80] ; 0x50 + return(result); + 80062c0: 6d3b ldr r3, [r7, #80] ; 0x50 + 80062c2: 2b00 cmp r3, #0 + 80062c4: d1e4 bne.n 8006290 + + /* Last bytes received, so no need as the abort is immediate */ + (void)HAL_DMA_Abort(huart->hdmarx); + 80062c6: 687b ldr r3, [r7, #4] + 80062c8: f8d3 3080 ldr.w r3, [r3, #128] ; 0x80 + 80062cc: 4618 mov r0, r3 + 80062ce: f7fc fa97 bl 8002800 + } + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 80062d2: 687b ldr r3, [r7, #4] + 80062d4: 2202 movs r2, #2 + 80062d6: 671a str r2, [r3, #112] ; 0x70 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); + 80062d8: 687b ldr r3, [r7, #4] + 80062da: f8b3 205c ldrh.w r2, [r3, #92] ; 0x5c + 80062de: 687b ldr r3, [r7, #4] + 80062e0: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80062e4: b29b uxth r3, r3 + 80062e6: 1ad3 subs r3, r2, r3 + 80062e8: b29b uxth r3, r3 + 80062ea: 4619 mov r1, r3 + 80062ec: 6878 ldr r0, [r7, #4] + 80062ee: f000 f8fb bl 80064e8 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + 80062f2: e0df b.n 80064b4 + else + { + /* DMA mode not enabled */ + /* Check received length : If all expected data are received, do nothing. + Otherwise, if at least one data has already been received, IDLE event is to be notified to user */ + uint16_t nb_rx_data = huart->RxXferSize - huart->RxXferCount; + 80062f4: 687b ldr r3, [r7, #4] + 80062f6: f8b3 205c ldrh.w r2, [r3, #92] ; 0x5c + 80062fa: 687b ldr r3, [r7, #4] + 80062fc: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8006300: b29b uxth r3, r3 + 8006302: 1ad3 subs r3, r2, r3 + 8006304: f8a7 30ce strh.w r3, [r7, #206] ; 0xce + if ((huart->RxXferCount > 0U) + 8006308: 687b ldr r3, [r7, #4] + 800630a: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 800630e: b29b uxth r3, r3 + 8006310: 2b00 cmp r3, #0 + 8006312: f000 80d1 beq.w 80064b8 + && (nb_rx_data > 0U)) + 8006316: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce + 800631a: 2b00 cmp r3, #0 + 800631c: f000 80cc beq.w 80064b8 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8006320: 687b ldr r3, [r7, #4] + 8006322: 681b ldr r3, [r3, #0] + 8006324: 63bb str r3, [r7, #56] ; 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006326: 6bbb ldr r3, [r7, #56] ; 0x38 + 8006328: e853 3f00 ldrex r3, [r3] + 800632c: 637b str r3, [r7, #52] ; 0x34 + return(result); + 800632e: 6b7b ldr r3, [r7, #52] ; 0x34 + 8006330: f423 7390 bic.w r3, r3, #288 ; 0x120 + 8006334: f8c7 30c8 str.w r3, [r7, #200] ; 0xc8 + 8006338: 687b ldr r3, [r7, #4] + 800633a: 681b ldr r3, [r3, #0] + 800633c: 461a mov r2, r3 + 800633e: f8d7 30c8 ldr.w r3, [r7, #200] ; 0xc8 + 8006342: 647b str r3, [r7, #68] ; 0x44 + 8006344: 643a str r2, [r7, #64] ; 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006346: 6c39 ldr r1, [r7, #64] ; 0x40 + 8006348: 6c7a ldr r2, [r7, #68] ; 0x44 + 800634a: e841 2300 strex r3, r2, [r1] + 800634e: 63fb str r3, [r7, #60] ; 0x3c + return(result); + 8006350: 6bfb ldr r3, [r7, #60] ; 0x3c + 8006352: 2b00 cmp r3, #0 + 8006354: d1e4 bne.n 8006320 + + /* Disable the UART Error Interrupt:(Frame error, noise error, overrun error) and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8006356: 687b ldr r3, [r7, #4] + 8006358: 681b ldr r3, [r3, #0] + 800635a: 3308 adds r3, #8 + 800635c: 627b str r3, [r7, #36] ; 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800635e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006360: e853 3f00 ldrex r3, [r3] + 8006364: 623b str r3, [r7, #32] + return(result); + 8006366: 6a3b ldr r3, [r7, #32] + 8006368: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 800636c: f023 0301 bic.w r3, r3, #1 + 8006370: f8c7 30c4 str.w r3, [r7, #196] ; 0xc4 + 8006374: 687b ldr r3, [r7, #4] + 8006376: 681b ldr r3, [r3, #0] + 8006378: 3308 adds r3, #8 + 800637a: f8d7 20c4 ldr.w r2, [r7, #196] ; 0xc4 + 800637e: 633a str r2, [r7, #48] ; 0x30 + 8006380: 62fb str r3, [r7, #44] ; 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006382: 6af9 ldr r1, [r7, #44] ; 0x2c + 8006384: 6b3a ldr r2, [r7, #48] ; 0x30 + 8006386: e841 2300 strex r3, r2, [r1] + 800638a: 62bb str r3, [r7, #40] ; 0x28 + return(result); + 800638c: 6abb ldr r3, [r7, #40] ; 0x28 + 800638e: 2b00 cmp r3, #0 + 8006390: d1e1 bne.n 8006356 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8006392: 687b ldr r3, [r7, #4] + 8006394: 2220 movs r2, #32 + 8006396: f8c3 208c str.w r2, [r3, #140] ; 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 800639a: 687b ldr r3, [r7, #4] + 800639c: 2200 movs r2, #0 + 800639e: 66da str r2, [r3, #108] ; 0x6c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 80063a0: 687b ldr r3, [r7, #4] + 80063a2: 2200 movs r2, #0 + 80063a4: 675a str r2, [r3, #116] ; 0x74 + + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80063a6: 687b ldr r3, [r7, #4] + 80063a8: 681b ldr r3, [r3, #0] + 80063aa: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80063ac: 693b ldr r3, [r7, #16] + 80063ae: e853 3f00 ldrex r3, [r3] + 80063b2: 60fb str r3, [r7, #12] + return(result); + 80063b4: 68fb ldr r3, [r7, #12] + 80063b6: f023 0310 bic.w r3, r3, #16 + 80063ba: f8c7 30c0 str.w r3, [r7, #192] ; 0xc0 + 80063be: 687b ldr r3, [r7, #4] + 80063c0: 681b ldr r3, [r3, #0] + 80063c2: 461a mov r2, r3 + 80063c4: f8d7 30c0 ldr.w r3, [r7, #192] ; 0xc0 + 80063c8: 61fb str r3, [r7, #28] + 80063ca: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80063cc: 69b9 ldr r1, [r7, #24] + 80063ce: 69fa ldr r2, [r7, #28] + 80063d0: e841 2300 strex r3, r2, [r1] + 80063d4: 617b str r3, [r7, #20] + return(result); + 80063d6: 697b ldr r3, [r7, #20] + 80063d8: 2b00 cmp r3, #0 + 80063da: d1e4 bne.n 80063a6 + + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + 80063dc: 687b ldr r3, [r7, #4] + 80063de: 2202 movs r2, #2 + 80063e0: 671a str r2, [r3, #112] ; 0x70 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxEventCallback(huart, nb_rx_data); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, nb_rx_data); + 80063e2: f8b7 30ce ldrh.w r3, [r7, #206] ; 0xce + 80063e6: 4619 mov r1, r3 + 80063e8: 6878 ldr r0, [r7, #4] + 80063ea: f000 f87d bl 80064e8 +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + return; + 80063ee: e063 b.n 80064b8 + } + } + + /* UART wakeup from Stop mode interrupt occurred ---------------------------*/ + if (((isrflags & USART_ISR_WUF) != 0U) && ((cr3its & USART_CR3_WUFIE) != 0U)) + 80063f0: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 80063f4: f403 1380 and.w r3, r3, #1048576 ; 0x100000 + 80063f8: 2b00 cmp r3, #0 + 80063fa: d00e beq.n 800641a + 80063fc: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 8006400: f403 0380 and.w r3, r3, #4194304 ; 0x400000 + 8006404: 2b00 cmp r3, #0 + 8006406: d008 beq.n 800641a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_WUF); + 8006408: 687b ldr r3, [r7, #4] + 800640a: 681b ldr r3, [r3, #0] + 800640c: f44f 1280 mov.w r2, #1048576 ; 0x100000 + 8006410: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Wakeup Callback */ + huart->WakeupCallback(huart); +#else + /* Call legacy weak Wakeup Callback */ + HAL_UARTEx_WakeupCallback(huart); + 8006412: 6878 ldr r0, [r7, #4] + 8006414: f001 fc5e bl 8007cd4 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 8006418: e051 b.n 80064be + } + + /* UART in mode Transmitter ------------------------------------------------*/ + if (((isrflags & USART_ISR_TXE_TXFNF) != 0U) + 800641a: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 800641e: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006422: 2b00 cmp r3, #0 + 8006424: d014 beq.n 8006450 + && (((cr1its & USART_CR1_TXEIE_TXFNFIE) != 0U) + 8006426: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 800642a: f003 0380 and.w r3, r3, #128 ; 0x80 + 800642e: 2b00 cmp r3, #0 + 8006430: d105 bne.n 800643e + || ((cr3its & USART_CR3_TXFTIE) != 0U))) + 8006432: f8d7 30dc ldr.w r3, [r7, #220] ; 0xdc + 8006436: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 800643a: 2b00 cmp r3, #0 + 800643c: d008 beq.n 8006450 + { + if (huart->TxISR != NULL) + 800643e: 687b ldr r3, [r7, #4] + 8006440: 6f9b ldr r3, [r3, #120] ; 0x78 + 8006442: 2b00 cmp r3, #0 + 8006444: d03a beq.n 80064bc + { + huart->TxISR(huart); + 8006446: 687b ldr r3, [r7, #4] + 8006448: 6f9b ldr r3, [r3, #120] ; 0x78 + 800644a: 6878 ldr r0, [r7, #4] + 800644c: 4798 blx r3 + } + return; + 800644e: e035 b.n 80064bc + } + + /* UART in mode Transmitter (transmission end) -----------------------------*/ + if (((isrflags & USART_ISR_TC) != 0U) && ((cr1its & USART_CR1_TCIE) != 0U)) + 8006450: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8006454: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006458: 2b00 cmp r3, #0 + 800645a: d009 beq.n 8006470 + 800645c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 8006460: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006464: 2b00 cmp r3, #0 + 8006466: d003 beq.n 8006470 + { + UART_EndTransmit_IT(huart); + 8006468: 6878 ldr r0, [r7, #4] + 800646a: f000 feeb bl 8007244 + return; + 800646e: e026 b.n 80064be + } + + /* UART TX Fifo Empty occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_TXFE) != 0U) && ((cr1its & USART_CR1_TXFEIE) != 0U)) + 8006470: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8006474: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8006478: 2b00 cmp r3, #0 + 800647a: d009 beq.n 8006490 + 800647c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 8006480: f003 4380 and.w r3, r3, #1073741824 ; 0x40000000 + 8006484: 2b00 cmp r3, #0 + 8006486: d003 beq.n 8006490 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Tx Fifo Empty Callback */ + huart->TxFifoEmptyCallback(huart); +#else + /* Call legacy weak Tx Fifo Empty Callback */ + HAL_UARTEx_TxFifoEmptyCallback(huart); + 8006488: 6878 ldr r0, [r7, #4] + 800648a: f001 fc35 bl 8007cf8 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 800648e: e016 b.n 80064be + } + + /* UART RX Fifo Full occurred ----------------------------------------------*/ + if (((isrflags & USART_ISR_RXFF) != 0U) && ((cr1its & USART_CR1_RXFFIE) != 0U)) + 8006490: f8d7 30e4 ldr.w r3, [r7, #228] ; 0xe4 + 8006494: f003 7380 and.w r3, r3, #16777216 ; 0x1000000 + 8006498: 2b00 cmp r3, #0 + 800649a: d010 beq.n 80064be + 800649c: f8d7 30e0 ldr.w r3, [r7, #224] ; 0xe0 + 80064a0: 2b00 cmp r3, #0 + 80064a2: da0c bge.n 80064be +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /* Call registered Rx Fifo Full Callback */ + huart->RxFifoFullCallback(huart); +#else + /* Call legacy weak Rx Fifo Full Callback */ + HAL_UARTEx_RxFifoFullCallback(huart); + 80064a4: 6878 ldr r0, [r7, #4] + 80064a6: f001 fc1e bl 8007ce6 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + return; + 80064aa: e008 b.n 80064be + return; + 80064ac: bf00 nop + 80064ae: e006 b.n 80064be + return; + 80064b0: bf00 nop + 80064b2: e004 b.n 80064be + return; + 80064b4: bf00 nop + 80064b6: e002 b.n 80064be + return; + 80064b8: bf00 nop + 80064ba: e000 b.n 80064be + return; + 80064bc: bf00 nop + } +} + 80064be: 37e8 adds r7, #232 ; 0xe8 + 80064c0: 46bd mov sp, r7 + 80064c2: bd80 pop {r7, pc} + +080064c4 : + * @brief Tx Half Transfer completed callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) +{ + 80064c4: b480 push {r7} + 80064c6: b083 sub sp, #12 + 80064c8: af00 add r7, sp, #0 + 80064ca: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE: This function should not be modified, when the callback is needed, + the HAL_UART_TxHalfCpltCallback can be implemented in the user file. + */ +} + 80064cc: bf00 nop + 80064ce: 370c adds r7, #12 + 80064d0: 46bd mov sp, r7 + 80064d2: bc80 pop {r7} + 80064d4: 4770 bx lr + +080064d6 : + * @brief UART error callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) +{ + 80064d6: b480 push {r7} + 80064d8: b083 sub sp, #12 + 80064da: af00 add r7, sp, #0 + 80064dc: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UART_ErrorCallback can be implemented in the user file. + */ +} + 80064de: bf00 nop + 80064e0: 370c adds r7, #12 + 80064e2: 46bd mov sp, r7 + 80064e4: bc80 pop {r7} + 80064e6: 4770 bx lr + +080064e8 : + * @param Size Number of data available in application reception buffer (indicates a position in + * reception buffer until which, data are available) + * @retval None + */ +__weak void HAL_UARTEx_RxEventCallback(UART_HandleTypeDef *huart, uint16_t Size) +{ + 80064e8: b480 push {r7} + 80064ea: b083 sub sp, #12 + 80064ec: af00 add r7, sp, #0 + 80064ee: 6078 str r0, [r7, #4] + 80064f0: 460b mov r3, r1 + 80064f2: 807b strh r3, [r7, #2] + UNUSED(Size); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxEventCallback can be implemented in the user file. + */ +} + 80064f4: bf00 nop + 80064f6: 370c adds r7, #12 + 80064f8: 46bd mov sp, r7 + 80064fa: bc80 pop {r7} + 80064fc: 4770 bx lr + ... + +08006500 : + * @brief Configure the UART peripheral. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) +{ + 8006500: e92d 4fb0 stmdb sp!, {r4, r5, r7, r8, r9, sl, fp, lr} + 8006504: b08c sub sp, #48 ; 0x30 + 8006506: af00 add r7, sp, #0 + 8006508: 6178 str r0, [r7, #20] + uint32_t tmpreg; + uint16_t brrtemp; + UART_ClockSourceTypeDef clocksource; + uint32_t usartdiv; + HAL_StatusTypeDef ret = HAL_OK; + 800650a: 2300 movs r3, #0 + 800650c: f887 302a strb.w r3, [r7, #42] ; 0x2a + * the UART Word Length, Parity, Mode and oversampling: + * set the M bits according to huart->Init.WordLength value + * set PCE and PS bits according to huart->Init.Parity value + * set TE and RE bits according to huart->Init.Mode value + * set OVER8 bit according to huart->Init.OverSampling value */ + tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling ; + 8006510: 697b ldr r3, [r7, #20] + 8006512: 689a ldr r2, [r3, #8] + 8006514: 697b ldr r3, [r7, #20] + 8006516: 691b ldr r3, [r3, #16] + 8006518: 431a orrs r2, r3 + 800651a: 697b ldr r3, [r7, #20] + 800651c: 695b ldr r3, [r3, #20] + 800651e: 431a orrs r2, r3 + 8006520: 697b ldr r3, [r7, #20] + 8006522: 69db ldr r3, [r3, #28] + 8006524: 4313 orrs r3, r2 + 8006526: 62fb str r3, [r7, #44] ; 0x2c + MODIFY_REG(huart->Instance->CR1, USART_CR1_FIELDS, tmpreg); + 8006528: 697b ldr r3, [r7, #20] + 800652a: 681b ldr r3, [r3, #0] + 800652c: 681a ldr r2, [r3, #0] + 800652e: 4b94 ldr r3, [pc, #592] ; (8006780 ) + 8006530: 4013 ands r3, r2 + 8006532: 697a ldr r2, [r7, #20] + 8006534: 6812 ldr r2, [r2, #0] + 8006536: 6af9 ldr r1, [r7, #44] ; 0x2c + 8006538: 430b orrs r3, r1 + 800653a: 6013 str r3, [r2, #0] + + /*-------------------------- USART CR2 Configuration -----------------------*/ + /* Configure the UART Stop Bits: Set STOP[13:12] bits according + * to huart->Init.StopBits value */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits); + 800653c: 697b ldr r3, [r7, #20] + 800653e: 681b ldr r3, [r3, #0] + 8006540: 685b ldr r3, [r3, #4] + 8006542: f423 5140 bic.w r1, r3, #12288 ; 0x3000 + 8006546: 697b ldr r3, [r7, #20] + 8006548: 68da ldr r2, [r3, #12] + 800654a: 697b ldr r3, [r7, #20] + 800654c: 681b ldr r3, [r3, #0] + 800654e: 430a orrs r2, r1 + 8006550: 605a str r2, [r3, #4] + /* Configure + * - UART HardWare Flow Control: set CTSE and RTSE bits according + * to huart->Init.HwFlowCtl value + * - one-bit sampling method versus three samples' majority rule according + * to huart->Init.OneBitSampling (not applicable to LPUART) */ + tmpreg = (uint32_t)huart->Init.HwFlowCtl; + 8006552: 697b ldr r3, [r7, #20] + 8006554: 699b ldr r3, [r3, #24] + 8006556: 62fb str r3, [r7, #44] ; 0x2c + + if (!(UART_INSTANCE_LOWPOWER(huart))) + 8006558: 697b ldr r3, [r7, #20] + 800655a: 681b ldr r3, [r3, #0] + 800655c: 4a89 ldr r2, [pc, #548] ; (8006784 ) + 800655e: 4293 cmp r3, r2 + 8006560: d004 beq.n 800656c + { + tmpreg |= huart->Init.OneBitSampling; + 8006562: 697b ldr r3, [r7, #20] + 8006564: 6a1b ldr r3, [r3, #32] + 8006566: 6afa ldr r2, [r7, #44] ; 0x2c + 8006568: 4313 orrs r3, r2 + 800656a: 62fb str r3, [r7, #44] ; 0x2c + } + MODIFY_REG(huart->Instance->CR3, USART_CR3_FIELDS, tmpreg); + 800656c: 697b ldr r3, [r7, #20] + 800656e: 681b ldr r3, [r3, #0] + 8006570: 689b ldr r3, [r3, #8] + 8006572: f023 436e bic.w r3, r3, #3992977408 ; 0xee000000 + 8006576: f423 6330 bic.w r3, r3, #2816 ; 0xb00 + 800657a: 697a ldr r2, [r7, #20] + 800657c: 6812 ldr r2, [r2, #0] + 800657e: 6af9 ldr r1, [r7, #44] ; 0x2c + 8006580: 430b orrs r3, r1 + 8006582: 6093 str r3, [r2, #8] + + /*-------------------------- USART PRESC Configuration -----------------------*/ + /* Configure + * - UART Clock Prescaler : set PRESCALER according to huart->Init.ClockPrescaler value */ + MODIFY_REG(huart->Instance->PRESC, USART_PRESC_PRESCALER, huart->Init.ClockPrescaler); + 8006584: 697b ldr r3, [r7, #20] + 8006586: 681b ldr r3, [r3, #0] + 8006588: 6adb ldr r3, [r3, #44] ; 0x2c + 800658a: f023 010f bic.w r1, r3, #15 + 800658e: 697b ldr r3, [r7, #20] + 8006590: 6a5a ldr r2, [r3, #36] ; 0x24 + 8006592: 697b ldr r3, [r7, #20] + 8006594: 681b ldr r3, [r3, #0] + 8006596: 430a orrs r2, r1 + 8006598: 62da str r2, [r3, #44] ; 0x2c + + /*-------------------------- USART BRR Configuration -----------------------*/ + UART_GETCLOCKSOURCE(huart, clocksource); + 800659a: 697b ldr r3, [r7, #20] + 800659c: 681b ldr r3, [r3, #0] + 800659e: 4a7a ldr r2, [pc, #488] ; (8006788 ) + 80065a0: 4293 cmp r3, r2 + 80065a2: d127 bne.n 80065f4 + 80065a4: 2003 movs r0, #3 + 80065a6: f7ff fa67 bl 8005a78 + 80065aa: 4603 mov r3, r0 + 80065ac: f5a3 3340 sub.w r3, r3, #196608 ; 0x30000 + 80065b0: 2b03 cmp r3, #3 + 80065b2: d81b bhi.n 80065ec + 80065b4: a201 add r2, pc, #4 ; (adr r2, 80065bc ) + 80065b6: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80065ba: bf00 nop + 80065bc: 080065cd .word 0x080065cd + 80065c0: 080065dd .word 0x080065dd + 80065c4: 080065d5 .word 0x080065d5 + 80065c8: 080065e5 .word 0x080065e5 + 80065cc: 2301 movs r3, #1 + 80065ce: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80065d2: e080 b.n 80066d6 + 80065d4: 2302 movs r3, #2 + 80065d6: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80065da: e07c b.n 80066d6 + 80065dc: 2304 movs r3, #4 + 80065de: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80065e2: e078 b.n 80066d6 + 80065e4: 2308 movs r3, #8 + 80065e6: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80065ea: e074 b.n 80066d6 + 80065ec: 2310 movs r3, #16 + 80065ee: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80065f2: e070 b.n 80066d6 + 80065f4: 697b ldr r3, [r7, #20] + 80065f6: 681b ldr r3, [r3, #0] + 80065f8: 4a64 ldr r2, [pc, #400] ; (800678c ) + 80065fa: 4293 cmp r3, r2 + 80065fc: d138 bne.n 8006670 + 80065fe: 200c movs r0, #12 + 8006600: f7ff fa3a bl 8005a78 + 8006604: 4603 mov r3, r0 + 8006606: f5a3 2340 sub.w r3, r3, #786432 ; 0xc0000 + 800660a: 2b0c cmp r3, #12 + 800660c: d82c bhi.n 8006668 + 800660e: a201 add r2, pc, #4 ; (adr r2, 8006614 ) + 8006610: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006614: 08006649 .word 0x08006649 + 8006618: 08006669 .word 0x08006669 + 800661c: 08006669 .word 0x08006669 + 8006620: 08006669 .word 0x08006669 + 8006624: 08006659 .word 0x08006659 + 8006628: 08006669 .word 0x08006669 + 800662c: 08006669 .word 0x08006669 + 8006630: 08006669 .word 0x08006669 + 8006634: 08006651 .word 0x08006651 + 8006638: 08006669 .word 0x08006669 + 800663c: 08006669 .word 0x08006669 + 8006640: 08006669 .word 0x08006669 + 8006644: 08006661 .word 0x08006661 + 8006648: 2300 movs r3, #0 + 800664a: f887 302b strb.w r3, [r7, #43] ; 0x2b + 800664e: e042 b.n 80066d6 + 8006650: 2302 movs r3, #2 + 8006652: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8006656: e03e b.n 80066d6 + 8006658: 2304 movs r3, #4 + 800665a: f887 302b strb.w r3, [r7, #43] ; 0x2b + 800665e: e03a b.n 80066d6 + 8006660: 2308 movs r3, #8 + 8006662: f887 302b strb.w r3, [r7, #43] ; 0x2b + 8006666: e036 b.n 80066d6 + 8006668: 2310 movs r3, #16 + 800666a: f887 302b strb.w r3, [r7, #43] ; 0x2b + 800666e: e032 b.n 80066d6 + 8006670: 697b ldr r3, [r7, #20] + 8006672: 681b ldr r3, [r3, #0] + 8006674: 4a43 ldr r2, [pc, #268] ; (8006784 ) + 8006676: 4293 cmp r3, r2 + 8006678: d12a bne.n 80066d0 + 800667a: f44f 6040 mov.w r0, #3072 ; 0xc00 + 800667e: f7ff fa0d bl 8005a9c + 8006682: 4603 mov r3, r0 + 8006684: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 8006688: d01a beq.n 80066c0 + 800668a: f5b3 6f40 cmp.w r3, #3072 ; 0xc00 + 800668e: d81b bhi.n 80066c8 + 8006690: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8006694: d00c beq.n 80066b0 + 8006696: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 800669a: d815 bhi.n 80066c8 + 800669c: 2b00 cmp r3, #0 + 800669e: d003 beq.n 80066a8 + 80066a0: f5b3 6f80 cmp.w r3, #1024 ; 0x400 + 80066a4: d008 beq.n 80066b8 + 80066a6: e00f b.n 80066c8 + 80066a8: 2300 movs r3, #0 + 80066aa: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80066ae: e012 b.n 80066d6 + 80066b0: 2302 movs r3, #2 + 80066b2: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80066b6: e00e b.n 80066d6 + 80066b8: 2304 movs r3, #4 + 80066ba: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80066be: e00a b.n 80066d6 + 80066c0: 2308 movs r3, #8 + 80066c2: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80066c6: e006 b.n 80066d6 + 80066c8: 2310 movs r3, #16 + 80066ca: f887 302b strb.w r3, [r7, #43] ; 0x2b + 80066ce: e002 b.n 80066d6 + 80066d0: 2310 movs r3, #16 + 80066d2: f887 302b strb.w r3, [r7, #43] ; 0x2b + + /* Check LPUART instance */ + if (UART_INSTANCE_LOWPOWER(huart)) + 80066d6: 697b ldr r3, [r7, #20] + 80066d8: 681b ldr r3, [r3, #0] + 80066da: 4a2a ldr r2, [pc, #168] ; (8006784 ) + 80066dc: 4293 cmp r3, r2 + 80066de: f040 80a4 bne.w 800682a + { + /* Retrieve frequency clock */ + switch (clocksource) + 80066e2: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 80066e6: 2b08 cmp r3, #8 + 80066e8: d823 bhi.n 8006732 + 80066ea: a201 add r2, pc, #4 ; (adr r2, 80066f0 ) + 80066ec: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 80066f0: 08006715 .word 0x08006715 + 80066f4: 08006733 .word 0x08006733 + 80066f8: 0800671d .word 0x0800671d + 80066fc: 08006733 .word 0x08006733 + 8006700: 08006723 .word 0x08006723 + 8006704: 08006733 .word 0x08006733 + 8006708: 08006733 .word 0x08006733 + 800670c: 08006733 .word 0x08006733 + 8006710: 0800672b .word 0x0800672b + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8006714: f7fd fe10 bl 8004338 + 8006718: 6278 str r0, [r7, #36] ; 0x24 + break; + 800671a: e010 b.n 800673e + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 800671c: 4b1c ldr r3, [pc, #112] ; (8006790 ) + 800671e: 627b str r3, [r7, #36] ; 0x24 + break; + 8006720: e00d b.n 800673e + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 8006722: f7fd fd55 bl 80041d0 + 8006726: 6278 str r0, [r7, #36] ; 0x24 + break; + 8006728: e009 b.n 800673e + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 800672a: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800672e: 627b str r3, [r7, #36] ; 0x24 + break; + 8006730: e005 b.n 800673e + default: + pclk = 0U; + 8006732: 2300 movs r3, #0 + 8006734: 627b str r3, [r7, #36] ; 0x24 + ret = HAL_ERROR; + 8006736: 2301 movs r3, #1 + 8006738: f887 302a strb.w r3, [r7, #42] ; 0x2a + break; + 800673c: bf00 nop + } + + /* If proper clock source reported */ + if (pclk != 0U) + 800673e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006740: 2b00 cmp r3, #0 + 8006742: f000 8137 beq.w 80069b4 + { + /* Compute clock after Prescaler */ + lpuart_ker_ck_pres = (pclk / UARTPrescTable[huart->Init.ClockPrescaler]); + 8006746: 697b ldr r3, [r7, #20] + 8006748: 6a5b ldr r3, [r3, #36] ; 0x24 + 800674a: 4a12 ldr r2, [pc, #72] ; (8006794 ) + 800674c: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 8006750: 461a mov r2, r3 + 8006752: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006754: fbb3 f3f2 udiv r3, r3, r2 + 8006758: 61bb str r3, [r7, #24] + + /* Ensure that Frequency clock is in the range [3 * baudrate, 4096 * baudrate] */ + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + 800675a: 697b ldr r3, [r7, #20] + 800675c: 685a ldr r2, [r3, #4] + 800675e: 4613 mov r3, r2 + 8006760: 005b lsls r3, r3, #1 + 8006762: 4413 add r3, r2 + 8006764: 69ba ldr r2, [r7, #24] + 8006766: 429a cmp r2, r3 + 8006768: d305 bcc.n 8006776 + (lpuart_ker_ck_pres > (4096U * huart->Init.BaudRate))) + 800676a: 697b ldr r3, [r7, #20] + 800676c: 685b ldr r3, [r3, #4] + 800676e: 031b lsls r3, r3, #12 + if ((lpuart_ker_ck_pres < (3U * huart->Init.BaudRate)) || + 8006770: 69ba ldr r2, [r7, #24] + 8006772: 429a cmp r2, r3 + 8006774: d910 bls.n 8006798 + { + ret = HAL_ERROR; + 8006776: 2301 movs r3, #1 + 8006778: f887 302a strb.w r3, [r7, #42] ; 0x2a + 800677c: e11a b.n 80069b4 + 800677e: bf00 nop + 8006780: cfff69f3 .word 0xcfff69f3 + 8006784: 40008000 .word 0x40008000 + 8006788: 40013800 .word 0x40013800 + 800678c: 40004400 .word 0x40004400 + 8006790: 00f42400 .word 0x00f42400 + 8006794: 0800e3dc .word 0x0800e3dc + } + else + { + /* Check computed UsartDiv value is in allocated range + (it is forbidden to write values lower than 0x300 in the LPUART_BRR register) */ + usartdiv = (uint32_t)(UART_DIV_LPUART(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 8006798: 6a7b ldr r3, [r7, #36] ; 0x24 + 800679a: 2200 movs r2, #0 + 800679c: 60bb str r3, [r7, #8] + 800679e: 60fa str r2, [r7, #12] + 80067a0: 697b ldr r3, [r7, #20] + 80067a2: 6a5b ldr r3, [r3, #36] ; 0x24 + 80067a4: 4a8e ldr r2, [pc, #568] ; (80069e0 ) + 80067a6: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 80067aa: b29b uxth r3, r3 + 80067ac: 2200 movs r2, #0 + 80067ae: 603b str r3, [r7, #0] + 80067b0: 607a str r2, [r7, #4] + 80067b2: e9d7 2300 ldrd r2, r3, [r7] + 80067b6: e9d7 0102 ldrd r0, r1, [r7, #8] + 80067ba: f7f9 fd39 bl 8000230 <__aeabi_uldivmod> + 80067be: 4602 mov r2, r0 + 80067c0: 460b mov r3, r1 + 80067c2: 4610 mov r0, r2 + 80067c4: 4619 mov r1, r3 + 80067c6: f04f 0200 mov.w r2, #0 + 80067ca: f04f 0300 mov.w r3, #0 + 80067ce: 020b lsls r3, r1, #8 + 80067d0: ea43 6310 orr.w r3, r3, r0, lsr #24 + 80067d4: 0202 lsls r2, r0, #8 + 80067d6: 6979 ldr r1, [r7, #20] + 80067d8: 6849 ldr r1, [r1, #4] + 80067da: 0849 lsrs r1, r1, #1 + 80067dc: 2000 movs r0, #0 + 80067de: 460c mov r4, r1 + 80067e0: 4605 mov r5, r0 + 80067e2: eb12 0804 adds.w r8, r2, r4 + 80067e6: eb43 0905 adc.w r9, r3, r5 + 80067ea: 697b ldr r3, [r7, #20] + 80067ec: 685b ldr r3, [r3, #4] + 80067ee: 2200 movs r2, #0 + 80067f0: 469a mov sl, r3 + 80067f2: 4693 mov fp, r2 + 80067f4: 4652 mov r2, sl + 80067f6: 465b mov r3, fp + 80067f8: 4640 mov r0, r8 + 80067fa: 4649 mov r1, r9 + 80067fc: f7f9 fd18 bl 8000230 <__aeabi_uldivmod> + 8006800: 4602 mov r2, r0 + 8006802: 460b mov r3, r1 + 8006804: 4613 mov r3, r2 + 8006806: 623b str r3, [r7, #32] + if ((usartdiv >= LPUART_BRR_MIN) && (usartdiv <= LPUART_BRR_MAX)) + 8006808: 6a3b ldr r3, [r7, #32] + 800680a: f5b3 7f40 cmp.w r3, #768 ; 0x300 + 800680e: d308 bcc.n 8006822 + 8006810: 6a3b ldr r3, [r7, #32] + 8006812: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8006816: d204 bcs.n 8006822 + { + huart->Instance->BRR = usartdiv; + 8006818: 697b ldr r3, [r7, #20] + 800681a: 681b ldr r3, [r3, #0] + 800681c: 6a3a ldr r2, [r7, #32] + 800681e: 60da str r2, [r3, #12] + 8006820: e0c8 b.n 80069b4 + } + else + { + ret = HAL_ERROR; + 8006822: 2301 movs r3, #1 + 8006824: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8006828: e0c4 b.n 80069b4 + } /* if ( (lpuart_ker_ck_pres < (3 * huart->Init.BaudRate) ) || + (lpuart_ker_ck_pres > (4096 * huart->Init.BaudRate) )) */ + } /* if (pclk != 0) */ + } + /* Check UART Over Sampling to set Baud Rate Register */ + else if (huart->Init.OverSampling == UART_OVERSAMPLING_8) + 800682a: 697b ldr r3, [r7, #20] + 800682c: 69db ldr r3, [r3, #28] + 800682e: f5b3 4f00 cmp.w r3, #32768 ; 0x8000 + 8006832: d167 bne.n 8006904 + { + switch (clocksource) + 8006834: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 8006838: 2b08 cmp r3, #8 + 800683a: d828 bhi.n 800688e + 800683c: a201 add r2, pc, #4 ; (adr r2, 8006844 ) + 800683e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006842: bf00 nop + 8006844: 08006869 .word 0x08006869 + 8006848: 08006871 .word 0x08006871 + 800684c: 08006879 .word 0x08006879 + 8006850: 0800688f .word 0x0800688f + 8006854: 0800687f .word 0x0800687f + 8006858: 0800688f .word 0x0800688f + 800685c: 0800688f .word 0x0800688f + 8006860: 0800688f .word 0x0800688f + 8006864: 08006887 .word 0x08006887 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8006868: f7fd fd66 bl 8004338 + 800686c: 6278 str r0, [r7, #36] ; 0x24 + break; + 800686e: e014 b.n 800689a + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 8006870: f7fd fd74 bl 800435c + 8006874: 6278 str r0, [r7, #36] ; 0x24 + break; + 8006876: e010 b.n 800689a + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8006878: 4b5a ldr r3, [pc, #360] ; (80069e4 ) + 800687a: 627b str r3, [r7, #36] ; 0x24 + break; + 800687c: e00d b.n 800689a + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 800687e: f7fd fca7 bl 80041d0 + 8006882: 6278 str r0, [r7, #36] ; 0x24 + break; + 8006884: e009 b.n 800689a + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8006886: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800688a: 627b str r3, [r7, #36] ; 0x24 + break; + 800688c: e005 b.n 800689a + default: + pclk = 0U; + 800688e: 2300 movs r3, #0 + 8006890: 627b str r3, [r7, #36] ; 0x24 + ret = HAL_ERROR; + 8006892: 2301 movs r3, #1 + 8006894: f887 302a strb.w r3, [r7, #42] ; 0x2a + break; + 8006898: bf00 nop + } + + /* USARTDIV must be greater than or equal to 0d16 */ + if (pclk != 0U) + 800689a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800689c: 2b00 cmp r3, #0 + 800689e: f000 8089 beq.w 80069b4 + { + usartdiv = (uint32_t)(UART_DIV_SAMPLING8(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 80068a2: 697b ldr r3, [r7, #20] + 80068a4: 6a5b ldr r3, [r3, #36] ; 0x24 + 80068a6: 4a4e ldr r2, [pc, #312] ; (80069e0 ) + 80068a8: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 80068ac: 461a mov r2, r3 + 80068ae: 6a7b ldr r3, [r7, #36] ; 0x24 + 80068b0: fbb3 f3f2 udiv r3, r3, r2 + 80068b4: 005a lsls r2, r3, #1 + 80068b6: 697b ldr r3, [r7, #20] + 80068b8: 685b ldr r3, [r3, #4] + 80068ba: 085b lsrs r3, r3, #1 + 80068bc: 441a add r2, r3 + 80068be: 697b ldr r3, [r7, #20] + 80068c0: 685b ldr r3, [r3, #4] + 80068c2: fbb2 f3f3 udiv r3, r2, r3 + 80068c6: 623b str r3, [r7, #32] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 80068c8: 6a3b ldr r3, [r7, #32] + 80068ca: 2b0f cmp r3, #15 + 80068cc: d916 bls.n 80068fc + 80068ce: 6a3b ldr r3, [r7, #32] + 80068d0: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80068d4: d212 bcs.n 80068fc + { + brrtemp = (uint16_t)(usartdiv & 0xFFF0U); + 80068d6: 6a3b ldr r3, [r7, #32] + 80068d8: b29b uxth r3, r3 + 80068da: f023 030f bic.w r3, r3, #15 + 80068de: 83fb strh r3, [r7, #30] + brrtemp |= (uint16_t)((usartdiv & (uint16_t)0x000FU) >> 1U); + 80068e0: 6a3b ldr r3, [r7, #32] + 80068e2: 085b lsrs r3, r3, #1 + 80068e4: b29b uxth r3, r3 + 80068e6: f003 0307 and.w r3, r3, #7 + 80068ea: b29a uxth r2, r3 + 80068ec: 8bfb ldrh r3, [r7, #30] + 80068ee: 4313 orrs r3, r2 + 80068f0: 83fb strh r3, [r7, #30] + huart->Instance->BRR = brrtemp; + 80068f2: 697b ldr r3, [r7, #20] + 80068f4: 681b ldr r3, [r3, #0] + 80068f6: 8bfa ldrh r2, [r7, #30] + 80068f8: 60da str r2, [r3, #12] + 80068fa: e05b b.n 80069b4 + } + else + { + ret = HAL_ERROR; + 80068fc: 2301 movs r3, #1 + 80068fe: f887 302a strb.w r3, [r7, #42] ; 0x2a + 8006902: e057 b.n 80069b4 + } + } + } + else + { + switch (clocksource) + 8006904: f897 302b ldrb.w r3, [r7, #43] ; 0x2b + 8006908: 2b08 cmp r3, #8 + 800690a: d828 bhi.n 800695e + 800690c: a201 add r2, pc, #4 ; (adr r2, 8006914 ) + 800690e: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8006912: bf00 nop + 8006914: 08006939 .word 0x08006939 + 8006918: 08006941 .word 0x08006941 + 800691c: 08006949 .word 0x08006949 + 8006920: 0800695f .word 0x0800695f + 8006924: 0800694f .word 0x0800694f + 8006928: 0800695f .word 0x0800695f + 800692c: 0800695f .word 0x0800695f + 8006930: 0800695f .word 0x0800695f + 8006934: 08006957 .word 0x08006957 + { + case UART_CLOCKSOURCE_PCLK1: + pclk = HAL_RCC_GetPCLK1Freq(); + 8006938: f7fd fcfe bl 8004338 + 800693c: 6278 str r0, [r7, #36] ; 0x24 + break; + 800693e: e014 b.n 800696a + case UART_CLOCKSOURCE_PCLK2: + pclk = HAL_RCC_GetPCLK2Freq(); + 8006940: f7fd fd0c bl 800435c + 8006944: 6278 str r0, [r7, #36] ; 0x24 + break; + 8006946: e010 b.n 800696a + case UART_CLOCKSOURCE_HSI: + pclk = (uint32_t) HSI_VALUE; + 8006948: 4b26 ldr r3, [pc, #152] ; (80069e4 ) + 800694a: 627b str r3, [r7, #36] ; 0x24 + break; + 800694c: e00d b.n 800696a + case UART_CLOCKSOURCE_SYSCLK: + pclk = HAL_RCC_GetSysClockFreq(); + 800694e: f7fd fc3f bl 80041d0 + 8006952: 6278 str r0, [r7, #36] ; 0x24 + break; + 8006954: e009 b.n 800696a + case UART_CLOCKSOURCE_LSE: + pclk = (uint32_t) LSE_VALUE; + 8006956: f44f 4300 mov.w r3, #32768 ; 0x8000 + 800695a: 627b str r3, [r7, #36] ; 0x24 + break; + 800695c: e005 b.n 800696a + default: + pclk = 0U; + 800695e: 2300 movs r3, #0 + 8006960: 627b str r3, [r7, #36] ; 0x24 + ret = HAL_ERROR; + 8006962: 2301 movs r3, #1 + 8006964: f887 302a strb.w r3, [r7, #42] ; 0x2a + break; + 8006968: bf00 nop + } + + if (pclk != 0U) + 800696a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800696c: 2b00 cmp r3, #0 + 800696e: d021 beq.n 80069b4 + { + /* USARTDIV must be greater than or equal to 0d16 */ + usartdiv = (uint32_t)(UART_DIV_SAMPLING16(pclk, huart->Init.BaudRate, huart->Init.ClockPrescaler)); + 8006970: 697b ldr r3, [r7, #20] + 8006972: 6a5b ldr r3, [r3, #36] ; 0x24 + 8006974: 4a1a ldr r2, [pc, #104] ; (80069e0 ) + 8006976: f832 3013 ldrh.w r3, [r2, r3, lsl #1] + 800697a: 461a mov r2, r3 + 800697c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800697e: fbb3 f2f2 udiv r2, r3, r2 + 8006982: 697b ldr r3, [r7, #20] + 8006984: 685b ldr r3, [r3, #4] + 8006986: 085b lsrs r3, r3, #1 + 8006988: 441a add r2, r3 + 800698a: 697b ldr r3, [r7, #20] + 800698c: 685b ldr r3, [r3, #4] + 800698e: fbb2 f3f3 udiv r3, r2, r3 + 8006992: 623b str r3, [r7, #32] + if ((usartdiv >= UART_BRR_MIN) && (usartdiv <= UART_BRR_MAX)) + 8006994: 6a3b ldr r3, [r7, #32] + 8006996: 2b0f cmp r3, #15 + 8006998: d909 bls.n 80069ae + 800699a: 6a3b ldr r3, [r7, #32] + 800699c: f5b3 3f80 cmp.w r3, #65536 ; 0x10000 + 80069a0: d205 bcs.n 80069ae + { + huart->Instance->BRR = (uint16_t)usartdiv; + 80069a2: 6a3b ldr r3, [r7, #32] + 80069a4: b29a uxth r2, r3 + 80069a6: 697b ldr r3, [r7, #20] + 80069a8: 681b ldr r3, [r3, #0] + 80069aa: 60da str r2, [r3, #12] + 80069ac: e002 b.n 80069b4 + } + else + { + ret = HAL_ERROR; + 80069ae: 2301 movs r3, #1 + 80069b0: f887 302a strb.w r3, [r7, #42] ; 0x2a + } + } + } + + /* Initialize the number of data to process during RX/TX ISR execution */ + huart->NbTxDataToProcess = 1; + 80069b4: 697b ldr r3, [r7, #20] + 80069b6: 2201 movs r2, #1 + 80069b8: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + huart->NbRxDataToProcess = 1; + 80069bc: 697b ldr r3, [r7, #20] + 80069be: 2201 movs r2, #1 + 80069c0: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + + /* Clear ISR function pointers */ + huart->RxISR = NULL; + 80069c4: 697b ldr r3, [r7, #20] + 80069c6: 2200 movs r2, #0 + 80069c8: 675a str r2, [r3, #116] ; 0x74 + huart->TxISR = NULL; + 80069ca: 697b ldr r3, [r7, #20] + 80069cc: 2200 movs r2, #0 + 80069ce: 679a str r2, [r3, #120] ; 0x78 + + return ret; + 80069d0: f897 302a ldrb.w r3, [r7, #42] ; 0x2a +} + 80069d4: 4618 mov r0, r3 + 80069d6: 3730 adds r7, #48 ; 0x30 + 80069d8: 46bd mov sp, r7 + 80069da: e8bd 8fb0 ldmia.w sp!, {r4, r5, r7, r8, r9, sl, fp, pc} + 80069de: bf00 nop + 80069e0: 0800e3dc .word 0x0800e3dc + 80069e4: 00f42400 .word 0x00f42400 + +080069e8 : + * @brief Configure the UART peripheral advanced features. + * @param huart UART handle. + * @retval None + */ +void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) +{ + 80069e8: b480 push {r7} + 80069ea: b083 sub sp, #12 + 80069ec: af00 add r7, sp, #0 + 80069ee: 6078 str r0, [r7, #4] + /* Check whether the set of advanced features to configure is properly set */ + assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit)); + + /* if required, configure TX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT)) + 80069f0: 687b ldr r3, [r7, #4] + 80069f2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80069f4: f003 0301 and.w r3, r3, #1 + 80069f8: 2b00 cmp r3, #0 + 80069fa: d00a beq.n 8006a12 + { + assert_param(IS_UART_ADVFEATURE_TXINV(huart->AdvancedInit.TxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_TXINV, huart->AdvancedInit.TxPinLevelInvert); + 80069fc: 687b ldr r3, [r7, #4] + 80069fe: 681b ldr r3, [r3, #0] + 8006a00: 685b ldr r3, [r3, #4] + 8006a02: f423 3100 bic.w r1, r3, #131072 ; 0x20000 + 8006a06: 687b ldr r3, [r7, #4] + 8006a08: 6ada ldr r2, [r3, #44] ; 0x2c + 8006a0a: 687b ldr r3, [r7, #4] + 8006a0c: 681b ldr r3, [r3, #0] + 8006a0e: 430a orrs r2, r1 + 8006a10: 605a str r2, [r3, #4] + } + + /* if required, configure RX pin active level inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXINVERT_INIT)) + 8006a12: 687b ldr r3, [r7, #4] + 8006a14: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006a16: f003 0302 and.w r3, r3, #2 + 8006a1a: 2b00 cmp r3, #0 + 8006a1c: d00a beq.n 8006a34 + { + assert_param(IS_UART_ADVFEATURE_RXINV(huart->AdvancedInit.RxPinLevelInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_RXINV, huart->AdvancedInit.RxPinLevelInvert); + 8006a1e: 687b ldr r3, [r7, #4] + 8006a20: 681b ldr r3, [r3, #0] + 8006a22: 685b ldr r3, [r3, #4] + 8006a24: f423 3180 bic.w r1, r3, #65536 ; 0x10000 + 8006a28: 687b ldr r3, [r7, #4] + 8006a2a: 6b1a ldr r2, [r3, #48] ; 0x30 + 8006a2c: 687b ldr r3, [r7, #4] + 8006a2e: 681b ldr r3, [r3, #0] + 8006a30: 430a orrs r2, r1 + 8006a32: 605a str r2, [r3, #4] + } + + /* if required, configure data inversion */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DATAINVERT_INIT)) + 8006a34: 687b ldr r3, [r7, #4] + 8006a36: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006a38: f003 0304 and.w r3, r3, #4 + 8006a3c: 2b00 cmp r3, #0 + 8006a3e: d00a beq.n 8006a56 + { + assert_param(IS_UART_ADVFEATURE_DATAINV(huart->AdvancedInit.DataInvert)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert); + 8006a40: 687b ldr r3, [r7, #4] + 8006a42: 681b ldr r3, [r3, #0] + 8006a44: 685b ldr r3, [r3, #4] + 8006a46: f423 2180 bic.w r1, r3, #262144 ; 0x40000 + 8006a4a: 687b ldr r3, [r7, #4] + 8006a4c: 6b5a ldr r2, [r3, #52] ; 0x34 + 8006a4e: 687b ldr r3, [r7, #4] + 8006a50: 681b ldr r3, [r3, #0] + 8006a52: 430a orrs r2, r1 + 8006a54: 605a str r2, [r3, #4] + } + + /* if required, configure RX/TX pins swap */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT)) + 8006a56: 687b ldr r3, [r7, #4] + 8006a58: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006a5a: f003 0308 and.w r3, r3, #8 + 8006a5e: 2b00 cmp r3, #0 + 8006a60: d00a beq.n 8006a78 + { + assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap); + 8006a62: 687b ldr r3, [r7, #4] + 8006a64: 681b ldr r3, [r3, #0] + 8006a66: 685b ldr r3, [r3, #4] + 8006a68: f423 4100 bic.w r1, r3, #32768 ; 0x8000 + 8006a6c: 687b ldr r3, [r7, #4] + 8006a6e: 6b9a ldr r2, [r3, #56] ; 0x38 + 8006a70: 687b ldr r3, [r7, #4] + 8006a72: 681b ldr r3, [r3, #0] + 8006a74: 430a orrs r2, r1 + 8006a76: 605a str r2, [r3, #4] + } + + /* if required, configure RX overrun detection disabling */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT)) + 8006a78: 687b ldr r3, [r7, #4] + 8006a7a: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006a7c: f003 0310 and.w r3, r3, #16 + 8006a80: 2b00 cmp r3, #0 + 8006a82: d00a beq.n 8006a9a + { + assert_param(IS_UART_OVERRUN(huart->AdvancedInit.OverrunDisable)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_OVRDIS, huart->AdvancedInit.OverrunDisable); + 8006a84: 687b ldr r3, [r7, #4] + 8006a86: 681b ldr r3, [r3, #0] + 8006a88: 689b ldr r3, [r3, #8] + 8006a8a: f423 5180 bic.w r1, r3, #4096 ; 0x1000 + 8006a8e: 687b ldr r3, [r7, #4] + 8006a90: 6bda ldr r2, [r3, #60] ; 0x3c + 8006a92: 687b ldr r3, [r7, #4] + 8006a94: 681b ldr r3, [r3, #0] + 8006a96: 430a orrs r2, r1 + 8006a98: 609a str r2, [r3, #8] + } + + /* if required, configure DMA disabling on reception error */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_DMADISABLEONERROR_INIT)) + 8006a9a: 687b ldr r3, [r7, #4] + 8006a9c: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006a9e: f003 0320 and.w r3, r3, #32 + 8006aa2: 2b00 cmp r3, #0 + 8006aa4: d00a beq.n 8006abc + { + assert_param(IS_UART_ADVFEATURE_DMAONRXERROR(huart->AdvancedInit.DMADisableonRxError)); + MODIFY_REG(huart->Instance->CR3, USART_CR3_DDRE, huart->AdvancedInit.DMADisableonRxError); + 8006aa6: 687b ldr r3, [r7, #4] + 8006aa8: 681b ldr r3, [r3, #0] + 8006aaa: 689b ldr r3, [r3, #8] + 8006aac: f423 5100 bic.w r1, r3, #8192 ; 0x2000 + 8006ab0: 687b ldr r3, [r7, #4] + 8006ab2: 6c1a ldr r2, [r3, #64] ; 0x40 + 8006ab4: 687b ldr r3, [r7, #4] + 8006ab6: 681b ldr r3, [r3, #0] + 8006ab8: 430a orrs r2, r1 + 8006aba: 609a str r2, [r3, #8] + } + + /* if required, configure auto Baud rate detection scheme */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_AUTOBAUDRATE_INIT)) + 8006abc: 687b ldr r3, [r7, #4] + 8006abe: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006ac0: f003 0340 and.w r3, r3, #64 ; 0x40 + 8006ac4: 2b00 cmp r3, #0 + 8006ac6: d01a beq.n 8006afe + { + assert_param(IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(huart->Instance)); + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATE(huart->AdvancedInit.AutoBaudRateEnable)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABREN, huart->AdvancedInit.AutoBaudRateEnable); + 8006ac8: 687b ldr r3, [r7, #4] + 8006aca: 681b ldr r3, [r3, #0] + 8006acc: 685b ldr r3, [r3, #4] + 8006ace: f423 1180 bic.w r1, r3, #1048576 ; 0x100000 + 8006ad2: 687b ldr r3, [r7, #4] + 8006ad4: 6c5a ldr r2, [r3, #68] ; 0x44 + 8006ad6: 687b ldr r3, [r7, #4] + 8006ad8: 681b ldr r3, [r3, #0] + 8006ada: 430a orrs r2, r1 + 8006adc: 605a str r2, [r3, #4] + /* set auto Baudrate detection parameters if detection is enabled */ + if (huart->AdvancedInit.AutoBaudRateEnable == UART_ADVFEATURE_AUTOBAUDRATE_ENABLE) + 8006ade: 687b ldr r3, [r7, #4] + 8006ae0: 6c5b ldr r3, [r3, #68] ; 0x44 + 8006ae2: f5b3 1f80 cmp.w r3, #1048576 ; 0x100000 + 8006ae6: d10a bne.n 8006afe + { + assert_param(IS_UART_ADVFEATURE_AUTOBAUDRATEMODE(huart->AdvancedInit.AutoBaudRateMode)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_ABRMODE, huart->AdvancedInit.AutoBaudRateMode); + 8006ae8: 687b ldr r3, [r7, #4] + 8006aea: 681b ldr r3, [r3, #0] + 8006aec: 685b ldr r3, [r3, #4] + 8006aee: f423 01c0 bic.w r1, r3, #6291456 ; 0x600000 + 8006af2: 687b ldr r3, [r7, #4] + 8006af4: 6c9a ldr r2, [r3, #72] ; 0x48 + 8006af6: 687b ldr r3, [r7, #4] + 8006af8: 681b ldr r3, [r3, #0] + 8006afa: 430a orrs r2, r1 + 8006afc: 605a str r2, [r3, #4] + } + } + + /* if required, configure MSB first on communication line */ + if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_MSBFIRST_INIT)) + 8006afe: 687b ldr r3, [r7, #4] + 8006b00: 6a9b ldr r3, [r3, #40] ; 0x28 + 8006b02: f003 0380 and.w r3, r3, #128 ; 0x80 + 8006b06: 2b00 cmp r3, #0 + 8006b08: d00a beq.n 8006b20 + { + assert_param(IS_UART_ADVFEATURE_MSBFIRST(huart->AdvancedInit.MSBFirst)); + MODIFY_REG(huart->Instance->CR2, USART_CR2_MSBFIRST, huart->AdvancedInit.MSBFirst); + 8006b0a: 687b ldr r3, [r7, #4] + 8006b0c: 681b ldr r3, [r3, #0] + 8006b0e: 685b ldr r3, [r3, #4] + 8006b10: f423 2100 bic.w r1, r3, #524288 ; 0x80000 + 8006b14: 687b ldr r3, [r7, #4] + 8006b16: 6cda ldr r2, [r3, #76] ; 0x4c + 8006b18: 687b ldr r3, [r7, #4] + 8006b1a: 681b ldr r3, [r3, #0] + 8006b1c: 430a orrs r2, r1 + 8006b1e: 605a str r2, [r3, #4] + } +} + 8006b20: bf00 nop + 8006b22: 370c adds r7, #12 + 8006b24: 46bd mov sp, r7 + 8006b26: bc80 pop {r7} + 8006b28: 4770 bx lr + +08006b2a : + * @brief Check the UART Idle State. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) +{ + 8006b2a: b580 push {r7, lr} + 8006b2c: b086 sub sp, #24 + 8006b2e: af02 add r7, sp, #8 + 8006b30: 6078 str r0, [r7, #4] + uint32_t tickstart; + + /* Initialize the UART ErrorCode */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006b32: 687b ldr r3, [r7, #4] + 8006b34: 2200 movs r2, #0 + 8006b36: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8006b3a: f7fa f8ef bl 8000d1c + 8006b3e: 60f8 str r0, [r7, #12] + + /* Check if the Transmitter is enabled */ + if ((huart->Instance->CR1 & USART_CR1_TE) == USART_CR1_TE) + 8006b40: 687b ldr r3, [r7, #4] + 8006b42: 681b ldr r3, [r3, #0] + 8006b44: 681b ldr r3, [r3, #0] + 8006b46: f003 0308 and.w r3, r3, #8 + 8006b4a: 2b08 cmp r3, #8 + 8006b4c: d10e bne.n 8006b6c + { + /* Wait until TEACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_TEACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8006b4e: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8006b52: 9300 str r3, [sp, #0] + 8006b54: 68fb ldr r3, [r7, #12] + 8006b56: 2200 movs r2, #0 + 8006b58: f44f 1100 mov.w r1, #2097152 ; 0x200000 + 8006b5c: 6878 ldr r0, [r7, #4] + 8006b5e: f000 f832 bl 8006bc6 + 8006b62: 4603 mov r3, r0 + 8006b64: 2b00 cmp r3, #0 + 8006b66: d001 beq.n 8006b6c + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 8006b68: 2303 movs r3, #3 + 8006b6a: e028 b.n 8006bbe + } + } + + /* Check if the Receiver is enabled */ + if ((huart->Instance->CR1 & USART_CR1_RE) == USART_CR1_RE) + 8006b6c: 687b ldr r3, [r7, #4] + 8006b6e: 681b ldr r3, [r3, #0] + 8006b70: 681b ldr r3, [r3, #0] + 8006b72: f003 0304 and.w r3, r3, #4 + 8006b76: 2b04 cmp r3, #4 + 8006b78: d10e bne.n 8006b98 + { + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8006b7a: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8006b7e: 9300 str r3, [sp, #0] + 8006b80: 68fb ldr r3, [r7, #12] + 8006b82: 2200 movs r2, #0 + 8006b84: f44f 0180 mov.w r1, #4194304 ; 0x400000 + 8006b88: 6878 ldr r0, [r7, #4] + 8006b8a: f000 f81c bl 8006bc6 + 8006b8e: 4603 mov r3, r0 + 8006b90: 2b00 cmp r3, #0 + 8006b92: d001 beq.n 8006b98 + { + /* Timeout occurred */ + return HAL_TIMEOUT; + 8006b94: 2303 movs r3, #3 + 8006b96: e012 b.n 8006bbe + } + } + + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 8006b98: 687b ldr r3, [r7, #4] + 8006b9a: 2220 movs r2, #32 + 8006b9c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + huart->RxState = HAL_UART_STATE_READY; + 8006ba0: 687b ldr r3, [r7, #4] + 8006ba2: 2220 movs r2, #32 + 8006ba4: f8c3 208c str.w r2, [r3, #140] ; 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8006ba8: 687b ldr r3, [r7, #4] + 8006baa: 2200 movs r2, #0 + 8006bac: 66da str r2, [r3, #108] ; 0x6c + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8006bae: 687b ldr r3, [r7, #4] + 8006bb0: 2200 movs r2, #0 + 8006bb2: 671a str r2, [r3, #112] ; 0x70 + + __HAL_UNLOCK(huart); + 8006bb4: 687b ldr r3, [r7, #4] + 8006bb6: 2200 movs r2, #0 + 8006bb8: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8006bbc: 2300 movs r3, #0 +} + 8006bbe: 4618 mov r0, r3 + 8006bc0: 3710 adds r7, #16 + 8006bc2: 46bd mov sp, r7 + 8006bc4: bd80 pop {r7, pc} + +08006bc6 : + * @param Timeout Timeout duration + * @retval HAL status + */ +HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, + uint32_t Tickstart, uint32_t Timeout) +{ + 8006bc6: b580 push {r7, lr} + 8006bc8: b09c sub sp, #112 ; 0x70 + 8006bca: af00 add r7, sp, #0 + 8006bcc: 60f8 str r0, [r7, #12] + 8006bce: 60b9 str r1, [r7, #8] + 8006bd0: 603b str r3, [r7, #0] + 8006bd2: 4613 mov r3, r2 + 8006bd4: 71fb strb r3, [r7, #7] + /* Wait until flag is set */ + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8006bd6: e0a9 b.n 8006d2c + { + /* Check for the Timeout */ + if (Timeout != HAL_MAX_DELAY) + 8006bd8: 6fbb ldr r3, [r7, #120] ; 0x78 + 8006bda: f1b3 3fff cmp.w r3, #4294967295 + 8006bde: f000 80a5 beq.w 8006d2c + { + if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) + 8006be2: f7fa f89b bl 8000d1c + 8006be6: 4602 mov r2, r0 + 8006be8: 683b ldr r3, [r7, #0] + 8006bea: 1ad3 subs r3, r2, r3 + 8006bec: 6fba ldr r2, [r7, #120] ; 0x78 + 8006bee: 429a cmp r2, r3 + 8006bf0: d302 bcc.n 8006bf8 + 8006bf2: 6fbb ldr r3, [r7, #120] ; 0x78 + 8006bf4: 2b00 cmp r3, #0 + 8006bf6: d140 bne.n 8006c7a + { + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + 8006bf8: 68fb ldr r3, [r7, #12] + 8006bfa: 681b ldr r3, [r3, #0] + 8006bfc: 653b str r3, [r7, #80] ; 0x50 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006bfe: 6d3b ldr r3, [r7, #80] ; 0x50 + 8006c00: e853 3f00 ldrex r3, [r3] + 8006c04: 64fb str r3, [r7, #76] ; 0x4c + return(result); + 8006c06: 6cfb ldr r3, [r7, #76] ; 0x4c + 8006c08: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 8006c0c: 667b str r3, [r7, #100] ; 0x64 + 8006c0e: 68fb ldr r3, [r7, #12] + 8006c10: 681b ldr r3, [r3, #0] + 8006c12: 461a mov r2, r3 + 8006c14: 6e7b ldr r3, [r7, #100] ; 0x64 + 8006c16: 65fb str r3, [r7, #92] ; 0x5c + 8006c18: 65ba str r2, [r7, #88] ; 0x58 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006c1a: 6db9 ldr r1, [r7, #88] ; 0x58 + 8006c1c: 6dfa ldr r2, [r7, #92] ; 0x5c + 8006c1e: e841 2300 strex r3, r2, [r1] + 8006c22: 657b str r3, [r7, #84] ; 0x54 + return(result); + 8006c24: 6d7b ldr r3, [r7, #84] ; 0x54 + 8006c26: 2b00 cmp r3, #0 + 8006c28: d1e6 bne.n 8006bf8 + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006c2a: 68fb ldr r3, [r7, #12] + 8006c2c: 681b ldr r3, [r3, #0] + 8006c2e: 3308 adds r3, #8 + 8006c30: 63fb str r3, [r7, #60] ; 0x3c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006c32: 6bfb ldr r3, [r7, #60] ; 0x3c + 8006c34: e853 3f00 ldrex r3, [r3] + 8006c38: 63bb str r3, [r7, #56] ; 0x38 + return(result); + 8006c3a: 6bbb ldr r3, [r7, #56] ; 0x38 + 8006c3c: f023 0301 bic.w r3, r3, #1 + 8006c40: 663b str r3, [r7, #96] ; 0x60 + 8006c42: 68fb ldr r3, [r7, #12] + 8006c44: 681b ldr r3, [r3, #0] + 8006c46: 3308 adds r3, #8 + 8006c48: 6e3a ldr r2, [r7, #96] ; 0x60 + 8006c4a: 64ba str r2, [r7, #72] ; 0x48 + 8006c4c: 647b str r3, [r7, #68] ; 0x44 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006c4e: 6c79 ldr r1, [r7, #68] ; 0x44 + 8006c50: 6cba ldr r2, [r7, #72] ; 0x48 + 8006c52: e841 2300 strex r3, r2, [r1] + 8006c56: 643b str r3, [r7, #64] ; 0x40 + return(result); + 8006c58: 6c3b ldr r3, [r7, #64] ; 0x40 + 8006c5a: 2b00 cmp r3, #0 + 8006c5c: d1e5 bne.n 8006c2a + + huart->gState = HAL_UART_STATE_READY; + 8006c5e: 68fb ldr r3, [r7, #12] + 8006c60: 2220 movs r2, #32 + 8006c62: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + huart->RxState = HAL_UART_STATE_READY; + 8006c66: 68fb ldr r3, [r7, #12] + 8006c68: 2220 movs r2, #32 + 8006c6a: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + __HAL_UNLOCK(huart); + 8006c6e: 68fb ldr r3, [r7, #12] + 8006c70: 2200 movs r2, #0 + 8006c72: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_TIMEOUT; + 8006c76: 2303 movs r3, #3 + 8006c78: e069 b.n 8006d4e + } + + if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) + 8006c7a: 68fb ldr r3, [r7, #12] + 8006c7c: 681b ldr r3, [r3, #0] + 8006c7e: 681b ldr r3, [r3, #0] + 8006c80: f003 0304 and.w r3, r3, #4 + 8006c84: 2b00 cmp r3, #0 + 8006c86: d051 beq.n 8006d2c + { + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET) + 8006c88: 68fb ldr r3, [r7, #12] + 8006c8a: 681b ldr r3, [r3, #0] + 8006c8c: 69db ldr r3, [r3, #28] + 8006c8e: f403 6300 and.w r3, r3, #2048 ; 0x800 + 8006c92: f5b3 6f00 cmp.w r3, #2048 ; 0x800 + 8006c96: d149 bne.n 8006d2c + { + /* Clear Receiver Timeout flag*/ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_RTOF); + 8006c98: 68fb ldr r3, [r7, #12] + 8006c9a: 681b ldr r3, [r3, #0] + 8006c9c: f44f 6200 mov.w r2, #2048 ; 0x800 + 8006ca0: 621a str r2, [r3, #32] + + /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) + interrupts for the interrupt process */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE | + 8006ca2: 68fb ldr r3, [r7, #12] + 8006ca4: 681b ldr r3, [r3, #0] + 8006ca6: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006ca8: 6abb ldr r3, [r7, #40] ; 0x28 + 8006caa: e853 3f00 ldrex r3, [r3] + 8006cae: 627b str r3, [r7, #36] ; 0x24 + return(result); + 8006cb0: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006cb2: f423 73d0 bic.w r3, r3, #416 ; 0x1a0 + 8006cb6: 66fb str r3, [r7, #108] ; 0x6c + 8006cb8: 68fb ldr r3, [r7, #12] + 8006cba: 681b ldr r3, [r3, #0] + 8006cbc: 461a mov r2, r3 + 8006cbe: 6efb ldr r3, [r7, #108] ; 0x6c + 8006cc0: 637b str r3, [r7, #52] ; 0x34 + 8006cc2: 633a str r2, [r7, #48] ; 0x30 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006cc4: 6b39 ldr r1, [r7, #48] ; 0x30 + 8006cc6: 6b7a ldr r2, [r7, #52] ; 0x34 + 8006cc8: e841 2300 strex r3, r2, [r1] + 8006ccc: 62fb str r3, [r7, #44] ; 0x2c + return(result); + 8006cce: 6afb ldr r3, [r7, #44] ; 0x2c + 8006cd0: 2b00 cmp r3, #0 + 8006cd2: d1e6 bne.n 8006ca2 + USART_CR1_TXEIE_TXFNFIE)); + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006cd4: 68fb ldr r3, [r7, #12] + 8006cd6: 681b ldr r3, [r3, #0] + 8006cd8: 3308 adds r3, #8 + 8006cda: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006cdc: 697b ldr r3, [r7, #20] + 8006cde: e853 3f00 ldrex r3, [r3] + 8006ce2: 613b str r3, [r7, #16] + return(result); + 8006ce4: 693b ldr r3, [r7, #16] + 8006ce6: f023 0301 bic.w r3, r3, #1 + 8006cea: 66bb str r3, [r7, #104] ; 0x68 + 8006cec: 68fb ldr r3, [r7, #12] + 8006cee: 681b ldr r3, [r3, #0] + 8006cf0: 3308 adds r3, #8 + 8006cf2: 6eba ldr r2, [r7, #104] ; 0x68 + 8006cf4: 623a str r2, [r7, #32] + 8006cf6: 61fb str r3, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006cf8: 69f9 ldr r1, [r7, #28] + 8006cfa: 6a3a ldr r2, [r7, #32] + 8006cfc: e841 2300 strex r3, r2, [r1] + 8006d00: 61bb str r3, [r7, #24] + return(result); + 8006d02: 69bb ldr r3, [r7, #24] + 8006d04: 2b00 cmp r3, #0 + 8006d06: d1e5 bne.n 8006cd4 + + huart->gState = HAL_UART_STATE_READY; + 8006d08: 68fb ldr r3, [r7, #12] + 8006d0a: 2220 movs r2, #32 + 8006d0c: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + huart->RxState = HAL_UART_STATE_READY; + 8006d10: 68fb ldr r3, [r7, #12] + 8006d12: 2220 movs r2, #32 + 8006d14: f8c3 208c str.w r2, [r3, #140] ; 0x8c + huart->ErrorCode = HAL_UART_ERROR_RTO; + 8006d18: 68fb ldr r3, [r7, #12] + 8006d1a: 2220 movs r2, #32 + 8006d1c: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8006d20: 68fb ldr r3, [r7, #12] + 8006d22: 2200 movs r2, #0 + 8006d24: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_TIMEOUT; + 8006d28: 2303 movs r3, #3 + 8006d2a: e010 b.n 8006d4e + while ((__HAL_UART_GET_FLAG(huart, Flag) ? SET : RESET) == Status) + 8006d2c: 68fb ldr r3, [r7, #12] + 8006d2e: 681b ldr r3, [r3, #0] + 8006d30: 69da ldr r2, [r3, #28] + 8006d32: 68bb ldr r3, [r7, #8] + 8006d34: 4013 ands r3, r2 + 8006d36: 68ba ldr r2, [r7, #8] + 8006d38: 429a cmp r2, r3 + 8006d3a: bf0c ite eq + 8006d3c: 2301 moveq r3, #1 + 8006d3e: 2300 movne r3, #0 + 8006d40: b2db uxtb r3, r3 + 8006d42: 461a mov r2, r3 + 8006d44: 79fb ldrb r3, [r7, #7] + 8006d46: 429a cmp r2, r3 + 8006d48: f43f af46 beq.w 8006bd8 + } + } + } + } + return HAL_OK; + 8006d4c: 2300 movs r3, #0 +} + 8006d4e: 4618 mov r0, r3 + 8006d50: 3770 adds r7, #112 ; 0x70 + 8006d52: 46bd mov sp, r7 + 8006d54: bd80 pop {r7, pc} + ... + +08006d58 : + * @param pData Pointer to data buffer (u8 or u16 data elements). + * @param Size Amount of data elements (u8 or u16) to be received. + * @retval HAL status + */ +HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) +{ + 8006d58: b480 push {r7} + 8006d5a: b0a3 sub sp, #140 ; 0x8c + 8006d5c: af00 add r7, sp, #0 + 8006d5e: 60f8 str r0, [r7, #12] + 8006d60: 60b9 str r1, [r7, #8] + 8006d62: 4613 mov r3, r2 + 8006d64: 80fb strh r3, [r7, #6] + huart->pRxBuffPtr = pData; + 8006d66: 68fb ldr r3, [r7, #12] + 8006d68: 68ba ldr r2, [r7, #8] + 8006d6a: 659a str r2, [r3, #88] ; 0x58 + huart->RxXferSize = Size; + 8006d6c: 68fb ldr r3, [r7, #12] + 8006d6e: 88fa ldrh r2, [r7, #6] + 8006d70: f8a3 205c strh.w r2, [r3, #92] ; 0x5c + huart->RxXferCount = Size; + 8006d74: 68fb ldr r3, [r7, #12] + 8006d76: 88fa ldrh r2, [r7, #6] + 8006d78: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + huart->RxISR = NULL; + 8006d7c: 68fb ldr r3, [r7, #12] + 8006d7e: 2200 movs r2, #0 + 8006d80: 675a str r2, [r3, #116] ; 0x74 + + /* Computation of UART mask to apply to RDR register */ + UART_MASK_COMPUTATION(huart); + 8006d82: 68fb ldr r3, [r7, #12] + 8006d84: 689b ldr r3, [r3, #8] + 8006d86: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8006d8a: d10e bne.n 8006daa + 8006d8c: 68fb ldr r3, [r7, #12] + 8006d8e: 691b ldr r3, [r3, #16] + 8006d90: 2b00 cmp r3, #0 + 8006d92: d105 bne.n 8006da0 + 8006d94: 68fb ldr r3, [r7, #12] + 8006d96: f240 12ff movw r2, #511 ; 0x1ff + 8006d9a: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8006d9e: e02d b.n 8006dfc + 8006da0: 68fb ldr r3, [r7, #12] + 8006da2: 22ff movs r2, #255 ; 0xff + 8006da4: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8006da8: e028 b.n 8006dfc + 8006daa: 68fb ldr r3, [r7, #12] + 8006dac: 689b ldr r3, [r3, #8] + 8006dae: 2b00 cmp r3, #0 + 8006db0: d10d bne.n 8006dce + 8006db2: 68fb ldr r3, [r7, #12] + 8006db4: 691b ldr r3, [r3, #16] + 8006db6: 2b00 cmp r3, #0 + 8006db8: d104 bne.n 8006dc4 + 8006dba: 68fb ldr r3, [r7, #12] + 8006dbc: 22ff movs r2, #255 ; 0xff + 8006dbe: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8006dc2: e01b b.n 8006dfc + 8006dc4: 68fb ldr r3, [r7, #12] + 8006dc6: 227f movs r2, #127 ; 0x7f + 8006dc8: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8006dcc: e016 b.n 8006dfc + 8006dce: 68fb ldr r3, [r7, #12] + 8006dd0: 689b ldr r3, [r3, #8] + 8006dd2: f1b3 5f80 cmp.w r3, #268435456 ; 0x10000000 + 8006dd6: d10d bne.n 8006df4 + 8006dd8: 68fb ldr r3, [r7, #12] + 8006dda: 691b ldr r3, [r3, #16] + 8006ddc: 2b00 cmp r3, #0 + 8006dde: d104 bne.n 8006dea + 8006de0: 68fb ldr r3, [r7, #12] + 8006de2: 227f movs r2, #127 ; 0x7f + 8006de4: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8006de8: e008 b.n 8006dfc + 8006dea: 68fb ldr r3, [r7, #12] + 8006dec: 223f movs r2, #63 ; 0x3f + 8006dee: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + 8006df2: e003 b.n 8006dfc + 8006df4: 68fb ldr r3, [r7, #12] + 8006df6: 2200 movs r2, #0 + 8006df8: f8a3 2060 strh.w r2, [r3, #96] ; 0x60 + + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8006dfc: 68fb ldr r3, [r7, #12] + 8006dfe: 2200 movs r2, #0 + 8006e00: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + huart->RxState = HAL_UART_STATE_BUSY_RX; + 8006e04: 68fb ldr r3, [r7, #12] + 8006e06: 2222 movs r2, #34 ; 0x22 + 8006e08: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8006e0c: 68fb ldr r3, [r7, #12] + 8006e0e: 681b ldr r3, [r3, #0] + 8006e10: 3308 adds r3, #8 + 8006e12: 667b str r3, [r7, #100] ; 0x64 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006e14: 6e7b ldr r3, [r7, #100] ; 0x64 + 8006e16: e853 3f00 ldrex r3, [r3] + 8006e1a: 663b str r3, [r7, #96] ; 0x60 + return(result); + 8006e1c: 6e3b ldr r3, [r7, #96] ; 0x60 + 8006e1e: f043 0301 orr.w r3, r3, #1 + 8006e22: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 8006e26: 68fb ldr r3, [r7, #12] + 8006e28: 681b ldr r3, [r3, #0] + 8006e2a: 3308 adds r3, #8 + 8006e2c: f8d7 2084 ldr.w r2, [r7, #132] ; 0x84 + 8006e30: 673a str r2, [r7, #112] ; 0x70 + 8006e32: 66fb str r3, [r7, #108] ; 0x6c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006e34: 6ef9 ldr r1, [r7, #108] ; 0x6c + 8006e36: 6f3a ldr r2, [r7, #112] ; 0x70 + 8006e38: e841 2300 strex r3, r2, [r1] + 8006e3c: 66bb str r3, [r7, #104] ; 0x68 + return(result); + 8006e3e: 6ebb ldr r3, [r7, #104] ; 0x68 + 8006e40: 2b00 cmp r3, #0 + 8006e42: d1e3 bne.n 8006e0c + + /* Configure Rx interrupt processing */ + if ((huart->FifoMode == UART_FIFOMODE_ENABLE) && (Size >= huart->NbRxDataToProcess)) + 8006e44: 68fb ldr r3, [r7, #12] + 8006e46: 6e5b ldr r3, [r3, #100] ; 0x64 + 8006e48: f1b3 5f00 cmp.w r3, #536870912 ; 0x20000000 + 8006e4c: d14f bne.n 8006eee + 8006e4e: 68fb ldr r3, [r7, #12] + 8006e50: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 8006e54: 88fa ldrh r2, [r7, #6] + 8006e56: 429a cmp r2, r3 + 8006e58: d349 bcc.n 8006eee + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8006e5a: 68fb ldr r3, [r7, #12] + 8006e5c: 689b ldr r3, [r3, #8] + 8006e5e: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8006e62: d107 bne.n 8006e74 + 8006e64: 68fb ldr r3, [r7, #12] + 8006e66: 691b ldr r3, [r3, #16] + 8006e68: 2b00 cmp r3, #0 + 8006e6a: d103 bne.n 8006e74 + { + huart->RxISR = UART_RxISR_16BIT_FIFOEN; + 8006e6c: 68fb ldr r3, [r7, #12] + 8006e6e: 4a46 ldr r2, [pc, #280] ; (8006f88 ) + 8006e70: 675a str r2, [r3, #116] ; 0x74 + 8006e72: e002 b.n 8006e7a + } + else + { + huart->RxISR = UART_RxISR_8BIT_FIFOEN; + 8006e74: 68fb ldr r3, [r7, #12] + 8006e76: 4a45 ldr r2, [pc, #276] ; (8006f8c ) + 8006e78: 675a str r2, [r3, #116] ; 0x74 + } + + /* Enable the UART Parity Error interrupt and RX FIFO Threshold interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 8006e7a: 68fb ldr r3, [r7, #12] + 8006e7c: 691b ldr r3, [r3, #16] + 8006e7e: 2b00 cmp r3, #0 + 8006e80: d01a beq.n 8006eb8 + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 8006e82: 68fb ldr r3, [r7, #12] + 8006e84: 681b ldr r3, [r3, #0] + 8006e86: 653b str r3, [r7, #80] ; 0x50 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006e88: 6d3b ldr r3, [r7, #80] ; 0x50 + 8006e8a: e853 3f00 ldrex r3, [r3] + 8006e8e: 64fb str r3, [r7, #76] ; 0x4c + return(result); + 8006e90: 6cfb ldr r3, [r7, #76] ; 0x4c + 8006e92: f443 7380 orr.w r3, r3, #256 ; 0x100 + 8006e96: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 8006e9a: 68fb ldr r3, [r7, #12] + 8006e9c: 681b ldr r3, [r3, #0] + 8006e9e: 461a mov r2, r3 + 8006ea0: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 8006ea4: 65fb str r3, [r7, #92] ; 0x5c + 8006ea6: 65ba str r2, [r7, #88] ; 0x58 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006ea8: 6db9 ldr r1, [r7, #88] ; 0x58 + 8006eaa: 6dfa ldr r2, [r7, #92] ; 0x5c + 8006eac: e841 2300 strex r3, r2, [r1] + 8006eb0: 657b str r3, [r7, #84] ; 0x54 + return(result); + 8006eb2: 6d7b ldr r3, [r7, #84] ; 0x54 + 8006eb4: 2b00 cmp r3, #0 + 8006eb6: d1e4 bne.n 8006e82 + } + ATOMIC_SET_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 8006eb8: 68fb ldr r3, [r7, #12] + 8006eba: 681b ldr r3, [r3, #0] + 8006ebc: 3308 adds r3, #8 + 8006ebe: 63fb str r3, [r7, #60] ; 0x3c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006ec0: 6bfb ldr r3, [r7, #60] ; 0x3c + 8006ec2: e853 3f00 ldrex r3, [r3] + 8006ec6: 63bb str r3, [r7, #56] ; 0x38 + return(result); + 8006ec8: 6bbb ldr r3, [r7, #56] ; 0x38 + 8006eca: f043 5380 orr.w r3, r3, #268435456 ; 0x10000000 + 8006ece: 67fb str r3, [r7, #124] ; 0x7c + 8006ed0: 68fb ldr r3, [r7, #12] + 8006ed2: 681b ldr r3, [r3, #0] + 8006ed4: 3308 adds r3, #8 + 8006ed6: 6ffa ldr r2, [r7, #124] ; 0x7c + 8006ed8: 64ba str r2, [r7, #72] ; 0x48 + 8006eda: 647b str r3, [r7, #68] ; 0x44 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006edc: 6c79 ldr r1, [r7, #68] ; 0x44 + 8006ede: 6cba ldr r2, [r7, #72] ; 0x48 + 8006ee0: e841 2300 strex r3, r2, [r1] + 8006ee4: 643b str r3, [r7, #64] ; 0x40 + return(result); + 8006ee6: 6c3b ldr r3, [r7, #64] ; 0x40 + 8006ee8: 2b00 cmp r3, #0 + 8006eea: d1e5 bne.n 8006eb8 + 8006eec: e046 b.n 8006f7c + } + else + { + /* Set the Rx ISR function pointer according to the data word length */ + if ((huart->Init.WordLength == UART_WORDLENGTH_9B) && (huart->Init.Parity == UART_PARITY_NONE)) + 8006eee: 68fb ldr r3, [r7, #12] + 8006ef0: 689b ldr r3, [r3, #8] + 8006ef2: f5b3 5f80 cmp.w r3, #4096 ; 0x1000 + 8006ef6: d107 bne.n 8006f08 + 8006ef8: 68fb ldr r3, [r7, #12] + 8006efa: 691b ldr r3, [r3, #16] + 8006efc: 2b00 cmp r3, #0 + 8006efe: d103 bne.n 8006f08 + { + huart->RxISR = UART_RxISR_16BIT; + 8006f00: 68fb ldr r3, [r7, #12] + 8006f02: 4a23 ldr r2, [pc, #140] ; (8006f90 ) + 8006f04: 675a str r2, [r3, #116] ; 0x74 + 8006f06: e002 b.n 8006f0e + } + else + { + huart->RxISR = UART_RxISR_8BIT; + 8006f08: 68fb ldr r3, [r7, #12] + 8006f0a: 4a22 ldr r2, [pc, #136] ; (8006f94 ) + 8006f0c: 675a str r2, [r3, #116] ; 0x74 + } + + /* Enable the UART Parity Error interrupt and Data Register Not Empty interrupt */ + if (huart->Init.Parity != UART_PARITY_NONE) + 8006f0e: 68fb ldr r3, [r7, #12] + 8006f10: 691b ldr r3, [r3, #16] + 8006f12: 2b00 cmp r3, #0 + 8006f14: d019 beq.n 8006f4a + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_PEIE | USART_CR1_RXNEIE_RXFNEIE); + 8006f16: 68fb ldr r3, [r7, #12] + 8006f18: 681b ldr r3, [r3, #0] + 8006f1a: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006f1c: 6abb ldr r3, [r7, #40] ; 0x28 + 8006f1e: e853 3f00 ldrex r3, [r3] + 8006f22: 627b str r3, [r7, #36] ; 0x24 + return(result); + 8006f24: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006f26: f443 7390 orr.w r3, r3, #288 ; 0x120 + 8006f2a: 677b str r3, [r7, #116] ; 0x74 + 8006f2c: 68fb ldr r3, [r7, #12] + 8006f2e: 681b ldr r3, [r3, #0] + 8006f30: 461a mov r2, r3 + 8006f32: 6f7b ldr r3, [r7, #116] ; 0x74 + 8006f34: 637b str r3, [r7, #52] ; 0x34 + 8006f36: 633a str r2, [r7, #48] ; 0x30 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006f38: 6b39 ldr r1, [r7, #48] ; 0x30 + 8006f3a: 6b7a ldr r2, [r7, #52] ; 0x34 + 8006f3c: e841 2300 strex r3, r2, [r1] + 8006f40: 62fb str r3, [r7, #44] ; 0x2c + return(result); + 8006f42: 6afb ldr r3, [r7, #44] ; 0x2c + 8006f44: 2b00 cmp r3, #0 + 8006f46: d1e6 bne.n 8006f16 + 8006f48: e018 b.n 8006f7c + } + else + { + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8006f4a: 68fb ldr r3, [r7, #12] + 8006f4c: 681b ldr r3, [r3, #0] + 8006f4e: 617b str r3, [r7, #20] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006f50: 697b ldr r3, [r7, #20] + 8006f52: e853 3f00 ldrex r3, [r3] + 8006f56: 613b str r3, [r7, #16] + return(result); + 8006f58: 693b ldr r3, [r7, #16] + 8006f5a: f043 0320 orr.w r3, r3, #32 + 8006f5e: 67bb str r3, [r7, #120] ; 0x78 + 8006f60: 68fb ldr r3, [r7, #12] + 8006f62: 681b ldr r3, [r3, #0] + 8006f64: 461a mov r2, r3 + 8006f66: 6fbb ldr r3, [r7, #120] ; 0x78 + 8006f68: 623b str r3, [r7, #32] + 8006f6a: 61fa str r2, [r7, #28] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006f6c: 69f9 ldr r1, [r7, #28] + 8006f6e: 6a3a ldr r2, [r7, #32] + 8006f70: e841 2300 strex r3, r2, [r1] + 8006f74: 61bb str r3, [r7, #24] + return(result); + 8006f76: 69bb ldr r3, [r7, #24] + 8006f78: 2b00 cmp r3, #0 + 8006f7a: d1e6 bne.n 8006f4a + } + } + return HAL_OK; + 8006f7c: 2300 movs r3, #0 +} + 8006f7e: 4618 mov r0, r3 + 8006f80: 378c adds r7, #140 ; 0x8c + 8006f82: 46bd mov sp, r7 + 8006f84: bc80 pop {r7} + 8006f86: 4770 bx lr + 8006f88: 0800796d .word 0x0800796d + 8006f8c: 0800760d .word 0x0800760d + 8006f90: 08007455 .word 0x08007455 + 8006f94: 0800729d .word 0x0800729d + +08006f98 : + * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndTxTransfer(UART_HandleTypeDef *huart) +{ + 8006f98: b480 push {r7} + 8006f9a: b08f sub sp, #60 ; 0x3c + 8006f9c: af00 add r7, sp, #0 + 8006f9e: 6078 str r0, [r7, #4] + /* Disable TXEIE, TCIE, TXFT interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_TXEIE_TXFNFIE | USART_CR1_TCIE)); + 8006fa0: 687b ldr r3, [r7, #4] + 8006fa2: 681b ldr r3, [r3, #0] + 8006fa4: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006fa6: 6a3b ldr r3, [r7, #32] + 8006fa8: e853 3f00 ldrex r3, [r3] + 8006fac: 61fb str r3, [r7, #28] + return(result); + 8006fae: 69fb ldr r3, [r7, #28] + 8006fb0: f023 03c0 bic.w r3, r3, #192 ; 0xc0 + 8006fb4: 637b str r3, [r7, #52] ; 0x34 + 8006fb6: 687b ldr r3, [r7, #4] + 8006fb8: 681b ldr r3, [r3, #0] + 8006fba: 461a mov r2, r3 + 8006fbc: 6b7b ldr r3, [r7, #52] ; 0x34 + 8006fbe: 62fb str r3, [r7, #44] ; 0x2c + 8006fc0: 62ba str r2, [r7, #40] ; 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006fc2: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8006fc4: 6afa ldr r2, [r7, #44] ; 0x2c + 8006fc6: e841 2300 strex r3, r2, [r1] + 8006fca: 627b str r3, [r7, #36] ; 0x24 + return(result); + 8006fcc: 6a7b ldr r3, [r7, #36] ; 0x24 + 8006fce: 2b00 cmp r3, #0 + 8006fd0: d1e6 bne.n 8006fa0 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_TXFTIE)); + 8006fd2: 687b ldr r3, [r7, #4] + 8006fd4: 681b ldr r3, [r3, #0] + 8006fd6: 3308 adds r3, #8 + 8006fd8: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8006fda: 68fb ldr r3, [r7, #12] + 8006fdc: e853 3f00 ldrex r3, [r3] + 8006fe0: 60bb str r3, [r7, #8] + return(result); + 8006fe2: 68bb ldr r3, [r7, #8] + 8006fe4: f423 0300 bic.w r3, r3, #8388608 ; 0x800000 + 8006fe8: 633b str r3, [r7, #48] ; 0x30 + 8006fea: 687b ldr r3, [r7, #4] + 8006fec: 681b ldr r3, [r3, #0] + 8006fee: 3308 adds r3, #8 + 8006ff0: 6b3a ldr r2, [r7, #48] ; 0x30 + 8006ff2: 61ba str r2, [r7, #24] + 8006ff4: 617b str r3, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8006ff6: 6979 ldr r1, [r7, #20] + 8006ff8: 69ba ldr r2, [r7, #24] + 8006ffa: e841 2300 strex r3, r2, [r1] + 8006ffe: 613b str r3, [r7, #16] + return(result); + 8007000: 693b ldr r3, [r7, #16] + 8007002: 2b00 cmp r3, #0 + 8007004: d1e5 bne.n 8006fd2 + + /* At end of Tx process, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 8007006: 687b ldr r3, [r7, #4] + 8007008: 2220 movs r2, #32 + 800700a: f8c3 2088 str.w r2, [r3, #136] ; 0x88 +} + 800700e: bf00 nop + 8007010: 373c adds r7, #60 ; 0x3c + 8007012: 46bd mov sp, r7 + 8007014: bc80 pop {r7} + 8007016: 4770 bx lr + +08007018 : + * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). + * @param huart UART handle. + * @retval None + */ +static void UART_EndRxTransfer(UART_HandleTypeDef *huart) +{ + 8007018: b480 push {r7} + 800701a: b095 sub sp, #84 ; 0x54 + 800701c: af00 add r7, sp, #0 + 800701e: 6078 str r0, [r7, #4] + /* Disable RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8007020: 687b ldr r3, [r7, #4] + 8007022: 681b ldr r3, [r3, #0] + 8007024: 637b str r3, [r7, #52] ; 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007026: 6b7b ldr r3, [r7, #52] ; 0x34 + 8007028: e853 3f00 ldrex r3, [r3] + 800702c: 633b str r3, [r7, #48] ; 0x30 + return(result); + 800702e: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007030: f423 7390 bic.w r3, r3, #288 ; 0x120 + 8007034: 64fb str r3, [r7, #76] ; 0x4c + 8007036: 687b ldr r3, [r7, #4] + 8007038: 681b ldr r3, [r3, #0] + 800703a: 461a mov r2, r3 + 800703c: 6cfb ldr r3, [r7, #76] ; 0x4c + 800703e: 643b str r3, [r7, #64] ; 0x40 + 8007040: 63fa str r2, [r7, #60] ; 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007042: 6bf9 ldr r1, [r7, #60] ; 0x3c + 8007044: 6c3a ldr r2, [r7, #64] ; 0x40 + 8007046: e841 2300 strex r3, r2, [r1] + 800704a: 63bb str r3, [r7, #56] ; 0x38 + return(result); + 800704c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800704e: 2b00 cmp r3, #0 + 8007050: d1e6 bne.n 8007020 + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8007052: 687b ldr r3, [r7, #4] + 8007054: 681b ldr r3, [r3, #0] + 8007056: 3308 adds r3, #8 + 8007058: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800705a: 6a3b ldr r3, [r7, #32] + 800705c: e853 3f00 ldrex r3, [r3] + 8007060: 61fb str r3, [r7, #28] + return(result); + 8007062: 69fb ldr r3, [r7, #28] + 8007064: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8007068: f023 0301 bic.w r3, r3, #1 + 800706c: 64bb str r3, [r7, #72] ; 0x48 + 800706e: 687b ldr r3, [r7, #4] + 8007070: 681b ldr r3, [r3, #0] + 8007072: 3308 adds r3, #8 + 8007074: 6cba ldr r2, [r7, #72] ; 0x48 + 8007076: 62fa str r2, [r7, #44] ; 0x2c + 8007078: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800707a: 6ab9 ldr r1, [r7, #40] ; 0x28 + 800707c: 6afa ldr r2, [r7, #44] ; 0x2c + 800707e: e841 2300 strex r3, r2, [r1] + 8007082: 627b str r3, [r7, #36] ; 0x24 + return(result); + 8007084: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007086: 2b00 cmp r3, #0 + 8007088: d1e3 bne.n 8007052 + + /* In case of reception waiting for IDLE event, disable also the IDLE IE interrupt source */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 800708a: 687b ldr r3, [r7, #4] + 800708c: 6edb ldr r3, [r3, #108] ; 0x6c + 800708e: 2b01 cmp r3, #1 + 8007090: d118 bne.n 80070c4 + { + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8007092: 687b ldr r3, [r7, #4] + 8007094: 681b ldr r3, [r3, #0] + 8007096: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007098: 68fb ldr r3, [r7, #12] + 800709a: e853 3f00 ldrex r3, [r3] + 800709e: 60bb str r3, [r7, #8] + return(result); + 80070a0: 68bb ldr r3, [r7, #8] + 80070a2: f023 0310 bic.w r3, r3, #16 + 80070a6: 647b str r3, [r7, #68] ; 0x44 + 80070a8: 687b ldr r3, [r7, #4] + 80070aa: 681b ldr r3, [r3, #0] + 80070ac: 461a mov r2, r3 + 80070ae: 6c7b ldr r3, [r7, #68] ; 0x44 + 80070b0: 61bb str r3, [r7, #24] + 80070b2: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80070b4: 6979 ldr r1, [r7, #20] + 80070b6: 69ba ldr r2, [r7, #24] + 80070b8: e841 2300 strex r3, r2, [r1] + 80070bc: 613b str r3, [r7, #16] + return(result); + 80070be: 693b ldr r3, [r7, #16] + 80070c0: 2b00 cmp r3, #0 + 80070c2: d1e6 bne.n 8007092 + } + + /* At end of Rx process, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80070c4: 687b ldr r3, [r7, #4] + 80070c6: 2220 movs r2, #32 + 80070c8: f8c3 208c str.w r2, [r3, #140] ; 0x8c + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80070cc: 687b ldr r3, [r7, #4] + 80070ce: 2200 movs r2, #0 + 80070d0: 66da str r2, [r3, #108] ; 0x6c + + /* Reset RxIsr function pointer */ + huart->RxISR = NULL; + 80070d2: 687b ldr r3, [r7, #4] + 80070d4: 2200 movs r2, #0 + 80070d6: 675a str r2, [r3, #116] ; 0x74 +} + 80070d8: bf00 nop + 80070da: 3754 adds r7, #84 ; 0x54 + 80070dc: 46bd mov sp, r7 + 80070de: bc80 pop {r7} + 80070e0: 4770 bx lr + +080070e2 : + * @brief DMA UART transmit process complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) +{ + 80070e2: b580 push {r7, lr} + 80070e4: b090 sub sp, #64 ; 0x40 + 80070e6: af00 add r7, sp, #0 + 80070e8: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80070ea: 687b ldr r3, [r7, #4] + 80070ec: 6a9b ldr r3, [r3, #40] ; 0x28 + 80070ee: 63fb str r3, [r7, #60] ; 0x3c + + /* DMA Normal mode */ + if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) + 80070f0: 687b ldr r3, [r7, #4] + 80070f2: 681b ldr r3, [r3, #0] + 80070f4: 681b ldr r3, [r3, #0] + 80070f6: f003 0320 and.w r3, r3, #32 + 80070fa: 2b00 cmp r3, #0 + 80070fc: d137 bne.n 800716e + { + huart->TxXferCount = 0U; + 80070fe: 6bfb ldr r3, [r7, #60] ; 0x3c + 8007100: 2200 movs r2, #0 + 8007102: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 + + /* Disable the DMA transfer for transmit request by resetting the DMAT bit + in the UART CR3 register */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); + 8007106: 6bfb ldr r3, [r7, #60] ; 0x3c + 8007108: 681b ldr r3, [r3, #0] + 800710a: 3308 adds r3, #8 + 800710c: 627b str r3, [r7, #36] ; 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800710e: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007110: e853 3f00 ldrex r3, [r3] + 8007114: 623b str r3, [r7, #32] + return(result); + 8007116: 6a3b ldr r3, [r7, #32] + 8007118: f023 0380 bic.w r3, r3, #128 ; 0x80 + 800711c: 63bb str r3, [r7, #56] ; 0x38 + 800711e: 6bfb ldr r3, [r7, #60] ; 0x3c + 8007120: 681b ldr r3, [r3, #0] + 8007122: 3308 adds r3, #8 + 8007124: 6bba ldr r2, [r7, #56] ; 0x38 + 8007126: 633a str r2, [r7, #48] ; 0x30 + 8007128: 62fb str r3, [r7, #44] ; 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800712a: 6af9 ldr r1, [r7, #44] ; 0x2c + 800712c: 6b3a ldr r2, [r7, #48] ; 0x30 + 800712e: e841 2300 strex r3, r2, [r1] + 8007132: 62bb str r3, [r7, #40] ; 0x28 + return(result); + 8007134: 6abb ldr r3, [r7, #40] ; 0x28 + 8007136: 2b00 cmp r3, #0 + 8007138: d1e5 bne.n 8007106 + + /* Enable the UART Transmit Complete Interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 800713a: 6bfb ldr r3, [r7, #60] ; 0x3c + 800713c: 681b ldr r3, [r3, #0] + 800713e: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007140: 693b ldr r3, [r7, #16] + 8007142: e853 3f00 ldrex r3, [r3] + 8007146: 60fb str r3, [r7, #12] + return(result); + 8007148: 68fb ldr r3, [r7, #12] + 800714a: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800714e: 637b str r3, [r7, #52] ; 0x34 + 8007150: 6bfb ldr r3, [r7, #60] ; 0x3c + 8007152: 681b ldr r3, [r3, #0] + 8007154: 461a mov r2, r3 + 8007156: 6b7b ldr r3, [r7, #52] ; 0x34 + 8007158: 61fb str r3, [r7, #28] + 800715a: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800715c: 69b9 ldr r1, [r7, #24] + 800715e: 69fa ldr r2, [r7, #28] + 8007160: e841 2300 strex r3, r2, [r1] + 8007164: 617b str r3, [r7, #20] + return(result); + 8007166: 697b ldr r3, [r7, #20] + 8007168: 2b00 cmp r3, #0 + 800716a: d1e6 bne.n 800713a +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + } +} + 800716c: e002 b.n 8007174 + HAL_UART_TxCpltCallback(huart); + 800716e: 6bf8 ldr r0, [r7, #60] ; 0x3c + 8007170: f7fa fc32 bl 80019d8 +} + 8007174: bf00 nop + 8007176: 3740 adds r7, #64 ; 0x40 + 8007178: 46bd mov sp, r7 + 800717a: bd80 pop {r7, pc} + +0800717c : + * @brief DMA UART transmit process half complete callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) +{ + 800717c: b580 push {r7, lr} + 800717e: b084 sub sp, #16 + 8007180: af00 add r7, sp, #0 + 8007182: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8007184: 687b ldr r3, [r7, #4] + 8007186: 6a9b ldr r3, [r3, #40] ; 0x28 + 8007188: 60fb str r3, [r7, #12] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx Half complete callback*/ + huart->TxHalfCpltCallback(huart); +#else + /*Call legacy weak Tx Half complete callback*/ + HAL_UART_TxHalfCpltCallback(huart); + 800718a: 68f8 ldr r0, [r7, #12] + 800718c: f7ff f99a bl 80064c4 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8007190: bf00 nop + 8007192: 3710 adds r7, #16 + 8007194: 46bd mov sp, r7 + 8007196: bd80 pop {r7, pc} + +08007198 : + * @brief DMA UART communication error callback. + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAError(DMA_HandleTypeDef *hdma) +{ + 8007198: b580 push {r7, lr} + 800719a: b086 sub sp, #24 + 800719c: af00 add r7, sp, #0 + 800719e: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 80071a0: 687b ldr r3, [r7, #4] + 80071a2: 6a9b ldr r3, [r3, #40] ; 0x28 + 80071a4: 617b str r3, [r7, #20] + + const HAL_UART_StateTypeDef gstate = huart->gState; + 80071a6: 697b ldr r3, [r7, #20] + 80071a8: f8d3 3088 ldr.w r3, [r3, #136] ; 0x88 + 80071ac: 613b str r3, [r7, #16] + const HAL_UART_StateTypeDef rxstate = huart->RxState; + 80071ae: 697b ldr r3, [r7, #20] + 80071b0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80071b4: 60fb str r3, [r7, #12] + + /* Stop UART DMA Tx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && + 80071b6: 697b ldr r3, [r7, #20] + 80071b8: 681b ldr r3, [r3, #0] + 80071ba: 689b ldr r3, [r3, #8] + 80071bc: f003 0380 and.w r3, r3, #128 ; 0x80 + 80071c0: 2b80 cmp r3, #128 ; 0x80 + 80071c2: d109 bne.n 80071d8 + 80071c4: 693b ldr r3, [r7, #16] + 80071c6: 2b21 cmp r3, #33 ; 0x21 + 80071c8: d106 bne.n 80071d8 + (gstate == HAL_UART_STATE_BUSY_TX)) + { + huart->TxXferCount = 0U; + 80071ca: 697b ldr r3, [r7, #20] + 80071cc: 2200 movs r2, #0 + 80071ce: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 + UART_EndTxTransfer(huart); + 80071d2: 6978 ldr r0, [r7, #20] + 80071d4: f7ff fee0 bl 8006f98 + } + + /* Stop UART DMA Rx request if ongoing */ + if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && + 80071d8: 697b ldr r3, [r7, #20] + 80071da: 681b ldr r3, [r3, #0] + 80071dc: 689b ldr r3, [r3, #8] + 80071de: f003 0340 and.w r3, r3, #64 ; 0x40 + 80071e2: 2b40 cmp r3, #64 ; 0x40 + 80071e4: d109 bne.n 80071fa + 80071e6: 68fb ldr r3, [r7, #12] + 80071e8: 2b22 cmp r3, #34 ; 0x22 + 80071ea: d106 bne.n 80071fa + (rxstate == HAL_UART_STATE_BUSY_RX)) + { + huart->RxXferCount = 0U; + 80071ec: 697b ldr r3, [r7, #20] + 80071ee: 2200 movs r2, #0 + 80071f0: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + UART_EndRxTransfer(huart); + 80071f4: 6978 ldr r0, [r7, #20] + 80071f6: f7ff ff0f bl 8007018 + } + + huart->ErrorCode |= HAL_UART_ERROR_DMA; + 80071fa: 697b ldr r3, [r7, #20] + 80071fc: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007200: f043 0210 orr.w r2, r3, #16 + 8007204: 697b ldr r3, [r7, #20] + 8007206: f8c3 2090 str.w r2, [r3, #144] ; 0x90 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 800720a: 6978 ldr r0, [r7, #20] + 800720c: f7ff f963 bl 80064d6 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8007210: bf00 nop + 8007212: 3718 adds r7, #24 + 8007214: 46bd mov sp, r7 + 8007216: bd80 pop {r7, pc} + +08007218 : + * (To be called at end of DMA Abort procedure following error occurrence). + * @param hdma DMA handle. + * @retval None + */ +static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) +{ + 8007218: b580 push {r7, lr} + 800721a: b084 sub sp, #16 + 800721c: af00 add r7, sp, #0 + 800721e: 6078 str r0, [r7, #4] + UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); + 8007220: 687b ldr r3, [r7, #4] + 8007222: 6a9b ldr r3, [r3, #40] ; 0x28 + 8007224: 60fb str r3, [r7, #12] + huart->RxXferCount = 0U; + 8007226: 68fb ldr r3, [r7, #12] + 8007228: 2200 movs r2, #0 + 800722a: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + huart->TxXferCount = 0U; + 800722e: 68fb ldr r3, [r7, #12] + 8007230: 2200 movs r2, #0 + 8007232: f8a3 2056 strh.w r2, [r3, #86] ; 0x56 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8007236: 68f8 ldr r0, [r7, #12] + 8007238: f7ff f94d bl 80064d6 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 800723c: bf00 nop + 800723e: 3710 adds r7, #16 + 8007240: 46bd mov sp, r7 + 8007242: bd80 pop {r7, pc} + +08007244 : + * @param huart pointer to a UART_HandleTypeDef structure that contains + * the configuration information for the specified UART module. + * @retval None + */ +static void UART_EndTransmit_IT(UART_HandleTypeDef *huart) +{ + 8007244: b580 push {r7, lr} + 8007246: b088 sub sp, #32 + 8007248: af00 add r7, sp, #0 + 800724a: 6078 str r0, [r7, #4] + /* Disable the UART Transmit Complete Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_TCIE); + 800724c: 687b ldr r3, [r7, #4] + 800724e: 681b ldr r3, [r3, #0] + 8007250: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007252: 68fb ldr r3, [r7, #12] + 8007254: e853 3f00 ldrex r3, [r3] + 8007258: 60bb str r3, [r7, #8] + return(result); + 800725a: 68bb ldr r3, [r7, #8] + 800725c: f023 0340 bic.w r3, r3, #64 ; 0x40 + 8007260: 61fb str r3, [r7, #28] + 8007262: 687b ldr r3, [r7, #4] + 8007264: 681b ldr r3, [r3, #0] + 8007266: 461a mov r2, r3 + 8007268: 69fb ldr r3, [r7, #28] + 800726a: 61bb str r3, [r7, #24] + 800726c: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800726e: 6979 ldr r1, [r7, #20] + 8007270: 69ba ldr r2, [r7, #24] + 8007272: e841 2300 strex r3, r2, [r1] + 8007276: 613b str r3, [r7, #16] + return(result); + 8007278: 693b ldr r3, [r7, #16] + 800727a: 2b00 cmp r3, #0 + 800727c: d1e6 bne.n 800724c + + /* Tx process is ended, restore huart->gState to Ready */ + huart->gState = HAL_UART_STATE_READY; + 800727e: 687b ldr r3, [r7, #4] + 8007280: 2220 movs r2, #32 + 8007282: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Cleat TxISR function pointer */ + huart->TxISR = NULL; + 8007286: 687b ldr r3, [r7, #4] + 8007288: 2200 movs r2, #0 + 800728a: 679a str r2, [r3, #120] ; 0x78 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Tx complete callback*/ + huart->TxCpltCallback(huart); +#else + /*Call legacy weak Tx complete callback*/ + HAL_UART_TxCpltCallback(huart); + 800728c: 6878 ldr r0, [r7, #4] + 800728e: f7fa fba3 bl 80019d8 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ +} + 8007292: bf00 nop + 8007294: 3720 adds r7, #32 + 8007296: 46bd mov sp, r7 + 8007298: bd80 pop {r7, pc} + ... + +0800729c : + * @brief RX interrupt handler for 7 or 8 bits data word length . + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT(UART_HandleTypeDef *huart) +{ + 800729c: b580 push {r7, lr} + 800729e: b09c sub sp, #112 ; 0x70 + 80072a0: af00 add r7, sp, #0 + 80072a2: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 80072a4: 687b ldr r3, [r7, #4] + 80072a6: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 80072aa: f8a7 306e strh.w r3, [r7, #110] ; 0x6e + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 80072ae: 687b ldr r3, [r7, #4] + 80072b0: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80072b4: 2b22 cmp r3, #34 ; 0x22 + 80072b6: f040 80be bne.w 8007436 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80072ba: 687b ldr r3, [r7, #4] + 80072bc: 681b ldr r3, [r3, #0] + 80072be: 6a5b ldr r3, [r3, #36] ; 0x24 + 80072c0: f8a7 306c strh.w r3, [r7, #108] ; 0x6c + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 80072c4: f8b7 306c ldrh.w r3, [r7, #108] ; 0x6c + 80072c8: b2d9 uxtb r1, r3 + 80072ca: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e + 80072ce: b2da uxtb r2, r3 + 80072d0: 687b ldr r3, [r7, #4] + 80072d2: 6d9b ldr r3, [r3, #88] ; 0x58 + 80072d4: 400a ands r2, r1 + 80072d6: b2d2 uxtb r2, r2 + 80072d8: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 80072da: 687b ldr r3, [r7, #4] + 80072dc: 6d9b ldr r3, [r3, #88] ; 0x58 + 80072de: 1c5a adds r2, r3, #1 + 80072e0: 687b ldr r3, [r7, #4] + 80072e2: 659a str r2, [r3, #88] ; 0x58 + huart->RxXferCount--; + 80072e4: 687b ldr r3, [r7, #4] + 80072e6: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80072ea: b29b uxth r3, r3 + 80072ec: 3b01 subs r3, #1 + 80072ee: b29a uxth r2, r3 + 80072f0: 687b ldr r3, [r7, #4] + 80072f2: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + + if (huart->RxXferCount == 0U) + 80072f6: 687b ldr r3, [r7, #4] + 80072f8: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80072fc: b29b uxth r3, r3 + 80072fe: 2b00 cmp r3, #0 + 8007300: f040 80a1 bne.w 8007446 + { + /* Disable the UART Parity Error Interrupt and RXNE interrupts */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 8007304: 687b ldr r3, [r7, #4] + 8007306: 681b ldr r3, [r3, #0] + 8007308: 64fb str r3, [r7, #76] ; 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800730a: 6cfb ldr r3, [r7, #76] ; 0x4c + 800730c: e853 3f00 ldrex r3, [r3] + 8007310: 64bb str r3, [r7, #72] ; 0x48 + return(result); + 8007312: 6cbb ldr r3, [r7, #72] ; 0x48 + 8007314: f423 7390 bic.w r3, r3, #288 ; 0x120 + 8007318: 66bb str r3, [r7, #104] ; 0x68 + 800731a: 687b ldr r3, [r7, #4] + 800731c: 681b ldr r3, [r3, #0] + 800731e: 461a mov r2, r3 + 8007320: 6ebb ldr r3, [r7, #104] ; 0x68 + 8007322: 65bb str r3, [r7, #88] ; 0x58 + 8007324: 657a str r2, [r7, #84] ; 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007326: 6d79 ldr r1, [r7, #84] ; 0x54 + 8007328: 6dba ldr r2, [r7, #88] ; 0x58 + 800732a: e841 2300 strex r3, r2, [r1] + 800732e: 653b str r3, [r7, #80] ; 0x50 + return(result); + 8007330: 6d3b ldr r3, [r7, #80] ; 0x50 + 8007332: 2b00 cmp r3, #0 + 8007334: d1e6 bne.n 8007304 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 8007336: 687b ldr r3, [r7, #4] + 8007338: 681b ldr r3, [r3, #0] + 800733a: 3308 adds r3, #8 + 800733c: 63bb str r3, [r7, #56] ; 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800733e: 6bbb ldr r3, [r7, #56] ; 0x38 + 8007340: e853 3f00 ldrex r3, [r3] + 8007344: 637b str r3, [r7, #52] ; 0x34 + return(result); + 8007346: 6b7b ldr r3, [r7, #52] ; 0x34 + 8007348: f023 0301 bic.w r3, r3, #1 + 800734c: 667b str r3, [r7, #100] ; 0x64 + 800734e: 687b ldr r3, [r7, #4] + 8007350: 681b ldr r3, [r3, #0] + 8007352: 3308 adds r3, #8 + 8007354: 6e7a ldr r2, [r7, #100] ; 0x64 + 8007356: 647a str r2, [r7, #68] ; 0x44 + 8007358: 643b str r3, [r7, #64] ; 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800735a: 6c39 ldr r1, [r7, #64] ; 0x40 + 800735c: 6c7a ldr r2, [r7, #68] ; 0x44 + 800735e: e841 2300 strex r3, r2, [r1] + 8007362: 63fb str r3, [r7, #60] ; 0x3c + return(result); + 8007364: 6bfb ldr r3, [r7, #60] ; 0x3c + 8007366: 2b00 cmp r3, #0 + 8007368: d1e5 bne.n 8007336 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 800736a: 687b ldr r3, [r7, #4] + 800736c: 2220 movs r2, #32 + 800736e: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8007372: 687b ldr r3, [r7, #4] + 8007374: 2200 movs r2, #0 + 8007376: 675a str r2, [r3, #116] ; 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8007378: 687b ldr r3, [r7, #4] + 800737a: 2200 movs r2, #0 + 800737c: 671a str r2, [r3, #112] ; 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 800737e: 687b ldr r3, [r7, #4] + 8007380: 681b ldr r3, [r3, #0] + 8007382: 4a33 ldr r2, [pc, #204] ; (8007450 ) + 8007384: 4293 cmp r3, r2 + 8007386: d01f beq.n 80073c8 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8007388: 687b ldr r3, [r7, #4] + 800738a: 681b ldr r3, [r3, #0] + 800738c: 685b ldr r3, [r3, #4] + 800738e: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8007392: 2b00 cmp r3, #0 + 8007394: d018 beq.n 80073c8 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8007396: 687b ldr r3, [r7, #4] + 8007398: 681b ldr r3, [r3, #0] + 800739a: 627b str r3, [r7, #36] ; 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800739c: 6a7b ldr r3, [r7, #36] ; 0x24 + 800739e: e853 3f00 ldrex r3, [r3] + 80073a2: 623b str r3, [r7, #32] + return(result); + 80073a4: 6a3b ldr r3, [r7, #32] + 80073a6: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 80073aa: 663b str r3, [r7, #96] ; 0x60 + 80073ac: 687b ldr r3, [r7, #4] + 80073ae: 681b ldr r3, [r3, #0] + 80073b0: 461a mov r2, r3 + 80073b2: 6e3b ldr r3, [r7, #96] ; 0x60 + 80073b4: 633b str r3, [r7, #48] ; 0x30 + 80073b6: 62fa str r2, [r7, #44] ; 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80073b8: 6af9 ldr r1, [r7, #44] ; 0x2c + 80073ba: 6b3a ldr r2, [r7, #48] ; 0x30 + 80073bc: e841 2300 strex r3, r2, [r1] + 80073c0: 62bb str r3, [r7, #40] ; 0x28 + return(result); + 80073c2: 6abb ldr r3, [r7, #40] ; 0x28 + 80073c4: 2b00 cmp r3, #0 + 80073c6: d1e6 bne.n 8007396 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 80073c8: 687b ldr r3, [r7, #4] + 80073ca: 6edb ldr r3, [r3, #108] ; 0x6c + 80073cc: 2b01 cmp r3, #1 + 80073ce: d12e bne.n 800742e + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 80073d0: 687b ldr r3, [r7, #4] + 80073d2: 2200 movs r2, #0 + 80073d4: 66da str r2, [r3, #108] ; 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 80073d6: 687b ldr r3, [r7, #4] + 80073d8: 681b ldr r3, [r3, #0] + 80073da: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80073dc: 693b ldr r3, [r7, #16] + 80073de: e853 3f00 ldrex r3, [r3] + 80073e2: 60fb str r3, [r7, #12] + return(result); + 80073e4: 68fb ldr r3, [r7, #12] + 80073e6: f023 0310 bic.w r3, r3, #16 + 80073ea: 65fb str r3, [r7, #92] ; 0x5c + 80073ec: 687b ldr r3, [r7, #4] + 80073ee: 681b ldr r3, [r3, #0] + 80073f0: 461a mov r2, r3 + 80073f2: 6dfb ldr r3, [r7, #92] ; 0x5c + 80073f4: 61fb str r3, [r7, #28] + 80073f6: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80073f8: 69b9 ldr r1, [r7, #24] + 80073fa: 69fa ldr r2, [r7, #28] + 80073fc: e841 2300 strex r3, r2, [r1] + 8007400: 617b str r3, [r7, #20] + return(result); + 8007402: 697b ldr r3, [r7, #20] + 8007404: 2b00 cmp r3, #0 + 8007406: d1e6 bne.n 80073d6 + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8007408: 687b ldr r3, [r7, #4] + 800740a: 681b ldr r3, [r3, #0] + 800740c: 69db ldr r3, [r3, #28] + 800740e: f003 0310 and.w r3, r3, #16 + 8007412: 2b10 cmp r3, #16 + 8007414: d103 bne.n 800741e + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8007416: 687b ldr r3, [r7, #4] + 8007418: 681b ldr r3, [r3, #0] + 800741a: 2210 movs r2, #16 + 800741c: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 800741e: 687b ldr r3, [r7, #4] + 8007420: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 8007424: 4619 mov r1, r3 + 8007426: 6878 ldr r0, [r7, #4] + 8007428: f7ff f85e bl 80064e8 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 800742c: e00b b.n 8007446 + HAL_UART_RxCpltCallback(huart); + 800742e: 6878 ldr r0, [r7, #4] + 8007430: f7fa fae8 bl 8001a04 +} + 8007434: e007 b.n 8007446 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8007436: 687b ldr r3, [r7, #4] + 8007438: 681b ldr r3, [r3, #0] + 800743a: 699a ldr r2, [r3, #24] + 800743c: 687b ldr r3, [r7, #4] + 800743e: 681b ldr r3, [r3, #0] + 8007440: f042 0208 orr.w r2, r2, #8 + 8007444: 619a str r2, [r3, #24] +} + 8007446: bf00 nop + 8007448: 3770 adds r7, #112 ; 0x70 + 800744a: 46bd mov sp, r7 + 800744c: bd80 pop {r7, pc} + 800744e: bf00 nop + 8007450: 40008000 .word 0x40008000 + +08007454 : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT(UART_HandleTypeDef *huart) +{ + 8007454: b580 push {r7, lr} + 8007456: b09c sub sp, #112 ; 0x70 + 8007458: af00 add r7, sp, #0 + 800745a: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 800745c: 687b ldr r3, [r7, #4] + 800745e: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 8007462: f8a7 306e strh.w r3, [r7, #110] ; 0x6e + uint16_t uhdata; + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 8007466: 687b ldr r3, [r7, #4] + 8007468: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 800746c: 2b22 cmp r3, #34 ; 0x22 + 800746e: f040 80be bne.w 80075ee + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8007472: 687b ldr r3, [r7, #4] + 8007474: 681b ldr r3, [r3, #0] + 8007476: 6a5b ldr r3, [r3, #36] ; 0x24 + 8007478: f8a7 306c strh.w r3, [r7, #108] ; 0x6c + tmp = (uint16_t *) huart->pRxBuffPtr ; + 800747c: 687b ldr r3, [r7, #4] + 800747e: 6d9b ldr r3, [r3, #88] ; 0x58 + 8007480: 66bb str r3, [r7, #104] ; 0x68 + *tmp = (uint16_t)(uhdata & uhMask); + 8007482: f8b7 206c ldrh.w r2, [r7, #108] ; 0x6c + 8007486: f8b7 306e ldrh.w r3, [r7, #110] ; 0x6e + 800748a: 4013 ands r3, r2 + 800748c: b29a uxth r2, r3 + 800748e: 6ebb ldr r3, [r7, #104] ; 0x68 + 8007490: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 8007492: 687b ldr r3, [r7, #4] + 8007494: 6d9b ldr r3, [r3, #88] ; 0x58 + 8007496: 1c9a adds r2, r3, #2 + 8007498: 687b ldr r3, [r7, #4] + 800749a: 659a str r2, [r3, #88] ; 0x58 + huart->RxXferCount--; + 800749c: 687b ldr r3, [r7, #4] + 800749e: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80074a2: b29b uxth r3, r3 + 80074a4: 3b01 subs r3, #1 + 80074a6: b29a uxth r2, r3 + 80074a8: 687b ldr r3, [r7, #4] + 80074aa: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + + if (huart->RxXferCount == 0U) + 80074ae: 687b ldr r3, [r7, #4] + 80074b0: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80074b4: b29b uxth r3, r3 + 80074b6: 2b00 cmp r3, #0 + 80074b8: f040 80a1 bne.w 80075fe + { + /* Disable the UART Parity Error Interrupt and RXNE interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, (USART_CR1_RXNEIE_RXFNEIE | USART_CR1_PEIE)); + 80074bc: 687b ldr r3, [r7, #4] + 80074be: 681b ldr r3, [r3, #0] + 80074c0: 64bb str r3, [r7, #72] ; 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80074c2: 6cbb ldr r3, [r7, #72] ; 0x48 + 80074c4: e853 3f00 ldrex r3, [r3] + 80074c8: 647b str r3, [r7, #68] ; 0x44 + return(result); + 80074ca: 6c7b ldr r3, [r7, #68] ; 0x44 + 80074cc: f423 7390 bic.w r3, r3, #288 ; 0x120 + 80074d0: 667b str r3, [r7, #100] ; 0x64 + 80074d2: 687b ldr r3, [r7, #4] + 80074d4: 681b ldr r3, [r3, #0] + 80074d6: 461a mov r2, r3 + 80074d8: 6e7b ldr r3, [r7, #100] ; 0x64 + 80074da: 657b str r3, [r7, #84] ; 0x54 + 80074dc: 653a str r2, [r7, #80] ; 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80074de: 6d39 ldr r1, [r7, #80] ; 0x50 + 80074e0: 6d7a ldr r2, [r7, #84] ; 0x54 + 80074e2: e841 2300 strex r3, r2, [r1] + 80074e6: 64fb str r3, [r7, #76] ; 0x4c + return(result); + 80074e8: 6cfb ldr r3, [r7, #76] ; 0x4c + 80074ea: 2b00 cmp r3, #0 + 80074ec: d1e6 bne.n 80074bc + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); + 80074ee: 687b ldr r3, [r7, #4] + 80074f0: 681b ldr r3, [r3, #0] + 80074f2: 3308 adds r3, #8 + 80074f4: 637b str r3, [r7, #52] ; 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80074f6: 6b7b ldr r3, [r7, #52] ; 0x34 + 80074f8: e853 3f00 ldrex r3, [r3] + 80074fc: 633b str r3, [r7, #48] ; 0x30 + return(result); + 80074fe: 6b3b ldr r3, [r7, #48] ; 0x30 + 8007500: f023 0301 bic.w r3, r3, #1 + 8007504: 663b str r3, [r7, #96] ; 0x60 + 8007506: 687b ldr r3, [r7, #4] + 8007508: 681b ldr r3, [r3, #0] + 800750a: 3308 adds r3, #8 + 800750c: 6e3a ldr r2, [r7, #96] ; 0x60 + 800750e: 643a str r2, [r7, #64] ; 0x40 + 8007510: 63fb str r3, [r7, #60] ; 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007512: 6bf9 ldr r1, [r7, #60] ; 0x3c + 8007514: 6c3a ldr r2, [r7, #64] ; 0x40 + 8007516: e841 2300 strex r3, r2, [r1] + 800751a: 63bb str r3, [r7, #56] ; 0x38 + return(result); + 800751c: 6bbb ldr r3, [r7, #56] ; 0x38 + 800751e: 2b00 cmp r3, #0 + 8007520: d1e5 bne.n 80074ee + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8007522: 687b ldr r3, [r7, #4] + 8007524: 2220 movs r2, #32 + 8007526: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 800752a: 687b ldr r3, [r7, #4] + 800752c: 2200 movs r2, #0 + 800752e: 675a str r2, [r3, #116] ; 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8007530: 687b ldr r3, [r7, #4] + 8007532: 2200 movs r2, #0 + 8007534: 671a str r2, [r3, #112] ; 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8007536: 687b ldr r3, [r7, #4] + 8007538: 681b ldr r3, [r3, #0] + 800753a: 4a33 ldr r2, [pc, #204] ; (8007608 ) + 800753c: 4293 cmp r3, r2 + 800753e: d01f beq.n 8007580 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8007540: 687b ldr r3, [r7, #4] + 8007542: 681b ldr r3, [r3, #0] + 8007544: 685b ldr r3, [r3, #4] + 8007546: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 800754a: 2b00 cmp r3, #0 + 800754c: d018 beq.n 8007580 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 800754e: 687b ldr r3, [r7, #4] + 8007550: 681b ldr r3, [r3, #0] + 8007552: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007554: 6a3b ldr r3, [r7, #32] + 8007556: e853 3f00 ldrex r3, [r3] + 800755a: 61fb str r3, [r7, #28] + return(result); + 800755c: 69fb ldr r3, [r7, #28] + 800755e: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8007562: 65fb str r3, [r7, #92] ; 0x5c + 8007564: 687b ldr r3, [r7, #4] + 8007566: 681b ldr r3, [r3, #0] + 8007568: 461a mov r2, r3 + 800756a: 6dfb ldr r3, [r7, #92] ; 0x5c + 800756c: 62fb str r3, [r7, #44] ; 0x2c + 800756e: 62ba str r2, [r7, #40] ; 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007570: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8007572: 6afa ldr r2, [r7, #44] ; 0x2c + 8007574: e841 2300 strex r3, r2, [r1] + 8007578: 627b str r3, [r7, #36] ; 0x24 + return(result); + 800757a: 6a7b ldr r3, [r7, #36] ; 0x24 + 800757c: 2b00 cmp r3, #0 + 800757e: d1e6 bne.n 800754e + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8007580: 687b ldr r3, [r7, #4] + 8007582: 6edb ldr r3, [r3, #108] ; 0x6c + 8007584: 2b01 cmp r3, #1 + 8007586: d12e bne.n 80075e6 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8007588: 687b ldr r3, [r7, #4] + 800758a: 2200 movs r2, #0 + 800758c: 66da str r2, [r3, #108] ; 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 800758e: 687b ldr r3, [r7, #4] + 8007590: 681b ldr r3, [r3, #0] + 8007592: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007594: 68fb ldr r3, [r7, #12] + 8007596: e853 3f00 ldrex r3, [r3] + 800759a: 60bb str r3, [r7, #8] + return(result); + 800759c: 68bb ldr r3, [r7, #8] + 800759e: f023 0310 bic.w r3, r3, #16 + 80075a2: 65bb str r3, [r7, #88] ; 0x58 + 80075a4: 687b ldr r3, [r7, #4] + 80075a6: 681b ldr r3, [r3, #0] + 80075a8: 461a mov r2, r3 + 80075aa: 6dbb ldr r3, [r7, #88] ; 0x58 + 80075ac: 61bb str r3, [r7, #24] + 80075ae: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80075b0: 6979 ldr r1, [r7, #20] + 80075b2: 69ba ldr r2, [r7, #24] + 80075b4: e841 2300 strex r3, r2, [r1] + 80075b8: 613b str r3, [r7, #16] + return(result); + 80075ba: 693b ldr r3, [r7, #16] + 80075bc: 2b00 cmp r3, #0 + 80075be: d1e6 bne.n 800758e + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 80075c0: 687b ldr r3, [r7, #4] + 80075c2: 681b ldr r3, [r3, #0] + 80075c4: 69db ldr r3, [r3, #28] + 80075c6: f003 0310 and.w r3, r3, #16 + 80075ca: 2b10 cmp r3, #16 + 80075cc: d103 bne.n 80075d6 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 80075ce: 687b ldr r3, [r7, #4] + 80075d0: 681b ldr r3, [r3, #0] + 80075d2: 2210 movs r2, #16 + 80075d4: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 80075d6: 687b ldr r3, [r7, #4] + 80075d8: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 80075dc: 4619 mov r1, r3 + 80075de: 6878 ldr r0, [r7, #4] + 80075e0: f7fe ff82 bl 80064e8 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 80075e4: e00b b.n 80075fe + HAL_UART_RxCpltCallback(huart); + 80075e6: 6878 ldr r0, [r7, #4] + 80075e8: f7fa fa0c bl 8001a04 +} + 80075ec: e007 b.n 80075fe + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 80075ee: 687b ldr r3, [r7, #4] + 80075f0: 681b ldr r3, [r3, #0] + 80075f2: 699a ldr r2, [r3, #24] + 80075f4: 687b ldr r3, [r7, #4] + 80075f6: 681b ldr r3, [r3, #0] + 80075f8: f042 0208 orr.w r2, r2, #8 + 80075fc: 619a str r2, [r3, #24] +} + 80075fe: bf00 nop + 8007600: 3770 adds r7, #112 ; 0x70 + 8007602: 46bd mov sp, r7 + 8007604: bd80 pop {r7, pc} + 8007606: bf00 nop + 8007608: 40008000 .word 0x40008000 + +0800760c : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + 800760c: b580 push {r7, lr} + 800760e: b0ac sub sp, #176 ; 0xb0 + 8007610: af00 add r7, sp, #0 + 8007612: 6078 str r0, [r7, #4] + uint16_t uhMask = huart->Mask; + 8007614: 687b ldr r3, [r7, #4] + 8007616: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800761a: f8a7 30aa strh.w r3, [r7, #170] ; 0xaa + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 800761e: 687b ldr r3, [r7, #4] + 8007620: 681b ldr r3, [r3, #0] + 8007622: 69db ldr r3, [r3, #28] + 8007624: f8c7 30ac str.w r3, [r7, #172] ; 0xac + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8007628: 687b ldr r3, [r7, #4] + 800762a: 681b ldr r3, [r3, #0] + 800762c: 681b ldr r3, [r3, #0] + 800762e: f8c7 30a4 str.w r3, [r7, #164] ; 0xa4 + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8007632: 687b ldr r3, [r7, #4] + 8007634: 681b ldr r3, [r3, #0] + 8007636: 689b ldr r3, [r3, #8] + 8007638: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 800763c: 687b ldr r3, [r7, #4] + 800763e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 8007642: 2b22 cmp r3, #34 ; 0x22 + 8007644: f040 8182 bne.w 800794c + { + nb_rx_data = huart->NbRxDataToProcess; + 8007648: 687b ldr r3, [r7, #4] + 800764a: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 800764e: f8a7 309e strh.w r3, [r7, #158] ; 0x9e + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 8007652: e125 b.n 80078a0 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 8007654: 687b ldr r3, [r7, #4] + 8007656: 681b ldr r3, [r3, #0] + 8007658: 6a5b ldr r3, [r3, #36] ; 0x24 + 800765a: f8a7 309c strh.w r3, [r7, #156] ; 0x9c + *huart->pRxBuffPtr = (uint8_t)(uhdata & (uint8_t)uhMask); + 800765e: f8b7 309c ldrh.w r3, [r7, #156] ; 0x9c + 8007662: b2d9 uxtb r1, r3 + 8007664: f8b7 30aa ldrh.w r3, [r7, #170] ; 0xaa + 8007668: b2da uxtb r2, r3 + 800766a: 687b ldr r3, [r7, #4] + 800766c: 6d9b ldr r3, [r3, #88] ; 0x58 + 800766e: 400a ands r2, r1 + 8007670: b2d2 uxtb r2, r2 + 8007672: 701a strb r2, [r3, #0] + huart->pRxBuffPtr++; + 8007674: 687b ldr r3, [r7, #4] + 8007676: 6d9b ldr r3, [r3, #88] ; 0x58 + 8007678: 1c5a adds r2, r3, #1 + 800767a: 687b ldr r3, [r7, #4] + 800767c: 659a str r2, [r3, #88] ; 0x58 + huart->RxXferCount--; + 800767e: 687b ldr r3, [r7, #4] + 8007680: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8007684: b29b uxth r3, r3 + 8007686: 3b01 subs r3, #1 + 8007688: b29a uxth r2, r3 + 800768a: 687b ldr r3, [r7, #4] + 800768c: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + isrflags = READ_REG(huart->Instance->ISR); + 8007690: 687b ldr r3, [r7, #4] + 8007692: 681b ldr r3, [r3, #0] + 8007694: 69db ldr r3, [r3, #28] + 8007696: f8c7 30ac str.w r3, [r7, #172] ; 0xac + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + 800769a: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 800769e: f003 0307 and.w r3, r3, #7 + 80076a2: 2b00 cmp r3, #0 + 80076a4: d053 beq.n 800774e + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 80076a6: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 80076aa: f003 0301 and.w r3, r3, #1 + 80076ae: 2b00 cmp r3, #0 + 80076b0: d011 beq.n 80076d6 + 80076b2: f8d7 30a4 ldr.w r3, [r7, #164] ; 0xa4 + 80076b6: f403 7380 and.w r3, r3, #256 ; 0x100 + 80076ba: 2b00 cmp r3, #0 + 80076bc: d00b beq.n 80076d6 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 80076be: 687b ldr r3, [r7, #4] + 80076c0: 681b ldr r3, [r3, #0] + 80076c2: 2201 movs r2, #1 + 80076c4: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 80076c6: 687b ldr r3, [r7, #4] + 80076c8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80076cc: f043 0201 orr.w r2, r3, #1 + 80076d0: 687b ldr r3, [r7, #4] + 80076d2: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 80076d6: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 80076da: f003 0302 and.w r3, r3, #2 + 80076de: 2b00 cmp r3, #0 + 80076e0: d011 beq.n 8007706 + 80076e2: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 80076e6: f003 0301 and.w r3, r3, #1 + 80076ea: 2b00 cmp r3, #0 + 80076ec: d00b beq.n 8007706 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 80076ee: 687b ldr r3, [r7, #4] + 80076f0: 681b ldr r3, [r3, #0] + 80076f2: 2202 movs r2, #2 + 80076f4: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 80076f6: 687b ldr r3, [r7, #4] + 80076f8: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 80076fc: f043 0204 orr.w r2, r3, #4 + 8007700: 687b ldr r3, [r7, #4] + 8007702: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8007706: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 800770a: f003 0304 and.w r3, r3, #4 + 800770e: 2b00 cmp r3, #0 + 8007710: d011 beq.n 8007736 + 8007712: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 8007716: f003 0301 and.w r3, r3, #1 + 800771a: 2b00 cmp r3, #0 + 800771c: d00b beq.n 8007736 + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 800771e: 687b ldr r3, [r7, #4] + 8007720: 681b ldr r3, [r3, #0] + 8007722: 2204 movs r2, #4 + 8007724: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8007726: 687b ldr r3, [r7, #4] + 8007728: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800772c: f043 0202 orr.w r2, r3, #2 + 8007730: 687b ldr r3, [r7, #4] + 8007732: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8007736: 687b ldr r3, [r7, #4] + 8007738: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 800773c: 2b00 cmp r3, #0 + 800773e: d006 beq.n 800774e +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8007740: 6878 ldr r0, [r7, #4] + 8007742: f7fe fec8 bl 80064d6 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8007746: 687b ldr r3, [r7, #4] + 8007748: 2200 movs r2, #0 + 800774a: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + } + + if (huart->RxXferCount == 0U) + 800774e: 687b ldr r3, [r7, #4] + 8007750: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8007754: b29b uxth r3, r3 + 8007756: 2b00 cmp r3, #0 + 8007758: f040 80a2 bne.w 80078a0 + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 800775c: 687b ldr r3, [r7, #4] + 800775e: 681b ldr r3, [r3, #0] + 8007760: 673b str r3, [r7, #112] ; 0x70 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007762: 6f3b ldr r3, [r7, #112] ; 0x70 + 8007764: e853 3f00 ldrex r3, [r3] + 8007768: 66fb str r3, [r7, #108] ; 0x6c + return(result); + 800776a: 6efb ldr r3, [r7, #108] ; 0x6c + 800776c: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8007770: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 8007774: 687b ldr r3, [r7, #4] + 8007776: 681b ldr r3, [r3, #0] + 8007778: 461a mov r2, r3 + 800777a: f8d7 3098 ldr.w r3, [r7, #152] ; 0x98 + 800777e: 67fb str r3, [r7, #124] ; 0x7c + 8007780: 67ba str r2, [r7, #120] ; 0x78 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007782: 6fb9 ldr r1, [r7, #120] ; 0x78 + 8007784: 6ffa ldr r2, [r7, #124] ; 0x7c + 8007786: e841 2300 strex r3, r2, [r1] + 800778a: 677b str r3, [r7, #116] ; 0x74 + return(result); + 800778c: 6f7b ldr r3, [r7, #116] ; 0x74 + 800778e: 2b00 cmp r3, #0 + 8007790: d1e4 bne.n 800775c + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8007792: 687b ldr r3, [r7, #4] + 8007794: 681b ldr r3, [r3, #0] + 8007796: 3308 adds r3, #8 + 8007798: 65fb str r3, [r7, #92] ; 0x5c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800779a: 6dfb ldr r3, [r7, #92] ; 0x5c + 800779c: e853 3f00 ldrex r3, [r3] + 80077a0: 65bb str r3, [r7, #88] ; 0x58 + return(result); + 80077a2: 6dbb ldr r3, [r7, #88] ; 0x58 + 80077a4: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80077a8: f023 0301 bic.w r3, r3, #1 + 80077ac: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 80077b0: 687b ldr r3, [r7, #4] + 80077b2: 681b ldr r3, [r3, #0] + 80077b4: 3308 adds r3, #8 + 80077b6: f8d7 2094 ldr.w r2, [r7, #148] ; 0x94 + 80077ba: 66ba str r2, [r7, #104] ; 0x68 + 80077bc: 667b str r3, [r7, #100] ; 0x64 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80077be: 6e79 ldr r1, [r7, #100] ; 0x64 + 80077c0: 6eba ldr r2, [r7, #104] ; 0x68 + 80077c2: e841 2300 strex r3, r2, [r1] + 80077c6: 663b str r3, [r7, #96] ; 0x60 + return(result); + 80077c8: 6e3b ldr r3, [r7, #96] ; 0x60 + 80077ca: 2b00 cmp r3, #0 + 80077cc: d1e1 bne.n 8007792 + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 80077ce: 687b ldr r3, [r7, #4] + 80077d0: 2220 movs r2, #32 + 80077d2: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 80077d6: 687b ldr r3, [r7, #4] + 80077d8: 2200 movs r2, #0 + 80077da: 675a str r2, [r3, #116] ; 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 80077dc: 687b ldr r3, [r7, #4] + 80077de: 2200 movs r2, #0 + 80077e0: 671a str r2, [r3, #112] ; 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 80077e2: 687b ldr r3, [r7, #4] + 80077e4: 681b ldr r3, [r3, #0] + 80077e6: 4a5f ldr r2, [pc, #380] ; (8007964 ) + 80077e8: 4293 cmp r3, r2 + 80077ea: d021 beq.n 8007830 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 80077ec: 687b ldr r3, [r7, #4] + 80077ee: 681b ldr r3, [r3, #0] + 80077f0: 685b ldr r3, [r3, #4] + 80077f2: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 80077f6: 2b00 cmp r3, #0 + 80077f8: d01a beq.n 8007830 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 80077fa: 687b ldr r3, [r7, #4] + 80077fc: 681b ldr r3, [r3, #0] + 80077fe: 64bb str r3, [r7, #72] ; 0x48 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007800: 6cbb ldr r3, [r7, #72] ; 0x48 + 8007802: e853 3f00 ldrex r3, [r3] + 8007806: 647b str r3, [r7, #68] ; 0x44 + return(result); + 8007808: 6c7b ldr r3, [r7, #68] ; 0x44 + 800780a: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 800780e: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 8007812: 687b ldr r3, [r7, #4] + 8007814: 681b ldr r3, [r3, #0] + 8007816: 461a mov r2, r3 + 8007818: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 800781c: 657b str r3, [r7, #84] ; 0x54 + 800781e: 653a str r2, [r7, #80] ; 0x50 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007820: 6d39 ldr r1, [r7, #80] ; 0x50 + 8007822: 6d7a ldr r2, [r7, #84] ; 0x54 + 8007824: e841 2300 strex r3, r2, [r1] + 8007828: 64fb str r3, [r7, #76] ; 0x4c + return(result); + 800782a: 6cfb ldr r3, [r7, #76] ; 0x4c + 800782c: 2b00 cmp r3, #0 + 800782e: d1e4 bne.n 80077fa + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8007830: 687b ldr r3, [r7, #4] + 8007832: 6edb ldr r3, [r3, #108] ; 0x6c + 8007834: 2b01 cmp r3, #1 + 8007836: d130 bne.n 800789a + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8007838: 687b ldr r3, [r7, #4] + 800783a: 2200 movs r2, #0 + 800783c: 66da str r2, [r3, #108] ; 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 800783e: 687b ldr r3, [r7, #4] + 8007840: 681b ldr r3, [r3, #0] + 8007842: 637b str r3, [r7, #52] ; 0x34 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007844: 6b7b ldr r3, [r7, #52] ; 0x34 + 8007846: e853 3f00 ldrex r3, [r3] + 800784a: 633b str r3, [r7, #48] ; 0x30 + return(result); + 800784c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800784e: f023 0310 bic.w r3, r3, #16 + 8007852: f8c7 308c str.w r3, [r7, #140] ; 0x8c + 8007856: 687b ldr r3, [r7, #4] + 8007858: 681b ldr r3, [r3, #0] + 800785a: 461a mov r2, r3 + 800785c: f8d7 308c ldr.w r3, [r7, #140] ; 0x8c + 8007860: 643b str r3, [r7, #64] ; 0x40 + 8007862: 63fa str r2, [r7, #60] ; 0x3c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007864: 6bf9 ldr r1, [r7, #60] ; 0x3c + 8007866: 6c3a ldr r2, [r7, #64] ; 0x40 + 8007868: e841 2300 strex r3, r2, [r1] + 800786c: 63bb str r3, [r7, #56] ; 0x38 + return(result); + 800786e: 6bbb ldr r3, [r7, #56] ; 0x38 + 8007870: 2b00 cmp r3, #0 + 8007872: d1e4 bne.n 800783e + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8007874: 687b ldr r3, [r7, #4] + 8007876: 681b ldr r3, [r3, #0] + 8007878: 69db ldr r3, [r3, #28] + 800787a: f003 0310 and.w r3, r3, #16 + 800787e: 2b10 cmp r3, #16 + 8007880: d103 bne.n 800788a + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8007882: 687b ldr r3, [r7, #4] + 8007884: 681b ldr r3, [r3, #0] + 8007886: 2210 movs r2, #16 + 8007888: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 800788a: 687b ldr r3, [r7, #4] + 800788c: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 8007890: 4619 mov r1, r3 + 8007892: 6878 ldr r0, [r7, #4] + 8007894: f7fe fe28 bl 80064e8 + 8007898: e002 b.n 80078a0 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 800789a: 6878 ldr r0, [r7, #4] + 800789c: f7fa f8b2 bl 8001a04 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 80078a0: f8b7 309e ldrh.w r3, [r7, #158] ; 0x9e + 80078a4: 2b00 cmp r3, #0 + 80078a6: d006 beq.n 80078b6 + 80078a8: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 80078ac: f003 0320 and.w r3, r3, #32 + 80078b0: 2b00 cmp r3, #0 + 80078b2: f47f aecf bne.w 8007654 + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + 80078b6: 687b ldr r3, [r7, #4] + 80078b8: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80078bc: f8a7 308a strh.w r3, [r7, #138] ; 0x8a + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 80078c0: f8b7 308a ldrh.w r3, [r7, #138] ; 0x8a + 80078c4: 2b00 cmp r3, #0 + 80078c6: d049 beq.n 800795c + 80078c8: 687b ldr r3, [r7, #4] + 80078ca: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 80078ce: f8b7 208a ldrh.w r2, [r7, #138] ; 0x8a + 80078d2: 429a cmp r2, r3 + 80078d4: d242 bcs.n 800795c + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 80078d6: 687b ldr r3, [r7, #4] + 80078d8: 681b ldr r3, [r3, #0] + 80078da: 3308 adds r3, #8 + 80078dc: 623b str r3, [r7, #32] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 80078de: 6a3b ldr r3, [r7, #32] + 80078e0: e853 3f00 ldrex r3, [r3] + 80078e4: 61fb str r3, [r7, #28] + return(result); + 80078e6: 69fb ldr r3, [r7, #28] + 80078e8: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 80078ec: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 80078f0: 687b ldr r3, [r7, #4] + 80078f2: 681b ldr r3, [r3, #0] + 80078f4: 3308 adds r3, #8 + 80078f6: f8d7 2084 ldr.w r2, [r7, #132] ; 0x84 + 80078fa: 62fa str r2, [r7, #44] ; 0x2c + 80078fc: 62bb str r3, [r7, #40] ; 0x28 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 80078fe: 6ab9 ldr r1, [r7, #40] ; 0x28 + 8007900: 6afa ldr r2, [r7, #44] ; 0x2c + 8007902: e841 2300 strex r3, r2, [r1] + 8007906: 627b str r3, [r7, #36] ; 0x24 + return(result); + 8007908: 6a7b ldr r3, [r7, #36] ; 0x24 + 800790a: 2b00 cmp r3, #0 + 800790c: d1e3 bne.n 80078d6 + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_8BIT; + 800790e: 687b ldr r3, [r7, #4] + 8007910: 4a15 ldr r2, [pc, #84] ; (8007968 ) + 8007912: 675a str r2, [r3, #116] ; 0x74 + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8007914: 687b ldr r3, [r7, #4] + 8007916: 681b ldr r3, [r3, #0] + 8007918: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 800791a: 68fb ldr r3, [r7, #12] + 800791c: e853 3f00 ldrex r3, [r3] + 8007920: 60bb str r3, [r7, #8] + return(result); + 8007922: 68bb ldr r3, [r7, #8] + 8007924: f043 0320 orr.w r3, r3, #32 + 8007928: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 800792c: 687b ldr r3, [r7, #4] + 800792e: 681b ldr r3, [r3, #0] + 8007930: 461a mov r2, r3 + 8007932: f8d7 3080 ldr.w r3, [r7, #128] ; 0x80 + 8007936: 61bb str r3, [r7, #24] + 8007938: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 800793a: 6979 ldr r1, [r7, #20] + 800793c: 69ba ldr r2, [r7, #24] + 800793e: e841 2300 strex r3, r2, [r1] + 8007942: 613b str r3, [r7, #16] + return(result); + 8007944: 693b ldr r3, [r7, #16] + 8007946: 2b00 cmp r3, #0 + 8007948: d1e4 bne.n 8007914 + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 800794a: e007 b.n 800795c + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 800794c: 687b ldr r3, [r7, #4] + 800794e: 681b ldr r3, [r3, #0] + 8007950: 699a ldr r2, [r3, #24] + 8007952: 687b ldr r3, [r7, #4] + 8007954: 681b ldr r3, [r3, #0] + 8007956: f042 0208 orr.w r2, r2, #8 + 800795a: 619a str r2, [r3, #24] +} + 800795c: bf00 nop + 800795e: 37b0 adds r7, #176 ; 0xb0 + 8007960: 46bd mov sp, r7 + 8007962: bd80 pop {r7, pc} + 8007964: 40008000 .word 0x40008000 + 8007968: 0800729d .word 0x0800729d + +0800796c : + * interruptions have been enabled by HAL_UART_Receive_IT() + * @param huart UART handle. + * @retval None + */ +static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) +{ + 800796c: b580 push {r7, lr} + 800796e: b0ae sub sp, #184 ; 0xb8 + 8007970: af00 add r7, sp, #0 + 8007972: 6078 str r0, [r7, #4] + uint16_t *tmp; + uint16_t uhMask = huart->Mask; + 8007974: 687b ldr r3, [r7, #4] + 8007976: f8b3 3060 ldrh.w r3, [r3, #96] ; 0x60 + 800797a: f8a7 30b2 strh.w r3, [r7, #178] ; 0xb2 + uint16_t uhdata; + uint16_t nb_rx_data; + uint16_t rxdatacount; + uint32_t isrflags = READ_REG(huart->Instance->ISR); + 800797e: 687b ldr r3, [r7, #4] + 8007980: 681b ldr r3, [r3, #0] + 8007982: 69db ldr r3, [r3, #28] + 8007984: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + uint32_t cr1its = READ_REG(huart->Instance->CR1); + 8007988: 687b ldr r3, [r7, #4] + 800798a: 681b ldr r3, [r3, #0] + 800798c: 681b ldr r3, [r3, #0] + 800798e: f8c7 30ac str.w r3, [r7, #172] ; 0xac + uint32_t cr3its = READ_REG(huart->Instance->CR3); + 8007992: 687b ldr r3, [r7, #4] + 8007994: 681b ldr r3, [r3, #0] + 8007996: 689b ldr r3, [r3, #8] + 8007998: f8c7 30a8 str.w r3, [r7, #168] ; 0xa8 + + /* Check that a Rx process is ongoing */ + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + 800799c: 687b ldr r3, [r7, #4] + 800799e: f8d3 308c ldr.w r3, [r3, #140] ; 0x8c + 80079a2: 2b22 cmp r3, #34 ; 0x22 + 80079a4: f040 8186 bne.w 8007cb4 + { + nb_rx_data = huart->NbRxDataToProcess; + 80079a8: 687b ldr r3, [r7, #4] + 80079aa: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 80079ae: f8a7 30a6 strh.w r3, [r7, #166] ; 0xa6 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 80079b2: e129 b.n 8007c08 + { + uhdata = (uint16_t) READ_REG(huart->Instance->RDR); + 80079b4: 687b ldr r3, [r7, #4] + 80079b6: 681b ldr r3, [r3, #0] + 80079b8: 6a5b ldr r3, [r3, #36] ; 0x24 + 80079ba: f8a7 30a4 strh.w r3, [r7, #164] ; 0xa4 + tmp = (uint16_t *) huart->pRxBuffPtr ; + 80079be: 687b ldr r3, [r7, #4] + 80079c0: 6d9b ldr r3, [r3, #88] ; 0x58 + 80079c2: f8c7 30a0 str.w r3, [r7, #160] ; 0xa0 + *tmp = (uint16_t)(uhdata & uhMask); + 80079c6: f8b7 20a4 ldrh.w r2, [r7, #164] ; 0xa4 + 80079ca: f8b7 30b2 ldrh.w r3, [r7, #178] ; 0xb2 + 80079ce: 4013 ands r3, r2 + 80079d0: b29a uxth r2, r3 + 80079d2: f8d7 30a0 ldr.w r3, [r7, #160] ; 0xa0 + 80079d6: 801a strh r2, [r3, #0] + huart->pRxBuffPtr += 2U; + 80079d8: 687b ldr r3, [r7, #4] + 80079da: 6d9b ldr r3, [r3, #88] ; 0x58 + 80079dc: 1c9a adds r2, r3, #2 + 80079de: 687b ldr r3, [r7, #4] + 80079e0: 659a str r2, [r3, #88] ; 0x58 + huart->RxXferCount--; + 80079e2: 687b ldr r3, [r7, #4] + 80079e4: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 80079e8: b29b uxth r3, r3 + 80079ea: 3b01 subs r3, #1 + 80079ec: b29a uxth r2, r3 + 80079ee: 687b ldr r3, [r7, #4] + 80079f0: f8a3 205e strh.w r2, [r3, #94] ; 0x5e + isrflags = READ_REG(huart->Instance->ISR); + 80079f4: 687b ldr r3, [r7, #4] + 80079f6: 681b ldr r3, [r3, #0] + 80079f8: 69db ldr r3, [r3, #28] + 80079fa: f8c7 30b4 str.w r3, [r7, #180] ; 0xb4 + + /* If some non blocking errors occurred */ + if ((isrflags & (USART_ISR_PE | USART_ISR_FE | USART_ISR_NE)) != 0U) + 80079fe: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 8007a02: f003 0307 and.w r3, r3, #7 + 8007a06: 2b00 cmp r3, #0 + 8007a08: d053 beq.n 8007ab2 + { + /* UART parity error interrupt occurred -------------------------------------*/ + if (((isrflags & USART_ISR_PE) != 0U) && ((cr1its & USART_CR1_PEIE) != 0U)) + 8007a0a: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 8007a0e: f003 0301 and.w r3, r3, #1 + 8007a12: 2b00 cmp r3, #0 + 8007a14: d011 beq.n 8007a3a + 8007a16: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 8007a1a: f403 7380 and.w r3, r3, #256 ; 0x100 + 8007a1e: 2b00 cmp r3, #0 + 8007a20: d00b beq.n 8007a3a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_PEF); + 8007a22: 687b ldr r3, [r7, #4] + 8007a24: 681b ldr r3, [r3, #0] + 8007a26: 2201 movs r2, #1 + 8007a28: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_PE; + 8007a2a: 687b ldr r3, [r7, #4] + 8007a2c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007a30: f043 0201 orr.w r2, r3, #1 + 8007a34: 687b ldr r3, [r7, #4] + 8007a36: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART frame error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_FE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8007a3a: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 8007a3e: f003 0302 and.w r3, r3, #2 + 8007a42: 2b00 cmp r3, #0 + 8007a44: d011 beq.n 8007a6a + 8007a46: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 8007a4a: f003 0301 and.w r3, r3, #1 + 8007a4e: 2b00 cmp r3, #0 + 8007a50: d00b beq.n 8007a6a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_FEF); + 8007a52: 687b ldr r3, [r7, #4] + 8007a54: 681b ldr r3, [r3, #0] + 8007a56: 2202 movs r2, #2 + 8007a58: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_FE; + 8007a5a: 687b ldr r3, [r7, #4] + 8007a5c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007a60: f043 0204 orr.w r2, r3, #4 + 8007a64: 687b ldr r3, [r7, #4] + 8007a66: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* UART noise error interrupt occurred --------------------------------------*/ + if (((isrflags & USART_ISR_NE) != 0U) && ((cr3its & USART_CR3_EIE) != 0U)) + 8007a6a: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 8007a6e: f003 0304 and.w r3, r3, #4 + 8007a72: 2b00 cmp r3, #0 + 8007a74: d011 beq.n 8007a9a + 8007a76: f8d7 30a8 ldr.w r3, [r7, #168] ; 0xa8 + 8007a7a: f003 0301 and.w r3, r3, #1 + 8007a7e: 2b00 cmp r3, #0 + 8007a80: d00b beq.n 8007a9a + { + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_NEF); + 8007a82: 687b ldr r3, [r7, #4] + 8007a84: 681b ldr r3, [r3, #0] + 8007a86: 2204 movs r2, #4 + 8007a88: 621a str r2, [r3, #32] + + huart->ErrorCode |= HAL_UART_ERROR_NE; + 8007a8a: 687b ldr r3, [r7, #4] + 8007a8c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007a90: f043 0202 orr.w r2, r3, #2 + 8007a94: 687b ldr r3, [r7, #4] + 8007a96: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + + /* Call UART Error Call back function if need be ----------------------------*/ + if (huart->ErrorCode != HAL_UART_ERROR_NONE) + 8007a9a: 687b ldr r3, [r7, #4] + 8007a9c: f8d3 3090 ldr.w r3, [r3, #144] ; 0x90 + 8007aa0: 2b00 cmp r3, #0 + 8007aa2: d006 beq.n 8007ab2 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered error callback*/ + huart->ErrorCallback(huart); +#else + /*Call legacy weak error callback*/ + HAL_UART_ErrorCallback(huart); + 8007aa4: 6878 ldr r0, [r7, #4] + 8007aa6: f7fe fd16 bl 80064d6 +#endif /* USE_HAL_UART_REGISTER_CALLBACKS */ + huart->ErrorCode = HAL_UART_ERROR_NONE; + 8007aaa: 687b ldr r3, [r7, #4] + 8007aac: 2200 movs r2, #0 + 8007aae: f8c3 2090 str.w r2, [r3, #144] ; 0x90 + } + } + + if (huart->RxXferCount == 0U) + 8007ab2: 687b ldr r3, [r7, #4] + 8007ab4: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8007ab8: b29b uxth r3, r3 + 8007aba: 2b00 cmp r3, #0 + 8007abc: f040 80a4 bne.w 8007c08 + { + /* Disable the UART Parity Error Interrupt and RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); + 8007ac0: 687b ldr r3, [r7, #4] + 8007ac2: 681b ldr r3, [r3, #0] + 8007ac4: 677b str r3, [r7, #116] ; 0x74 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007ac6: 6f7b ldr r3, [r7, #116] ; 0x74 + 8007ac8: e853 3f00 ldrex r3, [r3] + 8007acc: 673b str r3, [r7, #112] ; 0x70 + return(result); + 8007ace: 6f3b ldr r3, [r7, #112] ; 0x70 + 8007ad0: f423 7380 bic.w r3, r3, #256 ; 0x100 + 8007ad4: f8c7 309c str.w r3, [r7, #156] ; 0x9c + 8007ad8: 687b ldr r3, [r7, #4] + 8007ada: 681b ldr r3, [r3, #0] + 8007adc: 461a mov r2, r3 + 8007ade: f8d7 309c ldr.w r3, [r7, #156] ; 0x9c + 8007ae2: f8c7 3080 str.w r3, [r7, #128] ; 0x80 + 8007ae6: 67fa str r2, [r7, #124] ; 0x7c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007ae8: 6ff9 ldr r1, [r7, #124] ; 0x7c + 8007aea: f8d7 2080 ldr.w r2, [r7, #128] ; 0x80 + 8007aee: e841 2300 strex r3, r2, [r1] + 8007af2: 67bb str r3, [r7, #120] ; 0x78 + return(result); + 8007af4: 6fbb ldr r3, [r7, #120] ; 0x78 + 8007af6: 2b00 cmp r3, #0 + 8007af8: d1e2 bne.n 8007ac0 + + /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) + and RX FIFO Threshold interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, (USART_CR3_EIE | USART_CR3_RXFTIE)); + 8007afa: 687b ldr r3, [r7, #4] + 8007afc: 681b ldr r3, [r3, #0] + 8007afe: 3308 adds r3, #8 + 8007b00: 663b str r3, [r7, #96] ; 0x60 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007b02: 6e3b ldr r3, [r7, #96] ; 0x60 + 8007b04: e853 3f00 ldrex r3, [r3] + 8007b08: 65fb str r3, [r7, #92] ; 0x5c + return(result); + 8007b0a: 6dfb ldr r3, [r7, #92] ; 0x5c + 8007b0c: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8007b10: f023 0301 bic.w r3, r3, #1 + 8007b14: f8c7 3098 str.w r3, [r7, #152] ; 0x98 + 8007b18: 687b ldr r3, [r7, #4] + 8007b1a: 681b ldr r3, [r3, #0] + 8007b1c: 3308 adds r3, #8 + 8007b1e: f8d7 2098 ldr.w r2, [r7, #152] ; 0x98 + 8007b22: 66fa str r2, [r7, #108] ; 0x6c + 8007b24: 66bb str r3, [r7, #104] ; 0x68 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007b26: 6eb9 ldr r1, [r7, #104] ; 0x68 + 8007b28: 6efa ldr r2, [r7, #108] ; 0x6c + 8007b2a: e841 2300 strex r3, r2, [r1] + 8007b2e: 667b str r3, [r7, #100] ; 0x64 + return(result); + 8007b30: 6e7b ldr r3, [r7, #100] ; 0x64 + 8007b32: 2b00 cmp r3, #0 + 8007b34: d1e1 bne.n 8007afa + + /* Rx process is completed, restore huart->RxState to Ready */ + huart->RxState = HAL_UART_STATE_READY; + 8007b36: 687b ldr r3, [r7, #4] + 8007b38: 2220 movs r2, #32 + 8007b3a: f8c3 208c str.w r2, [r3, #140] ; 0x8c + + /* Clear RxISR function pointer */ + huart->RxISR = NULL; + 8007b3e: 687b ldr r3, [r7, #4] + 8007b40: 2200 movs r2, #0 + 8007b42: 675a str r2, [r3, #116] ; 0x74 + + /* Initialize type of RxEvent to Transfer Complete */ + huart->RxEventType = HAL_UART_RXEVENT_TC; + 8007b44: 687b ldr r3, [r7, #4] + 8007b46: 2200 movs r2, #0 + 8007b48: 671a str r2, [r3, #112] ; 0x70 + + if (!(IS_LPUART_INSTANCE(huart->Instance))) + 8007b4a: 687b ldr r3, [r7, #4] + 8007b4c: 681b ldr r3, [r3, #0] + 8007b4e: 4a5f ldr r2, [pc, #380] ; (8007ccc ) + 8007b50: 4293 cmp r3, r2 + 8007b52: d021 beq.n 8007b98 + { + /* Check that USART RTOEN bit is set */ + if (READ_BIT(huart->Instance->CR2, USART_CR2_RTOEN) != 0U) + 8007b54: 687b ldr r3, [r7, #4] + 8007b56: 681b ldr r3, [r3, #0] + 8007b58: 685b ldr r3, [r3, #4] + 8007b5a: f403 0300 and.w r3, r3, #8388608 ; 0x800000 + 8007b5e: 2b00 cmp r3, #0 + 8007b60: d01a beq.n 8007b98 + { + /* Enable the UART Receiver Timeout Interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_RTOIE); + 8007b62: 687b ldr r3, [r7, #4] + 8007b64: 681b ldr r3, [r3, #0] + 8007b66: 64fb str r3, [r7, #76] ; 0x4c + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007b68: 6cfb ldr r3, [r7, #76] ; 0x4c + 8007b6a: e853 3f00 ldrex r3, [r3] + 8007b6e: 64bb str r3, [r7, #72] ; 0x48 + return(result); + 8007b70: 6cbb ldr r3, [r7, #72] ; 0x48 + 8007b72: f023 6380 bic.w r3, r3, #67108864 ; 0x4000000 + 8007b76: f8c7 3094 str.w r3, [r7, #148] ; 0x94 + 8007b7a: 687b ldr r3, [r7, #4] + 8007b7c: 681b ldr r3, [r3, #0] + 8007b7e: 461a mov r2, r3 + 8007b80: f8d7 3094 ldr.w r3, [r7, #148] ; 0x94 + 8007b84: 65bb str r3, [r7, #88] ; 0x58 + 8007b86: 657a str r2, [r7, #84] ; 0x54 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007b88: 6d79 ldr r1, [r7, #84] ; 0x54 + 8007b8a: 6dba ldr r2, [r7, #88] ; 0x58 + 8007b8c: e841 2300 strex r3, r2, [r1] + 8007b90: 653b str r3, [r7, #80] ; 0x50 + return(result); + 8007b92: 6d3b ldr r3, [r7, #80] ; 0x50 + 8007b94: 2b00 cmp r3, #0 + 8007b96: d1e4 bne.n 8007b62 + } + } + + /* Check current reception Mode : + If Reception till IDLE event has been selected : */ + if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) + 8007b98: 687b ldr r3, [r7, #4] + 8007b9a: 6edb ldr r3, [r3, #108] ; 0x6c + 8007b9c: 2b01 cmp r3, #1 + 8007b9e: d130 bne.n 8007c02 + { + /* Set reception type to Standard */ + huart->ReceptionType = HAL_UART_RECEPTION_STANDARD; + 8007ba0: 687b ldr r3, [r7, #4] + 8007ba2: 2200 movs r2, #0 + 8007ba4: 66da str r2, [r3, #108] ; 0x6c + + /* Disable IDLE interrupt */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_IDLEIE); + 8007ba6: 687b ldr r3, [r7, #4] + 8007ba8: 681b ldr r3, [r3, #0] + 8007baa: 63bb str r3, [r7, #56] ; 0x38 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007bac: 6bbb ldr r3, [r7, #56] ; 0x38 + 8007bae: e853 3f00 ldrex r3, [r3] + 8007bb2: 637b str r3, [r7, #52] ; 0x34 + return(result); + 8007bb4: 6b7b ldr r3, [r7, #52] ; 0x34 + 8007bb6: f023 0310 bic.w r3, r3, #16 + 8007bba: f8c7 3090 str.w r3, [r7, #144] ; 0x90 + 8007bbe: 687b ldr r3, [r7, #4] + 8007bc0: 681b ldr r3, [r3, #0] + 8007bc2: 461a mov r2, r3 + 8007bc4: f8d7 3090 ldr.w r3, [r7, #144] ; 0x90 + 8007bc8: 647b str r3, [r7, #68] ; 0x44 + 8007bca: 643a str r2, [r7, #64] ; 0x40 + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007bcc: 6c39 ldr r1, [r7, #64] ; 0x40 + 8007bce: 6c7a ldr r2, [r7, #68] ; 0x44 + 8007bd0: e841 2300 strex r3, r2, [r1] + 8007bd4: 63fb str r3, [r7, #60] ; 0x3c + return(result); + 8007bd6: 6bfb ldr r3, [r7, #60] ; 0x3c + 8007bd8: 2b00 cmp r3, #0 + 8007bda: d1e4 bne.n 8007ba6 + + if (__HAL_UART_GET_FLAG(huart, UART_FLAG_IDLE) == SET) + 8007bdc: 687b ldr r3, [r7, #4] + 8007bde: 681b ldr r3, [r3, #0] + 8007be0: 69db ldr r3, [r3, #28] + 8007be2: f003 0310 and.w r3, r3, #16 + 8007be6: 2b10 cmp r3, #16 + 8007be8: d103 bne.n 8007bf2 + { + /* Clear IDLE Flag */ + __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF); + 8007bea: 687b ldr r3, [r7, #4] + 8007bec: 681b ldr r3, [r3, #0] + 8007bee: 2210 movs r2, #16 + 8007bf0: 621a str r2, [r3, #32] +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + 8007bf2: 687b ldr r3, [r7, #4] + 8007bf4: f8b3 305c ldrh.w r3, [r3, #92] ; 0x5c + 8007bf8: 4619 mov r1, r3 + 8007bfa: 6878 ldr r0, [r7, #4] + 8007bfc: f7fe fc74 bl 80064e8 + 8007c00: e002 b.n 8007c08 +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx complete callback*/ + huart->RxCpltCallback(huart); +#else + /*Call legacy weak Rx complete callback*/ + HAL_UART_RxCpltCallback(huart); + 8007c02: 6878 ldr r0, [r7, #4] + 8007c04: f7f9 fefe bl 8001a04 + while ((nb_rx_data > 0U) && ((isrflags & USART_ISR_RXNE_RXFNE) != 0U)) + 8007c08: f8b7 30a6 ldrh.w r3, [r7, #166] ; 0xa6 + 8007c0c: 2b00 cmp r3, #0 + 8007c0e: d006 beq.n 8007c1e + 8007c10: f8d7 30b4 ldr.w r3, [r7, #180] ; 0xb4 + 8007c14: f003 0320 and.w r3, r3, #32 + 8007c18: 2b00 cmp r3, #0 + 8007c1a: f47f aecb bne.w 80079b4 + + /* When remaining number of bytes to receive is less than the RX FIFO + threshold, next incoming frames are processed as if FIFO mode was + disabled (i.e. one interrupt per received frame). + */ + rxdatacount = huart->RxXferCount; + 8007c1e: 687b ldr r3, [r7, #4] + 8007c20: f8b3 305e ldrh.w r3, [r3, #94] ; 0x5e + 8007c24: f8a7 308e strh.w r3, [r7, #142] ; 0x8e + if ((rxdatacount != 0U) && (rxdatacount < huart->NbRxDataToProcess)) + 8007c28: f8b7 308e ldrh.w r3, [r7, #142] ; 0x8e + 8007c2c: 2b00 cmp r3, #0 + 8007c2e: d049 beq.n 8007cc4 + 8007c30: 687b ldr r3, [r7, #4] + 8007c32: f8b3 3068 ldrh.w r3, [r3, #104] ; 0x68 + 8007c36: f8b7 208e ldrh.w r2, [r7, #142] ; 0x8e + 8007c3a: 429a cmp r2, r3 + 8007c3c: d242 bcs.n 8007cc4 + { + /* Disable the UART RXFT interrupt*/ + ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_RXFTIE); + 8007c3e: 687b ldr r3, [r7, #4] + 8007c40: 681b ldr r3, [r3, #0] + 8007c42: 3308 adds r3, #8 + 8007c44: 627b str r3, [r7, #36] ; 0x24 + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007c46: 6a7b ldr r3, [r7, #36] ; 0x24 + 8007c48: e853 3f00 ldrex r3, [r3] + 8007c4c: 623b str r3, [r7, #32] + return(result); + 8007c4e: 6a3b ldr r3, [r7, #32] + 8007c50: f023 5380 bic.w r3, r3, #268435456 ; 0x10000000 + 8007c54: f8c7 3088 str.w r3, [r7, #136] ; 0x88 + 8007c58: 687b ldr r3, [r7, #4] + 8007c5a: 681b ldr r3, [r3, #0] + 8007c5c: 3308 adds r3, #8 + 8007c5e: f8d7 2088 ldr.w r2, [r7, #136] ; 0x88 + 8007c62: 633a str r2, [r7, #48] ; 0x30 + 8007c64: 62fb str r3, [r7, #44] ; 0x2c + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007c66: 6af9 ldr r1, [r7, #44] ; 0x2c + 8007c68: 6b3a ldr r2, [r7, #48] ; 0x30 + 8007c6a: e841 2300 strex r3, r2, [r1] + 8007c6e: 62bb str r3, [r7, #40] ; 0x28 + return(result); + 8007c70: 6abb ldr r3, [r7, #40] ; 0x28 + 8007c72: 2b00 cmp r3, #0 + 8007c74: d1e3 bne.n 8007c3e + + /* Update the RxISR function pointer */ + huart->RxISR = UART_RxISR_16BIT; + 8007c76: 687b ldr r3, [r7, #4] + 8007c78: 4a15 ldr r2, [pc, #84] ; (8007cd0 ) + 8007c7a: 675a str r2, [r3, #116] ; 0x74 + + /* Enable the UART Data Register Not Empty interrupt */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_RXNEIE_RXFNEIE); + 8007c7c: 687b ldr r3, [r7, #4] + 8007c7e: 681b ldr r3, [r3, #0] + 8007c80: 613b str r3, [r7, #16] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007c82: 693b ldr r3, [r7, #16] + 8007c84: e853 3f00 ldrex r3, [r3] + 8007c88: 60fb str r3, [r7, #12] + return(result); + 8007c8a: 68fb ldr r3, [r7, #12] + 8007c8c: f043 0320 orr.w r3, r3, #32 + 8007c90: f8c7 3084 str.w r3, [r7, #132] ; 0x84 + 8007c94: 687b ldr r3, [r7, #4] + 8007c96: 681b ldr r3, [r3, #0] + 8007c98: 461a mov r2, r3 + 8007c9a: f8d7 3084 ldr.w r3, [r7, #132] ; 0x84 + 8007c9e: 61fb str r3, [r7, #28] + 8007ca0: 61ba str r2, [r7, #24] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007ca2: 69b9 ldr r1, [r7, #24] + 8007ca4: 69fa ldr r2, [r7, #28] + 8007ca6: e841 2300 strex r3, r2, [r1] + 8007caa: 617b str r3, [r7, #20] + return(result); + 8007cac: 697b ldr r3, [r7, #20] + 8007cae: 2b00 cmp r3, #0 + 8007cb0: d1e4 bne.n 8007c7c + else + { + /* Clear RXNE interrupt flag */ + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + } +} + 8007cb2: e007 b.n 8007cc4 + __HAL_UART_SEND_REQ(huart, UART_RXDATA_FLUSH_REQUEST); + 8007cb4: 687b ldr r3, [r7, #4] + 8007cb6: 681b ldr r3, [r3, #0] + 8007cb8: 699a ldr r2, [r3, #24] + 8007cba: 687b ldr r3, [r7, #4] + 8007cbc: 681b ldr r3, [r3, #0] + 8007cbe: f042 0208 orr.w r2, r2, #8 + 8007cc2: 619a str r2, [r3, #24] +} + 8007cc4: bf00 nop + 8007cc6: 37b8 adds r7, #184 ; 0xb8 + 8007cc8: 46bd mov sp, r7 + 8007cca: bd80 pop {r7, pc} + 8007ccc: 40008000 .word 0x40008000 + 8007cd0: 08007455 .word 0x08007455 + +08007cd4 : + * @brief UART wakeup from Stop mode callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_WakeupCallback(UART_HandleTypeDef *huart) +{ + 8007cd4: b480 push {r7} + 8007cd6: b083 sub sp, #12 + 8007cd8: af00 add r7, sp, #0 + 8007cda: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_WakeupCallback can be implemented in the user file. + */ +} + 8007cdc: bf00 nop + 8007cde: 370c adds r7, #12 + 8007ce0: 46bd mov sp, r7 + 8007ce2: bc80 pop {r7} + 8007ce4: 4770 bx lr + +08007ce6 : + * @brief UART RX Fifo full callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_RxFifoFullCallback(UART_HandleTypeDef *huart) +{ + 8007ce6: b480 push {r7} + 8007ce8: b083 sub sp, #12 + 8007cea: af00 add r7, sp, #0 + 8007cec: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_RxFifoFullCallback can be implemented in the user file. + */ +} + 8007cee: bf00 nop + 8007cf0: 370c adds r7, #12 + 8007cf2: 46bd mov sp, r7 + 8007cf4: bc80 pop {r7} + 8007cf6: 4770 bx lr + +08007cf8 : + * @brief UART TX Fifo empty callback. + * @param huart UART handle. + * @retval None + */ +__weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) +{ + 8007cf8: b480 push {r7} + 8007cfa: b083 sub sp, #12 + 8007cfc: af00 add r7, sp, #0 + 8007cfe: 6078 str r0, [r7, #4] + UNUSED(huart); + + /* NOTE : This function should not be modified, when the callback is needed, + the HAL_UARTEx_TxFifoEmptyCallback can be implemented in the user file. + */ +} + 8007d00: bf00 nop + 8007d02: 370c adds r7, #12 + 8007d04: 46bd mov sp, r7 + 8007d06: bc80 pop {r7} + 8007d08: 4770 bx lr + +08007d0a : + * @arg @ref UART_WAKEUP_ON_STARTBIT + * @arg @ref UART_WAKEUP_ON_READDATA_NONEMPTY + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_StopModeWakeUpSourceConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + 8007d0a: b580 push {r7, lr} + 8007d0c: b088 sub sp, #32 + 8007d0e: af02 add r7, sp, #8 + 8007d10: 60f8 str r0, [r7, #12] + 8007d12: 1d3b adds r3, r7, #4 + 8007d14: e883 0006 stmia.w r3, {r1, r2} + HAL_StatusTypeDef status = HAL_OK; + 8007d18: 2300 movs r3, #0 + 8007d1a: 75fb strb r3, [r7, #23] + assert_param(IS_UART_WAKEUP_FROMSTOP_INSTANCE(huart->Instance)); + /* check the wake-up selection parameter */ + assert_param(IS_UART_WAKEUP_SELECTION(WakeUpSelection.WakeUpEvent)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007d1c: 68fb ldr r3, [r7, #12] + 8007d1e: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007d22: 2b01 cmp r3, #1 + 8007d24: d101 bne.n 8007d2a + 8007d26: 2302 movs r3, #2 + 8007d28: e046 b.n 8007db8 + 8007d2a: 68fb ldr r3, [r7, #12] + 8007d2c: 2201 movs r2, #1 + 8007d2e: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 8007d32: 68fb ldr r3, [r7, #12] + 8007d34: 2224 movs r2, #36 ; 0x24 + 8007d36: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Disable the Peripheral */ + __HAL_UART_DISABLE(huart); + 8007d3a: 68fb ldr r3, [r7, #12] + 8007d3c: 681b ldr r3, [r3, #0] + 8007d3e: 681a ldr r2, [r3, #0] + 8007d40: 68fb ldr r3, [r7, #12] + 8007d42: 681b ldr r3, [r3, #0] + 8007d44: f022 0201 bic.w r2, r2, #1 + 8007d48: 601a str r2, [r3, #0] + + /* Set the wake-up selection scheme */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_WUS, WakeUpSelection.WakeUpEvent); + 8007d4a: 68fb ldr r3, [r7, #12] + 8007d4c: 681b ldr r3, [r3, #0] + 8007d4e: 689b ldr r3, [r3, #8] + 8007d50: f423 1140 bic.w r1, r3, #3145728 ; 0x300000 + 8007d54: 687a ldr r2, [r7, #4] + 8007d56: 68fb ldr r3, [r7, #12] + 8007d58: 681b ldr r3, [r3, #0] + 8007d5a: 430a orrs r2, r1 + 8007d5c: 609a str r2, [r3, #8] + + if (WakeUpSelection.WakeUpEvent == UART_WAKEUP_ON_ADDRESS) + 8007d5e: 687b ldr r3, [r7, #4] + 8007d60: 2b00 cmp r3, #0 + 8007d62: d105 bne.n 8007d70 + { + UARTEx_Wakeup_AddressConfig(huart, WakeUpSelection); + 8007d64: 1d3b adds r3, r7, #4 + 8007d66: e893 0006 ldmia.w r3, {r1, r2} + 8007d6a: 68f8 ldr r0, [r7, #12] + 8007d6c: f000 f97b bl 8008066 + } + + /* Enable the Peripheral */ + __HAL_UART_ENABLE(huart); + 8007d70: 68fb ldr r3, [r7, #12] + 8007d72: 681b ldr r3, [r3, #0] + 8007d74: 681a ldr r2, [r3, #0] + 8007d76: 68fb ldr r3, [r7, #12] + 8007d78: 681b ldr r3, [r3, #0] + 8007d7a: f042 0201 orr.w r2, r2, #1 + 8007d7e: 601a str r2, [r3, #0] + + /* Init tickstart for timeout management */ + tickstart = HAL_GetTick(); + 8007d80: f7f8 ffcc bl 8000d1c + 8007d84: 6138 str r0, [r7, #16] + + /* Wait until REACK flag is set */ + if (UART_WaitOnFlagUntilTimeout(huart, USART_ISR_REACK, RESET, tickstart, HAL_UART_TIMEOUT_VALUE) != HAL_OK) + 8007d86: f06f 437e mvn.w r3, #4261412864 ; 0xfe000000 + 8007d8a: 9300 str r3, [sp, #0] + 8007d8c: 693b ldr r3, [r7, #16] + 8007d8e: 2200 movs r2, #0 + 8007d90: f44f 0180 mov.w r1, #4194304 ; 0x400000 + 8007d94: 68f8 ldr r0, [r7, #12] + 8007d96: f7fe ff16 bl 8006bc6 + 8007d9a: 4603 mov r3, r0 + 8007d9c: 2b00 cmp r3, #0 + 8007d9e: d002 beq.n 8007da6 + { + status = HAL_TIMEOUT; + 8007da0: 2303 movs r3, #3 + 8007da2: 75fb strb r3, [r7, #23] + 8007da4: e003 b.n 8007dae + } + else + { + /* Initialize the UART State */ + huart->gState = HAL_UART_STATE_READY; + 8007da6: 68fb ldr r3, [r7, #12] + 8007da8: 2220 movs r2, #32 + 8007daa: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + } + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007dae: 68fb ldr r3, [r7, #12] + 8007db0: 2200 movs r2, #0 + 8007db2: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return status; + 8007db6: 7dfb ldrb r3, [r7, #23] +} + 8007db8: 4618 mov r0, r3 + 8007dba: 3718 adds r7, #24 + 8007dbc: 46bd mov sp, r7 + 8007dbe: bd80 pop {r7, pc} + +08007dc0 : + * @note The UART is able to wake up the MCU from Stop 1 mode as long as UART clock is HSI or LSE. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableStopMode(UART_HandleTypeDef *huart) +{ + 8007dc0: b480 push {r7} + 8007dc2: b089 sub sp, #36 ; 0x24 + 8007dc4: af00 add r7, sp, #0 + 8007dc6: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(huart); + 8007dc8: 687b ldr r3, [r7, #4] + 8007dca: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007dce: 2b01 cmp r3, #1 + 8007dd0: d101 bne.n 8007dd6 + 8007dd2: 2302 movs r3, #2 + 8007dd4: e021 b.n 8007e1a + 8007dd6: 687b ldr r3, [r7, #4] + 8007dd8: 2201 movs r2, #1 + 8007dda: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + /* Set UESM bit */ + ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_UESM); + 8007dde: 687b ldr r3, [r7, #4] + 8007de0: 681b ldr r3, [r3, #0] + 8007de2: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007de4: 68fb ldr r3, [r7, #12] + 8007de6: e853 3f00 ldrex r3, [r3] + 8007dea: 60bb str r3, [r7, #8] + return(result); + 8007dec: 68bb ldr r3, [r7, #8] + 8007dee: f043 0302 orr.w r3, r3, #2 + 8007df2: 61fb str r3, [r7, #28] + 8007df4: 687b ldr r3, [r7, #4] + 8007df6: 681b ldr r3, [r3, #0] + 8007df8: 461a mov r2, r3 + 8007dfa: 69fb ldr r3, [r7, #28] + 8007dfc: 61bb str r3, [r7, #24] + 8007dfe: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007e00: 6979 ldr r1, [r7, #20] + 8007e02: 69ba ldr r2, [r7, #24] + 8007e04: e841 2300 strex r3, r2, [r1] + 8007e08: 613b str r3, [r7, #16] + return(result); + 8007e0a: 693b ldr r3, [r7, #16] + 8007e0c: 2b00 cmp r3, #0 + 8007e0e: d1e6 bne.n 8007dde + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007e10: 687b ldr r3, [r7, #4] + 8007e12: 2200 movs r2, #0 + 8007e14: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8007e18: 2300 movs r3, #0 +} + 8007e1a: 4618 mov r0, r3 + 8007e1c: 3724 adds r7, #36 ; 0x24 + 8007e1e: 46bd mov sp, r7 + 8007e20: bc80 pop {r7} + 8007e22: 4770 bx lr + +08007e24 : + * @brief Disable UART Stop Mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableStopMode(UART_HandleTypeDef *huart) +{ + 8007e24: b480 push {r7} + 8007e26: b089 sub sp, #36 ; 0x24 + 8007e28: af00 add r7, sp, #0 + 8007e2a: 6078 str r0, [r7, #4] + /* Process Locked */ + __HAL_LOCK(huart); + 8007e2c: 687b ldr r3, [r7, #4] + 8007e2e: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007e32: 2b01 cmp r3, #1 + 8007e34: d101 bne.n 8007e3a + 8007e36: 2302 movs r3, #2 + 8007e38: e021 b.n 8007e7e + 8007e3a: 687b ldr r3, [r7, #4] + 8007e3c: 2201 movs r2, #1 + 8007e3e: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + /* Clear UESM bit */ + ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_UESM); + 8007e42: 687b ldr r3, [r7, #4] + 8007e44: 681b ldr r3, [r3, #0] + 8007e46: 60fb str r3, [r7, #12] + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + 8007e48: 68fb ldr r3, [r7, #12] + 8007e4a: e853 3f00 ldrex r3, [r3] + 8007e4e: 60bb str r3, [r7, #8] + return(result); + 8007e50: 68bb ldr r3, [r7, #8] + 8007e52: f023 0302 bic.w r3, r3, #2 + 8007e56: 61fb str r3, [r7, #28] + 8007e58: 687b ldr r3, [r7, #4] + 8007e5a: 681b ldr r3, [r3, #0] + 8007e5c: 461a mov r2, r3 + 8007e5e: 69fb ldr r3, [r7, #28] + 8007e60: 61bb str r3, [r7, #24] + 8007e62: 617a str r2, [r7, #20] + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + 8007e64: 6979 ldr r1, [r7, #20] + 8007e66: 69ba ldr r2, [r7, #24] + 8007e68: e841 2300 strex r3, r2, [r1] + 8007e6c: 613b str r3, [r7, #16] + return(result); + 8007e6e: 693b ldr r3, [r7, #16] + 8007e70: 2b00 cmp r3, #0 + 8007e72: d1e6 bne.n 8007e42 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007e74: 687b ldr r3, [r7, #4] + 8007e76: 2200 movs r2, #0 + 8007e78: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8007e7c: 2300 movs r3, #0 +} + 8007e7e: 4618 mov r0, r3 + 8007e80: 3724 adds r7, #36 ; 0x24 + 8007e82: 46bd mov sp, r7 + 8007e84: bc80 pop {r7} + 8007e86: 4770 bx lr + +08007e88 : + * @brief Enable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_EnableFifoMode(UART_HandleTypeDef *huart) +{ + 8007e88: b580 push {r7, lr} + 8007e8a: b084 sub sp, #16 + 8007e8c: af00 add r7, sp, #0 + 8007e8e: 6078 str r0, [r7, #4] + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007e90: 687b ldr r3, [r7, #4] + 8007e92: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007e96: 2b01 cmp r3, #1 + 8007e98: d101 bne.n 8007e9e + 8007e9a: 2302 movs r3, #2 + 8007e9c: e02b b.n 8007ef6 + 8007e9e: 687b ldr r3, [r7, #4] + 8007ea0: 2201 movs r2, #1 + 8007ea2: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 8007ea6: 687b ldr r3, [r7, #4] + 8007ea8: 2224 movs r2, #36 ; 0x24 + 8007eaa: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8007eae: 687b ldr r3, [r7, #4] + 8007eb0: 681b ldr r3, [r3, #0] + 8007eb2: 681b ldr r3, [r3, #0] + 8007eb4: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 8007eb6: 687b ldr r3, [r7, #4] + 8007eb8: 681b ldr r3, [r3, #0] + 8007eba: 681a ldr r2, [r3, #0] + 8007ebc: 687b ldr r3, [r7, #4] + 8007ebe: 681b ldr r3, [r3, #0] + 8007ec0: f022 0201 bic.w r2, r2, #1 + 8007ec4: 601a str r2, [r3, #0] + + /* Enable FIFO mode */ + SET_BIT(tmpcr1, USART_CR1_FIFOEN); + 8007ec6: 68fb ldr r3, [r7, #12] + 8007ec8: f043 5300 orr.w r3, r3, #536870912 ; 0x20000000 + 8007ecc: 60fb str r3, [r7, #12] + huart->FifoMode = UART_FIFOMODE_ENABLE; + 8007ece: 687b ldr r3, [r7, #4] + 8007ed0: f04f 5200 mov.w r2, #536870912 ; 0x20000000 + 8007ed4: 665a str r2, [r3, #100] ; 0x64 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007ed6: 687b ldr r3, [r7, #4] + 8007ed8: 681b ldr r3, [r3, #0] + 8007eda: 68fa ldr r2, [r7, #12] + 8007edc: 601a str r2, [r3, #0] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8007ede: 6878 ldr r0, [r7, #4] + 8007ee0: f000 f8e4 bl 80080ac + + huart->gState = HAL_UART_STATE_READY; + 8007ee4: 687b ldr r3, [r7, #4] + 8007ee6: 2220 movs r2, #32 + 8007ee8: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007eec: 687b ldr r3, [r7, #4] + 8007eee: 2200 movs r2, #0 + 8007ef0: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8007ef4: 2300 movs r3, #0 +} + 8007ef6: 4618 mov r0, r3 + 8007ef8: 3710 adds r7, #16 + 8007efa: 46bd mov sp, r7 + 8007efc: bd80 pop {r7, pc} + +08007efe : + * @brief Disable the FIFO mode. + * @param huart UART handle. + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) +{ + 8007efe: b480 push {r7} + 8007f00: b085 sub sp, #20 + 8007f02: af00 add r7, sp, #0 + 8007f04: 6078 str r0, [r7, #4] + + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007f06: 687b ldr r3, [r7, #4] + 8007f08: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007f0c: 2b01 cmp r3, #1 + 8007f0e: d101 bne.n 8007f14 + 8007f10: 2302 movs r3, #2 + 8007f12: e027 b.n 8007f64 + 8007f14: 687b ldr r3, [r7, #4] + 8007f16: 2201 movs r2, #1 + 8007f18: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 8007f1c: 687b ldr r3, [r7, #4] + 8007f1e: 2224 movs r2, #36 ; 0x24 + 8007f20: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8007f24: 687b ldr r3, [r7, #4] + 8007f26: 681b ldr r3, [r3, #0] + 8007f28: 681b ldr r3, [r3, #0] + 8007f2a: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 8007f2c: 687b ldr r3, [r7, #4] + 8007f2e: 681b ldr r3, [r3, #0] + 8007f30: 681a ldr r2, [r3, #0] + 8007f32: 687b ldr r3, [r7, #4] + 8007f34: 681b ldr r3, [r3, #0] + 8007f36: f022 0201 bic.w r2, r2, #1 + 8007f3a: 601a str r2, [r3, #0] + + /* Enable FIFO mode */ + CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); + 8007f3c: 68fb ldr r3, [r7, #12] + 8007f3e: f023 5300 bic.w r3, r3, #536870912 ; 0x20000000 + 8007f42: 60fb str r3, [r7, #12] + huart->FifoMode = UART_FIFOMODE_DISABLE; + 8007f44: 687b ldr r3, [r7, #4] + 8007f46: 2200 movs r2, #0 + 8007f48: 665a str r2, [r3, #100] ; 0x64 + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007f4a: 687b ldr r3, [r7, #4] + 8007f4c: 681b ldr r3, [r3, #0] + 8007f4e: 68fa ldr r2, [r7, #12] + 8007f50: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 8007f52: 687b ldr r3, [r7, #4] + 8007f54: 2220 movs r2, #32 + 8007f56: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007f5a: 687b ldr r3, [r7, #4] + 8007f5c: 2200 movs r2, #0 + 8007f5e: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8007f62: 2300 movs r3, #0 +} + 8007f64: 4618 mov r0, r3 + 8007f66: 3714 adds r7, #20 + 8007f68: 46bd mov sp, r7 + 8007f6a: bc80 pop {r7} + 8007f6c: 4770 bx lr + +08007f6e : + * @arg @ref UART_TXFIFO_THRESHOLD_7_8 + * @arg @ref UART_TXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 8007f6e: b580 push {r7, lr} + 8007f70: b084 sub sp, #16 + 8007f72: af00 add r7, sp, #0 + 8007f74: 6078 str r0, [r7, #4] + 8007f76: 6039 str r1, [r7, #0] + /* Check parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_TXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007f78: 687b ldr r3, [r7, #4] + 8007f7a: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007f7e: 2b01 cmp r3, #1 + 8007f80: d101 bne.n 8007f86 + 8007f82: 2302 movs r3, #2 + 8007f84: e02d b.n 8007fe2 + 8007f86: 687b ldr r3, [r7, #4] + 8007f88: 2201 movs r2, #1 + 8007f8a: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 8007f8e: 687b ldr r3, [r7, #4] + 8007f90: 2224 movs r2, #36 ; 0x24 + 8007f92: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8007f96: 687b ldr r3, [r7, #4] + 8007f98: 681b ldr r3, [r3, #0] + 8007f9a: 681b ldr r3, [r3, #0] + 8007f9c: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 8007f9e: 687b ldr r3, [r7, #4] + 8007fa0: 681b ldr r3, [r3, #0] + 8007fa2: 681a ldr r2, [r3, #0] + 8007fa4: 687b ldr r3, [r7, #4] + 8007fa6: 681b ldr r3, [r3, #0] + 8007fa8: f022 0201 bic.w r2, r2, #1 + 8007fac: 601a str r2, [r3, #0] + + /* Update TX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_TXFTCFG, Threshold); + 8007fae: 687b ldr r3, [r7, #4] + 8007fb0: 681b ldr r3, [r3, #0] + 8007fb2: 689b ldr r3, [r3, #8] + 8007fb4: f023 4160 bic.w r1, r3, #3758096384 ; 0xe0000000 + 8007fb8: 687b ldr r3, [r7, #4] + 8007fba: 681b ldr r3, [r3, #0] + 8007fbc: 683a ldr r2, [r7, #0] + 8007fbe: 430a orrs r2, r1 + 8007fc0: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 8007fc2: 6878 ldr r0, [r7, #4] + 8007fc4: f000 f872 bl 80080ac + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8007fc8: 687b ldr r3, [r7, #4] + 8007fca: 681b ldr r3, [r3, #0] + 8007fcc: 68fa ldr r2, [r7, #12] + 8007fce: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 8007fd0: 687b ldr r3, [r7, #4] + 8007fd2: 2220 movs r2, #32 + 8007fd4: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8007fd8: 687b ldr r3, [r7, #4] + 8007fda: 2200 movs r2, #0 + 8007fdc: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 8007fe0: 2300 movs r3, #0 +} + 8007fe2: 4618 mov r0, r3 + 8007fe4: 3710 adds r7, #16 + 8007fe6: 46bd mov sp, r7 + 8007fe8: bd80 pop {r7, pc} + +08007fea : + * @arg @ref UART_RXFIFO_THRESHOLD_7_8 + * @arg @ref UART_RXFIFO_THRESHOLD_8_8 + * @retval HAL status + */ +HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold) +{ + 8007fea: b580 push {r7, lr} + 8007fec: b084 sub sp, #16 + 8007fee: af00 add r7, sp, #0 + 8007ff0: 6078 str r0, [r7, #4] + 8007ff2: 6039 str r1, [r7, #0] + /* Check the parameters */ + assert_param(IS_UART_FIFO_INSTANCE(huart->Instance)); + assert_param(IS_UART_RXFIFO_THRESHOLD(Threshold)); + + /* Process Locked */ + __HAL_LOCK(huart); + 8007ff4: 687b ldr r3, [r7, #4] + 8007ff6: f893 3084 ldrb.w r3, [r3, #132] ; 0x84 + 8007ffa: 2b01 cmp r3, #1 + 8007ffc: d101 bne.n 8008002 + 8007ffe: 2302 movs r3, #2 + 8008000: e02d b.n 800805e + 8008002: 687b ldr r3, [r7, #4] + 8008004: 2201 movs r2, #1 + 8008006: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + huart->gState = HAL_UART_STATE_BUSY; + 800800a: 687b ldr r3, [r7, #4] + 800800c: 2224 movs r2, #36 ; 0x24 + 800800e: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Save actual UART configuration */ + tmpcr1 = READ_REG(huart->Instance->CR1); + 8008012: 687b ldr r3, [r7, #4] + 8008014: 681b ldr r3, [r3, #0] + 8008016: 681b ldr r3, [r3, #0] + 8008018: 60fb str r3, [r7, #12] + + /* Disable UART */ + __HAL_UART_DISABLE(huart); + 800801a: 687b ldr r3, [r7, #4] + 800801c: 681b ldr r3, [r3, #0] + 800801e: 681a ldr r2, [r3, #0] + 8008020: 687b ldr r3, [r7, #4] + 8008022: 681b ldr r3, [r3, #0] + 8008024: f022 0201 bic.w r2, r2, #1 + 8008028: 601a str r2, [r3, #0] + + /* Update RX threshold configuration */ + MODIFY_REG(huart->Instance->CR3, USART_CR3_RXFTCFG, Threshold); + 800802a: 687b ldr r3, [r7, #4] + 800802c: 681b ldr r3, [r3, #0] + 800802e: 689b ldr r3, [r3, #8] + 8008030: f023 6160 bic.w r1, r3, #234881024 ; 0xe000000 + 8008034: 687b ldr r3, [r7, #4] + 8008036: 681b ldr r3, [r3, #0] + 8008038: 683a ldr r2, [r7, #0] + 800803a: 430a orrs r2, r1 + 800803c: 609a str r2, [r3, #8] + + /* Determine the number of data to process during RX/TX ISR execution */ + UARTEx_SetNbDataToProcess(huart); + 800803e: 6878 ldr r0, [r7, #4] + 8008040: f000 f834 bl 80080ac + + /* Restore UART configuration */ + WRITE_REG(huart->Instance->CR1, tmpcr1); + 8008044: 687b ldr r3, [r7, #4] + 8008046: 681b ldr r3, [r3, #0] + 8008048: 68fa ldr r2, [r7, #12] + 800804a: 601a str r2, [r3, #0] + + huart->gState = HAL_UART_STATE_READY; + 800804c: 687b ldr r3, [r7, #4] + 800804e: 2220 movs r2, #32 + 8008050: f8c3 2088 str.w r2, [r3, #136] ; 0x88 + + /* Process Unlocked */ + __HAL_UNLOCK(huart); + 8008054: 687b ldr r3, [r7, #4] + 8008056: 2200 movs r2, #0 + 8008058: f883 2084 strb.w r2, [r3, #132] ; 0x84 + + return HAL_OK; + 800805c: 2300 movs r3, #0 +} + 800805e: 4618 mov r0, r3 + 8008060: 3710 adds r7, #16 + 8008062: 46bd mov sp, r7 + 8008064: bd80 pop {r7, pc} + +08008066 : + * @param huart UART handle. + * @param WakeUpSelection UART wake up from stop mode parameters. + * @retval None + */ +static void UARTEx_Wakeup_AddressConfig(UART_HandleTypeDef *huart, UART_WakeUpTypeDef WakeUpSelection) +{ + 8008066: b480 push {r7} + 8008068: b085 sub sp, #20 + 800806a: af00 add r7, sp, #0 + 800806c: 60f8 str r0, [r7, #12] + 800806e: 1d3b adds r3, r7, #4 + 8008070: e883 0006 stmia.w r3, {r1, r2} + assert_param(IS_UART_ADDRESSLENGTH_DETECT(WakeUpSelection.AddressLength)); + + /* Set the USART address length */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADDM7, WakeUpSelection.AddressLength); + 8008074: 68fb ldr r3, [r7, #12] + 8008076: 681b ldr r3, [r3, #0] + 8008078: 685b ldr r3, [r3, #4] + 800807a: f023 0210 bic.w r2, r3, #16 + 800807e: 893b ldrh r3, [r7, #8] + 8008080: 4619 mov r1, r3 + 8008082: 68fb ldr r3, [r7, #12] + 8008084: 681b ldr r3, [r3, #0] + 8008086: 430a orrs r2, r1 + 8008088: 605a str r2, [r3, #4] + + /* Set the USART address node */ + MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, ((uint32_t)WakeUpSelection.Address << UART_CR2_ADDRESS_LSB_POS)); + 800808a: 68fb ldr r3, [r7, #12] + 800808c: 681b ldr r3, [r3, #0] + 800808e: 685b ldr r3, [r3, #4] + 8008090: f023 417f bic.w r1, r3, #4278190080 ; 0xff000000 + 8008094: 7abb ldrb r3, [r7, #10] + 8008096: 061a lsls r2, r3, #24 + 8008098: 68fb ldr r3, [r7, #12] + 800809a: 681b ldr r3, [r3, #0] + 800809c: 430a orrs r2, r1 + 800809e: 605a str r2, [r3, #4] +} + 80080a0: bf00 nop + 80080a2: 3714 adds r7, #20 + 80080a4: 46bd mov sp, r7 + 80080a6: bc80 pop {r7} + 80080a8: 4770 bx lr + ... + +080080ac : + * the UART configuration registers. + * @param huart UART handle. + * @retval None + */ +static void UARTEx_SetNbDataToProcess(UART_HandleTypeDef *huart) +{ + 80080ac: b480 push {r7} + 80080ae: b085 sub sp, #20 + 80080b0: af00 add r7, sp, #0 + 80080b2: 6078 str r0, [r7, #4] + uint8_t rx_fifo_threshold; + uint8_t tx_fifo_threshold; + static const uint8_t numerator[] = {1U, 1U, 1U, 3U, 7U, 1U, 0U, 0U}; + static const uint8_t denominator[] = {8U, 4U, 2U, 4U, 8U, 1U, 1U, 1U}; + + if (huart->FifoMode == UART_FIFOMODE_DISABLE) + 80080b4: 687b ldr r3, [r7, #4] + 80080b6: 6e5b ldr r3, [r3, #100] ; 0x64 + 80080b8: 2b00 cmp r3, #0 + 80080ba: d108 bne.n 80080ce + { + huart->NbTxDataToProcess = 1U; + 80080bc: 687b ldr r3, [r7, #4] + 80080be: 2201 movs r2, #1 + 80080c0: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + huart->NbRxDataToProcess = 1U; + 80080c4: 687b ldr r3, [r7, #4] + 80080c6: 2201 movs r2, #1 + 80080c8: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + (uint16_t)denominator[tx_fifo_threshold]; + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + (uint16_t)denominator[rx_fifo_threshold]; + } +} + 80080cc: e031 b.n 8008132 + rx_fifo_depth = RX_FIFO_DEPTH; + 80080ce: 2308 movs r3, #8 + 80080d0: 73fb strb r3, [r7, #15] + tx_fifo_depth = TX_FIFO_DEPTH; + 80080d2: 2308 movs r3, #8 + 80080d4: 73bb strb r3, [r7, #14] + rx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); + 80080d6: 687b ldr r3, [r7, #4] + 80080d8: 681b ldr r3, [r3, #0] + 80080da: 689b ldr r3, [r3, #8] + 80080dc: 0e5b lsrs r3, r3, #25 + 80080de: b2db uxtb r3, r3 + 80080e0: f003 0307 and.w r3, r3, #7 + 80080e4: 737b strb r3, [r7, #13] + tx_fifo_threshold = (uint8_t)(READ_BIT(huart->Instance->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); + 80080e6: 687b ldr r3, [r7, #4] + 80080e8: 681b ldr r3, [r3, #0] + 80080ea: 689b ldr r3, [r3, #8] + 80080ec: 0f5b lsrs r3, r3, #29 + 80080ee: b2db uxtb r3, r3 + 80080f0: f003 0307 and.w r3, r3, #7 + 80080f4: 733b strb r3, [r7, #12] + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + 80080f6: 7bbb ldrb r3, [r7, #14] + 80080f8: 7b3a ldrb r2, [r7, #12] + 80080fa: 4910 ldr r1, [pc, #64] ; (800813c ) + 80080fc: 5c8a ldrb r2, [r1, r2] + 80080fe: fb02 f303 mul.w r3, r2, r3 + (uint16_t)denominator[tx_fifo_threshold]; + 8008102: 7b3a ldrb r2, [r7, #12] + 8008104: 490e ldr r1, [pc, #56] ; (8008140 ) + 8008106: 5c8a ldrb r2, [r1, r2] + huart->NbTxDataToProcess = ((uint16_t)tx_fifo_depth * numerator[tx_fifo_threshold]) / + 8008108: fb93 f3f2 sdiv r3, r3, r2 + 800810c: b29a uxth r2, r3 + 800810e: 687b ldr r3, [r7, #4] + 8008110: f8a3 206a strh.w r2, [r3, #106] ; 0x6a + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + 8008114: 7bfb ldrb r3, [r7, #15] + 8008116: 7b7a ldrb r2, [r7, #13] + 8008118: 4908 ldr r1, [pc, #32] ; (800813c ) + 800811a: 5c8a ldrb r2, [r1, r2] + 800811c: fb02 f303 mul.w r3, r2, r3 + (uint16_t)denominator[rx_fifo_threshold]; + 8008120: 7b7a ldrb r2, [r7, #13] + 8008122: 4907 ldr r1, [pc, #28] ; (8008140 ) + 8008124: 5c8a ldrb r2, [r1, r2] + huart->NbRxDataToProcess = ((uint16_t)rx_fifo_depth * numerator[rx_fifo_threshold]) / + 8008126: fb93 f3f2 sdiv r3, r3, r2 + 800812a: b29a uxth r2, r3 + 800812c: 687b ldr r3, [r7, #4] + 800812e: f8a3 2068 strh.w r2, [r3, #104] ; 0x68 +} + 8008132: bf00 nop + 8008134: 3714 adds r7, #20 + 8008136: 46bd mov sp, r7 + 8008138: bc80 pop {r7} + 800813a: 4770 bx lr + 800813c: 0800e3f4 .word 0x0800e3f4 + 8008140: 0800e3fc .word 0x0800e3fc + +08008144 : +TimerEvent_t RxTimeoutTimer; + +/* Private functions ---------------------------------------------------------*/ + +static void RadioInit( RadioEvents_t *events ) +{ + 8008144: b580 push {r7, lr} + 8008146: b084 sub sp, #16 + 8008148: af02 add r7, sp, #8 + 800814a: 6078 str r0, [r7, #4] + RadioEvents = events; + 800814c: 4a24 ldr r2, [pc, #144] ; (80081e0 ) + 800814e: 687b ldr r3, [r7, #4] + 8008150: 6013 str r3, [r2, #0] + + SubgRf.RxContinuous = false; + 8008152: 4b24 ldr r3, [pc, #144] ; (80081e4 ) + 8008154: 2200 movs r2, #0 + 8008156: 705a strb r2, [r3, #1] + SubgRf.TxTimeout = 0; + 8008158: 4b22 ldr r3, [pc, #136] ; (80081e4 ) + 800815a: 2200 movs r2, #0 + 800815c: 605a str r2, [r3, #4] + SubgRf.RxTimeout = 0; + 800815e: 4b21 ldr r3, [pc, #132] ; (80081e4 ) + 8008160: 2200 movs r2, #0 + 8008162: 609a str r2, [r3, #8] + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008164: 4b1f ldr r3, [pc, #124] ; (80081e4 ) + 8008166: 2200 movs r2, #0 + 8008168: 659a str r2, [r3, #88] ; 0x58 +#if( RADIO_LR_FHSS_IS_ON == 1 ) + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + SUBGRF_Init( RadioOnDioIrq ); + 800816a: 481f ldr r0, [pc, #124] ; (80081e8 ) + 800816c: f001 ffc2 bl 800a0f4 + /*SubgRf.publicNetwork set to false*/ + SubgRf.PublicNetwork.Current = false; + 8008170: 4b1c ldr r3, [pc, #112] ; (80081e4 ) + 8008172: 2200 movs r2, #0 + 8008174: 735a strb r2, [r3, #13] + SubgRf.PublicNetwork.Previous = false; + 8008176: 4b1b ldr r3, [pc, #108] ; (80081e4 ) + 8008178: 2200 movs r2, #0 + 800817a: 731a strb r2, [r3, #12] + + RADIO_IRQ_PROCESS_INIT(); + + SUBGRF_SetRegulatorMode( ); + 800817c: f002 fa56 bl 800a62c + + SUBGRF_SetBufferBaseAddress( 0x00, 0x00 ); + 8008180: 2100 movs r1, #0 + 8008182: 2000 movs r0, #0 + 8008184: f002 fe22 bl 800adcc + SUBGRF_SetTxParams( RFO_LP, 0, RADIO_RAMP_200_US ); + 8008188: 2204 movs r2, #4 + 800818a: 2100 movs r1, #0 + 800818c: 2001 movs r0, #1 + 800818e: f002 fbdf bl 800a950 + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 8008192: 2300 movs r3, #0 + 8008194: 2200 movs r2, #0 + 8008196: f64f 71ff movw r1, #65535 ; 0xffff + 800819a: f64f 70ff movw r0, #65535 ; 0xffff + 800819e: f002 fb0f bl 800a7c0 + + RadioSleep(); + 80081a2: f000 fe99 bl 8008ed8 + // Initialize driver timeout timers + TimerInit( &TxTimeoutTimer, RadioOnTxTimeoutIrq ); + 80081a6: 2300 movs r3, #0 + 80081a8: 9300 str r3, [sp, #0] + 80081aa: 4b10 ldr r3, [pc, #64] ; (80081ec ) + 80081ac: 2200 movs r2, #0 + 80081ae: f04f 31ff mov.w r1, #4294967295 + 80081b2: 480f ldr r0, [pc, #60] ; (80081f0 ) + 80081b4: f004 fa60 bl 800c678 + TimerInit( &RxTimeoutTimer, RadioOnRxTimeoutIrq ); + 80081b8: 2300 movs r3, #0 + 80081ba: 9300 str r3, [sp, #0] + 80081bc: 4b0d ldr r3, [pc, #52] ; (80081f4 ) + 80081be: 2200 movs r2, #0 + 80081c0: f04f 31ff mov.w r1, #4294967295 + 80081c4: 480c ldr r0, [pc, #48] ; (80081f8 ) + 80081c6: f004 fa57 bl 800c678 + TimerStop( &TxTimeoutTimer ); + 80081ca: 4809 ldr r0, [pc, #36] ; (80081f0 ) + 80081cc: f004 faf8 bl 800c7c0 + TimerStop( &RxTimeoutTimer ); + 80081d0: 4809 ldr r0, [pc, #36] ; (80081f8 ) + 80081d2: f004 faf5 bl 800c7c0 +} + 80081d6: bf00 nop + 80081d8: 3708 adds r7, #8 + 80081da: 46bd mov sp, r7 + 80081dc: bd80 pop {r7, pc} + 80081de: bf00 nop + 80081e0: 200003fc .word 0x200003fc + 80081e4: 20000400 .word 0x20000400 + 80081e8: 080092d1 .word 0x080092d1 + 80081ec: 08009259 .word 0x08009259 + 80081f0: 2000045c .word 0x2000045c + 80081f4: 0800926d .word 0x0800926d + 80081f8: 20000474 .word 0x20000474 + +080081fc : + +static RadioState_t RadioGetStatus( void ) +{ + 80081fc: b580 push {r7, lr} + 80081fe: af00 add r7, sp, #0 + switch( SUBGRF_GetOperatingMode( ) ) + 8008200: f001 ffc0 bl 800a184 + 8008204: 4603 mov r3, r0 + 8008206: 2b07 cmp r3, #7 + 8008208: d00a beq.n 8008220 + 800820a: 2b07 cmp r3, #7 + 800820c: dc0a bgt.n 8008224 + 800820e: 2b04 cmp r3, #4 + 8008210: d002 beq.n 8008218 + 8008212: 2b05 cmp r3, #5 + 8008214: d002 beq.n 800821c + 8008216: e005 b.n 8008224 + { + case MODE_TX: + return RF_TX_RUNNING; + 8008218: 2302 movs r3, #2 + 800821a: e004 b.n 8008226 + case MODE_RX: + return RF_RX_RUNNING; + 800821c: 2301 movs r3, #1 + 800821e: e002 b.n 8008226 + case MODE_CAD: + return RF_CAD; + 8008220: 2303 movs r3, #3 + 8008222: e000 b.n 8008226 + default: + return RF_IDLE; + 8008224: 2300 movs r3, #0 + } +} + 8008226: 4618 mov r0, r3 + 8008228: bd80 pop {r7, pc} + ... + +0800822c : + +static void RadioSetModem( RadioModems_t modem ) +{ + 800822c: b580 push {r7, lr} + 800822e: b082 sub sp, #8 + 8008230: af00 add r7, sp, #0 + 8008232: 4603 mov r3, r0 + 8008234: 71fb strb r3, [r7, #7] + SubgRf.Modem = modem; + 8008236: 4a2a ldr r2, [pc, #168] ; (80082e0 ) + 8008238: 79fb ldrb r3, [r7, #7] + 800823a: 7013 strb r3, [r2, #0] + RFW_SetRadioModem( modem ); + 800823c: 79fb ldrb r3, [r7, #7] + 800823e: 4618 mov r0, r3 + 8008240: f003 f997 bl 800b572 + switch( modem ) + 8008244: 79fb ldrb r3, [r7, #7] + 8008246: 2b05 cmp r3, #5 + 8008248: d80e bhi.n 8008268 + 800824a: a201 add r2, pc, #4 ; (adr r2, 8008250 ) + 800824c: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008250: 08008277 .word 0x08008277 + 8008254: 08008285 .word 0x08008285 + 8008258: 08008269 .word 0x08008269 + 800825c: 080082ab .word 0x080082ab + 8008260: 080082b9 .word 0x080082b9 + 8008264: 080082c7 .word 0x080082c7 + { + default: + case MODEM_MSK: + SUBGRF_SetPacketType( PACKET_TYPE_GMSK ); + 8008268: 2003 movs r0, #3 + 800826a: f002 fb4b bl 800a904 + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 800826e: 4b1c ldr r3, [pc, #112] ; (80082e0 ) + 8008270: 2200 movs r2, #0 + 8008272: 735a strb r2, [r3, #13] + break; + 8008274: e02f b.n 80082d6 + case MODEM_FSK: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + 8008276: 2000 movs r0, #0 + 8008278: f002 fb44 bl 800a904 + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 800827c: 4b18 ldr r3, [pc, #96] ; (80082e0 ) + 800827e: 2200 movs r2, #0 + 8008280: 735a strb r2, [r3, #13] + break; + 8008282: e028 b.n 80082d6 + case MODEM_LORA: + SUBGRF_SetPacketType( PACKET_TYPE_LORA ); + 8008284: 2001 movs r0, #1 + 8008286: f002 fb3d bl 800a904 + // Public/Private network register is reset when switching modems + if( SubgRf.PublicNetwork.Current != SubgRf.PublicNetwork.Previous ) + 800828a: 4b15 ldr r3, [pc, #84] ; (80082e0 ) + 800828c: 7b5a ldrb r2, [r3, #13] + 800828e: 4b14 ldr r3, [pc, #80] ; (80082e0 ) + 8008290: 7b1b ldrb r3, [r3, #12] + 8008292: 429a cmp r2, r3 + 8008294: d01e beq.n 80082d4 + { + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous; + 8008296: 4b12 ldr r3, [pc, #72] ; (80082e0 ) + 8008298: 7b1a ldrb r2, [r3, #12] + 800829a: 4b11 ldr r3, [pc, #68] ; (80082e0 ) + 800829c: 735a strb r2, [r3, #13] + RadioSetPublicNetwork( SubgRf.PublicNetwork.Current ); + 800829e: 4b10 ldr r3, [pc, #64] ; (80082e0 ) + 80082a0: 7b5b ldrb r3, [r3, #13] + 80082a2: 4618 mov r0, r3 + 80082a4: f000 ffa2 bl 80091ec + } + break; + 80082a8: e014 b.n 80082d4 + case MODEM_BPSK: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + 80082aa: 2002 movs r0, #2 + 80082ac: f002 fb2a bl 800a904 + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 80082b0: 4b0b ldr r3, [pc, #44] ; (80082e0 ) + 80082b2: 2200 movs r2, #0 + 80082b4: 735a strb r2, [r3, #13] + break; + 80082b6: e00e b.n 80082d6 +#if (RADIO_SIGFOX_ENABLE == 1) + case MODEM_SIGFOX_TX: + SUBGRF_SetPacketType( PACKET_TYPE_BPSK ); + 80082b8: 2002 movs r0, #2 + 80082ba: f002 fb23 bl 800a904 + // When switching to BPSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 80082be: 4b08 ldr r3, [pc, #32] ; (80082e0 ) + 80082c0: 2200 movs r2, #0 + 80082c2: 735a strb r2, [r3, #13] + break; + 80082c4: e007 b.n 80082d6 + case MODEM_SIGFOX_RX: + SUBGRF_SetPacketType( PACKET_TYPE_GFSK ); + 80082c6: 2000 movs r0, #0 + 80082c8: f002 fb1c bl 800a904 + // When switching to GFSK mode the LoRa SyncWord register value is reset + // Thus, we also reset the RadioPublicNetwork variable + SubgRf.PublicNetwork.Current = false; + 80082cc: 4b04 ldr r3, [pc, #16] ; (80082e0 ) + 80082ce: 2200 movs r2, #0 + 80082d0: 735a strb r2, [r3, #13] + break; + 80082d2: e000 b.n 80082d6 + break; + 80082d4: bf00 nop +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + } +} + 80082d6: bf00 nop + 80082d8: 3708 adds r7, #8 + 80082da: 46bd mov sp, r7 + 80082dc: bd80 pop {r7, pc} + 80082de: bf00 nop + 80082e0: 20000400 .word 0x20000400 + +080082e4 : + +static void RadioSetChannel( uint32_t freq ) +{ + 80082e4: b580 push {r7, lr} + 80082e6: b082 sub sp, #8 + 80082e8: af00 add r7, sp, #0 + 80082ea: 6078 str r0, [r7, #4] + SUBGRF_SetRfFrequency( freq ); + 80082ec: 6878 ldr r0, [r7, #4] + 80082ee: f002 fac3 bl 800a878 +} + 80082f2: bf00 nop + 80082f4: 3708 adds r7, #8 + 80082f6: 46bd mov sp, r7 + 80082f8: bd80 pop {r7, pc} + +080082fa : + +static bool RadioIsChannelFree( uint32_t freq, uint32_t rxBandwidth, int16_t rssiThresh, uint32_t maxCarrierSenseTime ) +{ + 80082fa: b580 push {r7, lr} + 80082fc: b090 sub sp, #64 ; 0x40 + 80082fe: af0a add r7, sp, #40 ; 0x28 + 8008300: 60f8 str r0, [r7, #12] + 8008302: 60b9 str r1, [r7, #8] + 8008304: 603b str r3, [r7, #0] + 8008306: 4613 mov r3, r2 + 8008308: 80fb strh r3, [r7, #6] + bool status = true; + 800830a: 2301 movs r3, #1 + 800830c: 75fb strb r3, [r7, #23] + int16_t rssi = 0; + 800830e: 2300 movs r3, #0 + 8008310: 82bb strh r3, [r7, #20] + uint32_t carrierSenseTime = 0; + 8008312: 2300 movs r3, #0 + 8008314: 613b str r3, [r7, #16] + + RadioStandby( ); + 8008316: f000 fdf2 bl 8008efe + + RadioSetModem( MODEM_FSK ); + 800831a: 2000 movs r0, #0 + 800831c: f7ff ff86 bl 800822c + + RadioSetChannel( freq ); + 8008320: 68f8 ldr r0, [r7, #12] + 8008322: f7ff ffdf bl 80082e4 + + // Set Rx bandwidth. Other parameters are not used. + RadioSetRxConfig( MODEM_FSK, rxBandwidth, 600, 0, rxBandwidth, 3, 0, false, + 8008326: 2301 movs r3, #1 + 8008328: 9309 str r3, [sp, #36] ; 0x24 + 800832a: 2300 movs r3, #0 + 800832c: 9308 str r3, [sp, #32] + 800832e: 2300 movs r3, #0 + 8008330: 9307 str r3, [sp, #28] + 8008332: 2300 movs r3, #0 + 8008334: 9306 str r3, [sp, #24] + 8008336: 2300 movs r3, #0 + 8008338: 9305 str r3, [sp, #20] + 800833a: 2300 movs r3, #0 + 800833c: 9304 str r3, [sp, #16] + 800833e: 2300 movs r3, #0 + 8008340: 9303 str r3, [sp, #12] + 8008342: 2300 movs r3, #0 + 8008344: 9302 str r3, [sp, #8] + 8008346: 2303 movs r3, #3 + 8008348: 9301 str r3, [sp, #4] + 800834a: 68bb ldr r3, [r7, #8] + 800834c: 9300 str r3, [sp, #0] + 800834e: 2300 movs r3, #0 + 8008350: f44f 7216 mov.w r2, #600 ; 0x258 + 8008354: 68b9 ldr r1, [r7, #8] + 8008356: 2000 movs r0, #0 + 8008358: f000 f83c bl 80083d4 + 0, false, 0, 0, false, true ); + RadioRx( 0 ); + 800835c: 2000 movs r0, #0 + 800835e: f000 fdd5 bl 8008f0c + + RADIO_DELAY_MS( RadioGetWakeupTime( ) ); + 8008362: f000 ff71 bl 8009248 + 8008366: 4603 mov r3, r0 + 8008368: 4618 mov r0, r3 + 800836a: f7f8 fceb bl 8000d44 + + carrierSenseTime = TimerGetCurrentTime( ); + 800836e: f004 fac1 bl 800c8f4 + 8008372: 6138 str r0, [r7, #16] + + // Perform carrier sense for maxCarrierSenseTime + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + 8008374: e00d b.n 8008392 + { + rssi = RadioRssi( MODEM_FSK ); + 8008376: 2000 movs r0, #0 + 8008378: f000 feb6 bl 80090e8 + 800837c: 4603 mov r3, r0 + 800837e: 82bb strh r3, [r7, #20] + + if( rssi > rssiThresh ) + 8008380: f9b7 2014 ldrsh.w r2, [r7, #20] + 8008384: f9b7 3006 ldrsh.w r3, [r7, #6] + 8008388: 429a cmp r2, r3 + 800838a: dd02 ble.n 8008392 + { + status = false; + 800838c: 2300 movs r3, #0 + 800838e: 75fb strb r3, [r7, #23] + break; + 8008390: e006 b.n 80083a0 + while( TimerGetElapsedTime( carrierSenseTime ) < maxCarrierSenseTime ) + 8008392: 6938 ldr r0, [r7, #16] + 8008394: f004 fac0 bl 800c918 + 8008398: 4602 mov r2, r0 + 800839a: 683b ldr r3, [r7, #0] + 800839c: 4293 cmp r3, r2 + 800839e: d8ea bhi.n 8008376 + } + } + RadioStandby( ); + 80083a0: f000 fdad bl 8008efe + + return status; + 80083a4: 7dfb ldrb r3, [r7, #23] +} + 80083a6: 4618 mov r0, r3 + 80083a8: 3718 adds r7, #24 + 80083aa: 46bd mov sp, r7 + 80083ac: bd80 pop {r7, pc} + +080083ae : + +static uint32_t RadioRandom( void ) +{ + 80083ae: b580 push {r7, lr} + 80083b0: b082 sub sp, #8 + 80083b2: af00 add r7, sp, #0 + uint32_t rnd = 0; + 80083b4: 2300 movs r3, #0 + 80083b6: 607b str r3, [r7, #4] + + /* + * Radio setup for random number generation + */ + // Disable modem interrupts + SUBGRF_SetDioIrqParams( IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 80083b8: 2300 movs r3, #0 + 80083ba: 2200 movs r2, #0 + 80083bc: 2100 movs r1, #0 + 80083be: 2000 movs r0, #0 + 80083c0: f002 f9fe bl 800a7c0 + + rnd = SUBGRF_GetRandom(); + 80083c4: f001 ffaf bl 800a326 + 80083c8: 6078 str r0, [r7, #4] + + return rnd; + 80083ca: 687b ldr r3, [r7, #4] +} + 80083cc: 4618 mov r0, r3 + 80083ce: 3708 adds r7, #8 + 80083d0: 46bd mov sp, r7 + 80083d2: bd80 pop {r7, pc} + +080083d4 : + uint32_t bandwidthAfc, uint16_t preambleLen, + uint16_t symbTimeout, bool fixLen, + uint8_t payloadLen, + bool crcOn, bool freqHopOn, uint8_t hopPeriod, + bool iqInverted, bool rxContinuous ) +{ + 80083d4: b580 push {r7, lr} + 80083d6: b08a sub sp, #40 ; 0x28 + 80083d8: af00 add r7, sp, #0 + 80083da: 60b9 str r1, [r7, #8] + 80083dc: 607a str r2, [r7, #4] + 80083de: 461a mov r2, r3 + 80083e0: 4603 mov r3, r0 + 80083e2: 73fb strb r3, [r7, #15] + 80083e4: 4613 mov r3, r2 + 80083e6: 73bb strb r3, [r7, #14] +#if (RADIO_SIGFOX_ENABLE == 1) + uint8_t modReg; +#endif + SubgRf.RxContinuous = rxContinuous; + 80083e8: 4ab9 ldr r2, [pc, #740] ; (80086d0 ) + 80083ea: f897 3054 ldrb.w r3, [r7, #84] ; 0x54 + 80083ee: 7053 strb r3, [r2, #1] + RFW_DeInit(); + 80083f0: f003 f87d bl 800b4ee + if( rxContinuous == true ) + 80083f4: f897 3054 ldrb.w r3, [r7, #84] ; 0x54 + 80083f8: 2b00 cmp r3, #0 + 80083fa: d001 beq.n 8008400 + { + symbTimeout = 0; + 80083fc: 2300 movs r3, #0 + 80083fe: 873b strh r3, [r7, #56] ; 0x38 + } + if( fixLen == true ) + 8008400: f897 303c ldrb.w r3, [r7, #60] ; 0x3c + 8008404: 2b00 cmp r3, #0 + 8008406: d004 beq.n 8008412 + { + MaxPayloadLength = payloadLen; + 8008408: 4ab2 ldr r2, [pc, #712] ; (80086d4 ) + 800840a: f897 3040 ldrb.w r3, [r7, #64] ; 0x40 + 800840e: 7013 strb r3, [r2, #0] + 8008410: e002 b.n 8008418 + } + else + { + MaxPayloadLength = 0xFF; + 8008412: 4bb0 ldr r3, [pc, #704] ; (80086d4 ) + 8008414: 22ff movs r2, #255 ; 0xff + 8008416: 701a strb r2, [r3, #0] + } + + switch( modem ) + 8008418: 7bfb ldrb r3, [r7, #15] + 800841a: 2b05 cmp r3, #5 + 800841c: d009 beq.n 8008432 + 800841e: 2b05 cmp r3, #5 + 8008420: f300 81d7 bgt.w 80087d2 + 8008424: 2b00 cmp r3, #0 + 8008426: f000 80bf beq.w 80085a8 + 800842a: 2b01 cmp r3, #1 + 800842c: f000 8124 beq.w 8008678 + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + + break; + default: + break; + 8008430: e1cf b.n 80087d2 + SUBGRF_SetStopRxTimerOnPreambleDetect( true ); + 8008432: 2001 movs r0, #1 + 8008434: f002 f8bc bl 800a5b0 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8008438: 4ba5 ldr r3, [pc, #660] ; (80086d0 ) + 800843a: 2200 movs r2, #0 + 800843c: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 8008440: 4aa3 ldr r2, [pc, #652] ; (80086d0 ) + 8008442: 687b ldr r3, [r7, #4] + 8008444: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_05; + 8008446: 4ba2 ldr r3, [pc, #648] ; (80086d0 ) + 8008448: 2209 movs r2, #9 + 800844a: f883 2044 strb.w r2, [r3, #68] ; 0x44 + SubgRf.ModulationParams.Params.Gfsk.Fdev = 800; + 800844e: 4ba0 ldr r3, [pc, #640] ; (80086d0 ) + 8008450: f44f 7248 mov.w r2, #800 ; 0x320 + 8008454: 641a str r2, [r3, #64] ; 0x40 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8008456: 68b8 ldr r0, [r7, #8] + 8008458: f002 ff7c bl 800b354 + 800845c: 4603 mov r3, r0 + 800845e: 461a mov r2, r3 + 8008460: 4b9b ldr r3, [pc, #620] ; (80086d0 ) + 8008462: f883 2045 strb.w r2, [r3, #69] ; 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8008466: 4b9a ldr r3, [pc, #616] ; (80086d0 ) + 8008468: 2200 movs r2, #0 + 800846a: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 800846c: 8ebb ldrh r3, [r7, #52] ; 0x34 + 800846e: 00db lsls r3, r3, #3 + 8008470: b29a uxth r2, r3 + 8008472: 4b97 ldr r3, [pc, #604] ; (80086d0 ) + 8008474: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_OFF; + 8008476: 4b96 ldr r3, [pc, #600] ; (80086d0 ) + 8008478: 2200 movs r2, #0 + 800847a: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 2 << 3; // convert byte into bit + 800847c: 4b94 ldr r3, [pc, #592] ; (80086d0 ) + 800847e: 2210 movs r2, #16 + 8008480: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8008482: 4b93 ldr r3, [pc, #588] ; (80086d0 ) + 8008484: 2200 movs r2, #0 + 8008486: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = RADIO_PACKET_FIXED_LENGTH; + 8008488: 4b91 ldr r3, [pc, #580] ; (80086d0 ) + 800848a: 2200 movs r2, #0 + 800848c: 755a strb r2, [r3, #21] + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + 800848e: 4b91 ldr r3, [pc, #580] ; (80086d4 ) + 8008490: 781a ldrb r2, [r3, #0] + 8008492: 4b8f ldr r3, [pc, #572] ; (80086d0 ) + 8008494: 759a strb r2, [r3, #22] + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 8008496: 4b8e ldr r3, [pc, #568] ; (80086d0 ) + 8008498: 2201 movs r2, #1 + 800849a: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREE_OFF; + 800849c: 4b8c ldr r3, [pc, #560] ; (80086d0 ) + 800849e: 2200 movs r2, #0 + 80084a0: 761a strb r2, [r3, #24] + RadioSetModem( MODEM_SIGFOX_RX ); + 80084a2: 2005 movs r0, #5 + 80084a4: f7ff fec2 bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80084a8: 488b ldr r0, [pc, #556] ; (80086d8 ) + 80084aa: f002 fb1f bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80084ae: 488b ldr r0, [pc, #556] ; (80086dc ) + 80084b0: f002 fbee bl 800ac90 + SUBGRF_SetSyncWord( ( uint8_t[] ){0xB2, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 80084b4: 4a8a ldr r2, [pc, #552] ; (80086e0 ) + 80084b6: f107 031c add.w r3, r7, #28 + 80084ba: e892 0003 ldmia.w r2, {r0, r1} + 80084be: e883 0003 stmia.w r3, {r0, r1} + 80084c2: f107 031c add.w r3, r7, #28 + 80084c6: 4618 mov r0, r3 + 80084c8: f001 feab bl 800a222 + SUBGRF_SetWhiteningSeed( 0x01FF ); + 80084cc: f240 10ff movw r0, #511 ; 0x1ff + 80084d0: f001 fef6 bl 800a2c0 + modReg= RadioRead(SUBGHZ_AGCGFORSTCFGR); + 80084d4: f640 00b8 movw r0, #2232 ; 0x8b8 + 80084d8: f000 fe25 bl 8009126 + 80084dc: 4603 mov r3, r0 + 80084de: f887 3027 strb.w r3, [r7, #39] ; 0x27 + modReg&=RADIO_BIT_MASK(4); + 80084e2: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80084e6: f023 0310 bic.w r3, r3, #16 + 80084ea: f887 3027 strb.w r3, [r7, #39] ; 0x27 + RadioWrite(SUBGHZ_AGCGFORSTCFGR, modReg); + 80084ee: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 80084f2: 4619 mov r1, r3 + 80084f4: f640 00b8 movw r0, #2232 ; 0x8b8 + 80084f8: f000 fe03 bl 8009102 + RadioWrite(SUBGHZ_AGCGFORSTPOWTHR, 0x4 ); + 80084fc: 2104 movs r1, #4 + 80084fe: f640 00b9 movw r0, #2233 ; 0x8b9 + 8008502: f000 fdfe bl 8009102 + modReg= RadioRead(SUBGHZ_AGCRSSICTL0R); + 8008506: f640 009b movw r0, #2203 ; 0x89b + 800850a: f000 fe0c bl 8009126 + 800850e: 4603 mov r3, r0 + 8008510: f887 3027 strb.w r3, [r7, #39] ; 0x27 + modReg&=( RADIO_BIT_MASK(2) & RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + 8008514: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008518: f023 031c bic.w r3, r3, #28 + 800851c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + RadioWrite(SUBGHZ_AGCRSSICTL0R, (modReg| (0x1<<3) ) ); + 8008520: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008524: f043 0308 orr.w r3, r3, #8 + 8008528: b2db uxtb r3, r3 + 800852a: 4619 mov r1, r3 + 800852c: f640 009b movw r0, #2203 ; 0x89b + 8008530: f000 fde7 bl 8009102 + modReg= RadioRead(SUBGHZ_GAFCR); + 8008534: f240 60d1 movw r0, #1745 ; 0x6d1 + 8008538: f000 fdf5 bl 8009126 + 800853c: 4603 mov r3, r0 + 800853e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + modReg&=( RADIO_BIT_MASK(3) & RADIO_BIT_MASK(4) ); + 8008542: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008546: f023 0318 bic.w r3, r3, #24 + 800854a: f887 3027 strb.w r3, [r7, #39] ; 0x27 + RadioWrite(SUBGHZ_GAFCR, (modReg| (0x3<<3) )); + 800854e: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008552: f043 0318 orr.w r3, r3, #24 + 8008556: b2db uxtb r3, r3 + 8008558: 4619 mov r1, r3 + 800855a: f240 60d1 movw r0, #1745 ; 0x6d1 + 800855e: f000 fdd0 bl 8009102 + modReg= RadioRead(SUBGHZ_GBSYNCR); + 8008562: f240 60ac movw r0, #1708 ; 0x6ac + 8008566: f000 fdde bl 8009126 + 800856a: 4603 mov r3, r0 + 800856c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + modReg&=( RADIO_BIT_MASK(4) & RADIO_BIT_MASK(5) & RADIO_BIT_MASK(6) ); + 8008570: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008574: f023 0370 bic.w r3, r3, #112 ; 0x70 + 8008578: f887 3027 strb.w r3, [r7, #39] ; 0x27 + RadioWrite(SUBGHZ_GBSYNCR, (modReg| (0x5<<4) )); + 800857c: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008580: f043 0350 orr.w r3, r3, #80 ; 0x50 + 8008584: b2db uxtb r3, r3 + 8008586: 4619 mov r1, r3 + 8008588: f240 60ac movw r0, #1708 ; 0x6ac + 800858c: f000 fdb9 bl 8009102 + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + 8008590: 8f3b ldrh r3, [r7, #56] ; 0x38 + 8008592: f44f 52fa mov.w r2, #8000 ; 0x1f40 + 8008596: fb02 f303 mul.w r3, r2, r3 + 800859a: 461a mov r2, r3 + 800859c: 687b ldr r3, [r7, #4] + 800859e: fbb2 f3f3 udiv r3, r2, r3 + 80085a2: 4a4b ldr r2, [pc, #300] ; (80086d0 ) + 80085a4: 6093 str r3, [r2, #8] + break; + 80085a6: e115 b.n 80087d4 + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + 80085a8: 2000 movs r0, #0 + 80085aa: f002 f801 bl 800a5b0 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 80085ae: 4b48 ldr r3, [pc, #288] ; (80086d0 ) + 80085b0: 2200 movs r2, #0 + 80085b2: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 80085b6: 4a46 ldr r2, [pc, #280] ; (80086d0 ) + 80085b8: 687b ldr r3, [r7, #4] + 80085ba: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + 80085bc: 4b44 ldr r3, [pc, #272] ; (80086d0 ) + 80085be: 220b movs r2, #11 + 80085c0: f883 2044 strb.w r2, [r3, #68] ; 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 80085c4: 68b8 ldr r0, [r7, #8] + 80085c6: f002 fec5 bl 800b354 + 80085ca: 4603 mov r3, r0 + 80085cc: 461a mov r2, r3 + 80085ce: 4b40 ldr r3, [pc, #256] ; (80086d0 ) + 80085d0: f883 2045 strb.w r2, [r3, #69] ; 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 80085d4: 4b3e ldr r3, [pc, #248] ; (80086d0 ) + 80085d6: 2200 movs r2, #0 + 80085d8: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 80085da: 8ebb ldrh r3, [r7, #52] ; 0x34 + 80085dc: 00db lsls r3, r3, #3 + 80085de: b29a uxth r2, r3 + 80085e0: 4b3b ldr r3, [pc, #236] ; (80086d0 ) + 80085e2: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + 80085e4: 4b3a ldr r3, [pc, #232] ; (80086d0 ) + 80085e6: 2204 movs r2, #4 + 80085e8: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3; // convert byte into bit + 80085ea: 4b39 ldr r3, [pc, #228] ; (80086d0 ) + 80085ec: 2218 movs r2, #24 + 80085ee: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 80085f0: 4b37 ldr r3, [pc, #220] ; (80086d0 ) + 80085f2: 2200 movs r2, #0 + 80085f4: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + 80085f6: f897 303c ldrb.w r3, [r7, #60] ; 0x3c + 80085fa: f083 0301 eor.w r3, r3, #1 + 80085fe: b2db uxtb r3, r3 + 8008600: 461a mov r2, r3 + 8008602: 4b33 ldr r3, [pc, #204] ; (80086d0 ) + 8008604: 755a strb r2, [r3, #21] + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength; + 8008606: 4b33 ldr r3, [pc, #204] ; (80086d4 ) + 8008608: 781a ldrb r2, [r3, #0] + 800860a: 4b31 ldr r3, [pc, #196] ; (80086d0 ) + 800860c: 759a strb r2, [r3, #22] + if( crcOn == true ) + 800860e: f897 3044 ldrb.w r3, [r7, #68] ; 0x44 + 8008612: 2b00 cmp r3, #0 + 8008614: d003 beq.n 800861e + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + 8008616: 4b2e ldr r3, [pc, #184] ; (80086d0 ) + 8008618: 22f2 movs r2, #242 ; 0xf2 + 800861a: 75da strb r2, [r3, #23] + 800861c: e002 b.n 8008624 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 800861e: 4b2c ldr r3, [pc, #176] ; (80086d0 ) + 8008620: 2201 movs r2, #1 + 8008622: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + 8008624: 4b2a ldr r3, [pc, #168] ; (80086d0 ) + 8008626: 2201 movs r2, #1 + 8008628: 761a strb r2, [r3, #24] + RadioStandby( ); + 800862a: f000 fc68 bl 8008efe + RadioSetModem( MODEM_FSK ); + 800862e: 2000 movs r0, #0 + 8008630: f7ff fdfc bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8008634: 4828 ldr r0, [pc, #160] ; (80086d8 ) + 8008636: f002 fa59 bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800863a: 4828 ldr r0, [pc, #160] ; (80086dc ) + 800863c: f002 fb28 bl 800ac90 + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 8008640: 4a28 ldr r2, [pc, #160] ; (80086e4 ) + 8008642: f107 0314 add.w r3, r7, #20 + 8008646: e892 0003 ldmia.w r2, {r0, r1} + 800864a: e883 0003 stmia.w r3, {r0, r1} + 800864e: f107 0314 add.w r3, r7, #20 + 8008652: 4618 mov r0, r3 + 8008654: f001 fde5 bl 800a222 + SUBGRF_SetWhiteningSeed( 0x01FF ); + 8008658: f240 10ff movw r0, #511 ; 0x1ff + 800865c: f001 fe30 bl 800a2c0 + SubgRf.RxTimeout = ( uint32_t )(( symbTimeout * 8 * 1000 ) /datarate); + 8008660: 8f3b ldrh r3, [r7, #56] ; 0x38 + 8008662: f44f 52fa mov.w r2, #8000 ; 0x1f40 + 8008666: fb02 f303 mul.w r3, r2, r3 + 800866a: 461a mov r2, r3 + 800866c: 687b ldr r3, [r7, #4] + 800866e: fbb2 f3f3 udiv r3, r2, r3 + 8008672: 4a17 ldr r2, [pc, #92] ; (80086d0 ) + 8008674: 6093 str r3, [r2, #8] + break; + 8008676: e0ad b.n 80087d4 + SUBGRF_SetStopRxTimerOnPreambleDetect( false ); + 8008678: 2000 movs r0, #0 + 800867a: f001 ff99 bl 800a5b0 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 800867e: 4b14 ldr r3, [pc, #80] ; (80086d0 ) + 8008680: 2201 movs r2, #1 + 8008682: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t )datarate; + 8008686: 687b ldr r3, [r7, #4] + 8008688: b2da uxtb r2, r3 + 800868a: 4b11 ldr r3, [pc, #68] ; (80086d0 ) + 800868c: f883 2050 strb.w r2, [r3, #80] ; 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + 8008690: 4a15 ldr r2, [pc, #84] ; (80086e8 ) + 8008692: 68bb ldr r3, [r7, #8] + 8008694: 4413 add r3, r2 + 8008696: 781a ldrb r2, [r3, #0] + 8008698: 4b0d ldr r3, [pc, #52] ; (80086d0 ) + 800869a: f883 2051 strb.w r2, [r3, #81] ; 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t )coderate; + 800869e: 4a0c ldr r2, [pc, #48] ; (80086d0 ) + 80086a0: 7bbb ldrb r3, [r7, #14] + 80086a2: f882 3052 strb.w r3, [r2, #82] ; 0x52 + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 80086a6: 68bb ldr r3, [r7, #8] + 80086a8: 2b00 cmp r3, #0 + 80086aa: d105 bne.n 80086b8 + 80086ac: 687b ldr r3, [r7, #4] + 80086ae: 2b0b cmp r3, #11 + 80086b0: d008 beq.n 80086c4 + 80086b2: 687b ldr r3, [r7, #4] + 80086b4: 2b0c cmp r3, #12 + 80086b6: d005 beq.n 80086c4 + 80086b8: 68bb ldr r3, [r7, #8] + 80086ba: 2b01 cmp r3, #1 + 80086bc: d116 bne.n 80086ec + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 80086be: 687b ldr r3, [r7, #4] + 80086c0: 2b0c cmp r3, #12 + 80086c2: d113 bne.n 80086ec + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + 80086c4: 4b02 ldr r3, [pc, #8] ; (80086d0 ) + 80086c6: 2201 movs r2, #1 + 80086c8: f883 2053 strb.w r2, [r3, #83] ; 0x53 + 80086cc: e012 b.n 80086f4 + 80086ce: bf00 nop + 80086d0: 20000400 .word 0x20000400 + 80086d4: 20000009 .word 0x20000009 + 80086d8: 20000438 .word 0x20000438 + 80086dc: 2000040e .word 0x2000040e + 80086e0: 0800e020 .word 0x0800e020 + 80086e4: 0800e028 .word 0x0800e028 + 80086e8: 0800e490 .word 0x0800e490 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + 80086ec: 4b3b ldr r3, [pc, #236] ; (80087dc ) + 80086ee: 2200 movs r2, #0 + 80086f0: f883 2053 strb.w r2, [r3, #83] ; 0x53 + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 80086f4: 4b39 ldr r3, [pc, #228] ; (80087dc ) + 80086f6: 2201 movs r2, #1 + 80086f8: 739a strb r2, [r3, #14] + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 80086fa: 4b38 ldr r3, [pc, #224] ; (80087dc ) + 80086fc: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 8008700: 2b05 cmp r3, #5 + 8008702: d004 beq.n 800870e + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + 8008704: 4b35 ldr r3, [pc, #212] ; (80087dc ) + 8008706: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 800870a: 2b06 cmp r3, #6 + 800870c: d10a bne.n 8008724 + if( preambleLen < 12 ) + 800870e: 8ebb ldrh r3, [r7, #52] ; 0x34 + 8008710: 2b0b cmp r3, #11 + 8008712: d803 bhi.n 800871c + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + 8008714: 4b31 ldr r3, [pc, #196] ; (80087dc ) + 8008716: 220c movs r2, #12 + 8008718: 839a strh r2, [r3, #28] + if( preambleLen < 12 ) + 800871a: e006 b.n 800872a + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 800871c: 4a2f ldr r2, [pc, #188] ; (80087dc ) + 800871e: 8ebb ldrh r3, [r7, #52] ; 0x34 + 8008720: 8393 strh r3, [r2, #28] + if( preambleLen < 12 ) + 8008722: e002 b.n 800872a + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8008724: 4a2d ldr r2, [pc, #180] ; (80087dc ) + 8008726: 8ebb ldrh r3, [r7, #52] ; 0x34 + 8008728: 8393 strh r3, [r2, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + 800872a: f897 203c ldrb.w r2, [r7, #60] ; 0x3c + 800872e: 4b2b ldr r3, [pc, #172] ; (80087dc ) + 8008730: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8008732: 4b2b ldr r3, [pc, #172] ; (80087e0 ) + 8008734: 781a ldrb r2, [r3, #0] + 8008736: 4b29 ldr r3, [pc, #164] ; (80087dc ) + 8008738: 77da strb r2, [r3, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + 800873a: f897 2044 ldrb.w r2, [r7, #68] ; 0x44 + 800873e: 4b27 ldr r3, [pc, #156] ; (80087dc ) + 8008740: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + 8008744: f897 2050 ldrb.w r2, [r7, #80] ; 0x50 + 8008748: 4b24 ldr r3, [pc, #144] ; (80087dc ) + 800874a: f883 2021 strb.w r2, [r3, #33] ; 0x21 + RadioStandby( ); + 800874e: f000 fbd6 bl 8008efe + RadioSetModem( MODEM_LORA ); + 8008752: 2001 movs r0, #1 + 8008754: f7ff fd6a bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8008758: 4822 ldr r0, [pc, #136] ; (80087e4 ) + 800875a: f002 f9c7 bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800875e: 4822 ldr r0, [pc, #136] ; (80087e8 ) + 8008760: f002 fa96 bl 800ac90 + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + 8008764: 8f3b ldrh r3, [r7, #56] ; 0x38 + 8008766: b2db uxtb r3, r3 + 8008768: 4618 mov r0, r3 + 800876a: f001 ff30 bl 800a5ce + SUBGRF_WriteRegister(SUBGHZ_AGCCFG,SUBGRF_ReadRegister(SUBGHZ_AGCCFG)&0x1); + 800876e: f640 00a3 movw r0, #2211 ; 0x8a3 + 8008772: f002 fbe9 bl 800af48 + 8008776: 4603 mov r3, r0 + 8008778: f003 0301 and.w r3, r3, #1 + 800877c: b2db uxtb r3, r3 + 800877e: 4619 mov r1, r3 + 8008780: f640 00a3 movw r0, #2211 ; 0x8a3 + 8008784: f002 fbcc bl 800af20 + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + 8008788: 4b14 ldr r3, [pc, #80] ; (80087dc ) + 800878a: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 + 800878e: 2b01 cmp r3, #1 + 8008790: d10d bne.n 80087ae + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + 8008792: f240 7036 movw r0, #1846 ; 0x736 + 8008796: f002 fbd7 bl 800af48 + 800879a: 4603 mov r3, r0 + 800879c: f023 0304 bic.w r3, r3, #4 + 80087a0: b2db uxtb r3, r3 + 80087a2: 4619 mov r1, r3 + 80087a4: f240 7036 movw r0, #1846 ; 0x736 + 80087a8: f002 fbba bl 800af20 + 80087ac: e00c b.n 80087c8 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + 80087ae: f240 7036 movw r0, #1846 ; 0x736 + 80087b2: f002 fbc9 bl 800af48 + 80087b6: 4603 mov r3, r0 + 80087b8: f043 0304 orr.w r3, r3, #4 + 80087bc: b2db uxtb r3, r3 + 80087be: 4619 mov r1, r3 + 80087c0: f240 7036 movw r0, #1846 ; 0x736 + 80087c4: f002 fbac bl 800af20 + SubgRf.RxTimeout = 0xFFFF; + 80087c8: 4b04 ldr r3, [pc, #16] ; (80087dc ) + 80087ca: f64f 72ff movw r2, #65535 ; 0xffff + 80087ce: 609a str r2, [r3, #8] + break; + 80087d0: e000 b.n 80087d4 + break; + 80087d2: bf00 nop + } +} + 80087d4: bf00 nop + 80087d6: 3728 adds r7, #40 ; 0x28 + 80087d8: 46bd mov sp, r7 + 80087da: bd80 pop {r7, pc} + 80087dc: 20000400 .word 0x20000400 + 80087e0: 20000009 .word 0x20000009 + 80087e4: 20000438 .word 0x20000438 + 80087e8: 2000040e .word 0x2000040e + +080087ec : +static void RadioSetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev, + uint32_t bandwidth, uint32_t datarate, + uint8_t coderate, uint16_t preambleLen, + bool fixLen, bool crcOn, bool freqHopOn, + uint8_t hopPeriod, bool iqInverted, uint32_t timeout ) +{ + 80087ec: b580 push {r7, lr} + 80087ee: b086 sub sp, #24 + 80087f0: af00 add r7, sp, #0 + 80087f2: 60ba str r2, [r7, #8] + 80087f4: 607b str r3, [r7, #4] + 80087f6: 4603 mov r3, r0 + 80087f8: 73fb strb r3, [r7, #15] + 80087fa: 460b mov r3, r1 + 80087fc: 73bb strb r3, [r7, #14] +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + RFW_DeInit(); + 80087fe: f002 fe76 bl 800b4ee + switch( modem ) + 8008802: 7bfb ldrb r3, [r7, #15] + 8008804: 2b04 cmp r3, #4 + 8008806: f000 80c7 beq.w 8008998 + 800880a: 2b04 cmp r3, #4 + 800880c: f300 80d6 bgt.w 80089bc + 8008810: 2b00 cmp r3, #0 + 8008812: d002 beq.n 800881a + 8008814: 2b01 cmp r3, #1 + 8008816: d059 beq.n 80088cc + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + break; +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + 8008818: e0d0 b.n 80089bc + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 800881a: 4b77 ldr r3, [pc, #476] ; (80089f8 ) + 800881c: 2200 movs r2, #0 + 800881e: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = datarate; + 8008822: 4a75 ldr r2, [pc, #468] ; (80089f8 ) + 8008824: 6a3b ldr r3, [r7, #32] + 8008826: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = MOD_SHAPING_G_BT_1; + 8008828: 4b73 ldr r3, [pc, #460] ; (80089f8 ) + 800882a: 220b movs r2, #11 + 800882c: f883 2044 strb.w r2, [r3, #68] ; 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( bandwidth ); + 8008830: 6878 ldr r0, [r7, #4] + 8008832: f002 fd8f bl 800b354 + 8008836: 4603 mov r3, r0 + 8008838: 461a mov r2, r3 + 800883a: 4b6f ldr r3, [pc, #444] ; (80089f8 ) + 800883c: f883 2045 strb.w r2, [r3, #69] ; 0x45 + SubgRf.ModulationParams.Params.Gfsk.Fdev = fdev; + 8008840: 4a6d ldr r2, [pc, #436] ; (80089f8 ) + 8008842: 68bb ldr r3, [r7, #8] + 8008844: 6413 str r3, [r2, #64] ; 0x40 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8008846: 4b6c ldr r3, [pc, #432] ; (80089f8 ) + 8008848: 2200 movs r2, #0 + 800884a: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( preambleLen << 3 ); // convert byte into bit + 800884c: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800884e: 00db lsls r3, r3, #3 + 8008850: b29a uxth r2, r3 + 8008852: 4b69 ldr r3, [pc, #420] ; (80089f8 ) + 8008854: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; + 8008856: 4b68 ldr r3, [pc, #416] ; (80089f8 ) + 8008858: 2204 movs r2, #4 + 800885a: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = 3 << 3 ; // convert byte into bit + 800885c: 4b66 ldr r3, [pc, #408] ; (80089f8 ) + 800885e: 2218 movs r2, #24 + 8008860: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; + 8008862: 4b65 ldr r3, [pc, #404] ; (80089f8 ) + 8008864: 2200 movs r2, #0 + 8008866: 751a strb r2, [r3, #20] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( fixLen == true ) ? RADIO_PACKET_FIXED_LENGTH : RADIO_PACKET_VARIABLE_LENGTH; + 8008868: f897 302c ldrb.w r3, [r7, #44] ; 0x2c + 800886c: f083 0301 eor.w r3, r3, #1 + 8008870: b2db uxtb r3, r3 + 8008872: 461a mov r2, r3 + 8008874: 4b60 ldr r3, [pc, #384] ; (80089f8 ) + 8008876: 755a strb r2, [r3, #21] + if( crcOn == true ) + 8008878: f897 3030 ldrb.w r3, [r7, #48] ; 0x30 + 800887c: 2b00 cmp r3, #0 + 800887e: d003 beq.n 8008888 + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_2_BYTES_CCIT; + 8008880: 4b5d ldr r3, [pc, #372] ; (80089f8 ) + 8008882: 22f2 movs r2, #242 ; 0xf2 + 8008884: 75da strb r2, [r3, #23] + 8008886: e002 b.n 800888e + SubgRf.PacketParams.Params.Gfsk.CrcLength = RADIO_CRC_OFF; + 8008888: 4b5b ldr r3, [pc, #364] ; (80089f8 ) + 800888a: 2201 movs r2, #1 + 800888c: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = RADIO_DC_FREEWHITENING; + 800888e: 4b5a ldr r3, [pc, #360] ; (80089f8 ) + 8008890: 2201 movs r2, #1 + 8008892: 761a strb r2, [r3, #24] + RadioStandby( ); + 8008894: f000 fb33 bl 8008efe + RadioSetModem( MODEM_FSK ); + 8008898: 2000 movs r0, #0 + 800889a: f7ff fcc7 bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 800889e: 4857 ldr r0, [pc, #348] ; (80089fc ) + 80088a0: f002 f924 bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80088a4: 4856 ldr r0, [pc, #344] ; (8008a00 ) + 80088a6: f002 f9f3 bl 800ac90 + SUBGRF_SetSyncWord( ( uint8_t[] ){ 0xC1, 0x94, 0xC1, 0x00, 0x00, 0x00, 0x00, 0x00 } ); + 80088aa: 4a56 ldr r2, [pc, #344] ; (8008a04 ) + 80088ac: f107 0310 add.w r3, r7, #16 + 80088b0: e892 0003 ldmia.w r2, {r0, r1} + 80088b4: e883 0003 stmia.w r3, {r0, r1} + 80088b8: f107 0310 add.w r3, r7, #16 + 80088bc: 4618 mov r0, r3 + 80088be: f001 fcb0 bl 800a222 + SUBGRF_SetWhiteningSeed( 0x01FF ); + 80088c2: f240 10ff movw r0, #511 ; 0x1ff + 80088c6: f001 fcfb bl 800a2c0 + break; + 80088ca: e078 b.n 80089be + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 80088cc: 4b4a ldr r3, [pc, #296] ; (80089f8 ) + 80088ce: 2201 movs r2, #1 + 80088d0: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) datarate; + 80088d4: 6a3b ldr r3, [r7, #32] + 80088d6: b2da uxtb r2, r3 + 80088d8: 4b47 ldr r3, [pc, #284] ; (80089f8 ) + 80088da: f883 2050 strb.w r2, [r3, #80] ; 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = Bandwidths[bandwidth]; + 80088de: 4a4a ldr r2, [pc, #296] ; (8008a08 ) + 80088e0: 687b ldr r3, [r7, #4] + 80088e2: 4413 add r3, r2 + 80088e4: 781a ldrb r2, [r3, #0] + 80088e6: 4b44 ldr r3, [pc, #272] ; (80089f8 ) + 80088e8: f883 2051 strb.w r2, [r3, #81] ; 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate= ( RadioLoRaCodingRates_t )coderate; + 80088ec: 4a42 ldr r2, [pc, #264] ; (80089f8 ) + 80088ee: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 80088f2: f882 3052 strb.w r3, [r2, #82] ; 0x52 + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 80088f6: 687b ldr r3, [r7, #4] + 80088f8: 2b00 cmp r3, #0 + 80088fa: d105 bne.n 8008908 + 80088fc: 6a3b ldr r3, [r7, #32] + 80088fe: 2b0b cmp r3, #11 + 8008900: d008 beq.n 8008914 + 8008902: 6a3b ldr r3, [r7, #32] + 8008904: 2b0c cmp r3, #12 + 8008906: d005 beq.n 8008914 + 8008908: 687b ldr r3, [r7, #4] + 800890a: 2b01 cmp r3, #1 + 800890c: d107 bne.n 800891e + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 800890e: 6a3b ldr r3, [r7, #32] + 8008910: 2b0c cmp r3, #12 + 8008912: d104 bne.n 800891e + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x01; + 8008914: 4b38 ldr r3, [pc, #224] ; (80089f8 ) + 8008916: 2201 movs r2, #1 + 8008918: f883 2053 strb.w r2, [r3, #83] ; 0x53 + 800891c: e003 b.n 8008926 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0x00; + 800891e: 4b36 ldr r3, [pc, #216] ; (80089f8 ) + 8008920: 2200 movs r2, #0 + 8008922: f883 2053 strb.w r2, [r3, #83] ; 0x53 + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8008926: 4b34 ldr r3, [pc, #208] ; (80089f8 ) + 8008928: 2201 movs r2, #1 + 800892a: 739a strb r2, [r3, #14] + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 800892c: 4b32 ldr r3, [pc, #200] ; (80089f8 ) + 800892e: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + 8008932: 2b05 cmp r3, #5 + 8008934: d004 beq.n 8008940 + ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF6 ) ) + 8008936: 4b30 ldr r3, [pc, #192] ; (80089f8 ) + 8008938: f893 3050 ldrb.w r3, [r3, #80] ; 0x50 + if( ( SubgRf.ModulationParams.Params.LoRa.SpreadingFactor == LORA_SF5 ) || + 800893c: 2b06 cmp r3, #6 + 800893e: d10a bne.n 8008956 + if( preambleLen < 12 ) + 8008940: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8008942: 2b0b cmp r3, #11 + 8008944: d803 bhi.n 800894e + SubgRf.PacketParams.Params.LoRa.PreambleLength = 12; + 8008946: 4b2c ldr r3, [pc, #176] ; (80089f8 ) + 8008948: 220c movs r2, #12 + 800894a: 839a strh r2, [r3, #28] + if( preambleLen < 12 ) + 800894c: e006 b.n 800895c + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 800894e: 4a2a ldr r2, [pc, #168] ; (80089f8 ) + 8008950: 8d3b ldrh r3, [r7, #40] ; 0x28 + 8008952: 8393 strh r3, [r2, #28] + if( preambleLen < 12 ) + 8008954: e002 b.n 800895c + SubgRf.PacketParams.Params.LoRa.PreambleLength = preambleLen; + 8008956: 4a28 ldr r2, [pc, #160] ; (80089f8 ) + 8008958: 8d3b ldrh r3, [r7, #40] ; 0x28 + 800895a: 8393 strh r3, [r2, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t )fixLen; + 800895c: f897 202c ldrb.w r2, [r7, #44] ; 0x2c + 8008960: 4b25 ldr r3, [pc, #148] ; (80089f8 ) + 8008962: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8008964: 4b29 ldr r3, [pc, #164] ; (8008a0c ) + 8008966: 781a ldrb r2, [r3, #0] + 8008968: 4b23 ldr r3, [pc, #140] ; (80089f8 ) + 800896a: 77da strb r2, [r3, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t )crcOn; + 800896c: f897 2030 ldrb.w r2, [r7, #48] ; 0x30 + 8008970: 4b21 ldr r3, [pc, #132] ; (80089f8 ) + 8008972: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t )iqInverted; + 8008976: f897 203c ldrb.w r2, [r7, #60] ; 0x3c + 800897a: 4b1f ldr r3, [pc, #124] ; (80089f8 ) + 800897c: f883 2021 strb.w r2, [r3, #33] ; 0x21 + RadioStandby( ); + 8008980: f000 fabd bl 8008efe + RadioSetModem( MODEM_LORA ); + 8008984: 2001 movs r0, #1 + 8008986: f7ff fc51 bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 800898a: 481c ldr r0, [pc, #112] ; (80089fc ) + 800898c: f002 f8ae bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008990: 481b ldr r0, [pc, #108] ; (8008a00 ) + 8008992: f002 f97d bl 800ac90 + break; + 8008996: e012 b.n 80089be + RadioSetModem(MODEM_SIGFOX_TX); + 8008998: 2004 movs r0, #4 + 800899a: f7ff fc47 bl 800822c + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + 800899e: 4b16 ldr r3, [pc, #88] ; (80089f8 ) + 80089a0: 2202 movs r2, #2 + 80089a2: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Bpsk.BitRate = datarate; + 80089a6: 4a14 ldr r2, [pc, #80] ; (80089f8 ) + 80089a8: 6a3b ldr r3, [r7, #32] + 80089aa: 6493 str r3, [r2, #72] ; 0x48 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + 80089ac: 4b12 ldr r3, [pc, #72] ; (80089f8 ) + 80089ae: 2216 movs r2, #22 + 80089b0: f883 204c strb.w r2, [r3, #76] ; 0x4c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 80089b4: 4811 ldr r0, [pc, #68] ; (80089fc ) + 80089b6: f002 f899 bl 800aaec + break; + 80089ba: e000 b.n 80089be + break; + 80089bc: bf00 nop + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + 80089be: f997 300e ldrsb.w r3, [r7, #14] + 80089c2: 4618 mov r0, r3 + 80089c4: f002 fbc8 bl 800b158 + 80089c8: 4603 mov r3, r0 + 80089ca: 461a mov r2, r3 + 80089cc: 4b0a ldr r3, [pc, #40] ; (80089f8 ) + 80089ce: f883 2056 strb.w r2, [r3, #86] ; 0x56 + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 80089d2: 210e movs r1, #14 + 80089d4: f640 101f movw r0, #2335 ; 0x91f + 80089d8: f002 faa2 bl 800af20 + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + 80089dc: 4b06 ldr r3, [pc, #24] ; (80089f8 ) + 80089de: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 80089e2: 4618 mov r0, r3 + 80089e4: f002 fd97 bl 800b516 + SubgRf.TxTimeout = timeout; + 80089e8: 4a03 ldr r2, [pc, #12] ; (80089f8 ) + 80089ea: 6c3b ldr r3, [r7, #64] ; 0x40 + 80089ec: 6053 str r3, [r2, #4] +} + 80089ee: bf00 nop + 80089f0: 3718 adds r7, #24 + 80089f2: 46bd mov sp, r7 + 80089f4: bd80 pop {r7, pc} + 80089f6: bf00 nop + 80089f8: 20000400 .word 0x20000400 + 80089fc: 20000438 .word 0x20000438 + 8008a00: 2000040e .word 0x2000040e + 8008a04: 0800e028 .word 0x0800e028 + 8008a08: 0800e490 .word 0x0800e490 + 8008a0c: 20000009 .word 0x20000009 + +08008a10 : + +static bool RadioCheckRfFrequency( uint32_t frequency ) +{ + 8008a10: b480 push {r7} + 8008a12: b083 sub sp, #12 + 8008a14: af00 add r7, sp, #0 + 8008a16: 6078 str r0, [r7, #4] + return true; + 8008a18: 2301 movs r3, #1 +} + 8008a1a: 4618 mov r0, r3 + 8008a1c: 370c adds r7, #12 + 8008a1e: 46bd mov sp, r7 + 8008a20: bc80 pop {r7} + 8008a22: 4770 bx lr + +08008a24 : + +static uint32_t RadioGetLoRaBandwidthInHz( RadioLoRaBandwidths_t bw ) +{ + 8008a24: b480 push {r7} + 8008a26: b085 sub sp, #20 + 8008a28: af00 add r7, sp, #0 + 8008a2a: 4603 mov r3, r0 + 8008a2c: 71fb strb r3, [r7, #7] + uint32_t bandwidthInHz = 0; + 8008a2e: 2300 movs r3, #0 + 8008a30: 60fb str r3, [r7, #12] + + switch( bw ) + 8008a32: 79fb ldrb r3, [r7, #7] + 8008a34: 2b0a cmp r3, #10 + 8008a36: d83e bhi.n 8008ab6 + 8008a38: a201 add r2, pc, #4 ; (adr r2, 8008a40 ) + 8008a3a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008a3e: bf00 nop + 8008a40: 08008a6d .word 0x08008a6d + 8008a44: 08008a7d .word 0x08008a7d + 8008a48: 08008a8d .word 0x08008a8d + 8008a4c: 08008a9d .word 0x08008a9d + 8008a50: 08008aa5 .word 0x08008aa5 + 8008a54: 08008aab .word 0x08008aab + 8008a58: 08008ab1 .word 0x08008ab1 + 8008a5c: 08008ab7 .word 0x08008ab7 + 8008a60: 08008a75 .word 0x08008a75 + 8008a64: 08008a85 .word 0x08008a85 + 8008a68: 08008a95 .word 0x08008a95 + { + case LORA_BW_007: + bandwidthInHz = 7812UL; + 8008a6c: f641 6384 movw r3, #7812 ; 0x1e84 + 8008a70: 60fb str r3, [r7, #12] + break; + 8008a72: e020 b.n 8008ab6 + case LORA_BW_010: + bandwidthInHz = 10417UL; + 8008a74: f642 03b1 movw r3, #10417 ; 0x28b1 + 8008a78: 60fb str r3, [r7, #12] + break; + 8008a7a: e01c b.n 8008ab6 + case LORA_BW_015: + bandwidthInHz = 15625UL; + 8008a7c: f643 5309 movw r3, #15625 ; 0x3d09 + 8008a80: 60fb str r3, [r7, #12] + break; + 8008a82: e018 b.n 8008ab6 + case LORA_BW_020: + bandwidthInHz = 20833UL; + 8008a84: f245 1361 movw r3, #20833 ; 0x5161 + 8008a88: 60fb str r3, [r7, #12] + break; + 8008a8a: e014 b.n 8008ab6 + case LORA_BW_031: + bandwidthInHz = 31250UL; + 8008a8c: f647 2312 movw r3, #31250 ; 0x7a12 + 8008a90: 60fb str r3, [r7, #12] + break; + 8008a92: e010 b.n 8008ab6 + case LORA_BW_041: + bandwidthInHz = 41667UL; + 8008a94: f24a 23c3 movw r3, #41667 ; 0xa2c3 + 8008a98: 60fb str r3, [r7, #12] + break; + 8008a9a: e00c b.n 8008ab6 + case LORA_BW_062: + bandwidthInHz = 62500UL; + 8008a9c: f24f 4324 movw r3, #62500 ; 0xf424 + 8008aa0: 60fb str r3, [r7, #12] + break; + 8008aa2: e008 b.n 8008ab6 + case LORA_BW_125: + bandwidthInHz = 125000UL; + 8008aa4: 4b07 ldr r3, [pc, #28] ; (8008ac4 ) + 8008aa6: 60fb str r3, [r7, #12] + break; + 8008aa8: e005 b.n 8008ab6 + case LORA_BW_250: + bandwidthInHz = 250000UL; + 8008aaa: 4b07 ldr r3, [pc, #28] ; (8008ac8 ) + 8008aac: 60fb str r3, [r7, #12] + break; + 8008aae: e002 b.n 8008ab6 + case LORA_BW_500: + bandwidthInHz = 500000UL; + 8008ab0: 4b06 ldr r3, [pc, #24] ; (8008acc ) + 8008ab2: 60fb str r3, [r7, #12] + break; + 8008ab4: bf00 nop + } + + return bandwidthInHz; + 8008ab6: 68fb ldr r3, [r7, #12] +} + 8008ab8: 4618 mov r0, r3 + 8008aba: 3714 adds r7, #20 + 8008abc: 46bd mov sp, r7 + 8008abe: bc80 pop {r7} + 8008ac0: 4770 bx lr + 8008ac2: bf00 nop + 8008ac4: 0001e848 .word 0x0001e848 + 8008ac8: 0003d090 .word 0x0003d090 + 8008acc: 0007a120 .word 0x0007a120 + +08008ad0 : + +static uint32_t RadioGetGfskTimeOnAirNumerator( uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8008ad0: b480 push {r7} + 8008ad2: b083 sub sp, #12 + 8008ad4: af00 add r7, sp, #0 + 8008ad6: 6078 str r0, [r7, #4] + 8008ad8: 4608 mov r0, r1 + 8008ada: 4611 mov r1, r2 + 8008adc: 461a mov r2, r3 + 8008ade: 4603 mov r3, r0 + 8008ae0: 70fb strb r3, [r7, #3] + 8008ae2: 460b mov r3, r1 + 8008ae4: 803b strh r3, [r7, #0] + 8008ae6: 4613 mov r3, r2 + 8008ae8: 70bb strb r3, [r7, #2] + return ( preambleLen << 3 ) + + 8008aea: 883b ldrh r3, [r7, #0] + 8008aec: 00db lsls r3, r3, #3 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8008aee: 78ba ldrb r2, [r7, #2] + 8008af0: f082 0201 eor.w r2, r2, #1 + 8008af4: b2d2 uxtb r2, r2 + 8008af6: 2a00 cmp r2, #0 + 8008af8: d001 beq.n 8008afe + 8008afa: 2208 movs r2, #8 + 8008afc: e000 b.n 8008b00 + 8008afe: 2200 movs r2, #0 + return ( preambleLen << 3 ) + + 8008b00: 4413 add r3, r2 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8008b02: f103 0218 add.w r2, r3, #24 + ( ( payloadLen + ( ( crcOn == true ) ? 2 : 0 ) ) << 3 ); + 8008b06: 7c3b ldrb r3, [r7, #16] + 8008b08: 7d39 ldrb r1, [r7, #20] + 8008b0a: 2900 cmp r1, #0 + 8008b0c: d001 beq.n 8008b12 + 8008b0e: 2102 movs r1, #2 + 8008b10: e000 b.n 8008b14 + 8008b12: 2100 movs r1, #0 + 8008b14: 440b add r3, r1 + 8008b16: 00db lsls r3, r3, #3 + ( ( fixLen == false ) ? 8 : 0 ) + 24 + + 8008b18: 4413 add r3, r2 +} + 8008b1a: 4618 mov r0, r3 + 8008b1c: 370c adds r7, #12 + 8008b1e: 46bd mov sp, r7 + 8008b20: bc80 pop {r7} + 8008b22: 4770 bx lr + +08008b24 : + +static uint32_t RadioGetLoRaTimeOnAirNumerator( uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8008b24: b480 push {r7} + 8008b26: b08b sub sp, #44 ; 0x2c + 8008b28: af00 add r7, sp, #0 + 8008b2a: 60f8 str r0, [r7, #12] + 8008b2c: 60b9 str r1, [r7, #8] + 8008b2e: 4611 mov r1, r2 + 8008b30: 461a mov r2, r3 + 8008b32: 460b mov r3, r1 + 8008b34: 71fb strb r3, [r7, #7] + 8008b36: 4613 mov r3, r2 + 8008b38: 80bb strh r3, [r7, #4] + int32_t crDenom = coderate + 4; + 8008b3a: 79fb ldrb r3, [r7, #7] + 8008b3c: 3304 adds r3, #4 + 8008b3e: 617b str r3, [r7, #20] + bool lowDatareOptimize = false; + 8008b40: 2300 movs r3, #0 + 8008b42: f887 3027 strb.w r3, [r7, #39] ; 0x27 + + // Ensure that the preamble length is at least 12 symbols when using SF5 or SF6 + if( ( datarate == 5 ) || ( datarate == 6 ) ) + 8008b46: 68bb ldr r3, [r7, #8] + 8008b48: 2b05 cmp r3, #5 + 8008b4a: d002 beq.n 8008b52 + 8008b4c: 68bb ldr r3, [r7, #8] + 8008b4e: 2b06 cmp r3, #6 + 8008b50: d104 bne.n 8008b5c + { + if( preambleLen < 12 ) + 8008b52: 88bb ldrh r3, [r7, #4] + 8008b54: 2b0b cmp r3, #11 + 8008b56: d801 bhi.n 8008b5c + { + preambleLen = 12; + 8008b58: 230c movs r3, #12 + 8008b5a: 80bb strh r3, [r7, #4] + } + } + + if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) || + 8008b5c: 68fb ldr r3, [r7, #12] + 8008b5e: 2b00 cmp r3, #0 + 8008b60: d105 bne.n 8008b6e + 8008b62: 68bb ldr r3, [r7, #8] + 8008b64: 2b0b cmp r3, #11 + 8008b66: d008 beq.n 8008b7a + 8008b68: 68bb ldr r3, [r7, #8] + 8008b6a: 2b0c cmp r3, #12 + 8008b6c: d005 beq.n 8008b7a + 8008b6e: 68fb ldr r3, [r7, #12] + 8008b70: 2b01 cmp r3, #1 + 8008b72: d105 bne.n 8008b80 + ( ( bandwidth == 1 ) && ( datarate == 12 ) ) ) + 8008b74: 68bb ldr r3, [r7, #8] + 8008b76: 2b0c cmp r3, #12 + 8008b78: d102 bne.n 8008b80 + { + lowDatareOptimize = true; + 8008b7a: 2301 movs r3, #1 + 8008b7c: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + + int32_t ceilDenominator; + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8008b80: f897 3034 ldrb.w r3, [r7, #52] ; 0x34 + 8008b84: 00db lsls r3, r3, #3 + ( crcOn ? 16 : 0 ) - + 8008b86: f897 2038 ldrb.w r2, [r7, #56] ; 0x38 + 8008b8a: 2a00 cmp r2, #0 + 8008b8c: d001 beq.n 8008b92 + 8008b8e: 2210 movs r2, #16 + 8008b90: e000 b.n 8008b94 + 8008b92: 2200 movs r2, #0 + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8008b94: 4413 add r3, r2 + 8008b96: 461a mov r2, r3 + ( 4 * datarate ) + + 8008b98: 68bb ldr r3, [r7, #8] + 8008b9a: 009b lsls r3, r3, #2 + ( crcOn ? 16 : 0 ) - + 8008b9c: 1ad3 subs r3, r2, r3 + ( fixLen ? 0 : 20 ); + 8008b9e: f897 2030 ldrb.w r2, [r7, #48] ; 0x30 + 8008ba2: 2a00 cmp r2, #0 + 8008ba4: d001 beq.n 8008baa + 8008ba6: 2200 movs r2, #0 + 8008ba8: e000 b.n 8008bac + 8008baa: 2214 movs r2, #20 + ( 4 * datarate ) + + 8008bac: 4413 add r3, r2 + int32_t ceilNumerator = ( payloadLen << 3 ) + + 8008bae: 61fb str r3, [r7, #28] + + if( datarate <= 6 ) + 8008bb0: 68bb ldr r3, [r7, #8] + 8008bb2: 2b06 cmp r3, #6 + 8008bb4: d803 bhi.n 8008bbe + { + ceilDenominator = 4 * datarate; + 8008bb6: 68bb ldr r3, [r7, #8] + 8008bb8: 009b lsls r3, r3, #2 + 8008bba: 623b str r3, [r7, #32] + 8008bbc: e00e b.n 8008bdc + } + else + { + ceilNumerator += 8; + 8008bbe: 69fb ldr r3, [r7, #28] + 8008bc0: 3308 adds r3, #8 + 8008bc2: 61fb str r3, [r7, #28] + + if( lowDatareOptimize == true ) + 8008bc4: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 8008bc8: 2b00 cmp r3, #0 + 8008bca: d004 beq.n 8008bd6 + { + ceilDenominator = 4 * ( datarate - 2 ); + 8008bcc: 68bb ldr r3, [r7, #8] + 8008bce: 3b02 subs r3, #2 + 8008bd0: 009b lsls r3, r3, #2 + 8008bd2: 623b str r3, [r7, #32] + 8008bd4: e002 b.n 8008bdc + } + else + { + ceilDenominator = 4 * datarate; + 8008bd6: 68bb ldr r3, [r7, #8] + 8008bd8: 009b lsls r3, r3, #2 + 8008bda: 623b str r3, [r7, #32] + } + } + + if( ceilNumerator < 0 ) + 8008bdc: 69fb ldr r3, [r7, #28] + 8008bde: 2b00 cmp r3, #0 + 8008be0: da01 bge.n 8008be6 + { + ceilNumerator = 0; + 8008be2: 2300 movs r3, #0 + 8008be4: 61fb str r3, [r7, #28] + } + + // Perform integral ceil() + int32_t intermediate = + ( ( ceilNumerator + ceilDenominator - 1 ) / ceilDenominator ) * crDenom + preambleLen + 12; + 8008be6: 69fa ldr r2, [r7, #28] + 8008be8: 6a3b ldr r3, [r7, #32] + 8008bea: 4413 add r3, r2 + 8008bec: 1e5a subs r2, r3, #1 + 8008bee: 6a3b ldr r3, [r7, #32] + 8008bf0: fb92 f3f3 sdiv r3, r2, r3 + 8008bf4: 697a ldr r2, [r7, #20] + 8008bf6: fb03 f202 mul.w r2, r3, r2 + 8008bfa: 88bb ldrh r3, [r7, #4] + 8008bfc: 4413 add r3, r2 + int32_t intermediate = + 8008bfe: 330c adds r3, #12 + 8008c00: 61bb str r3, [r7, #24] + + if( datarate <= 6 ) + 8008c02: 68bb ldr r3, [r7, #8] + 8008c04: 2b06 cmp r3, #6 + 8008c06: d802 bhi.n 8008c0e + { + intermediate += 2; + 8008c08: 69bb ldr r3, [r7, #24] + 8008c0a: 3302 adds r3, #2 + 8008c0c: 61bb str r3, [r7, #24] + } + + return ( uint32_t )( ( 4 * intermediate + 1 ) * ( 1 << ( datarate - 2 ) ) ); + 8008c0e: 69bb ldr r3, [r7, #24] + 8008c10: 009b lsls r3, r3, #2 + 8008c12: 1c5a adds r2, r3, #1 + 8008c14: 68bb ldr r3, [r7, #8] + 8008c16: 3b02 subs r3, #2 + 8008c18: fa02 f303 lsl.w r3, r2, r3 +} + 8008c1c: 4618 mov r0, r3 + 8008c1e: 372c adds r7, #44 ; 0x2c + 8008c20: 46bd mov sp, r7 + 8008c22: bc80 pop {r7} + 8008c24: 4770 bx lr + ... + +08008c28 : + +static uint32_t RadioTimeOnAir( RadioModems_t modem, uint32_t bandwidth, + uint32_t datarate, uint8_t coderate, + uint16_t preambleLen, bool fixLen, uint8_t payloadLen, + bool crcOn ) +{ + 8008c28: b580 push {r7, lr} + 8008c2a: b08a sub sp, #40 ; 0x28 + 8008c2c: af04 add r7, sp, #16 + 8008c2e: 60b9 str r1, [r7, #8] + 8008c30: 607a str r2, [r7, #4] + 8008c32: 461a mov r2, r3 + 8008c34: 4603 mov r3, r0 + 8008c36: 73fb strb r3, [r7, #15] + 8008c38: 4613 mov r3, r2 + 8008c3a: 73bb strb r3, [r7, #14] + uint32_t numerator = 0; + 8008c3c: 2300 movs r3, #0 + 8008c3e: 617b str r3, [r7, #20] + uint32_t denominator = 1; + 8008c40: 2301 movs r3, #1 + 8008c42: 613b str r3, [r7, #16] + + switch( modem ) + 8008c44: 7bfb ldrb r3, [r7, #15] + 8008c46: 2b00 cmp r3, #0 + 8008c48: d002 beq.n 8008c50 + 8008c4a: 2b01 cmp r3, #1 + 8008c4c: d017 beq.n 8008c7e + fixLen, payloadLen, crcOn ); + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + } + break; + default: + break; + 8008c4e: e035 b.n 8008cbc + numerator = 1000U * RadioGetGfskTimeOnAirNumerator( datarate, coderate, + 8008c50: f897 0024 ldrb.w r0, [r7, #36] ; 0x24 + 8008c54: 8c3a ldrh r2, [r7, #32] + 8008c56: 7bb9 ldrb r1, [r7, #14] + 8008c58: f897 302c ldrb.w r3, [r7, #44] ; 0x2c + 8008c5c: 9301 str r3, [sp, #4] + 8008c5e: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 8008c62: 9300 str r3, [sp, #0] + 8008c64: 4603 mov r3, r0 + 8008c66: 6878 ldr r0, [r7, #4] + 8008c68: f7ff ff32 bl 8008ad0 + 8008c6c: 4603 mov r3, r0 + 8008c6e: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8008c72: fb02 f303 mul.w r3, r2, r3 + 8008c76: 617b str r3, [r7, #20] + denominator = datarate; + 8008c78: 687b ldr r3, [r7, #4] + 8008c7a: 613b str r3, [r7, #16] + break; + 8008c7c: e01e b.n 8008cbc + numerator = 1000U * RadioGetLoRaTimeOnAirNumerator( bandwidth, datarate, + 8008c7e: 8c39 ldrh r1, [r7, #32] + 8008c80: 7bba ldrb r2, [r7, #14] + 8008c82: f897 302c ldrb.w r3, [r7, #44] ; 0x2c + 8008c86: 9302 str r3, [sp, #8] + 8008c88: f897 3028 ldrb.w r3, [r7, #40] ; 0x28 + 8008c8c: 9301 str r3, [sp, #4] + 8008c8e: f897 3024 ldrb.w r3, [r7, #36] ; 0x24 + 8008c92: 9300 str r3, [sp, #0] + 8008c94: 460b mov r3, r1 + 8008c96: 6879 ldr r1, [r7, #4] + 8008c98: 68b8 ldr r0, [r7, #8] + 8008c9a: f7ff ff43 bl 8008b24 + 8008c9e: 4603 mov r3, r0 + 8008ca0: f44f 727a mov.w r2, #1000 ; 0x3e8 + 8008ca4: fb02 f303 mul.w r3, r2, r3 + 8008ca8: 617b str r3, [r7, #20] + denominator = RadioGetLoRaBandwidthInHz( Bandwidths[bandwidth] ); + 8008caa: 4a0a ldr r2, [pc, #40] ; (8008cd4 ) + 8008cac: 68bb ldr r3, [r7, #8] + 8008cae: 4413 add r3, r2 + 8008cb0: 781b ldrb r3, [r3, #0] + 8008cb2: 4618 mov r0, r3 + 8008cb4: f7ff feb6 bl 8008a24 + 8008cb8: 6138 str r0, [r7, #16] + break; + 8008cba: bf00 nop + } + // Perform integral ceil() + return DIVC( numerator, denominator ); + 8008cbc: 697a ldr r2, [r7, #20] + 8008cbe: 693b ldr r3, [r7, #16] + 8008cc0: 4413 add r3, r2 + 8008cc2: 1e5a subs r2, r3, #1 + 8008cc4: 693b ldr r3, [r7, #16] + 8008cc6: fbb2 f3f3 udiv r3, r2, r3 +} + 8008cca: 4618 mov r0, r3 + 8008ccc: 3718 adds r7, #24 + 8008cce: 46bd mov sp, r7 + 8008cd0: bd80 pop {r7, pc} + 8008cd2: bf00 nop + 8008cd4: 0800e490 .word 0x0800e490 + +08008cd8 : + +static radio_status_t RadioSend( uint8_t *buffer, uint8_t size ) +{ + 8008cd8: b580 push {r7, lr} + 8008cda: b084 sub sp, #16 + 8008cdc: af00 add r7, sp, #0 + 8008cde: 6078 str r0, [r7, #4] + 8008ce0: 460b mov r3, r1 + 8008ce2: 70fb strb r3, [r7, #3] + SUBGRF_SetDioIrqParams( IRQ_TX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_TX_DBG, + 8008ce4: 2300 movs r3, #0 + 8008ce6: 2200 movs r2, #0 + 8008ce8: f240 2101 movw r1, #513 ; 0x201 + 8008cec: f240 2001 movw r0, #513 ; 0x201 + 8008cf0: f001 fd66 bl 800a7c0 + + /* Set DBG pin */ + DBG_GPIO_RADIO_TX( SET ); + + /* Set RF switch */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + 8008cf4: 4b73 ldr r3, [pc, #460] ; (8008ec4 ) + 8008cf6: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 8008cfa: 2101 movs r1, #1 + 8008cfc: 4618 mov r0, r3 + 8008cfe: f002 fa03 bl 800b108 + /* WORKAROUND - Modulation Quality with 500 kHz LoRaTM Bandwidth*/ + /* RegTxModulation = @address 0x0889 */ + if( ( SubgRf.Modem == MODEM_LORA ) && ( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) ) + 8008d02: 4b70 ldr r3, [pc, #448] ; (8008ec4 ) + 8008d04: 781b ldrb r3, [r3, #0] + 8008d06: 2b01 cmp r3, #1 + 8008d08: d112 bne.n 8008d30 + 8008d0a: 4b6e ldr r3, [pc, #440] ; (8008ec4 ) + 8008d0c: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 + 8008d10: 2b06 cmp r3, #6 + 8008d12: d10d bne.n 8008d30 + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + 8008d14: f640 0089 movw r0, #2185 ; 0x889 + 8008d18: f002 f916 bl 800af48 + 8008d1c: 4603 mov r3, r0 + 8008d1e: f023 0304 bic.w r3, r3, #4 + 8008d22: b2db uxtb r3, r3 + 8008d24: 4619 mov r1, r3 + 8008d26: f640 0089 movw r0, #2185 ; 0x889 + 8008d2a: f002 f8f9 bl 800af20 + 8008d2e: e00c b.n 8008d4a + } + else + { + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + 8008d30: f640 0089 movw r0, #2185 ; 0x889 + 8008d34: f002 f908 bl 800af48 + 8008d38: 4603 mov r3, r0 + 8008d3a: f043 0304 orr.w r3, r3, #4 + 8008d3e: b2db uxtb r3, r3 + 8008d40: 4619 mov r1, r3 + 8008d42: f640 0089 movw r0, #2185 ; 0x889 + 8008d46: f002 f8eb bl 800af20 + } + else +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + { + /* WORKAROUND END */ + switch( SubgRf.Modem ) + 8008d4a: 4b5e ldr r3, [pc, #376] ; (8008ec4 ) + 8008d4c: 781b ldrb r3, [r3, #0] + 8008d4e: 2b04 cmp r3, #4 + 8008d50: f200 80a8 bhi.w 8008ea4 + 8008d54: a201 add r2, pc, #4 ; (adr r2, 8008d5c ) + 8008d56: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8008d5a: bf00 nop + 8008d5c: 08008d8b .word 0x08008d8b + 8008d60: 08008d71 .word 0x08008d71 + 8008d64: 08008d8b .word 0x08008d8b + 8008d68: 08008ded .word 0x08008ded + 8008d6c: 08008e0d .word 0x08008e0d + { + case MODEM_LORA: + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = size; + 8008d70: 4a54 ldr r2, [pc, #336] ; (8008ec4 ) + 8008d72: 78fb ldrb r3, [r7, #3] + 8008d74: 77d3 strb r3, [r2, #31] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008d76: 4854 ldr r0, [pc, #336] ; (8008ec8 ) + 8008d78: f001 ff8a bl 800ac90 + SUBGRF_SendPayload( buffer, size, 0 ); + 8008d7c: 78fb ldrb r3, [r7, #3] + 8008d7e: 2200 movs r2, #0 + 8008d80: 4619 mov r1, r3 + 8008d82: 6878 ldr r0, [r7, #4] + 8008d84: f001 fa3a bl 800a1fc + break; + 8008d88: e08d b.n 8008ea6 + } + case MODEM_MSK: + case MODEM_FSK: + { + if ( 1UL == RFW_Is_Init( ) ) + 8008d8a: f002 fbb6 bl 800b4fa + 8008d8e: 4603 mov r3, r0 + 8008d90: 2b01 cmp r3, #1 + 8008d92: d11e bne.n 8008dd2 + { + uint8_t outsize; + if ( 0UL == RFW_TransmitInit( buffer,size, &outsize ) ) + 8008d94: f107 020d add.w r2, r7, #13 + 8008d98: 78fb ldrb r3, [r7, #3] + 8008d9a: 4619 mov r1, r3 + 8008d9c: 6878 ldr r0, [r7, #4] + 8008d9e: f002 fbc4 bl 800b52a + 8008da2: 4603 mov r3, r0 + 8008da4: 2b00 cmp r3, #0 + 8008da6: d10c bne.n 8008dc2 + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = outsize; + 8008da8: 7b7a ldrb r2, [r7, #13] + 8008daa: 4b46 ldr r3, [pc, #280] ; (8008ec4 ) + 8008dac: 759a strb r2, [r3, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008dae: 4846 ldr r0, [pc, #280] ; (8008ec8 ) + 8008db0: f001 ff6e bl 800ac90 + SUBGRF_SendPayload( buffer, outsize, 0 ); + 8008db4: 7b7b ldrb r3, [r7, #13] + 8008db6: 2200 movs r2, #0 + 8008db8: 4619 mov r1, r3 + 8008dba: 6878 ldr r0, [r7, #4] + 8008dbc: f001 fa1e bl 800a1fc + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + SUBGRF_SendPayload( buffer, size, 0 ); + } + break; + 8008dc0: e071 b.n 8008ea6 + MW_LOG( TS_ON, VLEVEL_M, "RadioSend Oversize\r\n" ); + 8008dc2: 4b42 ldr r3, [pc, #264] ; (8008ecc ) + 8008dc4: 2201 movs r2, #1 + 8008dc6: 2100 movs r1, #0 + 8008dc8: 2002 movs r0, #2 + 8008dca: f003 fe71 bl 800cab0 + return RADIO_STATUS_ERROR; + 8008dce: 2303 movs r3, #3 + 8008dd0: e073 b.n 8008eba + SubgRf.PacketParams.Params.Gfsk.PayloadLength = size; + 8008dd2: 4a3c ldr r2, [pc, #240] ; (8008ec4 ) + 8008dd4: 78fb ldrb r3, [r7, #3] + 8008dd6: 7593 strb r3, [r2, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008dd8: 483b ldr r0, [pc, #236] ; (8008ec8 ) + 8008dda: f001 ff59 bl 800ac90 + SUBGRF_SendPayload( buffer, size, 0 ); + 8008dde: 78fb ldrb r3, [r7, #3] + 8008de0: 2200 movs r2, #0 + 8008de2: 4619 mov r1, r3 + 8008de4: 6878 ldr r0, [r7, #4] + 8008de6: f001 fa09 bl 800a1fc + break; + 8008dea: e05c b.n 8008ea6 + } + case MODEM_BPSK: + { + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + 8008dec: 4b35 ldr r3, [pc, #212] ; (8008ec4 ) + 8008dee: 2202 movs r2, #2 + 8008df0: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size; + 8008df2: 4a34 ldr r2, [pc, #208] ; (8008ec4 ) + 8008df4: 78fb ldrb r3, [r7, #3] + 8008df6: 7693 strb r3, [r2, #26] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008df8: 4833 ldr r0, [pc, #204] ; (8008ec8 ) + 8008dfa: f001 ff49 bl 800ac90 + SUBGRF_SendPayload( buffer, size, 0 ); + 8008dfe: 78fb ldrb r3, [r7, #3] + 8008e00: 2200 movs r2, #0 + 8008e02: 4619 mov r1, r3 + 8008e04: 6878 ldr r0, [r7, #4] + 8008e06: f001 f9f9 bl 800a1fc + break; + 8008e0a: e04c b.n 8008ea6 + case MODEM_SIGFOX_TX: + { + /* from bpsk to dbpsk */ + /* first 1 bit duplicated */ + /* RadioBuffer is 1 bytes more */ + payload_integration( RadioBuffer, buffer, size ); + 8008e0c: 78fb ldrb r3, [r7, #3] + 8008e0e: 461a mov r2, r3 + 8008e10: 6879 ldr r1, [r7, #4] + 8008e12: 482f ldr r0, [pc, #188] ; (8008ed0 ) + 8008e14: f000 fccc bl 80097b0 + + SubgRf.PacketParams.PacketType = PACKET_TYPE_BPSK; + 8008e18: 4b2a ldr r3, [pc, #168] ; (8008ec4 ) + 8008e1a: 2202 movs r2, #2 + 8008e1c: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Bpsk.PayloadLength = size + 1; + 8008e1e: 78fb ldrb r3, [r7, #3] + 8008e20: 3301 adds r3, #1 + 8008e22: b2da uxtb r2, r3 + 8008e24: 4b27 ldr r3, [pc, #156] ; (8008ec4 ) + 8008e26: 769a strb r2, [r3, #26] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8008e28: 4827 ldr r0, [pc, #156] ; (8008ec8 ) + 8008e2a: f001 ff31 bl 800ac90 + + RadioWrite( SUBGHZ_RAM_RAMPUPL, 0 ); // clean start-up LSB + 8008e2e: 2100 movs r1, #0 + 8008e30: 20f1 movs r0, #241 ; 0xf1 + 8008e32: f000 f966 bl 8009102 + RadioWrite( SUBGHZ_RAM_RAMPUPH, 0 ); // clean start-up MSB + 8008e36: 2100 movs r1, #0 + 8008e38: 20f0 movs r0, #240 ; 0xf0 + 8008e3a: f000 f962 bl 8009102 + if( SubgRf.ModulationParams.Params.Bpsk.BitRate == 100 ) + 8008e3e: 4b21 ldr r3, [pc, #132] ; (8008ec4 ) + 8008e40: 6c9b ldr r3, [r3, #72] ; 0x48 + 8008e42: 2b64 cmp r3, #100 ; 0x64 + 8008e44: d108 bne.n 8008e58 + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0x70 ); // clean end of frame LSB + 8008e46: 2170 movs r1, #112 ; 0x70 + 8008e48: 20f3 movs r0, #243 ; 0xf3 + 8008e4a: f000 f95a bl 8009102 + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x1D ); // clean end of frame MSB + 8008e4e: 211d movs r1, #29 + 8008e50: 20f2 movs r0, #242 ; 0xf2 + 8008e52: f000 f956 bl 8009102 + 8008e56: e007 b.n 8008e68 + } + else // 600 bps + { + RadioWrite( SUBGHZ_RAM_RAMPDNL, 0xE1 ); // clean end of frame LSB + 8008e58: 21e1 movs r1, #225 ; 0xe1 + 8008e5a: 20f3 movs r0, #243 ; 0xf3 + 8008e5c: f000 f951 bl 8009102 + RadioWrite( SUBGHZ_RAM_RAMPDNH, 0x04 ); // clean end of frame MSB + 8008e60: 2104 movs r1, #4 + 8008e62: 20f2 movs r0, #242 ; 0xf2 + 8008e64: f000 f94d bl 8009102 + } + + uint16_t bitNum = ( size * 8 ) + 2; + 8008e68: 78fb ldrb r3, [r7, #3] + 8008e6a: b29b uxth r3, r3 + 8008e6c: 00db lsls r3, r3, #3 + 8008e6e: b29b uxth r3, r3 + 8008e70: 3302 adds r3, #2 + 8008e72: 81fb strh r3, [r7, #14] + RadioWrite( SUBGHZ_RAM_FRAMELIMH, ( bitNum >> 8 ) & 0x00FF ); // limit frame + 8008e74: 89fb ldrh r3, [r7, #14] + 8008e76: 0a1b lsrs r3, r3, #8 + 8008e78: b29b uxth r3, r3 + 8008e7a: b2db uxtb r3, r3 + 8008e7c: 4619 mov r1, r3 + 8008e7e: 20f4 movs r0, #244 ; 0xf4 + 8008e80: f000 f93f bl 8009102 + RadioWrite( SUBGHZ_RAM_FRAMELIML, bitNum & 0x00FF ); // limit frame + 8008e84: 89fb ldrh r3, [r7, #14] + 8008e86: b2db uxtb r3, r3 + 8008e88: 4619 mov r1, r3 + 8008e8a: 20f5 movs r0, #245 ; 0xf5 + 8008e8c: f000 f939 bl 8009102 + SUBGRF_SendPayload( RadioBuffer, size + 1, 0xFFFFFF ); + 8008e90: 78fb ldrb r3, [r7, #3] + 8008e92: 3301 adds r3, #1 + 8008e94: b2db uxtb r3, r3 + 8008e96: f06f 427f mvn.w r2, #4278190080 ; 0xff000000 + 8008e9a: 4619 mov r1, r3 + 8008e9c: 480c ldr r0, [pc, #48] ; (8008ed0 ) + 8008e9e: f001 f9ad bl 800a1fc + break; + 8008ea2: e000 b.n 8008ea6 + } +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + default: + break; + 8008ea4: bf00 nop + } + + TimerSetValue( &TxTimeoutTimer, SubgRf.TxTimeout ); + 8008ea6: 4b07 ldr r3, [pc, #28] ; (8008ec4 ) + 8008ea8: 685b ldr r3, [r3, #4] + 8008eaa: 4619 mov r1, r3 + 8008eac: 4809 ldr r0, [pc, #36] ; (8008ed4 ) + 8008eae: f003 fcf7 bl 800c8a0 + TimerStart( &TxTimeoutTimer ); + 8008eb2: 4808 ldr r0, [pc, #32] ; (8008ed4 ) + 8008eb4: f003 fc16 bl 800c6e4 + } + + return RADIO_STATUS_OK; + 8008eb8: 2300 movs r3, #0 +} + 8008eba: 4618 mov r0, r3 + 8008ebc: 3710 adds r7, #16 + 8008ebe: 46bd mov sp, r7 + 8008ec0: bd80 pop {r7, pc} + 8008ec2: bf00 nop + 8008ec4: 20000400 .word 0x20000400 + 8008ec8: 2000040e .word 0x2000040e + 8008ecc: 0800e030 .word 0x0800e030 + 8008ed0: 200002fc .word 0x200002fc + 8008ed4: 2000045c .word 0x2000045c + +08008ed8 : + +static void RadioSleep( void ) +{ + 8008ed8: b580 push {r7, lr} + 8008eda: b082 sub sp, #8 + 8008edc: af00 add r7, sp, #0 + SleepParams_t params = { 0 }; + 8008ede: 2300 movs r3, #0 + 8008ee0: 713b strb r3, [r7, #4] + + params.Fields.WarmStart = 1; + 8008ee2: 793b ldrb r3, [r7, #4] + 8008ee4: f043 0304 orr.w r3, r3, #4 + 8008ee8: 713b strb r3, [r7, #4] + SUBGRF_SetSleep( params ); + 8008eea: 7938 ldrb r0, [r7, #4] + 8008eec: f001 fa62 bl 800a3b4 + + RADIO_DELAY_MS( 2 ); + 8008ef0: 2002 movs r0, #2 + 8008ef2: f7f7 ff27 bl 8000d44 +} + 8008ef6: bf00 nop + 8008ef8: 3708 adds r7, #8 + 8008efa: 46bd mov sp, r7 + 8008efc: bd80 pop {r7, pc} + +08008efe : + +static void RadioStandby( void ) +{ + 8008efe: b580 push {r7, lr} + 8008f00: af00 add r7, sp, #0 + SUBGRF_SetStandby( STDBY_RC ); + 8008f02: 2000 movs r0, #0 + 8008f04: f001 fa88 bl 800a418 +} + 8008f08: bf00 nop + 8008f0a: bd80 pop {r7, pc} + +08008f0c : + +static void RadioRx( uint32_t timeout ) +{ + 8008f0c: b580 push {r7, lr} + 8008f0e: b082 sub sp, #8 + 8008f10: af00 add r7, sp, #0 + 8008f12: 6078 str r0, [r7, #4] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init( ) ) + 8008f14: f002 faf1 bl 800b4fa + 8008f18: 4603 mov r3, r0 + 8008f1a: 2b01 cmp r3, #1 + 8008f1c: d102 bne.n 8008f24 + { + RFW_ReceiveInit( ); + 8008f1e: f002 fb14 bl 800b54a + 8008f22: e007 b.n 8008f34 + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 8008f24: 2300 movs r3, #0 + 8008f26: 2200 movs r2, #0 + 8008f28: f240 2162 movw r1, #610 ; 0x262 + 8008f2c: f240 2062 movw r0, #610 ; 0x262 + 8008f30: f001 fc46 bl 800a7c0 + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + + if( timeout != 0 ) + 8008f34: 687b ldr r3, [r7, #4] + 8008f36: 2b00 cmp r3, #0 + 8008f38: d006 beq.n 8008f48 + { + TimerSetValue( &RxTimeoutTimer, timeout ); + 8008f3a: 6879 ldr r1, [r7, #4] + 8008f3c: 4811 ldr r0, [pc, #68] ; (8008f84 ) + 8008f3e: f003 fcaf bl 800c8a0 + TimerStart( &RxTimeoutTimer ); + 8008f42: 4810 ldr r0, [pc, #64] ; (8008f84 ) + 8008f44: f003 fbce bl 800c6e4 + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008f48: 4b0f ldr r3, [pc, #60] ; (8008f88 ) + 8008f4a: 2200 movs r2, #0 + 8008f4c: 659a str r2, [r3, #88] ; 0x58 + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8008f4e: 4b0e ldr r3, [pc, #56] ; (8008f88 ) + 8008f50: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 8008f54: 2100 movs r1, #0 + 8008f56: 4618 mov r0, r3 + 8008f58: f002 f8d6 bl 800b108 + + if( SubgRf.RxContinuous == true ) + 8008f5c: 4b0a ldr r3, [pc, #40] ; (8008f88 ) + 8008f5e: 785b ldrb r3, [r3, #1] + 8008f60: 2b00 cmp r3, #0 + 8008f62: d004 beq.n 8008f6e + { + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + 8008f64: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 8008f68: f001 fa92 bl 800a490 + } + else + { + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + } +} + 8008f6c: e005 b.n 8008f7a + SUBGRF_SetRx( SubgRf.RxTimeout << 6 ); + 8008f6e: 4b06 ldr r3, [pc, #24] ; (8008f88 ) + 8008f70: 689b ldr r3, [r3, #8] + 8008f72: 019b lsls r3, r3, #6 + 8008f74: 4618 mov r0, r3 + 8008f76: f001 fa8b bl 800a490 +} + 8008f7a: bf00 nop + 8008f7c: 3708 adds r7, #8 + 8008f7e: 46bd mov sp, r7 + 8008f80: bd80 pop {r7, pc} + 8008f82: bf00 nop + 8008f84: 20000474 .word 0x20000474 + 8008f88: 20000400 .word 0x20000400 + +08008f8c : + +static void RadioRxBoosted( uint32_t timeout ) +{ + 8008f8c: b580 push {r7, lr} + 8008f8e: b082 sub sp, #8 + 8008f90: af00 add r7, sp, #0 + 8008f92: 6078 str r0, [r7, #4] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + if( 1UL == RFW_Is_Init() ) + 8008f94: f002 fab1 bl 800b4fa + 8008f98: 4603 mov r3, r0 + 8008f9a: 2b01 cmp r3, #1 + 8008f9c: d102 bne.n 8008fa4 + { + RFW_ReceiveInit(); + 8008f9e: f002 fad4 bl 800b54a + 8008fa2: e007 b.n 8008fb4 + } + else + { + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 8008fa4: 2300 movs r3, #0 + 8008fa6: 2200 movs r2, #0 + 8008fa8: f240 2162 movw r1, #610 ; 0x262 + 8008fac: f240 2062 movw r0, #610 ; 0x262 + 8008fb0: f001 fc06 bl 800a7c0 + IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + } + if( timeout != 0 ) + 8008fb4: 687b ldr r3, [r7, #4] + 8008fb6: 2b00 cmp r3, #0 + 8008fb8: d006 beq.n 8008fc8 + { + TimerSetValue( &RxTimeoutTimer, timeout ); + 8008fba: 6879 ldr r1, [r7, #4] + 8008fbc: 4811 ldr r0, [pc, #68] ; (8009004 ) + 8008fbe: f003 fc6f bl 800c8a0 + TimerStart( &RxTimeoutTimer ); + 8008fc2: 4810 ldr r0, [pc, #64] ; (8009004 ) + 8008fc4: f003 fb8e bl 800c6e4 + } + /* switch off RxDcPreambleDetect See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 0; + 8008fc8: 4b0f ldr r3, [pc, #60] ; (8009008 ) + 8008fca: 2200 movs r2, #0 + 8008fcc: 659a str r2, [r3, #88] ; 0x58 + /* Set DBG pin */ + DBG_GPIO_RADIO_RX( SET ); + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8008fce: 4b0e ldr r3, [pc, #56] ; (8009008 ) + 8008fd0: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 8008fd4: 2100 movs r1, #0 + 8008fd6: 4618 mov r0, r3 + 8008fd8: f002 f896 bl 800b108 + + if( SubgRf.RxContinuous == true ) + 8008fdc: 4b0a ldr r3, [pc, #40] ; (8009008 ) + 8008fde: 785b ldrb r3, [r3, #1] + 8008fe0: 2b00 cmp r3, #0 + 8008fe2: d004 beq.n 8008fee + { + SUBGRF_SetRxBoosted( 0xFFFFFF ); // Rx Continuous + 8008fe4: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 8008fe8: f001 fa72 bl 800a4d0 + } + else + { + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + } +} + 8008fec: e005 b.n 8008ffa + SUBGRF_SetRxBoosted( SubgRf.RxTimeout << 6 ); + 8008fee: 4b06 ldr r3, [pc, #24] ; (8009008 ) + 8008ff0: 689b ldr r3, [r3, #8] + 8008ff2: 019b lsls r3, r3, #6 + 8008ff4: 4618 mov r0, r3 + 8008ff6: f001 fa6b bl 800a4d0 +} + 8008ffa: bf00 nop + 8008ffc: 3708 adds r7, #8 + 8008ffe: 46bd mov sp, r7 + 8009000: bd80 pop {r7, pc} + 8009002: bf00 nop + 8009004: 20000474 .word 0x20000474 + 8009008: 20000400 .word 0x20000400 + +0800900c : + +static void RadioSetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + 800900c: b580 push {r7, lr} + 800900e: b082 sub sp, #8 + 8009010: af00 add r7, sp, #0 + 8009012: 6078 str r0, [r7, #4] + 8009014: 6039 str r1, [r7, #0] + /*See STM32WL Errata: RadioSetRxDutyCycle*/ + SubgRf.RxDcPreambleDetectTimeout = 2 * rxTime + sleepTime; + 8009016: 687b ldr r3, [r7, #4] + 8009018: 005a lsls r2, r3, #1 + 800901a: 683b ldr r3, [r7, #0] + 800901c: 4413 add r3, r2 + 800901e: 4a0c ldr r2, [pc, #48] ; (8009050 ) + 8009020: 6593 str r3, [r2, #88] ; 0x58 + /*Enable also the IRQ_PREAMBLE_DETECTED*/ + SUBGRF_SetDioIrqParams( IRQ_RADIO_ALL, IRQ_RADIO_ALL, IRQ_RADIO_NONE, IRQ_RADIO_NONE ); + 8009022: 2300 movs r3, #0 + 8009024: 2200 movs r2, #0 + 8009026: f64f 71ff movw r1, #65535 ; 0xffff + 800902a: f64f 70ff movw r0, #65535 ; 0xffff + 800902e: f001 fbc7 bl 800a7c0 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8009032: 4b07 ldr r3, [pc, #28] ; (8009050 ) + 8009034: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 8009038: 2100 movs r1, #0 + 800903a: 4618 mov r0, r3 + 800903c: f002 f864 bl 800b108 + /* Start Rx DutyCycle*/ + SUBGRF_SetRxDutyCycle( rxTime, sleepTime ); + 8009040: 6839 ldr r1, [r7, #0] + 8009042: 6878 ldr r0, [r7, #4] + 8009044: f001 fa68 bl 800a518 +} + 8009048: bf00 nop + 800904a: 3708 adds r7, #8 + 800904c: 46bd mov sp, r7 + 800904e: bd80 pop {r7, pc} + 8009050: 20000400 .word 0x20000400 + +08009054 : + +static void RadioStartCad( void ) +{ + 8009054: b580 push {r7, lr} + 8009056: af00 add r7, sp, #0 + /* RF switch configuration */ + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_RX ); + 8009058: 4b09 ldr r3, [pc, #36] ; (8009080 ) + 800905a: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 800905e: 2100 movs r1, #0 + 8009060: 4618 mov r0, r3 + 8009062: f002 f851 bl 800b108 + + SUBGRF_SetDioIrqParams( IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + 8009066: 2300 movs r3, #0 + 8009068: 2200 movs r2, #0 + 800906a: f44f 71c0 mov.w r1, #384 ; 0x180 + 800906e: f44f 70c0 mov.w r0, #384 ; 0x180 + 8009072: f001 fba5 bl 800a7c0 + IRQ_CAD_CLEAR | IRQ_CAD_DETECTED, + IRQ_RADIO_NONE, + IRQ_RADIO_NONE ); + SUBGRF_SetCad( ); + 8009076: f001 fa7b bl 800a570 +} + 800907a: bf00 nop + 800907c: bd80 pop {r7, pc} + 800907e: bf00 nop + 8009080: 20000400 .word 0x20000400 + +08009084 : + +static void RadioSetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time ) +{ + 8009084: b580 push {r7, lr} + 8009086: b084 sub sp, #16 + 8009088: af00 add r7, sp, #0 + 800908a: 6078 str r0, [r7, #4] + 800908c: 460b mov r3, r1 + 800908e: 70fb strb r3, [r7, #3] + 8009090: 4613 mov r3, r2 + 8009092: 803b strh r3, [r7, #0] + if( SubgRf.lr_fhss.is_lr_fhss_on == true ) + { + //return LORAMAC_RADIO_STATUS_ERROR; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + uint32_t timeout = ( uint32_t )time * 1000; + 8009094: 883b ldrh r3, [r7, #0] + 8009096: f44f 727a mov.w r2, #1000 ; 0x3e8 + 800909a: fb02 f303 mul.w r3, r2, r3 + 800909e: 60fb str r3, [r7, #12] + uint8_t antswitchpow; + + SUBGRF_SetRfFrequency( freq ); + 80090a0: 6878 ldr r0, [r7, #4] + 80090a2: f001 fbe9 bl 800a878 + + antswitchpow = SUBGRF_SetRfTxPower( power ); + 80090a6: f997 3003 ldrsb.w r3, [r7, #3] + 80090aa: 4618 mov r0, r3 + 80090ac: f002 f854 bl 800b158 + 80090b0: 4603 mov r3, r0 + 80090b2: 72fb strb r3, [r7, #11] + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 80090b4: 210e movs r1, #14 + 80090b6: f640 101f movw r0, #2335 ; 0x91f + 80090ba: f001 ff31 bl 800af20 + + /* Set RF switch */ + SUBGRF_SetSwitch( antswitchpow, RFSWITCH_TX ); + 80090be: 7afb ldrb r3, [r7, #11] + 80090c0: 2101 movs r1, #1 + 80090c2: 4618 mov r0, r3 + 80090c4: f002 f820 bl 800b108 + + SUBGRF_SetTxContinuousWave( ); + 80090c8: f001 fa60 bl 800a58c + + TimerSetValue( &TxTimeoutTimer, timeout ); + 80090cc: 68f9 ldr r1, [r7, #12] + 80090ce: 4805 ldr r0, [pc, #20] ; (80090e4 ) + 80090d0: f003 fbe6 bl 800c8a0 + TimerStart( &TxTimeoutTimer ); + 80090d4: 4803 ldr r0, [pc, #12] ; (80090e4 ) + 80090d6: f003 fb05 bl 800c6e4 +} + 80090da: bf00 nop + 80090dc: 3710 adds r7, #16 + 80090de: 46bd mov sp, r7 + 80090e0: bd80 pop {r7, pc} + 80090e2: bf00 nop + 80090e4: 2000045c .word 0x2000045c + +080090e8 : + +static int16_t RadioRssi( RadioModems_t modem ) +{ + 80090e8: b580 push {r7, lr} + 80090ea: b082 sub sp, #8 + 80090ec: af00 add r7, sp, #0 + 80090ee: 4603 mov r3, r0 + 80090f0: 71fb strb r3, [r7, #7] + return SUBGRF_GetRssiInst( ); + 80090f2: f001 fe82 bl 800adfa + 80090f6: 4603 mov r3, r0 + 80090f8: b21b sxth r3, r3 +} + 80090fa: 4618 mov r0, r3 + 80090fc: 3708 adds r7, #8 + 80090fe: 46bd mov sp, r7 + 8009100: bd80 pop {r7, pc} + +08009102 : + +static void RadioWrite( uint16_t addr, uint8_t data ) +{ + 8009102: b580 push {r7, lr} + 8009104: b082 sub sp, #8 + 8009106: af00 add r7, sp, #0 + 8009108: 4603 mov r3, r0 + 800910a: 460a mov r2, r1 + 800910c: 80fb strh r3, [r7, #6] + 800910e: 4613 mov r3, r2 + 8009110: 717b strb r3, [r7, #5] + SUBGRF_WriteRegister( addr, data ); + 8009112: 797a ldrb r2, [r7, #5] + 8009114: 88fb ldrh r3, [r7, #6] + 8009116: 4611 mov r1, r2 + 8009118: 4618 mov r0, r3 + 800911a: f001 ff01 bl 800af20 +} + 800911e: bf00 nop + 8009120: 3708 adds r7, #8 + 8009122: 46bd mov sp, r7 + 8009124: bd80 pop {r7, pc} + +08009126 : + +static uint8_t RadioRead( uint16_t addr ) +{ + 8009126: b580 push {r7, lr} + 8009128: b082 sub sp, #8 + 800912a: af00 add r7, sp, #0 + 800912c: 4603 mov r3, r0 + 800912e: 80fb strh r3, [r7, #6] + return SUBGRF_ReadRegister( addr ); + 8009130: 88fb ldrh r3, [r7, #6] + 8009132: 4618 mov r0, r3 + 8009134: f001 ff08 bl 800af48 + 8009138: 4603 mov r3, r0 +} + 800913a: 4618 mov r0, r3 + 800913c: 3708 adds r7, #8 + 800913e: 46bd mov sp, r7 + 8009140: bd80 pop {r7, pc} + +08009142 : + +static void RadioWriteRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + 8009142: b580 push {r7, lr} + 8009144: b082 sub sp, #8 + 8009146: af00 add r7, sp, #0 + 8009148: 4603 mov r3, r0 + 800914a: 6039 str r1, [r7, #0] + 800914c: 80fb strh r3, [r7, #6] + 800914e: 4613 mov r3, r2 + 8009150: 717b strb r3, [r7, #5] + SUBGRF_WriteRegisters( addr, buffer, size ); + 8009152: 797b ldrb r3, [r7, #5] + 8009154: b29a uxth r2, r3 + 8009156: 88fb ldrh r3, [r7, #6] + 8009158: 6839 ldr r1, [r7, #0] + 800915a: 4618 mov r0, r3 + 800915c: f001 ff08 bl 800af70 +} + 8009160: bf00 nop + 8009162: 3708 adds r7, #8 + 8009164: 46bd mov sp, r7 + 8009166: bd80 pop {r7, pc} + +08009168 : + +static void RadioReadRegisters( uint16_t addr, uint8_t *buffer, uint8_t size ) +{ + 8009168: b580 push {r7, lr} + 800916a: b082 sub sp, #8 + 800916c: af00 add r7, sp, #0 + 800916e: 4603 mov r3, r0 + 8009170: 6039 str r1, [r7, #0] + 8009172: 80fb strh r3, [r7, #6] + 8009174: 4613 mov r3, r2 + 8009176: 717b strb r3, [r7, #5] + SUBGRF_ReadRegisters( addr, buffer, size ); + 8009178: 797b ldrb r3, [r7, #5] + 800917a: b29a uxth r2, r3 + 800917c: 88fb ldrh r3, [r7, #6] + 800917e: 6839 ldr r1, [r7, #0] + 8009180: 4618 mov r0, r3 + 8009182: f001 ff17 bl 800afb4 +} + 8009186: bf00 nop + 8009188: 3708 adds r7, #8 + 800918a: 46bd mov sp, r7 + 800918c: bd80 pop {r7, pc} + ... + +08009190 : + +static void RadioSetMaxPayloadLength( RadioModems_t modem, uint8_t max ) +{ + 8009190: b580 push {r7, lr} + 8009192: b082 sub sp, #8 + 8009194: af00 add r7, sp, #0 + 8009196: 4603 mov r3, r0 + 8009198: 460a mov r2, r1 + 800919a: 71fb strb r3, [r7, #7] + 800919c: 4613 mov r3, r2 + 800919e: 71bb strb r3, [r7, #6] + if( modem == MODEM_LORA ) + 80091a0: 79fb ldrb r3, [r7, #7] + 80091a2: 2b01 cmp r3, #1 + 80091a4: d10a bne.n 80091bc + { + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength = max; + 80091a6: 4a0e ldr r2, [pc, #56] ; (80091e0 ) + 80091a8: 79bb ldrb r3, [r7, #6] + 80091aa: 7013 strb r3, [r2, #0] + 80091ac: 4b0c ldr r3, [pc, #48] ; (80091e0 ) + 80091ae: 781a ldrb r2, [r3, #0] + 80091b0: 4b0c ldr r3, [pc, #48] ; (80091e4 ) + 80091b2: 77da strb r2, [r3, #31] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80091b4: 480c ldr r0, [pc, #48] ; (80091e8 ) + 80091b6: f001 fd6b bl 800ac90 + { + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + } + } +} + 80091ba: e00d b.n 80091d8 + if( SubgRf.PacketParams.Params.Gfsk.HeaderType == RADIO_PACKET_VARIABLE_LENGTH ) + 80091bc: 4b09 ldr r3, [pc, #36] ; (80091e4 ) + 80091be: 7d5b ldrb r3, [r3, #21] + 80091c0: 2b01 cmp r3, #1 + 80091c2: d109 bne.n 80091d8 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = MaxPayloadLength = max; + 80091c4: 4a06 ldr r2, [pc, #24] ; (80091e0 ) + 80091c6: 79bb ldrb r3, [r7, #6] + 80091c8: 7013 strb r3, [r2, #0] + 80091ca: 4b05 ldr r3, [pc, #20] ; (80091e0 ) + 80091cc: 781a ldrb r2, [r3, #0] + 80091ce: 4b05 ldr r3, [pc, #20] ; (80091e4 ) + 80091d0: 759a strb r2, [r3, #22] + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 80091d2: 4805 ldr r0, [pc, #20] ; (80091e8 ) + 80091d4: f001 fd5c bl 800ac90 +} + 80091d8: bf00 nop + 80091da: 3708 adds r7, #8 + 80091dc: 46bd mov sp, r7 + 80091de: bd80 pop {r7, pc} + 80091e0: 20000009 .word 0x20000009 + 80091e4: 20000400 .word 0x20000400 + 80091e8: 2000040e .word 0x2000040e + +080091ec : + +static void RadioSetPublicNetwork( bool enable ) +{ + 80091ec: b580 push {r7, lr} + 80091ee: b082 sub sp, #8 + 80091f0: af00 add r7, sp, #0 + 80091f2: 4603 mov r3, r0 + 80091f4: 71fb strb r3, [r7, #7] + SubgRf.PublicNetwork.Current = SubgRf.PublicNetwork.Previous = enable; + 80091f6: 4a13 ldr r2, [pc, #76] ; (8009244 ) + 80091f8: 79fb ldrb r3, [r7, #7] + 80091fa: 7313 strb r3, [r2, #12] + 80091fc: 4b11 ldr r3, [pc, #68] ; (8009244 ) + 80091fe: 7b1a ldrb r2, [r3, #12] + 8009200: 4b10 ldr r3, [pc, #64] ; (8009244 ) + 8009202: 735a strb r2, [r3, #13] + + RadioSetModem( MODEM_LORA ); + 8009204: 2001 movs r0, #1 + 8009206: f7ff f811 bl 800822c + if( enable == true ) + 800920a: 79fb ldrb r3, [r7, #7] + 800920c: 2b00 cmp r3, #0 + 800920e: d00a beq.n 8009226 + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PUBLIC_SYNCWORD >> 8 ) & 0xFF ); + 8009210: 2134 movs r1, #52 ; 0x34 + 8009212: f44f 60e8 mov.w r0, #1856 ; 0x740 + 8009216: f001 fe83 bl 800af20 + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PUBLIC_SYNCWORD & 0xFF ); + 800921a: 2144 movs r1, #68 ; 0x44 + 800921c: f240 7041 movw r0, #1857 ; 0x741 + 8009220: f001 fe7e bl 800af20 + { + // Change LoRa modem SyncWord + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + } +} + 8009224: e009 b.n 800923a + SUBGRF_WriteRegister( REG_LR_SYNCWORD, ( LORA_MAC_PRIVATE_SYNCWORD >> 8 ) & 0xFF ); + 8009226: 2114 movs r1, #20 + 8009228: f44f 60e8 mov.w r0, #1856 ; 0x740 + 800922c: f001 fe78 bl 800af20 + SUBGRF_WriteRegister( REG_LR_SYNCWORD + 1, LORA_MAC_PRIVATE_SYNCWORD & 0xFF ); + 8009230: 2124 movs r1, #36 ; 0x24 + 8009232: f240 7041 movw r0, #1857 ; 0x741 + 8009236: f001 fe73 bl 800af20 +} + 800923a: bf00 nop + 800923c: 3708 adds r7, #8 + 800923e: 46bd mov sp, r7 + 8009240: bd80 pop {r7, pc} + 8009242: bf00 nop + 8009244: 20000400 .word 0x20000400 + +08009248 : + +static uint32_t RadioGetWakeupTime( void ) +{ + 8009248: b580 push {r7, lr} + 800924a: af00 add r7, sp, #0 + return SUBGRF_GetRadioWakeUpTime() + RADIO_WAKEUP_TIME; + 800924c: f001 ffb8 bl 800b1c0 + 8009250: 4603 mov r3, r0 + 8009252: 3303 adds r3, #3 +} + 8009254: 4618 mov r0, r3 + 8009256: bd80 pop {r7, pc} + +08009258 : + +static void RadioOnTxTimeoutIrq( void *context ) +{ + 8009258: b580 push {r7, lr} + 800925a: b082 sub sp, #8 + 800925c: af00 add r7, sp, #0 + 800925e: 6078 str r0, [r7, #4] + RADIO_TX_TIMEOUT_PROCESS(); + 8009260: f000 f80e bl 8009280 +} + 8009264: bf00 nop + 8009266: 3708 adds r7, #8 + 8009268: 46bd mov sp, r7 + 800926a: bd80 pop {r7, pc} + +0800926c : + +static void RadioOnRxTimeoutIrq( void *context ) +{ + 800926c: b580 push {r7, lr} + 800926e: b082 sub sp, #8 + 8009270: af00 add r7, sp, #0 + 8009272: 6078 str r0, [r7, #4] + RADIO_RX_TIMEOUT_PROCESS(); + 8009274: f000 f818 bl 80092a8 +} + 8009278: bf00 nop + 800927a: 3708 adds r7, #8 + 800927c: 46bd mov sp, r7 + 800927e: bd80 pop {r7, pc} + +08009280 : + +static void RadioOnTxTimeoutProcess( void ) +{ + 8009280: b580 push {r7, lr} + 8009282: af00 add r7, sp, #0 + DBG_GPIO_RADIO_TX( RST ); + + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 8009284: 4b07 ldr r3, [pc, #28] ; (80092a4 ) + 8009286: 681b ldr r3, [r3, #0] + 8009288: 2b00 cmp r3, #0 + 800928a: d008 beq.n 800929e + 800928c: 4b05 ldr r3, [pc, #20] ; (80092a4 ) + 800928e: 681b ldr r3, [r3, #0] + 8009290: 685b ldr r3, [r3, #4] + 8009292: 2b00 cmp r3, #0 + 8009294: d003 beq.n 800929e + { + RadioEvents->TxTimeout( ); + 8009296: 4b03 ldr r3, [pc, #12] ; (80092a4 ) + 8009298: 681b ldr r3, [r3, #0] + 800929a: 685b ldr r3, [r3, #4] + 800929c: 4798 blx r3 + } +} + 800929e: bf00 nop + 80092a0: bd80 pop {r7, pc} + 80092a2: bf00 nop + 80092a4: 200003fc .word 0x200003fc + +080092a8 : + +static void RadioOnRxTimeoutProcess( void ) +{ + 80092a8: b580 push {r7, lr} + 80092aa: af00 add r7, sp, #0 + DBG_GPIO_RADIO_RX( RST ); + + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 80092ac: 4b07 ldr r3, [pc, #28] ; (80092cc ) + 80092ae: 681b ldr r3, [r3, #0] + 80092b0: 2b00 cmp r3, #0 + 80092b2: d008 beq.n 80092c6 + 80092b4: 4b05 ldr r3, [pc, #20] ; (80092cc ) + 80092b6: 681b ldr r3, [r3, #0] + 80092b8: 68db ldr r3, [r3, #12] + 80092ba: 2b00 cmp r3, #0 + 80092bc: d003 beq.n 80092c6 + { + RadioEvents->RxTimeout( ); + 80092be: 4b03 ldr r3, [pc, #12] ; (80092cc ) + 80092c0: 681b ldr r3, [r3, #0] + 80092c2: 68db ldr r3, [r3, #12] + 80092c4: 4798 blx r3 + } +} + 80092c6: bf00 nop + 80092c8: bd80 pop {r7, pc} + 80092ca: bf00 nop + 80092cc: 200003fc .word 0x200003fc + +080092d0 : + +static void RadioOnDioIrq( RadioIrqMasks_t radioIrq ) +{ + 80092d0: b580 push {r7, lr} + 80092d2: b082 sub sp, #8 + 80092d4: af00 add r7, sp, #0 + 80092d6: 4603 mov r3, r0 + 80092d8: 80fb strh r3, [r7, #6] + SubgRf.RadioIrq = radioIrq; + 80092da: 4a05 ldr r2, [pc, #20] ; (80092f0 ) + 80092dc: 88fb ldrh r3, [r7, #6] + 80092de: f8a2 3054 strh.w r3, [r2, #84] ; 0x54 + + RADIO_IRQ_PROCESS(); + 80092e2: f000 f807 bl 80092f4 +} + 80092e6: bf00 nop + 80092e8: 3708 adds r7, #8 + 80092ea: 46bd mov sp, r7 + 80092ec: bd80 pop {r7, pc} + 80092ee: bf00 nop + 80092f0: 20000400 .word 0x20000400 + +080092f4 : + +static void RadioIrqProcess( void ) +{ + 80092f4: b5b0 push {r4, r5, r7, lr} + 80092f6: b082 sub sp, #8 + 80092f8: af00 add r7, sp, #0 + uint8_t size = 0; + 80092fa: 2300 movs r3, #0 + 80092fc: 71fb strb r3, [r7, #7] + int32_t cfo = 0; + 80092fe: 2300 movs r3, #0 + 8009300: 603b str r3, [r7, #0] + + switch( SubgRf.RadioIrq ) + 8009302: 4ba8 ldr r3, [pc, #672] ; (80095a4 ) + 8009304: f8b3 3054 ldrh.w r3, [r3, #84] ; 0x54 + 8009308: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800930c: f000 810d beq.w 800952a + 8009310: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 8009314: f300 81e8 bgt.w 80096e8 + 8009318: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 800931c: f000 80f1 beq.w 8009502 + 8009320: f5b3 7f80 cmp.w r3, #256 ; 0x100 + 8009324: f300 81e0 bgt.w 80096e8 + 8009328: 2b80 cmp r3, #128 ; 0x80 + 800932a: f000 80d6 beq.w 80094da + 800932e: 2b80 cmp r3, #128 ; 0x80 + 8009330: f300 81da bgt.w 80096e8 + 8009334: 2b20 cmp r3, #32 + 8009336: dc49 bgt.n 80093cc + 8009338: 2b00 cmp r3, #0 + 800933a: f340 81d5 ble.w 80096e8 + 800933e: 3b01 subs r3, #1 + 8009340: 2b1f cmp r3, #31 + 8009342: f200 81d1 bhi.w 80096e8 + 8009346: a201 add r2, pc, #4 ; (adr r2, 800934c ) + 8009348: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800934c: 080093d5 .word 0x080093d5 + 8009350: 0800940f .word 0x0800940f + 8009354: 080096e9 .word 0x080096e9 + 8009358: 080095c5 .word 0x080095c5 + 800935c: 080096e9 .word 0x080096e9 + 8009360: 080096e9 .word 0x080096e9 + 8009364: 080096e9 .word 0x080096e9 + 8009368: 08009641 .word 0x08009641 + 800936c: 080096e9 .word 0x080096e9 + 8009370: 080096e9 .word 0x080096e9 + 8009374: 080096e9 .word 0x080096e9 + 8009378: 080096e9 .word 0x080096e9 + 800937c: 080096e9 .word 0x080096e9 + 8009380: 080096e9 .word 0x080096e9 + 8009384: 080096e9 .word 0x080096e9 + 8009388: 0800965d .word 0x0800965d + 800938c: 080096e9 .word 0x080096e9 + 8009390: 080096e9 .word 0x080096e9 + 8009394: 080096e9 .word 0x080096e9 + 8009398: 080096e9 .word 0x080096e9 + 800939c: 080096e9 .word 0x080096e9 + 80093a0: 080096e9 .word 0x080096e9 + 80093a4: 080096e9 .word 0x080096e9 + 80093a8: 080096e9 .word 0x080096e9 + 80093ac: 080096e9 .word 0x080096e9 + 80093b0: 080096e9 .word 0x080096e9 + 80093b4: 080096e9 .word 0x080096e9 + 80093b8: 080096e9 .word 0x080096e9 + 80093bc: 080096e9 .word 0x080096e9 + 80093c0: 080096e9 .word 0x080096e9 + 80093c4: 080096e9 .word 0x080096e9 + 80093c8: 0800966b .word 0x0800966b + 80093cc: 2b40 cmp r3, #64 ; 0x40 + 80093ce: f000 816d beq.w 80096ac + MW_LOG( TS_ON, VLEVEL_M, "HOP\r\n" ); + break; + } +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + default: + break; + 80093d2: e189 b.n 80096e8 + TimerStop( &TxTimeoutTimer ); + 80093d4: 4874 ldr r0, [pc, #464] ; (80095a8 ) + 80093d6: f003 f9f3 bl 800c7c0 + SUBGRF_SetStandby( STDBY_RC ); + 80093da: 2000 movs r0, #0 + 80093dc: f001 f81c bl 800a418 + if( RFW_Is_LongPacketModeEnabled() == 1 ) + 80093e0: f002 f892 bl 800b508 + 80093e4: 4603 mov r3, r0 + 80093e6: 2b01 cmp r3, #1 + 80093e8: d101 bne.n 80093ee + RFW_DeInit_TxLongPacket( ); + 80093ea: f002 f8b6 bl 800b55a + if( ( RadioEvents != NULL ) && ( RadioEvents->TxDone != NULL ) ) + 80093ee: 4b6f ldr r3, [pc, #444] ; (80095ac ) + 80093f0: 681b ldr r3, [r3, #0] + 80093f2: 2b00 cmp r3, #0 + 80093f4: f000 817a beq.w 80096ec + 80093f8: 4b6c ldr r3, [pc, #432] ; (80095ac ) + 80093fa: 681b ldr r3, [r3, #0] + 80093fc: 681b ldr r3, [r3, #0] + 80093fe: 2b00 cmp r3, #0 + 8009400: f000 8174 beq.w 80096ec + RadioEvents->TxDone( ); + 8009404: 4b69 ldr r3, [pc, #420] ; (80095ac ) + 8009406: 681b ldr r3, [r3, #0] + 8009408: 681b ldr r3, [r3, #0] + 800940a: 4798 blx r3 + break; + 800940c: e16e b.n 80096ec + TimerStop( &RxTimeoutTimer ); + 800940e: 4868 ldr r0, [pc, #416] ; (80095b0 ) + 8009410: f003 f9d6 bl 800c7c0 + if( SubgRf.RxContinuous == false ) + 8009414: 4b63 ldr r3, [pc, #396] ; (80095a4 ) + 8009416: 785b ldrb r3, [r3, #1] + 8009418: f083 0301 eor.w r3, r3, #1 + 800941c: b2db uxtb r3, r3 + 800941e: 2b00 cmp r3, #0 + 8009420: d014 beq.n 800944c + SUBGRF_SetStandby( STDBY_RC ); + 8009422: 2000 movs r0, #0 + 8009424: f000 fff8 bl 800a418 + SUBGRF_WriteRegister( SUBGHZ_RTCCTLR, 0x00 ); + 8009428: 2100 movs r1, #0 + 800942a: f640 1002 movw r0, #2306 ; 0x902 + 800942e: f001 fd77 bl 800af20 + SUBGRF_WriteRegister( SUBGHZ_EVENTMASKR, SUBGRF_ReadRegister( SUBGHZ_EVENTMASKR ) | ( 1 << 1 ) ); + 8009432: f640 1044 movw r0, #2372 ; 0x944 + 8009436: f001 fd87 bl 800af48 + 800943a: 4603 mov r3, r0 + 800943c: f043 0302 orr.w r3, r3, #2 + 8009440: b2db uxtb r3, r3 + 8009442: 4619 mov r1, r3 + 8009444: f640 1044 movw r0, #2372 ; 0x944 + 8009448: f001 fd6a bl 800af20 + SUBGRF_GetPayload( RadioBuffer, &size, 255 ); + 800944c: 1dfb adds r3, r7, #7 + 800944e: 22ff movs r2, #255 ; 0xff + 8009450: 4619 mov r1, r3 + 8009452: 4858 ldr r0, [pc, #352] ; (80095b4 ) + 8009454: f000 feb0 bl 800a1b8 + SUBGRF_GetPacketStatus( &( SubgRf.PacketStatus ) ); + 8009458: 4857 ldr r0, [pc, #348] ; (80095b8 ) + 800945a: f001 fd0f bl 800ae7c + if( ( RadioEvents != NULL ) && ( RadioEvents->RxDone != NULL ) ) + 800945e: 4b53 ldr r3, [pc, #332] ; (80095ac ) + 8009460: 681b ldr r3, [r3, #0] + 8009462: 2b00 cmp r3, #0 + 8009464: f000 8144 beq.w 80096f0 + 8009468: 4b50 ldr r3, [pc, #320] ; (80095ac ) + 800946a: 681b ldr r3, [r3, #0] + 800946c: 689b ldr r3, [r3, #8] + 800946e: 2b00 cmp r3, #0 + 8009470: f000 813e beq.w 80096f0 + switch( SubgRf.PacketStatus.packetType ) + 8009474: 4b4b ldr r3, [pc, #300] ; (80095a4 ) + 8009476: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 800947a: 2b01 cmp r3, #1 + 800947c: d10e bne.n 800949c + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.LoRa.RssiPkt, + 800947e: 4b4b ldr r3, [pc, #300] ; (80095ac ) + 8009480: 681b ldr r3, [r3, #0] + 8009482: 689c ldr r4, [r3, #8] + 8009484: 79fb ldrb r3, [r7, #7] + 8009486: b299 uxth r1, r3 + 8009488: 4b46 ldr r3, [pc, #280] ; (80095a4 ) + 800948a: f993 3030 ldrsb.w r3, [r3, #48] ; 0x30 + 800948e: b21a sxth r2, r3 + 8009490: 4b44 ldr r3, [pc, #272] ; (80095a4 ) + 8009492: f993 3031 ldrsb.w r3, [r3, #49] ; 0x31 + 8009496: 4847 ldr r0, [pc, #284] ; (80095b4 ) + 8009498: 47a0 blx r4 + break; + 800949a: e01d b.n 80094d8 + SUBGRF_GetCFO( SubgRf.ModulationParams.Params.Gfsk.BitRate, &cfo ); + 800949c: 4b41 ldr r3, [pc, #260] ; (80095a4 ) + 800949e: 6bdb ldr r3, [r3, #60] ; 0x3c + 80094a0: 463a mov r2, r7 + 80094a2: 4611 mov r1, r2 + 80094a4: 4618 mov r0, r3 + 80094a6: f001 ff7d bl 800b3a4 + RadioEvents->RxDone( RadioBuffer, size, SubgRf.PacketStatus.Params.Gfsk.RssiAvg, ( int8_t ) DIVR( cfo, 1000 ) ); + 80094aa: 4b40 ldr r3, [pc, #256] ; (80095ac ) + 80094ac: 681b ldr r3, [r3, #0] + 80094ae: 689c ldr r4, [r3, #8] + 80094b0: 79fb ldrb r3, [r7, #7] + 80094b2: b299 uxth r1, r3 + 80094b4: 4b3b ldr r3, [pc, #236] ; (80095a4 ) + 80094b6: f993 3029 ldrsb.w r3, [r3, #41] ; 0x29 + 80094ba: b218 sxth r0, r3 + 80094bc: 683b ldr r3, [r7, #0] + 80094be: f503 73fa add.w r3, r3, #500 ; 0x1f4 + 80094c2: 4a3e ldr r2, [pc, #248] ; (80095bc ) + 80094c4: fb82 5203 smull r5, r2, r2, r3 + 80094c8: 1192 asrs r2, r2, #6 + 80094ca: 17db asrs r3, r3, #31 + 80094cc: 1ad3 subs r3, r2, r3 + 80094ce: b25b sxtb r3, r3 + 80094d0: 4602 mov r2, r0 + 80094d2: 4838 ldr r0, [pc, #224] ; (80095b4 ) + 80094d4: 47a0 blx r4 + break; + 80094d6: bf00 nop + break; + 80094d8: e10a b.n 80096f0 + SUBGRF_SetStandby( STDBY_RC ); + 80094da: 2000 movs r0, #0 + 80094dc: f000 ff9c bl 800a418 + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + 80094e0: 4b32 ldr r3, [pc, #200] ; (80095ac ) + 80094e2: 681b ldr r3, [r3, #0] + 80094e4: 2b00 cmp r3, #0 + 80094e6: f000 8105 beq.w 80096f4 + 80094ea: 4b30 ldr r3, [pc, #192] ; (80095ac ) + 80094ec: 681b ldr r3, [r3, #0] + 80094ee: 699b ldr r3, [r3, #24] + 80094f0: 2b00 cmp r3, #0 + 80094f2: f000 80ff beq.w 80096f4 + RadioEvents->CadDone( false ); + 80094f6: 4b2d ldr r3, [pc, #180] ; (80095ac ) + 80094f8: 681b ldr r3, [r3, #0] + 80094fa: 699b ldr r3, [r3, #24] + 80094fc: 2000 movs r0, #0 + 80094fe: 4798 blx r3 + break; + 8009500: e0f8 b.n 80096f4 + SUBGRF_SetStandby( STDBY_RC ); + 8009502: 2000 movs r0, #0 + 8009504: f000 ff88 bl 800a418 + if( ( RadioEvents != NULL ) && ( RadioEvents->CadDone != NULL ) ) + 8009508: 4b28 ldr r3, [pc, #160] ; (80095ac ) + 800950a: 681b ldr r3, [r3, #0] + 800950c: 2b00 cmp r3, #0 + 800950e: f000 80f3 beq.w 80096f8 + 8009512: 4b26 ldr r3, [pc, #152] ; (80095ac ) + 8009514: 681b ldr r3, [r3, #0] + 8009516: 699b ldr r3, [r3, #24] + 8009518: 2b00 cmp r3, #0 + 800951a: f000 80ed beq.w 80096f8 + RadioEvents->CadDone( true ); + 800951e: 4b23 ldr r3, [pc, #140] ; (80095ac ) + 8009520: 681b ldr r3, [r3, #0] + 8009522: 699b ldr r3, [r3, #24] + 8009524: 2001 movs r0, #1 + 8009526: 4798 blx r3 + break; + 8009528: e0e6 b.n 80096f8 + MW_LOG( TS_ON, VLEVEL_M, "IRQ_RX_TX_TIMEOUT\r\n" ); + 800952a: 4b25 ldr r3, [pc, #148] ; (80095c0 ) + 800952c: 2201 movs r2, #1 + 800952e: 2100 movs r1, #0 + 8009530: 2002 movs r0, #2 + 8009532: f003 fabd bl 800cab0 + if( SUBGRF_GetOperatingMode( ) == MODE_TX ) + 8009536: f000 fe25 bl 800a184 + 800953a: 4603 mov r3, r0 + 800953c: 2b04 cmp r3, #4 + 800953e: d115 bne.n 800956c + TimerStop( &TxTimeoutTimer ); + 8009540: 4819 ldr r0, [pc, #100] ; (80095a8 ) + 8009542: f003 f93d bl 800c7c0 + SUBGRF_SetStandby( STDBY_RC ); + 8009546: 2000 movs r0, #0 + 8009548: f000 ff66 bl 800a418 + if( ( RadioEvents != NULL ) && ( RadioEvents->TxTimeout != NULL ) ) + 800954c: 4b17 ldr r3, [pc, #92] ; (80095ac ) + 800954e: 681b ldr r3, [r3, #0] + 8009550: 2b00 cmp r3, #0 + 8009552: f000 80d3 beq.w 80096fc + 8009556: 4b15 ldr r3, [pc, #84] ; (80095ac ) + 8009558: 681b ldr r3, [r3, #0] + 800955a: 685b ldr r3, [r3, #4] + 800955c: 2b00 cmp r3, #0 + 800955e: f000 80cd beq.w 80096fc + RadioEvents->TxTimeout( ); + 8009562: 4b12 ldr r3, [pc, #72] ; (80095ac ) + 8009564: 681b ldr r3, [r3, #0] + 8009566: 685b ldr r3, [r3, #4] + 8009568: 4798 blx r3 + break; + 800956a: e0c7 b.n 80096fc + else if( SUBGRF_GetOperatingMode( ) == MODE_RX ) + 800956c: f000 fe0a bl 800a184 + 8009570: 4603 mov r3, r0 + 8009572: 2b05 cmp r3, #5 + 8009574: f040 80c2 bne.w 80096fc + TimerStop( &RxTimeoutTimer ); + 8009578: 480d ldr r0, [pc, #52] ; (80095b0 ) + 800957a: f003 f921 bl 800c7c0 + SUBGRF_SetStandby( STDBY_RC ); + 800957e: 2000 movs r0, #0 + 8009580: f000 ff4a bl 800a418 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8009584: 4b09 ldr r3, [pc, #36] ; (80095ac ) + 8009586: 681b ldr r3, [r3, #0] + 8009588: 2b00 cmp r3, #0 + 800958a: f000 80b7 beq.w 80096fc + 800958e: 4b07 ldr r3, [pc, #28] ; (80095ac ) + 8009590: 681b ldr r3, [r3, #0] + 8009592: 68db ldr r3, [r3, #12] + 8009594: 2b00 cmp r3, #0 + 8009596: f000 80b1 beq.w 80096fc + RadioEvents->RxTimeout( ); + 800959a: 4b04 ldr r3, [pc, #16] ; (80095ac ) + 800959c: 681b ldr r3, [r3, #0] + 800959e: 68db ldr r3, [r3, #12] + 80095a0: 4798 blx r3 + break; + 80095a2: e0ab b.n 80096fc + 80095a4: 20000400 .word 0x20000400 + 80095a8: 2000045c .word 0x2000045c + 80095ac: 200003fc .word 0x200003fc + 80095b0: 20000474 .word 0x20000474 + 80095b4: 200002fc .word 0x200002fc + 80095b8: 20000424 .word 0x20000424 + 80095bc: 10624dd3 .word 0x10624dd3 + 80095c0: 0800e048 .word 0x0800e048 + MW_LOG( TS_ON, VLEVEL_M, "PRE OK\r\n" ); + 80095c4: 4b54 ldr r3, [pc, #336] ; (8009718 ) + 80095c6: 2201 movs r2, #1 + 80095c8: 2100 movs r1, #0 + 80095ca: 2002 movs r0, #2 + 80095cc: f003 fa70 bl 800cab0 + if( SubgRf.RxDcPreambleDetectTimeout != 0 ) + 80095d0: 4b52 ldr r3, [pc, #328] ; (800971c ) + 80095d2: 6d9b ldr r3, [r3, #88] ; 0x58 + 80095d4: 2b00 cmp r3, #0 + 80095d6: f000 8093 beq.w 8009700 + Radio.Write( SUBGHZ_RTCPRDR2, ( SubgRf.RxDcPreambleDetectTimeout >> 16 ) & 0xFF ); /*Update Radio RTC Period MSB*/ + 80095da: 4a51 ldr r2, [pc, #324] ; (8009720 ) + 80095dc: 4b4f ldr r3, [pc, #316] ; (800971c ) + 80095de: 6d9b ldr r3, [r3, #88] ; 0x58 + 80095e0: 0c1b lsrs r3, r3, #16 + 80095e2: b2db uxtb r3, r3 + 80095e4: 4619 mov r1, r3 + 80095e6: f640 1003 movw r0, #2307 ; 0x903 + 80095ea: 4790 blx r2 + Radio.Write( SUBGHZ_RTCPRDR1, ( SubgRf.RxDcPreambleDetectTimeout >> 8 ) & 0xFF ); /*Update Radio RTC Period MidByte*/ + 80095ec: 4a4c ldr r2, [pc, #304] ; (8009720 ) + 80095ee: 4b4b ldr r3, [pc, #300] ; (800971c ) + 80095f0: 6d9b ldr r3, [r3, #88] ; 0x58 + 80095f2: 0a1b lsrs r3, r3, #8 + 80095f4: b2db uxtb r3, r3 + 80095f6: 4619 mov r1, r3 + 80095f8: f640 1004 movw r0, #2308 ; 0x904 + 80095fc: 4790 blx r2 + Radio.Write( SUBGHZ_RTCPRDR0, ( SubgRf.RxDcPreambleDetectTimeout ) & 0xFF ); /*Update Radio RTC Period lsb*/ + 80095fe: 4a48 ldr r2, [pc, #288] ; (8009720 ) + 8009600: 4b46 ldr r3, [pc, #280] ; (800971c ) + 8009602: 6d9b ldr r3, [r3, #88] ; 0x58 + 8009604: b2db uxtb r3, r3 + 8009606: 4619 mov r1, r3 + 8009608: f640 1005 movw r0, #2309 ; 0x905 + 800960c: 4790 blx r2 + Radio.Write( SUBGHZ_RTCCTLR, Radio.Read( SUBGHZ_RTCCTLR ) | 0x1 ); /*restart Radio RTC*/ + 800960e: 4c44 ldr r4, [pc, #272] ; (8009720 ) + 8009610: 4b44 ldr r3, [pc, #272] ; (8009724 ) + 8009612: f640 1002 movw r0, #2306 ; 0x902 + 8009616: 4798 blx r3 + 8009618: 4603 mov r3, r0 + 800961a: f043 0301 orr.w r3, r3, #1 + 800961e: b2db uxtb r3, r3 + 8009620: 4619 mov r1, r3 + 8009622: f640 1002 movw r0, #2306 ; 0x902 + 8009626: 47a0 blx r4 + SubgRf.RxDcPreambleDetectTimeout = 0; + 8009628: 4b3c ldr r3, [pc, #240] ; (800971c ) + 800962a: 2200 movs r2, #0 + 800962c: 659a str r2, [r3, #88] ; 0x58 + SUBGRF_SetDioIrqParams( IRQ_RX_DONE | IRQ_RX_TX_TIMEOUT | IRQ_CRC_ERROR | IRQ_HEADER_ERROR | IRQ_RX_DBG, + 800962e: 2300 movs r3, #0 + 8009630: 2200 movs r2, #0 + 8009632: f240 2162 movw r1, #610 ; 0x262 + 8009636: f240 2062 movw r0, #610 ; 0x262 + 800963a: f001 f8c1 bl 800a7c0 + break; + 800963e: e05f b.n 8009700 + MW_LOG( TS_ON, VLEVEL_M, "SYNC OK\r\n" ); + 8009640: 4b39 ldr r3, [pc, #228] ; (8009728 ) + 8009642: 2201 movs r2, #1 + 8009644: 2100 movs r1, #0 + 8009646: 2002 movs r0, #2 + 8009648: f003 fa32 bl 800cab0 + if( 1UL == RFW_Is_Init( ) ) + 800964c: f001 ff55 bl 800b4fa + 8009650: 4603 mov r3, r0 + 8009652: 2b01 cmp r3, #1 + 8009654: d156 bne.n 8009704 + RFW_ReceivePayload( ); + 8009656: f001 ff86 bl 800b566 + break; + 800965a: e053 b.n 8009704 + MW_LOG( TS_ON, VLEVEL_M, "HDR OK\r\n" ); + 800965c: 4b33 ldr r3, [pc, #204] ; (800972c ) + 800965e: 2201 movs r2, #1 + 8009660: 2100 movs r1, #0 + 8009662: 2002 movs r0, #2 + 8009664: f003 fa24 bl 800cab0 + break; + 8009668: e051 b.n 800970e + TimerStop( &RxTimeoutTimer ); + 800966a: 4831 ldr r0, [pc, #196] ; (8009730 ) + 800966c: f003 f8a8 bl 800c7c0 + if( SubgRf.RxContinuous == false ) + 8009670: 4b2a ldr r3, [pc, #168] ; (800971c ) + 8009672: 785b ldrb r3, [r3, #1] + 8009674: f083 0301 eor.w r3, r3, #1 + 8009678: b2db uxtb r3, r3 + 800967a: 2b00 cmp r3, #0 + 800967c: d002 beq.n 8009684 + SUBGRF_SetStandby( STDBY_RC ); + 800967e: 2000 movs r0, #0 + 8009680: f000 feca bl 800a418 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxTimeout != NULL ) ) + 8009684: 4b2b ldr r3, [pc, #172] ; (8009734 ) + 8009686: 681b ldr r3, [r3, #0] + 8009688: 2b00 cmp r3, #0 + 800968a: d03d beq.n 8009708 + 800968c: 4b29 ldr r3, [pc, #164] ; (8009734 ) + 800968e: 681b ldr r3, [r3, #0] + 8009690: 68db ldr r3, [r3, #12] + 8009692: 2b00 cmp r3, #0 + 8009694: d038 beq.n 8009708 + RadioEvents->RxTimeout( ); + 8009696: 4b27 ldr r3, [pc, #156] ; (8009734 ) + 8009698: 681b ldr r3, [r3, #0] + 800969a: 68db ldr r3, [r3, #12] + 800969c: 4798 blx r3 + MW_LOG( TS_ON, VLEVEL_M, "HDR KO\r\n" ); + 800969e: 4b26 ldr r3, [pc, #152] ; (8009738 ) + 80096a0: 2201 movs r2, #1 + 80096a2: 2100 movs r1, #0 + 80096a4: 2002 movs r0, #2 + 80096a6: f003 fa03 bl 800cab0 + break; + 80096aa: e02d b.n 8009708 + MW_LOG( TS_ON, VLEVEL_M, "IRQ_CRC_ERROR\r\n" ); + 80096ac: 4b23 ldr r3, [pc, #140] ; (800973c ) + 80096ae: 2201 movs r2, #1 + 80096b0: 2100 movs r1, #0 + 80096b2: 2002 movs r0, #2 + 80096b4: f003 f9fc bl 800cab0 + if( SubgRf.RxContinuous == false ) + 80096b8: 4b18 ldr r3, [pc, #96] ; (800971c ) + 80096ba: 785b ldrb r3, [r3, #1] + 80096bc: f083 0301 eor.w r3, r3, #1 + 80096c0: b2db uxtb r3, r3 + 80096c2: 2b00 cmp r3, #0 + 80096c4: d002 beq.n 80096cc + SUBGRF_SetStandby( STDBY_RC ); + 80096c6: 2000 movs r0, #0 + 80096c8: f000 fea6 bl 800a418 + if( ( RadioEvents != NULL ) && ( RadioEvents->RxError ) ) + 80096cc: 4b19 ldr r3, [pc, #100] ; (8009734 ) + 80096ce: 681b ldr r3, [r3, #0] + 80096d0: 2b00 cmp r3, #0 + 80096d2: d01b beq.n 800970c + 80096d4: 4b17 ldr r3, [pc, #92] ; (8009734 ) + 80096d6: 681b ldr r3, [r3, #0] + 80096d8: 691b ldr r3, [r3, #16] + 80096da: 2b00 cmp r3, #0 + 80096dc: d016 beq.n 800970c + RadioEvents->RxError( ); + 80096de: 4b15 ldr r3, [pc, #84] ; (8009734 ) + 80096e0: 681b ldr r3, [r3, #0] + 80096e2: 691b ldr r3, [r3, #16] + 80096e4: 4798 blx r3 + break; + 80096e6: e011 b.n 800970c + break; + 80096e8: bf00 nop + 80096ea: e010 b.n 800970e + break; + 80096ec: bf00 nop + 80096ee: e00e b.n 800970e + break; + 80096f0: bf00 nop + 80096f2: e00c b.n 800970e + break; + 80096f4: bf00 nop + 80096f6: e00a b.n 800970e + break; + 80096f8: bf00 nop + 80096fa: e008 b.n 800970e + break; + 80096fc: bf00 nop + 80096fe: e006 b.n 800970e + break; + 8009700: bf00 nop + 8009702: e004 b.n 800970e + break; + 8009704: bf00 nop + 8009706: e002 b.n 800970e + break; + 8009708: bf00 nop + 800970a: e000 b.n 800970e + break; + 800970c: bf00 nop + } +} + 800970e: bf00 nop + 8009710: 3708 adds r7, #8 + 8009712: 46bd mov sp, r7 + 8009714: bdb0 pop {r4, r5, r7, pc} + 8009716: bf00 nop + 8009718: 0800e05c .word 0x0800e05c + 800971c: 20000400 .word 0x20000400 + 8009720: 08009103 .word 0x08009103 + 8009724: 08009127 .word 0x08009127 + 8009728: 0800e068 .word 0x0800e068 + 800972c: 0800e074 .word 0x0800e074 + 8009730: 20000474 .word 0x20000474 + 8009734: 200003fc .word 0x200003fc + 8009738: 0800e080 .word 0x0800e080 + 800973c: 0800e08c .word 0x0800e08c + +08009740 : + +static void RadioTxPrbs( void ) +{ + 8009740: b580 push {r7, lr} + 8009742: af00 add r7, sp, #0 + SUBGRF_SetSwitch( SubgRf.AntSwitchPaSelect, RFSWITCH_TX ); + 8009744: 4b09 ldr r3, [pc, #36] ; (800976c ) + 8009746: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 800974a: 2101 movs r1, #1 + 800974c: 4618 mov r0, r3 + 800974e: f001 fcdb bl 800b108 + Radio.Write( SUBGHZ_GPKTCTL1AR, 0x2d ); // sel mode prbs9 instead of preamble + 8009752: 4b07 ldr r3, [pc, #28] ; (8009770 ) + 8009754: 212d movs r1, #45 ; 0x2d + 8009756: f44f 60d7 mov.w r0, #1720 ; 0x6b8 + 800975a: 4798 blx r3 + SUBGRF_SetTxInfinitePreamble( ); + 800975c: f000 ff1f bl 800a59e + SUBGRF_SetTx( 0x0fffff ); + 8009760: 4804 ldr r0, [pc, #16] ; (8009774 ) + 8009762: f000 fe75 bl 800a450 +} + 8009766: bf00 nop + 8009768: bd80 pop {r7, pc} + 800976a: bf00 nop + 800976c: 20000400 .word 0x20000400 + 8009770: 08009103 .word 0x08009103 + 8009774: 000fffff .word 0x000fffff + +08009778 : + +static void RadioTxCw( int8_t power ) +{ + 8009778: b580 push {r7, lr} + 800977a: b084 sub sp, #16 + 800977c: af00 add r7, sp, #0 + 800977e: 4603 mov r3, r0 + 8009780: 71fb strb r3, [r7, #7] + uint8_t paselect = SUBGRF_SetRfTxPower( power ); + 8009782: f997 3007 ldrsb.w r3, [r7, #7] + 8009786: 4618 mov r0, r3 + 8009788: f001 fce6 bl 800b158 + 800978c: 4603 mov r3, r0 + 800978e: 73fb strb r3, [r7, #15] + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 8009790: 210e movs r1, #14 + 8009792: f640 101f movw r0, #2335 ; 0x91f + 8009796: f001 fbc3 bl 800af20 + SUBGRF_SetSwitch( paselect, RFSWITCH_TX ); + 800979a: 7bfb ldrb r3, [r7, #15] + 800979c: 2101 movs r1, #1 + 800979e: 4618 mov r0, r3 + 80097a0: f001 fcb2 bl 800b108 + SUBGRF_SetTxContinuousWave( ); + 80097a4: f000 fef2 bl 800a58c +} + 80097a8: bf00 nop + 80097aa: 3710 adds r7, #16 + 80097ac: 46bd mov sp, r7 + 80097ae: bd80 pop {r7, pc} + +080097b0 : + +#if (RADIO_SIGFOX_ENABLE == 1) +static void payload_integration( uint8_t *outBuffer, uint8_t *inBuffer, uint8_t size ) +{ + 80097b0: b480 push {r7} + 80097b2: b089 sub sp, #36 ; 0x24 + 80097b4: af00 add r7, sp, #0 + 80097b6: 60f8 str r0, [r7, #12] + 80097b8: 60b9 str r1, [r7, #8] + 80097ba: 4613 mov r3, r2 + 80097bc: 71fb strb r3, [r7, #7] + uint8_t prevInt = 0; + 80097be: 2300 movs r3, #0 + 80097c0: 77fb strb r3, [r7, #31] + uint8_t currBit; + uint8_t index_bit; + uint8_t index_byte; + uint8_t index_bit_out; + uint8_t index_byte_out; + int32_t i = 0; + 80097c2: 2300 movs r3, #0 + 80097c4: 61bb str r3, [r7, #24] + + for( i = 0; i < size; i++ ) + 80097c6: 2300 movs r3, #0 + 80097c8: 61bb str r3, [r7, #24] + 80097ca: e011 b.n 80097f0 + { + /* reverse all inputs */ + inBuffer[i] = ~inBuffer[i]; + 80097cc: 69bb ldr r3, [r7, #24] + 80097ce: 68ba ldr r2, [r7, #8] + 80097d0: 4413 add r3, r2 + 80097d2: 781a ldrb r2, [r3, #0] + 80097d4: 69bb ldr r3, [r7, #24] + 80097d6: 68b9 ldr r1, [r7, #8] + 80097d8: 440b add r3, r1 + 80097da: 43d2 mvns r2, r2 + 80097dc: b2d2 uxtb r2, r2 + 80097de: 701a strb r2, [r3, #0] + /* init outBuffer */ + outBuffer[i] = 0; + 80097e0: 69bb ldr r3, [r7, #24] + 80097e2: 68fa ldr r2, [r7, #12] + 80097e4: 4413 add r3, r2 + 80097e6: 2200 movs r2, #0 + 80097e8: 701a strb r2, [r3, #0] + for( i = 0; i < size; i++ ) + 80097ea: 69bb ldr r3, [r7, #24] + 80097ec: 3301 adds r3, #1 + 80097ee: 61bb str r3, [r7, #24] + 80097f0: 79fb ldrb r3, [r7, #7] + 80097f2: 69ba ldr r2, [r7, #24] + 80097f4: 429a cmp r2, r3 + 80097f6: dbe9 blt.n 80097cc + } + + for( i = 0; i < ( size * 8 ); i++ ) + 80097f8: 2300 movs r3, #0 + 80097fa: 61bb str r3, [r7, #24] + 80097fc: e049 b.n 8009892 + { + /* index to take bit in inBuffer */ + index_bit = 7 - ( i % 8 ); + 80097fe: 69bb ldr r3, [r7, #24] + 8009800: 425a negs r2, r3 + 8009802: f003 0307 and.w r3, r3, #7 + 8009806: f002 0207 and.w r2, r2, #7 + 800980a: bf58 it pl + 800980c: 4253 negpl r3, r2 + 800980e: b2db uxtb r3, r3 + 8009810: f1c3 0307 rsb r3, r3, #7 + 8009814: 75fb strb r3, [r7, #23] + index_byte = i / 8; + 8009816: 69bb ldr r3, [r7, #24] + 8009818: 2b00 cmp r3, #0 + 800981a: da00 bge.n 800981e + 800981c: 3307 adds r3, #7 + 800981e: 10db asrs r3, r3, #3 + 8009820: 75bb strb r3, [r7, #22] + /* index to place bit in outBuffer is shifted 1 bit right */ + index_bit_out = 7 - ( ( i + 1 ) % 8 ); + 8009822: 69bb ldr r3, [r7, #24] + 8009824: 3301 adds r3, #1 + 8009826: 425a negs r2, r3 + 8009828: f003 0307 and.w r3, r3, #7 + 800982c: f002 0207 and.w r2, r2, #7 + 8009830: bf58 it pl + 8009832: 4253 negpl r3, r2 + 8009834: b2db uxtb r3, r3 + 8009836: f1c3 0307 rsb r3, r3, #7 + 800983a: 757b strb r3, [r7, #21] + index_byte_out = ( i + 1 ) / 8; + 800983c: 69bb ldr r3, [r7, #24] + 800983e: 3301 adds r3, #1 + 8009840: 2b00 cmp r3, #0 + 8009842: da00 bge.n 8009846 + 8009844: 3307 adds r3, #7 + 8009846: 10db asrs r3, r3, #3 + 8009848: 753b strb r3, [r7, #20] + /* extract current bit from input */ + currBit = ( inBuffer[index_byte] >> index_bit ) & 0x01; + 800984a: 7dbb ldrb r3, [r7, #22] + 800984c: 68ba ldr r2, [r7, #8] + 800984e: 4413 add r3, r2 + 8009850: 781b ldrb r3, [r3, #0] + 8009852: 461a mov r2, r3 + 8009854: 7dfb ldrb r3, [r7, #23] + 8009856: fa42 f303 asr.w r3, r2, r3 + 800985a: b2db uxtb r3, r3 + 800985c: f003 0301 and.w r3, r3, #1 + 8009860: 74fb strb r3, [r7, #19] + /* integration */ + prevInt ^= currBit; + 8009862: 7ffa ldrb r2, [r7, #31] + 8009864: 7cfb ldrb r3, [r7, #19] + 8009866: 4053 eors r3, r2 + 8009868: 77fb strb r3, [r7, #31] + /* write result integration in output */ + outBuffer[index_byte_out] |= ( prevInt << index_bit_out ); + 800986a: 7d3b ldrb r3, [r7, #20] + 800986c: 68fa ldr r2, [r7, #12] + 800986e: 4413 add r3, r2 + 8009870: 781b ldrb r3, [r3, #0] + 8009872: b25a sxtb r2, r3 + 8009874: 7ff9 ldrb r1, [r7, #31] + 8009876: 7d7b ldrb r3, [r7, #21] + 8009878: fa01 f303 lsl.w r3, r1, r3 + 800987c: b25b sxtb r3, r3 + 800987e: 4313 orrs r3, r2 + 8009880: b259 sxtb r1, r3 + 8009882: 7d3b ldrb r3, [r7, #20] + 8009884: 68fa ldr r2, [r7, #12] + 8009886: 4413 add r3, r2 + 8009888: b2ca uxtb r2, r1 + 800988a: 701a strb r2, [r3, #0] + for( i = 0; i < ( size * 8 ); i++ ) + 800988c: 69bb ldr r3, [r7, #24] + 800988e: 3301 adds r3, #1 + 8009890: 61bb str r3, [r7, #24] + 8009892: 79fb ldrb r3, [r7, #7] + 8009894: 00db lsls r3, r3, #3 + 8009896: 69ba ldr r2, [r7, #24] + 8009898: 429a cmp r2, r3 + 800989a: dbb0 blt.n 80097fe + } + + outBuffer[size] = ( prevInt << 7 ) | ( prevInt << 6 ) | ( ( ( !prevInt ) & 0x01 ) << 5 ) ; + 800989c: 7ffb ldrb r3, [r7, #31] + 800989e: 01db lsls r3, r3, #7 + 80098a0: b25a sxtb r2, r3 + 80098a2: 7ffb ldrb r3, [r7, #31] + 80098a4: 019b lsls r3, r3, #6 + 80098a6: b25b sxtb r3, r3 + 80098a8: 4313 orrs r3, r2 + 80098aa: b25b sxtb r3, r3 + 80098ac: 7ffa ldrb r2, [r7, #31] + 80098ae: 2a00 cmp r2, #0 + 80098b0: d101 bne.n 80098b6 + 80098b2: 2220 movs r2, #32 + 80098b4: e000 b.n 80098b8 + 80098b6: 2200 movs r2, #0 + 80098b8: 4313 orrs r3, r2 + 80098ba: b259 sxtb r1, r3 + 80098bc: 79fb ldrb r3, [r7, #7] + 80098be: 68fa ldr r2, [r7, #12] + 80098c0: 4413 add r3, r2 + 80098c2: b2ca uxtb r2, r1 + 80098c4: 701a strb r2, [r3, #0] +} + 80098c6: bf00 nop + 80098c8: 3724 adds r7, #36 ; 0x24 + 80098ca: 46bd mov sp, r7 + 80098cc: bc80 pop {r7} + 80098ce: 4770 bx lr + +080098d0 : +#endif /*RADIO_SIGFOX_ENABLE == 1*/ + +static int32_t RadioSetRxGenericConfig( GenericModems_t modem, RxConfigGeneric_t *config, uint32_t rxContinuous, + uint32_t symbTimeout ) +{ + 80098d0: b580 push {r7, lr} + 80098d2: b08c sub sp, #48 ; 0x30 + 80098d4: af00 add r7, sp, #0 + 80098d6: 60b9 str r1, [r7, #8] + 80098d8: 607a str r2, [r7, #4] + 80098da: 603b str r3, [r7, #0] + 80098dc: 4603 mov r3, r0 + 80098de: 73fb strb r3, [r7, #15] +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + int32_t status = 0; + 80098e0: 2300 movs r3, #0 + 80098e2: 62bb str r3, [r7, #40] ; 0x28 + uint8_t syncword[8] = {0}; + 80098e4: 2300 movs r3, #0 + 80098e6: 623b str r3, [r7, #32] + 80098e8: 2300 movs r3, #0 + 80098ea: 627b str r3, [r7, #36] ; 0x24 + uint8_t MaxPayloadLength; + + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + 80098ec: f001 fdff bl 800b4ee + + if( rxContinuous != 0 ) + 80098f0: 687b ldr r3, [r7, #4] + 80098f2: 2b00 cmp r3, #0 + 80098f4: d001 beq.n 80098fa + { + symbTimeout = 0; + 80098f6: 2300 movs r3, #0 + 80098f8: 603b str r3, [r7, #0] + } + SubgRf.RxContinuous = ( rxContinuous == 0 ) ? false : true; + 80098fa: 687b ldr r3, [r7, #4] + 80098fc: 2b00 cmp r3, #0 + 80098fe: bf14 ite ne + 8009900: 2301 movne r3, #1 + 8009902: 2300 moveq r3, #0 + 8009904: b2da uxtb r2, r3 + 8009906: 4ba3 ldr r3, [pc, #652] ; (8009b94 ) + 8009908: 705a strb r2, [r3, #1] + + switch( modem ) + 800990a: 7bfb ldrb r3, [r7, #15] + 800990c: 2b00 cmp r3, #0 + 800990e: d003 beq.n 8009918 + 8009910: 2b01 cmp r3, #1 + 8009912: f000 80dc beq.w 8009ace + + // Timeout Max, Timeout handled directly in SetRx function + SubgRf.RxTimeout = 0xFFFF; + break; + default: + break; + 8009916: e194 b.n 8009c42 + if( ( config->fsk.BitRate == 0 ) || ( config->fsk.PreambleLen == 0 ) ) + 8009918: 68bb ldr r3, [r7, #8] + 800991a: 689b ldr r3, [r3, #8] + 800991c: 2b00 cmp r3, #0 + 800991e: d003 beq.n 8009928 + 8009920: 68bb ldr r3, [r7, #8] + 8009922: 68db ldr r3, [r3, #12] + 8009924: 2b00 cmp r3, #0 + 8009926: d102 bne.n 800992e + return -1; + 8009928: f04f 33ff mov.w r3, #4294967295 + 800992c: e18a b.n 8009c44 + if( config->fsk.SyncWordLength > 8 ) + 800992e: 68bb ldr r3, [r7, #8] + 8009930: 7f9b ldrb r3, [r3, #30] + 8009932: 2b08 cmp r3, #8 + 8009934: d902 bls.n 800993c + return -1; + 8009936: f04f 33ff mov.w r3, #4294967295 + 800993a: e183 b.n 8009c44 + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + 800993c: 68bb ldr r3, [r7, #8] + 800993e: 6919 ldr r1, [r3, #16] + 8009940: 68bb ldr r3, [r7, #8] + 8009942: 7f9b ldrb r3, [r3, #30] + 8009944: b29a uxth r2, r3 + 8009946: f107 0320 add.w r3, r7, #32 + 800994a: 4618 mov r0, r3 + 800994c: f002 fa30 bl 800bdb0 + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->fsk.StopTimerOnPreambleDetect == 0 ) ? false : true ); + 8009950: 68bb ldr r3, [r7, #8] + 8009952: 681b ldr r3, [r3, #0] + 8009954: 2b00 cmp r3, #0 + 8009956: bf14 ite ne + 8009958: 2301 movne r3, #1 + 800995a: 2300 moveq r3, #0 + 800995c: b2db uxtb r3, r3 + 800995e: 4618 mov r0, r3 + 8009960: f000 fe26 bl 800a5b0 + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8009964: 4b8b ldr r3, [pc, #556] ; (8009b94 ) + 8009966: 2200 movs r2, #0 + 8009968: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + 800996c: 68bb ldr r3, [r7, #8] + 800996e: 689b ldr r3, [r3, #8] + 8009970: 4a88 ldr r2, [pc, #544] ; (8009b94 ) + 8009972: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + 8009974: 68bb ldr r3, [r7, #8] + 8009976: f893 2020 ldrb.w r2, [r3, #32] + 800997a: 4b86 ldr r3, [pc, #536] ; (8009b94 ) + 800997c: f883 2044 strb.w r2, [r3, #68] ; 0x44 + SubgRf.ModulationParams.Params.Gfsk.Bandwidth = SUBGRF_GetFskBandwidthRegValue( config->fsk.Bandwidth ); + 8009980: 68bb ldr r3, [r7, #8] + 8009982: 685b ldr r3, [r3, #4] + 8009984: 4618 mov r0, r3 + 8009986: f001 fce5 bl 800b354 + 800998a: 4603 mov r3, r0 + 800998c: 461a mov r2, r3 + 800998e: 4b81 ldr r3, [pc, #516] ; (8009b94 ) + 8009990: f883 2045 strb.w r2, [r3, #69] ; 0x45 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8009994: 4b7f ldr r3, [pc, #508] ; (8009b94 ) + 8009996: 2200 movs r2, #0 + 8009998: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3 ; // convert byte into bit + 800999a: 68bb ldr r3, [r7, #8] + 800999c: 68db ldr r3, [r3, #12] + 800999e: b29b uxth r3, r3 + 80099a0: 00db lsls r3, r3, #3 + 80099a2: b29a uxth r2, r3 + 80099a4: 4b7b ldr r3, [pc, #492] ; (8009b94 ) + 80099a6: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = ( RadioPreambleDetection_t ) config->fsk.PreambleMinDetect; + 80099a8: 68bb ldr r3, [r7, #8] + 80099aa: 7fda ldrb r2, [r3, #31] + 80099ac: 4b79 ldr r3, [pc, #484] ; (8009b94 ) + 80099ae: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + 80099b0: 68bb ldr r3, [r7, #8] + 80099b2: 7f9b ldrb r3, [r3, #30] + 80099b4: 00db lsls r3, r3, #3 + 80099b6: b2da uxtb r2, r3 + 80099b8: 4b76 ldr r3, [pc, #472] ; (8009b94 ) + 80099ba: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = ( RadioAddressComp_t ) config->fsk.AddrComp; + 80099bc: 68bb ldr r3, [r7, #8] + 80099be: f893 2021 ldrb.w r2, [r3, #33] ; 0x21 + 80099c2: 4b74 ldr r3, [pc, #464] ; (8009b94 ) + 80099c4: 751a strb r2, [r3, #20] + if( config->fsk.LengthMode == RADIO_FSK_PACKET_FIXED_LENGTH ) + 80099c6: 68bb ldr r3, [r7, #8] + 80099c8: f893 3022 ldrb.w r3, [r3, #34] ; 0x22 + 80099cc: 2b00 cmp r3, #0 + 80099ce: d105 bne.n 80099dc + SubgRf.PacketParams.Params.Gfsk.PayloadLength = config->fsk.MaxPayloadLength; + 80099d0: 68bb ldr r3, [r7, #8] + 80099d2: 695b ldr r3, [r3, #20] + 80099d4: b2da uxtb r2, r3 + 80099d6: 4b6f ldr r3, [pc, #444] ; (8009b94 ) + 80099d8: 759a strb r2, [r3, #22] + 80099da: e00b b.n 80099f4 + else if( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) + 80099dc: 68bb ldr r3, [r7, #8] + 80099de: f893 3022 ldrb.w r3, [r3, #34] ; 0x22 + 80099e2: 2b02 cmp r3, #2 + 80099e4: d103 bne.n 80099ee + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + 80099e6: 4b6b ldr r3, [pc, #428] ; (8009b94 ) + 80099e8: 22ff movs r2, #255 ; 0xff + 80099ea: 759a strb r2, [r3, #22] + 80099ec: e002 b.n 80099f4 + SubgRf.PacketParams.Params.Gfsk.PayloadLength = 0xFF; + 80099ee: 4b69 ldr r3, [pc, #420] ; (8009b94 ) + 80099f0: 22ff movs r2, #255 ; 0xff + 80099f2: 759a strb r2, [r3, #22] + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 80099f4: 68bb ldr r3, [r7, #8] + 80099f6: f893 3024 ldrb.w r3, [r3, #36] ; 0x24 + 80099fa: 2b02 cmp r3, #2 + 80099fc: d004 beq.n 8009a08 + || ( config->fsk.LengthMode == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 80099fe: 68bb ldr r3, [r7, #8] + 8009a00: f893 3022 ldrb.w r3, [r3, #34] ; 0x22 + 8009a04: 2b02 cmp r3, #2 + 8009a06: d12d bne.n 8009a64 + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 8009a08: 68bb ldr r3, [r7, #8] + 8009a0a: f893 3023 ldrb.w r3, [r3, #35] ; 0x23 + 8009a0e: 2bf1 cmp r3, #241 ; 0xf1 + 8009a10: d00c beq.n 8009a2c + 8009a12: 68bb ldr r3, [r7, #8] + 8009a14: f893 3023 ldrb.w r3, [r3, #35] ; 0x23 + 8009a18: 2bf2 cmp r3, #242 ; 0xf2 + 8009a1a: d007 beq.n 8009a2c + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 8009a1c: 68bb ldr r3, [r7, #8] + 8009a1e: f893 3023 ldrb.w r3, [r3, #35] ; 0x23 + 8009a22: 2b01 cmp r3, #1 + 8009a24: d002 beq.n 8009a2c + return -1; + 8009a26: f04f 33ff mov.w r3, #4294967295 + 8009a2a: e10b b.n 8009c44 + ConfigGeneric.rtx = CONFIG_RX; + 8009a2c: 2300 movs r3, #0 + 8009a2e: 773b strb r3, [r7, #28] + ConfigGeneric.RxConfig = config; + 8009a30: 68bb ldr r3, [r7, #8] + 8009a32: 61bb str r3, [r7, #24] + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &RxTimeoutTimer ) ) + 8009a34: 4b58 ldr r3, [pc, #352] ; (8009b98 ) + 8009a36: 6819 ldr r1, [r3, #0] + 8009a38: f107 0314 add.w r3, r7, #20 + 8009a3c: 4a57 ldr r2, [pc, #348] ; (8009b9c ) + 8009a3e: 4618 mov r0, r3 + 8009a40: f001 fd48 bl 800b4d4 + 8009a44: 4603 mov r3, r0 + 8009a46: 2b00 cmp r3, #0 + 8009a48: d002 beq.n 8009a50 + return -1; + 8009a4a: f04f 33ff mov.w r3, #4294967295 + 8009a4e: e0f9 b.n 8009c44 + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 8009a50: 4b50 ldr r3, [pc, #320] ; (8009b94 ) + 8009a52: 2200 movs r2, #0 + 8009a54: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 8009a56: 4b4f ldr r3, [pc, #316] ; (8009b94 ) + 8009a58: 2201 movs r2, #1 + 8009a5a: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 8009a5c: 4b4d ldr r3, [pc, #308] ; (8009b94 ) + 8009a5e: 2200 movs r2, #0 + 8009a60: 755a strb r2, [r3, #21] + { + 8009a62: e00e b.n 8009a82 + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + 8009a64: 68bb ldr r3, [r7, #8] + 8009a66: f893 2023 ldrb.w r2, [r3, #35] ; 0x23 + 8009a6a: 4b4a ldr r3, [pc, #296] ; (8009b94 ) + 8009a6c: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + 8009a6e: 68bb ldr r3, [r7, #8] + 8009a70: f893 2024 ldrb.w r2, [r3, #36] ; 0x24 + 8009a74: 4b47 ldr r3, [pc, #284] ; (8009b94 ) + 8009a76: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.LengthMode; + 8009a78: 68bb ldr r3, [r7, #8] + 8009a7a: f893 2022 ldrb.w r2, [r3, #34] ; 0x22 + 8009a7e: 4b45 ldr r3, [pc, #276] ; (8009b94 ) + 8009a80: 755a strb r2, [r3, #21] + RadioStandby( ); + 8009a82: f7ff fa3c bl 8008efe + RadioSetModem( MODEM_FSK ); + 8009a86: 2000 movs r0, #0 + 8009a88: f7fe fbd0 bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009a8c: 4844 ldr r0, [pc, #272] ; (8009ba0 ) + 8009a8e: f001 f82d bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8009a92: 4844 ldr r0, [pc, #272] ; (8009ba4 ) + 8009a94: f001 f8fc bl 800ac90 + SUBGRF_SetSyncWord( syncword ); + 8009a98: f107 0320 add.w r3, r7, #32 + 8009a9c: 4618 mov r0, r3 + 8009a9e: f000 fbc0 bl 800a222 + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + 8009aa2: 68bb ldr r3, [r7, #8] + 8009aa4: 8b9b ldrh r3, [r3, #28] + 8009aa6: 4618 mov r0, r3 + 8009aa8: f000 fc0a bl 800a2c0 + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + 8009aac: 68bb ldr r3, [r7, #8] + 8009aae: 8b1b ldrh r3, [r3, #24] + 8009ab0: 4618 mov r0, r3 + 8009ab2: f000 fbe5 bl 800a280 + SubgRf.RxTimeout = ( uint32_t )( ( symbTimeout * 1000 * 8 ) / config->fsk.BitRate ); + 8009ab6: 683b ldr r3, [r7, #0] + 8009ab8: f44f 52fa mov.w r2, #8000 ; 0x1f40 + 8009abc: fb03 f202 mul.w r2, r3, r2 + 8009ac0: 68bb ldr r3, [r7, #8] + 8009ac2: 689b ldr r3, [r3, #8] + 8009ac4: fbb2 f3f3 udiv r3, r2, r3 + 8009ac8: 4a32 ldr r2, [pc, #200] ; (8009b94 ) + 8009aca: 6093 str r3, [r2, #8] + break; + 8009acc: e0b9 b.n 8009c42 + if( config->lora.PreambleLen == 0 ) + 8009ace: 68bb ldr r3, [r7, #8] + 8009ad0: 8e1b ldrh r3, [r3, #48] ; 0x30 + 8009ad2: 2b00 cmp r3, #0 + 8009ad4: d102 bne.n 8009adc + return -1; + 8009ad6: f04f 33ff mov.w r3, #4294967295 + 8009ada: e0b3 b.n 8009c44 + if( config->lora.LengthMode == RADIO_LORA_PACKET_FIXED_LENGTH ) + 8009adc: 68bb ldr r3, [r7, #8] + 8009ade: f893 3032 ldrb.w r3, [r3, #50] ; 0x32 + 8009ae2: 2b01 cmp r3, #1 + 8009ae4: d104 bne.n 8009af0 + MaxPayloadLength = config->fsk.MaxPayloadLength; + 8009ae6: 68bb ldr r3, [r7, #8] + 8009ae8: 695b ldr r3, [r3, #20] + 8009aea: f887 302f strb.w r3, [r7, #47] ; 0x2f + 8009aee: e002 b.n 8009af6 + MaxPayloadLength = 0xFF; + 8009af0: 23ff movs r3, #255 ; 0xff + 8009af2: f887 302f strb.w r3, [r7, #47] ; 0x2f + SUBGRF_SetStopRxTimerOnPreambleDetect( ( config->lora.StopTimerOnPreambleDetect == 0 ) ? false : true ); + 8009af6: 68bb ldr r3, [r7, #8] + 8009af8: 6a9b ldr r3, [r3, #40] ; 0x28 + 8009afa: 2b00 cmp r3, #0 + 8009afc: bf14 ite ne + 8009afe: 2301 movne r3, #1 + 8009b00: 2300 moveq r3, #0 + 8009b02: b2db uxtb r3, r3 + 8009b04: 4618 mov r0, r3 + 8009b06: f000 fd53 bl 800a5b0 + SUBGRF_SetLoRaSymbNumTimeout( symbTimeout ); + 8009b0a: 683b ldr r3, [r7, #0] + 8009b0c: b2db uxtb r3, r3 + 8009b0e: 4618 mov r0, r3 + 8009b10: f000 fd5d bl 800a5ce + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8009b14: 4b1f ldr r3, [pc, #124] ; (8009b94 ) + 8009b16: 2201 movs r2, #1 + 8009b18: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + 8009b1c: 68bb ldr r3, [r7, #8] + 8009b1e: f893 202c ldrb.w r2, [r3, #44] ; 0x2c + 8009b22: 4b1c ldr r3, [pc, #112] ; (8009b94 ) + 8009b24: f883 2050 strb.w r2, [r3, #80] ; 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + 8009b28: 68bb ldr r3, [r7, #8] + 8009b2a: f893 202d ldrb.w r2, [r3, #45] ; 0x2d + 8009b2e: 4b19 ldr r3, [pc, #100] ; (8009b94 ) + 8009b30: f883 2051 strb.w r2, [r3, #81] ; 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + 8009b34: 68bb ldr r3, [r7, #8] + 8009b36: f893 202e ldrb.w r2, [r3, #46] ; 0x2e + 8009b3a: 4b16 ldr r3, [pc, #88] ; (8009b94 ) + 8009b3c: f883 2052 strb.w r2, [r3, #82] ; 0x52 + switch( config->lora.LowDatarateOptimize ) + 8009b40: 68bb ldr r3, [r7, #8] + 8009b42: f893 302f ldrb.w r3, [r3, #47] ; 0x2f + 8009b46: 2b02 cmp r3, #2 + 8009b48: d010 beq.n 8009b6c + 8009b4a: 2b02 cmp r3, #2 + 8009b4c: dc2c bgt.n 8009ba8 + 8009b4e: 2b00 cmp r3, #0 + 8009b50: d002 beq.n 8009b58 + 8009b52: 2b01 cmp r3, #1 + 8009b54: d005 beq.n 8009b62 + break; + 8009b56: e027 b.n 8009ba8 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8009b58: 4b0e ldr r3, [pc, #56] ; (8009b94 ) + 8009b5a: 2200 movs r2, #0 + 8009b5c: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009b60: e023 b.n 8009baa + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009b62: 4b0c ldr r3, [pc, #48] ; (8009b94 ) + 8009b64: 2201 movs r2, #1 + 8009b66: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009b6a: e01e b.n 8009baa + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + 8009b6c: 68bb ldr r3, [r7, #8] + 8009b6e: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8009b72: 2b0b cmp r3, #11 + 8009b74: d004 beq.n 8009b80 + 8009b76: 68bb ldr r3, [r7, #8] + 8009b78: f893 302c ldrb.w r3, [r3, #44] ; 0x2c + 8009b7c: 2b0c cmp r3, #12 + 8009b7e: d104 bne.n 8009b8a + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009b80: 4b04 ldr r3, [pc, #16] ; (8009b94 ) + 8009b82: 2201 movs r2, #1 + 8009b84: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009b88: e00f b.n 8009baa + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8009b8a: 4b02 ldr r3, [pc, #8] ; (8009b94 ) + 8009b8c: 2200 movs r2, #0 + 8009b8e: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009b92: e00a b.n 8009baa + 8009b94: 20000400 .word 0x20000400 + 8009b98: 200003fc .word 0x200003fc + 8009b9c: 20000474 .word 0x20000474 + 8009ba0: 20000438 .word 0x20000438 + 8009ba4: 2000040e .word 0x2000040e + break; + 8009ba8: bf00 nop + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8009baa: 4b28 ldr r3, [pc, #160] ; (8009c4c ) + 8009bac: 2201 movs r2, #1 + 8009bae: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + 8009bb0: 68bb ldr r3, [r7, #8] + 8009bb2: 8e1a ldrh r2, [r3, #48] ; 0x30 + 8009bb4: 4b25 ldr r3, [pc, #148] ; (8009c4c ) + 8009bb6: 839a strh r2, [r3, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + 8009bb8: 68bb ldr r3, [r7, #8] + 8009bba: f893 2032 ldrb.w r2, [r3, #50] ; 0x32 + 8009bbe: 4b23 ldr r3, [pc, #140] ; (8009c4c ) + 8009bc0: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.PayloadLength = MaxPayloadLength; + 8009bc2: 4a22 ldr r2, [pc, #136] ; (8009c4c ) + 8009bc4: f897 302f ldrb.w r3, [r7, #47] ; 0x2f + 8009bc8: 77d3 strb r3, [r2, #31] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + 8009bca: 68bb ldr r3, [r7, #8] + 8009bcc: f893 2034 ldrb.w r2, [r3, #52] ; 0x34 + 8009bd0: 4b1e ldr r3, [pc, #120] ; (8009c4c ) + 8009bd2: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + 8009bd6: 68bb ldr r3, [r7, #8] + 8009bd8: f893 2035 ldrb.w r2, [r3, #53] ; 0x35 + 8009bdc: 4b1b ldr r3, [pc, #108] ; (8009c4c ) + 8009bde: f883 2021 strb.w r2, [r3, #33] ; 0x21 + RadioStandby( ); + 8009be2: f7ff f98c bl 8008efe + RadioSetModem( MODEM_LORA ); + 8009be6: 2001 movs r0, #1 + 8009be8: f7fe fb20 bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009bec: 4818 ldr r0, [pc, #96] ; (8009c50 ) + 8009bee: f000 ff7d bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8009bf2: 4818 ldr r0, [pc, #96] ; (8009c54 ) + 8009bf4: f001 f84c bl 800ac90 + if( SubgRf.PacketParams.Params.LoRa.InvertIQ == LORA_IQ_INVERTED ) + 8009bf8: 4b14 ldr r3, [pc, #80] ; (8009c4c ) + 8009bfa: f893 3021 ldrb.w r3, [r3, #33] ; 0x21 + 8009bfe: 2b01 cmp r3, #1 + 8009c00: d10d bne.n 8009c1e + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) & ~( 1 << 2 ) ); + 8009c02: f240 7036 movw r0, #1846 ; 0x736 + 8009c06: f001 f99f bl 800af48 + 8009c0a: 4603 mov r3, r0 + 8009c0c: f023 0304 bic.w r3, r3, #4 + 8009c10: b2db uxtb r3, r3 + 8009c12: 4619 mov r1, r3 + 8009c14: f240 7036 movw r0, #1846 ; 0x736 + 8009c18: f001 f982 bl 800af20 + 8009c1c: e00c b.n 8009c38 + SUBGRF_WriteRegister( SUBGHZ_LIQPOLR, SUBGRF_ReadRegister( SUBGHZ_LIQPOLR ) | ( 1 << 2 ) ); + 8009c1e: f240 7036 movw r0, #1846 ; 0x736 + 8009c22: f001 f991 bl 800af48 + 8009c26: 4603 mov r3, r0 + 8009c28: f043 0304 orr.w r3, r3, #4 + 8009c2c: b2db uxtb r3, r3 + 8009c2e: 4619 mov r1, r3 + 8009c30: f240 7036 movw r0, #1846 ; 0x736 + 8009c34: f001 f974 bl 800af20 + SubgRf.RxTimeout = 0xFFFF; + 8009c38: 4b04 ldr r3, [pc, #16] ; (8009c4c ) + 8009c3a: f64f 72ff movw r2, #65535 ; 0xffff + 8009c3e: 609a str r2, [r3, #8] + break; + 8009c40: bf00 nop + } + return status; + 8009c42: 6abb ldr r3, [r7, #40] ; 0x28 +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + 8009c44: 4618 mov r0, r3 + 8009c46: 3730 adds r7, #48 ; 0x30 + 8009c48: 46bd mov sp, r7 + 8009c4a: bd80 pop {r7, pc} + 8009c4c: 20000400 .word 0x20000400 + 8009c50: 20000438 .word 0x20000438 + 8009c54: 2000040e .word 0x2000040e + +08009c58 : + +static int32_t RadioSetTxGenericConfig( GenericModems_t modem, TxConfigGeneric_t *config, int8_t power, + uint32_t timeout ) +{ + 8009c58: b580 push {r7, lr} + 8009c5a: b08e sub sp, #56 ; 0x38 + 8009c5c: af00 add r7, sp, #0 + 8009c5e: 60b9 str r1, [r7, #8] + 8009c60: 607b str r3, [r7, #4] + 8009c62: 4603 mov r3, r0 + 8009c64: 73fb strb r3, [r7, #15] + 8009c66: 4613 mov r3, r2 + 8009c68: 73bb strb r3, [r7, #14] +#if( RADIO_LR_FHSS_IS_ON == 1 ) + /*disable LrFhss*/ + SubgRf.lr_fhss.is_lr_fhss_on = false; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ +#if (RADIO_GENERIC_CONFIG_ENABLE == 1) + uint8_t syncword[8] = {0}; + 8009c6a: 2300 movs r3, #0 + 8009c6c: 62fb str r3, [r7, #44] ; 0x2c + 8009c6e: 2300 movs r3, #0 + 8009c70: 633b str r3, [r7, #48] ; 0x30 + RadioModems_t radio_modem; + RFW_DeInit( ); /* switch Off FwPacketDecoding by default */ + 8009c72: f001 fc3c bl 800b4ee + switch( modem ) + 8009c76: 7bfb ldrb r3, [r7, #15] + 8009c78: 2b03 cmp r3, #3 + 8009c7a: f200 8204 bhi.w 800a086 + 8009c7e: a201 add r2, pc, #4 ; (adr r2, 8009c84 ) + 8009c80: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 8009c84: 08009e09 .word 0x08009e09 + 8009c88: 08009f51 .word 0x08009f51 + 8009c8c: 0800a049 .word 0x0800a049 + 8009c90: 08009c95 .word 0x08009c95 + { + case GENERIC_MSK: + if( config->msk.SyncWordLength > 8 ) + 8009c94: 68bb ldr r3, [r7, #8] + 8009c96: 7c9b ldrb r3, [r3, #18] + 8009c98: 2b08 cmp r3, #8 + 8009c9a: d902 bls.n 8009ca2 + { + return -1; + 8009c9c: f04f 33ff mov.w r3, #4294967295 + 8009ca0: e206 b.n 800a0b0 + } + else + { + RADIO_MEMCPY8( syncword, config->msk.SyncWord, config->msk.SyncWordLength ); + 8009ca2: 68bb ldr r3, [r7, #8] + 8009ca4: 6899 ldr r1, [r3, #8] + 8009ca6: 68bb ldr r3, [r7, #8] + 8009ca8: 7c9b ldrb r3, [r3, #18] + 8009caa: b29a uxth r2, r3 + 8009cac: f107 032c add.w r3, r7, #44 ; 0x2c + 8009cb0: 4618 mov r0, r3 + 8009cb2: f002 f87d bl 800bdb0 + } + if( ( config->msk.BitRate == 0 ) ) + 8009cb6: 68bb ldr r3, [r7, #8] + 8009cb8: 681b ldr r3, [r3, #0] + 8009cba: 2b00 cmp r3, #0 + 8009cbc: d102 bne.n 8009cc4 + { + return -1; + 8009cbe: f04f 33ff mov.w r3, #4294967295 + 8009cc2: e1f5 b.n 800a0b0 + } + else if( config->msk.BitRate <= 10000 ) + 8009cc4: 68bb ldr r3, [r7, #8] + 8009cc6: 681b ldr r3, [r3, #0] + 8009cc8: f242 7210 movw r2, #10000 ; 0x2710 + 8009ccc: 4293 cmp r3, r2 + 8009cce: d813 bhi.n 8009cf8 + { + /*max msk modulator datarate is 10kbps*/ + radio_modem = MODEM_MSK; + 8009cd0: 2302 movs r3, #2 + 8009cd2: f887 3037 strb.w r3, [r7, #55] ; 0x37 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GMSK; + 8009cd6: 4b99 ldr r3, [pc, #612] ; (8009f3c ) + 8009cd8: 2203 movs r2, #3 + 8009cda: 739a strb r2, [r3, #14] + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GMSK; + 8009cdc: 4b97 ldr r3, [pc, #604] ; (8009f3c ) + 8009cde: 2203 movs r2, #3 + 8009ce0: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + 8009ce4: 68bb ldr r3, [r7, #8] + 8009ce6: 681b ldr r3, [r3, #0] + 8009ce8: 4a94 ldr r2, [pc, #592] ; (8009f3c ) + 8009cea: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + 8009cec: 68bb ldr r3, [r7, #8] + 8009cee: 7cda ldrb r2, [r3, #19] + 8009cf0: 4b92 ldr r3, [pc, #584] ; (8009f3c ) + 8009cf2: f883 2044 strb.w r2, [r3, #68] ; 0x44 + 8009cf6: e017 b.n 8009d28 + } + else + { + radio_modem = MODEM_FSK; + 8009cf8: 2300 movs r3, #0 + 8009cfa: f887 3037 strb.w r3, [r7, #55] ; 0x37 + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8009cfe: 4b8f ldr r3, [pc, #572] ; (8009f3c ) + 8009d00: 2200 movs r2, #0 + 8009d02: 739a strb r2, [r3, #14] + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8009d04: 4b8d ldr r3, [pc, #564] ; (8009f3c ) + 8009d06: 2200 movs r2, #0 + 8009d08: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->msk.BitRate; + 8009d0c: 68bb ldr r3, [r7, #8] + 8009d0e: 681b ldr r3, [r3, #0] + 8009d10: 4a8a ldr r2, [pc, #552] ; (8009f3c ) + 8009d12: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->msk.ModulationShaping; + 8009d14: 68bb ldr r3, [r7, #8] + 8009d16: 7cda ldrb r2, [r3, #19] + 8009d18: 4b88 ldr r3, [pc, #544] ; (8009f3c ) + 8009d1a: f883 2044 strb.w r2, [r3, #68] ; 0x44 + /*do msk with gfsk modulator*/ + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->msk.BitRate / 4; + 8009d1e: 68bb ldr r3, [r7, #8] + 8009d20: 681b ldr r3, [r3, #0] + 8009d22: 089b lsrs r3, r3, #2 + 8009d24: 4a85 ldr r2, [pc, #532] ; (8009f3c ) + 8009d26: 6413 str r3, [r2, #64] ; 0x40 + } + + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->msk.PreambleLen ) << 3; // convert byte into bit + 8009d28: 68bb ldr r3, [r7, #8] + 8009d2a: 685b ldr r3, [r3, #4] + 8009d2c: b29b uxth r3, r3 + 8009d2e: 00db lsls r3, r3, #3 + 8009d30: b29a uxth r2, r3 + 8009d32: 4b82 ldr r3, [pc, #520] ; (8009f3c ) + 8009d34: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + 8009d36: 4b81 ldr r3, [pc, #516] ; (8009f3c ) + 8009d38: 2204 movs r2, #4 + 8009d3a: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->msk.SyncWordLength ) << 3; // convert byte into bit + 8009d3c: 68bb ldr r3, [r7, #8] + 8009d3e: 7c9b ldrb r3, [r3, #18] + 8009d40: 00db lsls r3, r3, #3 + 8009d42: b2da uxtb r2, r3 + 8009d44: 4b7d ldr r3, [pc, #500] ; (8009f3c ) + 8009d46: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + 8009d48: 4b7c ldr r3, [pc, #496] ; (8009f3c ) + 8009d4a: 2200 movs r2, #0 + 8009d4c: 751a strb r2, [r3, #20] + + if( ( config->msk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 8009d4e: 68bb ldr r3, [r7, #8] + 8009d50: 7d9b ldrb r3, [r3, #22] + 8009d52: 2b02 cmp r3, #2 + 8009d54: d003 beq.n 8009d5e + || ( config->msk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 8009d56: 68bb ldr r3, [r7, #8] + 8009d58: 7d1b ldrb r3, [r3, #20] + 8009d5a: 2b02 cmp r3, #2 + 8009d5c: d12b bne.n 8009db6 + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->msk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 8009d5e: 68bb ldr r3, [r7, #8] + 8009d60: 7d5b ldrb r3, [r3, #21] + 8009d62: 2bf1 cmp r3, #241 ; 0xf1 + 8009d64: d00a beq.n 8009d7c + 8009d66: 68bb ldr r3, [r7, #8] + 8009d68: 7d5b ldrb r3, [r3, #21] + 8009d6a: 2bf2 cmp r3, #242 ; 0xf2 + 8009d6c: d006 beq.n 8009d7c + && ( config->msk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 8009d6e: 68bb ldr r3, [r7, #8] + 8009d70: 7d5b ldrb r3, [r3, #21] + 8009d72: 2b01 cmp r3, #1 + 8009d74: d002 beq.n 8009d7c + { + return -1; + 8009d76: f04f 33ff mov.w r3, #4294967295 + 8009d7a: e199 b.n 800a0b0 + } + ConfigGeneric_t ConfigGeneric; + /*msk and fsk are union, no need for copy as fsk/msk struct are on same address*/ + ConfigGeneric.TxConfig = config; + 8009d7c: 68bb ldr r3, [r7, #8] + 8009d7e: 623b str r3, [r7, #32] + ConfigGeneric.rtx = CONFIG_TX; + 8009d80: 2301 movs r3, #1 + 8009d82: f887 3028 strb.w r3, [r7, #40] ; 0x28 + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + 8009d86: 4b6e ldr r3, [pc, #440] ; (8009f40 ) + 8009d88: 6819 ldr r1, [r3, #0] + 8009d8a: f107 0320 add.w r3, r7, #32 + 8009d8e: 4a6d ldr r2, [pc, #436] ; (8009f44 ) + 8009d90: 4618 mov r0, r3 + 8009d92: f001 fb9f bl 800b4d4 + 8009d96: 4603 mov r3, r0 + 8009d98: 2b00 cmp r3, #0 + 8009d9a: d002 beq.n 8009da2 + { + return -1; + 8009d9c: f04f 33ff mov.w r3, #4294967295 + 8009da0: e186 b.n 800a0b0 + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 8009da2: 4b66 ldr r3, [pc, #408] ; (8009f3c ) + 8009da4: 2200 movs r2, #0 + 8009da6: 761a strb r2, [r3, #24] + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 8009da8: 4b64 ldr r3, [pc, #400] ; (8009f3c ) + 8009daa: 2201 movs r2, #1 + 8009dac: 75da strb r2, [r3, #23] + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 8009dae: 4b63 ldr r3, [pc, #396] ; (8009f3c ) + 8009db0: 2200 movs r2, #0 + 8009db2: 755a strb r2, [r3, #21] + { + 8009db4: e00b b.n 8009dce + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->msk.CrcLength; + 8009db6: 68bb ldr r3, [r7, #8] + 8009db8: 7d5a ldrb r2, [r3, #21] + 8009dba: 4b60 ldr r3, [pc, #384] ; (8009f3c ) + 8009dbc: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->msk.Whitening; + 8009dbe: 68bb ldr r3, [r7, #8] + 8009dc0: 7d9a ldrb r2, [r3, #22] + 8009dc2: 4b5e ldr r3, [pc, #376] ; (8009f3c ) + 8009dc4: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->msk.HeaderType; + 8009dc6: 68bb ldr r3, [r7, #8] + 8009dc8: 7d1a ldrb r2, [r3, #20] + 8009dca: 4b5c ldr r3, [pc, #368] ; (8009f3c ) + 8009dcc: 755a strb r2, [r3, #21] + } + + RadioStandby( ); + 8009dce: f7ff f896 bl 8008efe + RadioSetModem( radio_modem ); + 8009dd2: f897 3037 ldrb.w r3, [r7, #55] ; 0x37 + 8009dd6: 4618 mov r0, r3 + 8009dd8: f7fe fa28 bl 800822c + + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009ddc: 485a ldr r0, [pc, #360] ; (8009f48 ) + 8009dde: f000 fe85 bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8009de2: 485a ldr r0, [pc, #360] ; (8009f4c ) + 8009de4: f000 ff54 bl 800ac90 + SUBGRF_SetSyncWord( syncword ); + 8009de8: f107 032c add.w r3, r7, #44 ; 0x2c + 8009dec: 4618 mov r0, r3 + 8009dee: f000 fa18 bl 800a222 + SUBGRF_SetWhiteningSeed( config->msk.whiteSeed ); + 8009df2: 68bb ldr r3, [r7, #8] + 8009df4: 8a1b ldrh r3, [r3, #16] + 8009df6: 4618 mov r0, r3 + 8009df8: f000 fa62 bl 800a2c0 + SUBGRF_SetCrcPolynomial( config->msk.CrcPolynomial ); + 8009dfc: 68bb ldr r3, [r7, #8] + 8009dfe: 899b ldrh r3, [r3, #12] + 8009e00: 4618 mov r0, r3 + 8009e02: f000 fa3d bl 800a280 + break; + 8009e06: e13f b.n 800a088 + case GENERIC_FSK: + if( config->fsk.BitRate == 0 ) + 8009e08: 68bb ldr r3, [r7, #8] + 8009e0a: 681b ldr r3, [r3, #0] + 8009e0c: 2b00 cmp r3, #0 + 8009e0e: d102 bne.n 8009e16 + { + return -1; + 8009e10: f04f 33ff mov.w r3, #4294967295 + 8009e14: e14c b.n 800a0b0 + } + if( config->fsk.SyncWordLength > 8 ) + 8009e16: 68bb ldr r3, [r7, #8] + 8009e18: 7c9b ldrb r3, [r3, #18] + 8009e1a: 2b08 cmp r3, #8 + 8009e1c: d902 bls.n 8009e24 + { + return -1; + 8009e1e: f04f 33ff mov.w r3, #4294967295 + 8009e22: e145 b.n 800a0b0 + } + else + { + RADIO_MEMCPY8( syncword, config->fsk.SyncWord, config->fsk.SyncWordLength ); + 8009e24: 68bb ldr r3, [r7, #8] + 8009e26: 6899 ldr r1, [r3, #8] + 8009e28: 68bb ldr r3, [r7, #8] + 8009e2a: 7c9b ldrb r3, [r3, #18] + 8009e2c: b29a uxth r2, r3 + 8009e2e: f107 032c add.w r3, r7, #44 ; 0x2c + 8009e32: 4618 mov r0, r3 + 8009e34: f001 ffbc bl 800bdb0 + } + SubgRf.ModulationParams.PacketType = PACKET_TYPE_GFSK; + 8009e38: 4b40 ldr r3, [pc, #256] ; (8009f3c ) + 8009e3a: 2200 movs r2, #0 + 8009e3c: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Gfsk.BitRate = config->fsk.BitRate; + 8009e40: 68bb ldr r3, [r7, #8] + 8009e42: 681b ldr r3, [r3, #0] + 8009e44: 4a3d ldr r2, [pc, #244] ; (8009f3c ) + 8009e46: 63d3 str r3, [r2, #60] ; 0x3c + SubgRf.ModulationParams.Params.Gfsk.ModulationShaping = ( RadioModShapings_t ) config->fsk.ModulationShaping; + 8009e48: 68bb ldr r3, [r7, #8] + 8009e4a: 7cda ldrb r2, [r3, #19] + 8009e4c: 4b3b ldr r3, [pc, #236] ; (8009f3c ) + 8009e4e: f883 2044 strb.w r2, [r3, #68] ; 0x44 + SubgRf.ModulationParams.Params.Gfsk.Fdev = config->fsk.FrequencyDeviation; + 8009e52: 68bb ldr r3, [r7, #8] + 8009e54: 699b ldr r3, [r3, #24] + 8009e56: 4a39 ldr r2, [pc, #228] ; (8009f3c ) + 8009e58: 6413 str r3, [r2, #64] ; 0x40 + + SubgRf.PacketParams.PacketType = PACKET_TYPE_GFSK; + 8009e5a: 4b38 ldr r3, [pc, #224] ; (8009f3c ) + 8009e5c: 2200 movs r2, #0 + 8009e5e: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.Gfsk.PreambleLength = ( config->fsk.PreambleLen ) << 3; // convert byte into bit + 8009e60: 68bb ldr r3, [r7, #8] + 8009e62: 685b ldr r3, [r3, #4] + 8009e64: b29b uxth r3, r3 + 8009e66: 00db lsls r3, r3, #3 + 8009e68: b29a uxth r2, r3 + 8009e6a: 4b34 ldr r3, [pc, #208] ; (8009f3c ) + 8009e6c: 821a strh r2, [r3, #16] + SubgRf.PacketParams.Params.Gfsk.PreambleMinDetect = RADIO_PREAMBLE_DETECTOR_08_BITS; // don't care in tx + 8009e6e: 4b33 ldr r3, [pc, #204] ; (8009f3c ) + 8009e70: 2204 movs r2, #4 + 8009e72: 749a strb r2, [r3, #18] + SubgRf.PacketParams.Params.Gfsk.SyncWordLength = ( config->fsk.SyncWordLength ) << 3; // convert byte into bit + 8009e74: 68bb ldr r3, [r7, #8] + 8009e76: 7c9b ldrb r3, [r3, #18] + 8009e78: 00db lsls r3, r3, #3 + 8009e7a: b2da uxtb r2, r3 + 8009e7c: 4b2f ldr r3, [pc, #188] ; (8009f3c ) + 8009e7e: 74da strb r2, [r3, #19] + SubgRf.PacketParams.Params.Gfsk.AddrComp = RADIO_ADDRESSCOMP_FILT_OFF; // don't care in tx + 8009e80: 4b2e ldr r3, [pc, #184] ; (8009f3c ) + 8009e82: 2200 movs r2, #0 + 8009e84: 751a strb r2, [r3, #20] + + if( ( config->fsk.Whitening == RADIO_FSK_DC_IBM_WHITENING ) + 8009e86: 68bb ldr r3, [r7, #8] + 8009e88: 7d9b ldrb r3, [r3, #22] + 8009e8a: 2b02 cmp r3, #2 + 8009e8c: d003 beq.n 8009e96 + || ( config->fsk.HeaderType == RADIO_FSK_PACKET_2BYTES_LENGTH ) ) + 8009e8e: 68bb ldr r3, [r7, #8] + 8009e90: 7d1b ldrb r3, [r3, #20] + 8009e92: 2b02 cmp r3, #2 + 8009e94: d12a bne.n 8009eec + { + /* Supports only RADIO_FSK_CRC_2_BYTES_IBM or RADIO_FSK_CRC_2_BYTES_CCIT */ + if( ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_IBM ) && ( config->fsk.CrcLength != RADIO_FSK_CRC_2_BYTES_CCIT ) + 8009e96: 68bb ldr r3, [r7, #8] + 8009e98: 7d5b ldrb r3, [r3, #21] + 8009e9a: 2bf1 cmp r3, #241 ; 0xf1 + 8009e9c: d00a beq.n 8009eb4 + 8009e9e: 68bb ldr r3, [r7, #8] + 8009ea0: 7d5b ldrb r3, [r3, #21] + 8009ea2: 2bf2 cmp r3, #242 ; 0xf2 + 8009ea4: d006 beq.n 8009eb4 + && ( config->fsk.CrcLength != RADIO_FSK_CRC_OFF ) ) + 8009ea6: 68bb ldr r3, [r7, #8] + 8009ea8: 7d5b ldrb r3, [r3, #21] + 8009eaa: 2b01 cmp r3, #1 + 8009eac: d002 beq.n 8009eb4 + { + return -1; + 8009eae: f04f 33ff mov.w r3, #4294967295 + 8009eb2: e0fd b.n 800a0b0 + } + ConfigGeneric_t ConfigGeneric; + ConfigGeneric.rtx = CONFIG_TX; + 8009eb4: 2301 movs r3, #1 + 8009eb6: 773b strb r3, [r7, #28] + ConfigGeneric.TxConfig = config; + 8009eb8: 68bb ldr r3, [r7, #8] + 8009eba: 617b str r3, [r7, #20] + if( 0UL != RFW_Init( &ConfigGeneric, RadioEvents, &TxTimeoutTimer ) ) + 8009ebc: 4b20 ldr r3, [pc, #128] ; (8009f40 ) + 8009ebe: 6819 ldr r1, [r3, #0] + 8009ec0: f107 0314 add.w r3, r7, #20 + 8009ec4: 4a1f ldr r2, [pc, #124] ; (8009f44 ) + 8009ec6: 4618 mov r0, r3 + 8009ec8: f001 fb04 bl 800b4d4 + 8009ecc: 4603 mov r3, r0 + 8009ece: 2b00 cmp r3, #0 + 8009ed0: d002 beq.n 8009ed8 + { + return -1; + 8009ed2: f04f 33ff mov.w r3, #4294967295 + 8009ed6: e0eb b.n 800a0b0 + } + /* whitening off, will be processed by FW, switch off built-in radio whitening */ + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) RADIO_FSK_DC_FREE_OFF; + 8009ed8: 4b18 ldr r3, [pc, #96] ; (8009f3c ) + 8009eda: 2200 movs r2, #0 + 8009edc: 761a strb r2, [r3, #24] + /* Crc processed by FW, switch off built-in radio Crc */ + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) RADIO_CRC_OFF; + 8009ede: 4b17 ldr r3, [pc, #92] ; (8009f3c ) + 8009ee0: 2201 movs r2, #1 + 8009ee2: 75da strb r2, [r3, #23] + /* length contained in Tx, but will be processed by FW after de-whitening */ + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) RADIO_PACKET_FIXED_LENGTH; + 8009ee4: 4b15 ldr r3, [pc, #84] ; (8009f3c ) + 8009ee6: 2200 movs r2, #0 + 8009ee8: 755a strb r2, [r3, #21] + { + 8009eea: e00b b.n 8009f04 + } + else + { + SubgRf.PacketParams.Params.Gfsk.CrcLength = ( RadioCrcTypes_t ) config->fsk.CrcLength; + 8009eec: 68bb ldr r3, [r7, #8] + 8009eee: 7d5a ldrb r2, [r3, #21] + 8009ef0: 4b12 ldr r3, [pc, #72] ; (8009f3c ) + 8009ef2: 75da strb r2, [r3, #23] + SubgRf.PacketParams.Params.Gfsk.DcFree = ( RadioDcFree_t ) config->fsk.Whitening; + 8009ef4: 68bb ldr r3, [r7, #8] + 8009ef6: 7d9a ldrb r2, [r3, #22] + 8009ef8: 4b10 ldr r3, [pc, #64] ; (8009f3c ) + 8009efa: 761a strb r2, [r3, #24] + SubgRf.PacketParams.Params.Gfsk.HeaderType = ( RadioPacketLengthModes_t ) config->fsk.HeaderType; + 8009efc: 68bb ldr r3, [r7, #8] + 8009efe: 7d1a ldrb r2, [r3, #20] + 8009f00: 4b0e ldr r3, [pc, #56] ; (8009f3c ) + 8009f02: 755a strb r2, [r3, #21] + } + + RadioStandby( ); + 8009f04: f7fe fffb bl 8008efe + RadioSetModem( MODEM_FSK ); + 8009f08: 2000 movs r0, #0 + 8009f0a: f7fe f98f bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009f0e: 480e ldr r0, [pc, #56] ; (8009f48 ) + 8009f10: f000 fdec bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 8009f14: 480d ldr r0, [pc, #52] ; (8009f4c ) + 8009f16: f000 febb bl 800ac90 + SUBGRF_SetSyncWord( syncword ); + 8009f1a: f107 032c add.w r3, r7, #44 ; 0x2c + 8009f1e: 4618 mov r0, r3 + 8009f20: f000 f97f bl 800a222 + SUBGRF_SetWhiteningSeed( config->fsk.whiteSeed ); + 8009f24: 68bb ldr r3, [r7, #8] + 8009f26: 8a1b ldrh r3, [r3, #16] + 8009f28: 4618 mov r0, r3 + 8009f2a: f000 f9c9 bl 800a2c0 + SUBGRF_SetCrcPolynomial( config->fsk.CrcPolynomial ); + 8009f2e: 68bb ldr r3, [r7, #8] + 8009f30: 899b ldrh r3, [r3, #12] + 8009f32: 4618 mov r0, r3 + 8009f34: f000 f9a4 bl 800a280 + break; + 8009f38: e0a6 b.n 800a088 + 8009f3a: bf00 nop + 8009f3c: 20000400 .word 0x20000400 + 8009f40: 200003fc .word 0x200003fc + 8009f44: 2000045c .word 0x2000045c + 8009f48: 20000438 .word 0x20000438 + 8009f4c: 2000040e .word 0x2000040e + case GENERIC_LORA: + SubgRf.ModulationParams.PacketType = PACKET_TYPE_LORA; + 8009f50: 4b59 ldr r3, [pc, #356] ; (800a0b8 ) + 8009f52: 2201 movs r2, #1 + 8009f54: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.LoRa.SpreadingFactor = ( RadioLoRaSpreadingFactors_t ) config->lora.SpreadingFactor; + 8009f58: 68bb ldr r3, [r7, #8] + 8009f5a: 781a ldrb r2, [r3, #0] + 8009f5c: 4b56 ldr r3, [pc, #344] ; (800a0b8 ) + 8009f5e: f883 2050 strb.w r2, [r3, #80] ; 0x50 + SubgRf.ModulationParams.Params.LoRa.Bandwidth = ( RadioLoRaBandwidths_t ) config->lora.Bandwidth; + 8009f62: 68bb ldr r3, [r7, #8] + 8009f64: 785a ldrb r2, [r3, #1] + 8009f66: 4b54 ldr r3, [pc, #336] ; (800a0b8 ) + 8009f68: f883 2051 strb.w r2, [r3, #81] ; 0x51 + SubgRf.ModulationParams.Params.LoRa.CodingRate = ( RadioLoRaCodingRates_t ) config->lora.Coderate; + 8009f6c: 68bb ldr r3, [r7, #8] + 8009f6e: 789a ldrb r2, [r3, #2] + 8009f70: 4b51 ldr r3, [pc, #324] ; (800a0b8 ) + 8009f72: f883 2052 strb.w r2, [r3, #82] ; 0x52 + switch( config->lora.LowDatarateOptimize ) + 8009f76: 68bb ldr r3, [r7, #8] + 8009f78: 78db ldrb r3, [r3, #3] + 8009f7a: 2b02 cmp r3, #2 + 8009f7c: d010 beq.n 8009fa0 + 8009f7e: 2b02 cmp r3, #2 + 8009f80: dc20 bgt.n 8009fc4 + 8009f82: 2b00 cmp r3, #0 + 8009f84: d002 beq.n 8009f8c + 8009f86: 2b01 cmp r3, #1 + 8009f88: d005 beq.n 8009f96 + { + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + } + break; + default: + break; + 8009f8a: e01b b.n 8009fc4 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8009f8c: 4b4a ldr r3, [pc, #296] ; (800a0b8 ) + 8009f8e: 2200 movs r2, #0 + 8009f90: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009f94: e017 b.n 8009fc6 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009f96: 4b48 ldr r3, [pc, #288] ; (800a0b8 ) + 8009f98: 2201 movs r2, #1 + 8009f9a: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009f9e: e012 b.n 8009fc6 + if( ( config->lora.SpreadingFactor == RADIO_LORA_SF11 ) || ( config->lora.SpreadingFactor == RADIO_LORA_SF12 ) ) + 8009fa0: 68bb ldr r3, [r7, #8] + 8009fa2: 781b ldrb r3, [r3, #0] + 8009fa4: 2b0b cmp r3, #11 + 8009fa6: d003 beq.n 8009fb0 + 8009fa8: 68bb ldr r3, [r7, #8] + 8009faa: 781b ldrb r3, [r3, #0] + 8009fac: 2b0c cmp r3, #12 + 8009fae: d104 bne.n 8009fba + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 1; + 8009fb0: 4b41 ldr r3, [pc, #260] ; (800a0b8 ) + 8009fb2: 2201 movs r2, #1 + 8009fb4: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009fb8: e005 b.n 8009fc6 + SubgRf.ModulationParams.Params.LoRa.LowDatarateOptimize = 0; + 8009fba: 4b3f ldr r3, [pc, #252] ; (800a0b8 ) + 8009fbc: 2200 movs r2, #0 + 8009fbe: f883 2053 strb.w r2, [r3, #83] ; 0x53 + break; + 8009fc2: e000 b.n 8009fc6 + break; + 8009fc4: bf00 nop + } + + SubgRf.PacketParams.PacketType = PACKET_TYPE_LORA; + 8009fc6: 4b3c ldr r3, [pc, #240] ; (800a0b8 ) + 8009fc8: 2201 movs r2, #1 + 8009fca: 739a strb r2, [r3, #14] + SubgRf.PacketParams.Params.LoRa.PreambleLength = config->lora.PreambleLen; + 8009fcc: 68bb ldr r3, [r7, #8] + 8009fce: 889a ldrh r2, [r3, #4] + 8009fd0: 4b39 ldr r3, [pc, #228] ; (800a0b8 ) + 8009fd2: 839a strh r2, [r3, #28] + SubgRf.PacketParams.Params.LoRa.HeaderType = ( RadioLoRaPacketLengthsMode_t ) config->lora.LengthMode; + 8009fd4: 68bb ldr r3, [r7, #8] + 8009fd6: 799a ldrb r2, [r3, #6] + 8009fd8: 4b37 ldr r3, [pc, #220] ; (800a0b8 ) + 8009fda: 779a strb r2, [r3, #30] + SubgRf.PacketParams.Params.LoRa.CrcMode = ( RadioLoRaCrcModes_t ) config->lora.CrcMode; + 8009fdc: 68bb ldr r3, [r7, #8] + 8009fde: 79da ldrb r2, [r3, #7] + 8009fe0: 4b35 ldr r3, [pc, #212] ; (800a0b8 ) + 8009fe2: f883 2020 strb.w r2, [r3, #32] + SubgRf.PacketParams.Params.LoRa.InvertIQ = ( RadioLoRaIQModes_t ) config->lora.IqInverted; + 8009fe6: 68bb ldr r3, [r7, #8] + 8009fe8: 7a1a ldrb r2, [r3, #8] + 8009fea: 4b33 ldr r3, [pc, #204] ; (800a0b8 ) + 8009fec: f883 2021 strb.w r2, [r3, #33] ; 0x21 + + RadioStandby( ); + 8009ff0: f7fe ff85 bl 8008efe + RadioSetModem( MODEM_LORA ); + 8009ff4: 2001 movs r0, #1 + 8009ff6: f7fe f919 bl 800822c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 8009ffa: 4830 ldr r0, [pc, #192] ; (800a0bc ) + 8009ffc: f000 fd76 bl 800aaec + SUBGRF_SetPacketParams( &SubgRf.PacketParams ); + 800a000: 482f ldr r0, [pc, #188] ; (800a0c0 ) + 800a002: f000 fe45 bl 800ac90 + + /* WORKAROUND - Modulation Quality with 500 kHz LoRa Bandwidth, see STM32WL Erratasheet */ + if( SubgRf.ModulationParams.Params.LoRa.Bandwidth == LORA_BW_500 ) + 800a006: 4b2c ldr r3, [pc, #176] ; (800a0b8 ) + 800a008: f893 3051 ldrb.w r3, [r3, #81] ; 0x51 + 800a00c: 2b06 cmp r3, #6 + 800a00e: d10d bne.n 800a02c + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) & ~( 1 << 2 ) ); + 800a010: f640 0089 movw r0, #2185 ; 0x889 + 800a014: f000 ff98 bl 800af48 + 800a018: 4603 mov r3, r0 + 800a01a: f023 0304 bic.w r3, r3, #4 + 800a01e: b2db uxtb r3, r3 + 800a020: 4619 mov r1, r3 + 800a022: f640 0089 movw r0, #2185 ; 0x889 + 800a026: f000 ff7b bl 800af20 + { + // RegTxModulation = @address 0x0889 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + } + /* WORKAROUND END */ + break; + 800a02a: e02d b.n 800a088 + SUBGRF_WriteRegister( SUBGHZ_SDCFG0R, SUBGRF_ReadRegister( SUBGHZ_SDCFG0R ) | ( 1 << 2 ) ); + 800a02c: f640 0089 movw r0, #2185 ; 0x889 + 800a030: f000 ff8a bl 800af48 + 800a034: 4603 mov r3, r0 + 800a036: f043 0304 orr.w r3, r3, #4 + 800a03a: b2db uxtb r3, r3 + 800a03c: 4619 mov r1, r3 + 800a03e: f640 0089 movw r0, #2185 ; 0x889 + 800a042: f000 ff6d bl 800af20 + break; + 800a046: e01f b.n 800a088 + case GENERIC_BPSK: + if( ( config->bpsk.BitRate == 0 ) || ( config->bpsk.BitRate > 1000 ) ) + 800a048: 68bb ldr r3, [r7, #8] + 800a04a: 681b ldr r3, [r3, #0] + 800a04c: 2b00 cmp r3, #0 + 800a04e: d004 beq.n 800a05a + 800a050: 68bb ldr r3, [r7, #8] + 800a052: 681b ldr r3, [r3, #0] + 800a054: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 800a058: d902 bls.n 800a060 + { + return -1; + 800a05a: f04f 33ff mov.w r3, #4294967295 + 800a05e: e027 b.n 800a0b0 + } + RadioSetModem( MODEM_BPSK ); + 800a060: 2003 movs r0, #3 + 800a062: f7fe f8e3 bl 800822c + SubgRf.ModulationParams.PacketType = PACKET_TYPE_BPSK; + 800a066: 4b14 ldr r3, [pc, #80] ; (800a0b8 ) + 800a068: 2202 movs r2, #2 + 800a06a: f883 2038 strb.w r2, [r3, #56] ; 0x38 + SubgRf.ModulationParams.Params.Bpsk.BitRate = config->bpsk.BitRate; + 800a06e: 68bb ldr r3, [r7, #8] + 800a070: 681b ldr r3, [r3, #0] + 800a072: 4a11 ldr r2, [pc, #68] ; (800a0b8 ) + 800a074: 6493 str r3, [r2, #72] ; 0x48 + SubgRf.ModulationParams.Params.Bpsk.ModulationShaping = MOD_SHAPING_DBPSK; + 800a076: 4b10 ldr r3, [pc, #64] ; (800a0b8 ) + 800a078: 2216 movs r2, #22 + 800a07a: f883 204c strb.w r2, [r3, #76] ; 0x4c + SUBGRF_SetModulationParams( &SubgRf.ModulationParams ); + 800a07e: 480f ldr r0, [pc, #60] ; (800a0bc ) + 800a080: f000 fd34 bl 800aaec + break; + 800a084: e000 b.n 800a088 + default: + break; + 800a086: bf00 nop + } + + SubgRf.AntSwitchPaSelect = SUBGRF_SetRfTxPower( power ); + 800a088: f997 300e ldrsb.w r3, [r7, #14] + 800a08c: 4618 mov r0, r3 + 800a08e: f001 f863 bl 800b158 + 800a092: 4603 mov r3, r0 + 800a094: 461a mov r2, r3 + 800a096: 4b08 ldr r3, [pc, #32] ; (800a0b8 ) + 800a098: f883 2056 strb.w r2, [r3, #86] ; 0x56 + RFW_SetAntSwitch( SubgRf.AntSwitchPaSelect ); + 800a09c: 4b06 ldr r3, [pc, #24] ; (800a0b8 ) + 800a09e: f893 3056 ldrb.w r3, [r3, #86] ; 0x56 + 800a0a2: 4618 mov r0, r3 + 800a0a4: f001 fa37 bl 800b516 + SubgRf.TxTimeout = timeout; + 800a0a8: 4a03 ldr r2, [pc, #12] ; (800a0b8 ) + 800a0aa: 687b ldr r3, [r7, #4] + 800a0ac: 6053 str r3, [r2, #4] + return 0; + 800a0ae: 2300 movs r3, #0 +#else /* RADIO_GENERIC_CONFIG_ENABLE == 1*/ + return -1; +#endif /* RADIO_GENERIC_CONFIG_ENABLE == 0*/ +} + 800a0b0: 4618 mov r0, r3 + 800a0b2: 3738 adds r7, #56 ; 0x38 + 800a0b4: 46bd mov sp, r7 + 800a0b6: bd80 pop {r7, pc} + 800a0b8: 20000400 .word 0x20000400 + 800a0bc: 20000438 .word 0x20000438 + 800a0c0: 2000040e .word 0x2000040e + +0800a0c4 : + return ( prbs31_val - 1 ) % ( max ); +} +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + +static radio_status_t RadioLrFhssSetCfg( const radio_lr_fhss_cfg_params_t *cfg_params ) +{ + 800a0c4: b480 push {r7} + 800a0c6: b085 sub sp, #20 + 800a0c8: af00 add r7, sp, #0 + 800a0ca: 6078 str r0, [r7, #4] + radio_status_t status = RADIO_STATUS_UNSUPPORTED_FEATURE; + 800a0cc: 2301 movs r3, #1 + 800a0ce: 73fb strb r3, [r7, #15] + { + return status; + } + SubgRf.lr_fhss.is_lr_fhss_on = true; +#endif /* RADIO_LR_FHSS_IS_ON == 1 */ + return status; + 800a0d0: 7bfb ldrb r3, [r7, #15] +} + 800a0d2: 4618 mov r0, r3 + 800a0d4: 3714 adds r7, #20 + 800a0d6: 46bd mov sp, r7 + 800a0d8: bc80 pop {r7} + 800a0da: 4770 bx lr + +0800a0dc : + +static radio_status_t RadioLrFhssGetTimeOnAirInMs( const radio_lr_fhss_time_on_air_params_t *params, + uint32_t *time_on_air_in_ms ) +{ + 800a0dc: b480 push {r7} + 800a0de: b083 sub sp, #12 + 800a0e0: af00 add r7, sp, #0 + 800a0e2: 6078 str r0, [r7, #4] + 800a0e4: 6039 str r1, [r7, #0] + *time_on_air_in_ms = lr_fhss_get_time_on_air_in_ms( ¶ms->radio_lr_fhss_params.lr_fhss_params, + params->pld_len_in_bytes ); + + return RADIO_STATUS_OK; +#else + return RADIO_STATUS_UNSUPPORTED_FEATURE; + 800a0e6: 2301 movs r3, #1 +#endif /* RADIO_LR_FHSS_IS_ON */ + 800a0e8: 4618 mov r0, r3 + 800a0ea: 370c adds r7, #12 + 800a0ec: 46bd mov sp, r7 + 800a0ee: bc80 pop {r7} + 800a0f0: 4770 bx lr + ... + +0800a0f4 : + */ +static DioIrqHandler RadioOnDioIrqCb; + +/* Exported functions ---------------------------------------------------------*/ +void SUBGRF_Init( DioIrqHandler dioIrq ) +{ + 800a0f4: b580 push {r7, lr} + 800a0f6: b084 sub sp, #16 + 800a0f8: af00 add r7, sp, #0 + 800a0fa: 6078 str r0, [r7, #4] + if ( dioIrq != NULL) + 800a0fc: 687b ldr r3, [r7, #4] + 800a0fe: 2b00 cmp r3, #0 + 800a100: d002 beq.n 800a108 + { + RadioOnDioIrqCb = dioIrq; + 800a102: 4a1d ldr r2, [pc, #116] ; (800a178 ) + 800a104: 687b ldr r3, [r7, #4] + 800a106: 6013 str r3, [r2, #0] + } + + RADIO_INIT(); + 800a108: f7f6 fd60 bl 8000bcc + + /* set default SMPS current drive to default*/ + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + 800a10c: 2002 movs r0, #2 + 800a10e: f001 f8ff bl 800b310 + + ImageCalibrated = false; + 800a112: 4b1a ldr r3, [pc, #104] ; (800a17c ) + 800a114: 2200 movs r2, #0 + 800a116: 701a strb r2, [r3, #0] + + SUBGRF_SetStandby( STDBY_RC ); + 800a118: 2000 movs r0, #0 + 800a11a: f000 f97d bl 800a418 + + // Initialize TCXO control + if (1U == RBI_IsTCXO() ) + 800a11e: f001 fd85 bl 800bc2c + 800a122: 4603 mov r3, r0 + 800a124: 2b01 cmp r3, #1 + 800a126: d10e bne.n 800a146 + { + SUBGRF_SetTcxoMode( TCXO_CTRL_VOLTAGE, RF_WAKEUP_TIME << 6 );// 100 ms + 800a128: 2140 movs r1, #64 ; 0x40 + 800a12a: 2001 movs r0, #1 + 800a12c: f000 fb82 bl 800a834 + SUBGRF_WriteRegister( REG_XTA_TRIM, 0x00 ); + 800a130: 2100 movs r1, #0 + 800a132: f640 1011 movw r0, #2321 ; 0x911 + 800a136: f000 fef3 bl 800af20 + + /*enable calibration for cut1.1 and later*/ + CalibrationParams_t calibParam; + calibParam.Value = 0x7F; + 800a13a: 237f movs r3, #127 ; 0x7f + 800a13c: 733b strb r3, [r7, #12] + SUBGRF_Calibrate( calibParam ); + 800a13e: 7b38 ldrb r0, [r7, #12] + 800a140: f000 fa8b bl 800a65a + 800a144: e009 b.n 800a15a + } + else + { + SUBGRF_WriteRegister( REG_XTA_TRIM, XTAL_DEFAULT_CAP_VALUE ); + 800a146: 2120 movs r1, #32 + 800a148: f640 1011 movw r0, #2321 ; 0x911 + 800a14c: f000 fee8 bl 800af20 + SUBGRF_WriteRegister( REG_XTB_TRIM, XTAL_DEFAULT_CAP_VALUE ); + 800a150: 2120 movs r1, #32 + 800a152: f640 1012 movw r0, #2322 ; 0x912 + 800a156: f000 fee3 bl 800af20 + } + + /* WORKAROUND - Trimming the output voltage power_ldo to 3.3V */ + SUBGRF_WriteRegister(REG_DRV_CTRL, 0x7 << 1); + 800a15a: 210e movs r1, #14 + 800a15c: f640 101f movw r0, #2335 ; 0x91f + 800a160: f000 fede bl 800af20 + + /* Init RF Switch */ + RBI_Init(); + 800a164: f001 fd46 bl 800bbf4 + + OperatingMode = MODE_STDBY_RC; + 800a168: 4b05 ldr r3, [pc, #20] ; (800a180 ) + 800a16a: 2201 movs r2, #1 + 800a16c: 701a strb r2, [r3, #0] +} + 800a16e: bf00 nop + 800a170: 3710 adds r7, #16 + 800a172: 46bd mov sp, r7 + 800a174: bd80 pop {r7, pc} + 800a176: bf00 nop + 800a178: 20000498 .word 0x20000498 + 800a17c: 20000494 .word 0x20000494 + 800a180: 2000048c .word 0x2000048c + +0800a184 : + +RadioOperatingModes_t SUBGRF_GetOperatingMode( void ) +{ + 800a184: b480 push {r7} + 800a186: af00 add r7, sp, #0 + return OperatingMode; + 800a188: 4b02 ldr r3, [pc, #8] ; (800a194 ) + 800a18a: 781b ldrb r3, [r3, #0] +} + 800a18c: 4618 mov r0, r3 + 800a18e: 46bd mov sp, r7 + 800a190: bc80 pop {r7} + 800a192: 4770 bx lr + 800a194: 2000048c .word 0x2000048c + +0800a198 : + +void SUBGRF_SetPayload( uint8_t *payload, uint8_t size ) +{ + 800a198: b580 push {r7, lr} + 800a19a: b082 sub sp, #8 + 800a19c: af00 add r7, sp, #0 + 800a19e: 6078 str r0, [r7, #4] + 800a1a0: 460b mov r3, r1 + 800a1a2: 70fb strb r3, [r7, #3] + SUBGRF_WriteBuffer( 0x00, payload, size ); + 800a1a4: 78fb ldrb r3, [r7, #3] + 800a1a6: 461a mov r2, r3 + 800a1a8: 6879 ldr r1, [r7, #4] + 800a1aa: 2000 movs r0, #0 + 800a1ac: f000 ff24 bl 800aff8 +} + 800a1b0: bf00 nop + 800a1b2: 3708 adds r7, #8 + 800a1b4: 46bd mov sp, r7 + 800a1b6: bd80 pop {r7, pc} + +0800a1b8 : + +uint8_t SUBGRF_GetPayload( uint8_t *buffer, uint8_t *size, uint8_t maxSize ) +{ + 800a1b8: b580 push {r7, lr} + 800a1ba: b086 sub sp, #24 + 800a1bc: af00 add r7, sp, #0 + 800a1be: 60f8 str r0, [r7, #12] + 800a1c0: 60b9 str r1, [r7, #8] + 800a1c2: 4613 mov r3, r2 + 800a1c4: 71fb strb r3, [r7, #7] + uint8_t offset = 0; + 800a1c6: 2300 movs r3, #0 + 800a1c8: 75fb strb r3, [r7, #23] + + SUBGRF_GetRxBufferStatus( size, &offset ); + 800a1ca: f107 0317 add.w r3, r7, #23 + 800a1ce: 4619 mov r1, r3 + 800a1d0: 68b8 ldr r0, [r7, #8] + 800a1d2: f000 fe27 bl 800ae24 + if( *size > maxSize ) + 800a1d6: 68bb ldr r3, [r7, #8] + 800a1d8: 781b ldrb r3, [r3, #0] + 800a1da: 79fa ldrb r2, [r7, #7] + 800a1dc: 429a cmp r2, r3 + 800a1de: d201 bcs.n 800a1e4 + { + return 1; + 800a1e0: 2301 movs r3, #1 + 800a1e2: e007 b.n 800a1f4 + } + SUBGRF_ReadBuffer( offset, buffer, *size ); + 800a1e4: 7df8 ldrb r0, [r7, #23] + 800a1e6: 68bb ldr r3, [r7, #8] + 800a1e8: 781b ldrb r3, [r3, #0] + 800a1ea: 461a mov r2, r3 + 800a1ec: 68f9 ldr r1, [r7, #12] + 800a1ee: f000 ff25 bl 800b03c + + return 0; + 800a1f2: 2300 movs r3, #0 +} + 800a1f4: 4618 mov r0, r3 + 800a1f6: 3718 adds r7, #24 + 800a1f8: 46bd mov sp, r7 + 800a1fa: bd80 pop {r7, pc} + +0800a1fc : + +void SUBGRF_SendPayload( uint8_t *payload, uint8_t size, uint32_t timeout) +{ + 800a1fc: b580 push {r7, lr} + 800a1fe: b084 sub sp, #16 + 800a200: af00 add r7, sp, #0 + 800a202: 60f8 str r0, [r7, #12] + 800a204: 460b mov r3, r1 + 800a206: 607a str r2, [r7, #4] + 800a208: 72fb strb r3, [r7, #11] + SUBGRF_SetPayload( payload, size ); + 800a20a: 7afb ldrb r3, [r7, #11] + 800a20c: 4619 mov r1, r3 + 800a20e: 68f8 ldr r0, [r7, #12] + 800a210: f7ff ffc2 bl 800a198 + SUBGRF_SetTx( timeout ); + 800a214: 6878 ldr r0, [r7, #4] + 800a216: f000 f91b bl 800a450 +} + 800a21a: bf00 nop + 800a21c: 3710 adds r7, #16 + 800a21e: 46bd mov sp, r7 + 800a220: bd80 pop {r7, pc} + +0800a222 : + +uint8_t SUBGRF_SetSyncWord( uint8_t *syncWord ) +{ + 800a222: b580 push {r7, lr} + 800a224: b082 sub sp, #8 + 800a226: af00 add r7, sp, #0 + 800a228: 6078 str r0, [r7, #4] + SUBGRF_WriteRegisters( REG_LR_SYNCWORDBASEADDRESS, syncWord, 8 ); + 800a22a: 2208 movs r2, #8 + 800a22c: 6879 ldr r1, [r7, #4] + 800a22e: f44f 60d8 mov.w r0, #1728 ; 0x6c0 + 800a232: f000 fe9d bl 800af70 + return 0; + 800a236: 2300 movs r3, #0 +} + 800a238: 4618 mov r0, r3 + 800a23a: 3708 adds r7, #8 + 800a23c: 46bd mov sp, r7 + 800a23e: bd80 pop {r7, pc} + +0800a240 : + +void SUBGRF_SetCrcSeed( uint16_t seed ) +{ + 800a240: b580 push {r7, lr} + 800a242: b084 sub sp, #16 + 800a244: af00 add r7, sp, #0 + 800a246: 4603 mov r3, r0 + 800a248: 80fb strh r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( seed >> 8 ) & 0xFF ); + 800a24a: 88fb ldrh r3, [r7, #6] + 800a24c: 0a1b lsrs r3, r3, #8 + 800a24e: b29b uxth r3, r3 + 800a250: b2db uxtb r3, r3 + 800a252: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( seed & 0xFF ); + 800a254: 88fb ldrh r3, [r7, #6] + 800a256: b2db uxtb r3, r3 + 800a258: 737b strb r3, [r7, #13] + + switch( SUBGRF_GetPacketType( ) ) + 800a25a: f000 fb6f bl 800a93c + 800a25e: 4603 mov r3, r0 + 800a260: 2b00 cmp r3, #0 + 800a262: d108 bne.n 800a276 + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCSEEDBASEADDR, buf, 2 ); + 800a264: f107 030c add.w r3, r7, #12 + 800a268: 2202 movs r2, #2 + 800a26a: 4619 mov r1, r3 + 800a26c: f240 60bc movw r0, #1724 ; 0x6bc + 800a270: f000 fe7e bl 800af70 + break; + 800a274: e000 b.n 800a278 + + default: + break; + 800a276: bf00 nop + } +} + 800a278: bf00 nop + 800a27a: 3710 adds r7, #16 + 800a27c: 46bd mov sp, r7 + 800a27e: bd80 pop {r7, pc} + +0800a280 : + +void SUBGRF_SetCrcPolynomial( uint16_t polynomial ) +{ + 800a280: b580 push {r7, lr} + 800a282: b084 sub sp, #16 + 800a284: af00 add r7, sp, #0 + 800a286: 4603 mov r3, r0 + 800a288: 80fb strh r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = ( uint8_t )( ( polynomial >> 8 ) & 0xFF ); + 800a28a: 88fb ldrh r3, [r7, #6] + 800a28c: 0a1b lsrs r3, r3, #8 + 800a28e: b29b uxth r3, r3 + 800a290: b2db uxtb r3, r3 + 800a292: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( polynomial & 0xFF ); + 800a294: 88fb ldrh r3, [r7, #6] + 800a296: b2db uxtb r3, r3 + 800a298: 737b strb r3, [r7, #13] + + switch( SUBGRF_GetPacketType( ) ) + 800a29a: f000 fb4f bl 800a93c + 800a29e: 4603 mov r3, r0 + 800a2a0: 2b00 cmp r3, #0 + 800a2a2: d108 bne.n 800a2b6 + { + case PACKET_TYPE_GFSK: + SUBGRF_WriteRegisters( REG_LR_CRCPOLYBASEADDR, buf, 2 ); + 800a2a4: f107 030c add.w r3, r7, #12 + 800a2a8: 2202 movs r2, #2 + 800a2aa: 4619 mov r1, r3 + 800a2ac: f240 60be movw r0, #1726 ; 0x6be + 800a2b0: f000 fe5e bl 800af70 + break; + 800a2b4: e000 b.n 800a2b8 + + default: + break; + 800a2b6: bf00 nop + } +} + 800a2b8: bf00 nop + 800a2ba: 3710 adds r7, #16 + 800a2bc: 46bd mov sp, r7 + 800a2be: bd80 pop {r7, pc} + +0800a2c0 : + +void SUBGRF_SetWhiteningSeed( uint16_t seed ) +{ + 800a2c0: b580 push {r7, lr} + 800a2c2: b084 sub sp, #16 + 800a2c4: af00 add r7, sp, #0 + 800a2c6: 4603 mov r3, r0 + 800a2c8: 80fb strh r3, [r7, #6] + uint8_t regValue = 0; + 800a2ca: 2300 movs r3, #0 + 800a2cc: 73fb strb r3, [r7, #15] + + switch( SUBGRF_GetPacketType( ) ) + 800a2ce: f000 fb35 bl 800a93c + 800a2d2: 4603 mov r3, r0 + 800a2d4: 2b00 cmp r3, #0 + 800a2d6: d121 bne.n 800a31c + { + case PACKET_TYPE_GFSK: + regValue = SUBGRF_ReadRegister( REG_LR_WHITSEEDBASEADDR_MSB ) & 0xFE; + 800a2d8: f44f 60d7 mov.w r0, #1720 ; 0x6b8 + 800a2dc: f000 fe34 bl 800af48 + 800a2e0: 4603 mov r3, r0 + 800a2e2: f023 0301 bic.w r3, r3, #1 + 800a2e6: 73fb strb r3, [r7, #15] + regValue = ( ( seed >> 8 ) & 0x01 ) | regValue; + 800a2e8: 88fb ldrh r3, [r7, #6] + 800a2ea: 0a1b lsrs r3, r3, #8 + 800a2ec: b29b uxth r3, r3 + 800a2ee: b25b sxtb r3, r3 + 800a2f0: f003 0301 and.w r3, r3, #1 + 800a2f4: b25a sxtb r2, r3 + 800a2f6: f997 300f ldrsb.w r3, [r7, #15] + 800a2fa: 4313 orrs r3, r2 + 800a2fc: b25b sxtb r3, r3 + 800a2fe: 73fb strb r3, [r7, #15] + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_MSB, regValue ); // only 1 bit. + 800a300: 7bfb ldrb r3, [r7, #15] + 800a302: 4619 mov r1, r3 + 800a304: f44f 60d7 mov.w r0, #1720 ; 0x6b8 + 800a308: f000 fe0a bl 800af20 + SUBGRF_WriteRegister( REG_LR_WHITSEEDBASEADDR_LSB, (uint8_t)seed ); + 800a30c: 88fb ldrh r3, [r7, #6] + 800a30e: b2db uxtb r3, r3 + 800a310: 4619 mov r1, r3 + 800a312: f240 60b9 movw r0, #1721 ; 0x6b9 + 800a316: f000 fe03 bl 800af20 + break; + 800a31a: e000 b.n 800a31e + + default: + break; + 800a31c: bf00 nop + } +} + 800a31e: bf00 nop + 800a320: 3710 adds r7, #16 + 800a322: 46bd mov sp, r7 + 800a324: bd80 pop {r7, pc} + +0800a326 : + +uint32_t SUBGRF_GetRandom( void ) +{ + 800a326: b580 push {r7, lr} + 800a328: b082 sub sp, #8 + 800a32a: af00 add r7, sp, #0 + uint32_t number = 0; + 800a32c: 2300 movs r3, #0 + 800a32e: 603b str r3, [r7, #0] + uint8_t regAnaLna = 0; + 800a330: 2300 movs r3, #0 + 800a332: 71fb strb r3, [r7, #7] + uint8_t regAnaMixer = 0; + 800a334: 2300 movs r3, #0 + 800a336: 71bb strb r3, [r7, #6] + + regAnaLna = SUBGRF_ReadRegister( REG_ANA_LNA ); + 800a338: f640 00e2 movw r0, #2274 ; 0x8e2 + 800a33c: f000 fe04 bl 800af48 + 800a340: 4603 mov r3, r0 + 800a342: 71fb strb r3, [r7, #7] + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna & ~( 1 << 0 ) ); + 800a344: 79fb ldrb r3, [r7, #7] + 800a346: f023 0301 bic.w r3, r3, #1 + 800a34a: b2db uxtb r3, r3 + 800a34c: 4619 mov r1, r3 + 800a34e: f640 00e2 movw r0, #2274 ; 0x8e2 + 800a352: f000 fde5 bl 800af20 + + regAnaMixer = SUBGRF_ReadRegister( REG_ANA_MIXER ); + 800a356: f640 00e5 movw r0, #2277 ; 0x8e5 + 800a35a: f000 fdf5 bl 800af48 + 800a35e: 4603 mov r3, r0 + 800a360: 71bb strb r3, [r7, #6] + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer & ~( 1 << 7 ) ); + 800a362: 79bb ldrb r3, [r7, #6] + 800a364: f003 037f and.w r3, r3, #127 ; 0x7f + 800a368: b2db uxtb r3, r3 + 800a36a: 4619 mov r1, r3 + 800a36c: f640 00e5 movw r0, #2277 ; 0x8e5 + 800a370: f000 fdd6 bl 800af20 + + // Set radio in continuous reception + SUBGRF_SetRx( 0xFFFFFF ); // Rx Continuous + 800a374: f06f 407f mvn.w r0, #4278190080 ; 0xff000000 + 800a378: f000 f88a bl 800a490 + + SUBGRF_ReadRegisters( RANDOM_NUMBER_GENERATORBASEADDR, ( uint8_t* )&number, 4 ); + 800a37c: 463b mov r3, r7 + 800a37e: 2204 movs r2, #4 + 800a380: 4619 mov r1, r3 + 800a382: f640 0019 movw r0, #2073 ; 0x819 + 800a386: f000 fe15 bl 800afb4 + + SUBGRF_SetStandby( STDBY_RC ); + 800a38a: 2000 movs r0, #0 + 800a38c: f000 f844 bl 800a418 + + SUBGRF_WriteRegister( REG_ANA_LNA, regAnaLna ); + 800a390: 79fb ldrb r3, [r7, #7] + 800a392: 4619 mov r1, r3 + 800a394: f640 00e2 movw r0, #2274 ; 0x8e2 + 800a398: f000 fdc2 bl 800af20 + SUBGRF_WriteRegister( REG_ANA_MIXER, regAnaMixer ); + 800a39c: 79bb ldrb r3, [r7, #6] + 800a39e: 4619 mov r1, r3 + 800a3a0: f640 00e5 movw r0, #2277 ; 0x8e5 + 800a3a4: f000 fdbc bl 800af20 + + return number; + 800a3a8: 683b ldr r3, [r7, #0] +} + 800a3aa: 4618 mov r0, r3 + 800a3ac: 3708 adds r7, #8 + 800a3ae: 46bd mov sp, r7 + 800a3b0: bd80 pop {r7, pc} + ... + +0800a3b4 : + +void SUBGRF_SetSleep( SleepParams_t sleepConfig ) +{ + 800a3b4: b580 push {r7, lr} + 800a3b6: b084 sub sp, #16 + 800a3b8: af00 add r7, sp, #0 + 800a3ba: 7138 strb r0, [r7, #4] + /* switch the antenna OFF by SW */ + RBI_ConfigRFSwitch(RBI_SWITCH_OFF); + 800a3bc: 2000 movs r0, #0 + 800a3be: f001 fc20 bl 800bc02 + + Radio_SMPS_Set(SMPS_DRIVE_SETTING_DEFAULT); + 800a3c2: 2002 movs r0, #2 + 800a3c4: f000 ffa4 bl 800b310 + + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 800a3c8: 793b ldrb r3, [r7, #4] + 800a3ca: f3c3 0380 ubfx r3, r3, #2, #1 + 800a3ce: b2db uxtb r3, r3 + 800a3d0: 009b lsls r3, r3, #2 + 800a3d2: b25a sxtb r2, r3 + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + 800a3d4: 793b ldrb r3, [r7, #4] + 800a3d6: f3c3 0340 ubfx r3, r3, #1, #1 + 800a3da: b2db uxtb r3, r3 + 800a3dc: 005b lsls r3, r3, #1 + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 800a3de: b25b sxtb r3, r3 + 800a3e0: 4313 orrs r3, r2 + 800a3e2: b25a sxtb r2, r3 + ( ( uint8_t )sleepConfig.Fields.WakeUpRTC ) ); + 800a3e4: 793b ldrb r3, [r7, #4] + 800a3e6: f3c3 0300 ubfx r3, r3, #0, #1 + 800a3ea: b2db uxtb r3, r3 + 800a3ec: b25b sxtb r3, r3 + ( ( uint8_t )sleepConfig.Fields.Reset << 1 ) | + 800a3ee: 4313 orrs r3, r2 + 800a3f0: b25b sxtb r3, r3 + 800a3f2: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )sleepConfig.Fields.WarmStart << 2 ) | + 800a3f4: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_SLEEP, &value, 1 ); + 800a3f6: f107 030f add.w r3, r7, #15 + 800a3fa: 2201 movs r2, #1 + 800a3fc: 4619 mov r1, r3 + 800a3fe: 2084 movs r0, #132 ; 0x84 + 800a400: f000 fe3e bl 800b080 + OperatingMode = MODE_SLEEP; + 800a404: 4b03 ldr r3, [pc, #12] ; (800a414 ) + 800a406: 2200 movs r2, #0 + 800a408: 701a strb r2, [r3, #0] +} + 800a40a: bf00 nop + 800a40c: 3710 adds r7, #16 + 800a40e: 46bd mov sp, r7 + 800a410: bd80 pop {r7, pc} + 800a412: bf00 nop + 800a414: 2000048c .word 0x2000048c + +0800a418 : + +void SUBGRF_SetStandby( RadioStandbyModes_t standbyConfig ) +{ + 800a418: b580 push {r7, lr} + 800a41a: b082 sub sp, #8 + 800a41c: af00 add r7, sp, #0 + 800a41e: 4603 mov r3, r0 + 800a420: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_STANDBY, ( uint8_t* )&standbyConfig, 1 ); + 800a422: 1dfb adds r3, r7, #7 + 800a424: 2201 movs r2, #1 + 800a426: 4619 mov r1, r3 + 800a428: 2080 movs r0, #128 ; 0x80 + 800a42a: f000 fe29 bl 800b080 + if( standbyConfig == STDBY_RC ) + 800a42e: 79fb ldrb r3, [r7, #7] + 800a430: 2b00 cmp r3, #0 + 800a432: d103 bne.n 800a43c + { + OperatingMode = MODE_STDBY_RC; + 800a434: 4b05 ldr r3, [pc, #20] ; (800a44c ) + 800a436: 2201 movs r2, #1 + 800a438: 701a strb r2, [r3, #0] + } + else + { + OperatingMode = MODE_STDBY_XOSC; + } +} + 800a43a: e002 b.n 800a442 + OperatingMode = MODE_STDBY_XOSC; + 800a43c: 4b03 ldr r3, [pc, #12] ; (800a44c ) + 800a43e: 2202 movs r2, #2 + 800a440: 701a strb r2, [r3, #0] +} + 800a442: bf00 nop + 800a444: 3708 adds r7, #8 + 800a446: 46bd mov sp, r7 + 800a448: bd80 pop {r7, pc} + 800a44a: bf00 nop + 800a44c: 2000048c .word 0x2000048c + +0800a450 : + SUBGRF_WriteCommand( RADIO_SET_FS, 0, 0 ); + OperatingMode = MODE_FS; +} + +void SUBGRF_SetTx( uint32_t timeout ) +{ + 800a450: b580 push {r7, lr} + 800a452: b084 sub sp, #16 + 800a454: af00 add r7, sp, #0 + 800a456: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_TX; + 800a458: 4b0c ldr r3, [pc, #48] ; (800a48c ) + 800a45a: 2204 movs r2, #4 + 800a45c: 701a strb r2, [r3, #0] + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 800a45e: 687b ldr r3, [r7, #4] + 800a460: 0c1b lsrs r3, r3, #16 + 800a462: b2db uxtb r3, r3 + 800a464: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800a466: 687b ldr r3, [r7, #4] + 800a468: 0a1b lsrs r3, r3, #8 + 800a46a: b2db uxtb r3, r3 + 800a46c: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 800a46e: 687b ldr r3, [r7, #4] + 800a470: b2db uxtb r3, r3 + 800a472: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_TX, buf, 3 ); + 800a474: f107 030c add.w r3, r7, #12 + 800a478: 2203 movs r2, #3 + 800a47a: 4619 mov r1, r3 + 800a47c: 2083 movs r0, #131 ; 0x83 + 800a47e: f000 fdff bl 800b080 +} + 800a482: bf00 nop + 800a484: 3710 adds r7, #16 + 800a486: 46bd mov sp, r7 + 800a488: bd80 pop {r7, pc} + 800a48a: bf00 nop + 800a48c: 2000048c .word 0x2000048c + +0800a490 : + +void SUBGRF_SetRx( uint32_t timeout ) +{ + 800a490: b580 push {r7, lr} + 800a492: b084 sub sp, #16 + 800a494: af00 add r7, sp, #0 + 800a496: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_RX; + 800a498: 4b0c ldr r3, [pc, #48] ; (800a4cc ) + 800a49a: 2205 movs r2, #5 + 800a49c: 701a strb r2, [r3, #0] + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 800a49e: 687b ldr r3, [r7, #4] + 800a4a0: 0c1b lsrs r3, r3, #16 + 800a4a2: b2db uxtb r3, r3 + 800a4a4: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800a4a6: 687b ldr r3, [r7, #4] + 800a4a8: 0a1b lsrs r3, r3, #8 + 800a4aa: b2db uxtb r3, r3 + 800a4ac: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 800a4ae: 687b ldr r3, [r7, #4] + 800a4b0: b2db uxtb r3, r3 + 800a4b2: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); + 800a4b4: f107 030c add.w r3, r7, #12 + 800a4b8: 2203 movs r2, #3 + 800a4ba: 4619 mov r1, r3 + 800a4bc: 2082 movs r0, #130 ; 0x82 + 800a4be: f000 fddf bl 800b080 +} + 800a4c2: bf00 nop + 800a4c4: 3710 adds r7, #16 + 800a4c6: 46bd mov sp, r7 + 800a4c8: bd80 pop {r7, pc} + 800a4ca: bf00 nop + 800a4cc: 2000048c .word 0x2000048c + +0800a4d0 : + +void SUBGRF_SetRxBoosted( uint32_t timeout ) +{ + 800a4d0: b580 push {r7, lr} + 800a4d2: b084 sub sp, #16 + 800a4d4: af00 add r7, sp, #0 + 800a4d6: 6078 str r0, [r7, #4] + uint8_t buf[3]; + + OperatingMode = MODE_RX; + 800a4d8: 4b0e ldr r3, [pc, #56] ; (800a514 ) + 800a4da: 2205 movs r2, #5 + 800a4dc: 701a strb r2, [r3, #0] + + SUBGRF_WriteRegister( REG_RX_GAIN, 0x97 ); // max LNA gain, increase current by ~2mA for around ~3dB in sensitivity + 800a4de: 2197 movs r1, #151 ; 0x97 + 800a4e0: f640 00ac movw r0, #2220 ; 0x8ac + 800a4e4: f000 fd1c bl 800af20 + + buf[0] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 800a4e8: 687b ldr r3, [r7, #4] + 800a4ea: 0c1b lsrs r3, r3, #16 + 800a4ec: b2db uxtb r3, r3 + 800a4ee: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800a4f0: 687b ldr r3, [r7, #4] + 800a4f2: 0a1b lsrs r3, r3, #8 + 800a4f4: b2db uxtb r3, r3 + 800a4f6: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( timeout & 0xFF ); + 800a4f8: 687b ldr r3, [r7, #4] + 800a4fa: b2db uxtb r3, r3 + 800a4fc: 73bb strb r3, [r7, #14] + SUBGRF_WriteCommand( RADIO_SET_RX, buf, 3 ); + 800a4fe: f107 030c add.w r3, r7, #12 + 800a502: 2203 movs r2, #3 + 800a504: 4619 mov r1, r3 + 800a506: 2082 movs r0, #130 ; 0x82 + 800a508: f000 fdba bl 800b080 +} + 800a50c: bf00 nop + 800a50e: 3710 adds r7, #16 + 800a510: 46bd mov sp, r7 + 800a512: bd80 pop {r7, pc} + 800a514: 2000048c .word 0x2000048c + +0800a518 : + +void SUBGRF_SetRxDutyCycle( uint32_t rxTime, uint32_t sleepTime ) +{ + 800a518: b580 push {r7, lr} + 800a51a: b084 sub sp, #16 + 800a51c: af00 add r7, sp, #0 + 800a51e: 6078 str r0, [r7, #4] + 800a520: 6039 str r1, [r7, #0] + uint8_t buf[6]; + + buf[0] = ( uint8_t )( ( rxTime >> 16 ) & 0xFF ); + 800a522: 687b ldr r3, [r7, #4] + 800a524: 0c1b lsrs r3, r3, #16 + 800a526: b2db uxtb r3, r3 + 800a528: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( ( rxTime >> 8 ) & 0xFF ); + 800a52a: 687b ldr r3, [r7, #4] + 800a52c: 0a1b lsrs r3, r3, #8 + 800a52e: b2db uxtb r3, r3 + 800a530: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( rxTime & 0xFF ); + 800a532: 687b ldr r3, [r7, #4] + 800a534: b2db uxtb r3, r3 + 800a536: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( ( sleepTime >> 16 ) & 0xFF ); + 800a538: 683b ldr r3, [r7, #0] + 800a53a: 0c1b lsrs r3, r3, #16 + 800a53c: b2db uxtb r3, r3 + 800a53e: 72fb strb r3, [r7, #11] + buf[4] = ( uint8_t )( ( sleepTime >> 8 ) & 0xFF ); + 800a540: 683b ldr r3, [r7, #0] + 800a542: 0a1b lsrs r3, r3, #8 + 800a544: b2db uxtb r3, r3 + 800a546: 733b strb r3, [r7, #12] + buf[5] = ( uint8_t )( sleepTime & 0xFF ); + 800a548: 683b ldr r3, [r7, #0] + 800a54a: b2db uxtb r3, r3 + 800a54c: 737b strb r3, [r7, #13] + SUBGRF_WriteCommand( RADIO_SET_RXDUTYCYCLE, buf, 6 ); + 800a54e: f107 0308 add.w r3, r7, #8 + 800a552: 2206 movs r2, #6 + 800a554: 4619 mov r1, r3 + 800a556: 2094 movs r0, #148 ; 0x94 + 800a558: f000 fd92 bl 800b080 + OperatingMode = MODE_RX_DC; + 800a55c: 4b03 ldr r3, [pc, #12] ; (800a56c ) + 800a55e: 2206 movs r2, #6 + 800a560: 701a strb r2, [r3, #0] +} + 800a562: bf00 nop + 800a564: 3710 adds r7, #16 + 800a566: 46bd mov sp, r7 + 800a568: bd80 pop {r7, pc} + 800a56a: bf00 nop + 800a56c: 2000048c .word 0x2000048c + +0800a570 : + +void SUBGRF_SetCad( void ) +{ + 800a570: b580 push {r7, lr} + 800a572: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_CAD, 0, 0 ); + 800a574: 2200 movs r2, #0 + 800a576: 2100 movs r1, #0 + 800a578: 20c5 movs r0, #197 ; 0xc5 + 800a57a: f000 fd81 bl 800b080 + OperatingMode = MODE_CAD; + 800a57e: 4b02 ldr r3, [pc, #8] ; (800a588 ) + 800a580: 2207 movs r2, #7 + 800a582: 701a strb r2, [r3, #0] +} + 800a584: bf00 nop + 800a586: bd80 pop {r7, pc} + 800a588: 2000048c .word 0x2000048c + +0800a58c : + +void SUBGRF_SetTxContinuousWave( void ) +{ + 800a58c: b580 push {r7, lr} + 800a58e: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSWAVE, 0, 0 ); + 800a590: 2200 movs r2, #0 + 800a592: 2100 movs r1, #0 + 800a594: 20d1 movs r0, #209 ; 0xd1 + 800a596: f000 fd73 bl 800b080 +} + 800a59a: bf00 nop + 800a59c: bd80 pop {r7, pc} + +0800a59e : + +void SUBGRF_SetTxInfinitePreamble( void ) +{ + 800a59e: b580 push {r7, lr} + 800a5a0: af00 add r7, sp, #0 + SUBGRF_WriteCommand( RADIO_SET_TXCONTINUOUSPREAMBLE, 0, 0 ); + 800a5a2: 2200 movs r2, #0 + 800a5a4: 2100 movs r1, #0 + 800a5a6: 20d2 movs r0, #210 ; 0xd2 + 800a5a8: f000 fd6a bl 800b080 +} + 800a5ac: bf00 nop + 800a5ae: bd80 pop {r7, pc} + +0800a5b0 : + +void SUBGRF_SetStopRxTimerOnPreambleDetect( bool enable ) +{ + 800a5b0: b580 push {r7, lr} + 800a5b2: b082 sub sp, #8 + 800a5b4: af00 add r7, sp, #0 + 800a5b6: 4603 mov r3, r0 + 800a5b8: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_STOPRXTIMERONPREAMBLE, ( uint8_t* )&enable, 1 ); + 800a5ba: 1dfb adds r3, r7, #7 + 800a5bc: 2201 movs r2, #1 + 800a5be: 4619 mov r1, r3 + 800a5c0: 209f movs r0, #159 ; 0x9f + 800a5c2: f000 fd5d bl 800b080 +} + 800a5c6: bf00 nop + 800a5c8: 3708 adds r7, #8 + 800a5ca: 46bd mov sp, r7 + 800a5cc: bd80 pop {r7, pc} + +0800a5ce : + +void SUBGRF_SetLoRaSymbNumTimeout( uint8_t symbNum ) +{ + 800a5ce: b580 push {r7, lr} + 800a5d0: b084 sub sp, #16 + 800a5d2: af00 add r7, sp, #0 + 800a5d4: 4603 mov r3, r0 + 800a5d6: 71fb strb r3, [r7, #7] + SUBGRF_WriteCommand( RADIO_SET_LORASYMBTIMEOUT, &symbNum, 1 ); + 800a5d8: 1dfb adds r3, r7, #7 + 800a5da: 2201 movs r2, #1 + 800a5dc: 4619 mov r1, r3 + 800a5de: 20a0 movs r0, #160 ; 0xa0 + 800a5e0: f000 fd4e bl 800b080 + + if( symbNum >= 64 ) + 800a5e4: 79fb ldrb r3, [r7, #7] + 800a5e6: 2b3f cmp r3, #63 ; 0x3f + 800a5e8: d91c bls.n 800a624 + { + uint8_t mant = symbNum >> 1; + 800a5ea: 79fb ldrb r3, [r7, #7] + 800a5ec: 085b lsrs r3, r3, #1 + 800a5ee: 73fb strb r3, [r7, #15] + uint8_t exp = 0; + 800a5f0: 2300 movs r3, #0 + 800a5f2: 73bb strb r3, [r7, #14] + uint8_t reg = 0; + 800a5f4: 2300 movs r3, #0 + 800a5f6: 737b strb r3, [r7, #13] + + while( mant > 31 ) + 800a5f8: e005 b.n 800a606 + { + mant >>= 2; + 800a5fa: 7bfb ldrb r3, [r7, #15] + 800a5fc: 089b lsrs r3, r3, #2 + 800a5fe: 73fb strb r3, [r7, #15] + exp++; + 800a600: 7bbb ldrb r3, [r7, #14] + 800a602: 3301 adds r3, #1 + 800a604: 73bb strb r3, [r7, #14] + while( mant > 31 ) + 800a606: 7bfb ldrb r3, [r7, #15] + 800a608: 2b1f cmp r3, #31 + 800a60a: d8f6 bhi.n 800a5fa + } + + reg = exp + ( mant << 3 ); + 800a60c: 7bfb ldrb r3, [r7, #15] + 800a60e: 00db lsls r3, r3, #3 + 800a610: b2da uxtb r2, r3 + 800a612: 7bbb ldrb r3, [r7, #14] + 800a614: 4413 add r3, r2 + 800a616: 737b strb r3, [r7, #13] + SUBGRF_WriteRegister( REG_LR_SYNCH_TIMEOUT, reg ); + 800a618: 7b7b ldrb r3, [r7, #13] + 800a61a: 4619 mov r1, r3 + 800a61c: f240 7006 movw r0, #1798 ; 0x706 + 800a620: f000 fc7e bl 800af20 + } +} + 800a624: bf00 nop + 800a626: 3710 adds r7, #16 + 800a628: 46bd mov sp, r7 + 800a62a: bd80 pop {r7, pc} + +0800a62c : + +void SUBGRF_SetRegulatorMode( void ) +{ + 800a62c: b580 push {r7, lr} + 800a62e: b082 sub sp, #8 + 800a630: af00 add r7, sp, #0 + RadioRegulatorMode_t mode; + + if ( ( 1UL == RBI_IsDCDC() ) && ( 1UL == DCDC_ENABLE ) ) + 800a632: f001 fb02 bl 800bc3a + 800a636: 4603 mov r3, r0 + 800a638: 2b01 cmp r3, #1 + 800a63a: d102 bne.n 800a642 + { + mode = USE_DCDC ; + 800a63c: 2301 movs r3, #1 + 800a63e: 71fb strb r3, [r7, #7] + 800a640: e001 b.n 800a646 + } + else + { + mode = USE_LDO ; + 800a642: 2300 movs r3, #0 + 800a644: 71fb strb r3, [r7, #7] + } + SUBGRF_WriteCommand( RADIO_SET_REGULATORMODE, ( uint8_t* )&mode, 1 ); + 800a646: 1dfb adds r3, r7, #7 + 800a648: 2201 movs r2, #1 + 800a64a: 4619 mov r1, r3 + 800a64c: 2096 movs r0, #150 ; 0x96 + 800a64e: f000 fd17 bl 800b080 +} + 800a652: bf00 nop + 800a654: 3708 adds r7, #8 + 800a656: 46bd mov sp, r7 + 800a658: bd80 pop {r7, pc} + +0800a65a : + +void SUBGRF_Calibrate( CalibrationParams_t calibParam ) +{ + 800a65a: b580 push {r7, lr} + 800a65c: b084 sub sp, #16 + 800a65e: af00 add r7, sp, #0 + 800a660: 7138 strb r0, [r7, #4] + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 800a662: 793b ldrb r3, [r7, #4] + 800a664: f3c3 1380 ubfx r3, r3, #6, #1 + 800a668: b2db uxtb r3, r3 + 800a66a: 019b lsls r3, r3, #6 + 800a66c: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + 800a66e: 793b ldrb r3, [r7, #4] + 800a670: f3c3 1340 ubfx r3, r3, #5, #1 + 800a674: b2db uxtb r3, r3 + 800a676: 015b lsls r3, r3, #5 + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 800a678: b25b sxtb r3, r3 + 800a67a: 4313 orrs r3, r2 + 800a67c: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + 800a67e: 793b ldrb r3, [r7, #4] + 800a680: f3c3 1300 ubfx r3, r3, #4, #1 + 800a684: b2db uxtb r3, r3 + 800a686: 011b lsls r3, r3, #4 + ( ( uint8_t )calibParam.Fields.ADCBulkPEnable << 5 ) | + 800a688: b25b sxtb r3, r3 + 800a68a: 4313 orrs r3, r2 + 800a68c: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + 800a68e: 793b ldrb r3, [r7, #4] + 800a690: f3c3 03c0 ubfx r3, r3, #3, #1 + 800a694: b2db uxtb r3, r3 + 800a696: 00db lsls r3, r3, #3 + ( ( uint8_t )calibParam.Fields.ADCBulkNEnable << 4 ) | + 800a698: b25b sxtb r3, r3 + 800a69a: 4313 orrs r3, r2 + 800a69c: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + 800a69e: 793b ldrb r3, [r7, #4] + 800a6a0: f3c3 0380 ubfx r3, r3, #2, #1 + 800a6a4: b2db uxtb r3, r3 + 800a6a6: 009b lsls r3, r3, #2 + ( ( uint8_t )calibParam.Fields.ADCPulseEnable << 3 ) | + 800a6a8: b25b sxtb r3, r3 + 800a6aa: 4313 orrs r3, r2 + 800a6ac: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + 800a6ae: 793b ldrb r3, [r7, #4] + 800a6b0: f3c3 0340 ubfx r3, r3, #1, #1 + 800a6b4: b2db uxtb r3, r3 + 800a6b6: 005b lsls r3, r3, #1 + ( ( uint8_t )calibParam.Fields.PLLEnable << 2 ) | + 800a6b8: b25b sxtb r3, r3 + 800a6ba: 4313 orrs r3, r2 + 800a6bc: b25a sxtb r2, r3 + ( ( uint8_t )calibParam.Fields.RC64KEnable ) ); + 800a6be: 793b ldrb r3, [r7, #4] + 800a6c0: f3c3 0300 ubfx r3, r3, #0, #1 + 800a6c4: b2db uxtb r3, r3 + 800a6c6: b25b sxtb r3, r3 + ( ( uint8_t )calibParam.Fields.RC13MEnable << 1 ) | + 800a6c8: 4313 orrs r3, r2 + 800a6ca: b25b sxtb r3, r3 + 800a6cc: b2db uxtb r3, r3 + uint8_t value = ( ( ( uint8_t )calibParam.Fields.ImgEnable << 6 ) | + 800a6ce: 73fb strb r3, [r7, #15] + + SUBGRF_WriteCommand( RADIO_CALIBRATE, &value, 1 ); + 800a6d0: f107 030f add.w r3, r7, #15 + 800a6d4: 2201 movs r2, #1 + 800a6d6: 4619 mov r1, r3 + 800a6d8: 2089 movs r0, #137 ; 0x89 + 800a6da: f000 fcd1 bl 800b080 +} + 800a6de: bf00 nop + 800a6e0: 3710 adds r7, #16 + 800a6e2: 46bd mov sp, r7 + 800a6e4: bd80 pop {r7, pc} + ... + +0800a6e8 : + +void SUBGRF_CalibrateImage( uint32_t freq ) +{ + 800a6e8: b580 push {r7, lr} + 800a6ea: b084 sub sp, #16 + 800a6ec: af00 add r7, sp, #0 + 800a6ee: 6078 str r0, [r7, #4] + uint8_t calFreq[2]; + + if( freq > 900000000 ) + 800a6f0: 687b ldr r3, [r7, #4] + 800a6f2: 4a1d ldr r2, [pc, #116] ; (800a768 ) + 800a6f4: 4293 cmp r3, r2 + 800a6f6: d904 bls.n 800a702 + { + calFreq[0] = 0xE1; + 800a6f8: 23e1 movs r3, #225 ; 0xe1 + 800a6fa: 733b strb r3, [r7, #12] + calFreq[1] = 0xE9; + 800a6fc: 23e9 movs r3, #233 ; 0xe9 + 800a6fe: 737b strb r3, [r7, #13] + 800a700: e027 b.n 800a752 + } + else if( freq > 850000000 ) + 800a702: 687b ldr r3, [r7, #4] + 800a704: 4a19 ldr r2, [pc, #100] ; (800a76c ) + 800a706: 4293 cmp r3, r2 + 800a708: d904 bls.n 800a714 + { + calFreq[0] = 0xD7; + 800a70a: 23d7 movs r3, #215 ; 0xd7 + 800a70c: 733b strb r3, [r7, #12] + calFreq[1] = 0xDB; + 800a70e: 23db movs r3, #219 ; 0xdb + 800a710: 737b strb r3, [r7, #13] + 800a712: e01e b.n 800a752 + } + else if( freq > 770000000 ) + 800a714: 687b ldr r3, [r7, #4] + 800a716: 4a16 ldr r2, [pc, #88] ; (800a770 ) + 800a718: 4293 cmp r3, r2 + 800a71a: d904 bls.n 800a726 + { + calFreq[0] = 0xC1; + 800a71c: 23c1 movs r3, #193 ; 0xc1 + 800a71e: 733b strb r3, [r7, #12] + calFreq[1] = 0xC5; + 800a720: 23c5 movs r3, #197 ; 0xc5 + 800a722: 737b strb r3, [r7, #13] + 800a724: e015 b.n 800a752 + } + else if( freq > 460000000 ) + 800a726: 687b ldr r3, [r7, #4] + 800a728: 4a12 ldr r2, [pc, #72] ; (800a774 ) + 800a72a: 4293 cmp r3, r2 + 800a72c: d904 bls.n 800a738 + { + calFreq[0] = 0x75; + 800a72e: 2375 movs r3, #117 ; 0x75 + 800a730: 733b strb r3, [r7, #12] + calFreq[1] = 0x81; + 800a732: 2381 movs r3, #129 ; 0x81 + 800a734: 737b strb r3, [r7, #13] + 800a736: e00c b.n 800a752 + } + else if( freq > 425000000 ) + 800a738: 687b ldr r3, [r7, #4] + 800a73a: 4a0f ldr r2, [pc, #60] ; (800a778 ) + 800a73c: 4293 cmp r3, r2 + 800a73e: d904 bls.n 800a74a + { + calFreq[0] = 0x6B; + 800a740: 236b movs r3, #107 ; 0x6b + 800a742: 733b strb r3, [r7, #12] + calFreq[1] = 0x6F; + 800a744: 236f movs r3, #111 ; 0x6f + 800a746: 737b strb r3, [r7, #13] + 800a748: e003 b.n 800a752 + } + else /* freq <= 425000000*/ + { + /* [ 156MHz - 171MHz ] */ + calFreq[0] = 0x29; + 800a74a: 2329 movs r3, #41 ; 0x29 + 800a74c: 733b strb r3, [r7, #12] + calFreq[1] = 0x2B ; + 800a74e: 232b movs r3, #43 ; 0x2b + 800a750: 737b strb r3, [r7, #13] + } + SUBGRF_WriteCommand( RADIO_CALIBRATEIMAGE, calFreq, 2 ); + 800a752: f107 030c add.w r3, r7, #12 + 800a756: 2202 movs r2, #2 + 800a758: 4619 mov r1, r3 + 800a75a: 2098 movs r0, #152 ; 0x98 + 800a75c: f000 fc90 bl 800b080 +} + 800a760: bf00 nop + 800a762: 3710 adds r7, #16 + 800a764: 46bd mov sp, r7 + 800a766: bd80 pop {r7, pc} + 800a768: 35a4e900 .word 0x35a4e900 + 800a76c: 32a9f880 .word 0x32a9f880 + 800a770: 2de54480 .word 0x2de54480 + 800a774: 1b6b0b00 .word 0x1b6b0b00 + 800a778: 1954fc40 .word 0x1954fc40 + +0800a77c : + +void SUBGRF_SetPaConfig( uint8_t paDutyCycle, uint8_t hpMax, uint8_t deviceSel, uint8_t paLut ) +{ + 800a77c: b590 push {r4, r7, lr} + 800a77e: b085 sub sp, #20 + 800a780: af00 add r7, sp, #0 + 800a782: 4604 mov r4, r0 + 800a784: 4608 mov r0, r1 + 800a786: 4611 mov r1, r2 + 800a788: 461a mov r2, r3 + 800a78a: 4623 mov r3, r4 + 800a78c: 71fb strb r3, [r7, #7] + 800a78e: 4603 mov r3, r0 + 800a790: 71bb strb r3, [r7, #6] + 800a792: 460b mov r3, r1 + 800a794: 717b strb r3, [r7, #5] + 800a796: 4613 mov r3, r2 + 800a798: 713b strb r3, [r7, #4] + uint8_t buf[4]; + + buf[0] = paDutyCycle; + 800a79a: 79fb ldrb r3, [r7, #7] + 800a79c: 733b strb r3, [r7, #12] + buf[1] = hpMax; + 800a79e: 79bb ldrb r3, [r7, #6] + 800a7a0: 737b strb r3, [r7, #13] + buf[2] = deviceSel; + 800a7a2: 797b ldrb r3, [r7, #5] + 800a7a4: 73bb strb r3, [r7, #14] + buf[3] = paLut; + 800a7a6: 793b ldrb r3, [r7, #4] + 800a7a8: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_PACONFIG, buf, 4 ); + 800a7aa: f107 030c add.w r3, r7, #12 + 800a7ae: 2204 movs r2, #4 + 800a7b0: 4619 mov r1, r3 + 800a7b2: 2095 movs r0, #149 ; 0x95 + 800a7b4: f000 fc64 bl 800b080 +} + 800a7b8: bf00 nop + 800a7ba: 3714 adds r7, #20 + 800a7bc: 46bd mov sp, r7 + 800a7be: bd90 pop {r4, r7, pc} + +0800a7c0 : +{ + SUBGRF_WriteCommand( RADIO_SET_TXFALLBACKMODE, &fallbackMode, 1 ); +} + +void SUBGRF_SetDioIrqParams( uint16_t irqMask, uint16_t dio1Mask, uint16_t dio2Mask, uint16_t dio3Mask ) +{ + 800a7c0: b590 push {r4, r7, lr} + 800a7c2: b085 sub sp, #20 + 800a7c4: af00 add r7, sp, #0 + 800a7c6: 4604 mov r4, r0 + 800a7c8: 4608 mov r0, r1 + 800a7ca: 4611 mov r1, r2 + 800a7cc: 461a mov r2, r3 + 800a7ce: 4623 mov r3, r4 + 800a7d0: 80fb strh r3, [r7, #6] + 800a7d2: 4603 mov r3, r0 + 800a7d4: 80bb strh r3, [r7, #4] + 800a7d6: 460b mov r3, r1 + 800a7d8: 807b strh r3, [r7, #2] + 800a7da: 4613 mov r3, r2 + 800a7dc: 803b strh r3, [r7, #0] + uint8_t buf[8]; + + buf[0] = ( uint8_t )( ( irqMask >> 8 ) & 0x00FF ); + 800a7de: 88fb ldrh r3, [r7, #6] + 800a7e0: 0a1b lsrs r3, r3, #8 + 800a7e2: b29b uxth r3, r3 + 800a7e4: b2db uxtb r3, r3 + 800a7e6: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( irqMask & 0x00FF ); + 800a7e8: 88fb ldrh r3, [r7, #6] + 800a7ea: b2db uxtb r3, r3 + 800a7ec: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( ( dio1Mask >> 8 ) & 0x00FF ); + 800a7ee: 88bb ldrh r3, [r7, #4] + 800a7f0: 0a1b lsrs r3, r3, #8 + 800a7f2: b29b uxth r3, r3 + 800a7f4: b2db uxtb r3, r3 + 800a7f6: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( dio1Mask & 0x00FF ); + 800a7f8: 88bb ldrh r3, [r7, #4] + 800a7fa: b2db uxtb r3, r3 + 800a7fc: 72fb strb r3, [r7, #11] + buf[4] = ( uint8_t )( ( dio2Mask >> 8 ) & 0x00FF ); + 800a7fe: 887b ldrh r3, [r7, #2] + 800a800: 0a1b lsrs r3, r3, #8 + 800a802: b29b uxth r3, r3 + 800a804: b2db uxtb r3, r3 + 800a806: 733b strb r3, [r7, #12] + buf[5] = ( uint8_t )( dio2Mask & 0x00FF ); + 800a808: 887b ldrh r3, [r7, #2] + 800a80a: b2db uxtb r3, r3 + 800a80c: 737b strb r3, [r7, #13] + buf[6] = ( uint8_t )( ( dio3Mask >> 8 ) & 0x00FF ); + 800a80e: 883b ldrh r3, [r7, #0] + 800a810: 0a1b lsrs r3, r3, #8 + 800a812: b29b uxth r3, r3 + 800a814: b2db uxtb r3, r3 + 800a816: 73bb strb r3, [r7, #14] + buf[7] = ( uint8_t )( dio3Mask & 0x00FF ); + 800a818: 883b ldrh r3, [r7, #0] + 800a81a: b2db uxtb r3, r3 + 800a81c: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_CFG_DIOIRQ, buf, 8 ); + 800a81e: f107 0308 add.w r3, r7, #8 + 800a822: 2208 movs r2, #8 + 800a824: 4619 mov r1, r3 + 800a826: 2008 movs r0, #8 + 800a828: f000 fc2a bl 800b080 +} + 800a82c: bf00 nop + 800a82e: 3714 adds r7, #20 + 800a830: 46bd mov sp, r7 + 800a832: bd90 pop {r4, r7, pc} + +0800a834 : + SUBGRF_ReadCommand( RADIO_GET_IRQSTATUS, irqStatus, 2 ); + return ( irqStatus[0] << 8 ) | irqStatus[1]; +} + +void SUBGRF_SetTcxoMode (RadioTcxoCtrlVoltage_t tcxoVoltage, uint32_t timeout ) +{ + 800a834: b580 push {r7, lr} + 800a836: b084 sub sp, #16 + 800a838: af00 add r7, sp, #0 + 800a83a: 4603 mov r3, r0 + 800a83c: 6039 str r1, [r7, #0] + 800a83e: 71fb strb r3, [r7, #7] + uint8_t buf[4]; + + buf[0] = tcxoVoltage & 0x07; + 800a840: 79fb ldrb r3, [r7, #7] + 800a842: f003 0307 and.w r3, r3, #7 + 800a846: b2db uxtb r3, r3 + 800a848: 733b strb r3, [r7, #12] + buf[1] = ( uint8_t )( ( timeout >> 16 ) & 0xFF ); + 800a84a: 683b ldr r3, [r7, #0] + 800a84c: 0c1b lsrs r3, r3, #16 + 800a84e: b2db uxtb r3, r3 + 800a850: 737b strb r3, [r7, #13] + buf[2] = ( uint8_t )( ( timeout >> 8 ) & 0xFF ); + 800a852: 683b ldr r3, [r7, #0] + 800a854: 0a1b lsrs r3, r3, #8 + 800a856: b2db uxtb r3, r3 + 800a858: 73bb strb r3, [r7, #14] + buf[3] = ( uint8_t )( timeout & 0xFF ); + 800a85a: 683b ldr r3, [r7, #0] + 800a85c: b2db uxtb r3, r3 + 800a85e: 73fb strb r3, [r7, #15] + + SUBGRF_WriteCommand( RADIO_SET_TCXOMODE, buf, 4 ); + 800a860: f107 030c add.w r3, r7, #12 + 800a864: 2204 movs r2, #4 + 800a866: 4619 mov r1, r3 + 800a868: 2097 movs r0, #151 ; 0x97 + 800a86a: f000 fc09 bl 800b080 +} + 800a86e: bf00 nop + 800a870: 3710 adds r7, #16 + 800a872: 46bd mov sp, r7 + 800a874: bd80 pop {r7, pc} + ... + +0800a878 : + +void SUBGRF_SetRfFrequency( uint32_t frequency ) +{ + 800a878: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 800a87c: b084 sub sp, #16 + 800a87e: af00 add r7, sp, #0 + 800a880: 6078 str r0, [r7, #4] + uint8_t buf[4]; + uint32_t chan = 0; + 800a882: 2300 movs r3, #0 + 800a884: 60fb str r3, [r7, #12] + + if( ImageCalibrated == false ) + 800a886: 4b1d ldr r3, [pc, #116] ; (800a8fc ) + 800a888: 781b ldrb r3, [r3, #0] + 800a88a: f083 0301 eor.w r3, r3, #1 + 800a88e: b2db uxtb r3, r3 + 800a890: 2b00 cmp r3, #0 + 800a892: d005 beq.n 800a8a0 + { + SUBGRF_CalibrateImage( frequency ); + 800a894: 6878 ldr r0, [r7, #4] + 800a896: f7ff ff27 bl 800a6e8 + ImageCalibrated = true; + 800a89a: 4b18 ldr r3, [pc, #96] ; (800a8fc ) + 800a89c: 2201 movs r2, #1 + 800a89e: 701a strb r2, [r3, #0] + } + SX_FREQ_TO_CHANNEL(chan, frequency); + 800a8a0: 687b ldr r3, [r7, #4] + 800a8a2: 2200 movs r2, #0 + 800a8a4: 461c mov r4, r3 + 800a8a6: 4615 mov r5, r2 + 800a8a8: ea4f 19d4 mov.w r9, r4, lsr #7 + 800a8ac: ea4f 6844 mov.w r8, r4, lsl #25 + 800a8b0: 4a13 ldr r2, [pc, #76] ; (800a900 ) + 800a8b2: f04f 0300 mov.w r3, #0 + 800a8b6: 4640 mov r0, r8 + 800a8b8: 4649 mov r1, r9 + 800a8ba: f7f5 fcb9 bl 8000230 <__aeabi_uldivmod> + 800a8be: 4602 mov r2, r0 + 800a8c0: 460b mov r3, r1 + 800a8c2: 4613 mov r3, r2 + 800a8c4: 60fb str r3, [r7, #12] + buf[0] = ( uint8_t )( ( chan >> 24 ) & 0xFF ); + 800a8c6: 68fb ldr r3, [r7, #12] + 800a8c8: 0e1b lsrs r3, r3, #24 + 800a8ca: b2db uxtb r3, r3 + 800a8cc: 723b strb r3, [r7, #8] + buf[1] = ( uint8_t )( ( chan >> 16 ) & 0xFF ); + 800a8ce: 68fb ldr r3, [r7, #12] + 800a8d0: 0c1b lsrs r3, r3, #16 + 800a8d2: b2db uxtb r3, r3 + 800a8d4: 727b strb r3, [r7, #9] + buf[2] = ( uint8_t )( ( chan >> 8 ) & 0xFF ); + 800a8d6: 68fb ldr r3, [r7, #12] + 800a8d8: 0a1b lsrs r3, r3, #8 + 800a8da: b2db uxtb r3, r3 + 800a8dc: 72bb strb r3, [r7, #10] + buf[3] = ( uint8_t )( chan & 0xFF ); + 800a8de: 68fb ldr r3, [r7, #12] + 800a8e0: b2db uxtb r3, r3 + 800a8e2: 72fb strb r3, [r7, #11] + SUBGRF_WriteCommand( RADIO_SET_RFFREQUENCY, buf, 4 ); + 800a8e4: f107 0308 add.w r3, r7, #8 + 800a8e8: 2204 movs r2, #4 + 800a8ea: 4619 mov r1, r3 + 800a8ec: 2086 movs r0, #134 ; 0x86 + 800a8ee: f000 fbc7 bl 800b080 +} + 800a8f2: bf00 nop + 800a8f4: 3710 adds r7, #16 + 800a8f6: 46bd mov sp, r7 + 800a8f8: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800a8fc: 20000494 .word 0x20000494 + 800a900: 01e84800 .word 0x01e84800 + +0800a904 : + +void SUBGRF_SetPacketType( RadioPacketTypes_t packetType ) +{ + 800a904: b580 push {r7, lr} + 800a906: b082 sub sp, #8 + 800a908: af00 add r7, sp, #0 + 800a90a: 4603 mov r3, r0 + 800a90c: 71fb strb r3, [r7, #7] + // Save packet type internally to avoid questioning the radio + PacketType = packetType; + 800a90e: 79fa ldrb r2, [r7, #7] + 800a910: 4b09 ldr r3, [pc, #36] ; (800a938 ) + 800a912: 701a strb r2, [r3, #0] + + if( packetType == PACKET_TYPE_GFSK ) + 800a914: 79fb ldrb r3, [r7, #7] + 800a916: 2b00 cmp r3, #0 + 800a918: d104 bne.n 800a924 + { + SUBGRF_WriteRegister( REG_BIT_SYNC, 0x00 ); + 800a91a: 2100 movs r1, #0 + 800a91c: f240 60ac movw r0, #1708 ; 0x6ac + 800a920: f000 fafe bl 800af20 + } + SUBGRF_WriteCommand( RADIO_SET_PACKETTYPE, ( uint8_t* )&packetType, 1 ); + 800a924: 1dfb adds r3, r7, #7 + 800a926: 2201 movs r2, #1 + 800a928: 4619 mov r1, r3 + 800a92a: 208a movs r0, #138 ; 0x8a + 800a92c: f000 fba8 bl 800b080 +} + 800a930: bf00 nop + 800a932: 3708 adds r7, #8 + 800a934: 46bd mov sp, r7 + 800a936: bd80 pop {r7, pc} + 800a938: 2000048d .word 0x2000048d + +0800a93c : + +RadioPacketTypes_t SUBGRF_GetPacketType( void ) +{ + 800a93c: b480 push {r7} + 800a93e: af00 add r7, sp, #0 + return PacketType; + 800a940: 4b02 ldr r3, [pc, #8] ; (800a94c ) + 800a942: 781b ldrb r3, [r3, #0] +} + 800a944: 4618 mov r0, r3 + 800a946: 46bd mov sp, r7 + 800a948: bc80 pop {r7} + 800a94a: 4770 bx lr + 800a94c: 2000048d .word 0x2000048d + +0800a950 : + +void SUBGRF_SetTxParams( uint8_t paSelect, int8_t power, RadioRampTimes_t rampTime ) +{ + 800a950: b580 push {r7, lr} + 800a952: b084 sub sp, #16 + 800a954: af00 add r7, sp, #0 + 800a956: 4603 mov r3, r0 + 800a958: 71fb strb r3, [r7, #7] + 800a95a: 460b mov r3, r1 + 800a95c: 71bb strb r3, [r7, #6] + 800a95e: 4613 mov r3, r2 + 800a960: 717b strb r3, [r7, #5] + uint8_t buf[2]; + int32_t max_power; + + if (paSelect == RFO_LP) + 800a962: 79fb ldrb r3, [r7, #7] + 800a964: 2b01 cmp r3, #1 + 800a966: d149 bne.n 800a9fc + { + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_LP_MAXPOWER); + 800a968: 2000 movs r0, #0 + 800a96a: f001 f96d bl 800bc48 + 800a96e: 60f8 str r0, [r7, #12] + if (power > max_power) + 800a970: f997 3006 ldrsb.w r3, [r7, #6] + 800a974: 68fa ldr r2, [r7, #12] + 800a976: 429a cmp r2, r3 + 800a978: da01 bge.n 800a97e + { + power = max_power; + 800a97a: 68fb ldr r3, [r7, #12] + 800a97c: 71bb strb r3, [r7, #6] + } + if (max_power == 14) + 800a97e: 68fb ldr r3, [r7, #12] + 800a980: 2b0e cmp r3, #14 + 800a982: d10e bne.n 800a9a2 + { + SUBGRF_SetPaConfig(0x04, 0x00, 0x01, 0x01); + 800a984: 2301 movs r3, #1 + 800a986: 2201 movs r2, #1 + 800a988: 2100 movs r1, #0 + 800a98a: 2004 movs r0, #4 + 800a98c: f7ff fef6 bl 800a77c + power = 0x0E - (max_power - power); + 800a990: 79ba ldrb r2, [r7, #6] + 800a992: 68fb ldr r3, [r7, #12] + 800a994: b2db uxtb r3, r3 + 800a996: 1ad3 subs r3, r2, r3 + 800a998: b2db uxtb r3, r3 + 800a99a: 330e adds r3, #14 + 800a99c: b2db uxtb r3, r3 + 800a99e: 71bb strb r3, [r7, #6] + 800a9a0: e01f b.n 800a9e2 + } + else if (max_power == 10) + 800a9a2: 68fb ldr r3, [r7, #12] + 800a9a4: 2b0a cmp r3, #10 + 800a9a6: d10e bne.n 800a9c6 + { + SUBGRF_SetPaConfig(0x01, 0x00, 0x01, 0x01); + 800a9a8: 2301 movs r3, #1 + 800a9aa: 2201 movs r2, #1 + 800a9ac: 2100 movs r1, #0 + 800a9ae: 2001 movs r0, #1 + 800a9b0: f7ff fee4 bl 800a77c + power = 0x0D - (max_power - power); + 800a9b4: 79ba ldrb r2, [r7, #6] + 800a9b6: 68fb ldr r3, [r7, #12] + 800a9b8: b2db uxtb r3, r3 + 800a9ba: 1ad3 subs r3, r2, r3 + 800a9bc: b2db uxtb r3, r3 + 800a9be: 330d adds r3, #13 + 800a9c0: b2db uxtb r3, r3 + 800a9c2: 71bb strb r3, [r7, #6] + 800a9c4: e00d b.n 800a9e2 + } + else /*default 15dBm*/ + { + SUBGRF_SetPaConfig(0x07, 0x00, 0x01, 0x01); + 800a9c6: 2301 movs r3, #1 + 800a9c8: 2201 movs r2, #1 + 800a9ca: 2100 movs r1, #0 + 800a9cc: 2007 movs r0, #7 + 800a9ce: f7ff fed5 bl 800a77c + power = 0x0E - (max_power - power); + 800a9d2: 79ba ldrb r2, [r7, #6] + 800a9d4: 68fb ldr r3, [r7, #12] + 800a9d6: b2db uxtb r3, r3 + 800a9d8: 1ad3 subs r3, r2, r3 + 800a9da: b2db uxtb r3, r3 + 800a9dc: 330e adds r3, #14 + 800a9de: b2db uxtb r3, r3 + 800a9e0: 71bb strb r3, [r7, #6] + } + if (power < -17) + 800a9e2: f997 3006 ldrsb.w r3, [r7, #6] + 800a9e6: f113 0f11 cmn.w r3, #17 + 800a9ea: da01 bge.n 800a9f0 + { + power = -17; + 800a9ec: 23ef movs r3, #239 ; 0xef + 800a9ee: 71bb strb r3, [r7, #6] + } + SUBGRF_WriteRegister(REG_OCP, 0x18); /* current max is 80 mA for the whole device*/ + 800a9f0: 2118 movs r1, #24 + 800a9f2: f640 00e7 movw r0, #2279 ; 0x8e7 + 800a9f6: f000 fa93 bl 800af20 + 800a9fa: e067 b.n 800aacc + } + else /* rfo_hp*/ + { + /* WORKAROUND - Better Resistance of the RFO High Power Tx to Antenna Mismatch, see STM32WL Erratasheet*/ + SUBGRF_WriteRegister(REG_TX_CLAMP, SUBGRF_ReadRegister(REG_TX_CLAMP) | (0x0F << 1)); + 800a9fc: f640 00d8 movw r0, #2264 ; 0x8d8 + 800aa00: f000 faa2 bl 800af48 + 800aa04: 4603 mov r3, r0 + 800aa06: f043 031e orr.w r3, r3, #30 + 800aa0a: b2db uxtb r3, r3 + 800aa0c: 4619 mov r1, r3 + 800aa0e: f640 00d8 movw r0, #2264 ; 0x8d8 + 800aa12: f000 fa85 bl 800af20 + /* WORKAROUND END*/ + max_power = RBI_GetRFOMaxPowerConfig(RBI_RFO_HP_MAXPOWER); + 800aa16: 2001 movs r0, #1 + 800aa18: f001 f916 bl 800bc48 + 800aa1c: 60f8 str r0, [r7, #12] + if (power > max_power) + 800aa1e: f997 3006 ldrsb.w r3, [r7, #6] + 800aa22: 68fa ldr r2, [r7, #12] + 800aa24: 429a cmp r2, r3 + 800aa26: da01 bge.n 800aa2c + { + power = max_power; + 800aa28: 68fb ldr r3, [r7, #12] + 800aa2a: 71bb strb r3, [r7, #6] + } + if (max_power == 20) + 800aa2c: 68fb ldr r3, [r7, #12] + 800aa2e: 2b14 cmp r3, #20 + 800aa30: d10e bne.n 800aa50 + { + SUBGRF_SetPaConfig(0x03, 0x05, 0x00, 0x01); + 800aa32: 2301 movs r3, #1 + 800aa34: 2200 movs r2, #0 + 800aa36: 2105 movs r1, #5 + 800aa38: 2003 movs r0, #3 + 800aa3a: f7ff fe9f bl 800a77c + power = 0x16 - (max_power - power); + 800aa3e: 79ba ldrb r2, [r7, #6] + 800aa40: 68fb ldr r3, [r7, #12] + 800aa42: b2db uxtb r3, r3 + 800aa44: 1ad3 subs r3, r2, r3 + 800aa46: b2db uxtb r3, r3 + 800aa48: 3316 adds r3, #22 + 800aa4a: b2db uxtb r3, r3 + 800aa4c: 71bb strb r3, [r7, #6] + 800aa4e: e031 b.n 800aab4 + } + else if (max_power == 17) + 800aa50: 68fb ldr r3, [r7, #12] + 800aa52: 2b11 cmp r3, #17 + 800aa54: d10e bne.n 800aa74 + { + SUBGRF_SetPaConfig(0x02, 0x03, 0x00, 0x01); + 800aa56: 2301 movs r3, #1 + 800aa58: 2200 movs r2, #0 + 800aa5a: 2103 movs r1, #3 + 800aa5c: 2002 movs r0, #2 + 800aa5e: f7ff fe8d bl 800a77c + power = 0x16 - (max_power - power); + 800aa62: 79ba ldrb r2, [r7, #6] + 800aa64: 68fb ldr r3, [r7, #12] + 800aa66: b2db uxtb r3, r3 + 800aa68: 1ad3 subs r3, r2, r3 + 800aa6a: b2db uxtb r3, r3 + 800aa6c: 3316 adds r3, #22 + 800aa6e: b2db uxtb r3, r3 + 800aa70: 71bb strb r3, [r7, #6] + 800aa72: e01f b.n 800aab4 + } + else if (max_power == 14) + 800aa74: 68fb ldr r3, [r7, #12] + 800aa76: 2b0e cmp r3, #14 + 800aa78: d10e bne.n 800aa98 + { + SUBGRF_SetPaConfig(0x02, 0x02, 0x00, 0x01); + 800aa7a: 2301 movs r3, #1 + 800aa7c: 2200 movs r2, #0 + 800aa7e: 2102 movs r1, #2 + 800aa80: 2002 movs r0, #2 + 800aa82: f7ff fe7b bl 800a77c + power = 0x0E - (max_power - power); + 800aa86: 79ba ldrb r2, [r7, #6] + 800aa88: 68fb ldr r3, [r7, #12] + 800aa8a: b2db uxtb r3, r3 + 800aa8c: 1ad3 subs r3, r2, r3 + 800aa8e: b2db uxtb r3, r3 + 800aa90: 330e adds r3, #14 + 800aa92: b2db uxtb r3, r3 + 800aa94: 71bb strb r3, [r7, #6] + 800aa96: e00d b.n 800aab4 + } + else /*22dBm*/ + { + SUBGRF_SetPaConfig(0x04, 0x07, 0x00, 0x01); + 800aa98: 2301 movs r3, #1 + 800aa9a: 2200 movs r2, #0 + 800aa9c: 2107 movs r1, #7 + 800aa9e: 2004 movs r0, #4 + 800aaa0: f7ff fe6c bl 800a77c + power = 0x16 - (max_power - power); + 800aaa4: 79ba ldrb r2, [r7, #6] + 800aaa6: 68fb ldr r3, [r7, #12] + 800aaa8: b2db uxtb r3, r3 + 800aaaa: 1ad3 subs r3, r2, r3 + 800aaac: b2db uxtb r3, r3 + 800aaae: 3316 adds r3, #22 + 800aab0: b2db uxtb r3, r3 + 800aab2: 71bb strb r3, [r7, #6] + } + if (power < -9) + 800aab4: f997 3006 ldrsb.w r3, [r7, #6] + 800aab8: f113 0f09 cmn.w r3, #9 + 800aabc: da01 bge.n 800aac2 + { + power = -9; + 800aabe: 23f7 movs r3, #247 ; 0xf7 + 800aac0: 71bb strb r3, [r7, #6] + } + SUBGRF_WriteRegister(REG_OCP, 0x38); /*current max 160mA for the whole device*/ + 800aac2: 2138 movs r1, #56 ; 0x38 + 800aac4: f640 00e7 movw r0, #2279 ; 0x8e7 + 800aac8: f000 fa2a bl 800af20 + } + buf[0] = power; + 800aacc: 79bb ldrb r3, [r7, #6] + 800aace: 723b strb r3, [r7, #8] + buf[1] = (uint8_t)rampTime; + 800aad0: 797b ldrb r3, [r7, #5] + 800aad2: 727b strb r3, [r7, #9] + SUBGRF_WriteCommand(RADIO_SET_TXPARAMS, buf, 2); + 800aad4: f107 0308 add.w r3, r7, #8 + 800aad8: 2202 movs r2, #2 + 800aada: 4619 mov r1, r3 + 800aadc: 208e movs r0, #142 ; 0x8e + 800aade: f000 facf bl 800b080 +} + 800aae2: bf00 nop + 800aae4: 3710 adds r7, #16 + 800aae6: 46bd mov sp, r7 + 800aae8: bd80 pop {r7, pc} + ... + +0800aaec : + +void SUBGRF_SetModulationParams( ModulationParams_t *modulationParams ) +{ + 800aaec: e92d 43b0 stmdb sp!, {r4, r5, r7, r8, r9, lr} + 800aaf0: b086 sub sp, #24 + 800aaf2: af00 add r7, sp, #0 + 800aaf4: 6078 str r0, [r7, #4] + uint8_t n; + uint32_t tempVal = 0; + 800aaf6: 2300 movs r3, #0 + 800aaf8: 617b str r3, [r7, #20] + uint8_t buf[8] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 800aafa: 4a61 ldr r2, [pc, #388] ; (800ac80 ) + 800aafc: f107 0308 add.w r3, r7, #8 + 800ab00: e892 0003 ldmia.w r2, {r0, r1} + 800ab04: e883 0003 stmia.w r3, {r0, r1} + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != modulationParams->PacketType ) + 800ab08: 687b ldr r3, [r7, #4] + 800ab0a: 781a ldrb r2, [r3, #0] + 800ab0c: 4b5d ldr r3, [pc, #372] ; (800ac84 ) + 800ab0e: 781b ldrb r3, [r3, #0] + 800ab10: 429a cmp r2, r3 + 800ab12: d004 beq.n 800ab1e + { + SUBGRF_SetPacketType( modulationParams->PacketType ); + 800ab14: 687b ldr r3, [r7, #4] + 800ab16: 781b ldrb r3, [r3, #0] + 800ab18: 4618 mov r0, r3 + 800ab1a: f7ff fef3 bl 800a904 + } + + switch( modulationParams->PacketType ) + 800ab1e: 687b ldr r3, [r7, #4] + 800ab20: 781b ldrb r3, [r3, #0] + 800ab22: 2b03 cmp r3, #3 + 800ab24: f200 80a5 bhi.w 800ac72 + 800ab28: a201 add r2, pc, #4 ; (adr r2, 800ab30 ) + 800ab2a: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800ab2e: bf00 nop + 800ab30: 0800ab41 .word 0x0800ab41 + 800ab34: 0800ac01 .word 0x0800ac01 + 800ab38: 0800abc3 .word 0x0800abc3 + 800ab3c: 0800ac2f .word 0x0800ac2f + { + case PACKET_TYPE_GFSK: + n = 8; + 800ab40: 2308 movs r3, #8 + 800ab42: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t )(( 32 * XTAL_FREQ ) / modulationParams->Params.Gfsk.BitRate ); + 800ab44: 687b ldr r3, [r7, #4] + 800ab46: 685b ldr r3, [r3, #4] + 800ab48: 4a4f ldr r2, [pc, #316] ; (800ac88 ) + 800ab4a: fbb2 f3f3 udiv r3, r2, r3 + 800ab4e: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800ab50: 697b ldr r3, [r7, #20] + 800ab52: 0c1b lsrs r3, r3, #16 + 800ab54: b2db uxtb r3, r3 + 800ab56: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800ab58: 697b ldr r3, [r7, #20] + 800ab5a: 0a1b lsrs r3, r3, #8 + 800ab5c: b2db uxtb r3, r3 + 800ab5e: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800ab60: 697b ldr r3, [r7, #20] + 800ab62: b2db uxtb r3, r3 + 800ab64: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + 800ab66: 687b ldr r3, [r7, #4] + 800ab68: 7b1b ldrb r3, [r3, #12] + 800ab6a: 72fb strb r3, [r7, #11] + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + 800ab6c: 687b ldr r3, [r7, #4] + 800ab6e: 7b5b ldrb r3, [r3, #13] + 800ab70: 733b strb r3, [r7, #12] + SX_FREQ_TO_CHANNEL(tempVal, modulationParams->Params.Gfsk.Fdev); + 800ab72: 687b ldr r3, [r7, #4] + 800ab74: 689b ldr r3, [r3, #8] + 800ab76: 2200 movs r2, #0 + 800ab78: 461c mov r4, r3 + 800ab7a: 4615 mov r5, r2 + 800ab7c: ea4f 19d4 mov.w r9, r4, lsr #7 + 800ab80: ea4f 6844 mov.w r8, r4, lsl #25 + 800ab84: 4a41 ldr r2, [pc, #260] ; (800ac8c ) + 800ab86: f04f 0300 mov.w r3, #0 + 800ab8a: 4640 mov r0, r8 + 800ab8c: 4649 mov r1, r9 + 800ab8e: f7f5 fb4f bl 8000230 <__aeabi_uldivmod> + 800ab92: 4602 mov r2, r0 + 800ab94: 460b mov r3, r1 + 800ab96: 4613 mov r3, r2 + 800ab98: 617b str r3, [r7, #20] + buf[5] = ( tempVal >> 16 ) & 0xFF; + 800ab9a: 697b ldr r3, [r7, #20] + 800ab9c: 0c1b lsrs r3, r3, #16 + 800ab9e: b2db uxtb r3, r3 + 800aba0: 737b strb r3, [r7, #13] + buf[6] = ( tempVal >> 8 ) & 0xFF; + 800aba2: 697b ldr r3, [r7, #20] + 800aba4: 0a1b lsrs r3, r3, #8 + 800aba6: b2db uxtb r3, r3 + 800aba8: 73bb strb r3, [r7, #14] + buf[7] = ( tempVal& 0xFF ); + 800abaa: 697b ldr r3, [r7, #20] + 800abac: b2db uxtb r3, r3 + 800abae: 73fb strb r3, [r7, #15] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800abb0: 7cfb ldrb r3, [r7, #19] + 800abb2: b29a uxth r2, r3 + 800abb4: f107 0308 add.w r3, r7, #8 + 800abb8: 4619 mov r1, r3 + 800abba: 208b movs r0, #139 ; 0x8b + 800abbc: f000 fa60 bl 800b080 + break; + 800abc0: e058 b.n 800ac74 + case PACKET_TYPE_BPSK: + n = 4; + 800abc2: 2304 movs r3, #4 + 800abc4: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t ) (( 32 * XTAL_FREQ) / modulationParams->Params.Bpsk.BitRate ); + 800abc6: 687b ldr r3, [r7, #4] + 800abc8: 691b ldr r3, [r3, #16] + 800abca: 4a2f ldr r2, [pc, #188] ; (800ac88 ) + 800abcc: fbb2 f3f3 udiv r3, r2, r3 + 800abd0: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800abd2: 697b ldr r3, [r7, #20] + 800abd4: 0c1b lsrs r3, r3, #16 + 800abd6: b2db uxtb r3, r3 + 800abd8: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800abda: 697b ldr r3, [r7, #20] + 800abdc: 0a1b lsrs r3, r3, #8 + 800abde: b2db uxtb r3, r3 + 800abe0: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800abe2: 697b ldr r3, [r7, #20] + 800abe4: b2db uxtb r3, r3 + 800abe6: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Bpsk.ModulationShaping; + 800abe8: 687b ldr r3, [r7, #4] + 800abea: 7d1b ldrb r3, [r3, #20] + 800abec: 72fb strb r3, [r7, #11] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800abee: 7cfb ldrb r3, [r7, #19] + 800abf0: b29a uxth r2, r3 + 800abf2: f107 0308 add.w r3, r7, #8 + 800abf6: 4619 mov r1, r3 + 800abf8: 208b movs r0, #139 ; 0x8b + 800abfa: f000 fa41 bl 800b080 + break; + 800abfe: e039 b.n 800ac74 + case PACKET_TYPE_LORA: + n = 4; + 800ac00: 2304 movs r3, #4 + 800ac02: 74fb strb r3, [r7, #19] + buf[0] = modulationParams->Params.LoRa.SpreadingFactor; + 800ac04: 687b ldr r3, [r7, #4] + 800ac06: 7e1b ldrb r3, [r3, #24] + 800ac08: 723b strb r3, [r7, #8] + buf[1] = modulationParams->Params.LoRa.Bandwidth; + 800ac0a: 687b ldr r3, [r7, #4] + 800ac0c: 7e5b ldrb r3, [r3, #25] + 800ac0e: 727b strb r3, [r7, #9] + buf[2] = modulationParams->Params.LoRa.CodingRate; + 800ac10: 687b ldr r3, [r7, #4] + 800ac12: 7e9b ldrb r3, [r3, #26] + 800ac14: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.LoRa.LowDatarateOptimize; + 800ac16: 687b ldr r3, [r7, #4] + 800ac18: 7edb ldrb r3, [r3, #27] + 800ac1a: 72fb strb r3, [r7, #11] + + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800ac1c: 7cfb ldrb r3, [r7, #19] + 800ac1e: b29a uxth r2, r3 + 800ac20: f107 0308 add.w r3, r7, #8 + 800ac24: 4619 mov r1, r3 + 800ac26: 208b movs r0, #139 ; 0x8b + 800ac28: f000 fa2a bl 800b080 + + break; + 800ac2c: e022 b.n 800ac74 + case PACKET_TYPE_GMSK: + n = 5; + 800ac2e: 2305 movs r3, #5 + 800ac30: 74fb strb r3, [r7, #19] + tempVal = ( uint32_t )(( 32 *XTAL_FREQ) / modulationParams->Params.Gfsk.BitRate ); + 800ac32: 687b ldr r3, [r7, #4] + 800ac34: 685b ldr r3, [r3, #4] + 800ac36: 4a14 ldr r2, [pc, #80] ; (800ac88 ) + 800ac38: fbb2 f3f3 udiv r3, r2, r3 + 800ac3c: 617b str r3, [r7, #20] + buf[0] = ( tempVal >> 16 ) & 0xFF; + 800ac3e: 697b ldr r3, [r7, #20] + 800ac40: 0c1b lsrs r3, r3, #16 + 800ac42: b2db uxtb r3, r3 + 800ac44: 723b strb r3, [r7, #8] + buf[1] = ( tempVal >> 8 ) & 0xFF; + 800ac46: 697b ldr r3, [r7, #20] + 800ac48: 0a1b lsrs r3, r3, #8 + 800ac4a: b2db uxtb r3, r3 + 800ac4c: 727b strb r3, [r7, #9] + buf[2] = tempVal & 0xFF; + 800ac4e: 697b ldr r3, [r7, #20] + 800ac50: b2db uxtb r3, r3 + 800ac52: 72bb strb r3, [r7, #10] + buf[3] = modulationParams->Params.Gfsk.ModulationShaping; + 800ac54: 687b ldr r3, [r7, #4] + 800ac56: 7b1b ldrb r3, [r3, #12] + 800ac58: 72fb strb r3, [r7, #11] + buf[4] = modulationParams->Params.Gfsk.Bandwidth; + 800ac5a: 687b ldr r3, [r7, #4] + 800ac5c: 7b5b ldrb r3, [r3, #13] + 800ac5e: 733b strb r3, [r7, #12] + SUBGRF_WriteCommand( RADIO_SET_MODULATIONPARAMS, buf, n ); + 800ac60: 7cfb ldrb r3, [r7, #19] + 800ac62: b29a uxth r2, r3 + 800ac64: f107 0308 add.w r3, r7, #8 + 800ac68: 4619 mov r1, r3 + 800ac6a: 208b movs r0, #139 ; 0x8b + 800ac6c: f000 fa08 bl 800b080 + break; + 800ac70: e000 b.n 800ac74 + default: + case PACKET_TYPE_NONE: + break; + 800ac72: bf00 nop + } +} + 800ac74: bf00 nop + 800ac76: 3718 adds r7, #24 + 800ac78: 46bd mov sp, r7 + 800ac7a: e8bd 83b0 ldmia.w sp!, {r4, r5, r7, r8, r9, pc} + 800ac7e: bf00 nop + 800ac80: 0800e09c .word 0x0800e09c + 800ac84: 2000048d .word 0x2000048d + 800ac88: 3d090000 .word 0x3d090000 + 800ac8c: 01e84800 .word 0x01e84800 + +0800ac90 : + +void SUBGRF_SetPacketParams( PacketParams_t *packetParams ) +{ + 800ac90: b580 push {r7, lr} + 800ac92: b086 sub sp, #24 + 800ac94: af00 add r7, sp, #0 + 800ac96: 6078 str r0, [r7, #4] + uint8_t n; + uint8_t crcVal = 0; + 800ac98: 2300 movs r3, #0 + 800ac9a: 75bb strb r3, [r7, #22] + uint8_t buf[9] = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; + 800ac9c: 4a48 ldr r2, [pc, #288] ; (800adc0 ) + 800ac9e: f107 030c add.w r3, r7, #12 + 800aca2: ca07 ldmia r2, {r0, r1, r2} + 800aca4: c303 stmia r3!, {r0, r1} + 800aca6: 701a strb r2, [r3, #0] + + // Check if required configuration corresponds to the stored packet type + // If not, silently update radio packet type + if( PacketType != packetParams->PacketType ) + 800aca8: 687b ldr r3, [r7, #4] + 800acaa: 781a ldrb r2, [r3, #0] + 800acac: 4b45 ldr r3, [pc, #276] ; (800adc4 ) + 800acae: 781b ldrb r3, [r3, #0] + 800acb0: 429a cmp r2, r3 + 800acb2: d004 beq.n 800acbe + { + SUBGRF_SetPacketType( packetParams->PacketType ); + 800acb4: 687b ldr r3, [r7, #4] + 800acb6: 781b ldrb r3, [r3, #0] + 800acb8: 4618 mov r0, r3 + 800acba: f7ff fe23 bl 800a904 + } + + switch( packetParams->PacketType ) + 800acbe: 687b ldr r3, [r7, #4] + 800acc0: 781b ldrb r3, [r3, #0] + 800acc2: 2b03 cmp r3, #3 + 800acc4: d878 bhi.n 800adb8 + 800acc6: a201 add r2, pc, #4 ; (adr r2, 800accc ) + 800acc8: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800accc: 0800acdd .word 0x0800acdd + 800acd0: 0800ad6d .word 0x0800ad6d + 800acd4: 0800ad61 .word 0x0800ad61 + 800acd8: 0800acdd .word 0x0800acdd + { + case PACKET_TYPE_GMSK: + case PACKET_TYPE_GFSK: + if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_IBM ) + 800acdc: 687b ldr r3, [r7, #4] + 800acde: 7a5b ldrb r3, [r3, #9] + 800ace0: 2bf1 cmp r3, #241 ; 0xf1 + 800ace2: d10a bne.n 800acfa + { + SUBGRF_SetCrcSeed( CRC_IBM_SEED ); + 800ace4: f64f 70ff movw r0, #65535 ; 0xffff + 800ace8: f7ff faaa bl 800a240 + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_IBM ); + 800acec: f248 0005 movw r0, #32773 ; 0x8005 + 800acf0: f7ff fac6 bl 800a280 + crcVal = RADIO_CRC_2_BYTES; + 800acf4: 2302 movs r3, #2 + 800acf6: 75bb strb r3, [r7, #22] + 800acf8: e011 b.n 800ad1e + } + else if( packetParams->Params.Gfsk.CrcLength == RADIO_CRC_2_BYTES_CCIT ) + 800acfa: 687b ldr r3, [r7, #4] + 800acfc: 7a5b ldrb r3, [r3, #9] + 800acfe: 2bf2 cmp r3, #242 ; 0xf2 + 800ad00: d10a bne.n 800ad18 + { + SUBGRF_SetCrcSeed( CRC_CCITT_SEED ); + 800ad02: f641 500f movw r0, #7439 ; 0x1d0f + 800ad06: f7ff fa9b bl 800a240 + SUBGRF_SetCrcPolynomial( CRC_POLYNOMIAL_CCITT ); + 800ad0a: f241 0021 movw r0, #4129 ; 0x1021 + 800ad0e: f7ff fab7 bl 800a280 + crcVal = RADIO_CRC_2_BYTES_INV; + 800ad12: 2306 movs r3, #6 + 800ad14: 75bb strb r3, [r7, #22] + 800ad16: e002 b.n 800ad1e + } + else + { + crcVal = packetParams->Params.Gfsk.CrcLength; + 800ad18: 687b ldr r3, [r7, #4] + 800ad1a: 7a5b ldrb r3, [r3, #9] + 800ad1c: 75bb strb r3, [r7, #22] + } + n = 9; + 800ad1e: 2309 movs r3, #9 + 800ad20: 75fb strb r3, [r7, #23] + buf[0] = ( packetParams->Params.Gfsk.PreambleLength >> 8 ) & 0xFF; + 800ad22: 687b ldr r3, [r7, #4] + 800ad24: 885b ldrh r3, [r3, #2] + 800ad26: 0a1b lsrs r3, r3, #8 + 800ad28: b29b uxth r3, r3 + 800ad2a: b2db uxtb r3, r3 + 800ad2c: 733b strb r3, [r7, #12] + buf[1] = packetParams->Params.Gfsk.PreambleLength; + 800ad2e: 687b ldr r3, [r7, #4] + 800ad30: 885b ldrh r3, [r3, #2] + 800ad32: b2db uxtb r3, r3 + 800ad34: 737b strb r3, [r7, #13] + buf[2] = packetParams->Params.Gfsk.PreambleMinDetect; + 800ad36: 687b ldr r3, [r7, #4] + 800ad38: 791b ldrb r3, [r3, #4] + 800ad3a: 73bb strb r3, [r7, #14] + buf[3] = ( packetParams->Params.Gfsk.SyncWordLength /*<< 3*/ ); // convert from byte to bit + 800ad3c: 687b ldr r3, [r7, #4] + 800ad3e: 795b ldrb r3, [r3, #5] + 800ad40: 73fb strb r3, [r7, #15] + buf[4] = packetParams->Params.Gfsk.AddrComp; + 800ad42: 687b ldr r3, [r7, #4] + 800ad44: 799b ldrb r3, [r3, #6] + 800ad46: 743b strb r3, [r7, #16] + buf[5] = packetParams->Params.Gfsk.HeaderType; + 800ad48: 687b ldr r3, [r7, #4] + 800ad4a: 79db ldrb r3, [r3, #7] + 800ad4c: 747b strb r3, [r7, #17] + buf[6] = packetParams->Params.Gfsk.PayloadLength; + 800ad4e: 687b ldr r3, [r7, #4] + 800ad50: 7a1b ldrb r3, [r3, #8] + 800ad52: 74bb strb r3, [r7, #18] + buf[7] = crcVal; + 800ad54: 7dbb ldrb r3, [r7, #22] + 800ad56: 74fb strb r3, [r7, #19] + buf[8] = packetParams->Params.Gfsk.DcFree; + 800ad58: 687b ldr r3, [r7, #4] + 800ad5a: 7a9b ldrb r3, [r3, #10] + 800ad5c: 753b strb r3, [r7, #20] + break; + 800ad5e: e022 b.n 800ada6 + case PACKET_TYPE_BPSK: + n = 1; + 800ad60: 2301 movs r3, #1 + 800ad62: 75fb strb r3, [r7, #23] + buf[0] = packetParams->Params.Bpsk.PayloadLength; + 800ad64: 687b ldr r3, [r7, #4] + 800ad66: 7b1b ldrb r3, [r3, #12] + 800ad68: 733b strb r3, [r7, #12] + break; + 800ad6a: e01c b.n 800ada6 + case PACKET_TYPE_LORA: + n = 6; + 800ad6c: 2306 movs r3, #6 + 800ad6e: 75fb strb r3, [r7, #23] + buf[0] = ( packetParams->Params.LoRa.PreambleLength >> 8 ) & 0xFF; + 800ad70: 687b ldr r3, [r7, #4] + 800ad72: 89db ldrh r3, [r3, #14] + 800ad74: 0a1b lsrs r3, r3, #8 + 800ad76: b29b uxth r3, r3 + 800ad78: b2db uxtb r3, r3 + 800ad7a: 733b strb r3, [r7, #12] + buf[1] = packetParams->Params.LoRa.PreambleLength; + 800ad7c: 687b ldr r3, [r7, #4] + 800ad7e: 89db ldrh r3, [r3, #14] + 800ad80: b2db uxtb r3, r3 + 800ad82: 737b strb r3, [r7, #13] + buf[2] = LoRaHeaderType = packetParams->Params.LoRa.HeaderType; + 800ad84: 687b ldr r3, [r7, #4] + 800ad86: 7c1a ldrb r2, [r3, #16] + 800ad88: 4b0f ldr r3, [pc, #60] ; (800adc8 ) + 800ad8a: 4611 mov r1, r2 + 800ad8c: 7019 strb r1, [r3, #0] + 800ad8e: 4613 mov r3, r2 + 800ad90: 73bb strb r3, [r7, #14] + buf[3] = packetParams->Params.LoRa.PayloadLength; + 800ad92: 687b ldr r3, [r7, #4] + 800ad94: 7c5b ldrb r3, [r3, #17] + 800ad96: 73fb strb r3, [r7, #15] + buf[4] = packetParams->Params.LoRa.CrcMode; + 800ad98: 687b ldr r3, [r7, #4] + 800ad9a: 7c9b ldrb r3, [r3, #18] + 800ad9c: 743b strb r3, [r7, #16] + buf[5] = packetParams->Params.LoRa.InvertIQ; + 800ad9e: 687b ldr r3, [r7, #4] + 800ada0: 7cdb ldrb r3, [r3, #19] + 800ada2: 747b strb r3, [r7, #17] + break; + 800ada4: bf00 nop + default: + case PACKET_TYPE_NONE: + return; + } + SUBGRF_WriteCommand( RADIO_SET_PACKETPARAMS, buf, n ); + 800ada6: 7dfb ldrb r3, [r7, #23] + 800ada8: b29a uxth r2, r3 + 800adaa: f107 030c add.w r3, r7, #12 + 800adae: 4619 mov r1, r3 + 800adb0: 208c movs r0, #140 ; 0x8c + 800adb2: f000 f965 bl 800b080 + 800adb6: e000 b.n 800adba + return; + 800adb8: bf00 nop +} + 800adba: 3718 adds r7, #24 + 800adbc: 46bd mov sp, r7 + 800adbe: bd80 pop {r7, pc} + 800adc0: 0800e0a4 .word 0x0800e0a4 + 800adc4: 2000048d .word 0x2000048d + 800adc8: 2000048e .word 0x2000048e + +0800adcc : + SUBGRF_WriteCommand( RADIO_SET_CADPARAMS, buf, 7 ); + OperatingMode = MODE_CAD; +} + +void SUBGRF_SetBufferBaseAddress( uint8_t txBaseAddress, uint8_t rxBaseAddress ) +{ + 800adcc: b580 push {r7, lr} + 800adce: b084 sub sp, #16 + 800add0: af00 add r7, sp, #0 + 800add2: 4603 mov r3, r0 + 800add4: 460a mov r2, r1 + 800add6: 71fb strb r3, [r7, #7] + 800add8: 4613 mov r3, r2 + 800adda: 71bb strb r3, [r7, #6] + uint8_t buf[2]; + + buf[0] = txBaseAddress; + 800addc: 79fb ldrb r3, [r7, #7] + 800adde: 733b strb r3, [r7, #12] + buf[1] = rxBaseAddress; + 800ade0: 79bb ldrb r3, [r7, #6] + 800ade2: 737b strb r3, [r7, #13] + SUBGRF_WriteCommand( RADIO_SET_BUFFERBASEADDRESS, buf, 2 ); + 800ade4: f107 030c add.w r3, r7, #12 + 800ade8: 2202 movs r2, #2 + 800adea: 4619 mov r1, r3 + 800adec: 208f movs r0, #143 ; 0x8f + 800adee: f000 f947 bl 800b080 +} + 800adf2: bf00 nop + 800adf4: 3710 adds r7, #16 + 800adf6: 46bd mov sp, r7 + 800adf8: bd80 pop {r7, pc} + +0800adfa : + status.Fields.ChipMode = ( stat & ( 0x07 << 4 ) ) >> 4; + return status; +} + +int8_t SUBGRF_GetRssiInst( void ) +{ + 800adfa: b580 push {r7, lr} + 800adfc: b082 sub sp, #8 + 800adfe: af00 add r7, sp, #0 + uint8_t buf[1]; + int8_t rssi = 0; + 800ae00: 2300 movs r3, #0 + 800ae02: 71fb strb r3, [r7, #7] + + SUBGRF_ReadCommand( RADIO_GET_RSSIINST, buf, 1 ); + 800ae04: 1d3b adds r3, r7, #4 + 800ae06: 2201 movs r2, #1 + 800ae08: 4619 mov r1, r3 + 800ae0a: 2015 movs r0, #21 + 800ae0c: f000 f95a bl 800b0c4 + rssi = -buf[0] >> 1; + 800ae10: 793b ldrb r3, [r7, #4] + 800ae12: 425b negs r3, r3 + 800ae14: 105b asrs r3, r3, #1 + 800ae16: 71fb strb r3, [r7, #7] + return rssi; + 800ae18: f997 3007 ldrsb.w r3, [r7, #7] +} + 800ae1c: 4618 mov r0, r3 + 800ae1e: 3708 adds r7, #8 + 800ae20: 46bd mov sp, r7 + 800ae22: bd80 pop {r7, pc} + +0800ae24 : + +void SUBGRF_GetRxBufferStatus( uint8_t *payloadLength, uint8_t *rxStartBufferPointer ) +{ + 800ae24: b580 push {r7, lr} + 800ae26: b084 sub sp, #16 + 800ae28: af00 add r7, sp, #0 + 800ae2a: 6078 str r0, [r7, #4] + 800ae2c: 6039 str r1, [r7, #0] + uint8_t status[2]; + + SUBGRF_ReadCommand( RADIO_GET_RXBUFFERSTATUS, status, 2 ); + 800ae2e: f107 030c add.w r3, r7, #12 + 800ae32: 2202 movs r2, #2 + 800ae34: 4619 mov r1, r3 + 800ae36: 2013 movs r0, #19 + 800ae38: f000 f944 bl 800b0c4 + + // In case of LORA fixed header, the payloadLength is obtained by reading + // the register REG_LR_PAYLOADLENGTH + if( ( SUBGRF_GetPacketType( ) == PACKET_TYPE_LORA ) && ( LoRaHeaderType == LORA_PACKET_FIXED_LENGTH ) ) + 800ae3c: f7ff fd7e bl 800a93c + 800ae40: 4603 mov r3, r0 + 800ae42: 2b01 cmp r3, #1 + 800ae44: d10d bne.n 800ae62 + 800ae46: 4b0c ldr r3, [pc, #48] ; (800ae78 ) + 800ae48: 781b ldrb r3, [r3, #0] + 800ae4a: b2db uxtb r3, r3 + 800ae4c: 2b01 cmp r3, #1 + 800ae4e: d108 bne.n 800ae62 + { + *payloadLength = SUBGRF_ReadRegister( REG_LR_PAYLOADLENGTH ); + 800ae50: f240 7002 movw r0, #1794 ; 0x702 + 800ae54: f000 f878 bl 800af48 + 800ae58: 4603 mov r3, r0 + 800ae5a: 461a mov r2, r3 + 800ae5c: 687b ldr r3, [r7, #4] + 800ae5e: 701a strb r2, [r3, #0] + 800ae60: e002 b.n 800ae68 + } + else + { + *payloadLength = status[0]; + 800ae62: 7b3a ldrb r2, [r7, #12] + 800ae64: 687b ldr r3, [r7, #4] + 800ae66: 701a strb r2, [r3, #0] + } + *rxStartBufferPointer = status[1]; + 800ae68: 7b7a ldrb r2, [r7, #13] + 800ae6a: 683b ldr r3, [r7, #0] + 800ae6c: 701a strb r2, [r3, #0] +} + 800ae6e: bf00 nop + 800ae70: 3710 adds r7, #16 + 800ae72: 46bd mov sp, r7 + 800ae74: bd80 pop {r7, pc} + 800ae76: bf00 nop + 800ae78: 2000048e .word 0x2000048e + +0800ae7c : + +void SUBGRF_GetPacketStatus( PacketStatus_t *pktStatus ) +{ + 800ae7c: b580 push {r7, lr} + 800ae7e: b084 sub sp, #16 + 800ae80: af00 add r7, sp, #0 + 800ae82: 6078 str r0, [r7, #4] + uint8_t status[3]; + + SUBGRF_ReadCommand( RADIO_GET_PACKETSTATUS, status, 3 ); + 800ae84: f107 030c add.w r3, r7, #12 + 800ae88: 2203 movs r2, #3 + 800ae8a: 4619 mov r1, r3 + 800ae8c: 2014 movs r0, #20 + 800ae8e: f000 f919 bl 800b0c4 + + pktStatus->packetType = SUBGRF_GetPacketType( ); + 800ae92: f7ff fd53 bl 800a93c + 800ae96: 4603 mov r3, r0 + 800ae98: 461a mov r2, r3 + 800ae9a: 687b ldr r3, [r7, #4] + 800ae9c: 701a strb r2, [r3, #0] + switch( pktStatus->packetType ) + 800ae9e: 687b ldr r3, [r7, #4] + 800aea0: 781b ldrb r3, [r3, #0] + 800aea2: 2b00 cmp r3, #0 + 800aea4: d002 beq.n 800aeac + 800aea6: 2b01 cmp r3, #1 + 800aea8: d013 beq.n 800aed2 + 800aeaa: e02a b.n 800af02 + { + case PACKET_TYPE_GFSK: + pktStatus->Params.Gfsk.RxStatus = status[0]; + 800aeac: 7b3a ldrb r2, [r7, #12] + 800aeae: 687b ldr r3, [r7, #4] + 800aeb0: 711a strb r2, [r3, #4] + pktStatus->Params.Gfsk.RssiSync = -status[1] >> 1; + 800aeb2: 7b7b ldrb r3, [r7, #13] + 800aeb4: 425b negs r3, r3 + 800aeb6: 105b asrs r3, r3, #1 + 800aeb8: b25a sxtb r2, r3 + 800aeba: 687b ldr r3, [r7, #4] + 800aebc: 719a strb r2, [r3, #6] + pktStatus->Params.Gfsk.RssiAvg = -status[2] >> 1; + 800aebe: 7bbb ldrb r3, [r7, #14] + 800aec0: 425b negs r3, r3 + 800aec2: 105b asrs r3, r3, #1 + 800aec4: b25a sxtb r2, r3 + 800aec6: 687b ldr r3, [r7, #4] + 800aec8: 715a strb r2, [r3, #5] + pktStatus->Params.Gfsk.FreqError = 0; + 800aeca: 687b ldr r3, [r7, #4] + 800aecc: 2200 movs r2, #0 + 800aece: 609a str r2, [r3, #8] + break; + 800aed0: e020 b.n 800af14 + + case PACKET_TYPE_LORA: + pktStatus->Params.LoRa.RssiPkt = -status[0] >> 1; + 800aed2: 7b3b ldrb r3, [r7, #12] + 800aed4: 425b negs r3, r3 + 800aed6: 105b asrs r3, r3, #1 + 800aed8: b25a sxtb r2, r3 + 800aeda: 687b ldr r3, [r7, #4] + 800aedc: 731a strb r2, [r3, #12] + // Returns SNR value [dB] rounded to the nearest integer value + pktStatus->Params.LoRa.SnrPkt = ( ( ( int8_t )status[1] ) + 2 ) >> 2; + 800aede: 7b7b ldrb r3, [r7, #13] + 800aee0: b25b sxtb r3, r3 + 800aee2: 3302 adds r3, #2 + 800aee4: 109b asrs r3, r3, #2 + 800aee6: b25a sxtb r2, r3 + 800aee8: 687b ldr r3, [r7, #4] + 800aeea: 735a strb r2, [r3, #13] + pktStatus->Params.LoRa.SignalRssiPkt = -status[2] >> 1; + 800aeec: 7bbb ldrb r3, [r7, #14] + 800aeee: 425b negs r3, r3 + 800aef0: 105b asrs r3, r3, #1 + 800aef2: b25a sxtb r2, r3 + 800aef4: 687b ldr r3, [r7, #4] + 800aef6: 739a strb r2, [r3, #14] + pktStatus->Params.LoRa.FreqError = FrequencyError; + 800aef8: 4b08 ldr r3, [pc, #32] ; (800af1c ) + 800aefa: 681a ldr r2, [r3, #0] + 800aefc: 687b ldr r3, [r7, #4] + 800aefe: 611a str r2, [r3, #16] + break; + 800af00: e008 b.n 800af14 + + default: + case PACKET_TYPE_NONE: + // In that specific case, we set everything in the pktStatus to zeros + // and reset the packet type accordingly + RADIO_MEMSET8( pktStatus, 0, sizeof( PacketStatus_t ) ); + 800af02: 2214 movs r2, #20 + 800af04: 2100 movs r1, #0 + 800af06: 6878 ldr r0, [r7, #4] + 800af08: f000 ff71 bl 800bdee + pktStatus->packetType = PACKET_TYPE_NONE; + 800af0c: 687b ldr r3, [r7, #4] + 800af0e: 220f movs r2, #15 + 800af10: 701a strb r2, [r3, #0] + break; + 800af12: bf00 nop + } +} + 800af14: bf00 nop + 800af16: 3710 adds r7, #16 + 800af18: 46bd mov sp, r7 + 800af1a: bd80 pop {r7, pc} + 800af1c: 20000490 .word 0x20000490 + +0800af20 : + buf[1] = ( uint8_t )( ( uint16_t )irq & 0x00FF ); + SUBGRF_WriteCommand( RADIO_CLR_IRQSTATUS, buf, 2 ); +} + +void SUBGRF_WriteRegister( uint16_t addr, uint8_t data ) +{ + 800af20: b580 push {r7, lr} + 800af22: b082 sub sp, #8 + 800af24: af00 add r7, sp, #0 + 800af26: 4603 mov r3, r0 + 800af28: 460a mov r2, r1 + 800af2a: 80fb strh r3, [r7, #6] + 800af2c: 4613 mov r3, r2 + 800af2e: 717b strb r3, [r7, #5] + HAL_SUBGHZ_WriteRegisters( &hsubghz, addr, (uint8_t*)&data, 1 ); + 800af30: 1d7a adds r2, r7, #5 + 800af32: 88f9 ldrh r1, [r7, #6] + 800af34: 2301 movs r3, #1 + 800af36: 4803 ldr r0, [pc, #12] ; (800af44 ) + 800af38: f7fa f9e2 bl 8005300 +} + 800af3c: bf00 nop + 800af3e: 3708 adds r7, #8 + 800af40: 46bd mov sp, r7 + 800af42: bd80 pop {r7, pc} + 800af44: 20000148 .word 0x20000148 + +0800af48 : + +uint8_t SUBGRF_ReadRegister( uint16_t addr ) +{ + 800af48: b580 push {r7, lr} + 800af4a: b084 sub sp, #16 + 800af4c: af00 add r7, sp, #0 + 800af4e: 4603 mov r3, r0 + 800af50: 80fb strh r3, [r7, #6] + uint8_t data; + HAL_SUBGHZ_ReadRegisters( &hsubghz, addr, &data, 1 ); + 800af52: f107 020f add.w r2, r7, #15 + 800af56: 88f9 ldrh r1, [r7, #6] + 800af58: 2301 movs r3, #1 + 800af5a: 4804 ldr r0, [pc, #16] ; (800af6c ) + 800af5c: f7fa fa2f bl 80053be + return data; + 800af60: 7bfb ldrb r3, [r7, #15] +} + 800af62: 4618 mov r0, r3 + 800af64: 3710 adds r7, #16 + 800af66: 46bd mov sp, r7 + 800af68: bd80 pop {r7, pc} + 800af6a: bf00 nop + 800af6c: 20000148 .word 0x20000148 + +0800af70 : + +void SUBGRF_WriteRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + 800af70: b580 push {r7, lr} + 800af72: b086 sub sp, #24 + 800af74: af00 add r7, sp, #0 + 800af76: 4603 mov r3, r0 + 800af78: 6039 str r1, [r7, #0] + 800af7a: 80fb strh r3, [r7, #6] + 800af7c: 4613 mov r3, r2 + 800af7e: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800af80: f3ef 8310 mrs r3, PRIMASK + 800af84: 60fb str r3, [r7, #12] + return(result); + 800af86: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800af88: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800af8a: b672 cpsid i +} + 800af8c: bf00 nop + HAL_SUBGHZ_WriteRegisters( &hsubghz, address, buffer, size ); + 800af8e: 88bb ldrh r3, [r7, #4] + 800af90: 88f9 ldrh r1, [r7, #6] + 800af92: 683a ldr r2, [r7, #0] + 800af94: 4806 ldr r0, [pc, #24] ; (800afb0 ) + 800af96: f7fa f9b3 bl 8005300 + 800af9a: 697b ldr r3, [r7, #20] + 800af9c: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800af9e: 693b ldr r3, [r7, #16] + 800afa0: f383 8810 msr PRIMASK, r3 +} + 800afa4: bf00 nop + CRITICAL_SECTION_END(); +} + 800afa6: bf00 nop + 800afa8: 3718 adds r7, #24 + 800afaa: 46bd mov sp, r7 + 800afac: bd80 pop {r7, pc} + 800afae: bf00 nop + 800afb0: 20000148 .word 0x20000148 + +0800afb4 : + +void SUBGRF_ReadRegisters( uint16_t address, uint8_t *buffer, uint16_t size ) +{ + 800afb4: b580 push {r7, lr} + 800afb6: b086 sub sp, #24 + 800afb8: af00 add r7, sp, #0 + 800afba: 4603 mov r3, r0 + 800afbc: 6039 str r1, [r7, #0] + 800afbe: 80fb strh r3, [r7, #6] + 800afc0: 4613 mov r3, r2 + 800afc2: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800afc4: f3ef 8310 mrs r3, PRIMASK + 800afc8: 60fb str r3, [r7, #12] + return(result); + 800afca: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800afcc: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800afce: b672 cpsid i +} + 800afd0: bf00 nop + HAL_SUBGHZ_ReadRegisters( &hsubghz, address, buffer, size ); + 800afd2: 88bb ldrh r3, [r7, #4] + 800afd4: 88f9 ldrh r1, [r7, #6] + 800afd6: 683a ldr r2, [r7, #0] + 800afd8: 4806 ldr r0, [pc, #24] ; (800aff4 ) + 800afda: f7fa f9f0 bl 80053be + 800afde: 697b ldr r3, [r7, #20] + 800afe0: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800afe2: 693b ldr r3, [r7, #16] + 800afe4: f383 8810 msr PRIMASK, r3 +} + 800afe8: bf00 nop + CRITICAL_SECTION_END(); +} + 800afea: bf00 nop + 800afec: 3718 adds r7, #24 + 800afee: 46bd mov sp, r7 + 800aff0: bd80 pop {r7, pc} + 800aff2: bf00 nop + 800aff4: 20000148 .word 0x20000148 + +0800aff8 : + +void SUBGRF_WriteBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + 800aff8: b580 push {r7, lr} + 800affa: b086 sub sp, #24 + 800affc: af00 add r7, sp, #0 + 800affe: 4603 mov r3, r0 + 800b000: 6039 str r1, [r7, #0] + 800b002: 71fb strb r3, [r7, #7] + 800b004: 4613 mov r3, r2 + 800b006: 71bb strb r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800b008: f3ef 8310 mrs r3, PRIMASK + 800b00c: 60fb str r3, [r7, #12] + return(result); + 800b00e: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800b010: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800b012: b672 cpsid i +} + 800b014: bf00 nop + HAL_SUBGHZ_WriteBuffer( &hsubghz, offset, buffer, size ); + 800b016: 79bb ldrb r3, [r7, #6] + 800b018: b29b uxth r3, r3 + 800b01a: 79f9 ldrb r1, [r7, #7] + 800b01c: 683a ldr r2, [r7, #0] + 800b01e: 4806 ldr r0, [pc, #24] ; (800b038 ) + 800b020: f7fa fae1 bl 80055e6 + 800b024: 697b ldr r3, [r7, #20] + 800b026: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800b028: 693b ldr r3, [r7, #16] + 800b02a: f383 8810 msr PRIMASK, r3 +} + 800b02e: bf00 nop + CRITICAL_SECTION_END(); +} + 800b030: bf00 nop + 800b032: 3718 adds r7, #24 + 800b034: 46bd mov sp, r7 + 800b036: bd80 pop {r7, pc} + 800b038: 20000148 .word 0x20000148 + +0800b03c : + +void SUBGRF_ReadBuffer( uint8_t offset, uint8_t *buffer, uint8_t size ) +{ + 800b03c: b580 push {r7, lr} + 800b03e: b086 sub sp, #24 + 800b040: af00 add r7, sp, #0 + 800b042: 4603 mov r3, r0 + 800b044: 6039 str r1, [r7, #0] + 800b046: 71fb strb r3, [r7, #7] + 800b048: 4613 mov r3, r2 + 800b04a: 71bb strb r3, [r7, #6] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800b04c: f3ef 8310 mrs r3, PRIMASK + 800b050: 60fb str r3, [r7, #12] + return(result); + 800b052: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800b054: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800b056: b672 cpsid i +} + 800b058: bf00 nop + HAL_SUBGHZ_ReadBuffer( &hsubghz, offset, buffer, size ); + 800b05a: 79bb ldrb r3, [r7, #6] + 800b05c: b29b uxth r3, r3 + 800b05e: 79f9 ldrb r1, [r7, #7] + 800b060: 683a ldr r2, [r7, #0] + 800b062: 4806 ldr r0, [pc, #24] ; (800b07c ) + 800b064: f7fa fb12 bl 800568c + 800b068: 697b ldr r3, [r7, #20] + 800b06a: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800b06c: 693b ldr r3, [r7, #16] + 800b06e: f383 8810 msr PRIMASK, r3 +} + 800b072: bf00 nop + CRITICAL_SECTION_END(); +} + 800b074: bf00 nop + 800b076: 3718 adds r7, #24 + 800b078: 46bd mov sp, r7 + 800b07a: bd80 pop {r7, pc} + 800b07c: 20000148 .word 0x20000148 + +0800b080 : + +void SUBGRF_WriteCommand( SUBGHZ_RadioSetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + 800b080: b580 push {r7, lr} + 800b082: b086 sub sp, #24 + 800b084: af00 add r7, sp, #0 + 800b086: 4603 mov r3, r0 + 800b088: 6039 str r1, [r7, #0] + 800b08a: 71fb strb r3, [r7, #7] + 800b08c: 4613 mov r3, r2 + 800b08e: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800b090: f3ef 8310 mrs r3, PRIMASK + 800b094: 60fb str r3, [r7, #12] + return(result); + 800b096: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800b098: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800b09a: b672 cpsid i +} + 800b09c: bf00 nop + HAL_SUBGHZ_ExecSetCmd( &hsubghz, Command, pBuffer, Size ); + 800b09e: 88bb ldrh r3, [r7, #4] + 800b0a0: 79f9 ldrb r1, [r7, #7] + 800b0a2: 683a ldr r2, [r7, #0] + 800b0a4: 4806 ldr r0, [pc, #24] ; (800b0c0 ) + 800b0a6: f7fa f9eb bl 8005480 + 800b0aa: 697b ldr r3, [r7, #20] + 800b0ac: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800b0ae: 693b ldr r3, [r7, #16] + 800b0b0: f383 8810 msr PRIMASK, r3 +} + 800b0b4: bf00 nop + CRITICAL_SECTION_END(); +} + 800b0b6: bf00 nop + 800b0b8: 3718 adds r7, #24 + 800b0ba: 46bd mov sp, r7 + 800b0bc: bd80 pop {r7, pc} + 800b0be: bf00 nop + 800b0c0: 20000148 .word 0x20000148 + +0800b0c4 : + +void SUBGRF_ReadCommand( SUBGHZ_RadioGetCmd_t Command, uint8_t *pBuffer, + uint16_t Size ) +{ + 800b0c4: b580 push {r7, lr} + 800b0c6: b086 sub sp, #24 + 800b0c8: af00 add r7, sp, #0 + 800b0ca: 4603 mov r3, r0 + 800b0cc: 6039 str r1, [r7, #0] + 800b0ce: 71fb strb r3, [r7, #7] + 800b0d0: 4613 mov r3, r2 + 800b0d2: 80bb strh r3, [r7, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800b0d4: f3ef 8310 mrs r3, PRIMASK + 800b0d8: 60fb str r3, [r7, #12] + return(result); + 800b0da: 68fb ldr r3, [r7, #12] + CRITICAL_SECTION_BEGIN(); + 800b0dc: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800b0de: b672 cpsid i +} + 800b0e0: bf00 nop + HAL_SUBGHZ_ExecGetCmd( &hsubghz, Command, pBuffer, Size ); + 800b0e2: 88bb ldrh r3, [r7, #4] + 800b0e4: 79f9 ldrb r1, [r7, #7] + 800b0e6: 683a ldr r2, [r7, #0] + 800b0e8: 4806 ldr r0, [pc, #24] ; (800b104 ) + 800b0ea: f7fa fa28 bl 800553e + 800b0ee: 697b ldr r3, [r7, #20] + 800b0f0: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800b0f2: 693b ldr r3, [r7, #16] + 800b0f4: f383 8810 msr PRIMASK, r3 +} + 800b0f8: bf00 nop + CRITICAL_SECTION_END(); +} + 800b0fa: bf00 nop + 800b0fc: 3718 adds r7, #24 + 800b0fe: 46bd mov sp, r7 + 800b100: bd80 pop {r7, pc} + 800b102: bf00 nop + 800b104: 20000148 .word 0x20000148 + +0800b108 : + +void SUBGRF_SetSwitch( uint8_t paSelect, RFState_t rxtx ) +{ + 800b108: b580 push {r7, lr} + 800b10a: b084 sub sp, #16 + 800b10c: af00 add r7, sp, #0 + 800b10e: 4603 mov r3, r0 + 800b110: 460a mov r2, r1 + 800b112: 71fb strb r3, [r7, #7] + 800b114: 4613 mov r3, r2 + 800b116: 71bb strb r3, [r7, #6] + RBI_Switch_TypeDef state = RBI_SWITCH_RX; + 800b118: 2301 movs r3, #1 + 800b11a: 73fb strb r3, [r7, #15] + + if (rxtx == RFSWITCH_TX) + 800b11c: 79bb ldrb r3, [r7, #6] + 800b11e: 2b01 cmp r3, #1 + 800b120: d10d bne.n 800b13e + { + if (paSelect == RFO_LP) + 800b122: 79fb ldrb r3, [r7, #7] + 800b124: 2b01 cmp r3, #1 + 800b126: d104 bne.n 800b132 + { + state = RBI_SWITCH_RFO_LP; + 800b128: 2302 movs r3, #2 + 800b12a: 73fb strb r3, [r7, #15] + Radio_SMPS_Set(SMPS_DRIVE_SETTING_MAX); + 800b12c: 2004 movs r0, #4 + 800b12e: f000 f8ef bl 800b310 + } + if (paSelect == RFO_HP) + 800b132: 79fb ldrb r3, [r7, #7] + 800b134: 2b02 cmp r3, #2 + 800b136: d107 bne.n 800b148 + { + state = RBI_SWITCH_RFO_HP; + 800b138: 2303 movs r3, #3 + 800b13a: 73fb strb r3, [r7, #15] + 800b13c: e004 b.n 800b148 + } + } + else + { + if (rxtx == RFSWITCH_RX) + 800b13e: 79bb ldrb r3, [r7, #6] + 800b140: 2b00 cmp r3, #0 + 800b142: d101 bne.n 800b148 + { + state = RBI_SWITCH_RX; + 800b144: 2301 movs r3, #1 + 800b146: 73fb strb r3, [r7, #15] + } + } + RBI_ConfigRFSwitch(state); + 800b148: 7bfb ldrb r3, [r7, #15] + 800b14a: 4618 mov r0, r3 + 800b14c: f000 fd59 bl 800bc02 +} + 800b150: bf00 nop + 800b152: 3710 adds r7, #16 + 800b154: 46bd mov sp, r7 + 800b156: bd80 pop {r7, pc} + +0800b158 : + +uint8_t SUBGRF_SetRfTxPower( int8_t power ) +{ + 800b158: b580 push {r7, lr} + 800b15a: b084 sub sp, #16 + 800b15c: af00 add r7, sp, #0 + 800b15e: 4603 mov r3, r0 + 800b160: 71fb strb r3, [r7, #7] + uint8_t paSelect= RFO_LP; + 800b162: 2301 movs r3, #1 + 800b164: 73fb strb r3, [r7, #15] + + int32_t TxConfig = RBI_GetTxConfig(); + 800b166: f000 fd5a bl 800bc1e + 800b16a: 60b8 str r0, [r7, #8] + + switch (TxConfig) + 800b16c: 68bb ldr r3, [r7, #8] + 800b16e: 2b02 cmp r3, #2 + 800b170: d016 beq.n 800b1a0 + 800b172: 68bb ldr r3, [r7, #8] + 800b174: 2b02 cmp r3, #2 + 800b176: dc16 bgt.n 800b1a6 + 800b178: 68bb ldr r3, [r7, #8] + 800b17a: 2b00 cmp r3, #0 + 800b17c: d003 beq.n 800b186 + 800b17e: 68bb ldr r3, [r7, #8] + 800b180: 2b01 cmp r3, #1 + 800b182: d00a beq.n 800b19a + { + paSelect = RFO_HP; + break; + } + default: + break; + 800b184: e00f b.n 800b1a6 + if (power > 15) + 800b186: f997 3007 ldrsb.w r3, [r7, #7] + 800b18a: 2b0f cmp r3, #15 + 800b18c: dd02 ble.n 800b194 + paSelect = RFO_HP; + 800b18e: 2302 movs r3, #2 + 800b190: 73fb strb r3, [r7, #15] + break; + 800b192: e009 b.n 800b1a8 + paSelect = RFO_LP; + 800b194: 2301 movs r3, #1 + 800b196: 73fb strb r3, [r7, #15] + break; + 800b198: e006 b.n 800b1a8 + paSelect = RFO_LP; + 800b19a: 2301 movs r3, #1 + 800b19c: 73fb strb r3, [r7, #15] + break; + 800b19e: e003 b.n 800b1a8 + paSelect = RFO_HP; + 800b1a0: 2302 movs r3, #2 + 800b1a2: 73fb strb r3, [r7, #15] + break; + 800b1a4: e000 b.n 800b1a8 + break; + 800b1a6: bf00 nop + } + + SUBGRF_SetTxParams( paSelect, power, RADIO_RAMP_40_US ); + 800b1a8: f997 1007 ldrsb.w r1, [r7, #7] + 800b1ac: 7bfb ldrb r3, [r7, #15] + 800b1ae: 2202 movs r2, #2 + 800b1b0: 4618 mov r0, r3 + 800b1b2: f7ff fbcd bl 800a950 + + return paSelect; + 800b1b6: 7bfb ldrb r3, [r7, #15] +} + 800b1b8: 4618 mov r0, r3 + 800b1ba: 3710 adds r7, #16 + 800b1bc: 46bd mov sp, r7 + 800b1be: bd80 pop {r7, pc} + +0800b1c0 : + +uint32_t SUBGRF_GetRadioWakeUpTime( void ) +{ + 800b1c0: b480 push {r7} + 800b1c2: af00 add r7, sp, #0 + return RF_WAKEUP_TIME; + 800b1c4: 2301 movs r3, #1 +} + 800b1c6: 4618 mov r0, r3 + 800b1c8: 46bd mov sp, r7 + 800b1ca: bc80 pop {r7} + 800b1cc: 4770 bx lr + ... + +0800b1d0 : + +/* HAL_SUBGHz Callbacks definitions */ +void HAL_SUBGHZ_TxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b1d0: b580 push {r7, lr} + 800b1d2: b082 sub sp, #8 + 800b1d4: af00 add r7, sp, #0 + 800b1d6: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_TX_DONE ); + 800b1d8: 4b03 ldr r3, [pc, #12] ; (800b1e8 ) + 800b1da: 681b ldr r3, [r3, #0] + 800b1dc: 2001 movs r0, #1 + 800b1de: 4798 blx r3 +} + 800b1e0: bf00 nop + 800b1e2: 3708 adds r7, #8 + 800b1e4: 46bd mov sp, r7 + 800b1e6: bd80 pop {r7, pc} + 800b1e8: 20000498 .word 0x20000498 + +0800b1ec : + +void HAL_SUBGHZ_RxCpltCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b1ec: b580 push {r7, lr} + 800b1ee: b082 sub sp, #8 + 800b1f0: af00 add r7, sp, #0 + 800b1f2: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_RX_DONE ); + 800b1f4: 4b03 ldr r3, [pc, #12] ; (800b204 ) + 800b1f6: 681b ldr r3, [r3, #0] + 800b1f8: 2002 movs r0, #2 + 800b1fa: 4798 blx r3 +} + 800b1fc: bf00 nop + 800b1fe: 3708 adds r7, #8 + 800b200: 46bd mov sp, r7 + 800b202: bd80 pop {r7, pc} + 800b204: 20000498 .word 0x20000498 + +0800b208 : + +void HAL_SUBGHZ_CRCErrorCallback (SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b208: b580 push {r7, lr} + 800b20a: b082 sub sp, #8 + 800b20c: af00 add r7, sp, #0 + 800b20e: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_CRC_ERROR); + 800b210: 4b03 ldr r3, [pc, #12] ; (800b220 ) + 800b212: 681b ldr r3, [r3, #0] + 800b214: 2040 movs r0, #64 ; 0x40 + 800b216: 4798 blx r3 +} + 800b218: bf00 nop + 800b21a: 3708 adds r7, #8 + 800b21c: 46bd mov sp, r7 + 800b21e: bd80 pop {r7, pc} + 800b220: 20000498 .word 0x20000498 + +0800b224 : + +void HAL_SUBGHZ_CADStatusCallback(SUBGHZ_HandleTypeDef *hsubghz, HAL_SUBGHZ_CadStatusTypeDef cadstatus) +{ + 800b224: b580 push {r7, lr} + 800b226: b082 sub sp, #8 + 800b228: af00 add r7, sp, #0 + 800b22a: 6078 str r0, [r7, #4] + 800b22c: 460b mov r3, r1 + 800b22e: 70fb strb r3, [r7, #3] + switch (cadstatus) + 800b230: 78fb ldrb r3, [r7, #3] + 800b232: 2b00 cmp r3, #0 + 800b234: d002 beq.n 800b23c + 800b236: 2b01 cmp r3, #1 + 800b238: d005 beq.n 800b246 + break; + case HAL_SUBGHZ_CAD_DETECTED: + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + break; + default: + break; + 800b23a: e00a b.n 800b252 + RadioOnDioIrqCb( IRQ_CAD_CLEAR); + 800b23c: 4b07 ldr r3, [pc, #28] ; (800b25c ) + 800b23e: 681b ldr r3, [r3, #0] + 800b240: 2080 movs r0, #128 ; 0x80 + 800b242: 4798 blx r3 + break; + 800b244: e005 b.n 800b252 + RadioOnDioIrqCb( IRQ_CAD_DETECTED); + 800b246: 4b05 ldr r3, [pc, #20] ; (800b25c ) + 800b248: 681b ldr r3, [r3, #0] + 800b24a: f44f 7080 mov.w r0, #256 ; 0x100 + 800b24e: 4798 blx r3 + break; + 800b250: bf00 nop + } +} + 800b252: bf00 nop + 800b254: 3708 adds r7, #8 + 800b256: 46bd mov sp, r7 + 800b258: bd80 pop {r7, pc} + 800b25a: bf00 nop + 800b25c: 20000498 .word 0x20000498 + +0800b260 : + +void HAL_SUBGHZ_RxTxTimeoutCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b260: b580 push {r7, lr} + 800b262: b082 sub sp, #8 + 800b264: af00 add r7, sp, #0 + 800b266: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_RX_TX_TIMEOUT ); + 800b268: 4b04 ldr r3, [pc, #16] ; (800b27c ) + 800b26a: 681b ldr r3, [r3, #0] + 800b26c: f44f 7000 mov.w r0, #512 ; 0x200 + 800b270: 4798 blx r3 +} + 800b272: bf00 nop + 800b274: 3708 adds r7, #8 + 800b276: 46bd mov sp, r7 + 800b278: bd80 pop {r7, pc} + 800b27a: bf00 nop + 800b27c: 20000498 .word 0x20000498 + +0800b280 : + +void HAL_SUBGHZ_HeaderErrorCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b280: b580 push {r7, lr} + 800b282: b082 sub sp, #8 + 800b284: af00 add r7, sp, #0 + 800b286: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_HEADER_ERROR ); + 800b288: 4b03 ldr r3, [pc, #12] ; (800b298 ) + 800b28a: 681b ldr r3, [r3, #0] + 800b28c: 2020 movs r0, #32 + 800b28e: 4798 blx r3 +} + 800b290: bf00 nop + 800b292: 3708 adds r7, #8 + 800b294: 46bd mov sp, r7 + 800b296: bd80 pop {r7, pc} + 800b298: 20000498 .word 0x20000498 + +0800b29c : + +void HAL_SUBGHZ_PreambleDetectedCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b29c: b580 push {r7, lr} + 800b29e: b082 sub sp, #8 + 800b2a0: af00 add r7, sp, #0 + 800b2a2: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_PREAMBLE_DETECTED ); + 800b2a4: 4b03 ldr r3, [pc, #12] ; (800b2b4 ) + 800b2a6: 681b ldr r3, [r3, #0] + 800b2a8: 2004 movs r0, #4 + 800b2aa: 4798 blx r3 +} + 800b2ac: bf00 nop + 800b2ae: 3708 adds r7, #8 + 800b2b0: 46bd mov sp, r7 + 800b2b2: bd80 pop {r7, pc} + 800b2b4: 20000498 .word 0x20000498 + +0800b2b8 : + +void HAL_SUBGHZ_SyncWordValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b2b8: b580 push {r7, lr} + 800b2ba: b082 sub sp, #8 + 800b2bc: af00 add r7, sp, #0 + 800b2be: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_SYNCWORD_VALID ); + 800b2c0: 4b03 ldr r3, [pc, #12] ; (800b2d0 ) + 800b2c2: 681b ldr r3, [r3, #0] + 800b2c4: 2008 movs r0, #8 + 800b2c6: 4798 blx r3 +} + 800b2c8: bf00 nop + 800b2ca: 3708 adds r7, #8 + 800b2cc: 46bd mov sp, r7 + 800b2ce: bd80 pop {r7, pc} + 800b2d0: 20000498 .word 0x20000498 + +0800b2d4 : + +void HAL_SUBGHZ_HeaderValidCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b2d4: b580 push {r7, lr} + 800b2d6: b082 sub sp, #8 + 800b2d8: af00 add r7, sp, #0 + 800b2da: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_HEADER_VALID ); + 800b2dc: 4b03 ldr r3, [pc, #12] ; (800b2ec ) + 800b2de: 681b ldr r3, [r3, #0] + 800b2e0: 2010 movs r0, #16 + 800b2e2: 4798 blx r3 +} + 800b2e4: bf00 nop + 800b2e6: 3708 adds r7, #8 + 800b2e8: 46bd mov sp, r7 + 800b2ea: bd80 pop {r7, pc} + 800b2ec: 20000498 .word 0x20000498 + +0800b2f0 : + +void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz) +{ + 800b2f0: b580 push {r7, lr} + 800b2f2: b082 sub sp, #8 + 800b2f4: af00 add r7, sp, #0 + 800b2f6: 6078 str r0, [r7, #4] + RadioOnDioIrqCb( IRQ_LR_FHSS_HOP ); + 800b2f8: 4b04 ldr r3, [pc, #16] ; (800b30c ) + 800b2fa: 681b ldr r3, [r3, #0] + 800b2fc: f44f 4080 mov.w r0, #16384 ; 0x4000 + 800b300: 4798 blx r3 +} + 800b302: bf00 nop + 800b304: 3708 adds r7, #8 + 800b306: 46bd mov sp, r7 + 800b308: bd80 pop {r7, pc} + 800b30a: bf00 nop + 800b30c: 20000498 .word 0x20000498 + +0800b310 : + +static void Radio_SMPS_Set(uint8_t level) +{ + 800b310: b580 push {r7, lr} + 800b312: b084 sub sp, #16 + 800b314: af00 add r7, sp, #0 + 800b316: 4603 mov r3, r0 + 800b318: 71fb strb r3, [r7, #7] + if ( 1U == RBI_IsDCDC() ) + 800b31a: f000 fc8e bl 800bc3a + 800b31e: 4603 mov r3, r0 + 800b320: 2b01 cmp r3, #1 + 800b322: d112 bne.n 800b34a + { + uint8_t modReg; + modReg= SUBGRF_ReadRegister(SUBGHZ_SMPSC2R); + 800b324: f640 1023 movw r0, #2339 ; 0x923 + 800b328: f7ff fe0e bl 800af48 + 800b32c: 4603 mov r3, r0 + 800b32e: 73fb strb r3, [r7, #15] + modReg&= (~SMPS_DRV_MASK); + 800b330: 7bfb ldrb r3, [r7, #15] + 800b332: f023 0306 bic.w r3, r3, #6 + 800b336: 73fb strb r3, [r7, #15] + SUBGRF_WriteRegister(SUBGHZ_SMPSC2R, modReg | level); + 800b338: 7bfa ldrb r2, [r7, #15] + 800b33a: 79fb ldrb r3, [r7, #7] + 800b33c: 4313 orrs r3, r2 + 800b33e: b2db uxtb r3, r3 + 800b340: 4619 mov r1, r3 + 800b342: f640 1023 movw r0, #2339 ; 0x923 + 800b346: f7ff fdeb bl 800af20 + } +} + 800b34a: bf00 nop + 800b34c: 3710 adds r7, #16 + 800b34e: 46bd mov sp, r7 + 800b350: bd80 pop {r7, pc} + ... + +0800b354 : + +uint8_t SUBGRF_GetFskBandwidthRegValue( uint32_t bandwidth ) +{ + 800b354: b480 push {r7} + 800b356: b085 sub sp, #20 + 800b358: af00 add r7, sp, #0 + 800b35a: 6078 str r0, [r7, #4] + uint8_t i; + + if( bandwidth == 0 ) + 800b35c: 687b ldr r3, [r7, #4] + 800b35e: 2b00 cmp r3, #0 + 800b360: d101 bne.n 800b366 + { + return( 0x1F ); + 800b362: 231f movs r3, #31 + 800b364: e016 b.n 800b394 + } + + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + 800b366: 2300 movs r3, #0 + 800b368: 73fb strb r3, [r7, #15] + 800b36a: e00f b.n 800b38c + { + if ( bandwidth < FskBandwidths[i].bandwidth ) + 800b36c: 7bfb ldrb r3, [r7, #15] + 800b36e: 4a0c ldr r2, [pc, #48] ; (800b3a0 ) + 800b370: f852 3033 ldr.w r3, [r2, r3, lsl #3] + 800b374: 687a ldr r2, [r7, #4] + 800b376: 429a cmp r2, r3 + 800b378: d205 bcs.n 800b386 + { + return FskBandwidths[i].RegValue; + 800b37a: 7bfb ldrb r3, [r7, #15] + 800b37c: 4a08 ldr r2, [pc, #32] ; (800b3a0 ) + 800b37e: 00db lsls r3, r3, #3 + 800b380: 4413 add r3, r2 + 800b382: 791b ldrb r3, [r3, #4] + 800b384: e006 b.n 800b394 + for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ); i++ ) + 800b386: 7bfb ldrb r3, [r7, #15] + 800b388: 3301 adds r3, #1 + 800b38a: 73fb strb r3, [r7, #15] + 800b38c: 7bfb ldrb r3, [r7, #15] + 800b38e: 2b15 cmp r3, #21 + 800b390: d9ec bls.n 800b36c + } + } + // ERROR: Value not found + while( 1 ); + 800b392: e7fe b.n 800b392 +} + 800b394: 4618 mov r0, r3 + 800b396: 3714 adds r7, #20 + 800b398: 46bd mov sp, r7 + 800b39a: bc80 pop {r7} + 800b39c: 4770 bx lr + 800b39e: bf00 nop + 800b3a0: 0800e494 .word 0x0800e494 + +0800b3a4 : +void SUBGRF_GetCFO( uint32_t bitRate, int32_t *cfo) +{ + 800b3a4: b580 push {r7, lr} + 800b3a6: b08a sub sp, #40 ; 0x28 + 800b3a8: af00 add r7, sp, #0 + 800b3aa: 6078 str r0, [r7, #4] + 800b3ac: 6039 str r1, [r7, #0] + uint8_t BwMant[] = {4, 8, 10, 12}; + 800b3ae: 4b35 ldr r3, [pc, #212] ; (800b484 ) + 800b3b0: 60fb str r3, [r7, #12] + /* read demod bandwidth: mant bit4:3, exp bits 2:0 */ + uint8_t reg = (SUBGRF_ReadRegister( SUBGHZ_BWSELR )); + 800b3b2: f640 0007 movw r0, #2055 ; 0x807 + 800b3b6: f7ff fdc7 bl 800af48 + 800b3ba: 4603 mov r3, r0 + 800b3bc: 77fb strb r3, [r7, #31] + uint8_t bandwidth_mant = BwMant[( reg >> 3 ) & 0x3]; + 800b3be: 7ffb ldrb r3, [r7, #31] + 800b3c0: 08db lsrs r3, r3, #3 + 800b3c2: b2db uxtb r3, r3 + 800b3c4: f003 0303 and.w r3, r3, #3 + 800b3c8: 3328 adds r3, #40 ; 0x28 + 800b3ca: 443b add r3, r7 + 800b3cc: f813 3c1c ldrb.w r3, [r3, #-28] + 800b3d0: 77bb strb r3, [r7, #30] + uint8_t bandwidth_exp = reg & 0x7; + 800b3d2: 7ffb ldrb r3, [r7, #31] + 800b3d4: f003 0307 and.w r3, r3, #7 + 800b3d8: 777b strb r3, [r7, #29] + uint32_t cf_fs = XTAL_FREQ / ( bandwidth_mant * ( 1 << ( bandwidth_exp + 1 ))); + 800b3da: 7fba ldrb r2, [r7, #30] + 800b3dc: 7f7b ldrb r3, [r7, #29] + 800b3de: 3301 adds r3, #1 + 800b3e0: fa02 f303 lsl.w r3, r2, r3 + 800b3e4: 461a mov r2, r3 + 800b3e6: 4b28 ldr r3, [pc, #160] ; (800b488 ) + 800b3e8: fbb3 f3f2 udiv r3, r3, r2 + 800b3ec: 61bb str r3, [r7, #24] + uint32_t cf_osr = cf_fs / bitRate; + 800b3ee: 69ba ldr r2, [r7, #24] + 800b3f0: 687b ldr r3, [r7, #4] + 800b3f2: fbb2 f3f3 udiv r3, r2, r3 + 800b3f6: 617b str r3, [r7, #20] + uint8_t interp = 1; + 800b3f8: 2301 movs r3, #1 + 800b3fa: f887 3027 strb.w r3, [r7, #39] ; 0x27 + /* calculate demod interpolation factor */ + if (cf_osr * interp < 8) + 800b3fe: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800b402: 697a ldr r2, [r7, #20] + 800b404: fb02 f303 mul.w r3, r2, r3 + 800b408: 2b07 cmp r3, #7 + 800b40a: d802 bhi.n 800b412 + { + interp = 2; + 800b40c: 2302 movs r3, #2 + 800b40e: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + if (cf_osr * interp < 4) + 800b412: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 + 800b416: 697a ldr r2, [r7, #20] + 800b418: fb02 f303 mul.w r3, r2, r3 + 800b41c: 2b03 cmp r3, #3 + 800b41e: d802 bhi.n 800b426 + { + interp = 4; + 800b420: 2304 movs r3, #4 + 800b422: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + /* calculate demod sampling frequency */ + uint32_t fs = cf_fs* interp; + 800b426: f897 2027 ldrb.w r2, [r7, #39] ; 0x27 + 800b42a: 69bb ldr r3, [r7, #24] + 800b42c: fb02 f303 mul.w r3, r2, r3 + 800b430: 613b str r3, [r7, #16] + /* get the cfo registers */ + int32_t cfo_bin = ( SUBGRF_ReadRegister( SUBGHZ_GCFORH ) & 0xF ) << 8; + 800b432: f44f 60d6 mov.w r0, #1712 ; 0x6b0 + 800b436: f7ff fd87 bl 800af48 + 800b43a: 4603 mov r3, r0 + 800b43c: 021b lsls r3, r3, #8 + 800b43e: f403 6370 and.w r3, r3, #3840 ; 0xf00 + 800b442: 623b str r3, [r7, #32] + cfo_bin |= SUBGRF_ReadRegister( SUBGHZ_GCFORL ); + 800b444: f240 60b1 movw r0, #1713 ; 0x6b1 + 800b448: f7ff fd7e bl 800af48 + 800b44c: 4603 mov r3, r0 + 800b44e: 461a mov r2, r3 + 800b450: 6a3b ldr r3, [r7, #32] + 800b452: 4313 orrs r3, r2 + 800b454: 623b str r3, [r7, #32] + /* negate if 12 bits sign bit is 1 */ + if (( cfo_bin & 0x800 ) == 0x800 ) + 800b456: 6a3b ldr r3, [r7, #32] + 800b458: f403 6300 and.w r3, r3, #2048 ; 0x800 + 800b45c: 2b00 cmp r3, #0 + 800b45e: d005 beq.n 800b46c + { + cfo_bin |= 0xFFFFF000; + 800b460: 6a3b ldr r3, [r7, #32] + 800b462: ea6f 5303 mvn.w r3, r3, lsl #20 + 800b466: ea6f 5313 mvn.w r3, r3, lsr #20 + 800b46a: 623b str r3, [r7, #32] + } + /* calculate cfo in Hz */ + /* shift by 5 first to not saturate, cfo_bin on 12bits */ + *cfo = ((int32_t)( cfo_bin * ( fs >> 5 ))) >> ( 12 - 5 ); + 800b46c: 693b ldr r3, [r7, #16] + 800b46e: 095b lsrs r3, r3, #5 + 800b470: 6a3a ldr r2, [r7, #32] + 800b472: fb02 f303 mul.w r3, r2, r3 + 800b476: 11da asrs r2, r3, #7 + 800b478: 683b ldr r3, [r7, #0] + 800b47a: 601a str r2, [r3, #0] +} + 800b47c: bf00 nop + 800b47e: 3728 adds r7, #40 ; 0x28 + 800b480: 46bd mov sp, r7 + 800b482: bd80 pop {r7, pc} + 800b484: 0c0a0804 .word 0x0c0a0804 + 800b488: 01e84800 .word 0x01e84800 + +0800b48c : +#endif /* RFW_ENABLE == 1 */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RFW_TransmitLongPacket( uint16_t payload_size, uint32_t timeout, + void ( *TxLongPacketGetNextChunkCb )( uint8_t **buffer, uint8_t buffer_size ) ) +{ + 800b48c: b480 push {r7} + 800b48e: b087 sub sp, #28 + 800b490: af00 add r7, sp, #0 + 800b492: 4603 mov r3, r0 + 800b494: 60b9 str r1, [r7, #8] + 800b496: 607a str r2, [r7, #4] + 800b498: 81fb strh r3, [r7, #14] + int32_t status = 0; + 800b49a: 2300 movs r3, #0 + 800b49c: 617b str r3, [r7, #20] + default: + break; + } + } +#else + status = -1; + 800b49e: f04f 33ff mov.w r3, #4294967295 + 800b4a2: 617b str r3, [r7, #20] +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; + 800b4a4: 697b ldr r3, [r7, #20] +} + 800b4a6: 4618 mov r0, r3 + 800b4a8: 371c adds r7, #28 + 800b4aa: 46bd mov sp, r7 + 800b4ac: bc80 pop {r7} + 800b4ae: 4770 bx lr + +0800b4b0 : + +int32_t RFW_ReceiveLongPacket( uint8_t boosted_mode, uint32_t timeout, + void ( *RxLongPacketStoreChunkCb )( uint8_t *buffer, uint8_t chunk_size ) ) +{ + 800b4b0: b480 push {r7} + 800b4b2: b087 sub sp, #28 + 800b4b4: af00 add r7, sp, #0 + 800b4b6: 4603 mov r3, r0 + 800b4b8: 60b9 str r1, [r7, #8] + 800b4ba: 607a str r2, [r7, #4] + 800b4bc: 73fb strb r3, [r7, #15] + int32_t status = 0; + 800b4be: 2300 movs r3, #0 + 800b4c0: 617b str r3, [r7, #20] + { + SUBGRF_SetRx( 0xFFFFFF ); /* Rx Continuous */ + } + } +#else + status = -1; + 800b4c2: f04f 33ff mov.w r3, #4294967295 + 800b4c6: 617b str r3, [r7, #20] +#endif /* RFW_LONGPACKET_ENABLE == 1 */ + return status; + 800b4c8: 697b ldr r3, [r7, #20] +} + 800b4ca: 4618 mov r0, r3 + 800b4cc: 371c adds r7, #28 + 800b4ce: 46bd mov sp, r7 + 800b4d0: bc80 pop {r7} + 800b4d2: 4770 bx lr + +0800b4d4 : + +int32_t RFW_Init( ConfigGeneric_t *config, RadioEvents_t *RadioEvents, TimerEvent_t *TimeoutTimerEvent ) +{ + 800b4d4: b480 push {r7} + 800b4d6: b085 sub sp, #20 + 800b4d8: af00 add r7, sp, #0 + 800b4da: 60f8 str r0, [r7, #12] + 800b4dc: 60b9 str r1, [r7, #8] + 800b4de: 607a str r2, [r7, #4] + RFWPacket.Init.Enable = 1; + /* Initialize Timer for end of fixed packet, started at sync*/ + TimerInit( &RFWPacket.Timer, RFW_GetPayloadTimerEvent ); + return 0; +#else + return -1; + 800b4e0: f04f 33ff mov.w r3, #4294967295 +#endif /* RFW_ENABLE == 1 */ +} + 800b4e4: 4618 mov r0, r3 + 800b4e6: 3714 adds r7, #20 + 800b4e8: 46bd mov sp, r7 + 800b4ea: bc80 pop {r7} + 800b4ec: 4770 bx lr + +0800b4ee : + +void RFW_DeInit( void ) +{ + 800b4ee: b480 push {r7} + 800b4f0: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Enable = 0; /*Disable the RFWPacket decoding*/ +#endif /* RFW_ENABLE == 1 */ +} + 800b4f2: bf00 nop + 800b4f4: 46bd mov sp, r7 + 800b4f6: bc80 pop {r7} + 800b4f8: 4770 bx lr + +0800b4fa : + +uint8_t RFW_Is_Init( void ) +{ + 800b4fa: b480 push {r7} + 800b4fc: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + return RFWPacket.Init.Enable; +#else + return 0; + 800b4fe: 2300 movs r3, #0 +#endif /* RFW_ENABLE == 1 */ +} + 800b500: 4618 mov r0, r3 + 800b502: 46bd mov sp, r7 + 800b504: bc80 pop {r7} + 800b506: 4770 bx lr + +0800b508 : + +uint8_t RFW_Is_LongPacketModeEnabled( void ) +{ + 800b508: b480 push {r7} + 800b50a: af00 add r7, sp, #0 +#if (RFW_ENABLE == 1 ) + return RFWPacket.LongPacketModeEnable; +#else + return 0; + 800b50c: 2300 movs r3, #0 +#endif /* RFW_ENABLE == 1 */ +} + 800b50e: 4618 mov r0, r3 + 800b510: 46bd mov sp, r7 + 800b512: bc80 pop {r7} + 800b514: 4770 bx lr + +0800b516 : + +void RFW_SetAntSwitch( uint8_t AntSwitch ) +{ + 800b516: b480 push {r7} + 800b518: b083 sub sp, #12 + 800b51a: af00 add r7, sp, #0 + 800b51c: 4603 mov r3, r0 + 800b51e: 71fb strb r3, [r7, #7] +#if (RFW_ENABLE == 1 ) + RFWPacket.AntSwitchPaSelect = AntSwitch; +#endif /* RFW_ENABLE == 1 */ +} + 800b520: bf00 nop + 800b522: 370c adds r7, #12 + 800b524: 46bd mov sp, r7 + 800b526: bc80 pop {r7} + 800b528: 4770 bx lr + +0800b52a : + +int32_t RFW_TransmitInit( uint8_t *inOutBuffer, uint8_t size, uint8_t *outSize ) +{ + 800b52a: b480 push {r7} + 800b52c: b087 sub sp, #28 + 800b52e: af00 add r7, sp, #0 + 800b530: 60f8 str r0, [r7, #12] + 800b532: 460b mov r3, r1 + 800b534: 607a str r2, [r7, #4] + 800b536: 72fb strb r3, [r7, #11] + int32_t status = -1; + 800b538: f04f 33ff mov.w r3, #4294967295 + 800b53c: 617b str r3, [r7, #20] + RFWPacket.LongPacketModeEnable = 0; + + status = 0; + } +#endif /* RFW_ENABLE == 1 */ + return status; + 800b53e: 697b ldr r3, [r7, #20] +} + 800b540: 4618 mov r0, r3 + 800b542: 371c adds r7, #28 + 800b544: 46bd mov sp, r7 + 800b546: bc80 pop {r7} + 800b548: 4770 bx lr + +0800b54a : + +int32_t RFW_ReceiveInit( void ) +{ + 800b54a: b480 push {r7} + 800b54c: af00 add r7, sp, #0 + RFWPacket.RxPayloadOffset = 0; + + RFWPacket.LongPacketModeEnable = 0; + return 0; +#else + return -1; + 800b54e: f04f 33ff mov.w r3, #4294967295 +#endif /* RFW_ENABLE == 1 */ +} + 800b552: 4618 mov r0, r3 + 800b554: 46bd mov sp, r7 + 800b556: bc80 pop {r7} + 800b558: 4770 bx lr + +0800b55a : + +void RFW_DeInit_TxLongPacket( void ) +{ + 800b55a: b480 push {r7} + 800b55c: af00 add r7, sp, #0 + /*long packet WA*/ + uint8_t reg = SUBGRF_ReadRegister( SUBGHZ_GPKTCTL1AR ); + SUBGRF_WriteRegister( SUBGHZ_GPKTCTL1AR, reg & ~0x02 ); /* clear infinite_sequence bit */ + SUBGRF_WriteRegister( SUBGHZ_GRTXPLDLEN, 0xFF ); /* RxTxPldLen: reset to 0xFF */ +#endif /* RFW_LONGPACKET_ENABLE == 1 */ +} + 800b55e: bf00 nop + 800b560: 46bd mov sp, r7 + 800b562: bc80 pop {r7} + 800b564: 4770 bx lr + +0800b566 : + +void RFW_ReceivePayload( void ) +{ + 800b566: b480 push {r7} + 800b568: af00 add r7, sp, #0 + /*timeout*/ + SUBGRF_SetStandby( STDBY_RC ); + RFWPacket.Init.RadioEvents->RxTimeout( ); + } +#endif /* RFW_ENABLE == 1 */ +} + 800b56a: bf00 nop + 800b56c: 46bd mov sp, r7 + 800b56e: bc80 pop {r7} + 800b570: 4770 bx lr + +0800b572 : + +void RFW_SetRadioModem( RadioModems_t Modem ) +{ + 800b572: b480 push {r7} + 800b574: b083 sub sp, #12 + 800b576: af00 add r7, sp, #0 + 800b578: 4603 mov r3, r0 + 800b57a: 71fb strb r3, [r7, #7] +#if (RFW_ENABLE == 1 ) + RFWPacket.Init.Modem = Modem; +#endif /* RFW_ENABLE == 1 */ +} + 800b57c: bf00 nop + 800b57e: 370c adds r7, #12 + 800b580: 46bd mov sp, r7 + 800b582: bc80 pop {r7} + 800b584: 4770 bx lr + +0800b586 : + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + 800b586: b480 push {r7} + 800b588: af00 add r7, sp, #0 + SET_BIT(RCC->CSR, RCC_CSR_RMVF); + 800b58a: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800b58e: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800b592: f04f 42b0 mov.w r2, #1476395008 ; 0x58000000 + 800b596: f443 0300 orr.w r3, r3, #8388608 ; 0x800000 + 800b59a: f8c2 3094 str.w r3, [r2, #148] ; 0x94 +} + 800b59e: bf00 nop + 800b5a0: 46bd mov sp, r7 + 800b5a2: bc80 pop {r7} + 800b5a4: 4770 bx lr + ... + +0800b5a8 : +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ + +void MX_SubGHz_Phy_Init(void) +{ + 800b5a8: b580 push {r7, lr} + 800b5aa: b086 sub sp, #24 + 800b5ac: af04 add r7, sp, #16 + /* USER CODE BEGIN MX_SubGHz_Phy_Init_1 */ + uint32_t InitCounter = 1; + 800b5ae: 2301 movs r3, #1 + 800b5b0: 603b str r3, [r7, #0] + /* USER CODE END MX_SubGHz_Phy_Init_1 */ + SystemApp_Init(); + 800b5b2: f7f5 fb43 bl 8000c3c + /* USER CODE BEGIN MX_SubGHz_Phy_Init_1_1 */ + APP_LOG(TS_OFF, VLEVEL_M, "\n\rAPRS Demo\n\r"); + 800b5b6: 4b23 ldr r3, [pc, #140] ; (800b644 ) + 800b5b8: 2200 movs r2, #0 + 800b5ba: 2100 movs r1, #0 + 800b5bc: 2002 movs r0, #2 + 800b5be: f001 fa77 bl 800cab0 + + /* Get SubGHY_Phy APP version*/ + APP_LOG(TS_OFF, VLEVEL_M, "Application version:\tV%X.%X.%X\r\n", + 800b5c2: 2300 movs r3, #0 + 800b5c4: 9302 str r3, [sp, #8] + 800b5c6: 2303 movs r3, #3 + 800b5c8: 9301 str r3, [sp, #4] + 800b5ca: 2301 movs r3, #1 + 800b5cc: 9300 str r3, [sp, #0] + 800b5ce: 4b1e ldr r3, [pc, #120] ; (800b648 ) + 800b5d0: 2200 movs r2, #0 + 800b5d2: 2100 movs r1, #0 + 800b5d4: 2002 movs r0, #2 + 800b5d6: f001 fa6b bl 800cab0 + (uint8_t)(APP_VERSION_MAIN), + (uint8_t)(APP_VERSION_SUB1), + (uint8_t)(APP_VERSION_SUB2)); + /* USER CODE END MX_SubGHz_Phy_Init_1_1 */ + SubghzApp_Init(); + 800b5da: f000 f9e3 bl 800b9a4 + /* USER CODE BEGIN MX_SubGHz_Phy_Init_2 */ + + // Run the device initialization when a PoR or Pin reset has happened. + if (__HAL_RCC_GET_FLAG(RCC_FLAG_LPWRRST) || __HAL_RCC_GET_FLAG(RCC_FLAG_PINRST)) + 800b5de: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800b5e2: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800b5e6: 2b00 cmp r3, #0 + 800b5e8: db07 blt.n 800b5fa + 800b5ea: f04f 43b0 mov.w r3, #1476395008 ; 0x58000000 + 800b5ee: f8d3 3094 ldr.w r3, [r3, #148] ; 0x94 + 800b5f2: f003 6380 and.w r3, r3, #67108864 ; 0x4000000 + 800b5f6: 2b00 cmp r3, #0 + 800b5f8: d017 beq.n 800b62a + { + APP_LOG(TS_OFF, VLEVEL_M, "Device reset...\n\r"); + 800b5fa: 4b14 ldr r3, [pc, #80] ; (800b64c ) + 800b5fc: 2200 movs r2, #0 + 800b5fe: 2100 movs r1, #0 + 800b600: 2002 movs r0, #2 + 800b602: f001 fa55 bl 800cab0 + { + Error_Handler(); + } + } while (MX_USART1_GPS_Init() != HAL_OK); +*/ + APP_LOG(TS_OFF, VLEVEL_M, "Initialization successful!\n\r"); + 800b606: 4b12 ldr r3, [pc, #72] ; (800b650 ) + 800b608: 2200 movs r2, #0 + 800b60a: 2100 movs r1, #0 + 800b60c: 2002 movs r0, #2 + 800b60e: f001 fa4f bl 800cab0 + + for (uint8_t i = 0; i < 4; i++) + 800b612: 2300 movs r3, #0 + 800b614: 71fb strb r3, [r7, #7] + 800b616: e002 b.n 800b61e + 800b618: 79fb ldrb r3, [r7, #7] + 800b61a: 3301 adds r3, #1 + 800b61c: 71fb strb r3, [r7, #7] + 800b61e: 79fb ldrb r3, [r7, #7] + 800b620: 2b03 cmp r3, #3 + 800b622: d9f9 bls.n 800b618 + //HAL_Delay(100); + //HAL_GPIO_WritePin(GPIOB, LED1_Pin, GPIO_PIN_RESET); + //HAL_Delay(100); + } + + __HAL_RCC_CLEAR_RESET_FLAGS(); + 800b624: f7ff ffaf bl 800b586 + 800b628: e008 b.n 800b63c + } + else + { + APP_LOG(TS_OFF, VLEVEL_M, "Wake up\n\r"); + 800b62a: 4b0a ldr r3, [pc, #40] ; (800b654 ) + 800b62c: 2200 movs r2, #0 + 800b62e: 2100 movs r1, #0 + 800b630: 2002 movs r0, #2 + 800b632: f001 fa3d bl 800cab0 + MX_USART1_GPS_WakeUp(); + 800b636: f7f6 f8c3 bl 80017c0 + } + + /* USER CODE END MX_SubGHz_Phy_Init_2 */ +} + 800b63a: bf00 nop + 800b63c: bf00 nop + 800b63e: 3708 adds r7, #8 + 800b640: 46bd mov sp, r7 + 800b642: bd80 pop {r7, pc} + 800b644: 0800e0b0 .word 0x0800e0b0 + 800b648: 0800e0c0 .word 0x0800e0c0 + 800b64c: 0800e0e4 .word 0x0800e0e4 + 800b650: 0800e0f8 .word 0x0800e0f8 + 800b654: 0800e118 .word 0x0800e118 + +0800b658 : + +void MX_SubGHz_Phy_Process(void) +{ + 800b658: b580 push {r7, lr} + 800b65a: b0ae sub sp, #184 ; 0xb8 + 800b65c: af02 add r7, sp, #8 + /* USER CODE BEGIN MX_SubGHz_Phy_Process_1 */ + int32_t Status; + char LineBuffer[128]; + GPS_GPGGA_t GPGGA_Data; + + memset(&GPGGA_Data, 0, sizeof(GPGGA_Data)); + 800b65e: 463b mov r3, r7 + 800b660: 2225 movs r2, #37 ; 0x25 + 800b662: 2100 movs r1, #0 + 800b664: 4618 mov r0, r3 + 800b666: f001 fda0 bl 800d1aa + + Status = MX_USART1_GPS_GetNMEA(LineBuffer, sizeof(LineBuffer)); + 800b66a: f107 0328 add.w r3, r7, #40 ; 0x28 + 800b66e: 2180 movs r1, #128 ; 0x80 + 800b670: 4618 mov r0, r3 + 800b672: f7f6 f8af bl 80017d4 + 800b676: f8c7 00ac str.w r0, [r7, #172] ; 0xac + if (Status == HAL_OK) + 800b67a: f8d7 30ac ldr.w r3, [r7, #172] ; 0xac + 800b67e: 2b00 cmp r3, #0 + 800b680: f040 80a9 bne.w 800b7d6 + { + APP_LOG(TS_OFF, VLEVEL_M, "Message: %s\n\r", LineBuffer); + 800b684: f107 0328 add.w r3, r7, #40 ; 0x28 + 800b688: 9300 str r3, [sp, #0] + 800b68a: 4b57 ldr r3, [pc, #348] ; (800b7e8 ) + 800b68c: 2200 movs r2, #0 + 800b68e: 2100 movs r1, #0 + 800b690: 2002 movs r0, #2 + 800b692: f001 fa0d bl 800cab0 + + // Format: $GPGGA,174857.000,4932.1285,N,01046.6422,E,2,9,0.90,388.3,M,47.9,M,,*5E + if (strstr(LineBuffer, "$GPGGA") != NULL) + 800b696: f107 0328 add.w r3, r7, #40 ; 0x28 + 800b69a: 4954 ldr r1, [pc, #336] ; (800b7ec ) + 800b69c: 4618 mov r0, r3 + 800b69e: f001 fde9 bl 800d274 + 800b6a2: 4603 mov r3, r0 + 800b6a4: 2b00 cmp r3, #0 + 800b6a6: f000 8096 beq.w 800b7d6 + { + char* Token; + + // Fetch and discard the header + strtok(LineBuffer, ","); + 800b6aa: f107 0328 add.w r3, r7, #40 ; 0x28 + 800b6ae: 4950 ldr r1, [pc, #320] ; (800b7f0 ) + 800b6b0: 4618 mov r0, r3 + 800b6b2: f001 fd83 bl 800d1bc + + Token = strtok(NULL, ","); + 800b6b6: 494e ldr r1, [pc, #312] ; (800b7f0 ) + 800b6b8: 2000 movs r0, #0 + 800b6ba: f001 fd7f bl 800d1bc + 800b6be: f8c7 00a8 str.w r0, [r7, #168] ; 0xa8 + memcpy(&GPGGA_Data.utc, Token, strlen(Token)); + 800b6c2: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 + 800b6c6: f7f4 fd5b bl 8000180 + 800b6ca: 4602 mov r2, r0 + 800b6cc: 463b mov r3, r7 + 800b6ce: f8d7 10a8 ldr.w r1, [r7, #168] ; 0xa8 + 800b6d2: 4618 mov r0, r3 + 800b6d4: f001 fe57 bl 800d386 + Token = strtok(NULL, ","); + 800b6d8: 4945 ldr r1, [pc, #276] ; (800b7f0 ) + 800b6da: 2000 movs r0, #0 + 800b6dc: f001 fd6e bl 800d1bc + 800b6e0: f8c7 00a8 str.w r0, [r7, #168] ; 0xa8 + memcpy(&GPGGA_Data.lat, Token, strlen(Token)); + 800b6e4: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 + 800b6e8: f7f4 fd4a bl 8000180 + 800b6ec: 4602 mov r2, r0 + 800b6ee: 463b mov r3, r7 + 800b6f0: 330b adds r3, #11 + 800b6f2: f8d7 10a8 ldr.w r1, [r7, #168] ; 0xa8 + 800b6f6: 4618 mov r0, r3 + 800b6f8: f001 fe45 bl 800d386 + Token = strtok(NULL, ","); + 800b6fc: 493c ldr r1, [pc, #240] ; (800b7f0 ) + 800b6fe: 2000 movs r0, #0 + 800b700: f001 fd5c bl 800d1bc + 800b704: f8c7 00a8 str.w r0, [r7, #168] ; 0xa8 + memcpy(&GPGGA_Data.lat_dir, Token, strlen(Token)); + 800b708: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 + 800b70c: f7f4 fd38 bl 8000180 + 800b710: 4602 mov r2, r0 + 800b712: 463b mov r3, r7 + 800b714: 3315 adds r3, #21 + 800b716: f8d7 10a8 ldr.w r1, [r7, #168] ; 0xa8 + 800b71a: 4618 mov r0, r3 + 800b71c: f001 fe33 bl 800d386 + Token = strtok(NULL, ","); + 800b720: 4933 ldr r1, [pc, #204] ; (800b7f0 ) + 800b722: 2000 movs r0, #0 + 800b724: f001 fd4a bl 800d1bc + 800b728: f8c7 00a8 str.w r0, [r7, #168] ; 0xa8 + memcpy(&GPGGA_Data.lon, Token, strlen(Token)); + 800b72c: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 + 800b730: f7f4 fd26 bl 8000180 + 800b734: 4602 mov r2, r0 + 800b736: 463b mov r3, r7 + 800b738: 3317 adds r3, #23 + 800b73a: f8d7 10a8 ldr.w r1, [r7, #168] ; 0xa8 + 800b73e: 4618 mov r0, r3 + 800b740: f001 fe21 bl 800d386 + Token = strtok(NULL, ","); + 800b744: 492a ldr r1, [pc, #168] ; (800b7f0 ) + 800b746: 2000 movs r0, #0 + 800b748: f001 fd38 bl 800d1bc + 800b74c: f8c7 00a8 str.w r0, [r7, #168] ; 0xa8 + memcpy(&GPGGA_Data.lon_dir, Token, strlen(Token)); + 800b750: f8d7 00a8 ldr.w r0, [r7, #168] ; 0xa8 + 800b754: f7f4 fd14 bl 8000180 + 800b758: 4602 mov r2, r0 + 800b75a: 463b mov r3, r7 + 800b75c: 3322 adds r3, #34 ; 0x22 + 800b75e: f8d7 10a8 ldr.w r1, [r7, #168] ; 0xa8 + 800b762: 4618 mov r0, r3 + 800b764: f001 fe0f bl 800d386 + + APP_LOG(TS_OFF, VLEVEL_M, "\tUTC: %s\n\r", GPGGA_Data.utc); + 800b768: 463b mov r3, r7 + 800b76a: 9300 str r3, [sp, #0] + 800b76c: 4b21 ldr r3, [pc, #132] ; (800b7f4 ) + 800b76e: 2200 movs r2, #0 + 800b770: 2100 movs r1, #0 + 800b772: 2002 movs r0, #2 + 800b774: f001 f99c bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLatitude: %s\n\r", GPGGA_Data.lat); + 800b778: 463b mov r3, r7 + 800b77a: 330b adds r3, #11 + 800b77c: 9300 str r3, [sp, #0] + 800b77e: 4b1e ldr r3, [pc, #120] ; (800b7f8 ) + 800b780: 2200 movs r2, #0 + 800b782: 2100 movs r1, #0 + 800b784: 2002 movs r0, #2 + 800b786: f001 f993 bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLatitude direction: %s\n\r", GPGGA_Data.lat_dir); + 800b78a: 463b mov r3, r7 + 800b78c: 3315 adds r3, #21 + 800b78e: 9300 str r3, [sp, #0] + 800b790: 4b1a ldr r3, [pc, #104] ; (800b7fc ) + 800b792: 2200 movs r2, #0 + 800b794: 2100 movs r1, #0 + 800b796: 2002 movs r0, #2 + 800b798: f001 f98a bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLongitude: %s\n\r", GPGGA_Data.lon); + 800b79c: 463b mov r3, r7 + 800b79e: 3317 adds r3, #23 + 800b7a0: 9300 str r3, [sp, #0] + 800b7a2: 4b17 ldr r3, [pc, #92] ; (800b800 ) + 800b7a4: 2200 movs r2, #0 + 800b7a6: 2100 movs r1, #0 + 800b7a8: 2002 movs r0, #2 + 800b7aa: f001 f981 bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLongitude direction: %s\n\r", GPGGA_Data.lon_dir); + 800b7ae: 463b mov r3, r7 + 800b7b0: 3322 adds r3, #34 ; 0x22 + 800b7b2: 9300 str r3, [sp, #0] + 800b7b4: 4b13 ldr r3, [pc, #76] ; (800b804 ) + 800b7b6: 2200 movs r2, #0 + 800b7b8: 2100 movs r1, #0 + 800b7ba: 2002 movs r0, #2 + 800b7bc: f001 f978 bl 800cab0 + MX_SubGHz_Phy_APRS_Send(&GPGGA_Data, APRS_Callsign, "Test123"); + 800b7c0: 463b mov r3, r7 + 800b7c2: 4a11 ldr r2, [pc, #68] ; (800b808 ) + 800b7c4: 4911 ldr r1, [pc, #68] ; (800b80c ) + 800b7c6: 4618 mov r0, r3 + 800b7c8: f000 f842 bl 800b850 + HAL_Delay(100); + 800b7cc: 2064 movs r0, #100 ; 0x64 + 800b7ce: f7f5 fab9 bl 8000d44 + + MX_SubGHz_Phy_EnterSleep(); + 800b7d2: f000 f81d bl 800b810 + } + } + + /* USER CODE END MX_SubGHz_Phy_Process_1 */ + UTIL_SEQ_Run(UTIL_SEQ_DEFAULT); + 800b7d6: f04f 30ff mov.w r0, #4294967295 + 800b7da: f000 fdfb bl 800c3d4 + /* USER CODE BEGIN MX_SubGHz_Phy_Process_2 */ + + /* USER CODE END MX_SubGHz_Phy_Process_2 */ +} + 800b7de: bf00 nop + 800b7e0: 37b0 adds r7, #176 ; 0xb0 + 800b7e2: 46bd mov sp, r7 + 800b7e4: bd80 pop {r7, pc} + 800b7e6: bf00 nop + 800b7e8: 0800e124 .word 0x0800e124 + 800b7ec: 0800e134 .word 0x0800e134 + 800b7f0: 0800e13c .word 0x0800e13c + 800b7f4: 0800e140 .word 0x0800e140 + 800b7f8: 0800e14c .word 0x0800e14c + 800b7fc: 0800e15c .word 0x0800e15c + 800b800: 0800e178 .word 0x0800e178 + 800b804: 0800e18c .word 0x0800e18c + 800b808: 0800e1a8 .word 0x0800e1a8 + 800b80c: 2000000c .word 0x2000000c + +0800b810 : + +/* Private Functions Definition -----------------------------------------------*/ +/* USER CODE BEGIN PrFD */ + +void MX_SubGHz_Phy_EnterSleep(void) +{ + 800b810: b580 push {r7, lr} + 800b812: b082 sub sp, #8 + 800b814: af00 add r7, sp, #0 + UART_WakeUpTypeDef WakeUpSelection; + + SubghzApp_Sleep(); + 800b816: f000 f993 bl 800bb40 + + MX_USART1_GPS_Sleep(); + 800b81a: f7f5 ffad bl 8001778 + + // Set the wake-up event + WakeUpSelection.WakeUpEvent = UART_WAKEUP_ON_READDATA_NONEMPTY; + 800b81e: f44f 1340 mov.w r3, #3145728 ; 0x300000 + 800b822: 603b str r3, [r7, #0] + if (HAL_UARTEx_StopModeWakeUpSourceConfig(&hlpuart1, WakeUpSelection) != HAL_OK) + 800b824: 463b mov r3, r7 + 800b826: e893 0006 ldmia.w r3, {r1, r2} + 800b82a: 4808 ldr r0, [pc, #32] ; (800b84c ) + 800b82c: f7fc fa6d bl 8007d0a + 800b830: 4603 mov r3, r0 + 800b832: 2b00 cmp r3, #0 + 800b834: d001 beq.n 800b83a + { + Error_Handler(); + 800b836: f7f5 f865 bl 8000904 + } + + HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI); + 800b83a: 2101 movs r1, #1 + 800b83c: f44f 4080 mov.w r0, #16384 ; 0x4000 + 800b840: f7f7 fcac bl 800319c +} + 800b844: bf00 nop + 800b846: 3708 adds r7, #8 + 800b848: 46bd mov sp, r7 + 800b84a: bd80 pop {r7, pc} + 800b84c: 20000164 .word 0x20000164 + +0800b850 : + +int32_t MX_SubGHz_Phy_APRS_Send(GPS_GPGGA_t* p_Position, char* p_Challsign, char* p_Message) +{ + 800b850: b590 push {r4, r7, lr} + 800b852: b087 sub sp, #28 + 800b854: af00 add r7, sp, #0 + 800b856: 60f8 str r0, [r7, #12] + 800b858: 60b9 str r1, [r7, #8] + 800b85a: 607a str r2, [r7, #4] + uint8_t TotalLength = 0; + 800b85c: 2300 movs r3, #0 + 800b85e: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], APRS_Header, sizeof(APRS_Header)); + 800b860: 7dfb ldrb r3, [r7, #23] + 800b862: 4a4d ldr r2, [pc, #308] ; (800b998 ) + 800b864: 4413 add r3, r2 + 800b866: 4a4d ldr r2, [pc, #308] ; (800b99c ) + 800b868: 8811 ldrh r1, [r2, #0] + 800b86a: 7892 ldrb r2, [r2, #2] + 800b86c: 8019 strh r1, [r3, #0] + 800b86e: 709a strb r2, [r3, #2] + TotalLength += sizeof(APRS_Header); + 800b870: 7dfb ldrb r3, [r7, #23] + 800b872: 3303 adds r3, #3 + 800b874: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], p_Challsign, strlen(p_Challsign)); + 800b876: 7dfb ldrb r3, [r7, #23] + 800b878: 4a47 ldr r2, [pc, #284] ; (800b998 ) + 800b87a: 189c adds r4, r3, r2 + 800b87c: 68b8 ldr r0, [r7, #8] + 800b87e: f7f4 fc7f bl 8000180 + 800b882: 4603 mov r3, r0 + 800b884: 461a mov r2, r3 + 800b886: 68b9 ldr r1, [r7, #8] + 800b888: 4620 mov r0, r4 + 800b88a: f001 fd7c bl 800d386 + TotalLength += strlen(p_Challsign); + 800b88e: 68b8 ldr r0, [r7, #8] + 800b890: f7f4 fc76 bl 8000180 + 800b894: 4603 mov r3, r0 + 800b896: b2da uxtb r2, r3 + 800b898: 7dfb ldrb r3, [r7, #23] + 800b89a: 4413 add r3, r2 + 800b89c: 75fb strb r3, [r7, #23] + + APRS_TransmitBuffer[TotalLength] = '>'; + 800b89e: 7dfb ldrb r3, [r7, #23] + 800b8a0: 4a3d ldr r2, [pc, #244] ; (800b998 ) + 800b8a2: 213e movs r1, #62 ; 0x3e + 800b8a4: 54d1 strb r1, [r2, r3] + TotalLength += 1; + 800b8a6: 7dfb ldrb r3, [r7, #23] + 800b8a8: 3301 adds r3, #1 + 800b8aa: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], APRS_Destination, strlen(APRS_Destination)); + 800b8ac: 7dfb ldrb r3, [r7, #23] + 800b8ae: 4a3a ldr r2, [pc, #232] ; (800b998 ) + 800b8b0: 189c adds r4, r3, r2 + 800b8b2: 483b ldr r0, [pc, #236] ; (800b9a0 ) + 800b8b4: f7f4 fc64 bl 8000180 + 800b8b8: 4603 mov r3, r0 + 800b8ba: 461a mov r2, r3 + 800b8bc: 4938 ldr r1, [pc, #224] ; (800b9a0 ) + 800b8be: 4620 mov r0, r4 + 800b8c0: f001 fd61 bl 800d386 + TotalLength += strlen(APRS_Destination); + 800b8c4: 4836 ldr r0, [pc, #216] ; (800b9a0 ) + 800b8c6: f7f4 fc5b bl 8000180 + 800b8ca: 4603 mov r3, r0 + 800b8cc: b2da uxtb r2, r3 + 800b8ce: 7dfb ldrb r3, [r7, #23] + 800b8d0: 4413 add r3, r2 + 800b8d2: 75fb strb r3, [r7, #23] + + APRS_TransmitBuffer[TotalLength] = ':'; + 800b8d4: 7dfb ldrb r3, [r7, #23] + 800b8d6: 4a30 ldr r2, [pc, #192] ; (800b998 ) + 800b8d8: 213a movs r1, #58 ; 0x3a + 800b8da: 54d1 strb r1, [r2, r3] + TotalLength += 1; + 800b8dc: 7dfb ldrb r3, [r7, #23] + 800b8de: 3301 adds r3, #1 + 800b8e0: 75fb strb r3, [r7, #23] + + APRS_TransmitBuffer[TotalLength] = '!'; + 800b8e2: 7dfb ldrb r3, [r7, #23] + 800b8e4: 4a2c ldr r2, [pc, #176] ; (800b998 ) + 800b8e6: 2121 movs r1, #33 ; 0x21 + 800b8e8: 54d1 strb r1, [r2, r3] + TotalLength += 1; + 800b8ea: 7dfb ldrb r3, [r7, #23] + 800b8ec: 3301 adds r3, #1 + 800b8ee: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], p_Position->lat, 7); + 800b8f0: 7dfb ldrb r3, [r7, #23] + 800b8f2: 4a29 ldr r2, [pc, #164] ; (800b998 ) + 800b8f4: 1898 adds r0, r3, r2 + 800b8f6: 68fb ldr r3, [r7, #12] + 800b8f8: 330b adds r3, #11 + 800b8fa: 2207 movs r2, #7 + 800b8fc: 4619 mov r1, r3 + 800b8fe: f001 fd42 bl 800d386 + TotalLength += 7; + 800b902: 7dfb ldrb r3, [r7, #23] + 800b904: 3307 adds r3, #7 + 800b906: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], p_Position->lat_dir, 1); + 800b908: 7dfb ldrb r3, [r7, #23] + 800b90a: 4a23 ldr r2, [pc, #140] ; (800b998 ) + 800b90c: 4413 add r3, r2 + 800b90e: 68fa ldr r2, [r7, #12] + 800b910: 3215 adds r2, #21 + 800b912: 7812 ldrb r2, [r2, #0] + 800b914: 701a strb r2, [r3, #0] + TotalLength += 1; + 800b916: 7dfb ldrb r3, [r7, #23] + 800b918: 3301 adds r3, #1 + 800b91a: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], p_Position->lon, 8); + 800b91c: 7dfb ldrb r3, [r7, #23] + 800b91e: 4a1e ldr r2, [pc, #120] ; (800b998 ) + 800b920: 1898 adds r0, r3, r2 + 800b922: 68fb ldr r3, [r7, #12] + 800b924: 3317 adds r3, #23 + 800b926: 2208 movs r2, #8 + 800b928: 4619 mov r1, r3 + 800b92a: f001 fd2c bl 800d386 + TotalLength += 8; + 800b92e: 7dfb ldrb r3, [r7, #23] + 800b930: 3308 adds r3, #8 + 800b932: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], p_Position->lon_dir, 1); + 800b934: 7dfb ldrb r3, [r7, #23] + 800b936: 4a18 ldr r2, [pc, #96] ; (800b998 ) + 800b938: 4413 add r3, r2 + 800b93a: 68fa ldr r2, [r7, #12] + 800b93c: 3222 adds r2, #34 ; 0x22 + 800b93e: 7812 ldrb r2, [r2, #0] + 800b940: 701a strb r2, [r3, #0] + TotalLength += 1; + 800b942: 7dfb ldrb r3, [r7, #23] + 800b944: 3301 adds r3, #1 + 800b946: 75fb strb r3, [r7, #23] + + if (p_Message != NULL) + 800b948: 687b ldr r3, [r7, #4] + 800b94a: 2b00 cmp r3, #0 + 800b94c: d01a beq.n 800b984 + { + APRS_TransmitBuffer[TotalLength] = '&'; + 800b94e: 7dfb ldrb r3, [r7, #23] + 800b950: 4a11 ldr r2, [pc, #68] ; (800b998 ) + 800b952: 2126 movs r1, #38 ; 0x26 + 800b954: 54d1 strb r1, [r2, r3] + TotalLength += 1; + 800b956: 7dfb ldrb r3, [r7, #23] + 800b958: 3301 adds r3, #1 + 800b95a: 75fb strb r3, [r7, #23] + + memcpy(&APRS_TransmitBuffer[TotalLength], p_Message, strlen(p_Message)); + 800b95c: 7dfb ldrb r3, [r7, #23] + 800b95e: 4a0e ldr r2, [pc, #56] ; (800b998 ) + 800b960: 189c adds r4, r3, r2 + 800b962: 6878 ldr r0, [r7, #4] + 800b964: f7f4 fc0c bl 8000180 + 800b968: 4603 mov r3, r0 + 800b96a: 461a mov r2, r3 + 800b96c: 6879 ldr r1, [r7, #4] + 800b96e: 4620 mov r0, r4 + 800b970: f001 fd09 bl 800d386 + TotalLength += strlen(p_Message); + 800b974: 6878 ldr r0, [r7, #4] + 800b976: f7f4 fc03 bl 8000180 + 800b97a: 4603 mov r3, r0 + 800b97c: b2da uxtb r2, r3 + 800b97e: 7dfb ldrb r3, [r7, #23] + 800b980: 4413 add r3, r2 + 800b982: 75fb strb r3, [r7, #23] + } + + return SubghzApp_Transmit(APRS_TransmitBuffer, TotalLength); + 800b984: 7dfb ldrb r3, [r7, #23] + 800b986: 4619 mov r1, r3 + 800b988: 4803 ldr r0, [pc, #12] ; (800b998 ) + 800b98a: f000 f8b3 bl 800baf4 + 800b98e: 4603 mov r3, r0 +} + 800b990: 4618 mov r0, r3 + 800b992: 371c adds r7, #28 + 800b994: 46bd mov sp, r7 + 800b996: bd90 pop {r4, r7, pc} + 800b998: 2000049c .word 0x2000049c + 800b99c: 20000020 .word 0x20000020 + 800b9a0: 20000018 .word 0x20000018 + +0800b9a4 : +/* USER CODE BEGIN PFP */ +/* USER CODE END PFP */ + +/* Exported functions ---------------------------------------------------------*/ +void SubghzApp_Init(void) +{ + 800b9a4: b590 push {r4, r7, lr} + 800b9a6: b08b sub sp, #44 ; 0x2c + 800b9a8: af0a add r7, sp, #40 ; 0x28 + /* USER CODE BEGIN SubghzApp_Init_1 */ + /* Get MW SubGhz_Phy info */ + APP_LOG(TS_OFF, VLEVEL_M, "Radio version:\tV%X.%X.%X\r\n", + 800b9aa: 2300 movs r3, #0 + 800b9ac: 9302 str r3, [sp, #8] + 800b9ae: 2303 movs r3, #3 + 800b9b0: 9301 str r3, [sp, #4] + 800b9b2: 2301 movs r3, #1 + 800b9b4: 9300 str r3, [sp, #0] + 800b9b6: 4b41 ldr r3, [pc, #260] ; (800babc ) + 800b9b8: 2200 movs r2, #0 + 800b9ba: 2100 movs r1, #0 + 800b9bc: 2002 movs r0, #2 + 800b9be: f001 f877 bl 800cab0 + (uint8_t)(SUBGHZ_PHY_VERSION_SUB1), + (uint8_t)(SUBGHZ_PHY_VERSION_SUB2)); + /* USER CODE END SubghzApp_Init_1 */ + + /* Radio initialization */ + RadioEvents.TxDone = OnTxDone; + 800b9c2: 4b3f ldr r3, [pc, #252] ; (800bac0 ) + 800b9c4: 4a3f ldr r2, [pc, #252] ; (800bac4 ) + 800b9c6: 601a str r2, [r3, #0] + RadioEvents.RxDone = OnRxDone; + 800b9c8: 4b3d ldr r3, [pc, #244] ; (800bac0 ) + 800b9ca: 4a3f ldr r2, [pc, #252] ; (800bac8 ) + 800b9cc: 609a str r2, [r3, #8] + RadioEvents.TxTimeout = OnTxTimeout; + 800b9ce: 4b3c ldr r3, [pc, #240] ; (800bac0 ) + 800b9d0: 4a3e ldr r2, [pc, #248] ; (800bacc ) + 800b9d2: 605a str r2, [r3, #4] + RadioEvents.RxTimeout = OnRxTimeout; + 800b9d4: 4b3a ldr r3, [pc, #232] ; (800bac0 ) + 800b9d6: 4a3e ldr r2, [pc, #248] ; (800bad0 ) + 800b9d8: 60da str r2, [r3, #12] + RadioEvents.RxError = OnRxError; + 800b9da: 4b39 ldr r3, [pc, #228] ; (800bac0 ) + 800b9dc: 4a3d ldr r2, [pc, #244] ; (800bad4 ) + 800b9de: 611a str r2, [r3, #16] + + Radio.Init(&RadioEvents); + 800b9e0: 4b3d ldr r3, [pc, #244] ; (800bad8 ) + 800b9e2: 681b ldr r3, [r3, #0] + 800b9e4: 4836 ldr r0, [pc, #216] ; (800bac0 ) + 800b9e6: 4798 blx r3 + + /* USER CODE BEGIN SubghzApp_Init_2 */ + /* Radio Set frequency */ + Radio.SetChannel(RF_FREQUENCY); + 800b9e8: 4b3b ldr r3, [pc, #236] ; (800bad8 ) + 800b9ea: 68db ldr r3, [r3, #12] + 800b9ec: 483b ldr r0, [pc, #236] ; (800badc ) + 800b9ee: 4798 blx r3 + + /* Radio configuration */ + APP_LOG(TS_OFF, VLEVEL_M, "\n\r"); + 800b9f0: 4b3b ldr r3, [pc, #236] ; (800bae0 ) + 800b9f2: 2200 movs r2, #0 + 800b9f4: 2100 movs r1, #0 + 800b9f6: 2002 movs r0, #2 + 800b9f8: f001 f85a bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "Radio settings\n\r"); + 800b9fc: 4b39 ldr r3, [pc, #228] ; (800bae4 ) + 800b9fe: 2200 movs r2, #0 + 800ba00: 2100 movs r1, #0 + 800ba02: 2002 movs r0, #2 + 800ba04: f001 f854 bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLoRa Bandwidth: %d kHz\n\r", (1 << LORA_BANDWIDTH) * 125); + 800ba08: 237d movs r3, #125 ; 0x7d + 800ba0a: 9300 str r3, [sp, #0] + 800ba0c: 4b36 ldr r3, [pc, #216] ; (800bae8 ) + 800ba0e: 2200 movs r2, #0 + 800ba10: 2100 movs r1, #0 + 800ba12: 2002 movs r0, #2 + 800ba14: f001 f84c bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLoRa Spreading factor: %d\n\r", LORA_SPREADING_FACTOR); + 800ba18: 230c movs r3, #12 + 800ba1a: 9300 str r3, [sp, #0] + 800ba1c: 4b33 ldr r3, [pc, #204] ; (800baec ) + 800ba1e: 2200 movs r2, #0 + 800ba20: 2100 movs r1, #0 + 800ba22: 2002 movs r0, #2 + 800ba24: f001 f844 bl 800cab0 + APP_LOG(TS_OFF, VLEVEL_M, "\tLoRa Frequency: %d\n\r", RF_FREQUENCY); + 800ba28: 4b2c ldr r3, [pc, #176] ; (800badc ) + 800ba2a: 9300 str r3, [sp, #0] + 800ba2c: 4b30 ldr r3, [pc, #192] ; (800baf0 ) + 800ba2e: 2200 movs r2, #0 + 800ba30: 2100 movs r1, #0 + 800ba32: 2002 movs r0, #2 + 800ba34: f001 f83c bl 800cab0 + + Radio.SetTxConfig(MODEM_LORA, TX_OUTPUT_POWER, 0, LORA_BANDWIDTH, + 800ba38: 4b27 ldr r3, [pc, #156] ; (800bad8 ) + 800ba3a: 69dc ldr r4, [r3, #28] + 800ba3c: f640 33b8 movw r3, #3000 ; 0xbb8 + 800ba40: 9308 str r3, [sp, #32] + 800ba42: 2300 movs r3, #0 + 800ba44: 9307 str r3, [sp, #28] + 800ba46: 2300 movs r3, #0 + 800ba48: 9306 str r3, [sp, #24] + 800ba4a: 2300 movs r3, #0 + 800ba4c: 9305 str r3, [sp, #20] + 800ba4e: 2301 movs r3, #1 + 800ba50: 9304 str r3, [sp, #16] + 800ba52: 2300 movs r3, #0 + 800ba54: 9303 str r3, [sp, #12] + 800ba56: 2308 movs r3, #8 + 800ba58: 9302 str r3, [sp, #8] + 800ba5a: 2301 movs r3, #1 + 800ba5c: 9301 str r3, [sp, #4] + 800ba5e: 230c movs r3, #12 + 800ba60: 9300 str r3, [sp, #0] + 800ba62: 2300 movs r3, #0 + 800ba64: 2200 movs r2, #0 + 800ba66: 210e movs r1, #14 + 800ba68: 2001 movs r0, #1 + 800ba6a: 47a0 blx r4 + LORA_SPREADING_FACTOR, LORA_CODINGRATE, + LORA_PREAMBLE_LENGTH, LORA_FIX_LENGTH_PAYLOAD_ON, + true, 0, 0, LORA_IQ_INVERSION_ON, 3000); + + Radio.SetRxConfig(MODEM_LORA, LORA_BANDWIDTH, LORA_SPREADING_FACTOR, + 800ba6c: 4b1a ldr r3, [pc, #104] ; (800bad8 ) + 800ba6e: 699c ldr r4, [r3, #24] + 800ba70: 2301 movs r3, #1 + 800ba72: 9309 str r3, [sp, #36] ; 0x24 + 800ba74: 2300 movs r3, #0 + 800ba76: 9308 str r3, [sp, #32] + 800ba78: 2300 movs r3, #0 + 800ba7a: 9307 str r3, [sp, #28] + 800ba7c: 2300 movs r3, #0 + 800ba7e: 9306 str r3, [sp, #24] + 800ba80: 2301 movs r3, #1 + 800ba82: 9305 str r3, [sp, #20] + 800ba84: 2300 movs r3, #0 + 800ba86: 9304 str r3, [sp, #16] + 800ba88: 2300 movs r3, #0 + 800ba8a: 9303 str r3, [sp, #12] + 800ba8c: 2305 movs r3, #5 + 800ba8e: 9302 str r3, [sp, #8] + 800ba90: 2308 movs r3, #8 + 800ba92: 9301 str r3, [sp, #4] + 800ba94: 2300 movs r3, #0 + 800ba96: 9300 str r3, [sp, #0] + 800ba98: 2301 movs r3, #1 + 800ba9a: 220c movs r2, #12 + 800ba9c: 2100 movs r1, #0 + 800ba9e: 2001 movs r0, #1 + 800baa0: 47a0 blx r4 + LORA_CODINGRATE, 0, LORA_PREAMBLE_LENGTH, + LORA_SYMBOL_TIMEOUT, LORA_FIX_LENGTH_PAYLOAD_ON, + 0, true, 0, 0, LORA_IQ_INVERSION_ON, true); + + Radio.SetMaxPayloadLength(MODEM_LORA, MAX_APP_BUFFER_SIZE); + 800baa2: 4b0d ldr r3, [pc, #52] ; (800bad8 ) + 800baa4: 6d5b ldr r3, [r3, #84] ; 0x54 + 800baa6: 21ff movs r1, #255 ; 0xff + 800baa8: 2001 movs r0, #1 + 800baaa: 4798 blx r3 + Radio.Sleep(); + 800baac: 4b0a ldr r3, [pc, #40] ; (800bad8 ) + 800baae: 6adb ldr r3, [r3, #44] ; 0x2c + 800bab0: 4798 blx r3 + /* USER CODE END SubghzApp_Init_2 */ +} + 800bab2: bf00 nop + 800bab4: 3704 adds r7, #4 + 800bab6: 46bd mov sp, r7 + 800bab8: bd90 pop {r4, r7, pc} + 800baba: bf00 nop + 800babc: 0800e1b0 .word 0x0800e1b0 + 800bac0: 2000059c .word 0x2000059c + 800bac4: 0800bb55 .word 0x0800bb55 + 800bac8: 0800bb79 .word 0x0800bb79 + 800bacc: 0800bbad .word 0x0800bbad + 800bad0: 0800bbc5 .word 0x0800bbc5 + 800bad4: 0800bbdd .word 0x0800bbdd + 800bad8: 0800e404 .word 0x0800e404 + 800badc: 33bca100 .word 0x33bca100 + 800bae0: 0800e1cc .word 0x0800e1cc + 800bae4: 0800e1d0 .word 0x0800e1d0 + 800bae8: 0800e1e4 .word 0x0800e1e4 + 800baec: 0800e200 .word 0x0800e200 + 800baf0: 0800e220 .word 0x0800e220 + +0800baf4 : + +/* USER CODE BEGIN EF */ +int32_t SubghzApp_Transmit(const uint8_t* p_Buffer, uint8_t Length) +{ + 800baf4: b580 push {r7, lr} + 800baf6: b082 sub sp, #8 + 800baf8: af00 add r7, sp, #0 + 800bafa: 6078 str r0, [r7, #4] + 800bafc: 460b mov r3, r1 + 800bafe: 70fb strb r3, [r7, #3] + if (Length > MAX_APP_BUFFER_SIZE) + { + return -1; + } + + TxDone = false; + 800bb00: 4b0d ldr r3, [pc, #52] ; (800bb38 ) + 800bb02: 2200 movs r2, #0 + 800bb04: 701a strb r2, [r3, #0] + if (Radio.Send((uint8_t*)p_Buffer, Length) != RADIO_STATUS_OK) + 800bb06: 4b0d ldr r3, [pc, #52] ; (800bb3c ) + 800bb08: 6a9b ldr r3, [r3, #40] ; 0x28 + 800bb0a: 78fa ldrb r2, [r7, #3] + 800bb0c: 4611 mov r1, r2 + 800bb0e: 6878 ldr r0, [r7, #4] + 800bb10: 4798 blx r3 + 800bb12: 4603 mov r3, r0 + 800bb14: 2b00 cmp r3, #0 + 800bb16: d002 beq.n 800bb1e + { + return -1; + 800bb18: f04f 33ff mov.w r3, #4294967295 + 800bb1c: e008 b.n 800bb30 + } + + while (TxDone == false); + 800bb1e: bf00 nop + 800bb20: 4b05 ldr r3, [pc, #20] ; (800bb38 ) + 800bb22: 781b ldrb r3, [r3, #0] + 800bb24: f083 0301 eor.w r3, r3, #1 + 800bb28: b2db uxtb r3, r3 + 800bb2a: 2b00 cmp r3, #0 + 800bb2c: d1f8 bne.n 800bb20 + + return 0; + 800bb2e: 2300 movs r3, #0 +} + 800bb30: 4618 mov r0, r3 + 800bb32: 3708 adds r7, #8 + 800bb34: 46bd mov sp, r7 + 800bb36: bd80 pop {r7, pc} + 800bb38: 200005b8 .word 0x200005b8 + 800bb3c: 0800e404 .word 0x0800e404 + +0800bb40 : + +void SubghzApp_Sleep(void) +{ + 800bb40: b580 push {r7, lr} + 800bb42: af00 add r7, sp, #0 + Radio.Sleep(); + 800bb44: 4b02 ldr r3, [pc, #8] ; (800bb50 ) + 800bb46: 6adb ldr r3, [r3, #44] ; 0x2c + 800bb48: 4798 blx r3 +} + 800bb4a: bf00 nop + 800bb4c: bd80 pop {r7, pc} + 800bb4e: bf00 nop + 800bb50: 0800e404 .word 0x0800e404 + +0800bb54 : + +/* USER CODE END EF */ + +/* Private functions ---------------------------------------------------------*/ +static void OnTxDone(void) +{ + 800bb54: b580 push {r7, lr} + 800bb56: af00 add r7, sp, #0 + /* USER CODE BEGIN OnTxDone */ + APP_LOG(TS_ON, VLEVEL_L, "OnTxDone\n\r"); + 800bb58: 4b05 ldr r3, [pc, #20] ; (800bb70 ) + 800bb5a: 2201 movs r2, #1 + 800bb5c: 2100 movs r1, #0 + 800bb5e: 2001 movs r0, #1 + 800bb60: f000 ffa6 bl 800cab0 + TxDone = true; + 800bb64: 4b03 ldr r3, [pc, #12] ; (800bb74 ) + 800bb66: 2201 movs r2, #1 + 800bb68: 701a strb r2, [r3, #0] + /* USER CODE END OnTxDone */ +} + 800bb6a: bf00 nop + 800bb6c: bd80 pop {r7, pc} + 800bb6e: bf00 nop + 800bb70: 0800e238 .word 0x0800e238 + 800bb74: 200005b8 .word 0x200005b8 + +0800bb78 : + +static void OnRxDone(uint8_t *payload, uint16_t size, int16_t rssi, int8_t LoraSnr_FskCfo) +{ + 800bb78: b580 push {r7, lr} + 800bb7a: b084 sub sp, #16 + 800bb7c: af00 add r7, sp, #0 + 800bb7e: 60f8 str r0, [r7, #12] + 800bb80: 4608 mov r0, r1 + 800bb82: 4611 mov r1, r2 + 800bb84: 461a mov r2, r3 + 800bb86: 4603 mov r3, r0 + 800bb88: 817b strh r3, [r7, #10] + 800bb8a: 460b mov r3, r1 + 800bb8c: 813b strh r3, [r7, #8] + 800bb8e: 4613 mov r3, r2 + 800bb90: 71fb strb r3, [r7, #7] + /* USER CODE BEGIN OnRxDone */ + APP_LOG(TS_ON, VLEVEL_L, "OnRxDone\n\r"); + 800bb92: 4b05 ldr r3, [pc, #20] ; (800bba8 ) + 800bb94: 2201 movs r2, #1 + 800bb96: 2100 movs r1, #0 + 800bb98: 2001 movs r0, #1 + 800bb9a: f000 ff89 bl 800cab0 + /* USER CODE END OnRxDone */ +} + 800bb9e: bf00 nop + 800bba0: 3710 adds r7, #16 + 800bba2: 46bd mov sp, r7 + 800bba4: bd80 pop {r7, pc} + 800bba6: bf00 nop + 800bba8: 0800e244 .word 0x0800e244 + +0800bbac : + +static void OnTxTimeout(void) +{ + 800bbac: b580 push {r7, lr} + 800bbae: af00 add r7, sp, #0 + /* USER CODE BEGIN OnTxTimeout */ + APP_LOG(TS_ON, VLEVEL_L, "OnTxTimeout\n\r"); + 800bbb0: 4b03 ldr r3, [pc, #12] ; (800bbc0 ) + 800bbb2: 2201 movs r2, #1 + 800bbb4: 2100 movs r1, #0 + 800bbb6: 2001 movs r0, #1 + 800bbb8: f000 ff7a bl 800cab0 + /* USER CODE END OnTxTimeout */ +} + 800bbbc: bf00 nop + 800bbbe: bd80 pop {r7, pc} + 800bbc0: 0800e250 .word 0x0800e250 + +0800bbc4 : + +static void OnRxTimeout(void) +{ + 800bbc4: b580 push {r7, lr} + 800bbc6: af00 add r7, sp, #0 + /* USER CODE BEGIN OnRxTimeout */ + APP_LOG(TS_ON, VLEVEL_L, "OnRxTimeout\n\r"); + 800bbc8: 4b03 ldr r3, [pc, #12] ; (800bbd8 ) + 800bbca: 2201 movs r2, #1 + 800bbcc: 2100 movs r1, #0 + 800bbce: 2001 movs r0, #1 + 800bbd0: f000 ff6e bl 800cab0 + /* USER CODE END OnRxTimeout */ +} + 800bbd4: bf00 nop + 800bbd6: bd80 pop {r7, pc} + 800bbd8: 0800e260 .word 0x0800e260 + +0800bbdc : + +static void OnRxError(void) +{ + 800bbdc: b580 push {r7, lr} + 800bbde: af00 add r7, sp, #0 + /* USER CODE BEGIN OnRxError */ + APP_LOG(TS_ON, VLEVEL_L, "OnRxError\n\r"); + 800bbe0: 4b03 ldr r3, [pc, #12] ; (800bbf0 ) + 800bbe2: 2201 movs r2, #1 + 800bbe4: 2100 movs r1, #0 + 800bbe6: 2001 movs r0, #1 + 800bbe8: f000 ff62 bl 800cab0 + /* USER CODE END OnRxError */ +} + 800bbec: bf00 nop + 800bbee: bd80 pop {r7, pc} + 800bbf0: 0800e270 .word 0x0800e270 + +0800bbf4 : + +/* USER CODE END PFP */ + +/* Exported functions --------------------------------------------------------*/ +int32_t RBI_Init(void) +{ + 800bbf4: b580 push {r7, lr} + 800bbf6: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_Init(); + 800bbf8: f7f5 ff6e bl 8001ad8 + 800bbfc: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_Init_2 */ +#error user to provide its board code or to call his board driver functions + /* USER CODE END RBI_Init_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bbfe: 4618 mov r0, r3 + 800bc00: bd80 pop {r7, pc} + +0800bc02 : + return retcode; +#endif /* USE_BSP_DRIVER */ +} + +int32_t RBI_ConfigRFSwitch(RBI_Switch_TypeDef Config) +{ + 800bc02: b580 push {r7, lr} + 800bc04: b082 sub sp, #8 + 800bc06: af00 add r7, sp, #0 + 800bc08: 4603 mov r3, r0 + 800bc0a: 71fb strb r3, [r7, #7] + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_ConfigRFSwitch((BSP_RADIO_Switch_TypeDef) Config); + 800bc0c: 79fb ldrb r3, [r7, #7] + 800bc0e: 4618 mov r0, r3 + 800bc10: f7f5 ffa0 bl 8001b54 + 800bc14: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_ConfigRFSwitch_2 */ +#error user to provide its board code or to call his board driver functions + /* USER CODE END RBI_ConfigRFSwitch_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bc16: 4618 mov r0, r3 + 800bc18: 3708 adds r7, #8 + 800bc1a: 46bd mov sp, r7 + 800bc1c: bd80 pop {r7, pc} + +0800bc1e : + +int32_t RBI_GetTxConfig(void) +{ + 800bc1e: b580 push {r7, lr} + 800bc20: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetTxConfig(); + 800bc22: f7f5 fff3 bl 8001c0c + 800bc26: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_GetTxConfig_2 */ +#error user to provide its board code or to call his board driver functions + /* USER CODE END RBI_GetTxConfig_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bc28: 4618 mov r0, r3 + 800bc2a: bd80 pop {r7, pc} + +0800bc2c : + +int32_t RBI_IsTCXO(void) +{ + 800bc2c: b580 push {r7, lr} + 800bc2e: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsTCXO(); + 800bc30: f7f5 fff3 bl 8001c1a + 800bc34: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_IsTCXO_2 */ +#error user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsTCXO_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bc36: 4618 mov r0, r3 + 800bc38: bd80 pop {r7, pc} + +0800bc3a : + +int32_t RBI_IsDCDC(void) +{ + 800bc3a: b580 push {r7, lr} + 800bc3c: af00 add r7, sp, #0 + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_IsDCDC(); + 800bc3e: f7f5 fff3 bl 8001c28 + 800bc42: 4603 mov r3, r0 + /* USER CODE BEGIN RBI_IsDCDC_2 */ +#error user to provide its board code or to call his board driver functions + /* USER CODE END RBI_IsDCDC_2 */ + return retcode; +#endif /* USE_BSP_DRIVER */ +} + 800bc44: 4618 mov r0, r3 + 800bc46: bd80 pop {r7, pc} + +0800bc48 : + +int32_t RBI_GetRFOMaxPowerConfig(RBI_RFOMaxPowerConfig_TypeDef Config) +{ + 800bc48: b580 push {r7, lr} + 800bc4a: b082 sub sp, #8 + 800bc4c: af00 add r7, sp, #0 + 800bc4e: 4603 mov r3, r0 + 800bc50: 71fb strb r3, [r7, #7] + * 1/ For User boards, the BSP/STM32WLxx_Nucleo/ directory can be copied and replaced in the project. The copy must then be updated depending: + * on board RF switch configuration (pin control, number of port etc) + * on TCXO configuration + * on DC/DC configuration + * on maximum output power that the board can deliver*/ + return BSP_RADIO_GetRFOMaxPowerConfig((BSP_RADIO_RFOMaxPowerConfig_TypeDef) Config); + 800bc52: 79fb ldrb r3, [r7, #7] + 800bc54: 4618 mov r0, r3 + 800bc56: f7f5 ffee bl 8001c36 + 800bc5a: 4603 mov r3, r0 + ret = 22; /*dBm*/ + } + /* USER CODE END RBI_GetRFOMaxPowerConfig_2 */ + return ret; +#endif /* USE_BSP_DRIVER */ +} + 800bc5c: 4618 mov r0, r3 + 800bc5e: 3708 adds r7, #8 + 800bc60: 46bd mov sp, r7 + 800bc62: bd80 pop {r7, pc} + +0800bc64 : + +/** @addtogroup TINY_LPM_Exported_function + * @{ + */ +void UTIL_LPM_Init( void ) +{ + 800bc64: b480 push {r7} + 800bc66: af00 add r7, sp, #0 + StopModeDisable = UTIL_LPM_NO_BIT_SET; + 800bc68: 4b04 ldr r3, [pc, #16] ; (800bc7c ) + 800bc6a: 2200 movs r2, #0 + 800bc6c: 601a str r2, [r3, #0] + OffModeDisable = UTIL_LPM_NO_BIT_SET; + 800bc6e: 4b04 ldr r3, [pc, #16] ; (800bc80 ) + 800bc70: 2200 movs r2, #0 + 800bc72: 601a str r2, [r3, #0] + UTIL_LPM_INIT_CRITICAL_SECTION( ); +} + 800bc74: bf00 nop + 800bc76: 46bd mov sp, r7 + 800bc78: bc80 pop {r7} + 800bc7a: 4770 bx lr + 800bc7c: 200005bc .word 0x200005bc + 800bc80: 200005c0 .word 0x200005c0 + +0800bc84 : +void UTIL_LPM_DeInit( void ) +{ +} + +void UTIL_LPM_SetStopMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800bc84: b480 push {r7} + 800bc86: b087 sub sp, #28 + 800bc88: af00 add r7, sp, #0 + 800bc8a: 6078 str r0, [r7, #4] + 800bc8c: 460b mov r3, r1 + 800bc8e: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800bc90: f3ef 8310 mrs r3, PRIMASK + 800bc94: 613b str r3, [r7, #16] + return(result); + 800bc96: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 800bc98: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800bc9a: b672 cpsid i +} + 800bc9c: bf00 nop + + switch( state ) + 800bc9e: 78fb ldrb r3, [r7, #3] + 800bca0: 2b00 cmp r3, #0 + 800bca2: d008 beq.n 800bcb6 + 800bca4: 2b01 cmp r3, #1 + 800bca6: d10e bne.n 800bcc6 + { + case UTIL_LPM_DISABLE: + { + StopModeDisable |= lpm_id_bm; + 800bca8: 4b0d ldr r3, [pc, #52] ; (800bce0 ) + 800bcaa: 681a ldr r2, [r3, #0] + 800bcac: 687b ldr r3, [r7, #4] + 800bcae: 4313 orrs r3, r2 + 800bcb0: 4a0b ldr r2, [pc, #44] ; (800bce0 ) + 800bcb2: 6013 str r3, [r2, #0] + break; + 800bcb4: e008 b.n 800bcc8 + } + case UTIL_LPM_ENABLE: + { + StopModeDisable &= ( ~lpm_id_bm ); + 800bcb6: 687b ldr r3, [r7, #4] + 800bcb8: 43da mvns r2, r3 + 800bcba: 4b09 ldr r3, [pc, #36] ; (800bce0 ) + 800bcbc: 681b ldr r3, [r3, #0] + 800bcbe: 4013 ands r3, r2 + 800bcc0: 4a07 ldr r2, [pc, #28] ; (800bce0 ) + 800bcc2: 6013 str r3, [r2, #0] + break; + 800bcc4: e000 b.n 800bcc8 + } + default : + { + break; + 800bcc6: bf00 nop + 800bcc8: 697b ldr r3, [r7, #20] + 800bcca: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800bccc: 68fb ldr r3, [r7, #12] + 800bcce: f383 8810 msr PRIMASK, r3 +} + 800bcd2: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800bcd4: bf00 nop + 800bcd6: 371c adds r7, #28 + 800bcd8: 46bd mov sp, r7 + 800bcda: bc80 pop {r7} + 800bcdc: 4770 bx lr + 800bcde: bf00 nop + 800bce0: 200005bc .word 0x200005bc + +0800bce4 : + +void UTIL_LPM_SetOffMode( UTIL_LPM_bm_t lpm_id_bm, UTIL_LPM_State_t state ) +{ + 800bce4: b480 push {r7} + 800bce6: b087 sub sp, #28 + 800bce8: af00 add r7, sp, #0 + 800bcea: 6078 str r0, [r7, #4] + 800bcec: 460b mov r3, r1 + 800bcee: 70fb strb r3, [r7, #3] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800bcf0: f3ef 8310 mrs r3, PRIMASK + 800bcf4: 613b str r3, [r7, #16] + return(result); + 800bcf6: 693b ldr r3, [r7, #16] + UTIL_LPM_ENTER_CRITICAL_SECTION( ); + 800bcf8: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800bcfa: b672 cpsid i +} + 800bcfc: bf00 nop + + switch(state) + 800bcfe: 78fb ldrb r3, [r7, #3] + 800bd00: 2b00 cmp r3, #0 + 800bd02: d008 beq.n 800bd16 + 800bd04: 2b01 cmp r3, #1 + 800bd06: d10e bne.n 800bd26 + { + case UTIL_LPM_DISABLE: + { + OffModeDisable |= lpm_id_bm; + 800bd08: 4b0d ldr r3, [pc, #52] ; (800bd40 ) + 800bd0a: 681a ldr r2, [r3, #0] + 800bd0c: 687b ldr r3, [r7, #4] + 800bd0e: 4313 orrs r3, r2 + 800bd10: 4a0b ldr r2, [pc, #44] ; (800bd40 ) + 800bd12: 6013 str r3, [r2, #0] + break; + 800bd14: e008 b.n 800bd28 + } + case UTIL_LPM_ENABLE: + { + OffModeDisable &= ( ~lpm_id_bm ); + 800bd16: 687b ldr r3, [r7, #4] + 800bd18: 43da mvns r2, r3 + 800bd1a: 4b09 ldr r3, [pc, #36] ; (800bd40 ) + 800bd1c: 681b ldr r3, [r3, #0] + 800bd1e: 4013 ands r3, r2 + 800bd20: 4a07 ldr r2, [pc, #28] ; (800bd40 ) + 800bd22: 6013 str r3, [r2, #0] + break; + 800bd24: e000 b.n 800bd28 + } + default : + { + break; + 800bd26: bf00 nop + 800bd28: 697b ldr r3, [r7, #20] + 800bd2a: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800bd2c: 68fb ldr r3, [r7, #12] + 800bd2e: f383 8810 msr PRIMASK, r3 +} + 800bd32: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION( ); +} + 800bd34: bf00 nop + 800bd36: 371c adds r7, #28 + 800bd38: 46bd mov sp, r7 + 800bd3a: bc80 pop {r7} + 800bd3c: 4770 bx lr + 800bd3e: bf00 nop + 800bd40: 200005c0 .word 0x200005c0 + +0800bd44 : + + return mode_selected; +} + +void UTIL_LPM_EnterLowPower( void ) +{ + 800bd44: b580 push {r7, lr} + 800bd46: b084 sub sp, #16 + 800bd48: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800bd4a: f3ef 8310 mrs r3, PRIMASK + 800bd4e: 60bb str r3, [r7, #8] + return(result); + 800bd50: 68bb ldr r3, [r7, #8] + UTIL_LPM_ENTER_CRITICAL_SECTION_ELP( ); + 800bd52: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800bd54: b672 cpsid i +} + 800bd56: bf00 nop + + if( StopModeDisable != UTIL_LPM_NO_BIT_SET ) + 800bd58: 4b12 ldr r3, [pc, #72] ; (800bda4 ) + 800bd5a: 681b ldr r3, [r3, #0] + 800bd5c: 2b00 cmp r3, #0 + 800bd5e: d006 beq.n 800bd6e + { + /** + * At least one user disallows Stop Mode + * SLEEP mode is required + */ + UTIL_PowerDriver.EnterSleepMode( ); + 800bd60: 4b11 ldr r3, [pc, #68] ; (800bda8 ) + 800bd62: 681b ldr r3, [r3, #0] + 800bd64: 4798 blx r3 + UTIL_PowerDriver.ExitSleepMode( ); + 800bd66: 4b10 ldr r3, [pc, #64] ; (800bda8 ) + 800bd68: 685b ldr r3, [r3, #4] + 800bd6a: 4798 blx r3 + 800bd6c: e010 b.n 800bd90 + } + else + { + if( OffModeDisable != UTIL_LPM_NO_BIT_SET ) + 800bd6e: 4b0f ldr r3, [pc, #60] ; (800bdac ) + 800bd70: 681b ldr r3, [r3, #0] + 800bd72: 2b00 cmp r3, #0 + 800bd74: d006 beq.n 800bd84 + { + /** + * At least one user disallows Off Mode + * STOP mode is required + */ + UTIL_PowerDriver.EnterStopMode( ); + 800bd76: 4b0c ldr r3, [pc, #48] ; (800bda8 ) + 800bd78: 689b ldr r3, [r3, #8] + 800bd7a: 4798 blx r3 + UTIL_PowerDriver.ExitStopMode( ); + 800bd7c: 4b0a ldr r3, [pc, #40] ; (800bda8 ) + 800bd7e: 68db ldr r3, [r3, #12] + 800bd80: 4798 blx r3 + 800bd82: e005 b.n 800bd90 + else + { + /** + * OFF mode is required + */ + UTIL_PowerDriver.EnterOffMode( ); + 800bd84: 4b08 ldr r3, [pc, #32] ; (800bda8 ) + 800bd86: 691b ldr r3, [r3, #16] + 800bd88: 4798 blx r3 + UTIL_PowerDriver.ExitOffMode( ); + 800bd8a: 4b07 ldr r3, [pc, #28] ; (800bda8 ) + 800bd8c: 695b ldr r3, [r3, #20] + 800bd8e: 4798 blx r3 + 800bd90: 68fb ldr r3, [r7, #12] + 800bd92: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800bd94: 687b ldr r3, [r7, #4] + 800bd96: f383 8810 msr PRIMASK, r3 +} + 800bd9a: bf00 nop + } + } + + UTIL_LPM_EXIT_CRITICAL_SECTION_ELP( ); +} + 800bd9c: bf00 nop + 800bd9e: 3710 adds r7, #16 + 800bda0: 46bd mov sp, r7 + 800bda2: bd80 pop {r7, pc} + 800bda4: 200005bc .word 0x200005bc + 800bda8: 0800e2d4 .word 0x0800e2d4 + 800bdac: 200005c0 .word 0x200005c0 + +0800bdb0 : +/* Global variables ----------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Functions Definition ------------------------------------------------------*/ + +void UTIL_MEM_cpy_8( void *dst, const void *src, uint16_t size ) +{ + 800bdb0: b480 push {r7} + 800bdb2: b087 sub sp, #28 + 800bdb4: af00 add r7, sp, #0 + 800bdb6: 60f8 str r0, [r7, #12] + 800bdb8: 60b9 str r1, [r7, #8] + 800bdba: 4613 mov r3, r2 + 800bdbc: 80fb strh r3, [r7, #6] + uint8_t* dst8= (uint8_t *) dst; + 800bdbe: 68fb ldr r3, [r7, #12] + 800bdc0: 617b str r3, [r7, #20] + uint8_t* src8= (uint8_t *) src; + 800bdc2: 68bb ldr r3, [r7, #8] + 800bdc4: 613b str r3, [r7, #16] + + while( size-- ) + 800bdc6: e007 b.n 800bdd8 + { + *dst8++ = *src8++; + 800bdc8: 693a ldr r2, [r7, #16] + 800bdca: 1c53 adds r3, r2, #1 + 800bdcc: 613b str r3, [r7, #16] + 800bdce: 697b ldr r3, [r7, #20] + 800bdd0: 1c59 adds r1, r3, #1 + 800bdd2: 6179 str r1, [r7, #20] + 800bdd4: 7812 ldrb r2, [r2, #0] + 800bdd6: 701a strb r2, [r3, #0] + while( size-- ) + 800bdd8: 88fb ldrh r3, [r7, #6] + 800bdda: 1e5a subs r2, r3, #1 + 800bddc: 80fa strh r2, [r7, #6] + 800bdde: 2b00 cmp r3, #0 + 800bde0: d1f2 bne.n 800bdc8 + } +} + 800bde2: bf00 nop + 800bde4: bf00 nop + 800bde6: 371c adds r7, #28 + 800bde8: 46bd mov sp, r7 + 800bdea: bc80 pop {r7} + 800bdec: 4770 bx lr + +0800bdee : + *dst8-- = *src8++; + } +} + +void UTIL_MEM_set_8( void *dst, uint8_t value, uint16_t size ) +{ + 800bdee: b480 push {r7} + 800bdf0: b085 sub sp, #20 + 800bdf2: af00 add r7, sp, #0 + 800bdf4: 6078 str r0, [r7, #4] + 800bdf6: 460b mov r3, r1 + 800bdf8: 70fb strb r3, [r7, #3] + 800bdfa: 4613 mov r3, r2 + 800bdfc: 803b strh r3, [r7, #0] + uint8_t* dst8= (uint8_t *) dst; + 800bdfe: 687b ldr r3, [r7, #4] + 800be00: 60fb str r3, [r7, #12] + while( size-- ) + 800be02: e004 b.n 800be0e + { + *dst8++ = value; + 800be04: 68fb ldr r3, [r7, #12] + 800be06: 1c5a adds r2, r3, #1 + 800be08: 60fa str r2, [r7, #12] + 800be0a: 78fa ldrb r2, [r7, #3] + 800be0c: 701a strb r2, [r3, #0] + while( size-- ) + 800be0e: 883b ldrh r3, [r7, #0] + 800be10: 1e5a subs r2, r3, #1 + 800be12: 803a strh r2, [r7, #0] + 800be14: 2b00 cmp r3, #0 + 800be16: d1f5 bne.n 800be04 + } +} + 800be18: bf00 nop + 800be1a: bf00 nop + 800be1c: 3714 adds r7, #20 + 800be1e: 46bd mov sp, r7 + 800be20: bc80 pop {r7} + 800be22: 4770 bx lr + +0800be24 : + * @addtogroup SYSTIME_exported_function + * @{ + */ + +SysTime_t SysTimeAdd( SysTime_t a, SysTime_t b ) +{ + 800be24: b082 sub sp, #8 + 800be26: b480 push {r7} + 800be28: b087 sub sp, #28 + 800be2a: af00 add r7, sp, #0 + 800be2c: 60f8 str r0, [r7, #12] + 800be2e: 1d38 adds r0, r7, #4 + 800be30: e880 0006 stmia.w r0, {r1, r2} + 800be34: 627b str r3, [r7, #36] ; 0x24 + SysTime_t c = { .Seconds = 0, .SubSeconds = 0 }; + 800be36: 2300 movs r3, #0 + 800be38: 613b str r3, [r7, #16] + 800be3a: 2300 movs r3, #0 + 800be3c: 82bb strh r3, [r7, #20] + + c.Seconds = a.Seconds + b.Seconds; + 800be3e: 687a ldr r2, [r7, #4] + 800be40: 6a7b ldr r3, [r7, #36] ; 0x24 + 800be42: 4413 add r3, r2 + 800be44: 613b str r3, [r7, #16] + c.SubSeconds = a.SubSeconds + b.SubSeconds; + 800be46: f9b7 3008 ldrsh.w r3, [r7, #8] + 800be4a: b29a uxth r2, r3 + 800be4c: f9b7 3028 ldrsh.w r3, [r7, #40] ; 0x28 + 800be50: b29b uxth r3, r3 + 800be52: 4413 add r3, r2 + 800be54: b29b uxth r3, r3 + 800be56: b21b sxth r3, r3 + 800be58: 82bb strh r3, [r7, #20] + if( c.SubSeconds >= 1000 ) + 800be5a: f9b7 3014 ldrsh.w r3, [r7, #20] + 800be5e: f5b3 7f7a cmp.w r3, #1000 ; 0x3e8 + 800be62: db0a blt.n 800be7a + { + c.Seconds++; + 800be64: 693b ldr r3, [r7, #16] + 800be66: 3301 adds r3, #1 + 800be68: 613b str r3, [r7, #16] + c.SubSeconds -= 1000; + 800be6a: f9b7 3014 ldrsh.w r3, [r7, #20] + 800be6e: b29b uxth r3, r3 + 800be70: f5a3 737a sub.w r3, r3, #1000 ; 0x3e8 + 800be74: b29b uxth r3, r3 + 800be76: b21b sxth r3, r3 + 800be78: 82bb strh r3, [r7, #20] + } + return c; + 800be7a: 68fb ldr r3, [r7, #12] + 800be7c: 461a mov r2, r3 + 800be7e: f107 0310 add.w r3, r7, #16 + 800be82: e893 0003 ldmia.w r3, {r0, r1} + 800be86: e882 0003 stmia.w r2, {r0, r1} +} + 800be8a: 68f8 ldr r0, [r7, #12] + 800be8c: 371c adds r7, #28 + 800be8e: 46bd mov sp, r7 + 800be90: bc80 pop {r7} + 800be92: b002 add sp, #8 + 800be94: 4770 bx lr + ... + +0800be98 : + UTIL_SYSTIMDriver.BKUPWrite_Seconds( DeltaTime.Seconds ); + UTIL_SYSTIMDriver.BKUPWrite_SubSeconds( ( uint32_t ) DeltaTime.SubSeconds ); +} + +SysTime_t SysTimeGet( void ) +{ + 800be98: b580 push {r7, lr} + 800be9a: b08a sub sp, #40 ; 0x28 + 800be9c: af02 add r7, sp, #8 + 800be9e: 6078 str r0, [r7, #4] + SysTime_t calendarTime = { .Seconds = 0, .SubSeconds = 0 }; + 800bea0: 2300 movs r3, #0 + 800bea2: 61bb str r3, [r7, #24] + 800bea4: 2300 movs r3, #0 + 800bea6: 83bb strh r3, [r7, #28] + SysTime_t sysTime = { .Seconds = 0, .SubSeconds = 0 }; + 800bea8: 2300 movs r3, #0 + 800beaa: 613b str r3, [r7, #16] + 800beac: 2300 movs r3, #0 + 800beae: 82bb strh r3, [r7, #20] + SysTime_t DeltaTime; + + calendarTime.Seconds = UTIL_SYSTIMDriver.GetCalendarTime( ( uint16_t* )&calendarTime.SubSeconds ); + 800beb0: 4b14 ldr r3, [pc, #80] ; (800bf04 ) + 800beb2: 691b ldr r3, [r3, #16] + 800beb4: f107 0218 add.w r2, r7, #24 + 800beb8: 3204 adds r2, #4 + 800beba: 4610 mov r0, r2 + 800bebc: 4798 blx r3 + 800bebe: 4603 mov r3, r0 + 800bec0: 61bb str r3, [r7, #24] + + DeltaTime.SubSeconds = (int16_t)UTIL_SYSTIMDriver.BKUPRead_SubSeconds(); + 800bec2: 4b10 ldr r3, [pc, #64] ; (800bf04 ) + 800bec4: 68db ldr r3, [r3, #12] + 800bec6: 4798 blx r3 + 800bec8: 4603 mov r3, r0 + 800beca: b21b sxth r3, r3 + 800becc: 81bb strh r3, [r7, #12] + DeltaTime.Seconds = UTIL_SYSTIMDriver.BKUPRead_Seconds(); + 800bece: 4b0d ldr r3, [pc, #52] ; (800bf04 ) + 800bed0: 685b ldr r3, [r3, #4] + 800bed2: 4798 blx r3 + 800bed4: 4603 mov r3, r0 + 800bed6: 60bb str r3, [r7, #8] + + sysTime = SysTimeAdd( DeltaTime, calendarTime ); + 800bed8: f107 0010 add.w r0, r7, #16 + 800bedc: 69fb ldr r3, [r7, #28] + 800bede: 9300 str r3, [sp, #0] + 800bee0: 69bb ldr r3, [r7, #24] + 800bee2: f107 0208 add.w r2, r7, #8 + 800bee6: ca06 ldmia r2, {r1, r2} + 800bee8: f7ff ff9c bl 800be24 + + return sysTime; + 800beec: 687b ldr r3, [r7, #4] + 800beee: 461a mov r2, r3 + 800bef0: f107 0310 add.w r3, r7, #16 + 800bef4: e893 0003 ldmia.w r3, {r0, r1} + 800bef8: e882 0003 stmia.w r2, {r0, r1} +} + 800befc: 6878 ldr r0, [r7, #4] + 800befe: 3720 adds r7, #32 + 800bf00: 46bd mov sp, r7 + 800bf02: bd80 pop {r7, pc} + 800bf04: 0800e3b8 .word 0x0800e3b8 + +0800bf08 : + return sc - s; +} +#endif + +static int ee_skip_atoi(const char **s) +{ + 800bf08: b480 push {r7} + 800bf0a: b085 sub sp, #20 + 800bf0c: af00 add r7, sp, #0 + 800bf0e: 6078 str r0, [r7, #4] + int i = 0; + 800bf10: 2300 movs r3, #0 + 800bf12: 60fb str r3, [r7, #12] + while (is_digit(**s)) i = i*10 + *((*s)++) - '0'; + 800bf14: e00e b.n 800bf34 + 800bf16: 68fa ldr r2, [r7, #12] + 800bf18: 4613 mov r3, r2 + 800bf1a: 009b lsls r3, r3, #2 + 800bf1c: 4413 add r3, r2 + 800bf1e: 005b lsls r3, r3, #1 + 800bf20: 4618 mov r0, r3 + 800bf22: 687b ldr r3, [r7, #4] + 800bf24: 681b ldr r3, [r3, #0] + 800bf26: 1c59 adds r1, r3, #1 + 800bf28: 687a ldr r2, [r7, #4] + 800bf2a: 6011 str r1, [r2, #0] + 800bf2c: 781b ldrb r3, [r3, #0] + 800bf2e: 4403 add r3, r0 + 800bf30: 3b30 subs r3, #48 ; 0x30 + 800bf32: 60fb str r3, [r7, #12] + 800bf34: 687b ldr r3, [r7, #4] + 800bf36: 681b ldr r3, [r3, #0] + 800bf38: 781b ldrb r3, [r3, #0] + 800bf3a: 2b2f cmp r3, #47 ; 0x2f + 800bf3c: d904 bls.n 800bf48 + 800bf3e: 687b ldr r3, [r7, #4] + 800bf40: 681b ldr r3, [r3, #0] + 800bf42: 781b ldrb r3, [r3, #0] + 800bf44: 2b39 cmp r3, #57 ; 0x39 + 800bf46: d9e6 bls.n 800bf16 + return i; + 800bf48: 68fb ldr r3, [r7, #12] +} + 800bf4a: 4618 mov r0, r3 + 800bf4c: 3714 adds r7, #20 + 800bf4e: 46bd mov sp, r7 + 800bf50: bc80 pop {r7} + 800bf52: 4770 bx lr + +0800bf54 : + +#define ASSIGN_STR(_c) do { *str++ = (_c); max_size--; if (max_size == 0) return str; } while (0) + +static char *ee_number(char *str, int max_size, long num, int base, int size, int precision, int type) +{ + 800bf54: b480 push {r7} + 800bf56: b099 sub sp, #100 ; 0x64 + 800bf58: af00 add r7, sp, #0 + 800bf5a: 60f8 str r0, [r7, #12] + 800bf5c: 60b9 str r1, [r7, #8] + 800bf5e: 607a str r2, [r7, #4] + 800bf60: 603b str r3, [r7, #0] + char c; + char sign, tmp[66]; + char *dig = lower_digits; + 800bf62: 4b71 ldr r3, [pc, #452] ; (800c128 ) + 800bf64: 681b ldr r3, [r3, #0] + 800bf66: 65bb str r3, [r7, #88] ; 0x58 + int i; + + if (type & UPPERCASE) dig = upper_digits; + 800bf68: 6f3b ldr r3, [r7, #112] ; 0x70 + 800bf6a: f003 0340 and.w r3, r3, #64 ; 0x40 + 800bf6e: 2b00 cmp r3, #0 + 800bf70: d002 beq.n 800bf78 + 800bf72: 4b6e ldr r3, [pc, #440] ; (800c12c ) + 800bf74: 681b ldr r3, [r3, #0] + 800bf76: 65bb str r3, [r7, #88] ; 0x58 +#ifdef TINY_PRINTF +#else + if (type & LEFT) type &= ~ZEROPAD; +#endif + if (base < 2 || base > 36) return 0; + 800bf78: 683b ldr r3, [r7, #0] + 800bf7a: 2b01 cmp r3, #1 + 800bf7c: dd02 ble.n 800bf84 + 800bf7e: 683b ldr r3, [r7, #0] + 800bf80: 2b24 cmp r3, #36 ; 0x24 + 800bf82: dd01 ble.n 800bf88 + 800bf84: 2300 movs r3, #0 + 800bf86: e0ca b.n 800c11e + + c = (type & ZEROPAD) ? '0' : ' '; + 800bf88: 6f3b ldr r3, [r7, #112] ; 0x70 + 800bf8a: f003 0301 and.w r3, r3, #1 + 800bf8e: 2b00 cmp r3, #0 + 800bf90: d001 beq.n 800bf96 + 800bf92: 2330 movs r3, #48 ; 0x30 + 800bf94: e000 b.n 800bf98 + 800bf96: 2320 movs r3, #32 + 800bf98: f887 3053 strb.w r3, [r7, #83] ; 0x53 + sign = 0; + 800bf9c: 2300 movs r3, #0 + 800bf9e: f887 305f strb.w r3, [r7, #95] ; 0x5f + if (type & SIGN) + 800bfa2: 6f3b ldr r3, [r7, #112] ; 0x70 + 800bfa4: f003 0302 and.w r3, r3, #2 + 800bfa8: 2b00 cmp r3, #0 + 800bfaa: d00b beq.n 800bfc4 + { + if (num < 0) + 800bfac: 687b ldr r3, [r7, #4] + 800bfae: 2b00 cmp r3, #0 + 800bfb0: da08 bge.n 800bfc4 + { + sign = '-'; + 800bfb2: 232d movs r3, #45 ; 0x2d + 800bfb4: f887 305f strb.w r3, [r7, #95] ; 0x5f + num = -num; + 800bfb8: 687b ldr r3, [r7, #4] + 800bfba: 425b negs r3, r3 + 800bfbc: 607b str r3, [r7, #4] + size--; + 800bfbe: 6ebb ldr r3, [r7, #104] ; 0x68 + 800bfc0: 3b01 subs r3, #1 + 800bfc2: 66bb str r3, [r7, #104] ; 0x68 + else if (base == 8) + size--; + } +#endif + + i = 0; + 800bfc4: 2300 movs r3, #0 + 800bfc6: 657b str r3, [r7, #84] ; 0x54 + + if (num == 0) + 800bfc8: 687b ldr r3, [r7, #4] + 800bfca: 2b00 cmp r3, #0 + 800bfcc: d11e bne.n 800c00c + tmp[i++] = '0'; + 800bfce: 6d7b ldr r3, [r7, #84] ; 0x54 + 800bfd0: 1c5a adds r2, r3, #1 + 800bfd2: 657a str r2, [r7, #84] ; 0x54 + 800bfd4: 3360 adds r3, #96 ; 0x60 + 800bfd6: 443b add r3, r7 + 800bfd8: 2230 movs r2, #48 ; 0x30 + 800bfda: f803 2c50 strb.w r2, [r3, #-80] + 800bfde: e018 b.n 800c012 + else + { + while (num != 0) + { + tmp[i++] = dig[((unsigned long) num) % (unsigned) base]; + 800bfe0: 687b ldr r3, [r7, #4] + 800bfe2: 683a ldr r2, [r7, #0] + 800bfe4: fbb3 f1f2 udiv r1, r3, r2 + 800bfe8: fb01 f202 mul.w r2, r1, r2 + 800bfec: 1a9b subs r3, r3, r2 + 800bfee: 6dba ldr r2, [r7, #88] ; 0x58 + 800bff0: 441a add r2, r3 + 800bff2: 6d7b ldr r3, [r7, #84] ; 0x54 + 800bff4: 1c59 adds r1, r3, #1 + 800bff6: 6579 str r1, [r7, #84] ; 0x54 + 800bff8: 7812 ldrb r2, [r2, #0] + 800bffa: 3360 adds r3, #96 ; 0x60 + 800bffc: 443b add r3, r7 + 800bffe: f803 2c50 strb.w r2, [r3, #-80] + num = ((unsigned long) num) / (unsigned) base; + 800c002: 687a ldr r2, [r7, #4] + 800c004: 683b ldr r3, [r7, #0] + 800c006: fbb2 f3f3 udiv r3, r2, r3 + 800c00a: 607b str r3, [r7, #4] + while (num != 0) + 800c00c: 687b ldr r3, [r7, #4] + 800c00e: 2b00 cmp r3, #0 + 800c010: d1e6 bne.n 800bfe0 + } + } + + if (i > precision) precision = i; + 800c012: 6d7a ldr r2, [r7, #84] ; 0x54 + 800c014: 6efb ldr r3, [r7, #108] ; 0x6c + 800c016: 429a cmp r2, r3 + 800c018: dd01 ble.n 800c01e + 800c01a: 6d7b ldr r3, [r7, #84] ; 0x54 + 800c01c: 66fb str r3, [r7, #108] ; 0x6c + size -= precision; + 800c01e: 6eba ldr r2, [r7, #104] ; 0x68 + 800c020: 6efb ldr r3, [r7, #108] ; 0x6c + 800c022: 1ad3 subs r3, r2, r3 + 800c024: 66bb str r3, [r7, #104] ; 0x68 + if (!(type & (ZEROPAD /* TINY option | LEFT */))) while (size-- > 0) ASSIGN_STR(' '); + 800c026: 6f3b ldr r3, [r7, #112] ; 0x70 + 800c028: f003 0301 and.w r3, r3, #1 + 800c02c: 2b00 cmp r3, #0 + 800c02e: d112 bne.n 800c056 + 800c030: e00c b.n 800c04c + 800c032: 68fb ldr r3, [r7, #12] + 800c034: 1c5a adds r2, r3, #1 + 800c036: 60fa str r2, [r7, #12] + 800c038: 2220 movs r2, #32 + 800c03a: 701a strb r2, [r3, #0] + 800c03c: 68bb ldr r3, [r7, #8] + 800c03e: 3b01 subs r3, #1 + 800c040: 60bb str r3, [r7, #8] + 800c042: 68bb ldr r3, [r7, #8] + 800c044: 2b00 cmp r3, #0 + 800c046: d101 bne.n 800c04c + 800c048: 68fb ldr r3, [r7, #12] + 800c04a: e068 b.n 800c11e + 800c04c: 6ebb ldr r3, [r7, #104] ; 0x68 + 800c04e: 1e5a subs r2, r3, #1 + 800c050: 66ba str r2, [r7, #104] ; 0x68 + 800c052: 2b00 cmp r3, #0 + 800c054: dced bgt.n 800c032 + if (sign) ASSIGN_STR(sign); + 800c056: f897 305f ldrb.w r3, [r7, #95] ; 0x5f + 800c05a: 2b00 cmp r3, #0 + 800c05c: d01b beq.n 800c096 + 800c05e: 68fb ldr r3, [r7, #12] + 800c060: 1c5a adds r2, r3, #1 + 800c062: 60fa str r2, [r7, #12] + 800c064: f897 205f ldrb.w r2, [r7, #95] ; 0x5f + 800c068: 701a strb r2, [r3, #0] + 800c06a: 68bb ldr r3, [r7, #8] + 800c06c: 3b01 subs r3, #1 + 800c06e: 60bb str r3, [r7, #8] + 800c070: 68bb ldr r3, [r7, #8] + 800c072: 2b00 cmp r3, #0 + 800c074: d10f bne.n 800c096 + 800c076: 68fb ldr r3, [r7, #12] + 800c078: e051 b.n 800c11e + } + } +#endif + +#ifdef TINY_PRINTF + while (size-- > 0) ASSIGN_STR(c); + 800c07a: 68fb ldr r3, [r7, #12] + 800c07c: 1c5a adds r2, r3, #1 + 800c07e: 60fa str r2, [r7, #12] + 800c080: f897 2053 ldrb.w r2, [r7, #83] ; 0x53 + 800c084: 701a strb r2, [r3, #0] + 800c086: 68bb ldr r3, [r7, #8] + 800c088: 3b01 subs r3, #1 + 800c08a: 60bb str r3, [r7, #8] + 800c08c: 68bb ldr r3, [r7, #8] + 800c08e: 2b00 cmp r3, #0 + 800c090: d101 bne.n 800c096 + 800c092: 68fb ldr r3, [r7, #12] + 800c094: e043 b.n 800c11e + 800c096: 6ebb ldr r3, [r7, #104] ; 0x68 + 800c098: 1e5a subs r2, r3, #1 + 800c09a: 66ba str r2, [r7, #104] ; 0x68 + 800c09c: 2b00 cmp r3, #0 + 800c09e: dcec bgt.n 800c07a +#else + if (!(type & LEFT)) while (size-- > 0) ASSIGN_STR(c); +#endif + while (i < precision--) ASSIGN_STR('0'); + 800c0a0: e00c b.n 800c0bc + 800c0a2: 68fb ldr r3, [r7, #12] + 800c0a4: 1c5a adds r2, r3, #1 + 800c0a6: 60fa str r2, [r7, #12] + 800c0a8: 2230 movs r2, #48 ; 0x30 + 800c0aa: 701a strb r2, [r3, #0] + 800c0ac: 68bb ldr r3, [r7, #8] + 800c0ae: 3b01 subs r3, #1 + 800c0b0: 60bb str r3, [r7, #8] + 800c0b2: 68bb ldr r3, [r7, #8] + 800c0b4: 2b00 cmp r3, #0 + 800c0b6: d101 bne.n 800c0bc + 800c0b8: 68fb ldr r3, [r7, #12] + 800c0ba: e030 b.n 800c11e + 800c0bc: 6efb ldr r3, [r7, #108] ; 0x6c + 800c0be: 1e5a subs r2, r3, #1 + 800c0c0: 66fa str r2, [r7, #108] ; 0x6c + 800c0c2: 6d7a ldr r2, [r7, #84] ; 0x54 + 800c0c4: 429a cmp r2, r3 + 800c0c6: dbec blt.n 800c0a2 + while (i-- > 0) ASSIGN_STR(tmp[i]); + 800c0c8: e010 b.n 800c0ec + 800c0ca: 68fb ldr r3, [r7, #12] + 800c0cc: 1c5a adds r2, r3, #1 + 800c0ce: 60fa str r2, [r7, #12] + 800c0d0: f107 0110 add.w r1, r7, #16 + 800c0d4: 6d7a ldr r2, [r7, #84] ; 0x54 + 800c0d6: 440a add r2, r1 + 800c0d8: 7812 ldrb r2, [r2, #0] + 800c0da: 701a strb r2, [r3, #0] + 800c0dc: 68bb ldr r3, [r7, #8] + 800c0de: 3b01 subs r3, #1 + 800c0e0: 60bb str r3, [r7, #8] + 800c0e2: 68bb ldr r3, [r7, #8] + 800c0e4: 2b00 cmp r3, #0 + 800c0e6: d101 bne.n 800c0ec + 800c0e8: 68fb ldr r3, [r7, #12] + 800c0ea: e018 b.n 800c11e + 800c0ec: 6d7b ldr r3, [r7, #84] ; 0x54 + 800c0ee: 1e5a subs r2, r3, #1 + 800c0f0: 657a str r2, [r7, #84] ; 0x54 + 800c0f2: 2b00 cmp r3, #0 + 800c0f4: dce9 bgt.n 800c0ca + while (size-- > 0) ASSIGN_STR(' '); + 800c0f6: e00c b.n 800c112 + 800c0f8: 68fb ldr r3, [r7, #12] + 800c0fa: 1c5a adds r2, r3, #1 + 800c0fc: 60fa str r2, [r7, #12] + 800c0fe: 2220 movs r2, #32 + 800c100: 701a strb r2, [r3, #0] + 800c102: 68bb ldr r3, [r7, #8] + 800c104: 3b01 subs r3, #1 + 800c106: 60bb str r3, [r7, #8] + 800c108: 68bb ldr r3, [r7, #8] + 800c10a: 2b00 cmp r3, #0 + 800c10c: d101 bne.n 800c112 + 800c10e: 68fb ldr r3, [r7, #12] + 800c110: e005 b.n 800c11e + 800c112: 6ebb ldr r3, [r7, #104] ; 0x68 + 800c114: 1e5a subs r2, r3, #1 + 800c116: 66ba str r2, [r7, #104] ; 0x68 + 800c118: 2b00 cmp r3, #0 + 800c11a: dced bgt.n 800c0f8 + + return str; + 800c11c: 68fb ldr r3, [r7, #12] +} + 800c11e: 4618 mov r0, r3 + 800c120: 3764 adds r7, #100 ; 0x64 + 800c122: 46bd mov sp, r7 + 800c124: bc80 pop {r7} + 800c126: 4770 bx lr + 800c128: 20000024 .word 0x20000024 + 800c12c: 20000028 .word 0x20000028 + +0800c130 : + +#define CHECK_STR_SIZE(_buf, _str, _size) \ + if ((((_str) - (_buf)) >= ((_size)-1))) { break; } + +int tiny_vsnprintf_like(char *buf, const int size, const char *fmt, va_list args) +{ + 800c130: b580 push {r7, lr} + 800c132: b092 sub sp, #72 ; 0x48 + 800c134: af04 add r7, sp, #16 + 800c136: 60f8 str r0, [r7, #12] + 800c138: 60b9 str r1, [r7, #8] + 800c13a: 607a str r2, [r7, #4] + 800c13c: 603b str r3, [r7, #0] + + int field_width; // Width of output field + int precision; // Min. # of digits for integers; max number of chars for from string + int qualifier; // 'h', 'l', or 'L' for integer fields + + if (size <= 0) + 800c13e: 68bb ldr r3, [r7, #8] + 800c140: 2b00 cmp r3, #0 + 800c142: dc01 bgt.n 800c148 + { + return 0; + 800c144: 2300 movs r3, #0 + 800c146: e13e b.n 800c3c6 + } + + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + 800c148: 68fb ldr r3, [r7, #12] + 800c14a: 62fb str r3, [r7, #44] ; 0x2c + 800c14c: e128 b.n 800c3a0 + { + CHECK_STR_SIZE(buf, str, size); + 800c14e: 6afa ldr r2, [r7, #44] ; 0x2c + 800c150: 68fb ldr r3, [r7, #12] + 800c152: 1ad2 subs r2, r2, r3 + 800c154: 68bb ldr r3, [r7, #8] + 800c156: 3b01 subs r3, #1 + 800c158: 429a cmp r2, r3 + 800c15a: f280 812e bge.w 800c3ba + + if (*fmt != '%') + 800c15e: 687b ldr r3, [r7, #4] + 800c160: 781b ldrb r3, [r3, #0] + 800c162: 2b25 cmp r3, #37 ; 0x25 + 800c164: d006 beq.n 800c174 + { + *str++ = *fmt; + 800c166: 687a ldr r2, [r7, #4] + 800c168: 6afb ldr r3, [r7, #44] ; 0x2c + 800c16a: 1c59 adds r1, r3, #1 + 800c16c: 62f9 str r1, [r7, #44] ; 0x2c + 800c16e: 7812 ldrb r2, [r2, #0] + 800c170: 701a strb r2, [r3, #0] + continue; + 800c172: e112 b.n 800c39a + } + + // Process flags + flags = 0; + 800c174: 2300 movs r3, #0 + 800c176: 623b str r3, [r7, #32] +#ifdef TINY_PRINTF + /* Support %0, but not %-, %+, %space and %# */ + fmt++; + 800c178: 687b ldr r3, [r7, #4] + 800c17a: 3301 adds r3, #1 + 800c17c: 607b str r3, [r7, #4] + if (*fmt == '0') + 800c17e: 687b ldr r3, [r7, #4] + 800c180: 781b ldrb r3, [r3, #0] + 800c182: 2b30 cmp r3, #48 ; 0x30 + 800c184: d103 bne.n 800c18e + { + flags |= ZEROPAD; + 800c186: 6a3b ldr r3, [r7, #32] + 800c188: f043 0301 orr.w r3, r3, #1 + 800c18c: 623b str r3, [r7, #32] + case '0': flags |= ZEROPAD; goto repeat; + } +#endif + + // Get field width + field_width = -1; + 800c18e: f04f 33ff mov.w r3, #4294967295 + 800c192: 61fb str r3, [r7, #28] + if (is_digit(*fmt)) + 800c194: 687b ldr r3, [r7, #4] + 800c196: 781b ldrb r3, [r3, #0] + 800c198: 2b2f cmp r3, #47 ; 0x2f + 800c19a: d908 bls.n 800c1ae + 800c19c: 687b ldr r3, [r7, #4] + 800c19e: 781b ldrb r3, [r3, #0] + 800c1a0: 2b39 cmp r3, #57 ; 0x39 + 800c1a2: d804 bhi.n 800c1ae + field_width = ee_skip_atoi(&fmt); + 800c1a4: 1d3b adds r3, r7, #4 + 800c1a6: 4618 mov r0, r3 + 800c1a8: f7ff feae bl 800bf08 + 800c1ac: 61f8 str r0, [r7, #28] + } + } +#endif + + // Get the precision + precision = -1; + 800c1ae: f04f 33ff mov.w r3, #4294967295 + 800c1b2: 61bb str r3, [r7, #24] + if (precision < 0) precision = 0; + } +#endif + + // Get the conversion qualifier + qualifier = -1; + 800c1b4: f04f 33ff mov.w r3, #4294967295 + 800c1b8: 617b str r3, [r7, #20] + fmt++; + } +#endif + + // Default base + base = 10; + 800c1ba: 230a movs r3, #10 + 800c1bc: 633b str r3, [r7, #48] ; 0x30 + + switch (*fmt) + 800c1be: 687b ldr r3, [r7, #4] + 800c1c0: 781b ldrb r3, [r3, #0] + 800c1c2: 3b58 subs r3, #88 ; 0x58 + 800c1c4: 2b20 cmp r3, #32 + 800c1c6: f200 8094 bhi.w 800c2f2 + 800c1ca: a201 add r2, pc, #4 ; (adr r2, 800c1d0 ) + 800c1cc: f852 f023 ldr.w pc, [r2, r3, lsl #2] + 800c1d0: 0800c2db .word 0x0800c2db + 800c1d4: 0800c2f3 .word 0x0800c2f3 + 800c1d8: 0800c2f3 .word 0x0800c2f3 + 800c1dc: 0800c2f3 .word 0x0800c2f3 + 800c1e0: 0800c2f3 .word 0x0800c2f3 + 800c1e4: 0800c2f3 .word 0x0800c2f3 + 800c1e8: 0800c2f3 .word 0x0800c2f3 + 800c1ec: 0800c2f3 .word 0x0800c2f3 + 800c1f0: 0800c2f3 .word 0x0800c2f3 + 800c1f4: 0800c2f3 .word 0x0800c2f3 + 800c1f8: 0800c2f3 .word 0x0800c2f3 + 800c1fc: 0800c25f .word 0x0800c25f + 800c200: 0800c2e9 .word 0x0800c2e9 + 800c204: 0800c2f3 .word 0x0800c2f3 + 800c208: 0800c2f3 .word 0x0800c2f3 + 800c20c: 0800c2f3 .word 0x0800c2f3 + 800c210: 0800c2f3 .word 0x0800c2f3 + 800c214: 0800c2e9 .word 0x0800c2e9 + 800c218: 0800c2f3 .word 0x0800c2f3 + 800c21c: 0800c2f3 .word 0x0800c2f3 + 800c220: 0800c2f3 .word 0x0800c2f3 + 800c224: 0800c2f3 .word 0x0800c2f3 + 800c228: 0800c2f3 .word 0x0800c2f3 + 800c22c: 0800c2f3 .word 0x0800c2f3 + 800c230: 0800c2f3 .word 0x0800c2f3 + 800c234: 0800c2f3 .word 0x0800c2f3 + 800c238: 0800c2f3 .word 0x0800c2f3 + 800c23c: 0800c27f .word 0x0800c27f + 800c240: 0800c2f3 .word 0x0800c2f3 + 800c244: 0800c33f .word 0x0800c33f + 800c248: 0800c2f3 .word 0x0800c2f3 + 800c24c: 0800c2f3 .word 0x0800c2f3 + 800c250: 0800c2e3 .word 0x0800c2e3 + case 'c': +#ifdef TINY_PRINTF +#else + if (!(flags & LEFT)) +#endif + while (--field_width > 0) *str++ = ' '; + 800c254: 6afb ldr r3, [r7, #44] ; 0x2c + 800c256: 1c5a adds r2, r3, #1 + 800c258: 62fa str r2, [r7, #44] ; 0x2c + 800c25a: 2220 movs r2, #32 + 800c25c: 701a strb r2, [r3, #0] + 800c25e: 69fb ldr r3, [r7, #28] + 800c260: 3b01 subs r3, #1 + 800c262: 61fb str r3, [r7, #28] + 800c264: 69fb ldr r3, [r7, #28] + 800c266: 2b00 cmp r3, #0 + 800c268: dcf4 bgt.n 800c254 + *str++ = (unsigned char) va_arg(args, int); + 800c26a: 683b ldr r3, [r7, #0] + 800c26c: 1d1a adds r2, r3, #4 + 800c26e: 603a str r2, [r7, #0] + 800c270: 6819 ldr r1, [r3, #0] + 800c272: 6afb ldr r3, [r7, #44] ; 0x2c + 800c274: 1c5a adds r2, r3, #1 + 800c276: 62fa str r2, [r7, #44] ; 0x2c + 800c278: b2ca uxtb r2, r1 + 800c27a: 701a strb r2, [r3, #0] +#ifdef TINY_PRINTF +#else + while (--field_width > 0) *str++ = ' '; +#endif + continue; + 800c27c: e08d b.n 800c39a + + case 's': + s = va_arg(args, char *); + 800c27e: 683b ldr r3, [r7, #0] + 800c280: 1d1a adds r2, r3, #4 + 800c282: 603a str r2, [r7, #0] + 800c284: 681b ldr r3, [r3, #0] + 800c286: 627b str r3, [r7, #36] ; 0x24 + if (!s) s = ""; + 800c288: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c28a: 2b00 cmp r3, #0 + 800c28c: d101 bne.n 800c292 + 800c28e: 4b50 ldr r3, [pc, #320] ; (800c3d0 ) + 800c290: 627b str r3, [r7, #36] ; 0x24 +#ifdef TINY_PRINTF + len = strlen(s); + 800c292: 6a78 ldr r0, [r7, #36] ; 0x24 + 800c294: f7f3 ff74 bl 8000180 + 800c298: 4603 mov r3, r0 + 800c29a: 613b str r3, [r7, #16] +#else + len = strnlen(s, precision); + if (!(flags & LEFT)) +#endif + while (len < field_width--) *str++ = ' '; + 800c29c: e004 b.n 800c2a8 + 800c29e: 6afb ldr r3, [r7, #44] ; 0x2c + 800c2a0: 1c5a adds r2, r3, #1 + 800c2a2: 62fa str r2, [r7, #44] ; 0x2c + 800c2a4: 2220 movs r2, #32 + 800c2a6: 701a strb r2, [r3, #0] + 800c2a8: 69fb ldr r3, [r7, #28] + 800c2aa: 1e5a subs r2, r3, #1 + 800c2ac: 61fa str r2, [r7, #28] + 800c2ae: 693a ldr r2, [r7, #16] + 800c2b0: 429a cmp r2, r3 + 800c2b2: dbf4 blt.n 800c29e + for (i = 0; i < len; ++i) *str++ = *s++; + 800c2b4: 2300 movs r3, #0 + 800c2b6: 62bb str r3, [r7, #40] ; 0x28 + 800c2b8: e00a b.n 800c2d0 + 800c2ba: 6a7a ldr r2, [r7, #36] ; 0x24 + 800c2bc: 1c53 adds r3, r2, #1 + 800c2be: 627b str r3, [r7, #36] ; 0x24 + 800c2c0: 6afb ldr r3, [r7, #44] ; 0x2c + 800c2c2: 1c59 adds r1, r3, #1 + 800c2c4: 62f9 str r1, [r7, #44] ; 0x2c + 800c2c6: 7812 ldrb r2, [r2, #0] + 800c2c8: 701a strb r2, [r3, #0] + 800c2ca: 6abb ldr r3, [r7, #40] ; 0x28 + 800c2cc: 3301 adds r3, #1 + 800c2ce: 62bb str r3, [r7, #40] ; 0x28 + 800c2d0: 6aba ldr r2, [r7, #40] ; 0x28 + 800c2d2: 693b ldr r3, [r7, #16] + 800c2d4: 429a cmp r2, r3 + 800c2d6: dbf0 blt.n 800c2ba +#ifdef TINY_PRINTF +#else + while (len < field_width--) *str++ = ' '; +#endif + continue; + 800c2d8: e05f b.n 800c39a + base = 8; + break; +#endif + + case 'X': + flags |= UPPERCASE; + 800c2da: 6a3b ldr r3, [r7, #32] + 800c2dc: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800c2e0: 623b str r3, [r7, #32] + + case 'x': + base = 16; + 800c2e2: 2310 movs r3, #16 + 800c2e4: 633b str r3, [r7, #48] ; 0x30 + break; + 800c2e6: e02b b.n 800c340 + + case 'd': + case 'i': + flags |= SIGN; + 800c2e8: 6a3b ldr r3, [r7, #32] + 800c2ea: f043 0302 orr.w r3, r3, #2 + 800c2ee: 623b str r3, [r7, #32] + + case 'u': + break; + 800c2f0: e025 b.n 800c33e + continue; + +#endif + + default: + if (*fmt != '%') *str++ = '%'; + 800c2f2: 687b ldr r3, [r7, #4] + 800c2f4: 781b ldrb r3, [r3, #0] + 800c2f6: 2b25 cmp r3, #37 ; 0x25 + 800c2f8: d004 beq.n 800c304 + 800c2fa: 6afb ldr r3, [r7, #44] ; 0x2c + 800c2fc: 1c5a adds r2, r3, #1 + 800c2fe: 62fa str r2, [r7, #44] ; 0x2c + 800c300: 2225 movs r2, #37 ; 0x25 + 800c302: 701a strb r2, [r3, #0] + CHECK_STR_SIZE(buf, str, size); + 800c304: 6afa ldr r2, [r7, #44] ; 0x2c + 800c306: 68fb ldr r3, [r7, #12] + 800c308: 1ad2 subs r2, r2, r3 + 800c30a: 68bb ldr r3, [r7, #8] + 800c30c: 3b01 subs r3, #1 + 800c30e: 429a cmp r2, r3 + 800c310: da16 bge.n 800c340 + if (*fmt) + 800c312: 687b ldr r3, [r7, #4] + 800c314: 781b ldrb r3, [r3, #0] + 800c316: 2b00 cmp r3, #0 + 800c318: d006 beq.n 800c328 + *str++ = *fmt; + 800c31a: 687a ldr r2, [r7, #4] + 800c31c: 6afb ldr r3, [r7, #44] ; 0x2c + 800c31e: 1c59 adds r1, r3, #1 + 800c320: 62f9 str r1, [r7, #44] ; 0x2c + 800c322: 7812 ldrb r2, [r2, #0] + 800c324: 701a strb r2, [r3, #0] + 800c326: e002 b.n 800c32e + else + --fmt; + 800c328: 687b ldr r3, [r7, #4] + 800c32a: 3b01 subs r3, #1 + 800c32c: 607b str r3, [r7, #4] + CHECK_STR_SIZE(buf, str, size); + 800c32e: 6afa ldr r2, [r7, #44] ; 0x2c + 800c330: 68fb ldr r3, [r7, #12] + 800c332: 1ad2 subs r2, r2, r3 + 800c334: 68bb ldr r3, [r7, #8] + 800c336: 3b01 subs r3, #1 + 800c338: 429a cmp r2, r3 + 800c33a: db2d blt.n 800c398 + 800c33c: e000 b.n 800c340 + break; + 800c33e: bf00 nop + continue; + } + + if (qualifier == 'l') + 800c340: 697b ldr r3, [r7, #20] + 800c342: 2b6c cmp r3, #108 ; 0x6c + 800c344: d105 bne.n 800c352 + num = va_arg(args, unsigned long); + 800c346: 683b ldr r3, [r7, #0] + 800c348: 1d1a adds r2, r3, #4 + 800c34a: 603a str r2, [r7, #0] + 800c34c: 681b ldr r3, [r3, #0] + 800c34e: 637b str r3, [r7, #52] ; 0x34 + 800c350: e00f b.n 800c372 + else if (flags & SIGN) + 800c352: 6a3b ldr r3, [r7, #32] + 800c354: f003 0302 and.w r3, r3, #2 + 800c358: 2b00 cmp r3, #0 + 800c35a: d005 beq.n 800c368 + num = va_arg(args, int); + 800c35c: 683b ldr r3, [r7, #0] + 800c35e: 1d1a adds r2, r3, #4 + 800c360: 603a str r2, [r7, #0] + 800c362: 681b ldr r3, [r3, #0] + 800c364: 637b str r3, [r7, #52] ; 0x34 + 800c366: e004 b.n 800c372 + else + num = va_arg(args, unsigned int); + 800c368: 683b ldr r3, [r7, #0] + 800c36a: 1d1a adds r2, r3, #4 + 800c36c: 603a str r2, [r7, #0] + 800c36e: 681b ldr r3, [r3, #0] + 800c370: 637b str r3, [r7, #52] ; 0x34 + + str = ee_number(str, ((size - 1) - (str - buf)), num, base, field_width, precision, flags); + 800c372: 68bb ldr r3, [r7, #8] + 800c374: 1e5a subs r2, r3, #1 + 800c376: 6af9 ldr r1, [r7, #44] ; 0x2c + 800c378: 68fb ldr r3, [r7, #12] + 800c37a: 1acb subs r3, r1, r3 + 800c37c: 1ad1 subs r1, r2, r3 + 800c37e: 6b7a ldr r2, [r7, #52] ; 0x34 + 800c380: 6a3b ldr r3, [r7, #32] + 800c382: 9302 str r3, [sp, #8] + 800c384: 69bb ldr r3, [r7, #24] + 800c386: 9301 str r3, [sp, #4] + 800c388: 69fb ldr r3, [r7, #28] + 800c38a: 9300 str r3, [sp, #0] + 800c38c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c38e: 6af8 ldr r0, [r7, #44] ; 0x2c + 800c390: f7ff fde0 bl 800bf54 + 800c394: 62f8 str r0, [r7, #44] ; 0x2c + 800c396: e000 b.n 800c39a + continue; + 800c398: bf00 nop + for (str = buf; *fmt || ((str - buf) >= size-1); fmt++) + 800c39a: 687b ldr r3, [r7, #4] + 800c39c: 3301 adds r3, #1 + 800c39e: 607b str r3, [r7, #4] + 800c3a0: 687b ldr r3, [r7, #4] + 800c3a2: 781b ldrb r3, [r3, #0] + 800c3a4: 2b00 cmp r3, #0 + 800c3a6: f47f aed2 bne.w 800c14e + 800c3aa: 6afa ldr r2, [r7, #44] ; 0x2c + 800c3ac: 68fb ldr r3, [r7, #12] + 800c3ae: 1ad2 subs r2, r2, r3 + 800c3b0: 68bb ldr r3, [r7, #8] + 800c3b2: 3b01 subs r3, #1 + 800c3b4: 429a cmp r2, r3 + 800c3b6: f6bf aeca bge.w 800c14e + } + + *str = '\0'; + 800c3ba: 6afb ldr r3, [r7, #44] ; 0x2c + 800c3bc: 2200 movs r2, #0 + 800c3be: 701a strb r2, [r3, #0] + return str - buf; + 800c3c0: 6afa ldr r2, [r7, #44] ; 0x2c + 800c3c2: 68fb ldr r3, [r7, #12] + 800c3c4: 1ad3 subs r3, r2, r3 +} + 800c3c6: 4618 mov r0, r3 + 800c3c8: 3738 adds r7, #56 ; 0x38 + 800c3ca: 46bd mov sp, r7 + 800c3cc: bd80 pop {r7, pc} + 800c3ce: bf00 nop + 800c3d0: 0800e2cc .word 0x0800e2cc + +0800c3d4 : + * That is the reason why many variables that are used only in that function are declared static. + * Note: These variables could have been declared static in the function. + * + */ +void UTIL_SEQ_Run( UTIL_SEQ_bm_t Mask_bm ) +{ + 800c3d4: b580 push {r7, lr} + 800c3d6: b090 sub sp, #64 ; 0x40 + 800c3d8: af00 add r7, sp, #0 + 800c3da: 6078 str r0, [r7, #4] + /* + * When this function is nested, the mask to be applied cannot be larger than the first call + * The mask is always getting smaller and smaller + * A copy is made of the mask set by UTIL_SEQ_Run() in case it is called again in the task + */ + super_mask_backup = SuperMask; + 800c3dc: 4b73 ldr r3, [pc, #460] ; (800c5ac ) + 800c3de: 681b ldr r3, [r3, #0] + 800c3e0: 62bb str r3, [r7, #40] ; 0x28 + SuperMask &= Mask_bm; + 800c3e2: 4b72 ldr r3, [pc, #456] ; (800c5ac ) + 800c3e4: 681a ldr r2, [r3, #0] + 800c3e6: 687b ldr r3, [r7, #4] + 800c3e8: 4013 ands r3, r2 + 800c3ea: 4a70 ldr r2, [pc, #448] ; (800c5ac ) + 800c3ec: 6013 str r3, [r2, #0] + * TaskMask that comes from UTIL_SEQ_PauseTask() / UTIL_SEQ_ResumeTask + * SuperMask that comes from UTIL_SEQ_Run + * If the waited event is there, exit from UTIL_SEQ_Run() to return to the + * waiting task + */ + local_taskset = TaskSet; + 800c3ee: 4b70 ldr r3, [pc, #448] ; (800c5b0 ) + 800c3f0: 681b ldr r3, [r3, #0] + 800c3f2: 63bb str r3, [r7, #56] ; 0x38 + local_evtset = EvtSet; + 800c3f4: 4b6f ldr r3, [pc, #444] ; (800c5b4 ) + 800c3f6: 681b ldr r3, [r3, #0] + 800c3f8: 637b str r3, [r7, #52] ; 0x34 + local_taskmask = TaskMask; + 800c3fa: 4b6f ldr r3, [pc, #444] ; (800c5b8 ) + 800c3fc: 681b ldr r3, [r3, #0] + 800c3fe: 633b str r3, [r7, #48] ; 0x30 + local_evtwaited = EvtWaited; + 800c400: 4b6e ldr r3, [pc, #440] ; (800c5bc ) + 800c402: 681b ldr r3, [r3, #0] + 800c404: 62fb str r3, [r7, #44] ; 0x2c + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 800c406: e08d b.n 800c524 + { + counter = 0U; + 800c408: 2300 movs r3, #0 + 800c40a: 63fb str r3, [r7, #60] ; 0x3c + /* + * When a flag is set, the associated bit is set in TaskPrio[counter].priority mask depending + * on the priority parameter given from UTIL_SEQ_SetTask() + * The while loop is looking for a flag set from the highest priority maskr to the lower + */ + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 800c40c: e002 b.n 800c414 + { + counter++; + 800c40e: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c410: 3301 adds r3, #1 + 800c412: 63fb str r3, [r7, #60] ; 0x3c + while((TaskPrio[counter].priority & local_taskmask & SuperMask)== 0U) + 800c414: 4a6a ldr r2, [pc, #424] ; (800c5c0 ) + 800c416: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c418: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800c41c: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c41e: 401a ands r2, r3 + 800c420: 4b62 ldr r3, [pc, #392] ; (800c5ac ) + 800c422: 681b ldr r3, [r3, #0] + 800c424: 4013 ands r3, r2 + 800c426: 2b00 cmp r3, #0 + 800c428: d0f1 beq.n 800c40e + } + + current_task_set = TaskPrio[counter].priority & local_taskmask & SuperMask; + 800c42a: 4a65 ldr r2, [pc, #404] ; (800c5c0 ) + 800c42c: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c42e: f852 2033 ldr.w r2, [r2, r3, lsl #3] + 800c432: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c434: 401a ands r2, r3 + 800c436: 4b5d ldr r3, [pc, #372] ; (800c5ac ) + 800c438: 681b ldr r3, [r3, #0] + 800c43a: 4013 ands r3, r2 + 800c43c: 627b str r3, [r7, #36] ; 0x24 + * so that the second one can be executed. + * Note that the first flag is not removed from the list of pending task but just masked by the round_robin mask + * + * In the check below, the round_robin mask is reinitialize in case all pending tasks haven been executed at least once + */ + if ((TaskPrio[counter].round_robin & current_task_set) == 0U) + 800c43e: 4a60 ldr r2, [pc, #384] ; (800c5c0 ) + 800c440: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c442: 00db lsls r3, r3, #3 + 800c444: 4413 add r3, r2 + 800c446: 685a ldr r2, [r3, #4] + 800c448: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c44a: 4013 ands r3, r2 + 800c44c: 2b00 cmp r3, #0 + 800c44e: d106 bne.n 800c45e + { + TaskPrio[counter].round_robin = UTIL_SEQ_ALL_BIT_SET; + 800c450: 4a5b ldr r2, [pc, #364] ; (800c5c0 ) + 800c452: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c454: 00db lsls r3, r3, #3 + 800c456: 4413 add r3, r2 + 800c458: f04f 32ff mov.w r2, #4294967295 + 800c45c: 605a str r2, [r3, #4] + /* + * Read the flag index of the task to be executed + * Once the index is read, the associated task will be executed even though a higher priority stack is requested + * before task execution. + */ + CurrentTaskIdx = (SEQ_BitPosition(current_task_set & TaskPrio[counter].round_robin)); + 800c45e: 4a58 ldr r2, [pc, #352] ; (800c5c0 ) + 800c460: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c462: 00db lsls r3, r3, #3 + 800c464: 4413 add r3, r2 + 800c466: 685a ldr r2, [r3, #4] + 800c468: 6a7b ldr r3, [r7, #36] ; 0x24 + 800c46a: 4013 ands r3, r2 + 800c46c: 4618 mov r0, r3 + 800c46e: f000 f8b9 bl 800c5e4 + 800c472: 4603 mov r3, r0 + 800c474: 461a mov r2, r3 + 800c476: 4b53 ldr r3, [pc, #332] ; (800c5c4 ) + 800c478: 601a str r2, [r3, #0] + + /* + * remove from the roun_robin mask the task that has been selected to be executed + */ + TaskPrio[counter].round_robin &= ~(1U << CurrentTaskIdx); + 800c47a: 4a51 ldr r2, [pc, #324] ; (800c5c0 ) + 800c47c: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c47e: 00db lsls r3, r3, #3 + 800c480: 4413 add r3, r2 + 800c482: 685a ldr r2, [r3, #4] + 800c484: 4b4f ldr r3, [pc, #316] ; (800c5c4 ) + 800c486: 681b ldr r3, [r3, #0] + 800c488: 2101 movs r1, #1 + 800c48a: fa01 f303 lsl.w r3, r1, r3 + 800c48e: 43db mvns r3, r3 + 800c490: 401a ands r2, r3 + 800c492: 494b ldr r1, [pc, #300] ; (800c5c0 ) + 800c494: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c496: 00db lsls r3, r3, #3 + 800c498: 440b add r3, r1 + 800c49a: 605a str r2, [r3, #4] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c49c: f3ef 8310 mrs r3, PRIMASK + 800c4a0: 61bb str r3, [r7, #24] + return(result); + 800c4a2: 69bb ldr r3, [r7, #24] + + UTIL_SEQ_ENTER_CRITICAL_SECTION( ); + 800c4a4: 623b str r3, [r7, #32] + __ASM volatile ("cpsid i" : : : "memory"); + 800c4a6: b672 cpsid i +} + 800c4a8: bf00 nop + /* remove from the list or pending task the one that has been selected to be executed */ + TaskSet &= ~(1U << CurrentTaskIdx); + 800c4aa: 4b46 ldr r3, [pc, #280] ; (800c5c4 ) + 800c4ac: 681b ldr r3, [r3, #0] + 800c4ae: 2201 movs r2, #1 + 800c4b0: fa02 f303 lsl.w r3, r2, r3 + 800c4b4: 43da mvns r2, r3 + 800c4b6: 4b3e ldr r3, [pc, #248] ; (800c5b0 ) + 800c4b8: 681b ldr r3, [r3, #0] + 800c4ba: 4013 ands r3, r2 + 800c4bc: 4a3c ldr r2, [pc, #240] ; (800c5b0 ) + 800c4be: 6013 str r3, [r2, #0] + /* remove from all priority mask the task that has been selected to be executed */ + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800c4c0: 2301 movs r3, #1 + 800c4c2: 63fb str r3, [r7, #60] ; 0x3c + 800c4c4: e013 b.n 800c4ee + { + TaskPrio[counter - 1U].priority &= ~(1U << CurrentTaskIdx); + 800c4c6: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c4c8: 3b01 subs r3, #1 + 800c4ca: 4a3d ldr r2, [pc, #244] ; (800c5c0 ) + 800c4cc: f852 1033 ldr.w r1, [r2, r3, lsl #3] + 800c4d0: 4b3c ldr r3, [pc, #240] ; (800c5c4 ) + 800c4d2: 681b ldr r3, [r3, #0] + 800c4d4: 2201 movs r2, #1 + 800c4d6: fa02 f303 lsl.w r3, r2, r3 + 800c4da: 43da mvns r2, r3 + 800c4dc: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c4de: 3b01 subs r3, #1 + 800c4e0: 400a ands r2, r1 + 800c4e2: 4937 ldr r1, [pc, #220] ; (800c5c0 ) + 800c4e4: f841 2033 str.w r2, [r1, r3, lsl #3] + for (counter = UTIL_SEQ_CONF_PRIO_NBR; counter != 0U; counter--) + 800c4e8: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c4ea: 3b01 subs r3, #1 + 800c4ec: 63fb str r3, [r7, #60] ; 0x3c + 800c4ee: 6bfb ldr r3, [r7, #60] ; 0x3c + 800c4f0: 2b00 cmp r3, #0 + 800c4f2: d1e8 bne.n 800c4c6 + 800c4f4: 6a3b ldr r3, [r7, #32] + 800c4f6: 617b str r3, [r7, #20] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c4f8: 697b ldr r3, [r7, #20] + 800c4fa: f383 8810 msr PRIMASK, r3 +} + 800c4fe: bf00 nop + } + UTIL_SEQ_EXIT_CRITICAL_SECTION( ); + + /* Execute the task */ + TaskCb[CurrentTaskIdx]( ); + 800c500: 4b30 ldr r3, [pc, #192] ; (800c5c4 ) + 800c502: 681b ldr r3, [r3, #0] + 800c504: 4a30 ldr r2, [pc, #192] ; (800c5c8 ) + 800c506: f852 3023 ldr.w r3, [r2, r3, lsl #2] + 800c50a: 4798 blx r3 + + local_taskset = TaskSet; + 800c50c: 4b28 ldr r3, [pc, #160] ; (800c5b0 ) + 800c50e: 681b ldr r3, [r3, #0] + 800c510: 63bb str r3, [r7, #56] ; 0x38 + local_evtset = EvtSet; + 800c512: 4b28 ldr r3, [pc, #160] ; (800c5b4 ) + 800c514: 681b ldr r3, [r3, #0] + 800c516: 637b str r3, [r7, #52] ; 0x34 + local_taskmask = TaskMask; + 800c518: 4b27 ldr r3, [pc, #156] ; (800c5b8 ) + 800c51a: 681b ldr r3, [r3, #0] + 800c51c: 633b str r3, [r7, #48] ; 0x30 + local_evtwaited = EvtWaited; + 800c51e: 4b27 ldr r3, [pc, #156] ; (800c5bc ) + 800c520: 681b ldr r3, [r3, #0] + 800c522: 62fb str r3, [r7, #44] ; 0x2c + while(((local_taskset & local_taskmask & SuperMask) != 0U) && ((local_evtset & local_evtwaited)==0U)) + 800c524: 6bba ldr r2, [r7, #56] ; 0x38 + 800c526: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c528: 401a ands r2, r3 + 800c52a: 4b20 ldr r3, [pc, #128] ; (800c5ac ) + 800c52c: 681b ldr r3, [r3, #0] + 800c52e: 4013 ands r3, r2 + 800c530: 2b00 cmp r3, #0 + 800c532: d005 beq.n 800c540 + 800c534: 6b7a ldr r2, [r7, #52] ; 0x34 + 800c536: 6afb ldr r3, [r7, #44] ; 0x2c + 800c538: 4013 ands r3, r2 + 800c53a: 2b00 cmp r3, #0 + 800c53c: f43f af64 beq.w 800c408 + } + + /* the set of CurrentTaskIdx to no task running allows to call WaitEvt in the Pre/Post ilde context */ + CurrentTaskIdx = UTIL_SEQ_NOTASKRUNNING; + 800c540: 4b20 ldr r3, [pc, #128] ; (800c5c4 ) + 800c542: f04f 32ff mov.w r2, #4294967295 + 800c546: 601a str r2, [r3, #0] + UTIL_SEQ_PreIdle( ); + 800c548: f000 f840 bl 800c5cc + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c54c: f3ef 8310 mrs r3, PRIMASK + 800c550: 613b str r3, [r7, #16] + return(result); + 800c552: 693b ldr r3, [r7, #16] + + UTIL_SEQ_ENTER_CRITICAL_SECTION_IDLE( ); + 800c554: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800c556: b672 cpsid i +} + 800c558: bf00 nop + local_taskset = TaskSet; + 800c55a: 4b15 ldr r3, [pc, #84] ; (800c5b0 ) + 800c55c: 681b ldr r3, [r3, #0] + 800c55e: 63bb str r3, [r7, #56] ; 0x38 + local_evtset = EvtSet; + 800c560: 4b14 ldr r3, [pc, #80] ; (800c5b4 ) + 800c562: 681b ldr r3, [r3, #0] + 800c564: 637b str r3, [r7, #52] ; 0x34 + local_taskmask = TaskMask; + 800c566: 4b14 ldr r3, [pc, #80] ; (800c5b8 ) + 800c568: 681b ldr r3, [r3, #0] + 800c56a: 633b str r3, [r7, #48] ; 0x30 + if ((local_taskset & local_taskmask & SuperMask) == 0U) + 800c56c: 6bba ldr r2, [r7, #56] ; 0x38 + 800c56e: 6b3b ldr r3, [r7, #48] ; 0x30 + 800c570: 401a ands r2, r3 + 800c572: 4b0e ldr r3, [pc, #56] ; (800c5ac ) + 800c574: 681b ldr r3, [r3, #0] + 800c576: 4013 ands r3, r2 + 800c578: 2b00 cmp r3, #0 + 800c57a: d107 bne.n 800c58c + { + if ((local_evtset & EvtWaited)== 0U) + 800c57c: 4b0f ldr r3, [pc, #60] ; (800c5bc ) + 800c57e: 681a ldr r2, [r3, #0] + 800c580: 6b7b ldr r3, [r7, #52] ; 0x34 + 800c582: 4013 ands r3, r2 + 800c584: 2b00 cmp r3, #0 + 800c586: d101 bne.n 800c58c + { + UTIL_SEQ_Idle( ); + 800c588: f7f4 fb7c bl 8000c84 + 800c58c: 69fb ldr r3, [r7, #28] + 800c58e: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c590: 68fb ldr r3, [r7, #12] + 800c592: f383 8810 msr PRIMASK, r3 +} + 800c596: bf00 nop + } + } + UTIL_SEQ_EXIT_CRITICAL_SECTION_IDLE( ); + + UTIL_SEQ_PostIdle( ); + 800c598: f000 f81e bl 800c5d8 + + /* restore the mask from UTIL_SEQ_Run() */ + SuperMask = super_mask_backup; + 800c59c: 4a03 ldr r2, [pc, #12] ; (800c5ac ) + 800c59e: 6abb ldr r3, [r7, #40] ; 0x28 + 800c5a0: 6013 str r3, [r2, #0] + + return; + 800c5a2: bf00 nop +} + 800c5a4: 3740 adds r7, #64 ; 0x40 + 800c5a6: 46bd mov sp, r7 + 800c5a8: bd80 pop {r7, pc} + 800c5aa: bf00 nop + 800c5ac: 20000030 .word 0x20000030 + 800c5b0: 200005c4 .word 0x200005c4 + 800c5b4: 200005c8 .word 0x200005c8 + 800c5b8: 2000002c .word 0x2000002c + 800c5bc: 200005cc .word 0x200005cc + 800c5c0: 200005d8 .word 0x200005d8 + 800c5c4: 200005d0 .word 0x200005d0 + 800c5c8: 200005d4 .word 0x200005d4 + +0800c5cc : +{ + return; +} + +__WEAK void UTIL_SEQ_PreIdle( void ) +{ + 800c5cc: b480 push {r7} + 800c5ce: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 800c5d0: bf00 nop +} + 800c5d2: 46bd mov sp, r7 + 800c5d4: bc80 pop {r7} + 800c5d6: 4770 bx lr + +0800c5d8 : + +__WEAK void UTIL_SEQ_PostIdle( void ) +{ + 800c5d8: b480 push {r7} + 800c5da: af00 add r7, sp, #0 + /* + * Unless specified by the application, there is nothing to be done + */ + return; + 800c5dc: bf00 nop +} + 800c5de: 46bd mov sp, r7 + 800c5e0: bc80 pop {r7} + 800c5e2: 4770 bx lr + +0800c5e4 : + * @brief return the position of the first bit set to 1 + * @param Value 32 bit value + * @retval bit position + */ +uint8_t SEQ_BitPosition(uint32_t Value) +{ + 800c5e4: b480 push {r7} + 800c5e6: b085 sub sp, #20 + 800c5e8: af00 add r7, sp, #0 + 800c5ea: 6078 str r0, [r7, #4] +uint8_t n = 0U; + 800c5ec: 2300 movs r3, #0 + 800c5ee: 73fb strb r3, [r7, #15] +uint32_t lvalue = Value; + 800c5f0: 687b ldr r3, [r7, #4] + 800c5f2: 60bb str r3, [r7, #8] + + if ((lvalue & 0xFFFF0000U) == 0U) { n = 16U; lvalue <<= 16U; } + 800c5f4: 68bb ldr r3, [r7, #8] + 800c5f6: 0c1b lsrs r3, r3, #16 + 800c5f8: 041b lsls r3, r3, #16 + 800c5fa: 2b00 cmp r3, #0 + 800c5fc: d104 bne.n 800c608 + 800c5fe: 2310 movs r3, #16 + 800c600: 73fb strb r3, [r7, #15] + 800c602: 68bb ldr r3, [r7, #8] + 800c604: 041b lsls r3, r3, #16 + 800c606: 60bb str r3, [r7, #8] + if ((lvalue & 0xFF000000U) == 0U) { n += 8U; lvalue <<= 8U; } + 800c608: 68bb ldr r3, [r7, #8] + 800c60a: f003 437f and.w r3, r3, #4278190080 ; 0xff000000 + 800c60e: 2b00 cmp r3, #0 + 800c610: d105 bne.n 800c61e + 800c612: 7bfb ldrb r3, [r7, #15] + 800c614: 3308 adds r3, #8 + 800c616: 73fb strb r3, [r7, #15] + 800c618: 68bb ldr r3, [r7, #8] + 800c61a: 021b lsls r3, r3, #8 + 800c61c: 60bb str r3, [r7, #8] + if ((lvalue & 0xF0000000U) == 0U) { n += 4U; lvalue <<= 4U; } + 800c61e: 68bb ldr r3, [r7, #8] + 800c620: f003 4370 and.w r3, r3, #4026531840 ; 0xf0000000 + 800c624: 2b00 cmp r3, #0 + 800c626: d105 bne.n 800c634 + 800c628: 7bfb ldrb r3, [r7, #15] + 800c62a: 3304 adds r3, #4 + 800c62c: 73fb strb r3, [r7, #15] + 800c62e: 68bb ldr r3, [r7, #8] + 800c630: 011b lsls r3, r3, #4 + 800c632: 60bb str r3, [r7, #8] + + n += SEQ_clz_table_4bit[lvalue >> (32-4)]; + 800c634: 68bb ldr r3, [r7, #8] + 800c636: 0f1b lsrs r3, r3, #28 + 800c638: 4a06 ldr r2, [pc, #24] ; (800c654 ) + 800c63a: 5cd2 ldrb r2, [r2, r3] + 800c63c: 7bfb ldrb r3, [r7, #15] + 800c63e: 4413 add r3, r2 + 800c640: 73fb strb r3, [r7, #15] + + return (uint8_t)(31U-n); + 800c642: 7bfb ldrb r3, [r7, #15] + 800c644: f1c3 031f rsb r3, r3, #31 + 800c648: b2db uxtb r3, r3 +} + 800c64a: 4618 mov r0, r3 + 800c64c: 3714 adds r7, #20 + 800c64e: 46bd mov sp, r7 + 800c650: bc80 pop {r7} + 800c652: 4770 bx lr + 800c654: 0800e544 .word 0x0800e544 + +0800c658 : + * @addtogroup TIMER_SERVER_exported_function + * @{ + */ + +UTIL_TIMER_Status_t UTIL_TIMER_Init(void) +{ + 800c658: b580 push {r7, lr} + 800c65a: af00 add r7, sp, #0 + UTIL_TIMER_INIT_CRITICAL_SECTION(); + TimerListHead = NULL; + 800c65c: 4b04 ldr r3, [pc, #16] ; (800c670 ) + 800c65e: 2200 movs r2, #0 + 800c660: 601a str r2, [r3, #0] + return UTIL_TimerDriver.InitTimer(); + 800c662: 4b04 ldr r3, [pc, #16] ; (800c674 ) + 800c664: 681b ldr r3, [r3, #0] + 800c666: 4798 blx r3 + 800c668: 4603 mov r3, r0 +} + 800c66a: 4618 mov r0, r3 + 800c66c: bd80 pop {r7, pc} + 800c66e: bf00 nop + 800c670: 200005e0 .word 0x200005e0 + 800c674: 0800e38c .word 0x0800e38c + +0800c678 : +{ + return UTIL_TimerDriver.DeInitTimer(); +} + +UTIL_TIMER_Status_t UTIL_TIMER_Create( UTIL_TIMER_Object_t *TimerObject, uint32_t PeriodValue, UTIL_TIMER_Mode_t Mode, void ( *Callback )( void *), void *Argument) +{ + 800c678: b580 push {r7, lr} + 800c67a: b084 sub sp, #16 + 800c67c: af00 add r7, sp, #0 + 800c67e: 60f8 str r0, [r7, #12] + 800c680: 60b9 str r1, [r7, #8] + 800c682: 603b str r3, [r7, #0] + 800c684: 4613 mov r3, r2 + 800c686: 71fb strb r3, [r7, #7] + if((TimerObject != NULL) && (Callback != NULL)) + 800c688: 68fb ldr r3, [r7, #12] + 800c68a: 2b00 cmp r3, #0 + 800c68c: d023 beq.n 800c6d6 + 800c68e: 683b ldr r3, [r7, #0] + 800c690: 2b00 cmp r3, #0 + 800c692: d020 beq.n 800c6d6 + { + TimerObject->Timestamp = 0U; + 800c694: 68fb ldr r3, [r7, #12] + 800c696: 2200 movs r2, #0 + 800c698: 601a str r2, [r3, #0] + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(PeriodValue); + 800c69a: 4b11 ldr r3, [pc, #68] ; (800c6e0 ) + 800c69c: 6a5b ldr r3, [r3, #36] ; 0x24 + 800c69e: 68b8 ldr r0, [r7, #8] + 800c6a0: 4798 blx r3 + 800c6a2: 4602 mov r2, r0 + 800c6a4: 68fb ldr r3, [r7, #12] + 800c6a6: 605a str r2, [r3, #4] + TimerObject->IsPending = 0U; + 800c6a8: 68fb ldr r3, [r7, #12] + 800c6aa: 2200 movs r2, #0 + 800c6ac: 721a strb r2, [r3, #8] + TimerObject->IsRunning = 0U; + 800c6ae: 68fb ldr r3, [r7, #12] + 800c6b0: 2200 movs r2, #0 + 800c6b2: 725a strb r2, [r3, #9] + TimerObject->IsReloadStopped = 0U; + 800c6b4: 68fb ldr r3, [r7, #12] + 800c6b6: 2200 movs r2, #0 + 800c6b8: 729a strb r2, [r3, #10] + TimerObject->Callback = Callback; + 800c6ba: 68fb ldr r3, [r7, #12] + 800c6bc: 683a ldr r2, [r7, #0] + 800c6be: 60da str r2, [r3, #12] + TimerObject->argument = Argument; + 800c6c0: 68fb ldr r3, [r7, #12] + 800c6c2: 69ba ldr r2, [r7, #24] + 800c6c4: 611a str r2, [r3, #16] + TimerObject->Mode = Mode; + 800c6c6: 68fb ldr r3, [r7, #12] + 800c6c8: 79fa ldrb r2, [r7, #7] + 800c6ca: 72da strb r2, [r3, #11] + TimerObject->Next = NULL; + 800c6cc: 68fb ldr r3, [r7, #12] + 800c6ce: 2200 movs r2, #0 + 800c6d0: 615a str r2, [r3, #20] + return UTIL_TIMER_OK; + 800c6d2: 2300 movs r3, #0 + 800c6d4: e000 b.n 800c6d8 + } + else + { + return UTIL_TIMER_INVALID_PARAM; + 800c6d6: 2301 movs r3, #1 + } +} + 800c6d8: 4618 mov r0, r3 + 800c6da: 3710 adds r7, #16 + 800c6dc: 46bd mov sp, r7 + 800c6de: bd80 pop {r7, pc} + 800c6e0: 0800e38c .word 0x0800e38c + +0800c6e4 : + +UTIL_TIMER_Status_t UTIL_TIMER_Start( UTIL_TIMER_Object_t *TimerObject) +{ + 800c6e4: b580 push {r7, lr} + 800c6e6: b08a sub sp, #40 ; 0x28 + 800c6e8: af00 add r7, sp, #0 + 800c6ea: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800c6ec: 2300 movs r3, #0 + 800c6ee: f887 3027 strb.w r3, [r7, #39] ; 0x27 + uint32_t elapsedTime; + uint32_t minValue; + uint32_t ticks; + + if(( TimerObject != NULL ) && ( TimerExists( TimerObject ) == false ) && (TimerObject->IsRunning == 0U)) + 800c6f2: 687b ldr r3, [r7, #4] + 800c6f4: 2b00 cmp r3, #0 + 800c6f6: d056 beq.n 800c7a6 + 800c6f8: 6878 ldr r0, [r7, #4] + 800c6fa: f000 f929 bl 800c950 + 800c6fe: 4603 mov r3, r0 + 800c700: f083 0301 eor.w r3, r3, #1 + 800c704: b2db uxtb r3, r3 + 800c706: 2b00 cmp r3, #0 + 800c708: d04d beq.n 800c7a6 + 800c70a: 687b ldr r3, [r7, #4] + 800c70c: 7a5b ldrb r3, [r3, #9] + 800c70e: 2b00 cmp r3, #0 + 800c710: d149 bne.n 800c7a6 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c712: f3ef 8310 mrs r3, PRIMASK + 800c716: 613b str r3, [r7, #16] + return(result); + 800c718: 693b ldr r3, [r7, #16] + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800c71a: 61fb str r3, [r7, #28] + __ASM volatile ("cpsid i" : : : "memory"); + 800c71c: b672 cpsid i +} + 800c71e: bf00 nop + ticks = TimerObject->ReloadValue; + 800c720: 687b ldr r3, [r7, #4] + 800c722: 685b ldr r3, [r3, #4] + 800c724: 623b str r3, [r7, #32] + minValue = UTIL_TimerDriver.GetMinimumTimeout( ); + 800c726: 4b24 ldr r3, [pc, #144] ; (800c7b8 ) + 800c728: 6a1b ldr r3, [r3, #32] + 800c72a: 4798 blx r3 + 800c72c: 61b8 str r0, [r7, #24] + + if( ticks < minValue ) + 800c72e: 6a3a ldr r2, [r7, #32] + 800c730: 69bb ldr r3, [r7, #24] + 800c732: 429a cmp r2, r3 + 800c734: d201 bcs.n 800c73a + { + ticks = minValue; + 800c736: 69bb ldr r3, [r7, #24] + 800c738: 623b str r3, [r7, #32] + } + + TimerObject->Timestamp = ticks; + 800c73a: 687b ldr r3, [r7, #4] + 800c73c: 6a3a ldr r2, [r7, #32] + 800c73e: 601a str r2, [r3, #0] + TimerObject->IsPending = 0U; + 800c740: 687b ldr r3, [r7, #4] + 800c742: 2200 movs r2, #0 + 800c744: 721a strb r2, [r3, #8] + TimerObject->IsRunning = 1U; + 800c746: 687b ldr r3, [r7, #4] + 800c748: 2201 movs r2, #1 + 800c74a: 725a strb r2, [r3, #9] + TimerObject->IsReloadStopped = 0U; + 800c74c: 687b ldr r3, [r7, #4] + 800c74e: 2200 movs r2, #0 + 800c750: 729a strb r2, [r3, #10] + if( TimerListHead == NULL ) + 800c752: 4b1a ldr r3, [pc, #104] ; (800c7bc ) + 800c754: 681b ldr r3, [r3, #0] + 800c756: 2b00 cmp r3, #0 + 800c758: d106 bne.n 800c768 + { + UTIL_TimerDriver.SetTimerContext(); + 800c75a: 4b17 ldr r3, [pc, #92] ; (800c7b8 ) + 800c75c: 691b ldr r3, [r3, #16] + 800c75e: 4798 blx r3 + TimerInsertNewHeadTimer( TimerObject ); /* insert a timeout at now+obj->Timestamp */ + 800c760: 6878 ldr r0, [r7, #4] + 800c762: f000 f96b bl 800ca3c + 800c766: e017 b.n 800c798 + } + else + { + elapsedTime = UTIL_TimerDriver.GetTimerElapsedTime( ); + 800c768: 4b13 ldr r3, [pc, #76] ; (800c7b8 ) + 800c76a: 699b ldr r3, [r3, #24] + 800c76c: 4798 blx r3 + 800c76e: 6178 str r0, [r7, #20] + TimerObject->Timestamp += elapsedTime; + 800c770: 687b ldr r3, [r7, #4] + 800c772: 681a ldr r2, [r3, #0] + 800c774: 697b ldr r3, [r7, #20] + 800c776: 441a add r2, r3 + 800c778: 687b ldr r3, [r7, #4] + 800c77a: 601a str r2, [r3, #0] + + if( TimerObject->Timestamp < TimerListHead->Timestamp ) + 800c77c: 687b ldr r3, [r7, #4] + 800c77e: 681a ldr r2, [r3, #0] + 800c780: 4b0e ldr r3, [pc, #56] ; (800c7bc ) + 800c782: 681b ldr r3, [r3, #0] + 800c784: 681b ldr r3, [r3, #0] + 800c786: 429a cmp r2, r3 + 800c788: d203 bcs.n 800c792 + { + TimerInsertNewHeadTimer( TimerObject); + 800c78a: 6878 ldr r0, [r7, #4] + 800c78c: f000 f956 bl 800ca3c + 800c790: e002 b.n 800c798 + } + else + { + TimerInsertTimer( TimerObject); + 800c792: 6878 ldr r0, [r7, #4] + 800c794: f000 f922 bl 800c9dc + 800c798: 69fb ldr r3, [r7, #28] + 800c79a: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c79c: 68fb ldr r3, [r7, #12] + 800c79e: f383 8810 msr PRIMASK, r3 +} + 800c7a2: bf00 nop + { + 800c7a4: e002 b.n 800c7ac + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + 800c7a6: 2301 movs r3, #1 + 800c7a8: f887 3027 strb.w r3, [r7, #39] ; 0x27 + } + return ret; + 800c7ac: f897 3027 ldrb.w r3, [r7, #39] ; 0x27 +} + 800c7b0: 4618 mov r0, r3 + 800c7b2: 3728 adds r7, #40 ; 0x28 + 800c7b4: 46bd mov sp, r7 + 800c7b6: bd80 pop {r7, pc} + 800c7b8: 0800e38c .word 0x0800e38c + 800c7bc: 200005e0 .word 0x200005e0 + +0800c7c0 : + } + return ret; +} + +UTIL_TIMER_Status_t UTIL_TIMER_Stop( UTIL_TIMER_Object_t *TimerObject ) +{ + 800c7c0: b580 push {r7, lr} + 800c7c2: b088 sub sp, #32 + 800c7c4: af00 add r7, sp, #0 + 800c7c6: 6078 str r0, [r7, #4] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800c7c8: 2300 movs r3, #0 + 800c7ca: 77fb strb r3, [r7, #31] + + if (NULL != TimerObject) + 800c7cc: 687b ldr r3, [r7, #4] + 800c7ce: 2b00 cmp r3, #0 + 800c7d0: d05b beq.n 800c88a + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800c7d2: f3ef 8310 mrs r3, PRIMASK + 800c7d6: 60fb str r3, [r7, #12] + return(result); + 800c7d8: 68fb ldr r3, [r7, #12] + { + UTIL_TIMER_ENTER_CRITICAL_SECTION(); + 800c7da: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 800c7dc: b672 cpsid i +} + 800c7de: bf00 nop + UTIL_TIMER_Object_t* prev = TimerListHead; + 800c7e0: 4b2d ldr r3, [pc, #180] ; (800c898 ) + 800c7e2: 681b ldr r3, [r3, #0] + 800c7e4: 61bb str r3, [r7, #24] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800c7e6: 4b2c ldr r3, [pc, #176] ; (800c898 ) + 800c7e8: 681b ldr r3, [r3, #0] + 800c7ea: 617b str r3, [r7, #20] + TimerObject->IsReloadStopped = 1U; + 800c7ec: 687b ldr r3, [r7, #4] + 800c7ee: 2201 movs r2, #1 + 800c7f0: 729a strb r2, [r3, #10] + + /* List is empty or the Obj to stop does not exist */ + if(NULL != TimerListHead) + 800c7f2: 4b29 ldr r3, [pc, #164] ; (800c898 ) + 800c7f4: 681b ldr r3, [r3, #0] + 800c7f6: 2b00 cmp r3, #0 + 800c7f8: d041 beq.n 800c87e + { + TimerObject->IsRunning = 0U; + 800c7fa: 687b ldr r3, [r7, #4] + 800c7fc: 2200 movs r2, #0 + 800c7fe: 725a strb r2, [r3, #9] + + if( TimerListHead == TimerObject ) /* Stop the Head */ + 800c800: 4b25 ldr r3, [pc, #148] ; (800c898 ) + 800c802: 681b ldr r3, [r3, #0] + 800c804: 687a ldr r2, [r7, #4] + 800c806: 429a cmp r2, r3 + 800c808: d134 bne.n 800c874 + { + TimerListHead->IsPending = 0; + 800c80a: 4b23 ldr r3, [pc, #140] ; (800c898 ) + 800c80c: 681b ldr r3, [r3, #0] + 800c80e: 2200 movs r2, #0 + 800c810: 721a strb r2, [r3, #8] + if( TimerListHead->Next != NULL ) + 800c812: 4b21 ldr r3, [pc, #132] ; (800c898 ) + 800c814: 681b ldr r3, [r3, #0] + 800c816: 695b ldr r3, [r3, #20] + 800c818: 2b00 cmp r3, #0 + 800c81a: d00a beq.n 800c832 + { + TimerListHead = TimerListHead->Next; + 800c81c: 4b1e ldr r3, [pc, #120] ; (800c898 ) + 800c81e: 681b ldr r3, [r3, #0] + 800c820: 695b ldr r3, [r3, #20] + 800c822: 4a1d ldr r2, [pc, #116] ; (800c898 ) + 800c824: 6013 str r3, [r2, #0] + TimerSetTimeout( TimerListHead ); + 800c826: 4b1c ldr r3, [pc, #112] ; (800c898 ) + 800c828: 681b ldr r3, [r3, #0] + 800c82a: 4618 mov r0, r3 + 800c82c: f000 f8ac bl 800c988 + 800c830: e023 b.n 800c87a + } + else + { + UTIL_TimerDriver.StopTimerEvt( ); + 800c832: 4b1a ldr r3, [pc, #104] ; (800c89c ) + 800c834: 68db ldr r3, [r3, #12] + 800c836: 4798 blx r3 + TimerListHead = NULL; + 800c838: 4b17 ldr r3, [pc, #92] ; (800c898 ) + 800c83a: 2200 movs r2, #0 + 800c83c: 601a str r2, [r3, #0] + 800c83e: e01c b.n 800c87a + } + else /* Stop an object within the list */ + { + while( cur != NULL ) + { + if( cur == TimerObject ) + 800c840: 697a ldr r2, [r7, #20] + 800c842: 687b ldr r3, [r7, #4] + 800c844: 429a cmp r2, r3 + 800c846: d110 bne.n 800c86a + { + if( cur->Next != NULL ) + 800c848: 697b ldr r3, [r7, #20] + 800c84a: 695b ldr r3, [r3, #20] + 800c84c: 2b00 cmp r3, #0 + 800c84e: d006 beq.n 800c85e + { + cur = cur->Next; + 800c850: 697b ldr r3, [r7, #20] + 800c852: 695b ldr r3, [r3, #20] + 800c854: 617b str r3, [r7, #20] + prev->Next = cur; + 800c856: 69bb ldr r3, [r7, #24] + 800c858: 697a ldr r2, [r7, #20] + 800c85a: 615a str r2, [r3, #20] + else + { + cur = NULL; + prev->Next = cur; + } + break; + 800c85c: e00d b.n 800c87a + cur = NULL; + 800c85e: 2300 movs r3, #0 + 800c860: 617b str r3, [r7, #20] + prev->Next = cur; + 800c862: 69bb ldr r3, [r7, #24] + 800c864: 697a ldr r2, [r7, #20] + 800c866: 615a str r2, [r3, #20] + break; + 800c868: e007 b.n 800c87a + } + else + { + prev = cur; + 800c86a: 697b ldr r3, [r7, #20] + 800c86c: 61bb str r3, [r7, #24] + cur = cur->Next; + 800c86e: 697b ldr r3, [r7, #20] + 800c870: 695b ldr r3, [r3, #20] + 800c872: 617b str r3, [r7, #20] + while( cur != NULL ) + 800c874: 697b ldr r3, [r7, #20] + 800c876: 2b00 cmp r3, #0 + 800c878: d1e2 bne.n 800c840 + } + } + } + ret = UTIL_TIMER_OK; + 800c87a: 2300 movs r3, #0 + 800c87c: 77fb strb r3, [r7, #31] + 800c87e: 693b ldr r3, [r7, #16] + 800c880: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800c882: 68bb ldr r3, [r7, #8] + 800c884: f383 8810 msr PRIMASK, r3 +} + 800c888: e001 b.n 800c88e + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); + } + else + { + ret = UTIL_TIMER_INVALID_PARAM; + 800c88a: 2301 movs r3, #1 + 800c88c: 77fb strb r3, [r7, #31] + } + return ret; + 800c88e: 7ffb ldrb r3, [r7, #31] +} + 800c890: 4618 mov r0, r3 + 800c892: 3720 adds r7, #32 + 800c894: 46bd mov sp, r7 + 800c896: bd80 pop {r7, pc} + 800c898: 200005e0 .word 0x200005e0 + 800c89c: 0800e38c .word 0x0800e38c + +0800c8a0 : + +UTIL_TIMER_Status_t UTIL_TIMER_SetPeriod(UTIL_TIMER_Object_t *TimerObject, uint32_t NewPeriodValue) +{ + 800c8a0: b580 push {r7, lr} + 800c8a2: b084 sub sp, #16 + 800c8a4: af00 add r7, sp, #0 + 800c8a6: 6078 str r0, [r7, #4] + 800c8a8: 6039 str r1, [r7, #0] + UTIL_TIMER_Status_t ret = UTIL_TIMER_OK; + 800c8aa: 2300 movs r3, #0 + 800c8ac: 73fb strb r3, [r7, #15] + + if(NULL == TimerObject) + 800c8ae: 687b ldr r3, [r7, #4] + 800c8b0: 2b00 cmp r3, #0 + 800c8b2: d102 bne.n 800c8ba + { + ret = UTIL_TIMER_INVALID_PARAM; + 800c8b4: 2301 movs r3, #1 + 800c8b6: 73fb strb r3, [r7, #15] + 800c8b8: e014 b.n 800c8e4 + } + else + { + TimerObject->ReloadValue = UTIL_TimerDriver.ms2Tick(NewPeriodValue); + 800c8ba: 4b0d ldr r3, [pc, #52] ; (800c8f0 ) + 800c8bc: 6a5b ldr r3, [r3, #36] ; 0x24 + 800c8be: 6838 ldr r0, [r7, #0] + 800c8c0: 4798 blx r3 + 800c8c2: 4602 mov r2, r0 + 800c8c4: 687b ldr r3, [r7, #4] + 800c8c6: 605a str r2, [r3, #4] + if(TimerExists(TimerObject)) + 800c8c8: 6878 ldr r0, [r7, #4] + 800c8ca: f000 f841 bl 800c950 + 800c8ce: 4603 mov r3, r0 + 800c8d0: 2b00 cmp r3, #0 + 800c8d2: d007 beq.n 800c8e4 + { + (void)UTIL_TIMER_Stop(TimerObject); + 800c8d4: 6878 ldr r0, [r7, #4] + 800c8d6: f7ff ff73 bl 800c7c0 + ret = UTIL_TIMER_Start(TimerObject); + 800c8da: 6878 ldr r0, [r7, #4] + 800c8dc: f7ff ff02 bl 800c6e4 + 800c8e0: 4603 mov r3, r0 + 800c8e2: 73fb strb r3, [r7, #15] + } + } + return ret; + 800c8e4: 7bfb ldrb r3, [r7, #15] +} + 800c8e6: 4618 mov r0, r3 + 800c8e8: 3710 adds r7, #16 + 800c8ea: 46bd mov sp, r7 + 800c8ec: bd80 pop {r7, pc} + 800c8ee: bf00 nop + 800c8f0: 0800e38c .word 0x0800e38c + +0800c8f4 : + } + UTIL_TIMER_EXIT_CRITICAL_SECTION(); +} + +UTIL_TIMER_Time_t UTIL_TIMER_GetCurrentTime(void) +{ + 800c8f4: b580 push {r7, lr} + 800c8f6: b082 sub sp, #8 + 800c8f8: af00 add r7, sp, #0 + uint32_t now = UTIL_TimerDriver.GetTimerValue( ); + 800c8fa: 4b06 ldr r3, [pc, #24] ; (800c914 ) + 800c8fc: 69db ldr r3, [r3, #28] + 800c8fe: 4798 blx r3 + 800c900: 6078 str r0, [r7, #4] + return UTIL_TimerDriver.Tick2ms(now); + 800c902: 4b04 ldr r3, [pc, #16] ; (800c914 ) + 800c904: 6a9b ldr r3, [r3, #40] ; 0x28 + 800c906: 6878 ldr r0, [r7, #4] + 800c908: 4798 blx r3 + 800c90a: 4603 mov r3, r0 +} + 800c90c: 4618 mov r0, r3 + 800c90e: 3708 adds r7, #8 + 800c910: 46bd mov sp, r7 + 800c912: bd80 pop {r7, pc} + 800c914: 0800e38c .word 0x0800e38c + +0800c918 : + +UTIL_TIMER_Time_t UTIL_TIMER_GetElapsedTime(UTIL_TIMER_Time_t past ) +{ + 800c918: b580 push {r7, lr} + 800c91a: b084 sub sp, #16 + 800c91c: af00 add r7, sp, #0 + 800c91e: 6078 str r0, [r7, #4] + uint32_t nowInTicks = UTIL_TimerDriver.GetTimerValue( ); + 800c920: 4b0a ldr r3, [pc, #40] ; (800c94c ) + 800c922: 69db ldr r3, [r3, #28] + 800c924: 4798 blx r3 + 800c926: 60f8 str r0, [r7, #12] + uint32_t pastInTicks = UTIL_TimerDriver.ms2Tick( past ); + 800c928: 4b08 ldr r3, [pc, #32] ; (800c94c ) + 800c92a: 6a5b ldr r3, [r3, #36] ; 0x24 + 800c92c: 6878 ldr r0, [r7, #4] + 800c92e: 4798 blx r3 + 800c930: 60b8 str r0, [r7, #8] + /* intentional wrap around. Works Ok if tick duation below 1ms */ + return UTIL_TimerDriver.Tick2ms( nowInTicks- pastInTicks ); + 800c932: 4b06 ldr r3, [pc, #24] ; (800c94c ) + 800c934: 6a9b ldr r3, [r3, #40] ; 0x28 + 800c936: 68f9 ldr r1, [r7, #12] + 800c938: 68ba ldr r2, [r7, #8] + 800c93a: 1a8a subs r2, r1, r2 + 800c93c: 4610 mov r0, r2 + 800c93e: 4798 blx r3 + 800c940: 4603 mov r3, r0 +} + 800c942: 4618 mov r0, r3 + 800c944: 3710 adds r7, #16 + 800c946: 46bd mov sp, r7 + 800c948: bd80 pop {r7, pc} + 800c94a: bf00 nop + 800c94c: 0800e38c .word 0x0800e38c + +0800c950 : + * + * @param TimerObject Structure containing the timer object parameters + * @retval 1 (the object is already in the list) or 0 + */ +bool TimerExists( UTIL_TIMER_Object_t *TimerObject ) +{ + 800c950: b480 push {r7} + 800c952: b085 sub sp, #20 + 800c954: af00 add r7, sp, #0 + 800c956: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800c958: 4b0a ldr r3, [pc, #40] ; (800c984 ) + 800c95a: 681b ldr r3, [r3, #0] + 800c95c: 60fb str r3, [r7, #12] + + while( cur != NULL ) + 800c95e: e008 b.n 800c972 + { + if( cur == TimerObject ) + 800c960: 68fa ldr r2, [r7, #12] + 800c962: 687b ldr r3, [r7, #4] + 800c964: 429a cmp r2, r3 + 800c966: d101 bne.n 800c96c + { + return true; + 800c968: 2301 movs r3, #1 + 800c96a: e006 b.n 800c97a + } + cur = cur->Next; + 800c96c: 68fb ldr r3, [r7, #12] + 800c96e: 695b ldr r3, [r3, #20] + 800c970: 60fb str r3, [r7, #12] + while( cur != NULL ) + 800c972: 68fb ldr r3, [r7, #12] + 800c974: 2b00 cmp r3, #0 + 800c976: d1f3 bne.n 800c960 + } + return false; + 800c978: 2300 movs r3, #0 +} + 800c97a: 4618 mov r0, r3 + 800c97c: 3714 adds r7, #20 + 800c97e: 46bd mov sp, r7 + 800c980: bc80 pop {r7} + 800c982: 4770 bx lr + 800c984: 200005e0 .word 0x200005e0 + +0800c988 : + * @brief Sets a timeout with the duration "timestamp" + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerSetTimeout( UTIL_TIMER_Object_t *TimerObject ) +{ + 800c988: b590 push {r4, r7, lr} + 800c98a: b085 sub sp, #20 + 800c98c: af00 add r7, sp, #0 + 800c98e: 6078 str r0, [r7, #4] + uint32_t minTicks= UTIL_TimerDriver.GetMinimumTimeout( ); + 800c990: 4b11 ldr r3, [pc, #68] ; (800c9d8 ) + 800c992: 6a1b ldr r3, [r3, #32] + 800c994: 4798 blx r3 + 800c996: 60f8 str r0, [r7, #12] + TimerObject->IsPending = 1; + 800c998: 687b ldr r3, [r7, #4] + 800c99a: 2201 movs r2, #1 + 800c99c: 721a strb r2, [r3, #8] + + /* In case deadline too soon */ + if(TimerObject->Timestamp < (UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks) ) + 800c99e: 687b ldr r3, [r7, #4] + 800c9a0: 681c ldr r4, [r3, #0] + 800c9a2: 4b0d ldr r3, [pc, #52] ; (800c9d8 ) + 800c9a4: 699b ldr r3, [r3, #24] + 800c9a6: 4798 blx r3 + 800c9a8: 4602 mov r2, r0 + 800c9aa: 68fb ldr r3, [r7, #12] + 800c9ac: 4413 add r3, r2 + 800c9ae: 429c cmp r4, r3 + 800c9b0: d207 bcs.n 800c9c2 + { + TimerObject->Timestamp = UTIL_TimerDriver.GetTimerElapsedTime( ) + minTicks; + 800c9b2: 4b09 ldr r3, [pc, #36] ; (800c9d8 ) + 800c9b4: 699b ldr r3, [r3, #24] + 800c9b6: 4798 blx r3 + 800c9b8: 4602 mov r2, r0 + 800c9ba: 68fb ldr r3, [r7, #12] + 800c9bc: 441a add r2, r3 + 800c9be: 687b ldr r3, [r7, #4] + 800c9c0: 601a str r2, [r3, #0] + } + UTIL_TimerDriver.StartTimerEvt( TimerObject->Timestamp ); + 800c9c2: 4b05 ldr r3, [pc, #20] ; (800c9d8 ) + 800c9c4: 689b ldr r3, [r3, #8] + 800c9c6: 687a ldr r2, [r7, #4] + 800c9c8: 6812 ldr r2, [r2, #0] + 800c9ca: 4610 mov r0, r2 + 800c9cc: 4798 blx r3 +} + 800c9ce: bf00 nop + 800c9d0: 3714 adds r7, #20 + 800c9d2: 46bd mov sp, r7 + 800c9d4: bd90 pop {r4, r7, pc} + 800c9d6: bf00 nop + 800c9d8: 0800e38c .word 0x0800e38c + +0800c9dc : + * next timer to expire. + * + * @param TimerObject Structure containing the timer object parameters + */ +void TimerInsertTimer( UTIL_TIMER_Object_t *TimerObject) +{ + 800c9dc: b480 push {r7} + 800c9de: b085 sub sp, #20 + 800c9e0: af00 add r7, sp, #0 + 800c9e2: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800c9e4: 4b14 ldr r3, [pc, #80] ; (800ca38 ) + 800c9e6: 681b ldr r3, [r3, #0] + 800c9e8: 60fb str r3, [r7, #12] + UTIL_TIMER_Object_t* next = TimerListHead->Next; + 800c9ea: 4b13 ldr r3, [pc, #76] ; (800ca38 ) + 800c9ec: 681b ldr r3, [r3, #0] + 800c9ee: 695b ldr r3, [r3, #20] + 800c9f0: 60bb str r3, [r7, #8] + + while (cur->Next != NULL ) + 800c9f2: e012 b.n 800ca1a + { + if( TimerObject->Timestamp > next->Timestamp ) + 800c9f4: 687b ldr r3, [r7, #4] + 800c9f6: 681a ldr r2, [r3, #0] + 800c9f8: 68bb ldr r3, [r7, #8] + 800c9fa: 681b ldr r3, [r3, #0] + 800c9fc: 429a cmp r2, r3 + 800c9fe: d905 bls.n 800ca0c + { + cur = next; + 800ca00: 68bb ldr r3, [r7, #8] + 800ca02: 60fb str r3, [r7, #12] + next = next->Next; + 800ca04: 68bb ldr r3, [r7, #8] + 800ca06: 695b ldr r3, [r3, #20] + 800ca08: 60bb str r3, [r7, #8] + 800ca0a: e006 b.n 800ca1a + } + else + { + cur->Next = TimerObject; + 800ca0c: 68fb ldr r3, [r7, #12] + 800ca0e: 687a ldr r2, [r7, #4] + 800ca10: 615a str r2, [r3, #20] + TimerObject->Next = next; + 800ca12: 687b ldr r3, [r7, #4] + 800ca14: 68ba ldr r2, [r7, #8] + 800ca16: 615a str r2, [r3, #20] + return; + 800ca18: e009 b.n 800ca2e + while (cur->Next != NULL ) + 800ca1a: 68fb ldr r3, [r7, #12] + 800ca1c: 695b ldr r3, [r3, #20] + 800ca1e: 2b00 cmp r3, #0 + 800ca20: d1e8 bne.n 800c9f4 + + } + } + cur->Next = TimerObject; + 800ca22: 68fb ldr r3, [r7, #12] + 800ca24: 687a ldr r2, [r7, #4] + 800ca26: 615a str r2, [r3, #20] + TimerObject->Next = NULL; + 800ca28: 687b ldr r3, [r7, #4] + 800ca2a: 2200 movs r2, #0 + 800ca2c: 615a str r2, [r3, #20] +} + 800ca2e: 3714 adds r7, #20 + 800ca30: 46bd mov sp, r7 + 800ca32: bc80 pop {r7} + 800ca34: 4770 bx lr + 800ca36: bf00 nop + 800ca38: 200005e0 .word 0x200005e0 + +0800ca3c : + * + * @remark The list is automatically sorted. The list head always contains the + * next timer to expire. + */ +void TimerInsertNewHeadTimer( UTIL_TIMER_Object_t *TimerObject ) +{ + 800ca3c: b580 push {r7, lr} + 800ca3e: b084 sub sp, #16 + 800ca40: af00 add r7, sp, #0 + 800ca42: 6078 str r0, [r7, #4] + UTIL_TIMER_Object_t* cur = TimerListHead; + 800ca44: 4b0b ldr r3, [pc, #44] ; (800ca74 ) + 800ca46: 681b ldr r3, [r3, #0] + 800ca48: 60fb str r3, [r7, #12] + + if( cur != NULL ) + 800ca4a: 68fb ldr r3, [r7, #12] + 800ca4c: 2b00 cmp r3, #0 + 800ca4e: d002 beq.n 800ca56 + { + cur->IsPending = 0; + 800ca50: 68fb ldr r3, [r7, #12] + 800ca52: 2200 movs r2, #0 + 800ca54: 721a strb r2, [r3, #8] + } + + TimerObject->Next = cur; + 800ca56: 687b ldr r3, [r7, #4] + 800ca58: 68fa ldr r2, [r7, #12] + 800ca5a: 615a str r2, [r3, #20] + TimerListHead = TimerObject; + 800ca5c: 4a05 ldr r2, [pc, #20] ; (800ca74 ) + 800ca5e: 687b ldr r3, [r7, #4] + 800ca60: 6013 str r3, [r2, #0] + TimerSetTimeout( TimerListHead ); + 800ca62: 4b04 ldr r3, [pc, #16] ; (800ca74 ) + 800ca64: 681b ldr r3, [r3, #0] + 800ca66: 4618 mov r0, r3 + 800ca68: f7ff ff8e bl 800c988 +} + 800ca6c: bf00 nop + 800ca6e: 3710 adds r7, #16 + 800ca70: 46bd mov sp, r7 + 800ca72: bd80 pop {r7, pc} + 800ca74: 200005e0 .word 0x200005e0 + +0800ca78 : + +/** @addtogroup ADV_TRACE_exported_function + * @{ + */ +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_Init(void) +{ + 800ca78: b580 push {r7, lr} + 800ca7a: af00 add r7, sp, #0 + /* initialize the Ptr for Read/Write */ + (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Ctx, 0x0, sizeof(ADV_TRACE_Context)); + 800ca7c: 2218 movs r2, #24 + 800ca7e: 2100 movs r1, #0 + 800ca80: 4807 ldr r0, [pc, #28] ; (800caa0 ) + 800ca82: f7ff f9b4 bl 800bdee + (void)UTIL_ADV_TRACE_MEMSET8(&ADV_TRACE_Buffer, 0x0, sizeof(ADV_TRACE_Buffer)); + 800ca86: f44f 7200 mov.w r2, #512 ; 0x200 + 800ca8a: 2100 movs r1, #0 + 800ca8c: 4805 ldr r0, [pc, #20] ; (800caa4 ) + 800ca8e: f7ff f9ae bl 800bdee +#endif + /* Allocate Lock resource */ + UTIL_ADV_TRACE_INIT_CRITICAL_SECTION(); + + /* Initialize the Low Level interface */ + return UTIL_TraceDriver.Init(TRACE_TxCpltCallback); + 800ca92: 4b05 ldr r3, [pc, #20] ; (800caa8 ) + 800ca94: 681b ldr r3, [r3, #0] + 800ca96: 4805 ldr r0, [pc, #20] ; (800caac ) + 800ca98: 4798 blx r3 + 800ca9a: 4603 mov r3, r0 +} + 800ca9c: 4618 mov r0, r3 + 800ca9e: bd80 pop {r7, pc} + 800caa0: 200005e4 .word 0x200005e4 + 800caa4: 200005fc .word 0x200005fc + 800caa8: 0800e3cc .word 0x0800e3cc + 800caac: 0800ccf5 .word 0x0800ccf5 + +0800cab0 : + return UTIL_TraceDriver.StartRx(UserCallback); +} + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +UTIL_ADV_TRACE_Status_t UTIL_ADV_TRACE_COND_FSend(uint32_t VerboseLevel, uint32_t Region, uint32_t TimeStampState, const char *strFormat, ...) +{ + 800cab0: b408 push {r3} + 800cab2: b580 push {r7, lr} + 800cab4: b08d sub sp, #52 ; 0x34 + 800cab6: af00 add r7, sp, #0 + 800cab8: 60f8 str r0, [r7, #12] + 800caba: 60b9 str r1, [r7, #8] + 800cabc: 607a str r2, [r7, #4] + va_list vaArgs; +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + uint8_t buf[UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; + uint16_t timestamp_size = 0u; + 800cabe: 2300 movs r3, #0 + 800cac0: 82fb strh r3, [r7, #22] + uint16_t writepos; + uint16_t idx; +#else + uint8_t buf[UTIL_ADV_TRACE_TMP_BUF_SIZE+UTIL_ADV_TRACE_TMP_MAX_TIMESTMAP_SIZE]; +#endif + uint16_t buff_size = 0u; + 800cac2: 2300 movs r3, #0 + 800cac4: 85bb strh r3, [r7, #44] ; 0x2c + + /* check verbose level */ + if(!(ADV_TRACE_Ctx.CurrentVerboseLevel >= VerboseLevel)) + 800cac6: 4b37 ldr r3, [pc, #220] ; (800cba4 ) + 800cac8: 7a1b ldrb r3, [r3, #8] + 800caca: 461a mov r2, r3 + 800cacc: 68fb ldr r3, [r7, #12] + 800cace: 4293 cmp r3, r2 + 800cad0: d902 bls.n 800cad8 + { + return UTIL_ADV_TRACE_GIVEUP; + 800cad2: f06f 0304 mvn.w r3, #4 + 800cad6: e05e b.n 800cb96 + } + + if((Region & ADV_TRACE_Ctx.RegionMask) != Region) + 800cad8: 4b32 ldr r3, [pc, #200] ; (800cba4 ) + 800cada: 68da ldr r2, [r3, #12] + 800cadc: 68bb ldr r3, [r7, #8] + 800cade: 4013 ands r3, r2 + 800cae0: 68ba ldr r2, [r7, #8] + 800cae2: 429a cmp r2, r3 + 800cae4: d002 beq.n 800caec + { + return UTIL_ADV_TRACE_REGIONMASKED; + 800cae6: f06f 0305 mvn.w r3, #5 + 800caea: e054 b.n 800cb96 + } + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if((ADV_TRACE_Ctx.timestamp_func != NULL) && (TimeStampState != 0u)) + 800caec: 4b2d ldr r3, [pc, #180] ; (800cba4 ) + 800caee: 685b ldr r3, [r3, #4] + 800caf0: 2b00 cmp r3, #0 + 800caf2: d00a beq.n 800cb0a + 800caf4: 687b ldr r3, [r7, #4] + 800caf6: 2b00 cmp r3, #0 + 800caf8: d007 beq.n 800cb0a + { + ADV_TRACE_Ctx.timestamp_func(buf,×tamp_size); + 800cafa: 4b2a ldr r3, [pc, #168] ; (800cba4 ) + 800cafc: 685b ldr r3, [r3, #4] + 800cafe: f107 0116 add.w r1, r7, #22 + 800cb02: f107 0218 add.w r2, r7, #24 + 800cb06: 4610 mov r0, r2 + 800cb08: 4798 blx r3 + } + + va_start( vaArgs, strFormat); + 800cb0a: f107 0340 add.w r3, r7, #64 ; 0x40 + 800cb0e: 62bb str r3, [r7, #40] ; 0x28 + buff_size =(uint16_t)UTIL_ADV_TRACE_VSNPRINTF((char *)sztmp,UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + 800cb10: 6abb ldr r3, [r7, #40] ; 0x28 + 800cb12: 6bfa ldr r2, [r7, #60] ; 0x3c + 800cb14: f44f 7180 mov.w r1, #256 ; 0x100 + 800cb18: 4823 ldr r0, [pc, #140] ; (800cba8 ) + 800cb1a: f7ff fb09 bl 800c130 + 800cb1e: 4603 mov r3, r0 + 800cb20: 85bb strh r3, [r7, #44] ; 0x2c + + TRACE_Lock(); + 800cb22: f000 f9f1 bl 800cf08 + + /* if allocation is ok, write data into the buffer */ + if (TRACE_AllocateBufer((buff_size+timestamp_size),&writepos) != -1) + 800cb26: 8afa ldrh r2, [r7, #22] + 800cb28: 8dbb ldrh r3, [r7, #44] ; 0x2c + 800cb2a: 4413 add r3, r2 + 800cb2c: b29b uxth r3, r3 + 800cb2e: f107 0214 add.w r2, r7, #20 + 800cb32: 4611 mov r1, r2 + 800cb34: 4618 mov r0, r3 + 800cb36: f000 f969 bl 800ce0c + 800cb3a: 4603 mov r3, r0 + 800cb3c: f1b3 3fff cmp.w r3, #4294967295 + 800cb40: d025 beq.n 800cb8e + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + /* copy the timestamp */ + for (idx = 0u; idx < timestamp_size; idx++) + 800cb42: 2300 movs r3, #0 + 800cb44: 85fb strh r3, [r7, #46] ; 0x2e + 800cb46: e00e b.n 800cb66 + { + ADV_TRACE_Buffer[writepos] = buf[idx]; + 800cb48: 8dfb ldrh r3, [r7, #46] ; 0x2e + 800cb4a: 8aba ldrh r2, [r7, #20] + 800cb4c: 3330 adds r3, #48 ; 0x30 + 800cb4e: 443b add r3, r7 + 800cb50: f813 1c18 ldrb.w r1, [r3, #-24] + 800cb54: 4b15 ldr r3, [pc, #84] ; (800cbac ) + 800cb56: 5499 strb r1, [r3, r2] + writepos = writepos + 1u; + 800cb58: 8abb ldrh r3, [r7, #20] + 800cb5a: 3301 adds r3, #1 + 800cb5c: b29b uxth r3, r3 + 800cb5e: 82bb strh r3, [r7, #20] + for (idx = 0u; idx < timestamp_size; idx++) + 800cb60: 8dfb ldrh r3, [r7, #46] ; 0x2e + 800cb62: 3301 adds r3, #1 + 800cb64: 85fb strh r3, [r7, #46] ; 0x2e + 800cb66: 8afb ldrh r3, [r7, #22] + 800cb68: 8dfa ldrh r2, [r7, #46] ; 0x2e + 800cb6a: 429a cmp r2, r3 + 800cb6c: d3ec bcc.n 800cb48 + } + + /* copy the data */ + (void)UTIL_ADV_TRACE_VSNPRINTF((char *)(&ADV_TRACE_Buffer[writepos]), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + 800cb6e: 8abb ldrh r3, [r7, #20] + 800cb70: 461a mov r2, r3 + 800cb72: 4b0e ldr r3, [pc, #56] ; (800cbac ) + 800cb74: 18d0 adds r0, r2, r3 + 800cb76: 6abb ldr r3, [r7, #40] ; 0x28 + 800cb78: 6bfa ldr r2, [r7, #60] ; 0x3c + 800cb7a: f44f 7180 mov.w r1, #256 ; 0x100 + 800cb7e: f7ff fad7 bl 800c130 + va_end(vaArgs); + + TRACE_UnLock(); + 800cb82: f000 f9df bl 800cf44 + + return TRACE_Send(); + 800cb86: f000 f831 bl 800cbec + 800cb8a: 4603 mov r3, r0 + 800cb8c: e003 b.n 800cb96 + } + + va_end(vaArgs); + TRACE_UnLock(); + 800cb8e: f000 f9d9 bl 800cf44 + ADV_TRACE_Ctx.OverRunStatus = TRACE_OVERRUN_INDICATION; + } + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +#endif + + return UTIL_ADV_TRACE_MEM_FULL; + 800cb92: f06f 0302 mvn.w r3, #2 + buff_size += (uint16_t) UTIL_ADV_TRACE_VSNPRINTF((char* )(buf + buff_size), UTIL_ADV_TRACE_TMP_BUF_SIZE, strFormat, vaArgs); + va_end(vaArgs); + + return UTIL_ADV_TRACE_Send(buf, buff_size); +#endif +} + 800cb96: 4618 mov r0, r3 + 800cb98: 3734 adds r7, #52 ; 0x34 + 800cb9a: 46bd mov sp, r7 + 800cb9c: e8bd 4080 ldmia.w sp!, {r7, lr} + 800cba0: b001 add sp, #4 + 800cba2: 4770 bx lr + 800cba4: 200005e4 .word 0x200005e4 + 800cba8: 200007fc .word 0x200007fc + 800cbac: 200005fc .word 0x200005fc + +0800cbb0 : +} +#endif + +#if defined(UTIL_ADV_TRACE_CONDITIONNAL) +void UTIL_ADV_TRACE_RegisterTimeStampFunction(cb_timestamp *cb) +{ + 800cbb0: b480 push {r7} + 800cbb2: b083 sub sp, #12 + 800cbb4: af00 add r7, sp, #0 + 800cbb6: 6078 str r0, [r7, #4] + ADV_TRACE_Ctx.timestamp_func = *cb; + 800cbb8: 4a03 ldr r2, [pc, #12] ; (800cbc8 ) + 800cbba: 687b ldr r3, [r7, #4] + 800cbbc: 6053 str r3, [r2, #4] +} + 800cbbe: bf00 nop + 800cbc0: 370c adds r7, #12 + 800cbc2: 46bd mov sp, r7 + 800cbc4: bc80 pop {r7} + 800cbc6: 4770 bx lr + 800cbc8: 200005e4 .word 0x200005e4 + +0800cbcc : + +void UTIL_ADV_TRACE_SetVerboseLevel(uint8_t Level) +{ + 800cbcc: b480 push {r7} + 800cbce: b083 sub sp, #12 + 800cbd0: af00 add r7, sp, #0 + 800cbd2: 4603 mov r3, r0 + 800cbd4: 71fb strb r3, [r7, #7] + ADV_TRACE_Ctx.CurrentVerboseLevel = Level; + 800cbd6: 4a04 ldr r2, [pc, #16] ; (800cbe8 ) + 800cbd8: 79fb ldrb r3, [r7, #7] + 800cbda: 7213 strb r3, [r2, #8] +} + 800cbdc: bf00 nop + 800cbde: 370c adds r7, #12 + 800cbe0: 46bd mov sp, r7 + 800cbe2: bc80 pop {r7} + 800cbe4: 4770 bx lr + 800cbe6: bf00 nop + 800cbe8: 200005e4 .word 0x200005e4 + +0800cbec : +/** + * @brief send the data of the trace to low layer + * @retval Status based on @ref UTIL_ADV_TRACE_Status_t + */ +static UTIL_ADV_TRACE_Status_t TRACE_Send(void) +{ + 800cbec: b580 push {r7, lr} + 800cbee: b088 sub sp, #32 + 800cbf0: af00 add r7, sp, #0 + UTIL_ADV_TRACE_Status_t ret = UTIL_ADV_TRACE_OK; + 800cbf2: 2300 movs r3, #0 + 800cbf4: 77fb strb r3, [r7, #31] + uint8_t *ptr = NULL; + 800cbf6: 2300 movs r3, #0 + 800cbf8: 61bb str r3, [r7, #24] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800cbfa: f3ef 8310 mrs r3, PRIMASK + 800cbfe: 613b str r3, [r7, #16] + return(result); + 800cc00: 693b ldr r3, [r7, #16] + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800cc02: 617b str r3, [r7, #20] + __ASM volatile ("cpsid i" : : : "memory"); + 800cc04: b672 cpsid i +} + 800cc06: bf00 nop + + if(TRACE_IsLocked() == 0u) + 800cc08: f000 f9ba bl 800cf80 + 800cc0c: 4603 mov r3, r0 + 800cc0e: 2b00 cmp r3, #0 + 800cc10: d15d bne.n 800ccce + { + TRACE_Lock(); + 800cc12: f000 f979 bl 800cf08 + + if(ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) + 800cc16: 4b34 ldr r3, [pc, #208] ; (800cce8 ) + 800cc18: 8a1a ldrh r2, [r3, #16] + 800cc1a: 4b33 ldr r3, [pc, #204] ; (800cce8 ) + 800cc1c: 8a5b ldrh r3, [r3, #18] + 800cc1e: 429a cmp r2, r3 + 800cc20: d04d beq.n 800ccbe + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + 800cc22: 4b31 ldr r3, [pc, #196] ; (800cce8 ) + 800cc24: 789b ldrb r3, [r3, #2] + 800cc26: 2b01 cmp r3, #1 + 800cc28: d117 bne.n 800cc5a + { + ADV_TRACE_Ctx.TraceSentSize = (uint16_t) (ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr); + 800cc2a: 4b2f ldr r3, [pc, #188] ; (800cce8 ) + 800cc2c: 881a ldrh r2, [r3, #0] + 800cc2e: 4b2e ldr r3, [pc, #184] ; (800cce8 ) + 800cc30: 8a1b ldrh r3, [r3, #16] + 800cc32: 1ad3 subs r3, r2, r3 + 800cc34: b29a uxth r2, r3 + 800cc36: 4b2c ldr r3, [pc, #176] ; (800cce8 ) + 800cc38: 829a strh r2, [r3, #20] + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + 800cc3a: 4b2b ldr r3, [pc, #172] ; (800cce8 ) + 800cc3c: 2202 movs r2, #2 + 800cc3e: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = 0; + 800cc40: 4b29 ldr r3, [pc, #164] ; (800cce8 ) + 800cc42: 2200 movs r2, #0 + 800cc44: 801a strh r2, [r3, #0] + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + 800cc46: 4b28 ldr r3, [pc, #160] ; (800cce8 ) + 800cc48: 8a9b ldrh r3, [r3, #20] + 800cc4a: 2b00 cmp r3, #0 + 800cc4c: d105 bne.n 800cc5a + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800cc4e: 4b26 ldr r3, [pc, #152] ; (800cce8 ) + 800cc50: 2200 movs r2, #0 + 800cc52: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800cc54: 4b24 ldr r3, [pc, #144] ; (800cce8 ) + 800cc56: 2200 movs r2, #0 + 800cc58: 821a strh r2, [r3, #16] + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + 800cc5a: 4b23 ldr r3, [pc, #140] ; (800cce8 ) + 800cc5c: 789b ldrb r3, [r3, #2] + 800cc5e: 2b00 cmp r3, #0 + 800cc60: d115 bne.n 800cc8e + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800cc62: 4b21 ldr r3, [pc, #132] ; (800cce8 ) + 800cc64: 8a5a ldrh r2, [r3, #18] + 800cc66: 4b20 ldr r3, [pc, #128] ; (800cce8 ) + 800cc68: 8a1b ldrh r3, [r3, #16] + 800cc6a: 429a cmp r2, r3 + 800cc6c: d908 bls.n 800cc80 + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + 800cc6e: 4b1e ldr r3, [pc, #120] ; (800cce8 ) + 800cc70: 8a5a ldrh r2, [r3, #18] + 800cc72: 4b1d ldr r3, [pc, #116] ; (800cce8 ) + 800cc74: 8a1b ldrh r3, [r3, #16] + 800cc76: 1ad3 subs r3, r2, r3 + 800cc78: b29a uxth r2, r3 + 800cc7a: 4b1b ldr r3, [pc, #108] ; (800cce8 ) + 800cc7c: 829a strh r2, [r3, #20] + 800cc7e: e006 b.n 800cc8e + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + 800cc80: 4b19 ldr r3, [pc, #100] ; (800cce8 ) + 800cc82: 8a1b ldrh r3, [r3, #16] + 800cc84: f5c3 7300 rsb r3, r3, #512 ; 0x200 + 800cc88: b29a uxth r2, r3 + 800cc8a: 4b17 ldr r3, [pc, #92] ; (800cce8 ) + 800cc8c: 829a strh r2, [r3, #20] + + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + 800cc8e: 4b16 ldr r3, [pc, #88] ; (800cce8 ) + 800cc90: 8a1b ldrh r3, [r3, #16] + 800cc92: 461a mov r2, r3 + 800cc94: 4b15 ldr r3, [pc, #84] ; (800ccec ) + 800cc96: 4413 add r3, r2 + 800cc98: 61bb str r3, [r7, #24] + 800cc9a: 697b ldr r3, [r7, #20] + 800cc9c: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cc9e: 68fb ldr r3, [r7, #12] + 800cca0: f383 8810 msr PRIMASK, r3 +} + 800cca4: bf00 nop + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PreSendHook(); + 800cca6: f7f4 f813 bl 8000cd0 + + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + ret = UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + 800ccaa: 4b11 ldr r3, [pc, #68] ; (800ccf0 ) + 800ccac: 68db ldr r3, [r3, #12] + 800ccae: 4a0e ldr r2, [pc, #56] ; (800cce8 ) + 800ccb0: 8a92 ldrh r2, [r2, #20] + 800ccb2: 4611 mov r1, r2 + 800ccb4: 69b8 ldr r0, [r7, #24] + 800ccb6: 4798 blx r3 + 800ccb8: 4603 mov r3, r0 + 800ccba: 77fb strb r3, [r7, #31] + 800ccbc: e00d b.n 800ccda + } + else + { + TRACE_UnLock(); + 800ccbe: f000 f941 bl 800cf44 + 800ccc2: 697b ldr r3, [r7, #20] + 800ccc4: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800ccc6: 68bb ldr r3, [r7, #8] + 800ccc8: f383 8810 msr PRIMASK, r3 +} + 800cccc: e005 b.n 800ccda + 800ccce: 697b ldr r3, [r7, #20] + 800ccd0: 607b str r3, [r7, #4] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800ccd2: 687b ldr r3, [r7, #4] + 800ccd4: f383 8810 msr PRIMASK, r3 +} + 800ccd8: bf00 nop + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + } + + return ret; + 800ccda: f997 301f ldrsb.w r3, [r7, #31] +} + 800ccde: 4618 mov r0, r3 + 800cce0: 3720 adds r7, #32 + 800cce2: 46bd mov sp, r7 + 800cce4: bd80 pop {r7, pc} + 800cce6: bf00 nop + 800cce8: 200005e4 .word 0x200005e4 + 800ccec: 200005fc .word 0x200005fc + 800ccf0: 0800e3cc .word 0x0800e3cc + +0800ccf4 : + * @brief Tx callback called by the low layer level to inform a transfer complete + * @param Ptr pointer not used only for HAL compatibility + * @retval none + */ +static void TRACE_TxCpltCallback(void *Ptr) +{ + 800ccf4: b580 push {r7, lr} + 800ccf6: b088 sub sp, #32 + 800ccf8: af00 add r7, sp, #0 + 800ccfa: 6078 str r0, [r7, #4] + uint8_t *ptr = NULL; + 800ccfc: 2300 movs r3, #0 + 800ccfe: 61fb str r3, [r7, #28] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800cd00: f3ef 8310 mrs r3, PRIMASK + 800cd04: 617b str r3, [r7, #20] + return(result); + 800cd06: 697b ldr r3, [r7, #20] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800cd08: 61bb str r3, [r7, #24] + __ASM volatile ("cpsid i" : : : "memory"); + 800cd0a: b672 cpsid i +} + 800cd0c: bf00 nop + ADV_TRACE_Ctx.TraceSentSize = 0u; + } +#endif + +#if defined(UTIL_ADV_TRACE_UNCHUNK_MODE) + if(TRACE_UNCHUNK_TRANSFER == ADV_TRACE_Ctx.unchunk_status) + 800cd0e: 4b3c ldr r3, [pc, #240] ; (800ce00 ) + 800cd10: 789b ldrb r3, [r3, #2] + 800cd12: 2b02 cmp r3, #2 + 800cd14: d106 bne.n 800cd24 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800cd16: 4b3a ldr r3, [pc, #232] ; (800ce00 ) + 800cd18: 2200 movs r2, #0 + 800cd1a: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800cd1c: 4b38 ldr r3, [pc, #224] ; (800ce00 ) + 800cd1e: 2200 movs r2, #0 + 800cd20: 821a strh r2, [r3, #16] + 800cd22: e00a b.n 800cd3a + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk complete\n"); + } + else + { + ADV_TRACE_Ctx.TraceRdPtr = (ADV_TRACE_Ctx.TraceRdPtr + ADV_TRACE_Ctx.TraceSentSize) % UTIL_ADV_TRACE_FIFO_SIZE; + 800cd24: 4b36 ldr r3, [pc, #216] ; (800ce00 ) + 800cd26: 8a1a ldrh r2, [r3, #16] + 800cd28: 4b35 ldr r3, [pc, #212] ; (800ce00 ) + 800cd2a: 8a9b ldrh r3, [r3, #20] + 800cd2c: 4413 add r3, r2 + 800cd2e: b29b uxth r3, r3 + 800cd30: f3c3 0308 ubfx r3, r3, #0, #9 + 800cd34: b29a uxth r2, r3 + 800cd36: 4b32 ldr r3, [pc, #200] ; (800ce00 ) + 800cd38: 821a strh r2, [r3, #16] + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + return; + } +#endif + + if((ADV_TRACE_Ctx.TraceRdPtr != ADV_TRACE_Ctx.TraceWrPtr) && (1u == ADV_TRACE_Ctx.TraceLock)) + 800cd3a: 4b31 ldr r3, [pc, #196] ; (800ce00 ) + 800cd3c: 8a1a ldrh r2, [r3, #16] + 800cd3e: 4b30 ldr r3, [pc, #192] ; (800ce00 ) + 800cd40: 8a5b ldrh r3, [r3, #18] + 800cd42: 429a cmp r2, r3 + 800cd44: d04d beq.n 800cde2 + 800cd46: 4b2e ldr r3, [pc, #184] ; (800ce00 ) + 800cd48: 8adb ldrh r3, [r3, #22] + 800cd4a: 2b01 cmp r3, #1 + 800cd4c: d149 bne.n 800cde2 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if(TRACE_UNCHUNK_DETECTED == ADV_TRACE_Ctx.unchunk_status) + 800cd4e: 4b2c ldr r3, [pc, #176] ; (800ce00 ) + 800cd50: 789b ldrb r3, [r3, #2] + 800cd52: 2b01 cmp r3, #1 + 800cd54: d117 bne.n 800cd86 + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.unchunk_enabled - ADV_TRACE_Ctx.TraceRdPtr; + 800cd56: 4b2a ldr r3, [pc, #168] ; (800ce00 ) + 800cd58: 881a ldrh r2, [r3, #0] + 800cd5a: 4b29 ldr r3, [pc, #164] ; (800ce00 ) + 800cd5c: 8a1b ldrh r3, [r3, #16] + 800cd5e: 1ad3 subs r3, r2, r3 + 800cd60: b29a uxth r2, r3 + 800cd62: 4b27 ldr r3, [pc, #156] ; (800ce00 ) + 800cd64: 829a strh r2, [r3, #20] + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_TRANSFER; + 800cd66: 4b26 ldr r3, [pc, #152] ; (800ce00 ) + 800cd68: 2202 movs r2, #2 + 800cd6a: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = 0; + 800cd6c: 4b24 ldr r3, [pc, #144] ; (800ce00 ) + 800cd6e: 2200 movs r2, #0 + 800cd70: 801a strh r2, [r3, #0] + + UTIL_ADV_TRACE_DEBUG("\nTRACE_TxCpltCallback::unchunk start(%d,%d)\n", ADV_TRACE_Ctx.unchunk_enabled, ADV_TRACE_Ctx.TraceRdPtr); + + if(0u == ADV_TRACE_Ctx.TraceSentSize) + 800cd72: 4b23 ldr r3, [pc, #140] ; (800ce00 ) + 800cd74: 8a9b ldrh r3, [r3, #20] + 800cd76: 2b00 cmp r3, #0 + 800cd78: d105 bne.n 800cd86 + { + /* this case occurs when an ongoing write aligned the Rd position with chunk position */ + /* in that case the unchunk is forgot */ + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_NONE; + 800cd7a: 4b21 ldr r3, [pc, #132] ; (800ce00 ) + 800cd7c: 2200 movs r2, #0 + 800cd7e: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.TraceRdPtr = 0; + 800cd80: 4b1f ldr r3, [pc, #124] ; (800ce00 ) + 800cd82: 2200 movs r2, #0 + 800cd84: 821a strh r2, [r3, #16] + } + } + + if(TRACE_UNCHUNK_NONE == ADV_TRACE_Ctx.unchunk_status) + 800cd86: 4b1e ldr r3, [pc, #120] ; (800ce00 ) + 800cd88: 789b ldrb r3, [r3, #2] + 800cd8a: 2b00 cmp r3, #0 + 800cd8c: d115 bne.n 800cdba + { +#endif + if(ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800cd8e: 4b1c ldr r3, [pc, #112] ; (800ce00 ) + 800cd90: 8a5a ldrh r2, [r3, #18] + 800cd92: 4b1b ldr r3, [pc, #108] ; (800ce00 ) + 800cd94: 8a1b ldrh r3, [r3, #16] + 800cd96: 429a cmp r2, r3 + 800cd98: d908 bls.n 800cdac + { + ADV_TRACE_Ctx.TraceSentSize = ADV_TRACE_Ctx.TraceWrPtr - ADV_TRACE_Ctx.TraceRdPtr; + 800cd9a: 4b19 ldr r3, [pc, #100] ; (800ce00 ) + 800cd9c: 8a5a ldrh r2, [r3, #18] + 800cd9e: 4b18 ldr r3, [pc, #96] ; (800ce00 ) + 800cda0: 8a1b ldrh r3, [r3, #16] + 800cda2: 1ad3 subs r3, r2, r3 + 800cda4: b29a uxth r2, r3 + 800cda6: 4b16 ldr r3, [pc, #88] ; (800ce00 ) + 800cda8: 829a strh r2, [r3, #20] + 800cdaa: e006 b.n 800cdba + } + else /* TraceRdPtr > TraceWrPtr */ + { + ADV_TRACE_Ctx.TraceSentSize = UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceRdPtr; + 800cdac: 4b14 ldr r3, [pc, #80] ; (800ce00 ) + 800cdae: 8a1b ldrh r3, [r3, #16] + 800cdb0: f5c3 7300 rsb r3, r3, #512 ; 0x200 + 800cdb4: b29a uxth r2, r3 + 800cdb6: 4b12 ldr r3, [pc, #72] ; (800ce00 ) + 800cdb8: 829a strh r2, [r3, #20] + } +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + } +#endif + ptr = &ADV_TRACE_Buffer[ADV_TRACE_Ctx.TraceRdPtr]; + 800cdba: 4b11 ldr r3, [pc, #68] ; (800ce00 ) + 800cdbc: 8a1b ldrh r3, [r3, #16] + 800cdbe: 461a mov r2, r3 + 800cdc0: 4b10 ldr r3, [pc, #64] ; (800ce04 ) + 800cdc2: 4413 add r3, r2 + 800cdc4: 61fb str r3, [r7, #28] + 800cdc6: 69bb ldr r3, [r7, #24] + 800cdc8: 613b str r3, [r7, #16] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cdca: 693b ldr r3, [r7, #16] + 800cdcc: f383 8810 msr PRIMASK, r3 +} + 800cdd0: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_DEBUG("\n--TRACE_Send(%d-%d)--\n", ADV_TRACE_Ctx.TraceRdPtr, ADV_TRACE_Ctx.TraceSentSize); + UTIL_TraceDriver.Send(ptr, ADV_TRACE_Ctx.TraceSentSize); + 800cdd2: 4b0d ldr r3, [pc, #52] ; (800ce08 ) + 800cdd4: 68db ldr r3, [r3, #12] + 800cdd6: 4a0a ldr r2, [pc, #40] ; (800ce00 ) + 800cdd8: 8a92 ldrh r2, [r2, #20] + 800cdda: 4611 mov r1, r2 + 800cddc: 69f8 ldr r0, [r7, #28] + 800cdde: 4798 blx r3 + 800cde0: e00a b.n 800cdf8 + 800cde2: 69bb ldr r3, [r7, #24] + 800cde4: 60fb str r3, [r7, #12] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cde6: 68fb ldr r3, [r7, #12] + 800cde8: f383 8810 msr PRIMASK, r3 +} + 800cdec: bf00 nop + } + else + { + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + UTIL_ADV_TRACE_PostSendHook(); + 800cdee: f7f3 ff77 bl 8000ce0 + TRACE_UnLock(); + 800cdf2: f000 f8a7 bl 800cf44 + } +} + 800cdf6: bf00 nop + 800cdf8: bf00 nop + 800cdfa: 3720 adds r7, #32 + 800cdfc: 46bd mov sp, r7 + 800cdfe: bd80 pop {r7, pc} + 800ce00: 200005e4 .word 0x200005e4 + 800ce04: 200005fc .word 0x200005fc + 800ce08: 0800e3cc .word 0x0800e3cc + +0800ce0c : + * @param Size to allocate within fifo + * @param Pos position within the fifo + * @retval write position inside the buffer is -1 no space available. + */ +static int16_t TRACE_AllocateBufer(uint16_t Size, uint16_t *Pos) +{ + 800ce0c: b480 push {r7} + 800ce0e: b087 sub sp, #28 + 800ce10: af00 add r7, sp, #0 + 800ce12: 4603 mov r3, r0 + 800ce14: 6039 str r1, [r7, #0] + 800ce16: 80fb strh r3, [r7, #6] + uint16_t freesize; + int16_t ret = -1; + 800ce18: f64f 73ff movw r3, #65535 ; 0xffff + 800ce1c: 82bb strh r3, [r7, #20] + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800ce1e: f3ef 8310 mrs r3, PRIMASK + 800ce22: 60fb str r3, [r7, #12] + return(result); + 800ce24: 68fb ldr r3, [r7, #12] + + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800ce26: 613b str r3, [r7, #16] + __ASM volatile ("cpsid i" : : : "memory"); + 800ce28: b672 cpsid i +} + 800ce2a: bf00 nop + + if(ADV_TRACE_Ctx.TraceWrPtr == ADV_TRACE_Ctx.TraceRdPtr) + 800ce2c: 4b35 ldr r3, [pc, #212] ; (800cf04 ) + 800ce2e: 8a5a ldrh r2, [r3, #18] + 800ce30: 4b34 ldr r3, [pc, #208] ; (800cf04 ) + 800ce32: 8a1b ldrh r3, [r3, #16] + 800ce34: 429a cmp r2, r3 + 800ce36: d11b bne.n 800ce70 + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + 800ce38: 4b32 ldr r3, [pc, #200] ; (800cf04 ) + 800ce3a: 8a5b ldrh r3, [r3, #18] + 800ce3c: f5c3 7300 rsb r3, r3, #512 ; 0x200 + 800ce40: 82fb strh r3, [r7, #22] + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + 800ce42: 88fa ldrh r2, [r7, #6] + 800ce44: 8afb ldrh r3, [r7, #22] + 800ce46: 429a cmp r2, r3 + 800ce48: d33a bcc.n 800cec0 + 800ce4a: 4b2e ldr r3, [pc, #184] ; (800cf04 ) + 800ce4c: 8a1b ldrh r3, [r3, #16] + 800ce4e: 88fa ldrh r2, [r7, #6] + 800ce50: 429a cmp r2, r3 + 800ce52: d235 bcs.n 800cec0 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + 800ce54: 4b2b ldr r3, [pc, #172] ; (800cf04 ) + 800ce56: 2201 movs r2, #1 + 800ce58: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + 800ce5a: 4b2a ldr r3, [pc, #168] ; (800cf04 ) + 800ce5c: 8a5a ldrh r2, [r3, #18] + 800ce5e: 4b29 ldr r3, [pc, #164] ; (800cf04 ) + 800ce60: 801a strh r2, [r3, #0] + freesize = ADV_TRACE_Ctx.TraceRdPtr; + 800ce62: 4b28 ldr r3, [pc, #160] ; (800cf04 ) + 800ce64: 8a1b ldrh r3, [r3, #16] + 800ce66: 82fb strh r3, [r7, #22] + ADV_TRACE_Ctx.TraceWrPtr = 0; + 800ce68: 4b26 ldr r3, [pc, #152] ; (800cf04 ) + 800ce6a: 2200 movs r2, #0 + 800ce6c: 825a strh r2, [r3, #18] + 800ce6e: e027 b.n 800cec0 +#endif + } + else + { +#ifdef UTIL_ADV_TRACE_UNCHUNK_MODE + if (ADV_TRACE_Ctx.TraceWrPtr > ADV_TRACE_Ctx.TraceRdPtr) + 800ce70: 4b24 ldr r3, [pc, #144] ; (800cf04 ) + 800ce72: 8a5a ldrh r2, [r3, #18] + 800ce74: 4b23 ldr r3, [pc, #140] ; (800cf04 ) + 800ce76: 8a1b ldrh r3, [r3, #16] + 800ce78: 429a cmp r2, r3 + 800ce7a: d91b bls.n 800ceb4 + { + freesize = (uint16_t)(UTIL_ADV_TRACE_FIFO_SIZE - ADV_TRACE_Ctx.TraceWrPtr); + 800ce7c: 4b21 ldr r3, [pc, #132] ; (800cf04 ) + 800ce7e: 8a5b ldrh r3, [r3, #18] + 800ce80: f5c3 7300 rsb r3, r3, #512 ; 0x200 + 800ce84: 82fb strh r3, [r7, #22] + if((Size >= freesize) && (ADV_TRACE_Ctx.TraceRdPtr > Size)) + 800ce86: 88fa ldrh r2, [r7, #6] + 800ce88: 8afb ldrh r3, [r7, #22] + 800ce8a: 429a cmp r2, r3 + 800ce8c: d318 bcc.n 800cec0 + 800ce8e: 4b1d ldr r3, [pc, #116] ; (800cf04 ) + 800ce90: 8a1b ldrh r3, [r3, #16] + 800ce92: 88fa ldrh r2, [r7, #6] + 800ce94: 429a cmp r2, r3 + 800ce96: d213 bcs.n 800cec0 + { + ADV_TRACE_Ctx.unchunk_status = TRACE_UNCHUNK_DETECTED; + 800ce98: 4b1a ldr r3, [pc, #104] ; (800cf04 ) + 800ce9a: 2201 movs r2, #1 + 800ce9c: 709a strb r2, [r3, #2] + ADV_TRACE_Ctx.unchunk_enabled = ADV_TRACE_Ctx.TraceWrPtr; + 800ce9e: 4b19 ldr r3, [pc, #100] ; (800cf04 ) + 800cea0: 8a5a ldrh r2, [r3, #18] + 800cea2: 4b18 ldr r3, [pc, #96] ; (800cf04 ) + 800cea4: 801a strh r2, [r3, #0] + freesize = ADV_TRACE_Ctx.TraceRdPtr; + 800cea6: 4b17 ldr r3, [pc, #92] ; (800cf04 ) + 800cea8: 8a1b ldrh r3, [r3, #16] + 800ceaa: 82fb strh r3, [r7, #22] + ADV_TRACE_Ctx.TraceWrPtr = 0; + 800ceac: 4b15 ldr r3, [pc, #84] ; (800cf04 ) + 800ceae: 2200 movs r2, #0 + 800ceb0: 825a strh r2, [r3, #18] + 800ceb2: e005 b.n 800cec0 + } + } + else + { + freesize = (uint16_t)(ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr); + 800ceb4: 4b13 ldr r3, [pc, #76] ; (800cf04 ) + 800ceb6: 8a1a ldrh r2, [r3, #16] + 800ceb8: 4b12 ldr r3, [pc, #72] ; (800cf04 ) + 800ceba: 8a5b ldrh r3, [r3, #18] + 800cebc: 1ad3 subs r3, r2, r3 + 800cebe: 82fb strh r3, [r7, #22] + freesize = ADV_TRACE_Ctx.TraceRdPtr - ADV_TRACE_Ctx.TraceWrPtr; + } +#endif + } + + if(freesize > Size) + 800cec0: 8afa ldrh r2, [r7, #22] + 800cec2: 88fb ldrh r3, [r7, #6] + 800cec4: 429a cmp r2, r3 + 800cec6: d90f bls.n 800cee8 + { + *Pos = ADV_TRACE_Ctx.TraceWrPtr; + 800cec8: 4b0e ldr r3, [pc, #56] ; (800cf04 ) + 800ceca: 8a5a ldrh r2, [r3, #18] + 800cecc: 683b ldr r3, [r7, #0] + 800cece: 801a strh r2, [r3, #0] + ADV_TRACE_Ctx.TraceWrPtr = (ADV_TRACE_Ctx.TraceWrPtr + Size) % UTIL_ADV_TRACE_FIFO_SIZE; + 800ced0: 4b0c ldr r3, [pc, #48] ; (800cf04 ) + 800ced2: 8a5a ldrh r2, [r3, #18] + 800ced4: 88fb ldrh r3, [r7, #6] + 800ced6: 4413 add r3, r2 + 800ced8: b29b uxth r3, r3 + 800ceda: f3c3 0308 ubfx r3, r3, #0, #9 + 800cede: b29a uxth r2, r3 + 800cee0: 4b08 ldr r3, [pc, #32] ; (800cf04 ) + 800cee2: 825a strh r2, [r3, #18] + ret = 0; + 800cee4: 2300 movs r3, #0 + 800cee6: 82bb strh r3, [r7, #20] + 800cee8: 693b ldr r3, [r7, #16] + 800ceea: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800ceec: 68bb ldr r3, [r7, #8] + 800ceee: f383 8810 msr PRIMASK, r3 +} + 800cef2: bf00 nop + } + } +#endif + + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); + return ret; + 800cef4: f9b7 3014 ldrsh.w r3, [r7, #20] +} + 800cef8: 4618 mov r0, r3 + 800cefa: 371c adds r7, #28 + 800cefc: 46bd mov sp, r7 + 800cefe: bc80 pop {r7} + 800cf00: 4770 bx lr + 800cf02: bf00 nop + 800cf04: 200005e4 .word 0x200005e4 + +0800cf08 : +/** + * @brief Lock the trace buffer. + * @retval None. + */ +static void TRACE_Lock(void) +{ + 800cf08: b480 push {r7} + 800cf0a: b085 sub sp, #20 + 800cf0c: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800cf0e: f3ef 8310 mrs r3, PRIMASK + 800cf12: 607b str r3, [r7, #4] + return(result); + 800cf14: 687b ldr r3, [r7, #4] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800cf16: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800cf18: b672 cpsid i +} + 800cf1a: bf00 nop + ADV_TRACE_Ctx.TraceLock++; + 800cf1c: 4b08 ldr r3, [pc, #32] ; (800cf40 ) + 800cf1e: 8adb ldrh r3, [r3, #22] + 800cf20: 3301 adds r3, #1 + 800cf22: b29a uxth r2, r3 + 800cf24: 4b06 ldr r3, [pc, #24] ; (800cf40 ) + 800cf26: 82da strh r2, [r3, #22] + 800cf28: 68fb ldr r3, [r7, #12] + 800cf2a: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cf2c: 68bb ldr r3, [r7, #8] + 800cf2e: f383 8810 msr PRIMASK, r3 +} + 800cf32: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + 800cf34: bf00 nop + 800cf36: 3714 adds r7, #20 + 800cf38: 46bd mov sp, r7 + 800cf3a: bc80 pop {r7} + 800cf3c: 4770 bx lr + 800cf3e: bf00 nop + 800cf40: 200005e4 .word 0x200005e4 + +0800cf44 : +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static void TRACE_UnLock(void) +{ + 800cf44: b480 push {r7} + 800cf46: b085 sub sp, #20 + 800cf48: af00 add r7, sp, #0 + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + 800cf4a: f3ef 8310 mrs r3, PRIMASK + 800cf4e: 607b str r3, [r7, #4] + return(result); + 800cf50: 687b ldr r3, [r7, #4] + UTIL_ADV_TRACE_ENTER_CRITICAL_SECTION(); + 800cf52: 60fb str r3, [r7, #12] + __ASM volatile ("cpsid i" : : : "memory"); + 800cf54: b672 cpsid i +} + 800cf56: bf00 nop + ADV_TRACE_Ctx.TraceLock--; + 800cf58: 4b08 ldr r3, [pc, #32] ; (800cf7c ) + 800cf5a: 8adb ldrh r3, [r3, #22] + 800cf5c: 3b01 subs r3, #1 + 800cf5e: b29a uxth r2, r3 + 800cf60: 4b06 ldr r3, [pc, #24] ; (800cf7c ) + 800cf62: 82da strh r2, [r3, #22] + 800cf64: 68fb ldr r3, [r7, #12] + 800cf66: 60bb str r3, [r7, #8] + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); + 800cf68: 68bb ldr r3, [r7, #8] + 800cf6a: f383 8810 msr PRIMASK, r3 +} + 800cf6e: bf00 nop + UTIL_ADV_TRACE_EXIT_CRITICAL_SECTION(); +} + 800cf70: bf00 nop + 800cf72: 3714 adds r7, #20 + 800cf74: 46bd mov sp, r7 + 800cf76: bc80 pop {r7} + 800cf78: 4770 bx lr + 800cf7a: bf00 nop + 800cf7c: 200005e4 .word 0x200005e4 + +0800cf80 : +/** + * @brief UnLock the trace buffer. + * @retval None. + */ +static uint32_t TRACE_IsLocked(void) +{ + 800cf80: b480 push {r7} + 800cf82: af00 add r7, sp, #0 + return (ADV_TRACE_Ctx.TraceLock == 0u? 0u: 1u); + 800cf84: 4b05 ldr r3, [pc, #20] ; (800cf9c ) + 800cf86: 8adb ldrh r3, [r3, #22] + 800cf88: 2b00 cmp r3, #0 + 800cf8a: bf14 ite ne + 800cf8c: 2301 movne r3, #1 + 800cf8e: 2300 moveq r3, #0 + 800cf90: b2db uxtb r3, r3 +} + 800cf92: 4618 mov r0, r3 + 800cf94: 46bd mov sp, r7 + 800cf96: bc80 pop {r7} + 800cf98: 4770 bx lr + 800cf9a: bf00 nop + 800cf9c: 200005e4 .word 0x200005e4 + +0800cfa0 : + 800cfa0: 2300 movs r3, #0 + 800cfa2: b510 push {r4, lr} + 800cfa4: 4604 mov r4, r0 + 800cfa6: e9c0 3300 strd r3, r3, [r0] + 800cfaa: e9c0 3304 strd r3, r3, [r0, #16] + 800cfae: 6083 str r3, [r0, #8] + 800cfb0: 8181 strh r1, [r0, #12] + 800cfb2: 6643 str r3, [r0, #100] ; 0x64 + 800cfb4: 81c2 strh r2, [r0, #14] + 800cfb6: 6183 str r3, [r0, #24] + 800cfb8: 4619 mov r1, r3 + 800cfba: 2208 movs r2, #8 + 800cfbc: 305c adds r0, #92 ; 0x5c + 800cfbe: f000 f8f4 bl 800d1aa + 800cfc2: 4b0d ldr r3, [pc, #52] ; (800cff8 ) + 800cfc4: 6263 str r3, [r4, #36] ; 0x24 + 800cfc6: 4b0d ldr r3, [pc, #52] ; (800cffc ) + 800cfc8: 62a3 str r3, [r4, #40] ; 0x28 + 800cfca: 4b0d ldr r3, [pc, #52] ; (800d000 ) + 800cfcc: 62e3 str r3, [r4, #44] ; 0x2c + 800cfce: 4b0d ldr r3, [pc, #52] ; (800d004 ) + 800cfd0: 6323 str r3, [r4, #48] ; 0x30 + 800cfd2: 4b0d ldr r3, [pc, #52] ; (800d008 ) + 800cfd4: 6224 str r4, [r4, #32] + 800cfd6: 429c cmp r4, r3 + 800cfd8: d006 beq.n 800cfe8 + 800cfda: f103 0268 add.w r2, r3, #104 ; 0x68 + 800cfde: 4294 cmp r4, r2 + 800cfe0: d002 beq.n 800cfe8 + 800cfe2: 33d0 adds r3, #208 ; 0xd0 + 800cfe4: 429c cmp r4, r3 + 800cfe6: d105 bne.n 800cff4 + 800cfe8: f104 0058 add.w r0, r4, #88 ; 0x58 + 800cfec: e8bd 4010 ldmia.w sp!, {r4, lr} + 800cff0: f000 b9c6 b.w 800d380 <__retarget_lock_init_recursive> + 800cff4: bd10 pop {r4, pc} + 800cff6: bf00 nop + 800cff8: 0800d125 .word 0x0800d125 + 800cffc: 0800d147 .word 0x0800d147 + 800d000: 0800d17f .word 0x0800d17f + 800d004: 0800d1a3 .word 0x0800d1a3 + 800d008: 200008fc .word 0x200008fc + +0800d00c : + 800d00c: 4a02 ldr r2, [pc, #8] ; (800d018 ) + 800d00e: 4903 ldr r1, [pc, #12] ; (800d01c ) + 800d010: 4803 ldr r0, [pc, #12] ; (800d020 ) + 800d012: f000 b869 b.w 800d0e8 <_fwalk_sglue> + 800d016: bf00 nop + 800d018: 20000034 .word 0x20000034 + 800d01c: 0800d6e1 .word 0x0800d6e1 + 800d020: 20000040 .word 0x20000040 + +0800d024 : + 800d024: 6841 ldr r1, [r0, #4] + 800d026: 4b0c ldr r3, [pc, #48] ; (800d058 ) + 800d028: 4299 cmp r1, r3 + 800d02a: b510 push {r4, lr} + 800d02c: 4604 mov r4, r0 + 800d02e: d001 beq.n 800d034 + 800d030: f000 fb56 bl 800d6e0 <_fflush_r> + 800d034: 68a1 ldr r1, [r4, #8] + 800d036: 4b09 ldr r3, [pc, #36] ; (800d05c ) + 800d038: 4299 cmp r1, r3 + 800d03a: d002 beq.n 800d042 + 800d03c: 4620 mov r0, r4 + 800d03e: f000 fb4f bl 800d6e0 <_fflush_r> + 800d042: 68e1 ldr r1, [r4, #12] + 800d044: 4b06 ldr r3, [pc, #24] ; (800d060 ) + 800d046: 4299 cmp r1, r3 + 800d048: d004 beq.n 800d054 + 800d04a: 4620 mov r0, r4 + 800d04c: e8bd 4010 ldmia.w sp!, {r4, lr} + 800d050: f000 bb46 b.w 800d6e0 <_fflush_r> + 800d054: bd10 pop {r4, pc} + 800d056: bf00 nop + 800d058: 200008fc .word 0x200008fc + 800d05c: 20000964 .word 0x20000964 + 800d060: 200009cc .word 0x200009cc + +0800d064 : + 800d064: b510 push {r4, lr} + 800d066: 4b0b ldr r3, [pc, #44] ; (800d094 ) + 800d068: 4c0b ldr r4, [pc, #44] ; (800d098 ) + 800d06a: 4a0c ldr r2, [pc, #48] ; (800d09c ) + 800d06c: 601a str r2, [r3, #0] + 800d06e: 4620 mov r0, r4 + 800d070: 2200 movs r2, #0 + 800d072: 2104 movs r1, #4 + 800d074: f7ff ff94 bl 800cfa0 + 800d078: f104 0068 add.w r0, r4, #104 ; 0x68 + 800d07c: 2201 movs r2, #1 + 800d07e: 2109 movs r1, #9 + 800d080: f7ff ff8e bl 800cfa0 + 800d084: f104 00d0 add.w r0, r4, #208 ; 0xd0 + 800d088: 2202 movs r2, #2 + 800d08a: e8bd 4010 ldmia.w sp!, {r4, lr} + 800d08e: 2112 movs r1, #18 + 800d090: f7ff bf86 b.w 800cfa0 + 800d094: 20000a34 .word 0x20000a34 + 800d098: 200008fc .word 0x200008fc + 800d09c: 0800d00d .word 0x0800d00d + +0800d0a0 <__sfp_lock_acquire>: + 800d0a0: 4801 ldr r0, [pc, #4] ; (800d0a8 <__sfp_lock_acquire+0x8>) + 800d0a2: f000 b96e b.w 800d382 <__retarget_lock_acquire_recursive> + 800d0a6: bf00 nop + 800d0a8: 20000a3d .word 0x20000a3d + +0800d0ac <__sfp_lock_release>: + 800d0ac: 4801 ldr r0, [pc, #4] ; (800d0b4 <__sfp_lock_release+0x8>) + 800d0ae: f000 b969 b.w 800d384 <__retarget_lock_release_recursive> + 800d0b2: bf00 nop + 800d0b4: 20000a3d .word 0x20000a3d + +0800d0b8 <__sinit>: + 800d0b8: b510 push {r4, lr} + 800d0ba: 4604 mov r4, r0 + 800d0bc: f7ff fff0 bl 800d0a0 <__sfp_lock_acquire> + 800d0c0: 6a23 ldr r3, [r4, #32] + 800d0c2: b11b cbz r3, 800d0cc <__sinit+0x14> + 800d0c4: e8bd 4010 ldmia.w sp!, {r4, lr} + 800d0c8: f7ff bff0 b.w 800d0ac <__sfp_lock_release> + 800d0cc: 4b04 ldr r3, [pc, #16] ; (800d0e0 <__sinit+0x28>) + 800d0ce: 6223 str r3, [r4, #32] + 800d0d0: 4b04 ldr r3, [pc, #16] ; (800d0e4 <__sinit+0x2c>) + 800d0d2: 681b ldr r3, [r3, #0] + 800d0d4: 2b00 cmp r3, #0 + 800d0d6: d1f5 bne.n 800d0c4 <__sinit+0xc> + 800d0d8: f7ff ffc4 bl 800d064 + 800d0dc: e7f2 b.n 800d0c4 <__sinit+0xc> + 800d0de: bf00 nop + 800d0e0: 0800d025 .word 0x0800d025 + 800d0e4: 20000a34 .word 0x20000a34 + +0800d0e8 <_fwalk_sglue>: + 800d0e8: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800d0ec: 4607 mov r7, r0 + 800d0ee: 4688 mov r8, r1 + 800d0f0: 4614 mov r4, r2 + 800d0f2: 2600 movs r6, #0 + 800d0f4: e9d4 9501 ldrd r9, r5, [r4, #4] + 800d0f8: f1b9 0901 subs.w r9, r9, #1 + 800d0fc: d505 bpl.n 800d10a <_fwalk_sglue+0x22> + 800d0fe: 6824 ldr r4, [r4, #0] + 800d100: 2c00 cmp r4, #0 + 800d102: d1f7 bne.n 800d0f4 <_fwalk_sglue+0xc> + 800d104: 4630 mov r0, r6 + 800d106: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800d10a: 89ab ldrh r3, [r5, #12] + 800d10c: 2b01 cmp r3, #1 + 800d10e: d907 bls.n 800d120 <_fwalk_sglue+0x38> + 800d110: f9b5 300e ldrsh.w r3, [r5, #14] + 800d114: 3301 adds r3, #1 + 800d116: d003 beq.n 800d120 <_fwalk_sglue+0x38> + 800d118: 4629 mov r1, r5 + 800d11a: 4638 mov r0, r7 + 800d11c: 47c0 blx r8 + 800d11e: 4306 orrs r6, r0 + 800d120: 3568 adds r5, #104 ; 0x68 + 800d122: e7e9 b.n 800d0f8 <_fwalk_sglue+0x10> + +0800d124 <__sread>: + 800d124: b510 push {r4, lr} + 800d126: 460c mov r4, r1 + 800d128: f9b1 100e ldrsh.w r1, [r1, #14] + 800d12c: f000 f8da bl 800d2e4 <_read_r> + 800d130: 2800 cmp r0, #0 + 800d132: bfab itete ge + 800d134: 6d63 ldrge r3, [r4, #84] ; 0x54 + 800d136: 89a3 ldrhlt r3, [r4, #12] + 800d138: 181b addge r3, r3, r0 + 800d13a: f423 5380 biclt.w r3, r3, #4096 ; 0x1000 + 800d13e: bfac ite ge + 800d140: 6563 strge r3, [r4, #84] ; 0x54 + 800d142: 81a3 strhlt r3, [r4, #12] + 800d144: bd10 pop {r4, pc} + +0800d146 <__swrite>: + 800d146: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800d14a: 461f mov r7, r3 + 800d14c: 898b ldrh r3, [r1, #12] + 800d14e: 05db lsls r3, r3, #23 + 800d150: 4605 mov r5, r0 + 800d152: 460c mov r4, r1 + 800d154: 4616 mov r6, r2 + 800d156: d505 bpl.n 800d164 <__swrite+0x1e> + 800d158: f9b1 100e ldrsh.w r1, [r1, #14] + 800d15c: 2302 movs r3, #2 + 800d15e: 2200 movs r2, #0 + 800d160: f000 f8ae bl 800d2c0 <_lseek_r> + 800d164: 89a3 ldrh r3, [r4, #12] + 800d166: f9b4 100e ldrsh.w r1, [r4, #14] + 800d16a: f423 5380 bic.w r3, r3, #4096 ; 0x1000 + 800d16e: 81a3 strh r3, [r4, #12] + 800d170: 4632 mov r2, r6 + 800d172: 463b mov r3, r7 + 800d174: 4628 mov r0, r5 + 800d176: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800d17a: f000 b8c5 b.w 800d308 <_write_r> + +0800d17e <__sseek>: + 800d17e: b510 push {r4, lr} + 800d180: 460c mov r4, r1 + 800d182: f9b1 100e ldrsh.w r1, [r1, #14] + 800d186: f000 f89b bl 800d2c0 <_lseek_r> + 800d18a: 1c43 adds r3, r0, #1 + 800d18c: 89a3 ldrh r3, [r4, #12] + 800d18e: bf15 itete ne + 800d190: 6560 strne r0, [r4, #84] ; 0x54 + 800d192: f423 5380 biceq.w r3, r3, #4096 ; 0x1000 + 800d196: f443 5380 orrne.w r3, r3, #4096 ; 0x1000 + 800d19a: 81a3 strheq r3, [r4, #12] + 800d19c: bf18 it ne + 800d19e: 81a3 strhne r3, [r4, #12] + 800d1a0: bd10 pop {r4, pc} + +0800d1a2 <__sclose>: + 800d1a2: f9b1 100e ldrsh.w r1, [r1, #14] + 800d1a6: f000 b87b b.w 800d2a0 <_close_r> + +0800d1aa : + 800d1aa: 4402 add r2, r0 + 800d1ac: 4603 mov r3, r0 + 800d1ae: 4293 cmp r3, r2 + 800d1b0: d100 bne.n 800d1b4 + 800d1b2: 4770 bx lr + 800d1b4: f803 1b01 strb.w r1, [r3], #1 + 800d1b8: e7f9 b.n 800d1ae + ... + +0800d1bc : + 800d1bc: 4b16 ldr r3, [pc, #88] ; (800d218 ) + 800d1be: e92d 41f0 stmdb sp!, {r4, r5, r6, r7, r8, lr} + 800d1c2: 681f ldr r7, [r3, #0] + 800d1c4: 6c7c ldr r4, [r7, #68] ; 0x44 + 800d1c6: 4605 mov r5, r0 + 800d1c8: 460e mov r6, r1 + 800d1ca: b9ec cbnz r4, 800d208 + 800d1cc: 2050 movs r0, #80 ; 0x50 + 800d1ce: f000 f951 bl 800d474 + 800d1d2: 4602 mov r2, r0 + 800d1d4: 6478 str r0, [r7, #68] ; 0x44 + 800d1d6: b920 cbnz r0, 800d1e2 + 800d1d8: 4b10 ldr r3, [pc, #64] ; (800d21c ) + 800d1da: 4811 ldr r0, [pc, #68] ; (800d220 ) + 800d1dc: 215b movs r1, #91 ; 0x5b + 800d1de: f000 f8e1 bl 800d3a4 <__assert_func> + 800d1e2: e9c0 4400 strd r4, r4, [r0] + 800d1e6: e9c0 4402 strd r4, r4, [r0, #8] + 800d1ea: e9c0 4404 strd r4, r4, [r0, #16] + 800d1ee: e9c0 440a strd r4, r4, [r0, #40] ; 0x28 + 800d1f2: e9c0 440c strd r4, r4, [r0, #48] ; 0x30 + 800d1f6: e9c0 440e strd r4, r4, [r0, #56] ; 0x38 + 800d1fa: e9c0 4410 strd r4, r4, [r0, #64] ; 0x40 + 800d1fe: e9c0 4412 strd r4, r4, [r0, #72] ; 0x48 + 800d202: 6184 str r4, [r0, #24] + 800d204: 7704 strb r4, [r0, #28] + 800d206: 6244 str r4, [r0, #36] ; 0x24 + 800d208: 6c7a ldr r2, [r7, #68] ; 0x44 + 800d20a: 4631 mov r1, r6 + 800d20c: 4628 mov r0, r5 + 800d20e: 2301 movs r3, #1 + 800d210: e8bd 41f0 ldmia.w sp!, {r4, r5, r6, r7, r8, lr} + 800d214: f000 b806 b.w 800d224 <__strtok_r> + 800d218: 2000008c .word 0x2000008c + 800d21c: 0800e554 .word 0x0800e554 + 800d220: 0800e56b .word 0x0800e56b + +0800d224 <__strtok_r>: + 800d224: b5f0 push {r4, r5, r6, r7, lr} + 800d226: b908 cbnz r0, 800d22c <__strtok_r+0x8> + 800d228: 6810 ldr r0, [r2, #0] + 800d22a: b188 cbz r0, 800d250 <__strtok_r+0x2c> + 800d22c: 4604 mov r4, r0 + 800d22e: 4620 mov r0, r4 + 800d230: f814 5b01 ldrb.w r5, [r4], #1 + 800d234: 460f mov r7, r1 + 800d236: f817 6b01 ldrb.w r6, [r7], #1 + 800d23a: b91e cbnz r6, 800d244 <__strtok_r+0x20> + 800d23c: b965 cbnz r5, 800d258 <__strtok_r+0x34> + 800d23e: 6015 str r5, [r2, #0] + 800d240: 4628 mov r0, r5 + 800d242: e005 b.n 800d250 <__strtok_r+0x2c> + 800d244: 42b5 cmp r5, r6 + 800d246: d1f6 bne.n 800d236 <__strtok_r+0x12> + 800d248: 2b00 cmp r3, #0 + 800d24a: d1f0 bne.n 800d22e <__strtok_r+0xa> + 800d24c: 6014 str r4, [r2, #0] + 800d24e: 7003 strb r3, [r0, #0] + 800d250: bdf0 pop {r4, r5, r6, r7, pc} + 800d252: 461c mov r4, r3 + 800d254: e00c b.n 800d270 <__strtok_r+0x4c> + 800d256: b915 cbnz r5, 800d25e <__strtok_r+0x3a> + 800d258: f814 3b01 ldrb.w r3, [r4], #1 + 800d25c: 460e mov r6, r1 + 800d25e: f816 5b01 ldrb.w r5, [r6], #1 + 800d262: 42ab cmp r3, r5 + 800d264: d1f7 bne.n 800d256 <__strtok_r+0x32> + 800d266: 2b00 cmp r3, #0 + 800d268: d0f3 beq.n 800d252 <__strtok_r+0x2e> + 800d26a: 2300 movs r3, #0 + 800d26c: f804 3c01 strb.w r3, [r4, #-1] + 800d270: 6014 str r4, [r2, #0] + 800d272: e7ed b.n 800d250 <__strtok_r+0x2c> + +0800d274 : + 800d274: 780a ldrb r2, [r1, #0] + 800d276: b570 push {r4, r5, r6, lr} + 800d278: b96a cbnz r2, 800d296 + 800d27a: bd70 pop {r4, r5, r6, pc} + 800d27c: 429a cmp r2, r3 + 800d27e: d109 bne.n 800d294 + 800d280: 460c mov r4, r1 + 800d282: 4605 mov r5, r0 + 800d284: f814 3f01 ldrb.w r3, [r4, #1]! + 800d288: 2b00 cmp r3, #0 + 800d28a: d0f6 beq.n 800d27a + 800d28c: f815 6f01 ldrb.w r6, [r5, #1]! + 800d290: 429e cmp r6, r3 + 800d292: d0f7 beq.n 800d284 + 800d294: 3001 adds r0, #1 + 800d296: 7803 ldrb r3, [r0, #0] + 800d298: 2b00 cmp r3, #0 + 800d29a: d1ef bne.n 800d27c + 800d29c: 4618 mov r0, r3 + 800d29e: e7ec b.n 800d27a + +0800d2a0 <_close_r>: + 800d2a0: b538 push {r3, r4, r5, lr} + 800d2a2: 4d06 ldr r5, [pc, #24] ; (800d2bc <_close_r+0x1c>) + 800d2a4: 2300 movs r3, #0 + 800d2a6: 4604 mov r4, r0 + 800d2a8: 4608 mov r0, r1 + 800d2aa: 602b str r3, [r5, #0] + 800d2ac: f7f3 fdd2 bl 8000e54 <_close> + 800d2b0: 1c43 adds r3, r0, #1 + 800d2b2: d102 bne.n 800d2ba <_close_r+0x1a> + 800d2b4: 682b ldr r3, [r5, #0] + 800d2b6: b103 cbz r3, 800d2ba <_close_r+0x1a> + 800d2b8: 6023 str r3, [r4, #0] + 800d2ba: bd38 pop {r3, r4, r5, pc} + 800d2bc: 20000a38 .word 0x20000a38 + +0800d2c0 <_lseek_r>: + 800d2c0: b538 push {r3, r4, r5, lr} + 800d2c2: 4d07 ldr r5, [pc, #28] ; (800d2e0 <_lseek_r+0x20>) + 800d2c4: 4604 mov r4, r0 + 800d2c6: 4608 mov r0, r1 + 800d2c8: 4611 mov r1, r2 + 800d2ca: 2200 movs r2, #0 + 800d2cc: 602a str r2, [r5, #0] + 800d2ce: 461a mov r2, r3 + 800d2d0: f7f3 fde4 bl 8000e9c <_lseek> + 800d2d4: 1c43 adds r3, r0, #1 + 800d2d6: d102 bne.n 800d2de <_lseek_r+0x1e> + 800d2d8: 682b ldr r3, [r5, #0] + 800d2da: b103 cbz r3, 800d2de <_lseek_r+0x1e> + 800d2dc: 6023 str r3, [r4, #0] + 800d2de: bd38 pop {r3, r4, r5, pc} + 800d2e0: 20000a38 .word 0x20000a38 + +0800d2e4 <_read_r>: + 800d2e4: b538 push {r3, r4, r5, lr} + 800d2e6: 4d07 ldr r5, [pc, #28] ; (800d304 <_read_r+0x20>) + 800d2e8: 4604 mov r4, r0 + 800d2ea: 4608 mov r0, r1 + 800d2ec: 4611 mov r1, r2 + 800d2ee: 2200 movs r2, #0 + 800d2f0: 602a str r2, [r5, #0] + 800d2f2: 461a mov r2, r3 + 800d2f4: f7f3 fd75 bl 8000de2 <_read> + 800d2f8: 1c43 adds r3, r0, #1 + 800d2fa: d102 bne.n 800d302 <_read_r+0x1e> + 800d2fc: 682b ldr r3, [r5, #0] + 800d2fe: b103 cbz r3, 800d302 <_read_r+0x1e> + 800d300: 6023 str r3, [r4, #0] + 800d302: bd38 pop {r3, r4, r5, pc} + 800d304: 20000a38 .word 0x20000a38 + +0800d308 <_write_r>: + 800d308: b538 push {r3, r4, r5, lr} + 800d30a: 4d07 ldr r5, [pc, #28] ; (800d328 <_write_r+0x20>) + 800d30c: 4604 mov r4, r0 + 800d30e: 4608 mov r0, r1 + 800d310: 4611 mov r1, r2 + 800d312: 2200 movs r2, #0 + 800d314: 602a str r2, [r5, #0] + 800d316: 461a mov r2, r3 + 800d318: f7f3 fd80 bl 8000e1c <_write> + 800d31c: 1c43 adds r3, r0, #1 + 800d31e: d102 bne.n 800d326 <_write_r+0x1e> + 800d320: 682b ldr r3, [r5, #0] + 800d322: b103 cbz r3, 800d326 <_write_r+0x1e> + 800d324: 6023 str r3, [r4, #0] + 800d326: bd38 pop {r3, r4, r5, pc} + 800d328: 20000a38 .word 0x20000a38 + +0800d32c <__errno>: + 800d32c: 4b01 ldr r3, [pc, #4] ; (800d334 <__errno+0x8>) + 800d32e: 6818 ldr r0, [r3, #0] + 800d330: 4770 bx lr + 800d332: bf00 nop + 800d334: 2000008c .word 0x2000008c + +0800d338 <__libc_init_array>: + 800d338: b570 push {r4, r5, r6, lr} + 800d33a: 4d0d ldr r5, [pc, #52] ; (800d370 <__libc_init_array+0x38>) + 800d33c: 4c0d ldr r4, [pc, #52] ; (800d374 <__libc_init_array+0x3c>) + 800d33e: 1b64 subs r4, r4, r5 + 800d340: 10a4 asrs r4, r4, #2 + 800d342: 2600 movs r6, #0 + 800d344: 42a6 cmp r6, r4 + 800d346: d109 bne.n 800d35c <__libc_init_array+0x24> + 800d348: 4d0b ldr r5, [pc, #44] ; (800d378 <__libc_init_array+0x40>) + 800d34a: 4c0c ldr r4, [pc, #48] ; (800d37c <__libc_init_array+0x44>) + 800d34c: f000 fe48 bl 800dfe0 <_init> + 800d350: 1b64 subs r4, r4, r5 + 800d352: 10a4 asrs r4, r4, #2 + 800d354: 2600 movs r6, #0 + 800d356: 42a6 cmp r6, r4 + 800d358: d105 bne.n 800d366 <__libc_init_array+0x2e> + 800d35a: bd70 pop {r4, r5, r6, pc} + 800d35c: f855 3b04 ldr.w r3, [r5], #4 + 800d360: 4798 blx r3 + 800d362: 3601 adds r6, #1 + 800d364: e7ee b.n 800d344 <__libc_init_array+0xc> + 800d366: f855 3b04 ldr.w r3, [r5], #4 + 800d36a: 4798 blx r3 + 800d36c: 3601 adds r6, #1 + 800d36e: e7f2 b.n 800d356 <__libc_init_array+0x1e> + 800d370: 0800e63c .word 0x0800e63c + 800d374: 0800e63c .word 0x0800e63c + 800d378: 0800e63c .word 0x0800e63c + 800d37c: 0800e640 .word 0x0800e640 + +0800d380 <__retarget_lock_init_recursive>: + 800d380: 4770 bx lr + +0800d382 <__retarget_lock_acquire_recursive>: + 800d382: 4770 bx lr + +0800d384 <__retarget_lock_release_recursive>: + 800d384: 4770 bx lr + +0800d386 : + 800d386: 440a add r2, r1 + 800d388: 4291 cmp r1, r2 + 800d38a: f100 33ff add.w r3, r0, #4294967295 + 800d38e: d100 bne.n 800d392 + 800d390: 4770 bx lr + 800d392: b510 push {r4, lr} + 800d394: f811 4b01 ldrb.w r4, [r1], #1 + 800d398: f803 4f01 strb.w r4, [r3, #1]! + 800d39c: 4291 cmp r1, r2 + 800d39e: d1f9 bne.n 800d394 + 800d3a0: bd10 pop {r4, pc} + ... + +0800d3a4 <__assert_func>: + 800d3a4: b51f push {r0, r1, r2, r3, r4, lr} + 800d3a6: 4614 mov r4, r2 + 800d3a8: 461a mov r2, r3 + 800d3aa: 4b09 ldr r3, [pc, #36] ; (800d3d0 <__assert_func+0x2c>) + 800d3ac: 681b ldr r3, [r3, #0] + 800d3ae: 4605 mov r5, r0 + 800d3b0: 68d8 ldr r0, [r3, #12] + 800d3b2: b14c cbz r4, 800d3c8 <__assert_func+0x24> + 800d3b4: 4b07 ldr r3, [pc, #28] ; (800d3d4 <__assert_func+0x30>) + 800d3b6: 9100 str r1, [sp, #0] + 800d3b8: e9cd 3401 strd r3, r4, [sp, #4] + 800d3bc: 4906 ldr r1, [pc, #24] ; (800d3d8 <__assert_func+0x34>) + 800d3be: 462b mov r3, r5 + 800d3c0: f000 f9b6 bl 800d730 + 800d3c4: f000 f9d6 bl 800d774 + 800d3c8: 4b04 ldr r3, [pc, #16] ; (800d3dc <__assert_func+0x38>) + 800d3ca: 461c mov r4, r3 + 800d3cc: e7f3 b.n 800d3b6 <__assert_func+0x12> + 800d3ce: bf00 nop + 800d3d0: 2000008c .word 0x2000008c + 800d3d4: 0800e5c5 .word 0x0800e5c5 + 800d3d8: 0800e5d2 .word 0x0800e5d2 + 800d3dc: 0800e600 .word 0x0800e600 + +0800d3e0 <_free_r>: + 800d3e0: b538 push {r3, r4, r5, lr} + 800d3e2: 4605 mov r5, r0 + 800d3e4: 2900 cmp r1, #0 + 800d3e6: d041 beq.n 800d46c <_free_r+0x8c> + 800d3e8: f851 3c04 ldr.w r3, [r1, #-4] + 800d3ec: 1f0c subs r4, r1, #4 + 800d3ee: 2b00 cmp r3, #0 + 800d3f0: bfb8 it lt + 800d3f2: 18e4 addlt r4, r4, r3 + 800d3f4: f000 f8e6 bl 800d5c4 <__malloc_lock> + 800d3f8: 4a1d ldr r2, [pc, #116] ; (800d470 <_free_r+0x90>) + 800d3fa: 6813 ldr r3, [r2, #0] + 800d3fc: b933 cbnz r3, 800d40c <_free_r+0x2c> + 800d3fe: 6063 str r3, [r4, #4] + 800d400: 6014 str r4, [r2, #0] + 800d402: 4628 mov r0, r5 + 800d404: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800d408: f000 b8e2 b.w 800d5d0 <__malloc_unlock> + 800d40c: 42a3 cmp r3, r4 + 800d40e: d908 bls.n 800d422 <_free_r+0x42> + 800d410: 6820 ldr r0, [r4, #0] + 800d412: 1821 adds r1, r4, r0 + 800d414: 428b cmp r3, r1 + 800d416: bf01 itttt eq + 800d418: 6819 ldreq r1, [r3, #0] + 800d41a: 685b ldreq r3, [r3, #4] + 800d41c: 1809 addeq r1, r1, r0 + 800d41e: 6021 streq r1, [r4, #0] + 800d420: e7ed b.n 800d3fe <_free_r+0x1e> + 800d422: 461a mov r2, r3 + 800d424: 685b ldr r3, [r3, #4] + 800d426: b10b cbz r3, 800d42c <_free_r+0x4c> + 800d428: 42a3 cmp r3, r4 + 800d42a: d9fa bls.n 800d422 <_free_r+0x42> + 800d42c: 6811 ldr r1, [r2, #0] + 800d42e: 1850 adds r0, r2, r1 + 800d430: 42a0 cmp r0, r4 + 800d432: d10b bne.n 800d44c <_free_r+0x6c> + 800d434: 6820 ldr r0, [r4, #0] + 800d436: 4401 add r1, r0 + 800d438: 1850 adds r0, r2, r1 + 800d43a: 4283 cmp r3, r0 + 800d43c: 6011 str r1, [r2, #0] + 800d43e: d1e0 bne.n 800d402 <_free_r+0x22> + 800d440: 6818 ldr r0, [r3, #0] + 800d442: 685b ldr r3, [r3, #4] + 800d444: 6053 str r3, [r2, #4] + 800d446: 4408 add r0, r1 + 800d448: 6010 str r0, [r2, #0] + 800d44a: e7da b.n 800d402 <_free_r+0x22> + 800d44c: d902 bls.n 800d454 <_free_r+0x74> + 800d44e: 230c movs r3, #12 + 800d450: 602b str r3, [r5, #0] + 800d452: e7d6 b.n 800d402 <_free_r+0x22> + 800d454: 6820 ldr r0, [r4, #0] + 800d456: 1821 adds r1, r4, r0 + 800d458: 428b cmp r3, r1 + 800d45a: bf04 itt eq + 800d45c: 6819 ldreq r1, [r3, #0] + 800d45e: 685b ldreq r3, [r3, #4] + 800d460: 6063 str r3, [r4, #4] + 800d462: bf04 itt eq + 800d464: 1809 addeq r1, r1, r0 + 800d466: 6021 streq r1, [r4, #0] + 800d468: 6054 str r4, [r2, #4] + 800d46a: e7ca b.n 800d402 <_free_r+0x22> + 800d46c: bd38 pop {r3, r4, r5, pc} + 800d46e: bf00 nop + 800d470: 20000a40 .word 0x20000a40 + +0800d474 : + 800d474: 4b02 ldr r3, [pc, #8] ; (800d480 ) + 800d476: 4601 mov r1, r0 + 800d478: 6818 ldr r0, [r3, #0] + 800d47a: f000 b823 b.w 800d4c4 <_malloc_r> + 800d47e: bf00 nop + 800d480: 2000008c .word 0x2000008c + +0800d484 : + 800d484: b570 push {r4, r5, r6, lr} + 800d486: 4e0e ldr r6, [pc, #56] ; (800d4c0 ) + 800d488: 460c mov r4, r1 + 800d48a: 6831 ldr r1, [r6, #0] + 800d48c: 4605 mov r5, r0 + 800d48e: b911 cbnz r1, 800d496 + 800d490: f000 f960 bl 800d754 <_sbrk_r> + 800d494: 6030 str r0, [r6, #0] + 800d496: 4621 mov r1, r4 + 800d498: 4628 mov r0, r5 + 800d49a: f000 f95b bl 800d754 <_sbrk_r> + 800d49e: 1c43 adds r3, r0, #1 + 800d4a0: d00a beq.n 800d4b8 + 800d4a2: 1cc4 adds r4, r0, #3 + 800d4a4: f024 0403 bic.w r4, r4, #3 + 800d4a8: 42a0 cmp r0, r4 + 800d4aa: d007 beq.n 800d4bc + 800d4ac: 1a21 subs r1, r4, r0 + 800d4ae: 4628 mov r0, r5 + 800d4b0: f000 f950 bl 800d754 <_sbrk_r> + 800d4b4: 3001 adds r0, #1 + 800d4b6: d101 bne.n 800d4bc + 800d4b8: f04f 34ff mov.w r4, #4294967295 + 800d4bc: 4620 mov r0, r4 + 800d4be: bd70 pop {r4, r5, r6, pc} + 800d4c0: 20000a44 .word 0x20000a44 + +0800d4c4 <_malloc_r>: + 800d4c4: e92d 43f8 stmdb sp!, {r3, r4, r5, r6, r7, r8, r9, lr} + 800d4c8: 1ccd adds r5, r1, #3 + 800d4ca: f025 0503 bic.w r5, r5, #3 + 800d4ce: 3508 adds r5, #8 + 800d4d0: 2d0c cmp r5, #12 + 800d4d2: bf38 it cc + 800d4d4: 250c movcc r5, #12 + 800d4d6: 2d00 cmp r5, #0 + 800d4d8: 4607 mov r7, r0 + 800d4da: db01 blt.n 800d4e0 <_malloc_r+0x1c> + 800d4dc: 42a9 cmp r1, r5 + 800d4de: d905 bls.n 800d4ec <_malloc_r+0x28> + 800d4e0: 230c movs r3, #12 + 800d4e2: 603b str r3, [r7, #0] + 800d4e4: 2600 movs r6, #0 + 800d4e6: 4630 mov r0, r6 + 800d4e8: e8bd 83f8 ldmia.w sp!, {r3, r4, r5, r6, r7, r8, r9, pc} + 800d4ec: f8df 80d0 ldr.w r8, [pc, #208] ; 800d5c0 <_malloc_r+0xfc> + 800d4f0: f000 f868 bl 800d5c4 <__malloc_lock> + 800d4f4: f8d8 3000 ldr.w r3, [r8] + 800d4f8: 461c mov r4, r3 + 800d4fa: bb5c cbnz r4, 800d554 <_malloc_r+0x90> + 800d4fc: 4629 mov r1, r5 + 800d4fe: 4638 mov r0, r7 + 800d500: f7ff ffc0 bl 800d484 + 800d504: 1c43 adds r3, r0, #1 + 800d506: 4604 mov r4, r0 + 800d508: d155 bne.n 800d5b6 <_malloc_r+0xf2> + 800d50a: f8d8 4000 ldr.w r4, [r8] + 800d50e: 4626 mov r6, r4 + 800d510: 2e00 cmp r6, #0 + 800d512: d145 bne.n 800d5a0 <_malloc_r+0xdc> + 800d514: 2c00 cmp r4, #0 + 800d516: d048 beq.n 800d5aa <_malloc_r+0xe6> + 800d518: 6823 ldr r3, [r4, #0] + 800d51a: 4631 mov r1, r6 + 800d51c: 4638 mov r0, r7 + 800d51e: eb04 0903 add.w r9, r4, r3 + 800d522: f000 f917 bl 800d754 <_sbrk_r> + 800d526: 4581 cmp r9, r0 + 800d528: d13f bne.n 800d5aa <_malloc_r+0xe6> + 800d52a: 6821 ldr r1, [r4, #0] + 800d52c: 1a6d subs r5, r5, r1 + 800d52e: 4629 mov r1, r5 + 800d530: 4638 mov r0, r7 + 800d532: f7ff ffa7 bl 800d484 + 800d536: 3001 adds r0, #1 + 800d538: d037 beq.n 800d5aa <_malloc_r+0xe6> + 800d53a: 6823 ldr r3, [r4, #0] + 800d53c: 442b add r3, r5 + 800d53e: 6023 str r3, [r4, #0] + 800d540: f8d8 3000 ldr.w r3, [r8] + 800d544: 2b00 cmp r3, #0 + 800d546: d038 beq.n 800d5ba <_malloc_r+0xf6> + 800d548: 685a ldr r2, [r3, #4] + 800d54a: 42a2 cmp r2, r4 + 800d54c: d12b bne.n 800d5a6 <_malloc_r+0xe2> + 800d54e: 2200 movs r2, #0 + 800d550: 605a str r2, [r3, #4] + 800d552: e00f b.n 800d574 <_malloc_r+0xb0> + 800d554: 6822 ldr r2, [r4, #0] + 800d556: 1b52 subs r2, r2, r5 + 800d558: d41f bmi.n 800d59a <_malloc_r+0xd6> + 800d55a: 2a0b cmp r2, #11 + 800d55c: d917 bls.n 800d58e <_malloc_r+0xca> + 800d55e: 1961 adds r1, r4, r5 + 800d560: 42a3 cmp r3, r4 + 800d562: 6025 str r5, [r4, #0] + 800d564: bf18 it ne + 800d566: 6059 strne r1, [r3, #4] + 800d568: 6863 ldr r3, [r4, #4] + 800d56a: bf08 it eq + 800d56c: f8c8 1000 streq.w r1, [r8] + 800d570: 5162 str r2, [r4, r5] + 800d572: 604b str r3, [r1, #4] + 800d574: 4638 mov r0, r7 + 800d576: f104 060b add.w r6, r4, #11 + 800d57a: f000 f829 bl 800d5d0 <__malloc_unlock> + 800d57e: f026 0607 bic.w r6, r6, #7 + 800d582: 1d23 adds r3, r4, #4 + 800d584: 1af2 subs r2, r6, r3 + 800d586: d0ae beq.n 800d4e6 <_malloc_r+0x22> + 800d588: 1b9b subs r3, r3, r6 + 800d58a: 50a3 str r3, [r4, r2] + 800d58c: e7ab b.n 800d4e6 <_malloc_r+0x22> + 800d58e: 42a3 cmp r3, r4 + 800d590: 6862 ldr r2, [r4, #4] + 800d592: d1dd bne.n 800d550 <_malloc_r+0x8c> + 800d594: f8c8 2000 str.w r2, [r8] + 800d598: e7ec b.n 800d574 <_malloc_r+0xb0> + 800d59a: 4623 mov r3, r4 + 800d59c: 6864 ldr r4, [r4, #4] + 800d59e: e7ac b.n 800d4fa <_malloc_r+0x36> + 800d5a0: 4634 mov r4, r6 + 800d5a2: 6876 ldr r6, [r6, #4] + 800d5a4: e7b4 b.n 800d510 <_malloc_r+0x4c> + 800d5a6: 4613 mov r3, r2 + 800d5a8: e7cc b.n 800d544 <_malloc_r+0x80> + 800d5aa: 230c movs r3, #12 + 800d5ac: 603b str r3, [r7, #0] + 800d5ae: 4638 mov r0, r7 + 800d5b0: f000 f80e bl 800d5d0 <__malloc_unlock> + 800d5b4: e797 b.n 800d4e6 <_malloc_r+0x22> + 800d5b6: 6025 str r5, [r4, #0] + 800d5b8: e7dc b.n 800d574 <_malloc_r+0xb0> + 800d5ba: 605b str r3, [r3, #4] + 800d5bc: deff udf #255 ; 0xff + 800d5be: bf00 nop + 800d5c0: 20000a40 .word 0x20000a40 + +0800d5c4 <__malloc_lock>: + 800d5c4: 4801 ldr r0, [pc, #4] ; (800d5cc <__malloc_lock+0x8>) + 800d5c6: f7ff bedc b.w 800d382 <__retarget_lock_acquire_recursive> + 800d5ca: bf00 nop + 800d5cc: 20000a3c .word 0x20000a3c + +0800d5d0 <__malloc_unlock>: + 800d5d0: 4801 ldr r0, [pc, #4] ; (800d5d8 <__malloc_unlock+0x8>) + 800d5d2: f7ff bed7 b.w 800d384 <__retarget_lock_release_recursive> + 800d5d6: bf00 nop + 800d5d8: 20000a3c .word 0x20000a3c + +0800d5dc <__sflush_r>: + 800d5dc: 898a ldrh r2, [r1, #12] + 800d5de: b5f8 push {r3, r4, r5, r6, r7, lr} + 800d5e0: 4605 mov r5, r0 + 800d5e2: 0710 lsls r0, r2, #28 + 800d5e4: 460c mov r4, r1 + 800d5e6: d457 bmi.n 800d698 <__sflush_r+0xbc> + 800d5e8: 684b ldr r3, [r1, #4] + 800d5ea: 2b00 cmp r3, #0 + 800d5ec: dc04 bgt.n 800d5f8 <__sflush_r+0x1c> + 800d5ee: 6c0b ldr r3, [r1, #64] ; 0x40 + 800d5f0: 2b00 cmp r3, #0 + 800d5f2: dc01 bgt.n 800d5f8 <__sflush_r+0x1c> + 800d5f4: 2000 movs r0, #0 + 800d5f6: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800d5f8: 6ae6 ldr r6, [r4, #44] ; 0x2c + 800d5fa: 2e00 cmp r6, #0 + 800d5fc: d0fa beq.n 800d5f4 <__sflush_r+0x18> + 800d5fe: 2300 movs r3, #0 + 800d600: f412 5280 ands.w r2, r2, #4096 ; 0x1000 + 800d604: 682f ldr r7, [r5, #0] + 800d606: 6a21 ldr r1, [r4, #32] + 800d608: 602b str r3, [r5, #0] + 800d60a: d032 beq.n 800d672 <__sflush_r+0x96> + 800d60c: 6d60 ldr r0, [r4, #84] ; 0x54 + 800d60e: 89a3 ldrh r3, [r4, #12] + 800d610: 075a lsls r2, r3, #29 + 800d612: d505 bpl.n 800d620 <__sflush_r+0x44> + 800d614: 6863 ldr r3, [r4, #4] + 800d616: 1ac0 subs r0, r0, r3 + 800d618: 6b63 ldr r3, [r4, #52] ; 0x34 + 800d61a: b10b cbz r3, 800d620 <__sflush_r+0x44> + 800d61c: 6c23 ldr r3, [r4, #64] ; 0x40 + 800d61e: 1ac0 subs r0, r0, r3 + 800d620: 2300 movs r3, #0 + 800d622: 4602 mov r2, r0 + 800d624: 6ae6 ldr r6, [r4, #44] ; 0x2c + 800d626: 6a21 ldr r1, [r4, #32] + 800d628: 4628 mov r0, r5 + 800d62a: 47b0 blx r6 + 800d62c: 1c43 adds r3, r0, #1 + 800d62e: 89a3 ldrh r3, [r4, #12] + 800d630: d106 bne.n 800d640 <__sflush_r+0x64> + 800d632: 6829 ldr r1, [r5, #0] + 800d634: 291d cmp r1, #29 + 800d636: d82b bhi.n 800d690 <__sflush_r+0xb4> + 800d638: 4a28 ldr r2, [pc, #160] ; (800d6dc <__sflush_r+0x100>) + 800d63a: 410a asrs r2, r1 + 800d63c: 07d6 lsls r6, r2, #31 + 800d63e: d427 bmi.n 800d690 <__sflush_r+0xb4> + 800d640: 2200 movs r2, #0 + 800d642: 6062 str r2, [r4, #4] + 800d644: 04d9 lsls r1, r3, #19 + 800d646: 6922 ldr r2, [r4, #16] + 800d648: 6022 str r2, [r4, #0] + 800d64a: d504 bpl.n 800d656 <__sflush_r+0x7a> + 800d64c: 1c42 adds r2, r0, #1 + 800d64e: d101 bne.n 800d654 <__sflush_r+0x78> + 800d650: 682b ldr r3, [r5, #0] + 800d652: b903 cbnz r3, 800d656 <__sflush_r+0x7a> + 800d654: 6560 str r0, [r4, #84] ; 0x54 + 800d656: 6b61 ldr r1, [r4, #52] ; 0x34 + 800d658: 602f str r7, [r5, #0] + 800d65a: 2900 cmp r1, #0 + 800d65c: d0ca beq.n 800d5f4 <__sflush_r+0x18> + 800d65e: f104 0344 add.w r3, r4, #68 ; 0x44 + 800d662: 4299 cmp r1, r3 + 800d664: d002 beq.n 800d66c <__sflush_r+0x90> + 800d666: 4628 mov r0, r5 + 800d668: f7ff feba bl 800d3e0 <_free_r> + 800d66c: 2000 movs r0, #0 + 800d66e: 6360 str r0, [r4, #52] ; 0x34 + 800d670: e7c1 b.n 800d5f6 <__sflush_r+0x1a> + 800d672: 2301 movs r3, #1 + 800d674: 4628 mov r0, r5 + 800d676: 47b0 blx r6 + 800d678: 1c41 adds r1, r0, #1 + 800d67a: d1c8 bne.n 800d60e <__sflush_r+0x32> + 800d67c: 682b ldr r3, [r5, #0] + 800d67e: 2b00 cmp r3, #0 + 800d680: d0c5 beq.n 800d60e <__sflush_r+0x32> + 800d682: 2b1d cmp r3, #29 + 800d684: d001 beq.n 800d68a <__sflush_r+0xae> + 800d686: 2b16 cmp r3, #22 + 800d688: d101 bne.n 800d68e <__sflush_r+0xb2> + 800d68a: 602f str r7, [r5, #0] + 800d68c: e7b2 b.n 800d5f4 <__sflush_r+0x18> + 800d68e: 89a3 ldrh r3, [r4, #12] + 800d690: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800d694: 81a3 strh r3, [r4, #12] + 800d696: e7ae b.n 800d5f6 <__sflush_r+0x1a> + 800d698: 690f ldr r7, [r1, #16] + 800d69a: 2f00 cmp r7, #0 + 800d69c: d0aa beq.n 800d5f4 <__sflush_r+0x18> + 800d69e: 0793 lsls r3, r2, #30 + 800d6a0: 680e ldr r6, [r1, #0] + 800d6a2: bf08 it eq + 800d6a4: 694b ldreq r3, [r1, #20] + 800d6a6: 600f str r7, [r1, #0] + 800d6a8: bf18 it ne + 800d6aa: 2300 movne r3, #0 + 800d6ac: 1bf6 subs r6, r6, r7 + 800d6ae: 608b str r3, [r1, #8] + 800d6b0: 2e00 cmp r6, #0 + 800d6b2: dd9f ble.n 800d5f4 <__sflush_r+0x18> + 800d6b4: 6a21 ldr r1, [r4, #32] + 800d6b6: f8d4 c028 ldr.w ip, [r4, #40] ; 0x28 + 800d6ba: 4633 mov r3, r6 + 800d6bc: 463a mov r2, r7 + 800d6be: 4628 mov r0, r5 + 800d6c0: 47e0 blx ip + 800d6c2: 2800 cmp r0, #0 + 800d6c4: dc06 bgt.n 800d6d4 <__sflush_r+0xf8> + 800d6c6: 89a3 ldrh r3, [r4, #12] + 800d6c8: f043 0340 orr.w r3, r3, #64 ; 0x40 + 800d6cc: 81a3 strh r3, [r4, #12] + 800d6ce: f04f 30ff mov.w r0, #4294967295 + 800d6d2: e790 b.n 800d5f6 <__sflush_r+0x1a> + 800d6d4: 4407 add r7, r0 + 800d6d6: 1a36 subs r6, r6, r0 + 800d6d8: e7ea b.n 800d6b0 <__sflush_r+0xd4> + 800d6da: bf00 nop + 800d6dc: dfbffffe .word 0xdfbffffe + +0800d6e0 <_fflush_r>: + 800d6e0: b538 push {r3, r4, r5, lr} + 800d6e2: 690b ldr r3, [r1, #16] + 800d6e4: 4605 mov r5, r0 + 800d6e6: 460c mov r4, r1 + 800d6e8: b913 cbnz r3, 800d6f0 <_fflush_r+0x10> + 800d6ea: 2500 movs r5, #0 + 800d6ec: 4628 mov r0, r5 + 800d6ee: bd38 pop {r3, r4, r5, pc} + 800d6f0: b118 cbz r0, 800d6fa <_fflush_r+0x1a> + 800d6f2: 6a03 ldr r3, [r0, #32] + 800d6f4: b90b cbnz r3, 800d6fa <_fflush_r+0x1a> + 800d6f6: f7ff fcdf bl 800d0b8 <__sinit> + 800d6fa: f9b4 300c ldrsh.w r3, [r4, #12] + 800d6fe: 2b00 cmp r3, #0 + 800d700: d0f3 beq.n 800d6ea <_fflush_r+0xa> + 800d702: 6e62 ldr r2, [r4, #100] ; 0x64 + 800d704: 07d0 lsls r0, r2, #31 + 800d706: d404 bmi.n 800d712 <_fflush_r+0x32> + 800d708: 0599 lsls r1, r3, #22 + 800d70a: d402 bmi.n 800d712 <_fflush_r+0x32> + 800d70c: 6da0 ldr r0, [r4, #88] ; 0x58 + 800d70e: f7ff fe38 bl 800d382 <__retarget_lock_acquire_recursive> + 800d712: 4628 mov r0, r5 + 800d714: 4621 mov r1, r4 + 800d716: f7ff ff61 bl 800d5dc <__sflush_r> + 800d71a: 6e63 ldr r3, [r4, #100] ; 0x64 + 800d71c: 07da lsls r2, r3, #31 + 800d71e: 4605 mov r5, r0 + 800d720: d4e4 bmi.n 800d6ec <_fflush_r+0xc> + 800d722: 89a3 ldrh r3, [r4, #12] + 800d724: 059b lsls r3, r3, #22 + 800d726: d4e1 bmi.n 800d6ec <_fflush_r+0xc> + 800d728: 6da0 ldr r0, [r4, #88] ; 0x58 + 800d72a: f7ff fe2b bl 800d384 <__retarget_lock_release_recursive> + 800d72e: e7dd b.n 800d6ec <_fflush_r+0xc> + +0800d730 : + 800d730: b40e push {r1, r2, r3} + 800d732: b503 push {r0, r1, lr} + 800d734: 4601 mov r1, r0 + 800d736: ab03 add r3, sp, #12 + 800d738: 4805 ldr r0, [pc, #20] ; (800d750 ) + 800d73a: f853 2b04 ldr.w r2, [r3], #4 + 800d73e: 6800 ldr r0, [r0, #0] + 800d740: 9301 str r3, [sp, #4] + 800d742: f000 f845 bl 800d7d0 <_vfiprintf_r> + 800d746: b002 add sp, #8 + 800d748: f85d eb04 ldr.w lr, [sp], #4 + 800d74c: b003 add sp, #12 + 800d74e: 4770 bx lr + 800d750: 2000008c .word 0x2000008c + +0800d754 <_sbrk_r>: + 800d754: b538 push {r3, r4, r5, lr} + 800d756: 4d06 ldr r5, [pc, #24] ; (800d770 <_sbrk_r+0x1c>) + 800d758: 2300 movs r3, #0 + 800d75a: 4604 mov r4, r0 + 800d75c: 4608 mov r0, r1 + 800d75e: 602b str r3, [r5, #0] + 800d760: f7f3 fba8 bl 8000eb4 <_sbrk> + 800d764: 1c43 adds r3, r0, #1 + 800d766: d102 bne.n 800d76e <_sbrk_r+0x1a> + 800d768: 682b ldr r3, [r5, #0] + 800d76a: b103 cbz r3, 800d76e <_sbrk_r+0x1a> + 800d76c: 6023 str r3, [r4, #0] + 800d76e: bd38 pop {r3, r4, r5, pc} + 800d770: 20000a38 .word 0x20000a38 + +0800d774 : + 800d774: b508 push {r3, lr} + 800d776: 2006 movs r0, #6 + 800d778: f000 fb92 bl 800dea0 + 800d77c: 2001 movs r0, #1 + 800d77e: f7f3 fb26 bl 8000dce <_exit> + +0800d782 <__sfputc_r>: + 800d782: 6893 ldr r3, [r2, #8] + 800d784: 3b01 subs r3, #1 + 800d786: 2b00 cmp r3, #0 + 800d788: b410 push {r4} + 800d78a: 6093 str r3, [r2, #8] + 800d78c: da07 bge.n 800d79e <__sfputc_r+0x1c> + 800d78e: 6994 ldr r4, [r2, #24] + 800d790: 42a3 cmp r3, r4 + 800d792: db01 blt.n 800d798 <__sfputc_r+0x16> + 800d794: 290a cmp r1, #10 + 800d796: d102 bne.n 800d79e <__sfputc_r+0x1c> + 800d798: bc10 pop {r4} + 800d79a: f000 bac3 b.w 800dd24 <__swbuf_r> + 800d79e: 6813 ldr r3, [r2, #0] + 800d7a0: 1c58 adds r0, r3, #1 + 800d7a2: 6010 str r0, [r2, #0] + 800d7a4: 7019 strb r1, [r3, #0] + 800d7a6: 4608 mov r0, r1 + 800d7a8: bc10 pop {r4} + 800d7aa: 4770 bx lr + +0800d7ac <__sfputs_r>: + 800d7ac: b5f8 push {r3, r4, r5, r6, r7, lr} + 800d7ae: 4606 mov r6, r0 + 800d7b0: 460f mov r7, r1 + 800d7b2: 4614 mov r4, r2 + 800d7b4: 18d5 adds r5, r2, r3 + 800d7b6: 42ac cmp r4, r5 + 800d7b8: d101 bne.n 800d7be <__sfputs_r+0x12> + 800d7ba: 2000 movs r0, #0 + 800d7bc: e007 b.n 800d7ce <__sfputs_r+0x22> + 800d7be: f814 1b01 ldrb.w r1, [r4], #1 + 800d7c2: 463a mov r2, r7 + 800d7c4: 4630 mov r0, r6 + 800d7c6: f7ff ffdc bl 800d782 <__sfputc_r> + 800d7ca: 1c43 adds r3, r0, #1 + 800d7cc: d1f3 bne.n 800d7b6 <__sfputs_r+0xa> + 800d7ce: bdf8 pop {r3, r4, r5, r6, r7, pc} + +0800d7d0 <_vfiprintf_r>: + 800d7d0: e92d 4ff0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, fp, lr} + 800d7d4: 460d mov r5, r1 + 800d7d6: b09d sub sp, #116 ; 0x74 + 800d7d8: 4614 mov r4, r2 + 800d7da: 4698 mov r8, r3 + 800d7dc: 4606 mov r6, r0 + 800d7de: b118 cbz r0, 800d7e8 <_vfiprintf_r+0x18> + 800d7e0: 6a03 ldr r3, [r0, #32] + 800d7e2: b90b cbnz r3, 800d7e8 <_vfiprintf_r+0x18> + 800d7e4: f7ff fc68 bl 800d0b8 <__sinit> + 800d7e8: 6e6b ldr r3, [r5, #100] ; 0x64 + 800d7ea: 07d9 lsls r1, r3, #31 + 800d7ec: d405 bmi.n 800d7fa <_vfiprintf_r+0x2a> + 800d7ee: 89ab ldrh r3, [r5, #12] + 800d7f0: 059a lsls r2, r3, #22 + 800d7f2: d402 bmi.n 800d7fa <_vfiprintf_r+0x2a> + 800d7f4: 6da8 ldr r0, [r5, #88] ; 0x58 + 800d7f6: f7ff fdc4 bl 800d382 <__retarget_lock_acquire_recursive> + 800d7fa: 89ab ldrh r3, [r5, #12] + 800d7fc: 071b lsls r3, r3, #28 + 800d7fe: d501 bpl.n 800d804 <_vfiprintf_r+0x34> + 800d800: 692b ldr r3, [r5, #16] + 800d802: b99b cbnz r3, 800d82c <_vfiprintf_r+0x5c> + 800d804: 4629 mov r1, r5 + 800d806: 4630 mov r0, r6 + 800d808: f000 faca bl 800dda0 <__swsetup_r> + 800d80c: b170 cbz r0, 800d82c <_vfiprintf_r+0x5c> + 800d80e: 6e6b ldr r3, [r5, #100] ; 0x64 + 800d810: 07dc lsls r4, r3, #31 + 800d812: d504 bpl.n 800d81e <_vfiprintf_r+0x4e> + 800d814: f04f 30ff mov.w r0, #4294967295 + 800d818: b01d add sp, #116 ; 0x74 + 800d81a: e8bd 8ff0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, fp, pc} + 800d81e: 89ab ldrh r3, [r5, #12] + 800d820: 0598 lsls r0, r3, #22 + 800d822: d4f7 bmi.n 800d814 <_vfiprintf_r+0x44> + 800d824: 6da8 ldr r0, [r5, #88] ; 0x58 + 800d826: f7ff fdad bl 800d384 <__retarget_lock_release_recursive> + 800d82a: e7f3 b.n 800d814 <_vfiprintf_r+0x44> + 800d82c: 2300 movs r3, #0 + 800d82e: 9309 str r3, [sp, #36] ; 0x24 + 800d830: 2320 movs r3, #32 + 800d832: f88d 3029 strb.w r3, [sp, #41] ; 0x29 + 800d836: f8cd 800c str.w r8, [sp, #12] + 800d83a: 2330 movs r3, #48 ; 0x30 + 800d83c: f8df 81b0 ldr.w r8, [pc, #432] ; 800d9f0 <_vfiprintf_r+0x220> + 800d840: f88d 302a strb.w r3, [sp, #42] ; 0x2a + 800d844: f04f 0901 mov.w r9, #1 + 800d848: 4623 mov r3, r4 + 800d84a: 469a mov sl, r3 + 800d84c: f813 2b01 ldrb.w r2, [r3], #1 + 800d850: b10a cbz r2, 800d856 <_vfiprintf_r+0x86> + 800d852: 2a25 cmp r2, #37 ; 0x25 + 800d854: d1f9 bne.n 800d84a <_vfiprintf_r+0x7a> + 800d856: ebba 0b04 subs.w fp, sl, r4 + 800d85a: d00b beq.n 800d874 <_vfiprintf_r+0xa4> + 800d85c: 465b mov r3, fp + 800d85e: 4622 mov r2, r4 + 800d860: 4629 mov r1, r5 + 800d862: 4630 mov r0, r6 + 800d864: f7ff ffa2 bl 800d7ac <__sfputs_r> + 800d868: 3001 adds r0, #1 + 800d86a: f000 80a9 beq.w 800d9c0 <_vfiprintf_r+0x1f0> + 800d86e: 9a09 ldr r2, [sp, #36] ; 0x24 + 800d870: 445a add r2, fp + 800d872: 9209 str r2, [sp, #36] ; 0x24 + 800d874: f89a 3000 ldrb.w r3, [sl] + 800d878: 2b00 cmp r3, #0 + 800d87a: f000 80a1 beq.w 800d9c0 <_vfiprintf_r+0x1f0> + 800d87e: 2300 movs r3, #0 + 800d880: f04f 32ff mov.w r2, #4294967295 + 800d884: e9cd 2305 strd r2, r3, [sp, #20] + 800d888: f10a 0a01 add.w sl, sl, #1 + 800d88c: 9304 str r3, [sp, #16] + 800d88e: 9307 str r3, [sp, #28] + 800d890: f88d 3053 strb.w r3, [sp, #83] ; 0x53 + 800d894: 931a str r3, [sp, #104] ; 0x68 + 800d896: 4654 mov r4, sl + 800d898: 2205 movs r2, #5 + 800d89a: f814 1b01 ldrb.w r1, [r4], #1 + 800d89e: 4854 ldr r0, [pc, #336] ; (800d9f0 <_vfiprintf_r+0x220>) + 800d8a0: f7f2 fc76 bl 8000190 + 800d8a4: 9a04 ldr r2, [sp, #16] + 800d8a6: b9d8 cbnz r0, 800d8e0 <_vfiprintf_r+0x110> + 800d8a8: 06d1 lsls r1, r2, #27 + 800d8aa: bf44 itt mi + 800d8ac: 2320 movmi r3, #32 + 800d8ae: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 800d8b2: 0713 lsls r3, r2, #28 + 800d8b4: bf44 itt mi + 800d8b6: 232b movmi r3, #43 ; 0x2b + 800d8b8: f88d 3053 strbmi.w r3, [sp, #83] ; 0x53 + 800d8bc: f89a 3000 ldrb.w r3, [sl] + 800d8c0: 2b2a cmp r3, #42 ; 0x2a + 800d8c2: d015 beq.n 800d8f0 <_vfiprintf_r+0x120> + 800d8c4: 9a07 ldr r2, [sp, #28] + 800d8c6: 4654 mov r4, sl + 800d8c8: 2000 movs r0, #0 + 800d8ca: f04f 0c0a mov.w ip, #10 + 800d8ce: 4621 mov r1, r4 + 800d8d0: f811 3b01 ldrb.w r3, [r1], #1 + 800d8d4: 3b30 subs r3, #48 ; 0x30 + 800d8d6: 2b09 cmp r3, #9 + 800d8d8: d94d bls.n 800d976 <_vfiprintf_r+0x1a6> + 800d8da: b1b0 cbz r0, 800d90a <_vfiprintf_r+0x13a> + 800d8dc: 9207 str r2, [sp, #28] + 800d8de: e014 b.n 800d90a <_vfiprintf_r+0x13a> + 800d8e0: eba0 0308 sub.w r3, r0, r8 + 800d8e4: fa09 f303 lsl.w r3, r9, r3 + 800d8e8: 4313 orrs r3, r2 + 800d8ea: 9304 str r3, [sp, #16] + 800d8ec: 46a2 mov sl, r4 + 800d8ee: e7d2 b.n 800d896 <_vfiprintf_r+0xc6> + 800d8f0: 9b03 ldr r3, [sp, #12] + 800d8f2: 1d19 adds r1, r3, #4 + 800d8f4: 681b ldr r3, [r3, #0] + 800d8f6: 9103 str r1, [sp, #12] + 800d8f8: 2b00 cmp r3, #0 + 800d8fa: bfbb ittet lt + 800d8fc: 425b neglt r3, r3 + 800d8fe: f042 0202 orrlt.w r2, r2, #2 + 800d902: 9307 strge r3, [sp, #28] + 800d904: 9307 strlt r3, [sp, #28] + 800d906: bfb8 it lt + 800d908: 9204 strlt r2, [sp, #16] + 800d90a: 7823 ldrb r3, [r4, #0] + 800d90c: 2b2e cmp r3, #46 ; 0x2e + 800d90e: d10c bne.n 800d92a <_vfiprintf_r+0x15a> + 800d910: 7863 ldrb r3, [r4, #1] + 800d912: 2b2a cmp r3, #42 ; 0x2a + 800d914: d134 bne.n 800d980 <_vfiprintf_r+0x1b0> + 800d916: 9b03 ldr r3, [sp, #12] + 800d918: 1d1a adds r2, r3, #4 + 800d91a: 681b ldr r3, [r3, #0] + 800d91c: 9203 str r2, [sp, #12] + 800d91e: 2b00 cmp r3, #0 + 800d920: bfb8 it lt + 800d922: f04f 33ff movlt.w r3, #4294967295 + 800d926: 3402 adds r4, #2 + 800d928: 9305 str r3, [sp, #20] + 800d92a: f8df a0c8 ldr.w sl, [pc, #200] ; 800d9f4 <_vfiprintf_r+0x224> + 800d92e: 7821 ldrb r1, [r4, #0] + 800d930: 2203 movs r2, #3 + 800d932: 4650 mov r0, sl + 800d934: f7f2 fc2c bl 8000190 + 800d938: b138 cbz r0, 800d94a <_vfiprintf_r+0x17a> + 800d93a: 9b04 ldr r3, [sp, #16] + 800d93c: eba0 000a sub.w r0, r0, sl + 800d940: 2240 movs r2, #64 ; 0x40 + 800d942: 4082 lsls r2, r0 + 800d944: 4313 orrs r3, r2 + 800d946: 3401 adds r4, #1 + 800d948: 9304 str r3, [sp, #16] + 800d94a: f814 1b01 ldrb.w r1, [r4], #1 + 800d94e: 482a ldr r0, [pc, #168] ; (800d9f8 <_vfiprintf_r+0x228>) + 800d950: f88d 1028 strb.w r1, [sp, #40] ; 0x28 + 800d954: 2206 movs r2, #6 + 800d956: f7f2 fc1b bl 8000190 + 800d95a: 2800 cmp r0, #0 + 800d95c: d03f beq.n 800d9de <_vfiprintf_r+0x20e> + 800d95e: 4b27 ldr r3, [pc, #156] ; (800d9fc <_vfiprintf_r+0x22c>) + 800d960: bb1b cbnz r3, 800d9aa <_vfiprintf_r+0x1da> + 800d962: 9b03 ldr r3, [sp, #12] + 800d964: 3307 adds r3, #7 + 800d966: f023 0307 bic.w r3, r3, #7 + 800d96a: 3308 adds r3, #8 + 800d96c: 9303 str r3, [sp, #12] + 800d96e: 9b09 ldr r3, [sp, #36] ; 0x24 + 800d970: 443b add r3, r7 + 800d972: 9309 str r3, [sp, #36] ; 0x24 + 800d974: e768 b.n 800d848 <_vfiprintf_r+0x78> + 800d976: fb0c 3202 mla r2, ip, r2, r3 + 800d97a: 460c mov r4, r1 + 800d97c: 2001 movs r0, #1 + 800d97e: e7a6 b.n 800d8ce <_vfiprintf_r+0xfe> + 800d980: 2300 movs r3, #0 + 800d982: 3401 adds r4, #1 + 800d984: 9305 str r3, [sp, #20] + 800d986: 4619 mov r1, r3 + 800d988: f04f 0c0a mov.w ip, #10 + 800d98c: 4620 mov r0, r4 + 800d98e: f810 2b01 ldrb.w r2, [r0], #1 + 800d992: 3a30 subs r2, #48 ; 0x30 + 800d994: 2a09 cmp r2, #9 + 800d996: d903 bls.n 800d9a0 <_vfiprintf_r+0x1d0> + 800d998: 2b00 cmp r3, #0 + 800d99a: d0c6 beq.n 800d92a <_vfiprintf_r+0x15a> + 800d99c: 9105 str r1, [sp, #20] + 800d99e: e7c4 b.n 800d92a <_vfiprintf_r+0x15a> + 800d9a0: fb0c 2101 mla r1, ip, r1, r2 + 800d9a4: 4604 mov r4, r0 + 800d9a6: 2301 movs r3, #1 + 800d9a8: e7f0 b.n 800d98c <_vfiprintf_r+0x1bc> + 800d9aa: ab03 add r3, sp, #12 + 800d9ac: 9300 str r3, [sp, #0] + 800d9ae: 462a mov r2, r5 + 800d9b0: 4b13 ldr r3, [pc, #76] ; (800da00 <_vfiprintf_r+0x230>) + 800d9b2: a904 add r1, sp, #16 + 800d9b4: 4630 mov r0, r6 + 800d9b6: f3af 8000 nop.w + 800d9ba: 4607 mov r7, r0 + 800d9bc: 1c78 adds r0, r7, #1 + 800d9be: d1d6 bne.n 800d96e <_vfiprintf_r+0x19e> + 800d9c0: 6e6b ldr r3, [r5, #100] ; 0x64 + 800d9c2: 07d9 lsls r1, r3, #31 + 800d9c4: d405 bmi.n 800d9d2 <_vfiprintf_r+0x202> + 800d9c6: 89ab ldrh r3, [r5, #12] + 800d9c8: 059a lsls r2, r3, #22 + 800d9ca: d402 bmi.n 800d9d2 <_vfiprintf_r+0x202> + 800d9cc: 6da8 ldr r0, [r5, #88] ; 0x58 + 800d9ce: f7ff fcd9 bl 800d384 <__retarget_lock_release_recursive> + 800d9d2: 89ab ldrh r3, [r5, #12] + 800d9d4: 065b lsls r3, r3, #25 + 800d9d6: f53f af1d bmi.w 800d814 <_vfiprintf_r+0x44> + 800d9da: 9809 ldr r0, [sp, #36] ; 0x24 + 800d9dc: e71c b.n 800d818 <_vfiprintf_r+0x48> + 800d9de: ab03 add r3, sp, #12 + 800d9e0: 9300 str r3, [sp, #0] + 800d9e2: 462a mov r2, r5 + 800d9e4: 4b06 ldr r3, [pc, #24] ; (800da00 <_vfiprintf_r+0x230>) + 800d9e6: a904 add r1, sp, #16 + 800d9e8: 4630 mov r0, r6 + 800d9ea: f000 f879 bl 800dae0 <_printf_i> + 800d9ee: e7e4 b.n 800d9ba <_vfiprintf_r+0x1ea> + 800d9f0: 0800e601 .word 0x0800e601 + 800d9f4: 0800e607 .word 0x0800e607 + 800d9f8: 0800e60b .word 0x0800e60b + 800d9fc: 00000000 .word 0x00000000 + 800da00: 0800d7ad .word 0x0800d7ad + +0800da04 <_printf_common>: + 800da04: e92d 47f0 stmdb sp!, {r4, r5, r6, r7, r8, r9, sl, lr} + 800da08: 4616 mov r6, r2 + 800da0a: 4699 mov r9, r3 + 800da0c: 688a ldr r2, [r1, #8] + 800da0e: 690b ldr r3, [r1, #16] + 800da10: f8dd 8020 ldr.w r8, [sp, #32] + 800da14: 4293 cmp r3, r2 + 800da16: bfb8 it lt + 800da18: 4613 movlt r3, r2 + 800da1a: 6033 str r3, [r6, #0] + 800da1c: f891 2043 ldrb.w r2, [r1, #67] ; 0x43 + 800da20: 4607 mov r7, r0 + 800da22: 460c mov r4, r1 + 800da24: b10a cbz r2, 800da2a <_printf_common+0x26> + 800da26: 3301 adds r3, #1 + 800da28: 6033 str r3, [r6, #0] + 800da2a: 6823 ldr r3, [r4, #0] + 800da2c: 0699 lsls r1, r3, #26 + 800da2e: bf42 ittt mi + 800da30: 6833 ldrmi r3, [r6, #0] + 800da32: 3302 addmi r3, #2 + 800da34: 6033 strmi r3, [r6, #0] + 800da36: 6825 ldr r5, [r4, #0] + 800da38: f015 0506 ands.w r5, r5, #6 + 800da3c: d106 bne.n 800da4c <_printf_common+0x48> + 800da3e: f104 0a19 add.w sl, r4, #25 + 800da42: 68e3 ldr r3, [r4, #12] + 800da44: 6832 ldr r2, [r6, #0] + 800da46: 1a9b subs r3, r3, r2 + 800da48: 42ab cmp r3, r5 + 800da4a: dc26 bgt.n 800da9a <_printf_common+0x96> + 800da4c: f894 2043 ldrb.w r2, [r4, #67] ; 0x43 + 800da50: 1e13 subs r3, r2, #0 + 800da52: 6822 ldr r2, [r4, #0] + 800da54: bf18 it ne + 800da56: 2301 movne r3, #1 + 800da58: 0692 lsls r2, r2, #26 + 800da5a: d42b bmi.n 800dab4 <_printf_common+0xb0> + 800da5c: f104 0243 add.w r2, r4, #67 ; 0x43 + 800da60: 4649 mov r1, r9 + 800da62: 4638 mov r0, r7 + 800da64: 47c0 blx r8 + 800da66: 3001 adds r0, #1 + 800da68: d01e beq.n 800daa8 <_printf_common+0xa4> + 800da6a: 6823 ldr r3, [r4, #0] + 800da6c: 6922 ldr r2, [r4, #16] + 800da6e: f003 0306 and.w r3, r3, #6 + 800da72: 2b04 cmp r3, #4 + 800da74: bf02 ittt eq + 800da76: 68e5 ldreq r5, [r4, #12] + 800da78: 6833 ldreq r3, [r6, #0] + 800da7a: 1aed subeq r5, r5, r3 + 800da7c: 68a3 ldr r3, [r4, #8] + 800da7e: bf0c ite eq + 800da80: ea25 75e5 biceq.w r5, r5, r5, asr #31 + 800da84: 2500 movne r5, #0 + 800da86: 4293 cmp r3, r2 + 800da88: bfc4 itt gt + 800da8a: 1a9b subgt r3, r3, r2 + 800da8c: 18ed addgt r5, r5, r3 + 800da8e: 2600 movs r6, #0 + 800da90: 341a adds r4, #26 + 800da92: 42b5 cmp r5, r6 + 800da94: d11a bne.n 800dacc <_printf_common+0xc8> + 800da96: 2000 movs r0, #0 + 800da98: e008 b.n 800daac <_printf_common+0xa8> + 800da9a: 2301 movs r3, #1 + 800da9c: 4652 mov r2, sl + 800da9e: 4649 mov r1, r9 + 800daa0: 4638 mov r0, r7 + 800daa2: 47c0 blx r8 + 800daa4: 3001 adds r0, #1 + 800daa6: d103 bne.n 800dab0 <_printf_common+0xac> + 800daa8: f04f 30ff mov.w r0, #4294967295 + 800daac: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800dab0: 3501 adds r5, #1 + 800dab2: e7c6 b.n 800da42 <_printf_common+0x3e> + 800dab4: 18e1 adds r1, r4, r3 + 800dab6: 1c5a adds r2, r3, #1 + 800dab8: 2030 movs r0, #48 ; 0x30 + 800daba: f881 0043 strb.w r0, [r1, #67] ; 0x43 + 800dabe: 4422 add r2, r4 + 800dac0: f894 1045 ldrb.w r1, [r4, #69] ; 0x45 + 800dac4: f882 1043 strb.w r1, [r2, #67] ; 0x43 + 800dac8: 3302 adds r3, #2 + 800daca: e7c7 b.n 800da5c <_printf_common+0x58> + 800dacc: 2301 movs r3, #1 + 800dace: 4622 mov r2, r4 + 800dad0: 4649 mov r1, r9 + 800dad2: 4638 mov r0, r7 + 800dad4: 47c0 blx r8 + 800dad6: 3001 adds r0, #1 + 800dad8: d0e6 beq.n 800daa8 <_printf_common+0xa4> + 800dada: 3601 adds r6, #1 + 800dadc: e7d9 b.n 800da92 <_printf_common+0x8e> + ... + +0800dae0 <_printf_i>: + 800dae0: e92d 47ff stmdb sp!, {r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, sl, lr} + 800dae4: 7e0f ldrb r7, [r1, #24] + 800dae6: 9d0c ldr r5, [sp, #48] ; 0x30 + 800dae8: 2f78 cmp r7, #120 ; 0x78 + 800daea: 4691 mov r9, r2 + 800daec: 4680 mov r8, r0 + 800daee: 460c mov r4, r1 + 800daf0: 469a mov sl, r3 + 800daf2: f101 0243 add.w r2, r1, #67 ; 0x43 + 800daf6: d807 bhi.n 800db08 <_printf_i+0x28> + 800daf8: 2f62 cmp r7, #98 ; 0x62 + 800dafa: d80a bhi.n 800db12 <_printf_i+0x32> + 800dafc: 2f00 cmp r7, #0 + 800dafe: f000 80d4 beq.w 800dcaa <_printf_i+0x1ca> + 800db02: 2f58 cmp r7, #88 ; 0x58 + 800db04: f000 80c0 beq.w 800dc88 <_printf_i+0x1a8> + 800db08: f104 0542 add.w r5, r4, #66 ; 0x42 + 800db0c: f884 7042 strb.w r7, [r4, #66] ; 0x42 + 800db10: e03a b.n 800db88 <_printf_i+0xa8> + 800db12: f1a7 0363 sub.w r3, r7, #99 ; 0x63 + 800db16: 2b15 cmp r3, #21 + 800db18: d8f6 bhi.n 800db08 <_printf_i+0x28> + 800db1a: a101 add r1, pc, #4 ; (adr r1, 800db20 <_printf_i+0x40>) + 800db1c: f851 f023 ldr.w pc, [r1, r3, lsl #2] + 800db20: 0800db79 .word 0x0800db79 + 800db24: 0800db8d .word 0x0800db8d + 800db28: 0800db09 .word 0x0800db09 + 800db2c: 0800db09 .word 0x0800db09 + 800db30: 0800db09 .word 0x0800db09 + 800db34: 0800db09 .word 0x0800db09 + 800db38: 0800db8d .word 0x0800db8d + 800db3c: 0800db09 .word 0x0800db09 + 800db40: 0800db09 .word 0x0800db09 + 800db44: 0800db09 .word 0x0800db09 + 800db48: 0800db09 .word 0x0800db09 + 800db4c: 0800dc91 .word 0x0800dc91 + 800db50: 0800dbb9 .word 0x0800dbb9 + 800db54: 0800dc4b .word 0x0800dc4b + 800db58: 0800db09 .word 0x0800db09 + 800db5c: 0800db09 .word 0x0800db09 + 800db60: 0800dcb3 .word 0x0800dcb3 + 800db64: 0800db09 .word 0x0800db09 + 800db68: 0800dbb9 .word 0x0800dbb9 + 800db6c: 0800db09 .word 0x0800db09 + 800db70: 0800db09 .word 0x0800db09 + 800db74: 0800dc53 .word 0x0800dc53 + 800db78: 682b ldr r3, [r5, #0] + 800db7a: 1d1a adds r2, r3, #4 + 800db7c: 681b ldr r3, [r3, #0] + 800db7e: 602a str r2, [r5, #0] + 800db80: f104 0542 add.w r5, r4, #66 ; 0x42 + 800db84: f884 3042 strb.w r3, [r4, #66] ; 0x42 + 800db88: 2301 movs r3, #1 + 800db8a: e09f b.n 800dccc <_printf_i+0x1ec> + 800db8c: 6820 ldr r0, [r4, #0] + 800db8e: 682b ldr r3, [r5, #0] + 800db90: 0607 lsls r7, r0, #24 + 800db92: f103 0104 add.w r1, r3, #4 + 800db96: 6029 str r1, [r5, #0] + 800db98: d501 bpl.n 800db9e <_printf_i+0xbe> + 800db9a: 681e ldr r6, [r3, #0] + 800db9c: e003 b.n 800dba6 <_printf_i+0xc6> + 800db9e: 0646 lsls r6, r0, #25 + 800dba0: d5fb bpl.n 800db9a <_printf_i+0xba> + 800dba2: f9b3 6000 ldrsh.w r6, [r3] + 800dba6: 2e00 cmp r6, #0 + 800dba8: da03 bge.n 800dbb2 <_printf_i+0xd2> + 800dbaa: 232d movs r3, #45 ; 0x2d + 800dbac: 4276 negs r6, r6 + 800dbae: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800dbb2: 485a ldr r0, [pc, #360] ; (800dd1c <_printf_i+0x23c>) + 800dbb4: 230a movs r3, #10 + 800dbb6: e012 b.n 800dbde <_printf_i+0xfe> + 800dbb8: 682b ldr r3, [r5, #0] + 800dbba: 6820 ldr r0, [r4, #0] + 800dbbc: 1d19 adds r1, r3, #4 + 800dbbe: 6029 str r1, [r5, #0] + 800dbc0: 0605 lsls r5, r0, #24 + 800dbc2: d501 bpl.n 800dbc8 <_printf_i+0xe8> + 800dbc4: 681e ldr r6, [r3, #0] + 800dbc6: e002 b.n 800dbce <_printf_i+0xee> + 800dbc8: 0641 lsls r1, r0, #25 + 800dbca: d5fb bpl.n 800dbc4 <_printf_i+0xe4> + 800dbcc: 881e ldrh r6, [r3, #0] + 800dbce: 4853 ldr r0, [pc, #332] ; (800dd1c <_printf_i+0x23c>) + 800dbd0: 2f6f cmp r7, #111 ; 0x6f + 800dbd2: bf0c ite eq + 800dbd4: 2308 moveq r3, #8 + 800dbd6: 230a movne r3, #10 + 800dbd8: 2100 movs r1, #0 + 800dbda: f884 1043 strb.w r1, [r4, #67] ; 0x43 + 800dbde: 6865 ldr r5, [r4, #4] + 800dbe0: 60a5 str r5, [r4, #8] + 800dbe2: 2d00 cmp r5, #0 + 800dbe4: bfa2 ittt ge + 800dbe6: 6821 ldrge r1, [r4, #0] + 800dbe8: f021 0104 bicge.w r1, r1, #4 + 800dbec: 6021 strge r1, [r4, #0] + 800dbee: b90e cbnz r6, 800dbf4 <_printf_i+0x114> + 800dbf0: 2d00 cmp r5, #0 + 800dbf2: d04b beq.n 800dc8c <_printf_i+0x1ac> + 800dbf4: 4615 mov r5, r2 + 800dbf6: fbb6 f1f3 udiv r1, r6, r3 + 800dbfa: fb03 6711 mls r7, r3, r1, r6 + 800dbfe: 5dc7 ldrb r7, [r0, r7] + 800dc00: f805 7d01 strb.w r7, [r5, #-1]! + 800dc04: 4637 mov r7, r6 + 800dc06: 42bb cmp r3, r7 + 800dc08: 460e mov r6, r1 + 800dc0a: d9f4 bls.n 800dbf6 <_printf_i+0x116> + 800dc0c: 2b08 cmp r3, #8 + 800dc0e: d10b bne.n 800dc28 <_printf_i+0x148> + 800dc10: 6823 ldr r3, [r4, #0] + 800dc12: 07de lsls r6, r3, #31 + 800dc14: d508 bpl.n 800dc28 <_printf_i+0x148> + 800dc16: 6923 ldr r3, [r4, #16] + 800dc18: 6861 ldr r1, [r4, #4] + 800dc1a: 4299 cmp r1, r3 + 800dc1c: bfde ittt le + 800dc1e: 2330 movle r3, #48 ; 0x30 + 800dc20: f805 3c01 strble.w r3, [r5, #-1] + 800dc24: f105 35ff addle.w r5, r5, #4294967295 + 800dc28: 1b52 subs r2, r2, r5 + 800dc2a: 6122 str r2, [r4, #16] + 800dc2c: f8cd a000 str.w sl, [sp] + 800dc30: 464b mov r3, r9 + 800dc32: aa03 add r2, sp, #12 + 800dc34: 4621 mov r1, r4 + 800dc36: 4640 mov r0, r8 + 800dc38: f7ff fee4 bl 800da04 <_printf_common> + 800dc3c: 3001 adds r0, #1 + 800dc3e: d14a bne.n 800dcd6 <_printf_i+0x1f6> + 800dc40: f04f 30ff mov.w r0, #4294967295 + 800dc44: b004 add sp, #16 + 800dc46: e8bd 87f0 ldmia.w sp!, {r4, r5, r6, r7, r8, r9, sl, pc} + 800dc4a: 6823 ldr r3, [r4, #0] + 800dc4c: f043 0320 orr.w r3, r3, #32 + 800dc50: 6023 str r3, [r4, #0] + 800dc52: 4833 ldr r0, [pc, #204] ; (800dd20 <_printf_i+0x240>) + 800dc54: 2778 movs r7, #120 ; 0x78 + 800dc56: f884 7045 strb.w r7, [r4, #69] ; 0x45 + 800dc5a: 6823 ldr r3, [r4, #0] + 800dc5c: 6829 ldr r1, [r5, #0] + 800dc5e: 061f lsls r7, r3, #24 + 800dc60: f851 6b04 ldr.w r6, [r1], #4 + 800dc64: d402 bmi.n 800dc6c <_printf_i+0x18c> + 800dc66: 065f lsls r7, r3, #25 + 800dc68: bf48 it mi + 800dc6a: b2b6 uxthmi r6, r6 + 800dc6c: 07df lsls r7, r3, #31 + 800dc6e: bf48 it mi + 800dc70: f043 0320 orrmi.w r3, r3, #32 + 800dc74: 6029 str r1, [r5, #0] + 800dc76: bf48 it mi + 800dc78: 6023 strmi r3, [r4, #0] + 800dc7a: b91e cbnz r6, 800dc84 <_printf_i+0x1a4> + 800dc7c: 6823 ldr r3, [r4, #0] + 800dc7e: f023 0320 bic.w r3, r3, #32 + 800dc82: 6023 str r3, [r4, #0] + 800dc84: 2310 movs r3, #16 + 800dc86: e7a7 b.n 800dbd8 <_printf_i+0xf8> + 800dc88: 4824 ldr r0, [pc, #144] ; (800dd1c <_printf_i+0x23c>) + 800dc8a: e7e4 b.n 800dc56 <_printf_i+0x176> + 800dc8c: 4615 mov r5, r2 + 800dc8e: e7bd b.n 800dc0c <_printf_i+0x12c> + 800dc90: 682b ldr r3, [r5, #0] + 800dc92: 6826 ldr r6, [r4, #0] + 800dc94: 6961 ldr r1, [r4, #20] + 800dc96: 1d18 adds r0, r3, #4 + 800dc98: 6028 str r0, [r5, #0] + 800dc9a: 0635 lsls r5, r6, #24 + 800dc9c: 681b ldr r3, [r3, #0] + 800dc9e: d501 bpl.n 800dca4 <_printf_i+0x1c4> + 800dca0: 6019 str r1, [r3, #0] + 800dca2: e002 b.n 800dcaa <_printf_i+0x1ca> + 800dca4: 0670 lsls r0, r6, #25 + 800dca6: d5fb bpl.n 800dca0 <_printf_i+0x1c0> + 800dca8: 8019 strh r1, [r3, #0] + 800dcaa: 2300 movs r3, #0 + 800dcac: 6123 str r3, [r4, #16] + 800dcae: 4615 mov r5, r2 + 800dcb0: e7bc b.n 800dc2c <_printf_i+0x14c> + 800dcb2: 682b ldr r3, [r5, #0] + 800dcb4: 1d1a adds r2, r3, #4 + 800dcb6: 602a str r2, [r5, #0] + 800dcb8: 681d ldr r5, [r3, #0] + 800dcba: 6862 ldr r2, [r4, #4] + 800dcbc: 2100 movs r1, #0 + 800dcbe: 4628 mov r0, r5 + 800dcc0: f7f2 fa66 bl 8000190 + 800dcc4: b108 cbz r0, 800dcca <_printf_i+0x1ea> + 800dcc6: 1b40 subs r0, r0, r5 + 800dcc8: 6060 str r0, [r4, #4] + 800dcca: 6863 ldr r3, [r4, #4] + 800dccc: 6123 str r3, [r4, #16] + 800dcce: 2300 movs r3, #0 + 800dcd0: f884 3043 strb.w r3, [r4, #67] ; 0x43 + 800dcd4: e7aa b.n 800dc2c <_printf_i+0x14c> + 800dcd6: 6923 ldr r3, [r4, #16] + 800dcd8: 462a mov r2, r5 + 800dcda: 4649 mov r1, r9 + 800dcdc: 4640 mov r0, r8 + 800dcde: 47d0 blx sl + 800dce0: 3001 adds r0, #1 + 800dce2: d0ad beq.n 800dc40 <_printf_i+0x160> + 800dce4: 6823 ldr r3, [r4, #0] + 800dce6: 079b lsls r3, r3, #30 + 800dce8: d413 bmi.n 800dd12 <_printf_i+0x232> + 800dcea: 68e0 ldr r0, [r4, #12] + 800dcec: 9b03 ldr r3, [sp, #12] + 800dcee: 4298 cmp r0, r3 + 800dcf0: bfb8 it lt + 800dcf2: 4618 movlt r0, r3 + 800dcf4: e7a6 b.n 800dc44 <_printf_i+0x164> + 800dcf6: 2301 movs r3, #1 + 800dcf8: 4632 mov r2, r6 + 800dcfa: 4649 mov r1, r9 + 800dcfc: 4640 mov r0, r8 + 800dcfe: 47d0 blx sl + 800dd00: 3001 adds r0, #1 + 800dd02: d09d beq.n 800dc40 <_printf_i+0x160> + 800dd04: 3501 adds r5, #1 + 800dd06: 68e3 ldr r3, [r4, #12] + 800dd08: 9903 ldr r1, [sp, #12] + 800dd0a: 1a5b subs r3, r3, r1 + 800dd0c: 42ab cmp r3, r5 + 800dd0e: dcf2 bgt.n 800dcf6 <_printf_i+0x216> + 800dd10: e7eb b.n 800dcea <_printf_i+0x20a> + 800dd12: 2500 movs r5, #0 + 800dd14: f104 0619 add.w r6, r4, #25 + 800dd18: e7f5 b.n 800dd06 <_printf_i+0x226> + 800dd1a: bf00 nop + 800dd1c: 0800e612 .word 0x0800e612 + 800dd20: 0800e623 .word 0x0800e623 + +0800dd24 <__swbuf_r>: + 800dd24: b5f8 push {r3, r4, r5, r6, r7, lr} + 800dd26: 460e mov r6, r1 + 800dd28: 4614 mov r4, r2 + 800dd2a: 4605 mov r5, r0 + 800dd2c: b118 cbz r0, 800dd36 <__swbuf_r+0x12> + 800dd2e: 6a03 ldr r3, [r0, #32] + 800dd30: b90b cbnz r3, 800dd36 <__swbuf_r+0x12> + 800dd32: f7ff f9c1 bl 800d0b8 <__sinit> + 800dd36: 69a3 ldr r3, [r4, #24] + 800dd38: 60a3 str r3, [r4, #8] + 800dd3a: 89a3 ldrh r3, [r4, #12] + 800dd3c: 071a lsls r2, r3, #28 + 800dd3e: d525 bpl.n 800dd8c <__swbuf_r+0x68> + 800dd40: 6923 ldr r3, [r4, #16] + 800dd42: b31b cbz r3, 800dd8c <__swbuf_r+0x68> + 800dd44: 6823 ldr r3, [r4, #0] + 800dd46: 6922 ldr r2, [r4, #16] + 800dd48: 1a98 subs r0, r3, r2 + 800dd4a: 6963 ldr r3, [r4, #20] + 800dd4c: b2f6 uxtb r6, r6 + 800dd4e: 4283 cmp r3, r0 + 800dd50: 4637 mov r7, r6 + 800dd52: dc04 bgt.n 800dd5e <__swbuf_r+0x3a> + 800dd54: 4621 mov r1, r4 + 800dd56: 4628 mov r0, r5 + 800dd58: f7ff fcc2 bl 800d6e0 <_fflush_r> + 800dd5c: b9e0 cbnz r0, 800dd98 <__swbuf_r+0x74> + 800dd5e: 68a3 ldr r3, [r4, #8] + 800dd60: 3b01 subs r3, #1 + 800dd62: 60a3 str r3, [r4, #8] + 800dd64: 6823 ldr r3, [r4, #0] + 800dd66: 1c5a adds r2, r3, #1 + 800dd68: 6022 str r2, [r4, #0] + 800dd6a: 701e strb r6, [r3, #0] + 800dd6c: 6962 ldr r2, [r4, #20] + 800dd6e: 1c43 adds r3, r0, #1 + 800dd70: 429a cmp r2, r3 + 800dd72: d004 beq.n 800dd7e <__swbuf_r+0x5a> + 800dd74: 89a3 ldrh r3, [r4, #12] + 800dd76: 07db lsls r3, r3, #31 + 800dd78: d506 bpl.n 800dd88 <__swbuf_r+0x64> + 800dd7a: 2e0a cmp r6, #10 + 800dd7c: d104 bne.n 800dd88 <__swbuf_r+0x64> + 800dd7e: 4621 mov r1, r4 + 800dd80: 4628 mov r0, r5 + 800dd82: f7ff fcad bl 800d6e0 <_fflush_r> + 800dd86: b938 cbnz r0, 800dd98 <__swbuf_r+0x74> + 800dd88: 4638 mov r0, r7 + 800dd8a: bdf8 pop {r3, r4, r5, r6, r7, pc} + 800dd8c: 4621 mov r1, r4 + 800dd8e: 4628 mov r0, r5 + 800dd90: f000 f806 bl 800dda0 <__swsetup_r> + 800dd94: 2800 cmp r0, #0 + 800dd96: d0d5 beq.n 800dd44 <__swbuf_r+0x20> + 800dd98: f04f 37ff mov.w r7, #4294967295 + 800dd9c: e7f4 b.n 800dd88 <__swbuf_r+0x64> + ... + +0800dda0 <__swsetup_r>: + 800dda0: b538 push {r3, r4, r5, lr} + 800dda2: 4b2a ldr r3, [pc, #168] ; (800de4c <__swsetup_r+0xac>) + 800dda4: 4605 mov r5, r0 + 800dda6: 6818 ldr r0, [r3, #0] + 800dda8: 460c mov r4, r1 + 800ddaa: b118 cbz r0, 800ddb4 <__swsetup_r+0x14> + 800ddac: 6a03 ldr r3, [r0, #32] + 800ddae: b90b cbnz r3, 800ddb4 <__swsetup_r+0x14> + 800ddb0: f7ff f982 bl 800d0b8 <__sinit> + 800ddb4: 89a3 ldrh r3, [r4, #12] + 800ddb6: f9b4 200c ldrsh.w r2, [r4, #12] + 800ddba: 0718 lsls r0, r3, #28 + 800ddbc: d422 bmi.n 800de04 <__swsetup_r+0x64> + 800ddbe: 06d9 lsls r1, r3, #27 + 800ddc0: d407 bmi.n 800ddd2 <__swsetup_r+0x32> + 800ddc2: 2309 movs r3, #9 + 800ddc4: 602b str r3, [r5, #0] + 800ddc6: f042 0340 orr.w r3, r2, #64 ; 0x40 + 800ddca: 81a3 strh r3, [r4, #12] + 800ddcc: f04f 30ff mov.w r0, #4294967295 + 800ddd0: e034 b.n 800de3c <__swsetup_r+0x9c> + 800ddd2: 0758 lsls r0, r3, #29 + 800ddd4: d512 bpl.n 800ddfc <__swsetup_r+0x5c> + 800ddd6: 6b61 ldr r1, [r4, #52] ; 0x34 + 800ddd8: b141 cbz r1, 800ddec <__swsetup_r+0x4c> + 800ddda: f104 0344 add.w r3, r4, #68 ; 0x44 + 800ddde: 4299 cmp r1, r3 + 800dde0: d002 beq.n 800dde8 <__swsetup_r+0x48> + 800dde2: 4628 mov r0, r5 + 800dde4: f7ff fafc bl 800d3e0 <_free_r> + 800dde8: 2300 movs r3, #0 + 800ddea: 6363 str r3, [r4, #52] ; 0x34 + 800ddec: 89a3 ldrh r3, [r4, #12] + 800ddee: f023 0324 bic.w r3, r3, #36 ; 0x24 + 800ddf2: 81a3 strh r3, [r4, #12] + 800ddf4: 2300 movs r3, #0 + 800ddf6: 6063 str r3, [r4, #4] + 800ddf8: 6923 ldr r3, [r4, #16] + 800ddfa: 6023 str r3, [r4, #0] + 800ddfc: 89a3 ldrh r3, [r4, #12] + 800ddfe: f043 0308 orr.w r3, r3, #8 + 800de02: 81a3 strh r3, [r4, #12] + 800de04: 6923 ldr r3, [r4, #16] + 800de06: b94b cbnz r3, 800de1c <__swsetup_r+0x7c> + 800de08: 89a3 ldrh r3, [r4, #12] + 800de0a: f403 7320 and.w r3, r3, #640 ; 0x280 + 800de0e: f5b3 7f00 cmp.w r3, #512 ; 0x200 + 800de12: d003 beq.n 800de1c <__swsetup_r+0x7c> + 800de14: 4621 mov r1, r4 + 800de16: 4628 mov r0, r5 + 800de18: f000 f884 bl 800df24 <__smakebuf_r> + 800de1c: 89a0 ldrh r0, [r4, #12] + 800de1e: f9b4 200c ldrsh.w r2, [r4, #12] + 800de22: f010 0301 ands.w r3, r0, #1 + 800de26: d00a beq.n 800de3e <__swsetup_r+0x9e> + 800de28: 2300 movs r3, #0 + 800de2a: 60a3 str r3, [r4, #8] + 800de2c: 6963 ldr r3, [r4, #20] + 800de2e: 425b negs r3, r3 + 800de30: 61a3 str r3, [r4, #24] + 800de32: 6923 ldr r3, [r4, #16] + 800de34: b943 cbnz r3, 800de48 <__swsetup_r+0xa8> + 800de36: f010 0080 ands.w r0, r0, #128 ; 0x80 + 800de3a: d1c4 bne.n 800ddc6 <__swsetup_r+0x26> + 800de3c: bd38 pop {r3, r4, r5, pc} + 800de3e: 0781 lsls r1, r0, #30 + 800de40: bf58 it pl + 800de42: 6963 ldrpl r3, [r4, #20] + 800de44: 60a3 str r3, [r4, #8] + 800de46: e7f4 b.n 800de32 <__swsetup_r+0x92> + 800de48: 2000 movs r0, #0 + 800de4a: e7f7 b.n 800de3c <__swsetup_r+0x9c> + 800de4c: 2000008c .word 0x2000008c + +0800de50 <_raise_r>: + 800de50: 291f cmp r1, #31 + 800de52: b538 push {r3, r4, r5, lr} + 800de54: 4604 mov r4, r0 + 800de56: 460d mov r5, r1 + 800de58: d904 bls.n 800de64 <_raise_r+0x14> + 800de5a: 2316 movs r3, #22 + 800de5c: 6003 str r3, [r0, #0] + 800de5e: f04f 30ff mov.w r0, #4294967295 + 800de62: bd38 pop {r3, r4, r5, pc} + 800de64: 6bc2 ldr r2, [r0, #60] ; 0x3c + 800de66: b112 cbz r2, 800de6e <_raise_r+0x1e> + 800de68: f852 3021 ldr.w r3, [r2, r1, lsl #2] + 800de6c: b94b cbnz r3, 800de82 <_raise_r+0x32> + 800de6e: 4620 mov r0, r4 + 800de70: f000 f830 bl 800ded4 <_getpid_r> + 800de74: 462a mov r2, r5 + 800de76: 4601 mov r1, r0 + 800de78: 4620 mov r0, r4 + 800de7a: e8bd 4038 ldmia.w sp!, {r3, r4, r5, lr} + 800de7e: f000 b817 b.w 800deb0 <_kill_r> + 800de82: 2b01 cmp r3, #1 + 800de84: d00a beq.n 800de9c <_raise_r+0x4c> + 800de86: 1c59 adds r1, r3, #1 + 800de88: d103 bne.n 800de92 <_raise_r+0x42> + 800de8a: 2316 movs r3, #22 + 800de8c: 6003 str r3, [r0, #0] + 800de8e: 2001 movs r0, #1 + 800de90: e7e7 b.n 800de62 <_raise_r+0x12> + 800de92: 2400 movs r4, #0 + 800de94: f842 4025 str.w r4, [r2, r5, lsl #2] + 800de98: 4628 mov r0, r5 + 800de9a: 4798 blx r3 + 800de9c: 2000 movs r0, #0 + 800de9e: e7e0 b.n 800de62 <_raise_r+0x12> + +0800dea0 : + 800dea0: 4b02 ldr r3, [pc, #8] ; (800deac ) + 800dea2: 4601 mov r1, r0 + 800dea4: 6818 ldr r0, [r3, #0] + 800dea6: f7ff bfd3 b.w 800de50 <_raise_r> + 800deaa: bf00 nop + 800deac: 2000008c .word 0x2000008c + +0800deb0 <_kill_r>: + 800deb0: b538 push {r3, r4, r5, lr} + 800deb2: 4d07 ldr r5, [pc, #28] ; (800ded0 <_kill_r+0x20>) + 800deb4: 2300 movs r3, #0 + 800deb6: 4604 mov r4, r0 + 800deb8: 4608 mov r0, r1 + 800deba: 4611 mov r1, r2 + 800debc: 602b str r3, [r5, #0] + 800debe: f7f2 ff76 bl 8000dae <_kill> + 800dec2: 1c43 adds r3, r0, #1 + 800dec4: d102 bne.n 800decc <_kill_r+0x1c> + 800dec6: 682b ldr r3, [r5, #0] + 800dec8: b103 cbz r3, 800decc <_kill_r+0x1c> + 800deca: 6023 str r3, [r4, #0] + 800decc: bd38 pop {r3, r4, r5, pc} + 800dece: bf00 nop + 800ded0: 20000a38 .word 0x20000a38 + +0800ded4 <_getpid_r>: + 800ded4: f7f2 bf64 b.w 8000da0 <_getpid> + +0800ded8 <__swhatbuf_r>: + 800ded8: b570 push {r4, r5, r6, lr} + 800deda: 460c mov r4, r1 + 800dedc: f9b1 100e ldrsh.w r1, [r1, #14] + 800dee0: 2900 cmp r1, #0 + 800dee2: b096 sub sp, #88 ; 0x58 + 800dee4: 4615 mov r5, r2 + 800dee6: 461e mov r6, r3 + 800dee8: da0d bge.n 800df06 <__swhatbuf_r+0x2e> + 800deea: 89a3 ldrh r3, [r4, #12] + 800deec: f013 0f80 tst.w r3, #128 ; 0x80 + 800def0: f04f 0100 mov.w r1, #0 + 800def4: bf0c ite eq + 800def6: f44f 6380 moveq.w r3, #1024 ; 0x400 + 800defa: 2340 movne r3, #64 ; 0x40 + 800defc: 2000 movs r0, #0 + 800defe: 6031 str r1, [r6, #0] + 800df00: 602b str r3, [r5, #0] + 800df02: b016 add sp, #88 ; 0x58 + 800df04: bd70 pop {r4, r5, r6, pc} + 800df06: 466a mov r2, sp + 800df08: f000 f848 bl 800df9c <_fstat_r> + 800df0c: 2800 cmp r0, #0 + 800df0e: dbec blt.n 800deea <__swhatbuf_r+0x12> + 800df10: 9901 ldr r1, [sp, #4] + 800df12: f401 4170 and.w r1, r1, #61440 ; 0xf000 + 800df16: f5a1 5300 sub.w r3, r1, #8192 ; 0x2000 + 800df1a: 4259 negs r1, r3 + 800df1c: 4159 adcs r1, r3 + 800df1e: f44f 6380 mov.w r3, #1024 ; 0x400 + 800df22: e7eb b.n 800defc <__swhatbuf_r+0x24> + +0800df24 <__smakebuf_r>: + 800df24: 898b ldrh r3, [r1, #12] + 800df26: b573 push {r0, r1, r4, r5, r6, lr} + 800df28: 079d lsls r5, r3, #30 + 800df2a: 4606 mov r6, r0 + 800df2c: 460c mov r4, r1 + 800df2e: d507 bpl.n 800df40 <__smakebuf_r+0x1c> + 800df30: f104 0347 add.w r3, r4, #71 ; 0x47 + 800df34: 6023 str r3, [r4, #0] + 800df36: 6123 str r3, [r4, #16] + 800df38: 2301 movs r3, #1 + 800df3a: 6163 str r3, [r4, #20] + 800df3c: b002 add sp, #8 + 800df3e: bd70 pop {r4, r5, r6, pc} + 800df40: ab01 add r3, sp, #4 + 800df42: 466a mov r2, sp + 800df44: f7ff ffc8 bl 800ded8 <__swhatbuf_r> + 800df48: 9900 ldr r1, [sp, #0] + 800df4a: 4605 mov r5, r0 + 800df4c: 4630 mov r0, r6 + 800df4e: f7ff fab9 bl 800d4c4 <_malloc_r> + 800df52: b948 cbnz r0, 800df68 <__smakebuf_r+0x44> + 800df54: f9b4 300c ldrsh.w r3, [r4, #12] + 800df58: 059a lsls r2, r3, #22 + 800df5a: d4ef bmi.n 800df3c <__smakebuf_r+0x18> + 800df5c: f023 0303 bic.w r3, r3, #3 + 800df60: f043 0302 orr.w r3, r3, #2 + 800df64: 81a3 strh r3, [r4, #12] + 800df66: e7e3 b.n 800df30 <__smakebuf_r+0xc> + 800df68: 89a3 ldrh r3, [r4, #12] + 800df6a: 6020 str r0, [r4, #0] + 800df6c: f043 0380 orr.w r3, r3, #128 ; 0x80 + 800df70: 81a3 strh r3, [r4, #12] + 800df72: 9b00 ldr r3, [sp, #0] + 800df74: 6163 str r3, [r4, #20] + 800df76: 9b01 ldr r3, [sp, #4] + 800df78: 6120 str r0, [r4, #16] + 800df7a: b15b cbz r3, 800df94 <__smakebuf_r+0x70> + 800df7c: f9b4 100e ldrsh.w r1, [r4, #14] + 800df80: 4630 mov r0, r6 + 800df82: f000 f81d bl 800dfc0 <_isatty_r> + 800df86: b128 cbz r0, 800df94 <__smakebuf_r+0x70> + 800df88: 89a3 ldrh r3, [r4, #12] + 800df8a: f023 0303 bic.w r3, r3, #3 + 800df8e: f043 0301 orr.w r3, r3, #1 + 800df92: 81a3 strh r3, [r4, #12] + 800df94: 89a3 ldrh r3, [r4, #12] + 800df96: 431d orrs r5, r3 + 800df98: 81a5 strh r5, [r4, #12] + 800df9a: e7cf b.n 800df3c <__smakebuf_r+0x18> + +0800df9c <_fstat_r>: + 800df9c: b538 push {r3, r4, r5, lr} + 800df9e: 4d07 ldr r5, [pc, #28] ; (800dfbc <_fstat_r+0x20>) + 800dfa0: 2300 movs r3, #0 + 800dfa2: 4604 mov r4, r0 + 800dfa4: 4608 mov r0, r1 + 800dfa6: 4611 mov r1, r2 + 800dfa8: 602b str r3, [r5, #0] + 800dfaa: f7f2 ff5e bl 8000e6a <_fstat> + 800dfae: 1c43 adds r3, r0, #1 + 800dfb0: d102 bne.n 800dfb8 <_fstat_r+0x1c> + 800dfb2: 682b ldr r3, [r5, #0] + 800dfb4: b103 cbz r3, 800dfb8 <_fstat_r+0x1c> + 800dfb6: 6023 str r3, [r4, #0] + 800dfb8: bd38 pop {r3, r4, r5, pc} + 800dfba: bf00 nop + 800dfbc: 20000a38 .word 0x20000a38 + +0800dfc0 <_isatty_r>: + 800dfc0: b538 push {r3, r4, r5, lr} + 800dfc2: 4d06 ldr r5, [pc, #24] ; (800dfdc <_isatty_r+0x1c>) + 800dfc4: 2300 movs r3, #0 + 800dfc6: 4604 mov r4, r0 + 800dfc8: 4608 mov r0, r1 + 800dfca: 602b str r3, [r5, #0] + 800dfcc: f7f2 ff5c bl 8000e88 <_isatty> + 800dfd0: 1c43 adds r3, r0, #1 + 800dfd2: d102 bne.n 800dfda <_isatty_r+0x1a> + 800dfd4: 682b ldr r3, [r5, #0] + 800dfd6: b103 cbz r3, 800dfda <_isatty_r+0x1a> + 800dfd8: 6023 str r3, [r4, #0] + 800dfda: bd38 pop {r3, r4, r5, pc} + 800dfdc: 20000a38 .word 0x20000a38 + +0800dfe0 <_init>: + 800dfe0: b5f8 push {r3, r4, r5, r6, r7, lr} + 800dfe2: bf00 nop + 800dfe4: bcf8 pop {r3, r4, r5, r6, r7} + 800dfe6: bc08 pop {r3} + 800dfe8: 469e mov lr, r3 + 800dfea: 4770 bx lr + +0800dfec <_fini>: + 800dfec: b5f8 push {r3, r4, r5, r6, r7, lr} + 800dfee: bf00 nop + 800dff0: bcf8 pop {r3, r4, r5, r6, r7} + 800dff2: bc08 pop {r3} + 800dff4: 469e mov lr, r3 + 800dff6: 4770 bx lr diff --git a/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.map b/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.map new file mode 100644 index 0000000..236b66e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/LoRa-GPS-Tracker.map @@ -0,0 +1,10633 @@ +Archive member included to satisfy reference by file (symbol) + +E:/ST/STM32CubeIDE_1.13.1/STM32CubeIDE/plugins/com.st.stm32cube.ide.mcu.externaltools.gnu-tools-for-stm32.11.3.rel1.win32_1.1.100.202309141235/tools/bin/../lib/gcc/arm-none-eabi/11.3.1/../../../../arm-none-eabi/lib/thumb/v7e-m/nofp\libc_nano.a(libc_a-exit.o) + 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./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxDutyCycle + 0x000000000800900c 0x48 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioStartCad + 0x0000000008009054 0x30 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxContinuousWave + 0x0000000008009084 0x64 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRssi + 0x00000000080090e8 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioWrite + 0x0000000008009102 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioRead + 0x0000000008009126 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioWriteRegisters + 0x0000000008009142 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioReadRegisters + 0x0000000008009168 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x000000000800918e 0x2 + .text.RadioSetMaxPayloadLength + 0x0000000008009190 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetPublicNetwork + 0x00000000080091ec 0x5c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioGetWakeupTime + 0x0000000008009248 0x10 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnTxTimeoutIrq + 0x0000000008009258 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnRxTimeoutIrq + 0x000000000800926c 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnTxTimeoutProcess + 0x0000000008009280 0x28 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnRxTimeoutProcess + 0x00000000080092a8 0x28 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioOnDioIrq + 0x00000000080092d0 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioIrqProcess + 0x00000000080092f4 0x44c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioTxPrbs + 0x0000000008009740 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioTxCw + 0x0000000008009778 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.payload_integration + 0x00000000080097b0 0x120 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetRxGenericConfig + 0x00000000080098d0 0x388 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioSetTxGenericConfig + 0x0000000008009c58 0x46c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioLrFhssSetCfg + 0x000000000800a0c4 0x18 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + .text.RadioLrFhssGetTimeOnAirInMs + 0x000000000800a0dc 0x16 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o + *fill* 0x000000000800a0f2 0x2 + .text.SUBGRF_Init + 0x000000000800a0f4 0x90 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a0f4 SUBGRF_Init + .text.SUBGRF_GetOperatingMode + 0x000000000800a184 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a184 SUBGRF_GetOperatingMode + .text.SUBGRF_SetPayload + 0x000000000800a198 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a198 SUBGRF_SetPayload + .text.SUBGRF_GetPayload + 0x000000000800a1b8 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a1b8 SUBGRF_GetPayload + .text.SUBGRF_SendPayload + 0x000000000800a1fc 0x26 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a1fc SUBGRF_SendPayload + .text.SUBGRF_SetSyncWord + 0x000000000800a222 0x1e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a222 SUBGRF_SetSyncWord + .text.SUBGRF_SetCrcSeed + 0x000000000800a240 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a240 SUBGRF_SetCrcSeed + .text.SUBGRF_SetCrcPolynomial + 0x000000000800a280 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a280 SUBGRF_SetCrcPolynomial + .text.SUBGRF_SetWhiteningSeed + 0x000000000800a2c0 0x66 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a2c0 SUBGRF_SetWhiteningSeed + .text.SUBGRF_GetRandom + 0x000000000800a326 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a326 SUBGRF_GetRandom + *fill* 0x000000000800a3b2 0x2 + .text.SUBGRF_SetSleep + 0x000000000800a3b4 0x64 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a3b4 SUBGRF_SetSleep + .text.SUBGRF_SetStandby + 0x000000000800a418 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a418 SUBGRF_SetStandby + .text.SUBGRF_SetTx + 0x000000000800a450 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a450 SUBGRF_SetTx + .text.SUBGRF_SetRx + 0x000000000800a490 0x40 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a490 SUBGRF_SetRx + .text.SUBGRF_SetRxBoosted + 0x000000000800a4d0 0x48 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a4d0 SUBGRF_SetRxBoosted + .text.SUBGRF_SetRxDutyCycle + 0x000000000800a518 0x58 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a518 SUBGRF_SetRxDutyCycle + .text.SUBGRF_SetCad + 0x000000000800a570 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a570 SUBGRF_SetCad + .text.SUBGRF_SetTxContinuousWave + 0x000000000800a58c 0x12 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a58c SUBGRF_SetTxContinuousWave + .text.SUBGRF_SetTxInfinitePreamble + 0x000000000800a59e 0x12 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a59e SUBGRF_SetTxInfinitePreamble + .text.SUBGRF_SetStopRxTimerOnPreambleDetect + 0x000000000800a5b0 0x1e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a5b0 SUBGRF_SetStopRxTimerOnPreambleDetect + .text.SUBGRF_SetLoRaSymbNumTimeout + 0x000000000800a5ce 0x5e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a5ce SUBGRF_SetLoRaSymbNumTimeout + .text.SUBGRF_SetRegulatorMode + 0x000000000800a62c 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a62c SUBGRF_SetRegulatorMode + .text.SUBGRF_Calibrate + 0x000000000800a65a 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a65a SUBGRF_Calibrate + *fill* 0x000000000800a6e6 0x2 + .text.SUBGRF_CalibrateImage + 0x000000000800a6e8 0x94 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a6e8 SUBGRF_CalibrateImage + .text.SUBGRF_SetPaConfig + 0x000000000800a77c 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a77c SUBGRF_SetPaConfig + .text.SUBGRF_SetDioIrqParams + 0x000000000800a7c0 0x74 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a7c0 SUBGRF_SetDioIrqParams + .text.SUBGRF_SetTcxoMode + 0x000000000800a834 0x42 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a834 SUBGRF_SetTcxoMode + *fill* 0x000000000800a876 0x2 + .text.SUBGRF_SetRfFrequency + 0x000000000800a878 0x8c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a878 SUBGRF_SetRfFrequency + .text.SUBGRF_SetPacketType + 0x000000000800a904 0x38 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a904 SUBGRF_SetPacketType + .text.SUBGRF_GetPacketType + 0x000000000800a93c 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a93c SUBGRF_GetPacketType + .text.SUBGRF_SetTxParams + 0x000000000800a950 0x19a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800a950 SUBGRF_SetTxParams + *fill* 0x000000000800aaea 0x2 + .text.SUBGRF_SetModulationParams + 0x000000000800aaec 0x1a4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800aaec SUBGRF_SetModulationParams + .text.SUBGRF_SetPacketParams + 0x000000000800ac90 0x13c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800ac90 SUBGRF_SetPacketParams + .text.SUBGRF_SetBufferBaseAddress + 0x000000000800adcc 0x2e ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800adcc SUBGRF_SetBufferBaseAddress + .text.SUBGRF_GetRssiInst + 0x000000000800adfa 0x2a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800adfa SUBGRF_GetRssiInst + .text.SUBGRF_GetRxBufferStatus + 0x000000000800ae24 0x58 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800ae24 SUBGRF_GetRxBufferStatus + .text.SUBGRF_GetPacketStatus + 0x000000000800ae7c 0xa4 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800ae7c SUBGRF_GetPacketStatus + .text.SUBGRF_WriteRegister + 0x000000000800af20 0x28 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800af20 SUBGRF_WriteRegister + .text.SUBGRF_ReadRegister + 0x000000000800af48 0x28 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800af48 SUBGRF_ReadRegister + .text.SUBGRF_WriteRegisters + 0x000000000800af70 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800af70 SUBGRF_WriteRegisters + .text.SUBGRF_ReadRegisters + 0x000000000800afb4 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800afb4 SUBGRF_ReadRegisters + .text.SUBGRF_WriteBuffer + 0x000000000800aff8 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800aff8 SUBGRF_WriteBuffer + .text.SUBGRF_ReadBuffer + 0x000000000800b03c 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b03c SUBGRF_ReadBuffer + .text.SUBGRF_WriteCommand + 0x000000000800b080 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b080 SUBGRF_WriteCommand + .text.SUBGRF_ReadCommand + 0x000000000800b0c4 0x44 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b0c4 SUBGRF_ReadCommand + .text.SUBGRF_SetSwitch + 0x000000000800b108 0x50 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b108 SUBGRF_SetSwitch + .text.SUBGRF_SetRfTxPower + 0x000000000800b158 0x68 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b158 SUBGRF_SetRfTxPower + .text.SUBGRF_GetRadioWakeUpTime + 0x000000000800b1c0 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b1c0 SUBGRF_GetRadioWakeUpTime + *fill* 0x000000000800b1ce 0x2 + .text.HAL_SUBGHZ_TxCpltCallback + 0x000000000800b1d0 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b1d0 HAL_SUBGHZ_TxCpltCallback + .text.HAL_SUBGHZ_RxCpltCallback + 0x000000000800b1ec 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b1ec HAL_SUBGHZ_RxCpltCallback + .text.HAL_SUBGHZ_CRCErrorCallback + 0x000000000800b208 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b208 HAL_SUBGHZ_CRCErrorCallback + .text.HAL_SUBGHZ_CADStatusCallback + 0x000000000800b224 0x3c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b224 HAL_SUBGHZ_CADStatusCallback + .text.HAL_SUBGHZ_RxTxTimeoutCallback + 0x000000000800b260 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b260 HAL_SUBGHZ_RxTxTimeoutCallback + .text.HAL_SUBGHZ_HeaderErrorCallback + 0x000000000800b280 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b280 HAL_SUBGHZ_HeaderErrorCallback + .text.HAL_SUBGHZ_PreambleDetectedCallback + 0x000000000800b29c 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b29c HAL_SUBGHZ_PreambleDetectedCallback + .text.HAL_SUBGHZ_SyncWordValidCallback + 0x000000000800b2b8 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b2b8 HAL_SUBGHZ_SyncWordValidCallback + .text.HAL_SUBGHZ_HeaderValidCallback + 0x000000000800b2d4 0x1c ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b2d4 HAL_SUBGHZ_HeaderValidCallback + .text.HAL_SUBGHZ_LrFhssHopCallback + 0x000000000800b2f0 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b2f0 HAL_SUBGHZ_LrFhssHopCallback + .text.Radio_SMPS_Set + 0x000000000800b310 0x42 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + *fill* 0x000000000800b352 0x2 + .text.SUBGRF_GetFskBandwidthRegValue + 0x000000000800b354 0x50 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b354 SUBGRF_GetFskBandwidthRegValue + .text.SUBGRF_GetCFO + 0x000000000800b3a4 0xe8 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o + 0x000000000800b3a4 SUBGRF_GetCFO + .text.RFW_TransmitLongPacket + 0x000000000800b48c 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b48c RFW_TransmitLongPacket + .text.RFW_ReceiveLongPacket + 0x000000000800b4b0 0x24 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b4b0 RFW_ReceiveLongPacket + .text.RFW_Init + 0x000000000800b4d4 0x1a ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b4d4 RFW_Init + .text.RFW_DeInit + 0x000000000800b4ee 0xc ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b4ee RFW_DeInit + .text.RFW_Is_Init + 0x000000000800b4fa 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b4fa RFW_Is_Init + .text.RFW_Is_LongPacketModeEnabled + 0x000000000800b508 0xe ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b508 RFW_Is_LongPacketModeEnabled + .text.RFW_SetAntSwitch + 0x000000000800b516 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b516 RFW_SetAntSwitch + .text.RFW_TransmitInit + 0x000000000800b52a 0x20 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b52a RFW_TransmitInit + .text.RFW_ReceiveInit + 0x000000000800b54a 0x10 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b54a RFW_ReceiveInit + .text.RFW_DeInit_TxLongPacket + 0x000000000800b55a 0xc ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b55a RFW_DeInit_TxLongPacket + .text.RFW_ReceivePayload + 0x000000000800b566 0xc ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b566 RFW_ReceivePayload + .text.RFW_SetRadioModem + 0x000000000800b572 0x14 ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o + 0x000000000800b572 RFW_SetRadioModem + .text.LL_RCC_ClearResetFlags + 0x000000000800b586 0x20 ./SubGHz_Phy/App/app_subghz_phy.o + *fill* 0x000000000800b5a6 0x2 + .text.MX_SubGHz_Phy_Init + 0x000000000800b5a8 0xb0 ./SubGHz_Phy/App/app_subghz_phy.o + 0x000000000800b5a8 MX_SubGHz_Phy_Init + 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+../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:324:14:lr_fhss_get_hop_sequence_count 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:334:6:lr_fhss_process_parameters 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:349:16:lr_fhss_get_hop_params 23 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:426:10:lr_fhss_get_next_state 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:448:9:lr_fhss_get_next_freq_in_grid 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:480:10:lr_fhss_build_frame 15 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:589:10:lr_fhss_get_time_on_air_in_ms 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:600:17:lr_fhss_payload_crc16 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:612:16:lr_fhss_header_crc8 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:624:13:lr_fhss_payload_whitening 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:638:16:lr_fhss_extract_bit_in_byte_vector 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:650:13:lr_fhss_set_bit_in_byte_vector 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:658:17:lr_fhss_convolution_encode_viterbi_1_2_base 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:691:17:lr_fhss_convolution_encode_viterbi_1_3_base 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:726:17:lr_fhss_convolution_encode_viterbi_1_2 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:742:17:lr_fhss_convolution_encode_viterbi_1_3 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:749:17:sqrt_uint16 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:761:17:lr_fhss_payload_interleaving 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:809:13:lr_fhss_raw_header 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:819:13:lr_fhss_store_header_sync_word_index 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:824:17:lr_fhss_get_bit_and_hop_count 6 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d new file mode 100644 index 0000000..74d4db7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d @@ -0,0 +1,8 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o new file mode 100644 index 0000000..23c4d41 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su new file mode 100644 index 0000000..f5d979e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su @@ -0,0 +1,22 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h:174:24:lr_fhss_get_time_on_air_numerator 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:324:14:lr_fhss_get_hop_sequence_count 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:334:6:lr_fhss_process_parameters 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:349:16:lr_fhss_get_hop_params 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:426:10:lr_fhss_get_next_state 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:448:9:lr_fhss_get_next_freq_in_grid 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:480:10:lr_fhss_build_frame 720 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:589:10:lr_fhss_get_time_on_air_in_ms 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:600:17:lr_fhss_payload_crc16 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:612:16:lr_fhss_header_crc8 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:624:13:lr_fhss_payload_whitening 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:638:16:lr_fhss_extract_bit_in_byte_vector 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:650:13:lr_fhss_set_bit_in_byte_vector 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:658:17:lr_fhss_convolution_encode_viterbi_1_2_base 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:691:17:lr_fhss_convolution_encode_viterbi_1_3_base 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:726:17:lr_fhss_convolution_encode_viterbi_1_2 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:742:17:lr_fhss_convolution_encode_viterbi_1_3 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:749:17:sqrt_uint16 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:761:17:lr_fhss_payload_interleaving 56 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:809:13:lr_fhss_raw_header 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:819:13:lr_fhss_store_header_sync_word_index 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c:824:17:lr_fhss_get_bit_and_hop_count 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo new file mode 100644 index 0000000..1305a37 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo @@ -0,0 +1,42 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:704:13:RadioInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:737:21:RadioGetStatus 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:752:13:RadioSetModem 7 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:803:13:RadioSetChannel 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:808:13:RadioIsChannelFree 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:845:17:RadioRandom 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:860:13:RadioSetRxConfig 17 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1049:13:RadioSetTxConfig 14 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1159:13:RadioCheckRfFrequency 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1164:17:RadioGetLoRaBandwidthInHz 11 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1205:17:RadioGetGfskTimeOnAirNumerator 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1214:17:RadioGetLoRaTimeOnAirNumerator 15 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1278:17:RadioTimeOnAir 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1311:23:RadioSend 10 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1444:13:RadioSleep 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1454:13:RadioStandby 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1459:13:RadioRx 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1501:13:RadioRxBoosted 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1542:13:RadioSetRxDutyCycle 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1554:13:RadioStartCad 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1566:13:RadioSetTxContinuousWave 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1593:16:RadioRssi 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1598:13:RadioWrite 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1603:16:RadioRead 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1608:13:RadioWriteRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1613:13:RadioReadRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1618:13:RadioSetMaxPayloadLength 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1635:13:RadioSetPublicNetwork 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1654:17:RadioGetWakeupTime 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1659:13:RadioOnTxTimeoutIrq 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1664:13:RadioOnRxTimeoutIrq 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1669:13:RadioOnTxTimeoutProcess 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1679:13:RadioOnRxTimeoutProcess 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1689:13:RadioOnDioIrq 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1696:13:RadioIrqProcess 41 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1876:13:RadioTxPrbs 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1884:13:RadioTxCw 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1894:13:payload_integration 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1932:16:RadioSetRxGenericConfig 24 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2110:16:RadioSetTxGenericConfig 31 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2348:23:RadioLrFhssSetCfg 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2379:23:RadioLrFhssGetTimeOnAirInMs 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d new file mode 100644 index 0000000..cd8c0b4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d @@ -0,0 +1,144 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c \ + ../Middlewares/Third_Party/SubGHz_Phy/radio.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h \ + ../SubGHz_Phy/Target/timer.h ../Utilities/timer/stm32_timer.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../SubGHz_Phy/Target/mw_log_conf.h +../Middlewares/Third_Party/SubGHz_Phy/radio.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: +../SubGHz_Phy/Target/timer.h: +../Utilities/timer/stm32_timer.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../SubGHz_Phy/Target/mw_log_conf.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o new file mode 100644 index 0000000..cfeee8a Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su new file mode 100644 index 0000000..2bdd2e5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su @@ -0,0 +1,42 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:704:13:RadioInit 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:737:21:RadioGetStatus 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:752:13:RadioSetModem 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:803:13:RadioSetChannel 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:808:13:RadioIsChannelFree 72 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:845:17:RadioRandom 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:860:13:RadioSetRxConfig 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1049:13:RadioSetTxConfig 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1159:13:RadioCheckRfFrequency 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1164:17:RadioGetLoRaBandwidthInHz 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1205:17:RadioGetGfskTimeOnAirNumerator 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1214:17:RadioGetLoRaTimeOnAirNumerator 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1278:17:RadioTimeOnAir 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1311:23:RadioSend 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1444:13:RadioSleep 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1454:13:RadioStandby 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1459:13:RadioRx 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1501:13:RadioRxBoosted 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1542:13:RadioSetRxDutyCycle 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1554:13:RadioStartCad 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1566:13:RadioSetTxContinuousWave 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1593:16:RadioRssi 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1598:13:RadioWrite 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1603:16:RadioRead 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1608:13:RadioWriteRegisters 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1613:13:RadioReadRegisters 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1618:13:RadioSetMaxPayloadLength 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1635:13:RadioSetPublicNetwork 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1654:17:RadioGetWakeupTime 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1659:13:RadioOnTxTimeoutIrq 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1664:13:RadioOnRxTimeoutIrq 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1669:13:RadioOnTxTimeoutProcess 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1679:13:RadioOnRxTimeoutProcess 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1689:13:RadioOnDioIrq 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1696:13:RadioIrqProcess 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1876:13:RadioTxPrbs 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1884:13:RadioTxCw 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1894:13:payload_integration 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:1932:16:RadioSetRxGenericConfig 56 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2110:16:RadioSetTxGenericConfig 64 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2348:23:RadioLrFhssSetCfg 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c:2379:23:RadioLrFhssGetTimeOnAirInMs 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo new file mode 100644 index 0000000..587e7ca --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo @@ -0,0 +1,69 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:184:6:SUBGRF_Init 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:226:23:SUBGRF_GetOperatingMode 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:231:6:SUBGRF_SetPayload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:236:9:SUBGRF_GetPayload 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:250:6:SUBGRF_SendPayload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:256:9:SUBGRF_SetSyncWord 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:262:6:SUBGRF_SetCrcSeed 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:280:6:SUBGRF_SetCrcPolynomial 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:298:6:SUBGRF_SetWhiteningSeed 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:316:10:SUBGRF_GetRandom 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:341:6:SUBGRF_SetSleep 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:355:6:SUBGRF_SetStandby 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:368:6:SUBGRF_SetFs 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:374:6:SUBGRF_SetTx 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:386:6:SUBGRF_SetRx 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:398:6:SUBGRF_SetRxBoosted 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:412:6:SUBGRF_SetRxDutyCycle 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:426:6:SUBGRF_SetCad 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:432:6:SUBGRF_SetTxContinuousWave 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:437:6:SUBGRF_SetTxInfinitePreamble 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:442:6:SUBGRF_SetStopRxTimerOnPreambleDetect 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:447:6:SUBGRF_SetLoRaSymbNumTimeout 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:468:6:SUBGRF_SetRegulatorMode 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:483:6:SUBGRF_Calibrate 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:496:6:SUBGRF_CalibrateImage 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:534:6:SUBGRF_SetPaConfig 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:545:6:SUBGRF_SetRxTxFallbackMode 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:550:6:SUBGRF_SetDioIrqParams 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:565:10:SUBGRF_GetIrqStatus 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:573:6:SUBGRF_SetTcxoMode 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:585:6:SUBGRF_SetRfFrequency 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:603:6:SUBGRF_SetPacketType 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:615:20:SUBGRF_GetPacketType 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:620:6:SUBGRF_SetTxParams 11 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:694:6:SUBGRF_SetModulationParams 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:758:6:SUBGRF_SetPacketParams 7 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:822:6:SUBGRF_SetCadParams 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:837:6:SUBGRF_SetBufferBaseAddress 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:846:18:SUBGRF_GetStatus 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:857:8:SUBGRF_GetRssiInst 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:867:6:SUBGRF_GetRxBufferStatus 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:886:6:SUBGRF_GetPacketStatus 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:920:14:SUBGRF_GetDeviceErrors 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:937:6:SUBGRF_ClearDeviceErrors 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:943:6:SUBGRF_ClearIrqStatus 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:952:6:SUBGRF_WriteRegister 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:957:9:SUBGRF_ReadRegister 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:964:6:SUBGRF_WriteRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:971:6:SUBGRF_ReadRegisters 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:978:6:SUBGRF_WriteBuffer 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:985:6:SUBGRF_ReadBuffer 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:992:6:SUBGRF_WriteCommand 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1000:6:SUBGRF_ReadCommand 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1008:6:SUBGRF_SetSwitch 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1034:9:SUBGRF_SetRfTxPower 6 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1073:10:SUBGRF_GetRadioWakeUpTime 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1079:6:HAL_SUBGHZ_TxCpltCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1084:6:HAL_SUBGHZ_RxCpltCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1089:6:HAL_SUBGHZ_CRCErrorCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1094:6:HAL_SUBGHZ_CADStatusCallback 3 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1109:6:HAL_SUBGHZ_RxTxTimeoutCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1114:6:HAL_SUBGHZ_HeaderErrorCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1119:6:HAL_SUBGHZ_PreambleDetectedCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1124:6:HAL_SUBGHZ_SyncWordValidCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1129:6:HAL_SUBGHZ_HeaderValidCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1134:6:HAL_SUBGHZ_LrFhssHopCallback 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1139:13:Radio_SMPS_Set 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1150:9:SUBGRF_GetFskBandwidthRegValue 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1169:6:SUBGRF_GetCFO 4 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d new file mode 100644 index 0000000..55f5ed5 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d @@ -0,0 +1,121 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../SubGHz_Phy/Target/mw_log_conf.h +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../SubGHz_Phy/Target/mw_log_conf.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o new file mode 100644 index 0000000..511cba2 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su new file mode 100644 index 0000000..5629d24 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su @@ -0,0 +1,69 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:184:6:SUBGRF_Init 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:226:23:SUBGRF_GetOperatingMode 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:231:6:SUBGRF_SetPayload 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:236:9:SUBGRF_GetPayload 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:250:6:SUBGRF_SendPayload 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:256:9:SUBGRF_SetSyncWord 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:262:6:SUBGRF_SetCrcSeed 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:280:6:SUBGRF_SetCrcPolynomial 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:298:6:SUBGRF_SetWhiteningSeed 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:316:10:SUBGRF_GetRandom 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:341:6:SUBGRF_SetSleep 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:355:6:SUBGRF_SetStandby 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:368:6:SUBGRF_SetFs 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:374:6:SUBGRF_SetTx 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:386:6:SUBGRF_SetRx 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:398:6:SUBGRF_SetRxBoosted 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:412:6:SUBGRF_SetRxDutyCycle 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:426:6:SUBGRF_SetCad 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:432:6:SUBGRF_SetTxContinuousWave 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:437:6:SUBGRF_SetTxInfinitePreamble 8 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:442:6:SUBGRF_SetStopRxTimerOnPreambleDetect 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:447:6:SUBGRF_SetLoRaSymbNumTimeout 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:468:6:SUBGRF_SetRegulatorMode 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:483:6:SUBGRF_Calibrate 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:496:6:SUBGRF_CalibrateImage 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:534:6:SUBGRF_SetPaConfig 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:545:6:SUBGRF_SetRxTxFallbackMode 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:550:6:SUBGRF_SetDioIrqParams 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:565:10:SUBGRF_GetIrqStatus 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:573:6:SUBGRF_SetTcxoMode 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:585:6:SUBGRF_SetRfFrequency 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:603:6:SUBGRF_SetPacketType 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:615:20:SUBGRF_GetPacketType 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:620:6:SUBGRF_SetTxParams 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:694:6:SUBGRF_SetModulationParams 48 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:758:6:SUBGRF_SetPacketParams 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:822:6:SUBGRF_SetCadParams 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:837:6:SUBGRF_SetBufferBaseAddress 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:846:18:SUBGRF_GetStatus 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:857:8:SUBGRF_GetRssiInst 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:867:6:SUBGRF_GetRxBufferStatus 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:886:6:SUBGRF_GetPacketStatus 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:920:14:SUBGRF_GetDeviceErrors 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:937:6:SUBGRF_ClearDeviceErrors 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:943:6:SUBGRF_ClearIrqStatus 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:952:6:SUBGRF_WriteRegister 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:957:9:SUBGRF_ReadRegister 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:964:6:SUBGRF_WriteRegisters 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:971:6:SUBGRF_ReadRegisters 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:978:6:SUBGRF_WriteBuffer 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:985:6:SUBGRF_ReadBuffer 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:992:6:SUBGRF_WriteCommand 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1000:6:SUBGRF_ReadCommand 32 static,ignoring_inline_asm +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1008:6:SUBGRF_SetSwitch 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1034:9:SUBGRF_SetRfTxPower 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1073:10:SUBGRF_GetRadioWakeUpTime 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1079:6:HAL_SUBGHZ_TxCpltCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1084:6:HAL_SUBGHZ_RxCpltCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1089:6:HAL_SUBGHZ_CRCErrorCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1094:6:HAL_SUBGHZ_CADStatusCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1109:6:HAL_SUBGHZ_RxTxTimeoutCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1114:6:HAL_SUBGHZ_HeaderErrorCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1119:6:HAL_SUBGHZ_PreambleDetectedCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1124:6:HAL_SUBGHZ_SyncWordValidCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1129:6:HAL_SUBGHZ_HeaderValidCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1134:6:HAL_SUBGHZ_LrFhssHopCallback 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1139:13:Radio_SMPS_Set 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1150:9:SUBGRF_GetFskBandwidthRegValue 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c:1169:6:SUBGRF_GetCFO 48 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo new file mode 100644 index 0000000..2e7ae7a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo @@ -0,0 +1,12 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:257:9:RFW_TransmitLongPacket 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:422:9:RFW_ReceiveLongPacket 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:474:9:RFW_Init 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:552:6:RFW_DeInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:559:9:RFW_Is_Init 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:568:9:RFW_Is_LongPacketModeEnabled 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:577:6:RFW_SetAntSwitch 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:584:9:RFW_TransmitInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:636:9:RFW_ReceiveInit 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:659:6:RFW_DeInit_TxLongPacket 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:669:6:RFW_ReceivePayload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:724:6:RFW_SetRadioModem 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d new file mode 100644 index 0000000..767b292 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d @@ -0,0 +1,130 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c \ + ../SubGHz_Phy/Target/timer.h ../Utilities/timer/stm32_timer.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/Inc/utilities_conf.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/mw_log_conf.h +../SubGHz_Phy/Target/timer.h: +../Utilities/timer/stm32_timer.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/Inc/utilities_conf.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/mw_log_conf.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o new file mode 100644 index 0000000..e391360 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su new file mode 100644 index 0000000..088aa86 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su @@ -0,0 +1,12 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:257:9:RFW_TransmitLongPacket 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:422:9:RFW_ReceiveLongPacket 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:474:9:RFW_Init 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:552:6:RFW_DeInit 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:559:9:RFW_Is_Init 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:568:9:RFW_Is_LongPacketModeEnabled 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:577:6:RFW_SetAntSwitch 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:584:9:RFW_TransmitInit 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:636:9:RFW_ReceiveInit 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:659:6:RFW_DeInit_TxLongPacket 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:669:6:RFW_ReceivePayload 4 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c:724:6:RFW_SetRadioModem 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk new file mode 100644 index 0000000..9227116 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk @@ -0,0 +1,39 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.c \ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c + +OBJS += \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o + +C_DEPS += \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d \ +./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d + + +# Each subdirectory must supply rules for building sources it contributes +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.o Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.su Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.cyclo: ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/%.c Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Middlewares-2f-Third_Party-2f-SubGHz_Phy-2f-stm32_radio_driver + +clean-Middlewares-2f-Third_Party-2f-SubGHz_Phy-2f-stm32_radio_driver: + -$(RM) ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.su ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o ./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su + +.PHONY: clean-Middlewares-2f-Third_Party-2f-SubGHz_Phy-2f-stm32_radio_driver + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo new file mode 100644 index 0000000..0df5957 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.cyclo @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:134:16:wl_lr_fhss_init 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:150:16:wl_lr_fhss_process_parameters 12 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:200:16:wl_lr_fhss_write_hop_sequence_head 10 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:276:16:wl_lr_fhss_write_payload 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:284:16:wl_lr_fhss_build_frame 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:314:16:wl_lr_fhss_handle_hop 4 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:342:16:wl_lr_fhss_handle_tx_done 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:357:16:wl_lr_fhss_write_hop_config 1 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:366:16:wl_lr_fhss_write_hop 2 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:388:10:wl_lr_fhss_get_next_freq_in_pll_steps 5 +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:420:28:wl_lr_fhss_get_grid_in_pll_steps 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d new file mode 100644 index 0000000..88975ac --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.d @@ -0,0 +1,127 @@ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o: \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h \ + ../SubGHz_Phy/Target/radio_conf.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h ../Core/Inc/subghz.h \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../SubGHz_Phy/Target/mw_log_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/utilities_def.h \ + ../Core/Inc/sys_debug.h ../Core/Inc/sys_conf.h ../Core/Inc/platform.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.h: +../SubGHz_Phy/Target/radio_conf.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/subghz.h: +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/Target/mw_log_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/utilities_def.h: +../Core/Inc/sys_debug.h: +../Core/Inc/sys_conf.h: +../Core/Inc/platform.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o new file mode 100644 index 0000000..cf0e46c Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su new file mode 100644 index 0000000..eab3158 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.su @@ -0,0 +1,11 @@ +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:134:16:wl_lr_fhss_init 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:150:16:wl_lr_fhss_process_parameters 32 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:200:16:wl_lr_fhss_write_hop_sequence_head 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:276:16:wl_lr_fhss_write_payload 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:284:16:wl_lr_fhss_build_frame 296 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:314:16:wl_lr_fhss_handle_hop 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:342:16:wl_lr_fhss_handle_tx_done 16 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:357:16:wl_lr_fhss_write_hop_config 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:366:16:wl_lr_fhss_write_hop 24 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:388:10:wl_lr_fhss_get_next_freq_in_pll_steps 40 static +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.c:420:28:wl_lr_fhss_get_grid_in_pll_steps 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.cyclo b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.cyclo new file mode 100644 index 0000000..2cd4b6c --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.cyclo @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3168:22:LL_RCC_ClearResetFlags 1 +../SubGHz_Phy/App/app_subghz_phy.c:79:6:MX_SubGHz_Phy_Init 4 +../SubGHz_Phy/App/app_subghz_phy.c:133:6:MX_SubGHz_Phy_Process 3 +../SubGHz_Phy/App/app_subghz_phy.c:192:6:MX_SubGHz_Phy_EnterSleep 2 +../SubGHz_Phy/App/app_subghz_phy.c:210:9:MX_SubGHz_Phy_APRS_Send 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.d b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.d new file mode 100644 index 0000000..f86d0c0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.d @@ -0,0 +1,105 @@ +SubGHz_Phy/App/app_subghz_phy.o: ../SubGHz_Phy/App/app_subghz_phy.c \ + ../SubGHz_Phy/App/app_subghz_phy.h ../SubGHz_Phy/App/subghz_phy_app.h \ + ../Core/Inc/sys_app.h ../Core/Inc/sys_conf.h \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h \ + ../Utilities/sequencer/stm32_seq.h ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/usart.h ../Core/Inc/main.h ../Core/Inc/rtc.h \ + ../SubGHz_Phy/App/app_version.h +../SubGHz_Phy/App/app_subghz_phy.h: +../SubGHz_Phy/App/subghz_phy_app.h: +../Core/Inc/sys_app.h: +../Core/Inc/sys_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../Utilities/sequencer/stm32_seq.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/usart.h: +../Core/Inc/main.h: +../Core/Inc/rtc.h: +../SubGHz_Phy/App/app_version.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.o b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.o new file mode 100644 index 0000000..25109a5 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.su b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.su new file mode 100644 index 0000000..7fa9053 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/app_subghz_phy.su @@ -0,0 +1,5 @@ +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h:3168:22:LL_RCC_ClearResetFlags 4 static +../SubGHz_Phy/App/app_subghz_phy.c:79:6:MX_SubGHz_Phy_Init 32 static +../SubGHz_Phy/App/app_subghz_phy.c:133:6:MX_SubGHz_Phy_Process 192 static +../SubGHz_Phy/App/app_subghz_phy.c:192:6:MX_SubGHz_Phy_EnterSleep 16 static +../SubGHz_Phy/App/app_subghz_phy.c:210:9:MX_SubGHz_Phy_APRS_Send 40 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subdir.mk new file mode 100644 index 0000000..d1e044f --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subdir.mk @@ -0,0 +1,30 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../SubGHz_Phy/App/app_subghz_phy.c \ +../SubGHz_Phy/App/subghz_phy_app.c + +OBJS += \ +./SubGHz_Phy/App/app_subghz_phy.o \ +./SubGHz_Phy/App/subghz_phy_app.o + +C_DEPS += \ +./SubGHz_Phy/App/app_subghz_phy.d \ +./SubGHz_Phy/App/subghz_phy_app.d + + +# Each subdirectory must supply rules for building sources it contributes +SubGHz_Phy/App/%.o SubGHz_Phy/App/%.su SubGHz_Phy/App/%.cyclo: ../SubGHz_Phy/App/%.c SubGHz_Phy/App/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-SubGHz_Phy-2f-App + +clean-SubGHz_Phy-2f-App: + -$(RM) ./SubGHz_Phy/App/app_subghz_phy.cyclo ./SubGHz_Phy/App/app_subghz_phy.d ./SubGHz_Phy/App/app_subghz_phy.o ./SubGHz_Phy/App/app_subghz_phy.su ./SubGHz_Phy/App/subghz_phy_app.cyclo ./SubGHz_Phy/App/subghz_phy_app.d ./SubGHz_Phy/App/subghz_phy_app.o ./SubGHz_Phy/App/subghz_phy_app.su + +.PHONY: clean-SubGHz_Phy-2f-App + diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.cyclo b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.cyclo new file mode 100644 index 0000000..40afae4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.cyclo @@ -0,0 +1,8 @@ +../SubGHz_Phy/App/subghz_phy_app.c:96:6:SubghzApp_Init 1 +../SubGHz_Phy/App/subghz_phy_app.c:142:9:SubghzApp_Transmit 3 +../SubGHz_Phy/App/subghz_phy_app.c:160:6:SubghzApp_Sleep 1 +../SubGHz_Phy/App/subghz_phy_app.c:168:13:OnTxDone 1 +../SubGHz_Phy/App/subghz_phy_app.c:176:13:OnRxDone 1 +../SubGHz_Phy/App/subghz_phy_app.c:183:13:OnTxTimeout 1 +../SubGHz_Phy/App/subghz_phy_app.c:190:13:OnRxTimeout 1 +../SubGHz_Phy/App/subghz_phy_app.c:197:13:OnRxError 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.d b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.d new file mode 100644 index 0000000..84746f6 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.d @@ -0,0 +1,123 @@ +SubGHz_Phy/App/subghz_phy_app.o: ../SubGHz_Phy/App/subghz_phy_app.c \ + ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h ../Core/Inc/sys_app.h \ + ../Core/Inc/sys_conf.h ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h ../SubGHz_Phy/App/subghz_phy_app.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h \ + ../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h \ + ../Utilities/sequencer/stm32_seq.h ../Utilities/timer/stm32_timer.h \ + ../Core/Inc/utilities_def.h \ + ../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subghz_phy_version.h +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: +../Core/Inc/sys_app.h: +../Core/Inc/sys_conf.h: +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: +../SubGHz_Phy/App/subghz_phy_app.h: +../Middlewares/Third_Party/SubGHz_Phy/radio.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_def.h: +../Middlewares/Third_Party/SubGHz_Phy/radio_ex.h: +../Middlewares/Third_Party/SubGHz_Phy/lr_fhss_v1_base_types.h: +../Utilities/sequencer/stm32_seq.h: +../Utilities/timer/stm32_timer.h: +../Core/Inc/utilities_def.h: +../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subghz_phy_version.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.o b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.o new file mode 100644 index 0000000..ea2c95d Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.su b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.su new file mode 100644 index 0000000..2557177 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/App/subghz_phy_app.su @@ -0,0 +1,8 @@ +../SubGHz_Phy/App/subghz_phy_app.c:96:6:SubghzApp_Init 56 static +../SubGHz_Phy/App/subghz_phy_app.c:142:9:SubghzApp_Transmit 16 static +../SubGHz_Phy/App/subghz_phy_app.c:160:6:SubghzApp_Sleep 8 static +../SubGHz_Phy/App/subghz_phy_app.c:168:13:OnTxDone 8 static +../SubGHz_Phy/App/subghz_phy_app.c:176:13:OnRxDone 24 static +../SubGHz_Phy/App/subghz_phy_app.c:183:13:OnTxTimeout 8 static +../SubGHz_Phy/App/subghz_phy_app.c:190:13:OnRxTimeout 8 static +../SubGHz_Phy/App/subghz_phy_app.c:197:13:OnRxError 8 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.cyclo b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.cyclo new file mode 100644 index 0000000..e13c7eb --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.cyclo @@ -0,0 +1,7 @@ +../SubGHz_Phy/Target/radio_board_if.c:59:9:RBI_Init 1 +../SubGHz_Phy/Target/radio_board_if.c:85:9:RBI_DeInit 1 +../SubGHz_Phy/Target/radio_board_if.c:111:9:RBI_ConfigRFSwitch 1 +../SubGHz_Phy/Target/radio_board_if.c:138:9:RBI_GetTxConfig 1 +../SubGHz_Phy/Target/radio_board_if.c:164:9:RBI_IsTCXO 1 +../SubGHz_Phy/Target/radio_board_if.c:190:9:RBI_IsDCDC 1 +../SubGHz_Phy/Target/radio_board_if.c:216:9:RBI_GetRFOMaxPowerConfig 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.d b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.d new file mode 100644 index 0000000..b067680 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.d @@ -0,0 +1,96 @@ +SubGHz_Phy/Target/radio_board_if.o: ../SubGHz_Phy/Target/radio_board_if.c \ + ../SubGHz_Phy/Target/radio_board_if.h ../Core/Inc/platform.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h \ + ../Drivers/CMSIS/Include/core_cm4.h \ + ../Drivers/CMSIS/Include/cmsis_version.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h \ + ../Drivers/CMSIS/Include/mpu_armv7.h \ + ../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h \ + ../Core/Inc/stm32wlxx_hal_conf.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h \ + ../Core/Inc/main.h \ + ../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h \ + ../Core/Inc/stm32wlxx_nucleo_conf.h \ + ../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h +../SubGHz_Phy/Target/radio_board_if.h: +../Core/Inc/platform.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wlxx.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/stm32wle5xx.h: +../Drivers/CMSIS/Include/core_cm4.h: +../Drivers/CMSIS/Include/cmsis_version.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Drivers/CMSIS/Include/mpu_armv7.h: +../Drivers/CMSIS/Device/ST/STM32WLxx/Include/system_stm32wlxx.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h: +../Core/Inc/stm32wlxx_hal_conf.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rcc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_bus.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_exti.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h: +../Core/Inc/main.h: +../Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_errno.h: +../Core/Inc/stm32wlxx_nucleo_conf.h: +../Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.o b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.o new file mode 100644 index 0000000..0805b8a Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.su b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.su new file mode 100644 index 0000000..835eebc --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/radio_board_if.su @@ -0,0 +1,7 @@ +../SubGHz_Phy/Target/radio_board_if.c:59:9:RBI_Init 8 static +../SubGHz_Phy/Target/radio_board_if.c:85:9:RBI_DeInit 8 static +../SubGHz_Phy/Target/radio_board_if.c:111:9:RBI_ConfigRFSwitch 16 static +../SubGHz_Phy/Target/radio_board_if.c:138:9:RBI_GetTxConfig 8 static +../SubGHz_Phy/Target/radio_board_if.c:164:9:RBI_IsTCXO 8 static +../SubGHz_Phy/Target/radio_board_if.c:190:9:RBI_IsDCDC 8 static +../SubGHz_Phy/Target/radio_board_if.c:216:9:RBI_GetRFOMaxPowerConfig 16 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/subdir.mk new file mode 100644 index 0000000..e266cdb --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/SubGHz_Phy/Target/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../SubGHz_Phy/Target/radio_board_if.c + +OBJS += \ +./SubGHz_Phy/Target/radio_board_if.o + +C_DEPS += \ +./SubGHz_Phy/Target/radio_board_if.d + + +# Each subdirectory must supply rules for building sources it contributes +SubGHz_Phy/Target/%.o SubGHz_Phy/Target/%.su SubGHz_Phy/Target/%.cyclo: ../SubGHz_Phy/Target/%.c SubGHz_Phy/Target/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-SubGHz_Phy-2f-Target + +clean-SubGHz_Phy-2f-Target: + -$(RM) ./SubGHz_Phy/Target/radio_board_if.cyclo ./SubGHz_Phy/Target/radio_board_if.d ./SubGHz_Phy/Target/radio_board_if.o ./SubGHz_Phy/Target/radio_board_if.su + +.PHONY: clean-SubGHz_Phy-2f-Target + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.cyclo new file mode 100644 index 0000000..443e7e1 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.cyclo @@ -0,0 +1,6 @@ +../Utilities/lpm/tiny_lpm/stm32_lpm.c:121:6:UTIL_LPM_Init 1 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:128:6:UTIL_LPM_DeInit 1 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:132:6:UTIL_LPM_SetStopMode 3 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:157:6:UTIL_LPM_SetOffMode 3 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:182:17:UTIL_LPM_GetMode 3 +../Utilities/lpm/tiny_lpm/stm32_lpm.c:215:6:UTIL_LPM_EnterLowPower 3 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.d new file mode 100644 index 0000000..31852d7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.d @@ -0,0 +1,12 @@ +Utilities/lpm/tiny_lpm/stm32_lpm.o: ../Utilities/lpm/tiny_lpm/stm32_lpm.c \ + ../Utilities/lpm/tiny_lpm/stm32_lpm.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/lpm/tiny_lpm/stm32_lpm.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.o new file mode 100644 index 0000000..7d6a502 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.su new file mode 100644 index 0000000..22578f4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/stm32_lpm.su @@ -0,0 +1,6 @@ +../Utilities/lpm/tiny_lpm/stm32_lpm.c:121:6:UTIL_LPM_Init 4 static +../Utilities/lpm/tiny_lpm/stm32_lpm.c:128:6:UTIL_LPM_DeInit 4 static +../Utilities/lpm/tiny_lpm/stm32_lpm.c:132:6:UTIL_LPM_SetStopMode 32 static,ignoring_inline_asm +../Utilities/lpm/tiny_lpm/stm32_lpm.c:157:6:UTIL_LPM_SetOffMode 32 static,ignoring_inline_asm +../Utilities/lpm/tiny_lpm/stm32_lpm.c:182:17:UTIL_LPM_GetMode 24 static,ignoring_inline_asm +../Utilities/lpm/tiny_lpm/stm32_lpm.c:215:6:UTIL_LPM_EnterLowPower 24 static,ignoring_inline_asm diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/subdir.mk new file mode 100644 index 0000000..dc57e51 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/lpm/tiny_lpm/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/lpm/tiny_lpm/stm32_lpm.c + +OBJS += \ +./Utilities/lpm/tiny_lpm/stm32_lpm.o + +C_DEPS += \ +./Utilities/lpm/tiny_lpm/stm32_lpm.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/lpm/tiny_lpm/%.o Utilities/lpm/tiny_lpm/%.su Utilities/lpm/tiny_lpm/%.cyclo: ../Utilities/lpm/tiny_lpm/%.c Utilities/lpm/tiny_lpm/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-lpm-2f-tiny_lpm + +clean-Utilities-2f-lpm-2f-tiny_lpm: + -$(RM) ./Utilities/lpm/tiny_lpm/stm32_lpm.cyclo ./Utilities/lpm/tiny_lpm/stm32_lpm.d ./Utilities/lpm/tiny_lpm/stm32_lpm.o ./Utilities/lpm/tiny_lpm/stm32_lpm.su + +.PHONY: clean-Utilities-2f-lpm-2f-tiny_lpm + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.cyclo new file mode 100644 index 0000000..5de88d4 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.cyclo @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_mem.c:31:6:UTIL_MEM_cpy_8 2 +../Utilities/misc/stm32_mem.c:42:6:UTIL_MEM_cpyr_8 2 +../Utilities/misc/stm32_mem.c:54:6:UTIL_MEM_set_8 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.d new file mode 100644 index 0000000..aa500c7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.d @@ -0,0 +1,12 @@ +Utilities/misc/stm32_mem.o: ../Utilities/misc/stm32_mem.c \ + ../Utilities/misc/stm32_mem.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/misc/stm32_mem.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.o new file mode 100644 index 0000000..fd550f5 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.su new file mode 100644 index 0000000..90d582e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_mem.su @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_mem.c:31:6:UTIL_MEM_cpy_8 32 static +../Utilities/misc/stm32_mem.c:42:6:UTIL_MEM_cpyr_8 32 static +../Utilities/misc/stm32_mem.c:54:6:UTIL_MEM_set_8 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.cyclo new file mode 100644 index 0000000..b43fd35 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.cyclo @@ -0,0 +1,13 @@ +../Utilities/misc/stm32_systime.c:199:11:SysTimeAdd 2 +../Utilities/misc/stm32_systime.c:213:11:SysTimeSub 2 +../Utilities/misc/stm32_systime.c:227:6:SysTimeSet 1 +../Utilities/misc/stm32_systime.c:242:11:SysTimeGet 1 +../Utilities/misc/stm32_systime.c:259:11:SysTimeGetMcuTime 1 +../Utilities/misc/stm32_systime.c:268:10:SysTimeToMs 1 +../Utilities/misc/stm32_systime.c:278:11:SysTimeFromMs 1 +../Utilities/misc/stm32_systime.c:289:10:SysTimeMkTime 1 +../Utilities/misc/stm32_systime.c:318:6:SysTimeLocalTime 1 +../Utilities/misc/stm32_systime.c:381:17:CalendarGetMonth 6 +../Utilities/misc/stm32_systime.c:418:13:CalendarDiv86400 3 +../Utilities/misc/stm32_systime.c:444:17:CalendarDiv61 3 +../Utilities/misc/stm32_systime.c:466:13:CalendarDiv60 3 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.d new file mode 100644 index 0000000..b6045b2 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.d @@ -0,0 +1,3 @@ +Utilities/misc/stm32_systime.o: ../Utilities/misc/stm32_systime.c \ + ../Utilities/misc/stm32_systime.h +../Utilities/misc/stm32_systime.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.o new file mode 100644 index 0000000..f865a1c Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.su new file mode 100644 index 0000000..03ceef9 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_systime.su @@ -0,0 +1,13 @@ +../Utilities/misc/stm32_systime.c:199:11:SysTimeAdd 32 static +../Utilities/misc/stm32_systime.c:213:11:SysTimeSub 32 static +../Utilities/misc/stm32_systime.c:227:6:SysTimeSet 40 static +../Utilities/misc/stm32_systime.c:242:11:SysTimeGet 48 static +../Utilities/misc/stm32_systime.c:259:11:SysTimeGetMcuTime 24 static +../Utilities/misc/stm32_systime.c:268:10:SysTimeToMs 40 static +../Utilities/misc/stm32_systime.c:278:11:SysTimeFromMs 48 static +../Utilities/misc/stm32_systime.c:289:10:SysTimeMkTime 48 static +../Utilities/misc/stm32_systime.c:318:6:SysTimeLocalTime 64 static +../Utilities/misc/stm32_systime.c:381:17:CalendarGetMonth 24 static +../Utilities/misc/stm32_systime.c:418:13:CalendarDiv86400 32 static +../Utilities/misc/stm32_systime.c:444:17:CalendarDiv61 24 static +../Utilities/misc/stm32_systime.c:466:13:CalendarDiv60 32 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.cyclo new file mode 100644 index 0000000..1de6a73 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.cyclo @@ -0,0 +1,2 @@ +../Utilities/misc/stm32_tiny_sscanf.c:152:1:tiny_vfscanf 39 +../Utilities/misc/stm32_tiny_sscanf.c:983:1:tiny_sscanf 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.d new file mode 100644 index 0000000..fcb8a55 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.d @@ -0,0 +1,3 @@ +Utilities/misc/stm32_tiny_sscanf.o: ../Utilities/misc/stm32_tiny_sscanf.c \ + ../Utilities/misc/stm32_tiny_sscanf.h +../Utilities/misc/stm32_tiny_sscanf.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.o new file mode 100644 index 0000000..f8033e7 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.su new file mode 100644 index 0000000..7b09c51 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_sscanf.su @@ -0,0 +1,2 @@ +../Utilities/misc/stm32_tiny_sscanf.c:152:1:tiny_vfscanf 720 static +../Utilities/misc/stm32_tiny_sscanf.c:983:1:tiny_sscanf 28 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.cyclo new file mode 100644 index 0000000..8234188 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.cyclo @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_tiny_vsnprintf.c:91:12:ee_skip_atoi 3 +../Utilities/misc/stm32_tiny_vsnprintf.c:100:14:ee_number 23 +../Utilities/misc/stm32_tiny_vsnprintf.c:485:5:tiny_vsnprintf_like 25 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.d new file mode 100644 index 0000000..68bbb5b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.d @@ -0,0 +1,4 @@ +Utilities/misc/stm32_tiny_vsnprintf.o: \ + ../Utilities/misc/stm32_tiny_vsnprintf.c \ + ../Utilities/misc/stm32_tiny_vsnprintf.h +../Utilities/misc/stm32_tiny_vsnprintf.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.o new file mode 100644 index 0000000..7570b1c Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.su new file mode 100644 index 0000000..dcaa3ff --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/stm32_tiny_vsnprintf.su @@ -0,0 +1,3 @@ +../Utilities/misc/stm32_tiny_vsnprintf.c:91:12:ee_skip_atoi 24 static +../Utilities/misc/stm32_tiny_vsnprintf.c:100:14:ee_number 104 static +../Utilities/misc/stm32_tiny_vsnprintf.c:485:5:tiny_vsnprintf_like 80 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/subdir.mk new file mode 100644 index 0000000..2d33bbe --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/misc/subdir.mk @@ -0,0 +1,36 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/misc/stm32_mem.c \ +../Utilities/misc/stm32_systime.c \ +../Utilities/misc/stm32_tiny_sscanf.c \ +../Utilities/misc/stm32_tiny_vsnprintf.c + +OBJS += \ +./Utilities/misc/stm32_mem.o \ +./Utilities/misc/stm32_systime.o \ +./Utilities/misc/stm32_tiny_sscanf.o \ +./Utilities/misc/stm32_tiny_vsnprintf.o + +C_DEPS += \ +./Utilities/misc/stm32_mem.d \ +./Utilities/misc/stm32_systime.d \ +./Utilities/misc/stm32_tiny_sscanf.d \ +./Utilities/misc/stm32_tiny_vsnprintf.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/misc/%.o Utilities/misc/%.su Utilities/misc/%.cyclo: ../Utilities/misc/%.c Utilities/misc/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-misc + +clean-Utilities-2f-misc: + -$(RM) ./Utilities/misc/stm32_mem.cyclo ./Utilities/misc/stm32_mem.d ./Utilities/misc/stm32_mem.o ./Utilities/misc/stm32_mem.su ./Utilities/misc/stm32_systime.cyclo ./Utilities/misc/stm32_systime.d ./Utilities/misc/stm32_systime.o ./Utilities/misc/stm32_systime.su ./Utilities/misc/stm32_tiny_sscanf.cyclo ./Utilities/misc/stm32_tiny_sscanf.d ./Utilities/misc/stm32_tiny_sscanf.o ./Utilities/misc/stm32_tiny_sscanf.su ./Utilities/misc/stm32_tiny_vsnprintf.cyclo ./Utilities/misc/stm32_tiny_vsnprintf.d ./Utilities/misc/stm32_tiny_vsnprintf.o ./Utilities/misc/stm32_tiny_vsnprintf.su + +.PHONY: clean-Utilities-2f-misc + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.cyclo new file mode 100644 index 0000000..7c0fa9b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.cyclo @@ -0,0 +1,18 @@ +../Utilities/sequencer/stm32_seq.c:180:6:UTIL_SEQ_Init 2 +../Utilities/sequencer/stm32_seq.c:197:6:UTIL_SEQ_DeInit 1 +../Utilities/sequencer/stm32_seq.c:207:6:UTIL_SEQ_Run 8 +../Utilities/sequencer/stm32_seq.c:323:6:UTIL_SEQ_RegTask 1 +../Utilities/sequencer/stm32_seq.c:335:6:UTIL_SEQ_SetTask 1 +../Utilities/sequencer/stm32_seq.c:347:10:UTIL_SEQ_IsSchedulableTask 2 +../Utilities/sequencer/stm32_seq.c:361:6:UTIL_SEQ_PauseTask 1 +../Utilities/sequencer/stm32_seq.c:372:10:UTIL_SEQ_IsPauseTask 1 +../Utilities/sequencer/stm32_seq.c:383:6:UTIL_SEQ_ResumeTask 1 +../Utilities/sequencer/stm32_seq.c:394:6:UTIL_SEQ_SetEvt 1 +../Utilities/sequencer/stm32_seq.c:405:6:UTIL_SEQ_ClrEvt 1 +../Utilities/sequencer/stm32_seq.c:416:6:UTIL_SEQ_WaitEvt 3 +../Utilities/sequencer/stm32_seq.c:469:15:UTIL_SEQ_IsEvtPend 1 +../Utilities/sequencer/stm32_seq.c:475:13:UTIL_SEQ_EvtIdle 1 +../Utilities/sequencer/stm32_seq.c:482:13:UTIL_SEQ_Idle 1 +../Utilities/sequencer/stm32_seq.c:487:13:UTIL_SEQ_PreIdle 1 +../Utilities/sequencer/stm32_seq.c:495:13:UTIL_SEQ_PostIdle 1 +../Utilities/sequencer/stm32_seq.c:518:9:SEQ_BitPosition 4 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.d new file mode 100644 index 0000000..a960a74 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.d @@ -0,0 +1,12 @@ +Utilities/sequencer/stm32_seq.o: ../Utilities/sequencer/stm32_seq.c \ + ../Utilities/sequencer/stm32_seq.h ../Core/Inc/utilities_conf.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/sequencer/stm32_seq.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.o new file mode 100644 index 0000000..8c69580 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.su new file mode 100644 index 0000000..04dcb9e --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/stm32_seq.su @@ -0,0 +1,18 @@ +../Utilities/sequencer/stm32_seq.c:180:6:UTIL_SEQ_Init 16 static +../Utilities/sequencer/stm32_seq.c:197:6:UTIL_SEQ_DeInit 4 static +../Utilities/sequencer/stm32_seq.c:207:6:UTIL_SEQ_Run 72 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:323:6:UTIL_SEQ_RegTask 40 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:335:6:UTIL_SEQ_SetTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:347:10:UTIL_SEQ_IsSchedulableTask 40 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:361:6:UTIL_SEQ_PauseTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:372:10:UTIL_SEQ_IsPauseTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:383:6:UTIL_SEQ_ResumeTask 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:394:6:UTIL_SEQ_SetEvt 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:405:6:UTIL_SEQ_ClrEvt 32 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:416:6:UTIL_SEQ_WaitEvt 40 static,ignoring_inline_asm +../Utilities/sequencer/stm32_seq.c:469:15:UTIL_SEQ_IsEvtPend 16 static +../Utilities/sequencer/stm32_seq.c:475:13:UTIL_SEQ_EvtIdle 16 static +../Utilities/sequencer/stm32_seq.c:482:13:UTIL_SEQ_Idle 4 static +../Utilities/sequencer/stm32_seq.c:487:13:UTIL_SEQ_PreIdle 4 static +../Utilities/sequencer/stm32_seq.c:495:13:UTIL_SEQ_PostIdle 4 static +../Utilities/sequencer/stm32_seq.c:518:9:SEQ_BitPosition 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/subdir.mk new file mode 100644 index 0000000..40387a8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/sequencer/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/sequencer/stm32_seq.c + +OBJS += \ +./Utilities/sequencer/stm32_seq.o + +C_DEPS += \ +./Utilities/sequencer/stm32_seq.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/sequencer/%.o Utilities/sequencer/%.su Utilities/sequencer/%.cyclo: ../Utilities/sequencer/%.c Utilities/sequencer/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-sequencer + +clean-Utilities-2f-sequencer: + -$(RM) ./Utilities/sequencer/stm32_seq.cyclo ./Utilities/sequencer/stm32_seq.d ./Utilities/sequencer/stm32_seq.o ./Utilities/sequencer/stm32_seq.su + +.PHONY: clean-Utilities-2f-sequencer + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.cyclo new file mode 100644 index 0000000..705cd52 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.cyclo @@ -0,0 +1,18 @@ +../Utilities/timer/stm32_timer.c:116:21:UTIL_TIMER_Init 1 +../Utilities/timer/stm32_timer.c:123:21:UTIL_TIMER_DeInit 1 +../Utilities/timer/stm32_timer.c:128:21:UTIL_TIMER_Create 3 +../Utilities/timer/stm32_timer.c:149:21:UTIL_TIMER_Start 7 +../Utilities/timer/stm32_timer.c:199:21:UTIL_TIMER_StartWithPeriod 3 +../Utilities/timer/stm32_timer.c:219:21:UTIL_TIMER_Stop 8 +../Utilities/timer/stm32_timer.c:285:21:UTIL_TIMER_SetPeriod 3 +../Utilities/timer/stm32_timer.c:305:21:UTIL_TIMER_SetReloadMode 2 +../Utilities/timer/stm32_timer.c:320:21:UTIL_TIMER_GetRemainingTime 3 +../Utilities/timer/stm32_timer.c:342:10:UTIL_TIMER_IsRunning 2 +../Utilities/timer/stm32_timer.c:354:10:UTIL_TIMER_GetFirstRemainingTime 2 +../Utilities/timer/stm32_timer.c:365:6:UTIL_TIMER_IRQ_Handler 11 +../Utilities/timer/stm32_timer.c:417:19:UTIL_TIMER_GetCurrentTime 1 +../Utilities/timer/stm32_timer.c:423:19:UTIL_TIMER_GetElapsedTime 1 +../Utilities/timer/stm32_timer.c:448:6:TimerExists 3 +../Utilities/timer/stm32_timer.c:468:6:TimerSetTimeout 2 +../Utilities/timer/stm32_timer.c:489:6:TimerInsertTimer 3 +../Utilities/timer/stm32_timer.c:521:6:TimerInsertNewHeadTimer 2 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.d new file mode 100644 index 0000000..4bd6c91 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.d @@ -0,0 +1,13 @@ +Utilities/timer/stm32_timer.o: ../Utilities/timer/stm32_timer.c \ + ../Utilities/timer/stm32_timer.h \ + ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Core/Inc/utilities_conf.h \ + ../Utilities/misc/stm32_mem.h ../Utilities/misc/stm32_tiny_vsnprintf.h \ + ../Core/Inc/utilities_def.h +../Utilities/timer/stm32_timer.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Core/Inc/utilities_conf.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.o new file mode 100644 index 0000000..46b8a68 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.su new file mode 100644 index 0000000..12ca124 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/stm32_timer.su @@ -0,0 +1,18 @@ +../Utilities/timer/stm32_timer.c:116:21:UTIL_TIMER_Init 8 static +../Utilities/timer/stm32_timer.c:123:21:UTIL_TIMER_DeInit 8 static +../Utilities/timer/stm32_timer.c:128:21:UTIL_TIMER_Create 24 static +../Utilities/timer/stm32_timer.c:149:21:UTIL_TIMER_Start 48 static,ignoring_inline_asm +../Utilities/timer/stm32_timer.c:199:21:UTIL_TIMER_StartWithPeriod 24 static +../Utilities/timer/stm32_timer.c:219:21:UTIL_TIMER_Stop 40 static,ignoring_inline_asm +../Utilities/timer/stm32_timer.c:285:21:UTIL_TIMER_SetPeriod 24 static +../Utilities/timer/stm32_timer.c:305:21:UTIL_TIMER_SetReloadMode 24 static +../Utilities/timer/stm32_timer.c:320:21:UTIL_TIMER_GetRemainingTime 24 static +../Utilities/timer/stm32_timer.c:342:10:UTIL_TIMER_IsRunning 16 static +../Utilities/timer/stm32_timer.c:354:10:UTIL_TIMER_GetFirstRemainingTime 16 static +../Utilities/timer/stm32_timer.c:365:6:UTIL_TIMER_IRQ_Handler 48 static,ignoring_inline_asm +../Utilities/timer/stm32_timer.c:417:19:UTIL_TIMER_GetCurrentTime 16 static +../Utilities/timer/stm32_timer.c:423:19:UTIL_TIMER_GetElapsedTime 24 static +../Utilities/timer/stm32_timer.c:448:6:TimerExists 24 static +../Utilities/timer/stm32_timer.c:468:6:TimerSetTimeout 32 static +../Utilities/timer/stm32_timer.c:489:6:TimerInsertTimer 24 static +../Utilities/timer/stm32_timer.c:521:6:TimerInsertNewHeadTimer 24 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/subdir.mk new file mode 100644 index 0000000..951aaf7 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/timer/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/timer/stm32_timer.c + +OBJS += \ +./Utilities/timer/stm32_timer.o + +C_DEPS += \ +./Utilities/timer/stm32_timer.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/timer/%.o Utilities/timer/%.su Utilities/timer/%.cyclo: ../Utilities/timer/%.c Utilities/timer/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-timer + +clean-Utilities-2f-timer: + -$(RM) ./Utilities/timer/stm32_timer.cyclo ./Utilities/timer/stm32_timer.d ./Utilities/timer/stm32_timer.o ./Utilities/timer/stm32_timer.su + +.PHONY: clean-Utilities-2f-timer + diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.cyclo b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.cyclo new file mode 100644 index 0000000..64319a0 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.cyclo @@ -0,0 +1,26 @@ +../Utilities/trace/adv_trace/stm32_adv_trace.c:165:25:UTIL_ADV_TRACE_Init 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:181:25:UTIL_ADV_TRACE_DeInit 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:187:9:UTIL_ADV_TRACE_IsBufferEmpty 2 +../Utilities/trace/adv_trace/stm32_adv_trace.c:195:25:UTIL_ADV_TRACE_StartRxProcess 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:202:25:UTIL_ADV_TRACE_COND_FSend 7 +../Utilities/trace/adv_trace/stm32_adv_trace.c:295:25:UTIL_ADV_TRACE_FSend 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:308:25:UTIL_ADV_TRACE_COND_ZCSend_Allocation 7 +../Utilities/trace/adv_trace/stm32_adv_trace.c:356:25:UTIL_ADV_TRACE_COND_ZCSend_Finalize 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:362:25:UTIL_ADV_TRACE_ZCSend_Allocation 2 +../Utilities/trace/adv_trace/stm32_adv_trace.c:386:25:UTIL_ADV_TRACE_ZCSend_Finalize 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:393:25:UTIL_ADV_TRACE_COND_Send 8 +../Utilities/trace/adv_trace/stm32_adv_trace.c:448:25:UTIL_ADV_TRACE_Send 3 +../Utilities/trace/adv_trace/stm32_adv_trace.c:486:6:UTIL_ADV_TRACE_RegisterTimeStampFunction 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:491:6:UTIL_ADV_TRACE_SetVerboseLevel 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:496:9:UTIL_ADV_TRACE_GetVerboseLevel 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:501:6:UTIL_ADV_TRACE_SetRegion 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:506:10:UTIL_ADV_TRACE_GetRegion 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:511:6:UTIL_ADV_TRACE_ResetRegion 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:517:13:UTIL_ADV_TRACE_PreSendHook 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:521:13:UTIL_ADV_TRACE_PostSendHook 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:537:32:TRACE_Send 7 +../Utilities/trace/adv_trace/stm32_adv_trace.c:608:13:TRACE_TxCpltCallback 8 +../Utilities/trace/adv_trace/stm32_adv_trace.c:703:16:TRACE_AllocateBufer 8 +../Utilities/trace/adv_trace/stm32_adv_trace.c:794:13:TRACE_Lock 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:805:13:TRACE_UnLock 1 +../Utilities/trace/adv_trace/stm32_adv_trace.c:816:17:TRACE_IsLocked 1 diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.d b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.d new file mode 100644 index 0000000..4114487 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.d @@ -0,0 +1,13 @@ +Utilities/trace/adv_trace/stm32_adv_trace.o: \ + ../Utilities/trace/adv_trace/stm32_adv_trace.c \ + ../Utilities/trace/adv_trace/stm32_adv_trace.h \ + ../Core/Inc/utilities_conf.h ../Drivers/CMSIS/Include/cmsis_compiler.h \ + ../Drivers/CMSIS/Include/cmsis_gcc.h ../Utilities/misc/stm32_mem.h \ + ../Utilities/misc/stm32_tiny_vsnprintf.h ../Core/Inc/utilities_def.h +../Utilities/trace/adv_trace/stm32_adv_trace.h: +../Core/Inc/utilities_conf.h: +../Drivers/CMSIS/Include/cmsis_compiler.h: +../Drivers/CMSIS/Include/cmsis_gcc.h: +../Utilities/misc/stm32_mem.h: +../Utilities/misc/stm32_tiny_vsnprintf.h: +../Core/Inc/utilities_def.h: diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.o b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.o new file mode 100644 index 0000000..ccb6aa4 Binary files /dev/null and b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.o differ diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.su b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.su new file mode 100644 index 0000000..697208d --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/stm32_adv_trace.su @@ -0,0 +1,26 @@ +../Utilities/trace/adv_trace/stm32_adv_trace.c:165:25:UTIL_ADV_TRACE_Init 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:181:25:UTIL_ADV_TRACE_DeInit 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:187:9:UTIL_ADV_TRACE_IsBufferEmpty 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:195:25:UTIL_ADV_TRACE_StartRxProcess 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:202:25:UTIL_ADV_TRACE_COND_FSend 60 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:295:25:UTIL_ADV_TRACE_FSend 272 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:308:25:UTIL_ADV_TRACE_COND_ZCSend_Allocation 56 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:356:25:UTIL_ADV_TRACE_COND_ZCSend_Finalize 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:362:25:UTIL_ADV_TRACE_ZCSend_Allocation 32 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:386:25:UTIL_ADV_TRACE_ZCSend_Finalize 8 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:393:25:UTIL_ADV_TRACE_COND_Send 56 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:448:25:UTIL_ADV_TRACE_Send 32 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:486:6:UTIL_ADV_TRACE_RegisterTimeStampFunction 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:491:6:UTIL_ADV_TRACE_SetVerboseLevel 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:496:9:UTIL_ADV_TRACE_GetVerboseLevel 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:501:6:UTIL_ADV_TRACE_SetRegion 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:506:10:UTIL_ADV_TRACE_GetRegion 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:511:6:UTIL_ADV_TRACE_ResetRegion 16 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:517:13:UTIL_ADV_TRACE_PreSendHook 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:521:13:UTIL_ADV_TRACE_PostSendHook 4 static +../Utilities/trace/adv_trace/stm32_adv_trace.c:537:32:TRACE_Send 40 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:608:13:TRACE_TxCpltCallback 40 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:703:16:TRACE_AllocateBufer 32 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:794:13:TRACE_Lock 24 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:805:13:TRACE_UnLock 24 static,ignoring_inline_asm +../Utilities/trace/adv_trace/stm32_adv_trace.c:816:17:TRACE_IsLocked 4 static diff --git a/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/subdir.mk b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/subdir.mk new file mode 100644 index 0000000..abb6ef8 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/Utilities/trace/adv_trace/subdir.mk @@ -0,0 +1,27 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +# Add inputs and outputs from these tool invocations to the build variables +C_SRCS += \ +../Utilities/trace/adv_trace/stm32_adv_trace.c + +OBJS += \ +./Utilities/trace/adv_trace/stm32_adv_trace.o + +C_DEPS += \ +./Utilities/trace/adv_trace/stm32_adv_trace.d + + +# Each subdirectory must supply rules for building sources it contributes +Utilities/trace/adv_trace/%.o Utilities/trace/adv_trace/%.su Utilities/trace/adv_trace/%.cyclo: ../Utilities/trace/adv_trace/%.c Utilities/trace/adv_trace/subdir.mk + arm-none-eabi-gcc "$<" -mcpu=cortex-m4 -std=gnu11 -g3 -DDEBUG -DCORE_CM4 -DUSE_HAL_DRIVER -DSTM32WLE5xx -c -I../Core/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc -I../Drivers/STM32WLxx_HAL_Driver/Inc/Legacy -I../Drivers/CMSIS/Device/ST/STM32WLxx/Include -I../Drivers/CMSIS/Include -I../SubGHz_Phy/App -I../SubGHz_Phy/Target -I../Utilities/trace/adv_trace -I../Utilities/misc -I../Utilities/sequencer -I../Utilities/timer -I../Utilities/lpm/tiny_lpm -I../Middlewares/Third_Party/SubGHz_Phy -I../Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver -I../Drivers/BSP/LoRa-GPS-Tracker -O0 -ffunction-sections -fdata-sections -Wall -fstack-usage -fcyclomatic-complexity -MMD -MP -MF"$(@:%.o=%.d)" -MT"$@" --specs=nano.specs -mfloat-abi=soft -mthumb -o "$@" + +clean: clean-Utilities-2f-trace-2f-adv_trace + +clean-Utilities-2f-trace-2f-adv_trace: + -$(RM) ./Utilities/trace/adv_trace/stm32_adv_trace.cyclo ./Utilities/trace/adv_trace/stm32_adv_trace.d ./Utilities/trace/adv_trace/stm32_adv_trace.o ./Utilities/trace/adv_trace/stm32_adv_trace.su + +.PHONY: clean-Utilities-2f-trace-2f-adv_trace + diff --git a/firmware/LoRa-GPS-Tracker/Debug/makefile b/firmware/LoRa-GPS-Tracker/Debug/makefile new file mode 100644 index 0000000..b8eff0a --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/makefile @@ -0,0 +1,103 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +-include ../makefile.init + +RM := rm -rf + +# All of the sources participating in the build are defined here +-include sources.mk +-include Utilities/trace/adv_trace/subdir.mk +-include Utilities/timer/subdir.mk +-include Utilities/sequencer/subdir.mk +-include Utilities/misc/subdir.mk +-include Utilities/lpm/tiny_lpm/subdir.mk +-include SubGHz_Phy/Target/subdir.mk +-include SubGHz_Phy/App/subdir.mk +-include Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/subdir.mk +-include Drivers/STM32WLxx_HAL_Driver/Src/subdir.mk +-include Drivers/BSP/LoRa-GPS-Tracker/subdir.mk +-include Core/Startup/subdir.mk +-include Core/Src/subdir.mk +-include objects.mk + +ifneq ($(MAKECMDGOALS),clean) +ifneq ($(strip $(S_DEPS)),) +-include $(S_DEPS) +endif +ifneq ($(strip $(S_UPPER_DEPS)),) +-include $(S_UPPER_DEPS) +endif +ifneq ($(strip $(C_DEPS)),) +-include $(C_DEPS) +endif +endif + +-include ../makefile.defs + +OPTIONAL_TOOL_DEPS := \ +$(wildcard ../makefile.defs) \ +$(wildcard ../makefile.init) \ +$(wildcard ../makefile.targets) \ + + +BUILD_ARTIFACT_NAME := LoRa-GPS-Tracker +BUILD_ARTIFACT_EXTENSION := elf +BUILD_ARTIFACT_PREFIX := +BUILD_ARTIFACT := $(BUILD_ARTIFACT_PREFIX)$(BUILD_ARTIFACT_NAME)$(if $(BUILD_ARTIFACT_EXTENSION),.$(BUILD_ARTIFACT_EXTENSION),) + +# Add inputs and outputs from these tool invocations to the build variables +EXECUTABLES += \ +LoRa-GPS-Tracker.elf \ + +MAP_FILES += \ +LoRa-GPS-Tracker.map \ + +SIZE_OUTPUT += \ +default.size.stdout \ + +OBJDUMP_LIST += \ +LoRa-GPS-Tracker.list \ + + +# All Target +all: main-build + +# Main-build Target +main-build: LoRa-GPS-Tracker.elf secondary-outputs + +# Tool invocations +LoRa-GPS-Tracker.elf LoRa-GPS-Tracker.map: $(OBJS) $(USER_OBJS) F:\Git\LoRa-GPS-Tracker\firmware\LoRa-GPS-Tracker\STM32WLE5CCUX_FLASH.ld makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-gcc -o "LoRa-GPS-Tracker.elf" @"objects.list" $(USER_OBJS) $(LIBS) -mcpu=cortex-m4 -T"F:\Git\LoRa-GPS-Tracker\firmware\LoRa-GPS-Tracker\STM32WLE5CCUX_FLASH.ld" --specs=nosys.specs -Wl,-Map="LoRa-GPS-Tracker.map" -Wl,--gc-sections -static --specs=nano.specs -mfloat-abi=soft -mthumb -Wl,--start-group -lc -lm -Wl,--end-group + @echo 'Finished building target: $@' + @echo ' ' + +default.size.stdout: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-size $(EXECUTABLES) + @echo 'Finished building: $@' + @echo ' ' + +LoRa-GPS-Tracker.list: $(EXECUTABLES) makefile objects.list $(OPTIONAL_TOOL_DEPS) + arm-none-eabi-objdump -h -S $(EXECUTABLES) > "LoRa-GPS-Tracker.list" + @echo 'Finished building: $@' + @echo ' ' + +# Other Targets +clean: + -$(RM) LoRa-GPS-Tracker.elf LoRa-GPS-Tracker.list LoRa-GPS-Tracker.map default.size.stdout + -@echo ' ' + +secondary-outputs: $(SIZE_OUTPUT) $(OBJDUMP_LIST) + +fail-specified-linker-script-missing: + @echo 'Error: Cannot find the specified linker script. Check the linker settings in the build configuration.' + @exit 2 + +warn-no-linker-script-specified: + @echo 'Warning: No linker script specified. Check the linker settings in the build configuration.' + +.PHONY: all clean dependents main-build fail-specified-linker-script-missing warn-no-linker-script-specified + +-include ../makefile.targets diff --git a/firmware/LoRa-GPS-Tracker/Debug/objects.list b/firmware/LoRa-GPS-Tracker/Debug/objects.list new file mode 100644 index 0000000..ca92f40 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/objects.list @@ -0,0 +1,58 @@ +"./Core/Src/adc.o" +"./Core/Src/dma.o" +"./Core/Src/gpio.o" +"./Core/Src/main.o" +"./Core/Src/rtc.o" +"./Core/Src/stm32_lpm_if.o" +"./Core/Src/stm32wlxx_hal_msp.o" +"./Core/Src/stm32wlxx_it.o" +"./Core/Src/subghz.o" +"./Core/Src/sys_app.o" +"./Core/Src/sys_debug.o" +"./Core/Src/syscalls.o" +"./Core/Src/sysmem.o" +"./Core/Src/system_stm32wlxx.o" +"./Core/Src/timer_if.o" +"./Core/Src/usart.o" +"./Core/Src/usart_if.o" +"./Core/Startup/startup_stm32wle5ccux.o" +"./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo.o" +"./Drivers/BSP/LoRa-GPS-Tracker/stm32wlxx_nucleo_radio.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_adc_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_cortex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_dma_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_exti.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_flash_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_gpio.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_pwr_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rcc_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_rtc_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_subghz.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_tim_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_hal_uart_ex.o" +"./Drivers/STM32WLxx_HAL_Driver/Src/stm32wlxx_ll_adc.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/lr_fhss_mac.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_driver.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/radio_fw.o" +"./Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver/wl_lr_fhss.o" +"./SubGHz_Phy/App/app_subghz_phy.o" +"./SubGHz_Phy/App/subghz_phy_app.o" +"./SubGHz_Phy/Target/radio_board_if.o" +"./Utilities/lpm/tiny_lpm/stm32_lpm.o" +"./Utilities/misc/stm32_mem.o" +"./Utilities/misc/stm32_systime.o" +"./Utilities/misc/stm32_tiny_sscanf.o" +"./Utilities/misc/stm32_tiny_vsnprintf.o" +"./Utilities/sequencer/stm32_seq.o" +"./Utilities/timer/stm32_timer.o" +"./Utilities/trace/adv_trace/stm32_adv_trace.o" diff --git a/firmware/LoRa-GPS-Tracker/Debug/objects.mk b/firmware/LoRa-GPS-Tracker/Debug/objects.mk new file mode 100644 index 0000000..820854b --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/objects.mk @@ -0,0 +1,9 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +USER_OBJS := + +LIBS := + diff --git a/firmware/LoRa-GPS-Tracker/Debug/sources.mk b/firmware/LoRa-GPS-Tracker/Debug/sources.mk new file mode 100644 index 0000000..655a279 --- /dev/null +++ b/firmware/LoRa-GPS-Tracker/Debug/sources.mk @@ -0,0 +1,37 @@ +################################################################################ +# Automatically-generated file. Do not edit! +# Toolchain: GNU Tools for STM32 (11.3.rel1) +################################################################################ + +ELF_SRCS := +OBJ_SRCS := +S_SRCS := +C_SRCS := +S_UPPER_SRCS := +O_SRCS := +CYCLO_FILES := +SIZE_OUTPUT := +OBJDUMP_LIST := +SU_FILES := +EXECUTABLES := +OBJS := +MAP_FILES := +S_DEPS := +S_UPPER_DEPS := +C_DEPS := + +# Every subdirectory with source files must be described here +SUBDIRS := \ +Core/Src \ +Core/Startup \ +Drivers/BSP/LoRa-GPS-Tracker \ +Drivers/STM32WLxx_HAL_Driver/Src \ +Middlewares/Third_Party/SubGHz_Phy/stm32_radio_driver \ +SubGHz_Phy/App \ +SubGHz_Phy/Target \ +Utilities/lpm/tiny_lpm \ +Utilities/misc \ +Utilities/sequencer \ +Utilities/timer \ +Utilities/trace/adv_trace \ +