{"payload":{"header_redesign_enabled":false,"results":[{"id":"50612019","archived":false,"color":"#b2b7f8","followers":0,"has_funding_file":false,"hl_name":"KennethWilke/capi-parity","hl_trunc_description":"A sample CAPI project that utilizes an FPGA for generating parity","language":"Verilog","mirror":false,"owned_by_organization":false,"public":true,"repo":{"repository":{"id":50612019,"name":"capi-parity","owner_id":2534692,"owner_login":"KennethWilke","updated_at":"2016-02-05T18:55:21.105Z","has_issues":true}},"sponsorable":false,"topics":[],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":63,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253AKennethWilke%252Fcapi-parity%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/KennethWilke/capi-parity/star":{"post":"HoJty_TLbG9Ekj075o7egWR8x9xL1tZN60vVYPD4a3vHMFdwdPKxXg13Vem0pcXT5BGf1u4NBwxlC--lPwmw9w"},"/KennethWilke/capi-parity/unstar":{"post":"57vDCLzgW7zhEmvPTawzL4yjNTqtRXZaZ_zKzCMDJp-gE4sUuTwiA1o_NsWU49TTIO3V-EHsZ-u3ygwJsBWbwA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"_oCaDZXAFwa4_EKnWDWwXaWUAo49PzC3px01tcwdisZWdp28ayq0YghvFdzF2d6PDVRxYt3QNiptjSTCWP_lbg"}}},"title":"Repository search results"}