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handling reset

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kenneth-wilke
kenneth-wilke committed Feb 15, 2016
1 parent c587982 commit 39e56d8647964164b0a72ea931b804ff60dfd533
Showing with 21 additions and 2 deletions.
  1. +12 −2 parity_afu.sv
  2. +9 −0 shift_register.sv
@@ -14,16 +14,26 @@ module parity_afu (
input MMIOInterfaceInput mmio_in,
output MMIOInterfaceOutput mmio_out);

logic jdone;

shift_register jdone_shift(
.clock(clock),
.in(jdone),
.out(job_out.done));

assign job_out.running = 0,
job_out.done = 0,
job_out.cack = 0,
job_out.error = 0,
job_out.yield = 0,
timebase_request = 0,
parity_enabled = 0;

always_ff @(posedge clock) begin
$display("Clock edge!");
if(job_in.valid & job_in.command == RESET) begin
jdone <= 1;
end else begin
jdone <= 0;
end
end

endmodule
@@ -0,0 +1,9 @@
module shift_register (
input logic clock,
input logic in,
output logic out);

always_ff @ (posedge clock) begin
out <= in;
end
endmodule

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