Coursework and projects regarding the design of field-programmable-gate-arrays (FPGA) model applications in System Verilog Hardware Description Language at the University of Washington
Provides knowledge, theoretical background, and experience practicing with tools and techniques for design/modeling complex digital systems with SystemVerilog hardware description language, as well as concepts of maintaining signal integrity, managing power consumption, and ensuring robust intra- and inter-system communication. Labs are complex projects imposing combinational and sequential logic design on programming algorithms, various audio, signals, and controller drivers.
Overview of digital computer systems through concepts of logic, Boolean algebra, combinational and sequential circuits, logic design, programmable logic devices, and the design and operation of digital computers, including ALU, memory, and I/O. The last project is a design of a tug of war game between two players on FPGA in SystemVerilog HDL, displaying the current state of the game and score with user inputs.