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Mark MIPS lwc1/swc1 as only available on platforms with float support

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sp1187 committed May 27, 2018
1 parent da357ad commit 045099f3ba2f4201ce8dce29fecd679d45732241
Showing with 35 additions and 35 deletions.
  1. +1 −1 Archs/MIPS/CMipsInstruction.h
  2. +21 −21 Archs/MIPS/MipsOpcodes.cpp
  3. +13 −13 Archs/MIPS/MipsOpcodes.h
@@ -11,7 +11,7 @@ enum class MipsRegisterType
FpuControl,
Cop0,
Ps2Cop2,
PsxCop2Data,
PsxCop2Data,
PsxCop2Control,
VfpuVector,
VfpuMatrix,
@@ -44,7 +44,7 @@ const tMipsOpcode MipsOpcodes[] = {
{ "xori", "t,s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_IGNORERTD },
{ "xori", "s,i16", MIPS_OP(0x0E), MA_MIPS1, MO_RST },
{ "lui", "t,i16", MIPS_OP(0x0F), MA_MIPS1, MO_IGNORERTD },
{ "cop2", "i25", MIPS_OP(0x12)|1<<25, MA_PSX, 0 },
{ "cop2", "i25", MIPS_OP(0x12)|(1<<25), MA_PSX, 0 },
{ "beql", "s,t,i16", MIPS_OP(0x14), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "beqzl", "s,i16", MIPS_OP(0x14), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
{ "bnel", "s,t,i16", MIPS_OP(0x15), MA_MIPS2, MO_IPCR|MO_DELAY|MO_NODELAYSLOT },
@@ -101,12 +101,12 @@ const tMipsOpcode MipsOpcodes[] = {
{ "cache", "jc,(s)", MIPS_OP(0x2F), MA_MIPS2, 0 },
{ "ll", "t,i16(s)", MIPS_OP(0x30), MA_MIPS2, MO_DELAYRT|MO_IGNORERTD },
{ "ll", "t,(s)", MIPS_OP(0x30), MA_MIPS2, MO_DELAYRT|MO_IGNORERTD },
{ "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "lwc2", "gt,i16(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lwc2", "gt,(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lwc1", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
{ "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
{ "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
{ "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, MO_FPU },
{ "lwc2", "gt,i16(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lwc2", "gt,(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lv.s", "vt,i16(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED },
{ "lv.s", "vt,(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED },
{ "lld", "t,i16(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT },
@@ -128,12 +128,12 @@ const tMipsOpcode MipsOpcodes[] = {
{ "ld", "t,(s)", MIPS_OP(0x37), MA_MIPS3, MO_64BIT|MO_DELAYRT },
{ "sc", "t,i16(s)", MIPS_OP(0x38), MA_MIPS2, 0 },
{ "sc", "t,(s)", MIPS_OP(0x38), MA_MIPS2, 0 },
{ "swc1", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "swc2", "gt,i16(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "swc2", "gt,(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "swc1", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
{ "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
{ "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
{ "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, MO_FPU },
{ "swc2", "gt,i16(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "swc2", "gt,(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "sv.s", "vt,i16(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED },
{ "sv.s", "vt,(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED },
{ "scd", "t,i16(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT },
@@ -571,9 +571,9 @@ const tMipsOpcode MipsOpcodes[] = {
{ "ctc2", "t,Rc", MIPS_COP2(0x06), MA_RSP, 0 },
// VVVVVV VVVVV ttttt -------- C DDDDDDD
{ "mfv", "t,vd", MIPS_COP2(0x03), MA_PSP, MO_VFPU|MO_VFPU_SINGLE },
{ "mfvc", "t,vc", MIPS_COP2(0x03) | 0x80, MA_PSP, MO_VFPU },
{ "mfvc", "t,vc", MIPS_COP2(0x03)|0x80, MA_PSP, MO_VFPU },
{ "mtv", "t,vd", MIPS_COP2(0x07), MA_PSP, MO_VFPU|MO_VFPU_SINGLE },
{ "mtvc", "t,vc", MIPS_COP2(0x07) | 0x80, MA_PSP, MO_VFPU },
{ "mtvc", "t,vc", MIPS_COP2(0x07)|0x80, MA_PSP, MO_VFPU },
// COP2BC: ? indicates any, * indicates all
@@ -690,8 +690,8 @@ const tMipsOpcode MipsOpcodes[] = {
{ "vf2iu.S", "vd,vs,i5", MIPS_VFPU4(0x12), MA_PSP, MO_VFPU },
{ "vf2id.S", "vd,vs,i5", MIPS_VFPU4(0x13), MA_PSP, MO_VFPU },
{ "vi2f.S", "vd,vs,i5", MIPS_VFPU4(0x14), MA_PSP, MO_VFPU },
{ "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15) | 0, MA_PSP, MO_VFPU },
{ "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15) | (1<<19), MA_PSP, MO_VFPU },
{ "vcmovt.S", "vd,vs,i5", MIPS_VFPU4(0x15)|0, MA_PSP, MO_VFPU },
{ "vcmovf.S", "vd,vs,i5", MIPS_VFPU4(0x15)|(1<<19), MA_PSP, MO_VFPU },
{ "vwbn.S", "vd,vs,i5", MIPS_VFPU4(0x18), MA_PSP, MO_VFPU },
// 31-------------21-------16--------------------------------------0
@@ -771,10 +771,10 @@ const tMipsOpcode MipsOpcodes[] = {
{ "vsrt3.S", "vd,vs", MIPS_VFPU4_13(0x08), MA_PSP, MO_VFPU },
{ "vsrt4.S", "vd,vs", MIPS_VFPU4_13(0x09), MA_PSP, MO_VFPU },
{ "vsgn.S", "vd,vs", MIPS_VFPU4_13(0x0a), MA_PSP, MO_VFPU },
{ "vmfv.S", "vs,i7", MIPS_VFPU4_13(0x10) | 0x00, MA_PSP, MO_VFPU },
{ "vmtv.S", "vs,i7", MIPS_VFPU4_13(0x11) | 0x00, MA_PSP, MO_VFPU },
{ "vmfvc.S", "vs,i7", MIPS_VFPU4_13(0x10) | 0x80, MA_PSP, MO_VFPU },
{ "vmtvc.S", "vs,i7", MIPS_VFPU4_13(0x11) | 0x80, MA_PSP, MO_VFPU },
{ "vmfv.S", "vs,i7", MIPS_VFPU4_13(0x10)|0x00, MA_PSP, MO_VFPU },
{ "vmtv.S", "vs,i7", MIPS_VFPU4_13(0x11)|0x00, MA_PSP, MO_VFPU },
{ "vmfvc.S", "vs,i7", MIPS_VFPU4_13(0x10)|0x80, MA_PSP, MO_VFPU },
{ "vmtvc.S", "vs,i7", MIPS_VFPU4_13(0x11)|0x80, MA_PSP, MO_VFPU },
{ "vt4444.S", "vd,vs", MIPS_VFPU4_13(0x19), MA_PSP, MO_VFPU },
{ "vt5551.S", "vd,vs", MIPS_VFPU4_13(0x1a), MA_PSP, MO_VFPU },
{ "vt5650.S", "vd,vs", MIPS_VFPU4_13(0x1b), MA_PSP, MO_VFPU },
@@ -1,20 +1,20 @@
#pragma once
#include "Mips.h"
#define MA_MIPS1 0x0000001
#define MA_MIPS2 0x0000002
#define MA_MIPS3 0x0000004
#define MA_MIPS4 0x0000008
#define MA_PS2 0x0000010
#define MA_PSP 0x0000020
#define MA_RSP 0x0000040
#define MA_PSX 0x0000080
#define MA_MIPS1 0x00000001
#define MA_MIPS2 0x00000002
#define MA_MIPS3 0x00000004
#define MA_MIPS4 0x00000008
#define MA_PSX 0x00000010
#define MA_PS2 0x00000040
#define MA_PSP 0x00000080
#define MA_RSP 0x00000100
#define MA_EXPSX 0x0000100
#define MA_EXN64 0x0000200
#define MA_EXPS2 0x0000400
#define MA_EXPSP 0x0000800
#define MA_EXRSP 0x0001000
#define MA_EXPSX 0x00001000
#define MA_EXN64 0x00002000
#define MA_EXPS2 0x00004000
#define MA_EXPSP 0x00008000
#define MA_EXRSP 0x00010000
#define MO_IPCA 0x00000001 // pc >> 2
#define MO_IPCR 0x00000002 // PC, -> difference >> 2

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