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Added PSX COP2 Registers

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PeterLemon committed May 27, 2018
1 parent 4604ba2 commit 9124d4f99548a596fd37ac607dc585501d33650a
Showing with 70 additions and 8 deletions.
  1. +2 −0 Archs/MIPS/CMipsInstruction.h
  2. +8 −8 Archs/MIPS/MipsOpcodes.cpp
  3. +58 −0 Archs/MIPS/MipsParser.cpp
  4. +2 −0 Archs/MIPS/MipsParser.h
@@ -11,6 +11,8 @@ enum class MipsRegisterType
FpuControl,
Cop0,
Ps2Cop2,
PsxCop2Data,
PsxCop2Control,
VfpuVector,
VfpuMatrix,
RspCop0,
View
@@ -105,8 +105,8 @@ const tMipsOpcode MipsOpcodes[] = {
{ "lwc1", "T,(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "l.s", "T,i16(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "l.s", "T,(s)", MIPS_OP(0x31), MA_MIPS1, 0 },
{ "lwc2", "t,i16(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lwc2", "t,(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lwc2", "gt,i16(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lwc2", "gt,(s)", MIPS_OP(0x32), MA_PSX, 0 },
{ "lv.s", "vt,i16(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED },
{ "lv.s", "vt,(s)", MIPS_OP(0x32), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED },
{ "lld", "t,i16(s)", MIPS_OP(0x34), MA_MIPS3, MO_64BIT|MO_DELAYRT },
@@ -132,8 +132,8 @@ const tMipsOpcode MipsOpcodes[] = {
{ "swc1", "T,(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "s.s", "T,i16(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "s.s", "T,(s)", MIPS_OP(0x39), MA_MIPS1, 0 },
{ "swc2", "t,i16(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "swc2", "t,(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "swc2", "gt,i16(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "swc2", "gt,(s)", MIPS_OP(0x3A), MA_PSX, 0 },
{ "sv.s", "vt,i16(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED|MO_IMMALIGNED },
{ "sv.s", "vt,(s)", MIPS_OP(0x3A), MA_PSP, MO_VFPU_SINGLE|MO_VFPU_MIXED },
{ "scd", "t,i16(s)", MIPS_OP(0x3C), MA_MIPS3, MO_64BIT|MO_DELAYRT },
@@ -561,13 +561,13 @@ const tMipsOpcode MipsOpcodes[] = {
// 11 | --- | --- | --- | --- | --- | --- | --- | --- |
// hi |-------|-------|-------|-------|-------|-------|-------|-------|
{ "mfc2", "t,d", MIPS_COP2(0x00), MA_PSX, 0 },
{ "mfc2", "t,gs", MIPS_COP2(0x00), MA_PSX, 0 },
{ "mfc2", "t,RsRo", MIPS_COP2(0x00), MA_RSP, 0 },
{ "cfc2", "t,d", MIPS_COP2(0x02), MA_PSX, 0 },
{ "cfc2", "t,gc", MIPS_COP2(0x02), MA_PSX, 0 },
{ "cfc2", "t,Rc", MIPS_COP2(0x02), MA_RSP, 0 },
{ "mtc2", "t,d", MIPS_COP2(0x04), MA_PSX, 0 },
{ "mtc2", "t,gs", MIPS_COP2(0x04), MA_PSX, 0 },
{ "mtc2", "t,RsRo", MIPS_COP2(0x04), MA_RSP, 0 },
{ "ctc2", "t,d", MIPS_COP2(0x06), MA_PSX, 0 },
{ "ctc2", "t,gc", MIPS_COP2(0x06), MA_PSX, 0 },
{ "ctc2", "t,Rc", MIPS_COP2(0x06), MA_RSP, 0 },
// VVVVVV VVVVV ttttt -------- C DDDDDDD
{ "mfv", "t,vd", MIPS_COP2(0x03), MA_PSP, MO_VFPU|MO_VFPU_SINGLE },
View
@@ -76,6 +76,28 @@ const MipsRegisterDescriptor mipsPs2Cop2FpRegisters[] = {
{ L"vf30", 30 }, { L"vf31", 31 },
};
const MipsRegisterDescriptor mipsPsxCop2DataRegisters[] = {
{ L"vxy0", 0 }, { L"vz0", 1 }, { L"vxy1", 2 }, { L"vz1", 3 },
{ L"vxy2", 4 }, { L"vz2", 5 }, { L"rgbc", 6 }, { L"otz", 7 },
{ L"ir0", 8 }, { L"ir1", 9 }, { L"ir2", 10 }, { L"ir3", 11 },
{ L"sxy0", 12 }, { L"sxy1", 13 }, { L"sxy2", 14 }, { L"sxyp", 15 },
{ L"sz0", 16 }, { L"sz1", 17 }, { L"sz2", 18 }, { L"sz3", 19 },
{ L"rgb0", 20 }, { L"rgb1", 21 }, { L"rgb2", 22 }, { L"res1", 23 },
{ L"mac0", 24 }, { L"mac1", 25 }, { L"mac2", 26 }, { L"mac3", 27 },
{ L"irgb", 28 }, { L"orgb", 29 }, { L"lzcs", 30 }, { L"lzcr", 31 },
};
const MipsRegisterDescriptor mipsPsxCop2ControlRegisters[] = {
{ L"rt0", 0 }, { L"rt1", 1 }, { L"rt2", 2 }, { L"rt3", 3 },
{ L"rt4", 4 }, { L"trx", 5 }, { L"try", 6 }, { L"trz", 7 },
{ L"llm0", 8 }, { L"llm1", 9 }, { L"llm2", 10 }, { L"llm3", 11 },
{ L"llm4", 12 }, { L"rbk", 13 }, { L"gbk", 14 }, { L"bbk", 15 },
{ L"lcm0", 16 }, { L"lcm1", 17 }, { L"lcm2", 18 }, { L"lcm3", 19 },
{ L"lcm4", 20 }, { L"rfc", 21 }, { L"gfc", 22 }, { L"bfc", 23 },
{ L"ofx", 24 }, { L"ofy", 25 }, { L"h", 26 }, { L"dqa", 27 },
{ L"dqb", 28 }, { L"zsf3", 29 }, { L"zsf4", 30 }, { L"flag", 31 },
};
const MipsRegisterDescriptor mipsRspCop0Registers[] = {
{ L"sp_mem_addr", 0 }, { L"sp_dram_addr", 1 }, { L"sp_rd_len", 2 },
{ L"sp_wr_len", 3 }, { L"sp_status", 4 }, { L"sp_dma_full", 5 },
@@ -273,6 +295,26 @@ bool MipsParser::parsePs2Cop2Register(Parser& parser, MipsRegisterValue& dest)
return parseRegisterTable(parser,dest,mipsPs2Cop2FpRegisters,ARRAY_SIZE(mipsPs2Cop2FpRegisters));
}
bool MipsParser::parsePsxCop2DataRegister(Parser& parser, MipsRegisterValue& dest)
{
dest.type = MipsRegisterType::PsxCop2Data;
if (parseRegisterNumber(parser, dest, 32))
return true;
return parseRegisterTable(parser,dest,mipsPsxCop2DataRegisters,ARRAY_SIZE(mipsPsxCop2DataRegisters));
}
bool MipsParser::parsePsxCop2ControlRegister(Parser& parser, MipsRegisterValue& dest)
{
dest.type = MipsRegisterType::PsxCop2Control;
if (parseRegisterNumber(parser, dest, 32))
return true;
return parseRegisterTable(parser,dest,mipsPsxCop2ControlRegisters,ARRAY_SIZE(mipsPsxCop2ControlRegisters));
}
bool MipsParser::parseRspCop0Register(Parser& parser, MipsRegisterValue& dest)
{
dest.type = MipsRegisterType::RspCop0;
@@ -1284,6 +1326,22 @@ bool MipsParser::parseParameters(Parser& parser, const tMipsOpcode& opcode)
return false;
}
break;
case 'g': // psx cop2 reg
switch (*encoding++)
{
case 't': // gte data register
CHECK(parsePsxCop2DataRegister(parser,registers.grt));
break;
case 's': // gte data register
CHECK(parsePsxCop2DataRegister(parser,registers.grd));
break;
case 'c': // gte control register
CHECK(parsePsxCop2ControlRegister(parser,registers.grd));
break;
default:
return false;
}
break;
case 'r': // forced register
CHECK(parseRegister(parser,tempRegister));
CHECK(tempRegister.num == *encoding++);
View
@@ -24,6 +24,8 @@ class MipsParser
bool parseFpuControlRegister(Parser& parser, MipsRegisterValue& dest);
bool parseCop0Register(Parser& parser, MipsRegisterValue& dest);
bool parsePs2Cop2Register(Parser& parser, MipsRegisterValue& dest);
bool parsePsxCop2DataRegister(Parser& parser, MipsRegisterValue& dest);
bool parsePsxCop2ControlRegister(Parser& parser, MipsRegisterValue& dest);
bool parseRspCop0Register(Parser& parser, MipsRegisterValue& dest);
bool parseRspVectorControlRegister(Parser& parser, MipsRegisterValue& dest);
bool parseRspVectorRegister(Parser& parser, MipsRegisterValue& dest);

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