Runner class performs most of the generation work (up to Verilog and Vivado script). Run the following to invoke the class:
mill playground.runMain Runner
Runner will generate bash scripts for Vivado bitstream generation. Two scripts are generated:
bash out/generated-src/run_impl.sh # for running synthesis and implementation bash out/generated-src/rerun_impl_from_syn_ckpt.sh # for rerunning implementation after modifying synthesis checkpoint # e.g. after adding in ILA
History builds are stored under
out/history-builds with a minute timestamp, and
out/generated-src is a symbolic link to one of the history builds (most likely the most recent one).
This is a template repository for those who want to develop RTL based on rocket-chip and even chipyard, being able to edit all sources from chisel environments without publish them to local ivy.
You can add your own submodule in
For more information please visit mill documentation
after adding your own code, you can add your library to playground dependency, and re-index Intellij to add your own library.
For mill use
then open by your favorite IDE, which supports BSP
Philosophy of this repository is fast break and fast fix.
This repository always tracks remote developing branches, it may need some patches to work,
make patch will append below in sequence:
barstools ucb-bar/barstools#101 firrtl chipsalliance/firrtl#2276 rocket-chip chipsalliance/rocket-chip#2810 hwacha ucb-bar/hwacha#30 testchipip ucb-bar/testchipip#126 fpga-shells sifive/fpga-shells#161 fpga-shells sifive/fpga-shells#162
- Building Chisel and FIRRTL from sources, get rid of any version issue. You can view Chisel/FIRRTL source codes from IDEA.
- No more make+sbt: Scala dependencies are managed by mill -> bsp -> IDEA, minimal IDEA indexing time.
- flatten git submodule in dependency, get rid of submodule recursive update.
So generally, this repo is the fast and cleanest way to start your Chisel project codebase.
You can use this template and start your own job by appending commits on it. GitHub Action will automatically bump all dependencies, you can merge or rebase
sequencer/master to your branch.
Currently, only support Arch Linux, macOS and Debian sid, you can PR your own distributions, like Fedora. Notice Ubuntu and CentOS is unacceptable, since they have a stale package repository, not possible use official package manager to install these requirements, if you insist using them, please install requirements below by your self.
- GNU Make
- Arch Linux: make
- Debian: make
- Homebrew: make
- Arch Linux: git
- Debian: git
- Homebrew: git
- Arch Linux: mill
- Homebrew: mill
- Arch Linux: wget
- Debian: wget
- Homebrew: wget
- GNU Parallel
- Arch Linux: parallel
- Debian: parallel
- Homebrew: parallel
- Device Tree Compiler
- Arch Linux: dtc
- Debian: device-tree-compiler
- Homebrew: dtc
This package is the standalone tests to check is bumping correct or not, served as the unittest, this also can be a great example to illustrate usages.
NOTICE: SanityTests also contains additional system dependencies: **SanityTests do not support Mac, since LLVM package doesn't contain lld. **
- clang: bootrom cross compiling and veriltor C++ -> binary compiling
- Arch Linux: clang
- Debian: clang
- llvm: gnu toolchain replacement
- Arch Linux: llvm
- Debian: llvm
- lld: LLVM based linker
- Arch Linux: lld
- Debian: lld
- verilator -> Verilog -> C++ generation
- Arch Linux: verilator
- Debian: verilator
- cmake -> verilator emulator build system
- Arch Linux: cmake
- Debian: cmake
- ninja -> verilator emulator build system
- Arch Linux: ninja
- Debian: ninja-build
This package is a replacement to RocketChip Makefile based generator, it directly generate a simple RocketChip emulator with verilator and linked to spike.
This package uses rocketchip and fpga-shells to elaborate FPGA bitstream generator and debug script with board VCU118
If you wanna alter this to your own board, you can choose implmenting your own Shell to replace
VCU118Shell in this test.