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Communications between FPGAs are primarily used by the multiple FPGA compiler.
Traditionally, FPGAs have provided inter-chip communication by way of single ended or LVDS wires between chips. For example, the Nallatech ACP and HAPS boards are predicated on this style of communication. Often, this style of interconnect requires precise board engineering.
More recently, FPGAs have begun to include high-speed SERDES transceiver hardware as part of the physical FPGA silicon. Current FPGA trends toward exponential increases in both the number of SERDES available and the quality of each transceiver, in terms of throughput and latency.
SERDES hardware permits the direct linking of the commodity boards supported by LEAP by way of commodity link components, such as cross-over SATA cables. In particular, LEAP MultiFPGA support coupled with high-speed SERDES hardware permits the simple plug-n-play networking of low-cost FPGA boards to form very large systems of FPGAs with very low programmer burden.
LEAP views inter-board communications as FIFO channels with guaranteed in-order delivery. This treatment allows LEAP to capture both styles of FPGA interface (and many others, including ethernet) with a uniform interface. It is the responsibility of underlying device hardware to provide this abstraction internally.
LEAP SERDES architecture
LEAP builds several abstraction layers on top of the raw SERDES hardware, in an effort to insulate programmers from the notoriously buggy SERDES hardware provided by the FPGA vendors.
LEAP introduces an efficient credit-based flow-control layer on top of each individual SERDES transceiver. The receivers of each transcevier provide a large BRAM buffer to which incoming data is stored. As the user program drains this buffer the receiver accumulates credits to send back to the transmitter. Credit messages are sent en-block.
The current flow-control hardware also supports handshaking at channel-establishment to ensure the stability of the inter-FPGA channel before the commencement of data transmission. At this time, no error correction or recovery is applied once stable communication has been established, though this support is planned for a future release.
LEAP automatically adjusts marshaling and demarshaling between the SERDES clock domain and the user program clock domain to achieve optimal transport bandwidth.
LEAP currently supports only Xilinx parts, using modified Xilinx-provided Aurora IP as a base communications protocol. With SERDES LEAP achieves the following communications speeds and latencies (note, line rate reductions are possible, should the board require it):
|XUPV5||8b/10b,||3.125 Gbps||235 MB/s||1.2us|
|ML605||8b/10b, 5.3||5 Gbps||435 MB/s||0.4us|
|VC707||64b/66b, 7.3||10 Gbps||677 MB/s||0.8us|