{"payload":{"header_redesign_enabled":false,"results":[{"id":"730429159","archived":false,"color":"#b2b7f8","followers":4,"has_funding_file":false,"hl_name":"LSC-Unicamp/riscv-isa-ci","hl_trunc_description":"CI/CD for RISC-V Cores","language":"Verilog","mirror":false,"owned_by_organization":true,"public":true,"repo":{"repository":{"id":730429159,"name":"riscv-isa-ci","owner_id":11320249,"owner_login":"LSC-Unicamp","updated_at":"2024-06-24T18:54:55.026Z","has_issues":true}},"sponsorable":false,"topics":["hardware","eda","ci-cd","riscv","verilog","cicd","verilog-hdl","risc-v","litex"],"type":"Public","help_wanted_issues_count":0,"good_first_issue_issues_count":0,"starred_by_current_user":false}],"type":"repositories","page":1,"page_count":1,"elapsed_millis":51,"errors":[],"result_count":1,"facets":[],"protected_org_logins":[],"topics":null,"query_id":"","logged_in":false,"sign_up_path":"/signup?source=code_search_results","sign_in_path":"/login?return_to=https%3A%2F%2Fgithub.com%2Fsearch%3Fq%3Drepo%253ALSC-Unicamp%252Friscv-isa-ci%2B%2Blanguage%253AVerilog","metadata":null,"csrf_tokens":{"/LSC-Unicamp/riscv-isa-ci/star":{"post":"2lbgFfsS2yUaXBExJROC829EGPaBL9t3RimWcicOnTBCKVVQMzTIj7YfpeJ6t5mq74G4W9OlMkbGM1Oo7Q3xMA"},"/LSC-Unicamp/riscv-isa-ci/unstar":{"post":"afDxIMHYgUXG4wMQWmhMbPkVt69DOU7PDOsGZ2ctjh-XkpMQXDoXQIlqFhVsDhGjDiaLSaJgomD5VRJo3ZBJgA"},"/sponsors/batch_deferred_sponsor_buttons":{"post":"xs_vP_R3OJXwkE9TcXrwleQ6xvpoOECUsgDuuimo323YUD8-RKWIogvO2jLzg6bCLCHTaBT_ml8uFVUeF3LcMQ"}}},"title":"Repository search results"}