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Fix BOARD env variable and SDRAM part

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1 parent 9c0e34b commit 5bdcb963656c04cf5592d3b4f98f36fa85842ff7 @Lampus committed Feb 29, 2012
Showing with 3 additions and 3 deletions.
  1. +1 −1 boards/altera/de0/sw/Makefile.inc
  2. +2 −2 boards/altera/de0/sw/board/include/board.h
@@ -10,7 +10,7 @@ SW_ROOT=$(BOARD_SW_ROOT)/$(PROJ_ROOT)/sw
# Set the BOARD to be the path within the board/ path of the project that goes
# to this project.
-BOARD=actel/ordb1a3pe1500
+BOARD=altera/de0
# Set RTL_VERILOG_INCLUDE_DIR so software
RTL_VERILOG_INCLUDE_DIR=$(shell pwd)/$(BOARD_SW_ROOT)/../rtl/verilog/include
@@ -29,8 +29,8 @@
//
#define SDRAM_BASE 0x0
//#define MT48LC32M16A2 // 64MB SDRAM part
-#define MT48LC16M16A2 // 32MB SDRAM part
-//#define MT48LC4M16A2 // 8MB SDRAM part
+//#define MT48LC16M16A2 // 32MB SDRAM part
+#define MT48LC4M16A2 // 8MB SDRAM part
#define FLASHROM_BASE 0xcf000000
#define FLASHROM_SIZE 0x100

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