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amazon_s3_presentation_url amazon_s3_video_url author categories comments date image layout session_id session_track slideshare_presentation_url speakers title youtube_video_url tag
connect
yvr18
true
2018-09-16 09:00:00+00:00
featured file_name path
true
YVR18-303.png
/assets/images/featured-images/YVR18-303.png
resource-post
YVR18-303
Tools, IoT and Embedded, 96Boards
None
biography company job-title name speaker-image
""
Avnet
Senior Design Engineer
Daniel Rozwood
DanielRozwood.gif
YVR18-303:Managing customized FPGA accelerators with SDSoC!
session

Using Xilinx SDSoC and HLS as a model, this presentation, will discuss the merits and abilities of customized hardware accelerators involved with performance aspects of embedded systems. Using a designed and tested accelerator on the Avnet Ultra96, performance, power, development time metrics will be compared. Through comparing these various metrics, a new path forward for hardware accelerated software designs will be shown as a path forward for the embedded space. While this is a presentation, the author welcomes discussion!

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