{"payload":{"feedbackUrl":"https://github.com/orgs/community/discussions/53140","repo":{"id":334964073,"defaultBranch":"main","name":"vixl","ownerLogin":"Linaro","currentUserCanPush":false,"isFork":false,"isEmpty":false,"createdAt":"2021-02-01T13:47:48.000Z","ownerAvatar":"https://avatars.githubusercontent.com/u/1180626?v=4","public":true,"private":false,"isOrgOwned":true},"refInfo":{"name":"","listCacheKey":"v0:1708009287.0","currentOid":""},"activityList":{"items":[{"before":"5e267967c8e81b31b7c59b1da3c735b446ea9672","after":"662828c82625f2436153d2e4f22cbf269c5f959b","ref":"refs/heads/main","pushedAt":"2024-06-05T09:32:56.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Fix disassembly of Neon FCM, RDM and dot product instructions (#98)\n\nDisassembling some FCM, RDM and dot product instructions could report vector\r\ntypes that are undefined for the associated mnemonics. Fix this and add tests.","shortMessageHtmlLink":"Fix disassembly of Neon FCM, RDM and dot product instructions (#98)"}},{"before":"2cdba9ed4a1ee6872e513768311cc03ad68b315c","after":"5e267967c8e81b31b7c59b1da3c735b446ea9672","ref":"refs/heads/main","pushedAt":"2024-05-28T14:54:13.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Fix zeroing part of SVE register for Neon instructions (#97)\n\nFix some Neon lengthening, narrowing and insertion instructions that should\r\nzero the upper bits of SVE registers, and add regression tests.\r\n\r\nIn particular, this fixes ADDHN2, FCVTL, FCVTL2, FCVTN2, FCVTXN2,\r\nFMOV (to d[1]), LD1 (single element), RADDHN2, RSUBHN2, SQXTN2, SQXTUN2, SUBHN2,\r\nUQXTN2 and XTN2 for simulated systems with VL > 128 bits.\r\n\r\nAlso, enable FCMLA by-element instructions, for which code already exists but\r\nwasn't being called in simulation.","shortMessageHtmlLink":"Fix zeroing part of SVE register for Neon instructions (#97)"}},{"before":"3134e2560de12dfebbd72ef4868b2a5c5d7b5da9","after":"2cdba9ed4a1ee6872e513768311cc03ad68b315c","ref":"refs/heads/main","pushedAt":"2024-05-16T14:27:21.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Fix zeroing part of SVE register for Neon INS (#95)\n\nThe INS instruction inserts an element into an existing 128-bit vector, but for\r\nsystems with larger SVE registers, bits beyond the end of the vector must be\r\nzeroed. Fix this and add a regression test.","shortMessageHtmlLink":"Fix zeroing part of SVE register for Neon INS (#95)"}},{"before":"89dfbc009318786cffc22a902f2ea0930d937612","after":"3134e2560de12dfebbd72ef4868b2a5c5d7b5da9","ref":"refs/heads/main","pushedAt":"2024-04-30T09:55:11.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"jacobbramley","name":"Jacob Bramley","path":"/jacobbramley","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5206553?s=80&v=4"},"commit":{"message":"Perform implicit checks on store instructions\n\nIt is possible for runtimes to perform implicit checks on store\ninstructions as well as load instructions, therefore support\nperforming implicit checks on store instructions as well as loads. Do\nthis by returning true from memory write operations if they succeeded\nand false if they failed but were handled by a signal handler.\n\nImplicit checks on store instructions are simulated using a native\nmemory load because introducing an additional memory store could\nchange the observable behaviour of multithreaded runtimes. This means\nthat it is not currently possible to accurately simulate the\nbehaviour of implicit checks on regions with different access\npermissions for reads/writes. For example: if a page has read but not\nwrite permissions then an implicit check would not fail as the\nunderlying probing instruction will perform a memory read.","shortMessageHtmlLink":"Perform implicit checks on store instructions"}},{"before":"5a2144d133754452f7777ce71011412ad63eb6e0","after":"89dfbc009318786cffc22a902f2ea0930d937612","ref":"refs/heads/main","pushedAt":"2024-04-16T15:21:04.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Check ld* functions for failure (#92)\n\nAll memory read functions (e.g: ld1, ld2, etc...) return a value\r\n(either std::nullopt or false) to signal that the memory read failed.\r\nSome of these memory read functions were not being checked for\r\nfailure; fix this by checking these functions for failure.","shortMessageHtmlLink":"Check ld* functions for failure (#92)"}},{"before":"30e7bbdc37d8f6320056429b39e4896575e4ae64","after":"5a2144d133754452f7777ce71011412ad63eb6e0","ref":"refs/heads/main","pushedAt":"2024-02-23T17:23:23.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Support PMULL for 1Q destination vectors (#91)\n\nExtend the Neon PMULL instruction to support 1Q destination registers when the\r\nCPU feature is supported.","shortMessageHtmlLink":"Support PMULL for 1Q destination vectors (#91)"}},{"before":"accc97f1681043a9fc006a8263ebaa36ab434c53","after":"30e7bbdc37d8f6320056429b39e4896575e4ae64","ref":"refs/heads/main","pushedAt":"2024-02-15T15:05:25.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Add support for implicit checks (#86)\n\nSome runtimes make use of implicit checks, where a potentially\r\ninvalid memory access is performed. If the memory access is invalid\r\nthen a signal is raised which is then handled by a custom signal\r\nhandler which decides how to handle the signal, often returning\r\nexecution to a different function.\r\n\r\nThis patch enables this use case by performing an optional memory\r\naccess before any actual memory access. This ensures the signal is\r\nraised in a fixed location (_vixl_internal_AccessMemory) inside the\r\nsimulator which allows for signal handlers to determine:\r\n\r\n 1. That the signal came from inside the simulator (using\r\n IsSimulatedMemoryAccess) and can therefore be handled.\r\n 2. That simulation can be resumed at a determined location\r\n (using GetSignalReturnAddress) by placing that location in\r\n the signal handlers ucontext instruction pointer register, thus\r\n allowing execution to continue at the next physical instruction.\r\n\r\nIf a signal handler correctly handles a signal raised from inside the\r\nsimulator then the simulator can return to the main loop to continue\r\nsimulation at the program counter. If the signal handler needs to\r\nreturn to a different function then it can modify the PC via the\r\nexisting WritePc function.","shortMessageHtmlLink":"Add support for implicit checks (#86)"}},{"before":"ef2f4d152c6c2256101cca965295e51b78891199","after":"accc97f1681043a9fc006a8263ebaa36ab434c53","ref":"refs/heads/main","pushedAt":"2024-02-09T17:19:55.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Ensure the `threaded_tests` module can be imported safely (#90)\n\nOn MacOS, running `multiprocessing.Manager()` spawns a new process. This\r\nmeans it's not OK to run this in the global namespace, as that runs\r\nwhile modules are being resolved, before main. The multiprocessing\r\nguidelines [0], under \"Safe importing of main module\", indicate that\r\nmultiprocessing operations may have side-effects and mustn't run at that\r\npoint.\r\n\r\nThis turns the `Test.manager` global object into a local variable. The\r\nmanager's job is to handle shared state between processes and so its\r\nlifetime is tied to the shared data. That data is then tied to the\r\n`TestQueue` instance which runs tests in parallel and collects results.\r\n\r\nSo we can wrap the parallel test queue runner with a\r\n`multiprocess.Manager()` context:\r\n\r\n def Run(self, ...):\r\n with multiprocessing.Manager() as manager:\r\n # Run tests in parallel with manager\r\n\r\n[0]: https://docs.python.org/3/library/multiprocessing.html#multiprocessing-programming","shortMessageHtmlLink":"Ensure the threaded_tests module can be imported safely (#90)"}},{"before":"1a2c1d379f723416c157711eea948495dd475e57","after":"ef2f4d152c6c2256101cca965295e51b78891199","ref":"refs/heads/main","pushedAt":"2024-02-09T11:34:04.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Fix some portability and build problems (#89)\n\nRemove use of deprecated std::iterator.\r\nFix colordiff use in clang_format script (from jacob.bramley@arm.com).\r\nRemove debugger tests from non-simulator builds.\r\nUpdate code coverage record.","shortMessageHtmlLink":"Fix some portability and build problems (#89)"}},{"before":"2decd2cf315ba71ed6edc983b520760eef09aad5","after":"1a2c1d379f723416c157711eea948495dd475e57","ref":"refs/heads/main","pushedAt":"2024-02-01T16:43:49.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update clang tools to version 11+ (#87)\n\nCo-authored-by: Sebastian Nickolls ","shortMessageHtmlLink":"Update clang tools to version 11+ (#87)"}},{"before":"08574f1bae4295aec02776cc8fa74e0d448e8d20","after":"2decd2cf315ba71ed6edc983b520760eef09aad5","ref":"refs/heads/main","pushedAt":"2024-01-17T11:24:49.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update tools to python3 (#85)\n\nThis updates the scripts in the tools directory to work with python3, python2\r\nsupport is now deprecated.\r\n\r\nThe only significant API change is that the subprocess module works in bytes\r\ninstead of str, the rest are mainly style changes.","shortMessageHtmlLink":"Update tools to python3 (#85)"}},{"before":"7a2a47281bdc81320b3404d8cdc6c6a5e0a5dc9a","after":"08574f1bae4295aec02776cc8fa74e0d448e8d20","ref":"refs/heads/main","pushedAt":"2023-12-08T17:56:33.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update code coverage (#83)\n\nUpdates the code coverage log to the latest version.","shortMessageHtmlLink":"Update code coverage (#83)"}},{"before":"a0a143959b0b5b076eda5fd7e48da8263e6390be","after":"7a2a47281bdc81320b3404d8cdc6c6a5e0a5dc9a","ref":"refs/heads/main","pushedAt":"2023-12-08T17:18:49.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update to C++17 (#82)\n\nUpdate the default build to use C++17 instead of C++14. This enables\r\nusage of C++17 features in VIXL.\r\n\r\nNote: this removes C++14 as a testing target as use of C++17 features\r\nwill break building with C++14.","shortMessageHtmlLink":"Update to C++17 (#82)"}},{"before":"8eca2b7b2f7e51197198a7a3126887eaf73b226c","after":"a0a143959b0b5b076eda5fd7e48da8263e6390be","ref":"refs/heads/main","pushedAt":"2023-12-08T13:59:42.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Add a debugger to VIXL simulator (#81)\n\nAdd a basic debugger to the VIXL simulator. Once enabled (by default\r\nthe debugger is disabled) any brk instruction encountered while\r\nsimulating will cause the interactive debugger to be launched.\r\n\r\nThe debugger supports the following features:\r\n- Break\r\n- Step\r\n- Continue\r\n- Printing registers\r\n- Toggling tracing\r\n- Switching to GDB","shortMessageHtmlLink":"Add a debugger to VIXL simulator (#81)"}},{"before":"4676e74819891787a98f502b76215b4023fbfb91","after":"0e629a4b2d61062faf87c27342587cec3e624f82","ref":"refs/heads/morello","pushedAt":"2023-10-27T13:55:36.000Z","pushType":"push","commitsCount":1,"pusher":{"login":"jacobbramley","name":"Jacob Bramley","path":"/jacobbramley","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5206553?s=80&v=4"},"commit":{"message":"Morello: Adapt existing tests to run under purecap.\n\nInsert some translation code into the standard test prologue and\nepilogue, so that existing A64 tests can be called from a purecap\nenvironment.\n\nAll of the simulator tests are skipped for purecap hosts, as are a few\nassembler tests. These need manual porting to work with host\ncapabilities, or rely on unimplemented features (such as runtime calls).","shortMessageHtmlLink":"Morello: Adapt existing tests to run under purecap."}},{"before":"36500dff0fe6afd18fa9edd25e0a59f9ca1b3ae8","after":"4676e74819891787a98f502b76215b4023fbfb91","ref":"refs/heads/morello","pushedAt":"2023-10-27T08:39:44.000Z","pushType":"push","commitsCount":5,"pusher":{"login":"jacobbramley","name":"Jacob Bramley","path":"/jacobbramley","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/5206553?s=80&v=4"},"commit":{"message":"Morello: Fix a test for purecap (C64).\n\nThis is the first test that fails on purecap, using `--run-all`. It's a\nminimal `MacroAssembler` use-case, and failed because we assemble A64\ncode by default, assuming AAPCS64. This patch includes some basic\ninfrastructure that we'll use to fix other test cases.","shortMessageHtmlLink":"Morello: Fix a test for purecap (C64)."}},{"before":"b13d3bf3b1c51ccd2653eeace22cb30e9407d978","after":"8eca2b7b2f7e51197198a7a3126887eaf73b226c","ref":"refs/heads/main","pushedAt":"2023-09-13T09:09:12.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Add branch interception to VIXL simulator (#77)\n\n* Add maybe_unused to runtime call arguments\r\n\r\nCurrently runtime calls cannot be done if the function to be called\r\nhas no parameters because the compiler will give a\r\n\"unused-but-set-parameter\" warning which is treated as an error. Fix\r\nthis by always using the 'arguments' parameter.\r\n\r\nChange-Id: I9f4b75ea8b6ae6fe03be33cefa45fa99f5485b7a\r\n\r\n* Add branch interception to VIXL simulator\r\n\r\nSimulated AARCH64 code, that is not written in using the\r\nmacroassembler, can branch (change the simulated PC) to arbitrary\r\nfunction addresses. This works fine if that function is AARCH64\r\nhowever if that function is a native (x86_64) C++ function then an\r\nerror (likely SIGILL) will be thrown. To handle this case we need to\r\n\"intercept\" branches to these native (x86_64) C++ functions and\r\ninstead either perform a runtime call to the function or provide a\r\ncallback to manually handle the particular case.\r\n\r\nAdd a mechanism to intercept functions as they are branched to\r\nwithin the VIXL simulator. This means that whenever a function X is\r\nbranched to (e.g: bl X) instead, if provided, a callback function Y\r\nis called. If no callback is provided for the interception to\r\nfunction X then a runtime call will be done on function X.\r\n\r\nBranch interception objects consisting of the function to intercept:\r\nX, and an optional callback function Y are stored within the\r\nsimulator and checked every unconditional branch to register.\r\n\r\nChange-Id: I874a6fa5b8f0581fe930a7a98f762031bdb2f591","shortMessageHtmlLink":"Add branch interception to VIXL simulator (#77)"}},{"before":"279f08b57b2e7ebb38f60486e65319e82d12197a","after":"b13d3bf3b1c51ccd2653eeace22cb30e9407d978","ref":"refs/heads/main","pushedAt":"2023-08-15T16:59:08.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Fixes post-index vector loadstore writeback (#76)","shortMessageHtmlLink":"Fixes post-index vector loadstore writeback (#76)"}},{"before":"abca95f09c11d2631f8cf9e677dda1e2a410a29c","after":"3fae28899b8fd20afc3b12aa0cdc80519433f85e","ref":"refs/heads/dev/vixl-interception","pushedAt":"2023-07-28T11:25:32.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Simulator branch interception (#75)\n\n* Add maybe_unused to runtime call arguments\r\n\r\nCurrently runtime calls cannot be done if the function to be called\r\nhas no parameters because the compiler will give a\r\n\"unused-but-set-parameter\" warning which is treated as an error. Fix\r\nthis by always using the 'arguments' parameter.\r\n\r\nChange-Id: I9f4b75ea8b6ae6fe03be33cefa45fa99f5485b7a\r\n\r\n* Add branch interception to VIXL simulator\r\n\r\nSimulated AARCH64 code, that is not written in using the\r\nmacroassembler, can branch (change the simulated PC) to arbitrary\r\nfunction addresses. This works fine if that function is AARCH64\r\nhowever if that function is a native (x86_64) C++ function then an\r\nerror (likely SIGILL) will be thrown. To handle this case we need to\r\n\"intercept\" branches to these native (x86_64) C++ functions and\r\ninstead either perform a runtime call to the function or provide a\r\ncallback to manually handle the particular case.\r\n\r\nAdd a mechanism to intercept functions as they are branched to\r\nwithin the VIXL simulator. This means that whenever a function X is\r\nbranched to (e.g: bl X) instead, if provided, a callback function Y\r\nis called. If no callback is provided for the interception to\r\nfunction X then a runtime call will be done on function X.\r\n\r\nBranch interception objects consisting of the function to intercept:\r\nX, and an optional callback function Y are stored within the\r\nsimulator and checked every unconditional branch to register.\r\n\r\nChange-Id: I874a6fa5b8f0581fe930a7a98f762031bdb2f591","shortMessageHtmlLink":"Simulator branch interception (#75)"}},{"before":null,"after":"abca95f09c11d2631f8cf9e677dda1e2a410a29c","ref":"refs/heads/dev/vixl-interception","pushedAt":"2023-07-26T14:47:05.000Z","pushType":"branch_creation","commitsCount":0,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update version to 6.3.0","shortMessageHtmlLink":"Update version to 6.3.0"}},{"before":"02c670693338bfe55992bdc857808f5122bd45f3","after":"279f08b57b2e7ebb38f60486e65319e82d12197a","ref":"refs/heads/main","pushedAt":"2023-06-20T09:55:10.763Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Improve SIMD & FP constant materialization (#74)\n\n* Fix a code generation issue inside the MacroAssembler::Movi64bitHelper()\r\nmethod that could set the upper 64 bits of a vector register to an\r\nincorrect value instead of 0\r\n* Reduce the instructions necessary to materialize a vector constant\r\nby 2 when the upper 64 bits are 0, while the lower ones aren't\r\n* Restructure the code paths for the immediate forms of FMOV, so\r\nthat the common case, 0, is handled first","shortMessageHtmlLink":"Improve SIMD & FP constant materialization (#74)"}},{"before":"a20c62b4b12f567f71725a2dbc3cbabf9f40e963","after":"02c670693338bfe55992bdc857808f5122bd45f3","ref":"refs/heads/main","pushedAt":"2023-06-14T13:06:07.225Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update code coverage record (#73)","shortMessageHtmlLink":"Update code coverage record (#73)"}},{"before":"c5b3101ece6c9b6dab69fdc5b0efc1ea894e4541","after":"a20c62b4b12f567f71725a2dbc3cbabf9f40e963","ref":"refs/heads/main","pushedAt":"2023-05-30T13:06:36.746Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update comment to match the macro name (#72)","shortMessageHtmlLink":"Update comment to match the macro name (#72)"}},{"before":"64c25fed56cd9cb3f7b636a0d31336591fbb78e5","after":"c5b3101ece6c9b6dab69fdc5b0efc1ea894e4541","ref":"refs/heads/main","pushedAt":"2023-05-16T10:18:08.136Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Define PrintVector function only when necessary (#70)","shortMessageHtmlLink":"Define PrintVector function only when necessary (#70)"}},{"before":"b5c57c94bc1dec9c79a49c054a341c9d9b12313a","after":"64c25fed56cd9cb3f7b636a0d31336591fbb78e5","ref":"refs/heads/main","pushedAt":"2023-05-09T13:32:48.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Small optimisation for Assembler::Emit (#71)\n\nInside Emit(), the compiler can't be sure that the pc_ field of the Assembler\r\nobject doesn't point to itself, so it must be reloaded from the object after the\r\ncall to memcpy, in order to advance pc_.\r\n\r\nEmit() is used by all Assembler methods, so optimise it a little by making a\r\nlocal copy of the field.","shortMessageHtmlLink":"Small optimisation for Assembler::Emit (#71)"}},{"before":"94b311af82ccf578643f8f2878a4f1ec0468b134","after":"b5c57c94bc1dec9c79a49c054a341c9d9b12313a","ref":"refs/heads/main","pushedAt":"2023-03-16T16:26:32.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Add support for CSSC instructions (#69)\n\nAdd support for CSSC instructions (abs, cnt, ctz, smax, smin, umax, umin) to all\r\ncomponents, and refactor some of the code nearby.","shortMessageHtmlLink":"Add support for CSSC instructions (#69)"}},{"before":"b6725cfeb835ad46b8069f6e7e3da67153c64acc","after":"94b311af82ccf578643f8f2878a4f1ec0468b134","ref":"refs/heads/main","pushedAt":"2023-03-16T15:27:29.000Z","pushType":"pr_merge","commitsCount":1,"pusher":{"login":"mmc28a","name":null,"path":"/mmc28a","primaryAvatarUrl":"https://avatars.githubusercontent.com/u/78873583?s=80&v=4"},"commit":{"message":"Update instruction decoder (#68)\n\nUpdate the decoder to support the latest instructions defined by the\r\narchitecture and fix tests.","shortMessageHtmlLink":"Update instruction decoder (#68)"}}],"hasNextPage":false,"hasPreviousPage":false,"activityType":"all","actor":null,"timePeriod":"all","sort":"DESC","perPage":30,"cursor":"djE6ks8AAAAEXOyUGwA","startCursor":null,"endCursor":null}},"title":"Activity ยท Linaro/vixl"}