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2017-12-06 04:00:00 -0800
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Arm HPC Workshop Sessions and Speakers
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Arm HPC Workshop Sessions and Speakers

We are pleased to announce the sessions and speakers for the first ever Arm HPC workshop taking place in Tokyo 12-13th Dec 2017. The sold-out event has attracted over 100 attendees from Japan, UK, USA, China and other parts of the world. Joining us are speakers from RIKEN AICS, Fujitsu, Arm and some Research institutions. Please find the detailed schedule below. For more information on Linaro High Performance Computing (HPC) work click here.

Sessions


<div class="col-md-6">

    <div class="list-group">
      <a href="#dr" class="list-group-item">
        <h4 class="list-group-item-heading">Welcome Note</h4>
        <p class="list-group-item-text">David Rusling CTO, Linaro</p>
      </a>
      <a href="#1" class="list-group-item">
        <h4 class="list-group-item-heading">Introduction of Post-K development</h4>
        <p class="list-group-item-text">Yutaka Ishikawa, RIKEN AICS</p>
      </a>
      <a href="#2" class="list-group-item">
        <h4 class="list-group-item-heading">Post-K: Building the Arm HPC Ecosystem</h4>
        <p class="list-group-item-text">Koichi Hirai, Fujitsu</p>
      </a>
      <a href="#3" class="list-group-item">
        <h4 class="list-group-item-heading">Arm tools and roadmap for SVE compiler support</h4>
        <p class="list-group-item-text">Richard Sandiford, Florian Hahn (Arm), Arm</p>
      </a>
      <a href="#4" class="list-group-item">
        <h4 class="list-group-item-heading">HCQC : HPC Compiler Quality Checker</h4>
        <p class="list-group-item-text">Masaki Arai, Fujitsu Laboratories Ltd.</p>
      </a>
      <a href="#5" class="list-group-item">
        <h4 class="list-group-item-heading">State of the Scalasca Toolset</h4>
        <p class="list-group-item-text">Itaru Kitayama, RIKEN AICS</p>
      </a>
      <a href="#6" class="list-group-item">
        <h4 class="list-group-item-heading">Porting and Optimization of Numerical Libraries for Arm SVE	</h4>
        <p class="list-group-item-text">Toshiyuki Imamura, RIKEN AICS</p>
      </a>
      <a href="#7" class="list-group-item">
        <h4 class="list-group-item-heading">An Evaluation of EasyBuild for Open Source Software Deployment</h4>
        <p class="list-group-item-text">Takahiro Ogura, RIKEN</p>
      </a>
      <a href="#8" class="list-group-item">
        <h4 class="list-group-item-heading">An Overview of the IHK/McKernel Multi-kernel Operating System</h4>
        <p class="list-group-item-text">Balazs Gerofi,	RIKEN Advanced Institute For Computational Science</p>
      </a>
      <a href="#9" class="list-group-item">
        <h4 class="list-group-item-heading">Compilation of COSMO for GPU using LLVM</h4>
        <p class="list-group-item-text">Tobias Grosser, Scalable Parallel Computing Laboratory (SPCL)</p>
      </a>
      <a href="#10" class="list-group-item">
        <h4 class="list-group-item-heading">Involvement in OpenHPC</h4>
        <p class="list-group-item-text">Takeharu Kato, Fujitsu</p>
      </a>
    </div>

</div>

<div class="col-md-6">

     <div class="list-group">
      <a href="#11" class="list-group-item">
        <h4 class="list-group-item-heading">Cyber-physical System and Industrial Applications of Large-Scale Graph Analysis and Optimization Problem</h4>
        <p class="list-group-item-text">Katsuki Fujisawa: The Institute of Mathematics for Industry, Kyushu University & The Artificial Intelligence Research Center, Advanced Industrial Science and Technology)</p>
      </a>
      <a href="#12" class="list-group-item">
        <h4 class="list-group-item-heading">New Process/Thread Runtime</h4>
        <p class="list-group-item-text">Atsushi Hori, RIKEN</p>
      </a>
      <a href="#13" class="list-group-item">
        <h4 class="list-group-item-heading">An evaluation of LLVM compiler for SVE with fairly complicated loops</h4>
        <p class="list-group-item-text">Hiroshi Nakashima, Kyoto University / RIKEN AICS</p>
      </a>
      <a href="#14" class="list-group-item">
        <h4 class="list-group-item-heading">Oopstreaming</h4>
        <p class="list-group-item-text">Renato Golin, Linaro</p>
      </a>
      <a href="#15" class="list-group-item">
        <h4 class="list-group-item-heading">Programming Languages & Tools for Higher Performance & Productivity</h4>
        <p class="list-group-item-text">Hitoshi Murai, RIKEN AICS</p>
      </a>
      <a href="#16" class="list-group-item">
        <h4 class="list-group-item-heading">Advantages of the Compiler for Post-K computer</h4>
        <p class="list-group-item-text">Shun Kamatsuka, Fujitsu</p>
      </a>
      <a href="#17" class="list-group-item">
        <h4 class="list-group-item-heading">Application Development Tools for Post-K Supercomputer</h4>
        <p class="list-group-item-text">Tomotake Nakamura, Fujitsu</p>
      </a>
      <a href="#18" class="list-group-item">
        <h4 class="list-group-item-heading">The perfect mix: SUSE's HPC, Arm and Containers</h4>
        <p class="list-group-item-text">Vojtech Pavlik, SUSE</p>
      </a>
      <a href="#19" class="list-group-item">
        <h4 class="list-group-item-heading">OpenMP Extension for Explicit SIMD Programming using Arm SVE</h4>
        <p class="list-group-item-text">Jinpil Lee, RIKEN AICS</p>
      </a>
      <a href="#20" class="list-group-item">
        <h4 class="list-group-item-heading">Performance evaluation with Arm HPC tools for SVE</h4>
        <p class="list-group-item-text">Miwako Tsuji, RIKEN AICS</p>
      </a>

    </div>

</div>

Session Details

<div class="col-sm-9 session-info">
    <a name="dr"></a>
    <h4 class="talk-title">
        Welcome Note
    </h4>

    <em>By</em> David Rusling CTO, Linaro
    
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/3B60l14pgrhlGQ" %}

</div>

<div class="col-sm-3 speaker-info">

</div>
<div class="col-sm-9 session-info">
    <a name="1"></a>
    <h4 class="talk-title">
        Introduction of Post-K development
    </h4>

    <em>By</em> Yutaka Ishikawa, RIKEN AICS

    <p class="talk-abstract">
        Post-K is the next flagship supercomputer in Japan, replacement of the K supercomputer. Its node architecture and interconnect are based on Armv8 SVE and a 6-D mesh/torus network, respectively. A three level hierarchical storage system will be installed with compute nodes. The system software developed in the post K supercomputer includes a novel operating system for general-purpose manycore architectures, low-level communication and MPI libraries, and file I/O middleware.
    </p>

</div>

<div class="col-sm-3 speaker-info">
    <strong>Yutaka Ishikawa Bio</strong>
    <p>
    The project leader of flagship2020 project
    </p>
    <strong>Contact Email</strong>
    <p>
    yutaka.ishikawa@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="2"></a>
    <h4 class="talk-title">
        Post-K: Building the Arm HPC Ecosystem
    </h4>

    <em>By</em> Koichi Hirai, Fujitsu

    <p class="talk-abstract">
        Post-K use Arm based super computer. But there are not too many Arm based servers for HPC.
        Therefore we think to need to build Arm HPC Ecosystem until Post-K release.
        In this presentation, we describe our collaboration efforts to build the Arm HPC Ecosystem.
    </p>
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/GhuGCRY2cocWeH" %}
</div>

<div class="col-sm-3 speaker-info">

</div>
<div class="col-sm-9 session-info">
    <a name="3"></a>
    <h4 class="talk-title">
        Arm tools and roadmap for SVE compiler support
    </h4>

    <em>By</em> Richard Sandiford, Florian Hahn (Arm), Arm

    <p class="talk-abstract">
        This presentation will give an overview of what Arm is doing to develop the HPC ecosystem, with a particular focus on SVE.  It will include a brief synopsis of both the commercial and open-source tools and libraries that Arm is developing and a description of the various community initiatives that Arm is involved in.  The bulk of the talk will describe the roadmap for SVE compiler support in both GCC and LLVM.  It will cover the work that has already been done to support both hand-optimised and automatically-vectorised code, and the plans for future improvements.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/zM0BvjLMPq9woZ" %}

</div>

<div class="col-sm-3 speaker-info">

</div>
<div class="col-sm-9 session-info">
    <a name="4"></a>
    <h4 class="talk-title">
        HCQC : HPC Compiler Quality Checker
    </h4>

    <em>By</em> Masaki Arai, Fujitsu Laboratories Ltd.

    <p class="talk-abstract">
        For numerical calculation programs on supercomputers, the kernel part occupies 80% or more of the execution time in many cases.
        Therefore, the quality of the code generated by the compiler for these kernel parts is significant.
        We created a tool, which is called HCQC, to aid in the investigation of the quality of the code generated by the compiler for the kernel part.
        In this presentation, we report the details of HCQC and the results of evaluating the quality of GCC and LLVM when compiling the kernel part of benchmark programs using HCQC.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/DvyANaX3PEWHAV" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Masaki Arai Bio</strong>
    <p>
        In 1992, He joined Fujitsu Laboratories Ltd. His research interests
        are in the area of compiler optimizations and computer architectures.
        He joined Linaro as member engineer in 2017.
    </p>
    <strong>Email</strong>
    <p>
        arai.masaki@jp.fujitsu.com
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="5"></a>
    <h4 class="talk-title">
        State of the Scalasca Toolset
    </h4>

        <em>By</em> Itaru Kitayama, RIKEN AICS

    <p class="talk-abstract">
        Scalasca is a standardized toolset for parallel applications to evaluate their performance on HPC systems. In this talk, starting from the general introduction to the toolset, we’ll review the current state of Scalasca, focusing on the arm64 support. As of today Scalasca just works out of the box on arm64, except sampling mode support which is only available on x86 systems.  The on-going porting work to address this missing feature is presented in detail and also a major upgrade to their trace format called Online Trace Format (OTF) is summarized. As time permits, project outlook and demo slides actually carried on a Cavium ThunderX system will be given in the talk.
    </p>

</div>

<div class="col-sm-3 speaker-info">
    <strong>Itaru Kitayama Bio</strong>
    <p>
        Itaru Kitayama has been working on HPC tools for supercomputers at AICS since 2013.
    </p>
    <strong>Email</strong>
    <p>
        itaru.kitayama@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="6"></a>
    <h4 class="talk-title">
        Porting and Optimization of Numerical Libraries for Arm SVE
    </h4>

        <em>By</em> Toshiyuki Imamura, RIKEN AICS

    <p class="talk-abstract">
        RIKEN and Fujitsu are developing Arm-based numerical libraries optimized with the new feature of Arm-SVE. We present porting status of netlib+SSL-II for Arm-SVE and other OSS. Also, we demonstrate some optimization policies and techniques, especially for the basic numerical linear algebra kernels.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/AP6tYcCEtN4WTa" %}
</div>

<div class="col-sm-3 speaker-info">
    <strong>Toshiyuki Imamura Bio</strong>
    <p>
        Toshiyuki Imamura is currently a team leader of Large-scale Parallel Numerical Computing Technology at Advanced Institute for Computational Science (AICS), RIKEN. He is in charge of the development of numerical libraries for the post-K project. His research interests include high-performance computing, automatic-tuning technology, eigenvalue computation (algorithm/software/applications), etc. He and his colleagues (Japan Atomic Energy Agency (JAEA) team) were nominated as one of the finalists of Gordon Bell Prize in SC05 and SC06. He is a member of IPSJ, JSIAM, and SIAM.
    </p>
    <strong>Email</strong>
    <p>
        imamura.toshiyuki@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="7"></a>
    <h4 class="talk-title">
        An Evaluation of EasyBuild for Open Source Software Deployment
    </h4>

    <em>By</em> Takahiro Ogura, RIKEN

    <p class="talk-abstract">
        Sharing build procedures of Open Source Software (OSS) is critical to quick OSS deployment. It is difficult for us because our target architecture is Arm and the public know-hows are not abundant since Arm based HPC machines are not prevalent. We will share the lessons learned from our evaluation of EasyBuild, which facilitates formulation and sharing of build recipes.
    </p>

</div>

<div class="col-sm-3 speaker-info">
    <strong>Takahiro Ogura Bio</strong>
    <p>
        Advanced Institute for Computational Science
        Research & Development Scientist
    </p>
    <strong>Email</strong>
    <p>
        t-ogura@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="8"></a>
    <h4 class="talk-title">
        An Overview of the IHK/McKernel Multi-kernel Operating System
    </h4>

    <em>By</em> Balazs Gerofi, RIKEN Advanced Institute For Computational Science

    <p class="talk-abstract">
        RIKEN Advanced Institute for Computation Science is in charge of leading the development of Japan's next generation flagship supercomputer, the successor of the K. Part of this effort is to design and develop a system software stack that suits the needs of future extreme scale computing. In this talk, we focus on operating system (OS) requirements for HPC and discuss IHK/McKernel, a multi-kernel based operating system framework. IHK/McKernel runs Linux with a light-weight kernel (LWK) side-by-side on compute nodes with the primary motivation of providing scalable, consistent performance for large scale HPC simulations, but at the same time to retain a fully Linux compatible execution environment. We provide an overview of the project and discuss the status of its support for Arm architecture.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/NNdQnsWIgoCwHB" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Balazs Gerofi Bio</strong>
    <p>
        Research Scientist at RIKEN Advanced Institute For Computational Science.
    </p>
    <strong>Email</strong>
    <p>
        bgerofi@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="9"></a>
    <h4 class="talk-title">
        Compilation of COSMO for GPU using LLVM
    </h4>

    <em>By</em> Tobias Grosser, Scalable Parallel Computing Laboratory (SPCL)

    <p class="talk-abstract">
        The COSMO climate and weather model delivers daily forecasts for
        Switzerland and many other nations. As a traditional HPC application it
        was developed with SIMD-CPUs in mind and large manual efforts were
        required to enable the 2016 move to GPU acceleration. As today's high-performance computer systems increasingly rely on accelerators to
        reach peak performance and manual translation to accelerators is both
        costly and difficult to maintain, we propose a fully automatic
        accelerator compiler for the automatic translation of scientific Fortran
        codes to CUDA GPU accelerated systems. Several challenges had to be
        overcome to make this reality: 1) improved scalability, 2) automatic
        data placement using unified memory, 3) loop rescheduling to expose
        coarse-grained parallelism, 4) inter-procedural loop optimization, and
        5) plenty of performance tuning. Our evaluation shows that end-to-end
        automatic accelerator compilation is possible for non-trivial portions
        of the COSMO climate model, despite the lack of complete static
        information. Non-trivial loop optimizations previously implemented
        manually are performed fully automatically and memory management happens
        fully transparently using unified memory. Our preliminary results show
        notable performance improvements over sequential CPU code  (40s to 8s
        reduction in execution time) and we are currently working on closing the
        remaining gap to hand-tuned GPU code. This talk is a status update on
        our most recent efforts and also intended to gather feedback on future
        research plans towards automatically mapping COSMO to FPGAs.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/ye93RqO7aue73Y" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Tobias Grosser Bio</strong>
    <p>
        Tobias Grosser is a senior researcher in the Scalable Parallel Computing
        Laboratory (SPCL)  of Torsten Hoefler at the Computer Science Department
        of ETH Zürich. Supported by a Google PhD Fellowship he received his
        doctoral degree from Universite Pierre et Marie Curie under the
        supervision of Albert Cohen. Tobias' research is taking place at the
        border of low-level compilers and high-level program transformations
        with the goal of enabling complex - but highly-beneficial - program
        transformations in a production compiler environment. He develops with
        the Polly loop optimizer a loop transformation framework which today is
        a community project supported throught the Polly Labs research
        laboratory. Tobias also developed advanced tiling schemes for the
        efficient execution of iterated stencils. Today Tobias leads the
        heterogeneous compute efforts in the Swiss University funded ComPASC
        project and is about to start a three year NSF Ambizione project on
        advancing automatic compilation and heterogenization techniques at ETH
        Zurich.
    </p>
    <strong>Email</strong>
    <p>
        bgerofi@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="10"></a>
    <h4 class="talk-title">
        Involvement in OpenHPC
    </h4>

    <em>By</em> Takeharu Kato, Fujitsu

    <p class="talk-abstract">
        Nowadays, OpenHPC is gradually spreading as a software stack standard for HPC.
        OpenHPC is one of the most promising software stack to achieve interoperability among HPC systems.
        It is designed and developed to makes building HPC systems easier.
        In this presentation, we explain the current status of OpenHPC and our involvement in OpenHPC to establish Arm HPC eco-system.
    </p>
    
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/rQaMRYS38ty2qK" %}
</div>

<div class="col-sm-3 speaker-info">
</div>
<div class="col-sm-9 session-info">
    <a name="11"></a>
    <h4 class="talk-title">
        Cyber-physical System and Industrial Applications of Large-Scale Graph Analysis and Optimization Problem
    </h4>

    <em>By</em> Katsuki Fujisawa, The Institute of Mathematics for Industry, Kyushu University & The Artificial Intelligence Research Center, Advanced Industrial Science and Technology)

    <p class="talk-abstract">
        In this talk, we present our ongoing research project. The objective of many ongoing research projects in high performance computing (HPC) areas is to develop an advanced computing and optimization infrastructure for extremely large-scale graphs on the peta-scale supercomputers. The extremely large-scale graphs that have recently emerged in various application fields, such as transportation, social networks, cyber-security, and bioinformatics, require fast and scalable analysis. The number of vertices in the graph networks has grown from billions to trillions and that of the edges from hundreds of billions to tens of trillions. The Graph500 (http://graph500.org) and Green Graph 500 (http://green.graph500.org) benchmarks are designed to measure the performance of a computer system for applications that require irregular memory and network access patterns. Following its announcement in June 2010, the Graph500 list was released in November 2010, since when it has been updated semiannually. The Graph500 benchmark measures the performance of any supercomputer performing a breadth-first search (BFS) in terms of traversed edges per second (TEPS). In 2014 to 2017, our project team has been a winner at the eighth, and 10th to 15th Graph500 benchmark. We commenced our research project for developing the Urban OS (Operating System) for a large-scale city in 2013. The Urban OS, which is regarded as one of the emerging applications of the cyber-physical system (CPS), gathers big data sets of the distribution of people and transportation movements by utilizing sensor technologies and storing them in the cloud storage system. In the next step, we apply optimization and simulation techniques to solve them and check the validity of solutions obtained on the cyber space. The Urban OS employs the graph analysis system developed by this research project and provides a feedback to a predicting and controlling center to optimize many social systems and services. We briefly explain our ongoing research project for realizing the Urban OS.

    </p>

</div>

<div class="col-sm-3 speaker-info">
    <strong>Katsuki Fujisawa Bio</strong>
    <p>
        Fujisawa has been a Full Professor at the Institute of Mathematics for Industry (IMI) of Kyushu University, Japan. He had also been a research director of the JST (Japan Science and Technology Agency) CREST (Core Research for Evolutional Science and Technology) post-Peta High Performance Computing from 2011 to 2017. He received his Ph. D. from the Tokyo Institute of Technology in 1998. The objective of the JST CREST project is to develop an advanced computing and optimization infrastructure for extremely large-scale graphs on post peta-scale supercomputers. His project team has challenged the Graph500 benchmark, which is designed to measure the performance of a computer system for applications that require irregular memory and network access patterns. In 2014 to 2017, his project team was a winner at the eighth, and 10th to 14th Graph500 benchmark. In 2017, He received the Prize for Science and Technology (Research Category),  Commendation for Science and Technology by the Minister of Education, Culture, Sports, Science and Technology, Japan.

    </p>
    <strong>Email</strong>
    <p>
        fujisawa@imi.kyushu-u.ac.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="12"></a>
    <h4 class="talk-title">
        New Process/Thread Runtime
    </h4>

    <em>By</em> Atsushi Hori, RIKEN

    <p class="talk-abstract">
        New portable and practical parallel execution model, Process in Process (PiP in short) will be presented. PiP tasks share the same virtual address space like the multi-thread model and privatized variables like the multi-process model. Because of this, PiP provides the best of two worlds, multi-process (MPI) and multi-thread (OpenMP).
    </p>
    
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/hzv5CPRfIBIMwo" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Atsushi Hori Bio</strong>
    <p>
        Researcher, System Software Development Team, RIKEN
    </p>
    <strong>Email</strong>
    <p>
        ahori@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="13"></a>
    <h4 class="talk-title">
        An evaluation of LLVM compiler for SVE with fairly complicated loops
    </h4>

    <em>By</em> Hiroshi Nakashima, Kyoto University / RIKEN AICS

    <p class="talk-abstract">
        As a part of the evaluation of Post-K’s compilers, we have been investigating compiled codes of vectorizable kernel loops in a particle-in-cell simulation program. This talk will reveal how the latest version of LLVM compiler (v1.4) works on the loops together with the qualitative and quantitative comparison with the code generated by Intel’s compiler for KNL.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/MMw1lY5Crzp8cN" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Hiroshi Nakashima Bio</strong>
    <p>
        Currently working as a professor of Kyoto University’s supercomputer center (ACCMS) for R&D on HPC programming and supercomputer system architecture, as well as a visiting senior researcher of RIKEN AICS for the evaluation of Post-K computer and its compilers.
    </p>
    <strong>Email</strong>
    <p>
        h.nakashima@media.kyoto-u.ac.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="14"></a>
    <h4 class="talk-title">
        Oopstreaming
    </h4>

    <em>By</em> Renato Golin, Linaro
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/eNDtLYV2HhEP03" %}

    <p class="talk-abstract">

    </p>

</div>

<div class="col-sm-3 speaker-info">

</div>
<div class="col-sm-9 session-info">
    <a name="15"></a>
    <h4 class="talk-title">
        Programming Languages & Tools for Higher Performance & Productivity
    </h4>

    <em>By</em> Hitoshi Murai, RIKEN AICS

    <p class="talk-abstract">
        For higher performance and productivity of HPC systems, it is important to provide users with good programming environment including languages, compilers, and tools. In this talk, the programming model of the post-K supercomputer will be shown.
    </p>

    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/kjobNzT53Nnc8R" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Hitoshi Murai Bio</strong>
    <p>
        Hitoshi Murai received a master's degree in information science from Kyoto University in 1996. He worked as a software developer in NEC from 1996 to 2010. He received a Ph.D degree in computer science from University of Tsukuba in 2010. He is currently a research scientist of the programming environment research team and the Flagship 2020 project in Advanced Institute for Computational Science, RIKEN. His research interests include compilers and parallel programming languages.
    </p>
    <strong>Email</strong>
    <p>
        h-murai@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="16"></a>
    <h4 class="talk-title">
        Advantages of the Compiler for Post-K computer
    </h4>

        <em>By</em> Shun Kamatsuka, Fujitsu

    <p class="talk-abstract">
        Fujitsu is developing the compiler for Post-K computer to achieve high performance and productivity. The compiler utilizes Arm SVE and supports new features of C/C++ and Fortran language standards.

        In this presentation, I will show advantages of the Post-K compiler with Fujitsu's technologies, focusing on SVE and coarray features of Fortran.
    </p>

</div>

<div class="col-sm-3 speaker-info">

</div>
<div class="col-sm-9 session-info">
    <a name="17"></a>
    <h4 class="talk-title">
        Application Development Tools for Post-K Supercomputer
    </h4>

    <em>By</em> Tomotake Nakamura, Fujitsu

    <p class="talk-abstract">
    RIKEN and Fujitsu are developing programming assistance tools for Post-K computer, providing with new values.
    New features such as utilization of Eclipse PTP, and outputting performance data in XML-form are shown in this presentation.
    </p>
    
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/3Mq0GjWE37hIaP" %}

</div>

<div class="col-sm-3 speaker-info">

</div>
<div class="col-sm-9 session-info">
    <a name="18"></a>
    <h4 class="talk-title">
        The perfect mix: SUSE's HPC, Arm and Containers
    </h4>

        <em>By</em> Vojtech Pavlik , SUSE

    <p class="talk-abstract">
    SUSE's operating system is well established in the HPC market as a solid and flexible foundation to build on. SUSE is complementing that with strong Arm expertise and Container skills and tools. A perfect mix for the next generation of Arm-based supercomputer with scalable management. The talk discusses the details of what SUSE offers, including how it was achieved on the technical level, from Arm enablement to its HPCaaS - High Performance Computing as a Service.
    </p>

</div>

<div class="col-sm-3 speaker-info">
    <strong>Vojtech Pavlik Bio</strong>
    <p>
        Vojtěch Pavlík is the director of SUSE Labs, a department of SUSE R&D focusing on core Linux technologies - kernel, compiler, as well as specific applications of those - Real Time and High performance Computing. In his kernel developer past Vojtěch Pavlík worked on support of USB and human input devices in Linux, work which is used today on every Linux and Android device. He enjoys solving interesting problems facing Linux, most recently working on Linux live patching technology.
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="19"></a>
    <h4 class="talk-title">
        OpenMP Extension for Explicit SIMD Programming using Arm SVE
    </h4>

    <em>By</em> Jinpil Lee, RIKEN AICS

    <p class="talk-abstract">
        Recent trends in processor design accommodate wide vector extensions. SIMD vectorization is more important than before to exploit the potential performance of the target architecture. The latest OpenMP specification provides new directives which help compilers produce better code for SIMD auto-vectorization. However, it is hard to optimize the SIMD code performance in OpenMP since the target SIMD code generation mostly relies on the compiler implementation. In this research, we propose a new directive that specifies user-defined SIMD variants of functions used in SIMD loops. The compiler can then use the user-defined SIMD variants when it encounters OpenMP loops instead of auto-vectorized SIMD variants. The user can optimize the SIMD performance by implementing highly-optimized SIMD code with intrinsic functions.
    </p>

</div>

<div class="col-sm-3 speaker-info">
    <strong>Jinpil Lee Bio</strong>
    <p>
        Jinpil Lee received his PhD degree in computer science from University of Tsukuba in 2013, under the supervision of Prof. Mitsuhisa Sato. From 2013 to 2015, he was working in KISTI, the national supercomputing center in Korea. Currently he is working at Riken AICS in Japan, doing research about directive-based parallel programming models.
    </p>
    <strong>Email</strong>
    <p>
        jinpil.lee@riken.jp
    </p>
</div>
<div class="col-sm-9 session-info">
    <a name="20"></a>
    <h4 class="talk-title">
        Performance evaluation with Arm HPC tools for SVE
    </h4>

    <em>By</em> Miwako Tsuji, RIKEN AICS

    <p class="talk-abstract">
        The "co-design" is a bi-directional approach where a system would be designed on demand from applications and the applications must be optimized to the system. The performance estimation and evaluation of applications are important for the co-design. In this talk, we focus on the performance evaluation with Arm HPC tools for SVE.
    </p>
    
    {% include media.html media_url="https://www.slideshare.net/slideshow/embed_code/key/2YSUrOw3n2W4g" %}

</div>

<div class="col-sm-3 speaker-info">
    <strong>Miwako Tsuji Bio</strong>
    <p>
        Miwako Tsuji received master and PhD degrees from Information Science and Technology, Hokkaido University. From 2007 to 2013, she was working in University of Hokkaido, University of Tokyo, University of Tsukuba and Universite de Versailles Saint-Quentin-en-Yvelines. She is a research scientist at RIKEN Advanced Institute for Computational Science since 2013. She is a member of the architecture development team of the flagship 2020 project, i.e. post-K computer project, since the project was started in 2014. She is a coauthor of ACM Gordon Bell Prize in 2011.
    </p>
    <strong>Email</strong>
    <p>
        miwako.tsuji@riken.jp
    </p>
</div>