From 576caf6e4b8d1a93b3283c0915bbe82d32f8c510 Mon Sep 17 00:00:00 2001
From: David RACODON <david.racodon@gmail.com>
Date: Wed, 26 Apr 2023 13:40:21 +0200
Subject: [PATCH] Let's dream...

---
 hierarchy.ys             |  2 +-
 sonar-project.properties |  2 +-
 src/sleep.vhd            | 10 +++++++---
 3 files changed, 9 insertions(+), 5 deletions(-)

diff --git a/hierarchy.ys b/hierarchy.ys
index 9b9661e..55d623c 100644
--- a/hierarchy.ys
+++ b/hierarchy.ys
@@ -1 +1 @@
-hierarchy -top sleep
+hierarchy -top Dream
diff --git a/sonar-project.properties b/sonar-project.properties
index 0cba713..13ff76f 100644
--- a/sonar-project.properties
+++ b/sonar-project.properties
@@ -1,4 +1,4 @@
 sonar.projectKey=github-bugfinder-sample
 sonar.projectName=GitHub - BugFinder Sample
 sonar.sources=./src
-sonar.vhdl.topLevelEntity=sleep
+sonar.vhdl.topLevelEntity=Dream
diff --git a/src/sleep.vhd b/src/sleep.vhd
index ebedf0a..45963d9 100644
--- a/src/sleep.vhd
+++ b/src/sleep.vhd
@@ -1,18 +1,19 @@
 library ieee;
 use ieee.std_logic_1164.all;
 
-entity sleep is
+entity Dream is
   port (
     clk : in std_logic;
     rst : in std_logic;
     i1 : in std_logic;
     i2 : in std_logic;
     o1 : out std_logic;
-    o2 : out std_logic
+    o2 : out std_logic;
+    toto : out std_logic_vector(0 to 3)
   );
 end entity;
 
-architecture rtl of sleep is
+architecture rtl of Dream is
 begin
   p1 : process (clk) is
   begin
@@ -32,7 +33,10 @@ begin
         o2 <= '0';
       else
         o2 <= i1 or i2;
+        toto(0) <= '1';
+        toto(1) <= i1 or i2;
       end if;
     end if;
   end process;
+  toto(3) <= i1 or i2;
 end architecture;
\ No newline at end of file