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db
greybox_tmp
incremental_db
DE0_VGA.asm.rpt
DE0_VGA.cdf
DE0_VGA.done
DE0_VGA.fit.rpt
DE0_VGA.fit.smsg
DE0_VGA.fit.summary
DE0_VGA.flow.rpt
DE0_VGA.jdi
DE0_VGA.map.rpt
DE0_VGA.map.summary
DE0_VGA.pin
DE0_VGA.qpf
DE0_VGA.qsf
DE0_VGA.qws
DE0_VGA.sof
DE0_VGA.sta.rpt
DE0_VGA.sta.summary
DE0_VGA.v
DE0_VGA_Test.v
DE0_VGA_Test.v.bak
DE0_VGA_description.txt
LICENSE.md
PLLJ_PLLSPE_INFO.txt
PLL_PIXEL_CLK.ppf
PLL_PIXEL_CLK.qip
PLL_PIXEL_CLK.v
PLL_PIXEL_CLK_bb.v
README.md
de0_vga.v.bak

README.md

###DE0_VGA


Driver for VGA on the DE0

The DE0 has a VGA connector that is connected to a 12bit (4bit per color) resistor ladder DAC. Driver displays at 1280x1024 @ 60Hz.

Pressing no buttons will display a pure white screen.
Pressing BUTTON0 will push the combination of SW0 - SW9 into the display register. Flipping the toggle switches (SW0-SW9) will change the color in the this mode.
Pressing BUTTON1 shows a horizontal color pattern test.
Pressing BUTTON2 shows a vertical color pattern test.

DE0_VGA.v takes care of the driving the signals. The top level looks at the position of X_pix and Y_pix and figures out what to put on the pixel_color bus.

Quartus II V13.0 Project file: DE0_VGA.qpf

File Hierarchy

  • DE0_VGA_Test.v
    • DE0_VGA.v
      • PLL_PIXEL_CLK.v