From d1a5c3d48953d4c8bdb55d5aa771efc87da9a25d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?=E4=BA=91=E5=B9=95?= <cancet@embedfire.com>
Date: Thu, 22 Feb 2024 08:53:25 +0000
Subject: [PATCH] fix the whole bug

---
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 create mode 100644 target/linux/rockchip/patches-6.1/359-arm64-dts-rockchip-Add-Rockchip-RK3588J.patch
 create mode 100644 target/linux/rockchip/patches-6.1/360-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-S.patch
 create mode 100644 target/linux/rockchip/patches-6.1/361-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-I.patch
 rename target/linux/rockchip/patches-6.1/{005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch => 362-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch} (78%)
 create mode 100644 target/linux/rockchip/patches-6.1/363-rockchip-use-system-LED-for-OpenWrt.patch
 rename target/linux/rockchip/patches-6.1/{101-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch => 364-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch} (65%)
 rename target/linux/rockchip/patches-6.1/{103-nanopi-r4s-sd-signalling.patch => 365-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch} (65%)
 rename target/linux/rockchip/patches-6.1/{205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch => 366-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch} (81%)
 create mode 100644 target/linux/rockchip/patches-6.1/367-dts-rockchip-fix-rock3-a.patch
 create mode 100644 target/linux/rockchip/patches-6.1/368-dts-rockchip-fix-wifi-on-rock-pi-4b.patch
 create mode 100644 target/linux/rockchip/patches-6.1/369-dts-rockchip-fix-nanopi-r5c-r5s.patch
 create mode 100644 target/linux/rockchip/patches-6.1/370-arm64-dts-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch
 create mode 100644 target/linux/rockchip/patches-6.1/371-regulator-fan53555-Remove-unused-_SLEW_SHIFT-definit.patch
 create mode 100644 target/linux/rockchip/patches-6.1/372-regulator-fan53555-Make-use-of-the-bit-macros.patch
 create mode 100644 target/linux/rockchip/patches-6.1/373-regulator-fan53555-Improve-vsel_mask-computation.patch
 create mode 100644 target/linux/rockchip/patches-6.1/374-regulator-fan53555-Use-dev_err_probe.patch
 create mode 100644 target/linux/rockchip/patches-6.1/375-regulator-fan53555-Add-support-for-RK860X.patch
 create mode 100644 target/linux/rockchip/patches-6.1/376-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch
 create mode 100644 target/linux/rockchip/patches-6.1/377-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch
 create mode 100644 target/linux/rockchip/patches-6.1/378-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch
 create mode 100644 target/linux/rockchip/patches-6.1/384-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-em.patch
 create mode 100644 target/linux/rockchip/patches-6.1/385-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch
 create mode 100644 target/linux/rockchip/patches-6.1/386-dt-bindings-vendor-prefixes-add-Indiedroid.patch
 create mode 100644 target/linux/rockchip/patches-6.1/387-dt-bindings-arm-rockchip-Add-Indiedroid-Nova.patch
 create mode 100644 target/linux/rockchip/patches-6.1/388-arm64-dts-rockchip-Add-Indiedroid-Nova-board.patch
 create mode 100644 target/linux/rockchip/patches-6.1/390-PM-devfreq-rockchip-dfi-Embed-desc-into-private-data.patch
 create mode 100644 target/linux/rockchip/patches-6.1/391-PM-devfreq-rockchip-dfi-use-consistent-name-for-priv.patch
 create mode 100644 target/linux/rockchip/patches-6.1/392-PM-devfreq-rockchip-dfi-Add-SoC-specific-init-functi.patch
 create mode 100644 target/linux/rockchip/patches-6.1/393-PM-devfreq-rockchip-dfi-dfi-store-raw-values-in-coun.patch
 create mode 100644 target/linux/rockchip/patches-6.1/394-PM-devfreq-rockchip-dfi-Use-free-running-counter.patch
 create mode 100644 target/linux/rockchip/patches-6.1/395-PM-devfreq-rockchip-dfi-introduce-channel-mask.patch
 create mode 100644 target/linux/rockchip/patches-6.1/396-PM-devfreq-rk3399_dmc-dfi-generalize-DDRTYPE-defines.patch
 create mode 100644 target/linux/rockchip/patches-6.1/397-PM-devfreq-rockchip-dfi-Clean-up-DDR-type-register-d.patch
 create mode 100644 target/linux/rockchip/patches-6.1/398-PM-devfreq-rockchip-dfi-Add-RK3568-support.patch
 create mode 100644 target/linux/rockchip/patches-6.1/399-PM-devfreq-rockchip-dfi-Handle-LPDDR2-correctly.patch
 create mode 100644 target/linux/rockchip/patches-6.1/400-PM-devfreq-rockchip-dfi-Handle-LPDDR4X.patch
 create mode 100644 target/linux/rockchip/patches-6.1/401-PM-devfreq-rockchip-dfi-Pass-private-data-struct-to-.patch
 create mode 100644 target/linux/rockchip/patches-6.1/402-PM-devfreq-rockchip-dfi-Prepare-for-multiple-users.patch
 create mode 100644 target/linux/rockchip/patches-6.1/403-PM-devfreq-rockchip-dfi-give-variable-a-better-name.patch
 create mode 100644 target/linux/rockchip/patches-6.1/404-PM-devfreq-rockchip-dfi-Add-perf-support.patch
 create mode 100644 target/linux/rockchip/patches-6.1/405-PM-devfreq-rockchip-dfi-make-register-stride-SoC-spe.patch
 create mode 100644 target/linux/rockchip/patches-6.1/406-PM-devfreq-rockchip-dfi-account-for-multiple-DDRMON_.patch
 create mode 100644 target/linux/rockchip/patches-6.1/407-PM-devfreq-rockchip-dfi-add-support-for-RK3588.patch
 create mode 100644 target/linux/rockchip/patches-6.1/408-dt-bindings-devfreq-event-convert-Rockchip-DFI-bindi.patch
 create mode 100644 target/linux/rockchip/patches-6.1/409-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3568-su.patch
 create mode 100644 target/linux/rockchip/patches-6.1/410-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3588-su.patch
 create mode 100644 target/linux/rockchip/patches-6.1/411-arm64-dts-rockchip-rk3399-Enable-DFI.patch
 create mode 100644 target/linux/rockchip/patches-6.1/412-arm64-dts-rockchip-rk356x-Add-DFI.patch
 create mode 100644 target/linux/rockchip/patches-6.1/413-arm64-dts-rockchip-rk3588s-Add-DFI.patch
 create mode 100644 target/linux/rockchip/patches-6.1/414-arm64-dts-rockchip-rk3588-add-cpu-2.4-GHz-operating-.patch
 create mode 100644 target/linux/rockchip/patches-6.1/416-dt-bindings-iio-rockchip-Fix-oneOf-condition-failed-.patch
 create mode 100644 target/linux/rockchip/patches-6.1/417-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch
 create mode 100644 target/linux/rockchip/patches-6.1/418-irqchip-gic-v3-Enable-Rockchip-3588001-erratum-worka.patch
 create mode 100644 target/linux/rockchip/patches-6.1/502-arm64-defconfig-Enable-Rockchip-OTP-memory-driver.patch
 create mode 100644 target/linux/rockchip/patches-6.1/503-mfd-rk808-Make-MFD_RK8XX-tristate.patch
 create mode 100644 target/linux/rockchip/patches-6.1/504-dt-bindings-vendor-prefixes-Add-prefix-for-belling.patch
 create mode 100644 target/linux/rockchip/patches-6.1/505-dt-bindings-eeprom-at24-add-Belling-BL24C16A.patch
 create mode 100644 target/linux/rockchip/patches-6.1/506-dt-bindings-phy-rockchip-add-RK3588-PCIe-v3-phy.patch
 create mode 100644 target/linux/rockchip/patches-6.1/507-dt-bindings-PCI-dwc-improve-msi-handling.patch
 create mode 100644 target/linux/rockchip/patches-6.1/508-arm64-defconfig-enable-Synopsys-AHCI-SATA-support.patch
 create mode 100644 target/linux/rockchip/patches-6.1/509-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch
 create mode 100644 target/linux/rockchip/patches-6.1/510-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch
 create mode 100644 target/linux/rockchip/patches-6.1/511-dt-bindings-media-rockchip-Add-resets-property-into-.patch
 create mode 100644 target/linux/rockchip/patches-6.1/512-dt-bindings-es8328-convert-to-DT-schema-format.patch
 create mode 100644 target/linux/rockchip/patches-6.1/513-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch
 create mode 100644 target/linux/rockchip/patches-6.1/515-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch
 create mode 100644 target/linux/rockchip/patches-6.1/516-rockchip-sync-rk3588.patch
 create mode 100644 target/linux/rockchip/patches-6.1/517-usb-typec-tcpm_-try-to-get-role-switch-from-tcpc-fwnode.patch
 create mode 100644 target/linux/rockchip/patches-6.1/518-usb-typec-tcpm-avoid-graph-warning.patch
 create mode 100644 target/linux/rockchip/patches-6.1/519-irqchip-fix-its-timeout-issue.patch
 create mode 100644 target/linux/rockchip/patches-6.1/520-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch
 create mode 100644 target/linux/rockchip/patches-6.1/521-arm64-dts-rockchip-Add-Orange-Pi-5.patch
 create mode 100644 target/linux/rockchip/patches-6.1/522-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch
 create mode 100644 target/linux/rockchip/patches-6.1/523-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch
 create mode 100644 target/linux/rockchip/patches-6.1/524-1-dt-bindings-PCI-dwc-rockchip-Add-atu-property.patch
 create mode 100644 target/linux/rockchip/patches-6.1/524-2-arm64-dts-rockchip-add-missing-mandatory-rk3588-PCIe.patch
 create mode 100644 target/linux/rockchip/patches-6.1/524-3-dt-bindings-PCI-dwc-rockchip-Add-dma-properties.patch
 create mode 100644 target/linux/rockchip/patches-6.1/525-arm64-dts-rockchip-add-missing-rk3588-PCIe-dma-prope.patch
 create mode 100644 target/linux/rockchip/patches-6.1/526-dt-bindings-usb-rockchip-dwc3-fix-reference-to-nonex.patch
 create mode 100644 target/linux/rockchip/patches-6.1/527-dt-bindings-mfd-rk8xx-Deprecate-rockchip-system-powe.patch
 create mode 100644 target/linux/rockchip/patches-6.1/528-dt-bindings-mfd-rk806-Allow-system-power-controller-.patch
 create mode 100644 target/linux/rockchip/patches-6.1/529-mfd-rk8xx-Add-support-for-standard-system-power-cont.patch
 create mode 100644 target/linux/rockchip/patches-6.1/530-mfd-rk8xx-Add-support-for-RK806-power-off.patch
 create mode 100644 target/linux/rockchip/patches-6.1/531-arm64-dts-rockchip-Fix-rk3588-USB-power-domain-clocks.patch
 delete mode 100644 target/linux/rockchip/patches-6.1/801-char-add-support-for-rockchip-hardware-random-number.patch
 create mode 100644 target/linux/rockchip/patches-6.1/993-rockchip-rk356x-add-support-for-new-boards.patch
 delete mode 100644 target/linux/rockchip/patches-6.1/993-v91-i2s-mclk.patch

diff --git a/config/lubancat_defconfig b/config/lubancat_defconfig
index 03d2516c617..87ea6d40268 100644
--- a/config/lubancat_defconfig
+++ b/config/lubancat_defconfig
@@ -1,7 +1,6 @@
 CONFIG_TARGET_rockchip=y
 CONFIG_TARGET_rockchip_armv8=y
 CONFIG_TARGET_MULTI_PROFILE=y
-CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_embedfire_doornet1=y
 CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_embedfire_doornet2=y
 CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_embedfire_lubancat1=y
 CONFIG_TARGET_DEVICE_rockchip_armv8_DEVICE_embedfire_lubancat1n=y
@@ -152,6 +151,7 @@ CONFIG_PACKAGE_alpine-repositories=y
 CONFIG_PACKAGE_apk=y
 CONFIG_PACKAGE_aria2=y
 CONFIG_PACKAGE_ariang=y
+CONFIG_PACKAGE_arm-trusted-firmware-rk3328=y
 CONFIG_PACKAGE_attendedsysupgrade-common=y
 CONFIG_PACKAGE_attr=y
 CONFIG_PACKAGE_autocore-arm=y
@@ -249,6 +249,7 @@ CONFIG_PACKAGE_kmod-crypto-null=y
 CONFIG_PACKAGE_kmod-crypto-rng=y
 CONFIG_PACKAGE_kmod-crypto-seqiv=y
 CONFIG_PACKAGE_kmod-crypto-sha1=y
+CONFIG_PACKAGE_kmod-crypto-sha256=y
 CONFIG_PACKAGE_kmod-crypto-sha512=y
 CONFIG_PACKAGE_kmod-crypto-user=y
 CONFIG_PACKAGE_kmod-dax=y
@@ -322,6 +323,7 @@ CONFIG_PACKAGE_kmod-nf-nat6=y
 CONFIG_PACKAGE_kmod-nf-nathelper=y
 CONFIG_PACKAGE_kmod-nf-nathelper-extra=y
 CONFIG_PACKAGE_kmod-nft-compat=y
+CONFIG_PACKAGE_kmod-nls-base=y
 CONFIG_PACKAGE_kmod-nls-cp437=y
 CONFIG_PACKAGE_kmod-nls-iso8859-1=y
 CONFIG_PACKAGE_kmod-nls-utf8=y
@@ -364,6 +366,7 @@ CONFIG_PACKAGE_kmod-tpm=y
 CONFIG_PACKAGE_kmod-udptunnel4=y
 CONFIG_PACKAGE_kmod-udptunnel6=y
 CONFIG_PACKAGE_kmod-usb-acm=y
+CONFIG_PACKAGE_kmod-usb-core=y
 CONFIG_PACKAGE_kmod-usb-dwc2=y
 CONFIG_PACKAGE_kmod-usb-dwc3=y
 CONFIG_PACKAGE_kmod-usb-ehci=y
@@ -374,10 +377,13 @@ CONFIG_PACKAGE_kmod-usb-gadget-eth=y
 CONFIG_PACKAGE_kmod-usb-gadget-mass-storage=y
 CONFIG_PACKAGE_kmod-usb-gadget-serial=y
 CONFIG_PACKAGE_kmod-usb-lib-composite=y
+CONFIG_PACKAGE_kmod-usb-net=y
 CONFIG_PACKAGE_kmod-usb-net-asix=y
 CONFIG_PACKAGE_kmod-usb-net-asix-ax88179=y
 CONFIG_PACKAGE_kmod-usb-net-cdc-eem=y
+CONFIG_PACKAGE_kmod-usb-net-cdc-ether=y
 CONFIG_PACKAGE_kmod-usb-net-cdc-mbim=y
+CONFIG_PACKAGE_kmod-usb-net-cdc-ncm=y
 CONFIG_PACKAGE_kmod-usb-net-cdc-subset=y
 CONFIG_PACKAGE_kmod-usb-net-dm9601-ether=y
 CONFIG_PACKAGE_kmod-usb-net-hso=y
@@ -391,6 +397,7 @@ CONFIG_PACKAGE_kmod-usb-net-pl=y
 CONFIG_PACKAGE_kmod-usb-net-qmi-wwan=y
 CONFIG_PACKAGE_kmod-usb-net-rndis=y
 CONFIG_PACKAGE_kmod-usb-net-rtl8150=y
+CONFIG_PACKAGE_kmod-usb-net-rtl8152=y
 CONFIG_PACKAGE_kmod-usb-net-sierrawireless=y
 CONFIG_PACKAGE_kmod-usb-net-smsc95xx=y
 CONFIG_PACKAGE_kmod-usb-net-sr9700=y
@@ -1153,6 +1160,7 @@ CONFIG_PACKAGE_ppp-mod-pptp=y
 CONFIG_PACKAGE_procps-ng=y
 CONFIG_PACKAGE_procps-ng-ps=y
 CONFIG_PACKAGE_qmi-utils=y
+CONFIG_PACKAGE_r8152-firmware=y
 CONFIG_PACKAGE_resize2fs=y
 CONFIG_PACKAGE_resolveip=y
 CONFIG_PACKAGE_rpcd=y
diff --git a/include/kernel-6.1 b/include/kernel-6.1
index fde32f3ca32..95dede372aa 100644
--- a/include/kernel-6.1
+++ b/include/kernel-6.1
@@ -1,2 +1,2 @@
-LINUX_VERSION-6.1 = .73
-LINUX_KERNEL_HASH-6.1.73 = 6cad48706bf1cde342613dca2a2cd6dd4f79f88f9e4d356263564e4b2a5d7e87
+LINUX_VERSION-6.1 = .78
+LINUX_KERNEL_HASH-6.1.78 = 65206b969831236849c9906eba267e715734a93808e9909fd9b4f12eea10d689
diff --git a/package/boot/uboot-rockchip/Makefile b/package/boot/uboot-rockchip/Makefile
index c37da7c96ab..f931a76c4b9 100644
--- a/package/boot/uboot-rockchip/Makefile
+++ b/package/boot/uboot-rockchip/Makefile
@@ -207,6 +207,12 @@ else
 	$(CP) $(PKG_BUILD_DIR)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
 	$(CP) $(PKG_BUILD_DIR)/u-boot.itb $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
 endif
+
+ifneq ($(OF_PRE_BUILD),)
+	$(CP) $(PKG_BUILD_DIR)/of-pre-build/$(OF_PRE_BUILD)/idbloader.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-idbloader.img
+	$(CP) $(PKG_BUILD_DIR)/of-pre-build/$(OF_PRE_BUILD)/uboot.img $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-u-boot.itb
+	$(CP) $(PKG_BUILD_DIR)/of-pre-build/$(OF_PRE_BUILD)/boot.scr $(STAGING_DIR_IMAGE)/$(BUILD_VARIANT)-boot.scr
+endif
 endef
 
 define Package/u-boot/install/default
diff --git a/package/boot/uboot-rockchip/patches/202-rockchip-rk356x-add-support-for-new-boards.patch b/package/boot/uboot-rockchip/patches/202-rockchip-rk356x-add-support-for-new-boards.patch
new file mode 100644
index 00000000000..0898e49ff4b
--- /dev/null
+++ b/package/boot/uboot-rockchip/patches/202-rockchip-rk356x-add-support-for-new-boards.patch
@@ -0,0 +1,29 @@
+From 190d2a3d5a6522a61a2a6b2f3980fbed81cd049a Mon Sep 17 00:00:00 2001
+From: DHDAXCW <lasstp5011@gmail.com>
+Date: Thu, 22 Feb 2024 08:49:34 +0800
+Subject: [PATCH] wode
+
+---
+ arch/arm/dts/Makefile | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
+index 92118411..c401b767 100644
+--- a/arch/arm/dts/Makefile
++++ b/arch/arm/dts/Makefile
+@@ -167,6 +167,12 @@ dtb-$(CONFIG_ROCKCHIP_RK3399) += \
+ 
+ dtb-$(CONFIG_ROCKCHIP_RK3568) += \
+ 	rk3568-evb.dtb \
++	rk3566-lubancat-zero-n.dtb \
++	rk3566-lubancat1.dtb \
++	rk3566-lubancat1n.dtb \
++	rk3568-lubancat2.dtb \
++	rk3568-lubancat2n.dtb \
++	rk3568-lubancat2io.dtb \
+ 	rk3566-quartz64-a.dtb \
+ 	rk3568-rock-3a.dtb
+ 
+-- 
+2.34.1
+
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat-zero-n-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat-zero-n-u-boot.dtsi
new file mode 100644
index 00000000000..3f6bc812585
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat-zero-n-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat-zero-n.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat-zero-n.dts
new file mode 100644
index 00000000000..a4f8a113320
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat-zero-n.dts
@@ -0,0 +1,480 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "EmbedFire LubanCat Zero N";
+	compatible = "embedfire,lubancat-zero-n", "rockchip,rk3566";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: sys-led {
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	usb_5v: usb-5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&usb_5v>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&gmac1 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 75ms, 100ms */
+    snps,reset-delays-us = <0 75000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+    assigned-clock-rates = <0>, <125000000>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac1m1_miim
+             &gmac1m1_tx_bus2_level3
+             &gmac1m1_rx_bus2
+             &gmac1m1_rgmii_clk_level2
+             &gmac1m1_rgmii_bus_level3>;
+
+    tx_delay = <0x24>;
+    rx_delay = <0x08>;
+
+    phy-handle = <&rgmii_phy1>;
+    status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-status-led-pin {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+    status = "okay";
+    pmuio2-supply = <&vcc3v3_pmu>;
+    vccio1-supply = <&vccio_acodec>;
+    vccio3-supply = <&vccio_sd>;
+    vccio4-supply = <&vcc_3v3>;
+    vccio5-supply = <&vcc_3v3>;
+    vccio6-supply = <&vcc_1v8>;
+    vccio7-supply = <&vcc_3v3>;
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1-u-boot.dtsi
new file mode 100644
index 00000000000..3f6bc812585
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1.dts
new file mode 100644
index 00000000000..419843aca90
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1.dts
@@ -0,0 +1,535 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "EmbedFire LubanCat 1";
+	compatible = "embedfire,lubancat1", "rockchip,rk3566";
+
+	aliases {
+		ethernet0 = &gmac1;
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: sys-led {
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	usb_5v: usb-5v-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "usb_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&usb_5v>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc3v3_pcie: vcc3v3-pcie-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_pcie";
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		enable-active-high;
+		gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+		startup-delay-us = <5000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
+		regulator-name = "vcc5v0_usb20_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb30_host_en>;
+		regulator-name = "vcc5v0_usb30_host";
+		regulator-always-on;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&combphy1 {
+	status = "okay";
+};
+
+&combphy2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		wakeup-source;
+		#clock-cells = <1>;
+
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&gmac1 {
+	phy-mode = "rgmii";
+	clock_in_out = "output";
+	snps,reset-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
+	snps,reset-active-low;
+	/* Reset time is 75ms, 100ms */
+	snps,reset-delays-us = <0 75000 100000>;
+	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+	assigned-clock-rates = <0>, <125000000>;
+	pinctrl-names = "default";
+	pinctrl-0 = <&gmac1m1_miim
+			&gmac1m1_tx_bus2_level3
+			&gmac1m1_rx_bus2
+			&gmac1m1_rgmii_clk_level2
+			&gmac1m1_rgmii_bus_level3>;
+	tx_delay = <0x1a>;
+	rx_delay = <0x0c>; 
+	phy-handle = <&rgmii_phy1>;
+	status = "okay";
+};
+
+&mdio1 {
+	rgmii_phy1: phy@0 {
+		compatible = "ethernet-phy-ieee802.3-c22";
+		reg = <0x0>;
+	};
+};
+
+&pcie2x1 {
+	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
+	disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+	vpcie3v3-supply = <&vcc3v3_pcie>;
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-status-led-pin {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
+
+&pmu_io_domains {
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_3v3>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdhci {
+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;		
+	non-removable;	
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
+	supports-emmc;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1n-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1n-u-boot.dtsi
new file mode 100644
index 00000000000..5f5afa88e6d
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1n-u-boot.dtsi
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,dm-spl;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	clock-frequency = <24000000>;
+	u-boot,dm-spl;
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1n.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1n.dts
new file mode 100644
index 00000000000..335aba02216
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3566-lubancat1n.dts
@@ -0,0 +1,485 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+	model = "EmbedFire LubanCat1N";
+	compatible = "embedfire,lubancat1n", "rockchip,rk3566";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+	
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: sys-led {
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	dc_5v: dc-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_5v>;
+	};
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&gmac1 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 100ms, 100ms */
+    snps,reset-delays-us = <0 75000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+    assigned-clock-rates = <0>, <125000000>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac1m1_miim
+             &gmac1m1_tx_bus2_level3
+             &gmac1m1_rx_bus2
+             &gmac1m1_rgmii_clk_level2
+             &gmac1m1_rgmii_bus_level3>;
+
+    tx_delay = <0x24>;
+    rx_delay = <0x08>;
+
+    phy-handle = <&rgmii_phy1>;
+    status = "okay";
+};
+
+&mdio1 {
+    rgmii_phy1: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+&pmu_io_domains {
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdhci {
+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;		
+	non-removable;	
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
+	supports-emmc;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	status = "okay";
+};
+
+&u2phy0_otg {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-status-led-pin {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2-u-boot.dtsi
new file mode 100644
index 00000000000..3f6bc812585
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2.dts
new file mode 100644
index 00000000000..bb9b48f783c
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2.dts
@@ -0,0 +1,590 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+    model = "EmbedFire LubanCat 2";
+    compatible = "embedfire,lubancat2", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac0_clkin: external-gmac0-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac0_clkin";
+		#clock-cells = <0>;
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+	
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: sys-led {
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	dc_5v: dc-5v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_5v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&vcc5v0_sys>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_5v>;
+	};
+
+	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
+		regulator-name = "vcc5v0_usb20_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb30_host_en>;
+		regulator-name = "vcc5v0_usb30_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_vbus_en>;
+		regulator-name = "vcc5v0_otg_vbus";
+	};
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+&gmac0 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 20ms, 100ms for rtl8211f */
+    snps,reset-delays-us = <0 20000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac0_miim
+             &gmac0_tx_bus2
+             &gmac0_rx_bus2
+             &gmac0_rgmii_clk
+             &gmac0_rgmii_bus>;
+
+    tx_delay = <0x22>;
+    rx_delay = <0x0e>;
+
+    phy-handle = <&rgmii_phy0>;
+    status = "okay";
+};
+
+&mdio0 {
+    rgmii_phy0: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+&gmac1 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 20ms, 100ms for rtl8211f */
+    snps,reset-delays-us = <0 20000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac1m1_miim
+             &gmac1m1_tx_bus2
+             &gmac1m1_rx_bus2
+             &gmac1m1_rgmii_clk
+             &gmac1m1_rgmii_bus>;
+
+    tx_delay = <0x21>;
+    rx_delay = <0x0e>;
+
+    phy-handle = <&rgmii_phy1>;
+    status = "okay";
+};
+
+&mdio1 {
+    rgmii_phy1: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+&pmu_io_domains {
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm8 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart3m1_xfer>;
+	status = "disabled";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdhci {
+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;		
+	non-removable;	
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
+	supports-emmc;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_otg_vbus>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&sata0 {
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-status-led-pin {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
+			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2io-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2io-u-boot.dtsi
new file mode 100644
index 00000000000..3f6bc812585
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2io-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2io.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2io.dts
new file mode 100644
index 00000000000..be1f84459b2
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2io.dts
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+    model = "EmbedFire LubanCat 2IO";
+    compatible = "embedfire,lubancat2io", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac0_clkin: external-gmac0-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac0_clkin";
+		#clock-cells = <0>;
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+	
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: sys-led {
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio3 RK_PA6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
+		regulator-name = "vcc5v0_usb20_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb30_host_en>;
+		regulator-name = "vcc5v0_usb30_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_vbus_en>;
+		regulator-name = "vcc5v0_otg_vbus";
+	};
+
+	sata_power: sata-power-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "sata_power";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio1 RK_PA4 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sata_pwr_en>;
+	};
+
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+// ETH0
+&gmac0 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio1 RK_PA1 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 20ms, 100ms for rtl8211f */
+    snps,reset-delays-us = <0 20000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac0_miim
+             &gmac0_tx_bus2
+             &gmac0_rx_bus2
+             &gmac0_rgmii_clk
+             &gmac0_rgmii_bus>;
+
+	tx_delay = <0x1c>;
+	rx_delay = <0x08>;
+
+    phy-handle = <&rgmii_phy0>;
+    status = "okay";
+};
+
+&mdio0 {
+    rgmii_phy0: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+// ETH1
+&gmac1 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 20ms, 100ms for rtl8211f */
+    snps,reset-delays-us = <0 20000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac1m1_miim
+             &gmac1m1_tx_bus2
+             &gmac1m1_rx_bus2
+             &gmac1m1_rgmii_clk
+             &gmac1m1_rgmii_bus>;
+
+	tx_delay = <0x26>;
+	rx_delay = <0x00>;
+
+    phy-handle = <&rgmii_phy1>;
+    status = "okay";
+};
+
+&mdio1 {
+    rgmii_phy1: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+&pmu_io_domains {
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm8 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdhci {
+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;		
+	non-removable;	
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
+	supports-emmc;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_otg_vbus>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&sata0 {
+	target-supply = <&sata_power>;
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-status-led-pin {
+			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
+			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sata {
+		sata_pwr_en: sata-pwr-en {
+			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2n-u-boot.dtsi b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2n-u-boot.dtsi
new file mode 100644
index 00000000000..3f6bc812585
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2n-u-boot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
+ */
+
+#include "rk3568-u-boot.dtsi"
+
+/ {
+	chosen {
+		stdout-path = &uart2;
+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
+	};
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	u-boot,spl-fifo-mode;
+};
+
+&uart2 {
+	u-boot,dm-spl;
+	clock-frequency = <24000000>;
+	status = "okay";
+};
diff --git a/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2n.dts b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2n.dts
new file mode 100644
index 00000000000..1c196dae87a
--- /dev/null
+++ b/package/boot/uboot-rockchip/src/arch/arm/dts/rk3568-lubancat2n.dts
@@ -0,0 +1,602 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
+*/
+
+/dts-v1/;
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/leds/common.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include <dt-bindings/soc/rockchip,vop2.h>
+#include "rk3568.dtsi"
+
+/ {
+    model = "EmbedFire LubanCat 2N";
+    compatible = "embedfire,lubancat2n", "rockchip,rk3568";
+
+	aliases {
+		mmc0 = &sdmmc0;
+		mmc1 = &sdhci;
+	};
+
+	chosen: chosen {
+		stdout-path = "serial2:1500000n8";
+	};
+
+	gmac0_clkin: external-gmac0-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac0_clkin";
+		#clock-cells = <0>;
+	};
+
+	gmac1_clkin: external-gmac1-clock {
+		compatible = "fixed-clock";
+		clock-frequency = <125000000>;
+		clock-output-names = "gmac1_clkin";
+		#clock-cells = <0>;
+	};
+	
+	gpio-leds {
+		compatible = "gpio-leds";
+
+		sys_led: sys-led {
+			label = "sys_led";
+			linux,default-trigger = "heartbeat";
+			default-state = "on";
+			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
+			pinctrl-names = "default";
+			pinctrl-0 = <&sys_led_pin>;
+		};
+	};
+
+	dc_12v: dc-12v {
+		compatible = "regulator-fixed";
+		regulator-name = "dc_12v";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+	};
+
+	vcc3v3_sys: vcc3v3-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc3v3_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <3300000>;
+		regulator-max-microvolt = <3300000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_sys: vcc5v0-sys {
+		compatible = "regulator-fixed";
+		regulator-name = "vcc5v0_sys";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		vin-supply = <&dc_12v>;
+	};
+
+	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb20_host_en>;
+		regulator-name = "vcc5v0_usb20_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_usb30_host_en>;
+		regulator-name = "vcc5v0_usb30_host";
+		regulator-always-on;
+	};
+
+	vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
+		compatible = "regulator-fixed";
+		enable-active-high;
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&vcc5v0_otg_vbus_en>;
+		regulator-name = "vcc5v0_otg_vbus";
+	};
+
+	sata_power: sata-power-regulator {
+		compatible = "regulator-fixed";
+		regulator-name = "sata_power";
+		regulator-min-microvolt = <12000000>;
+		regulator-max-microvolt = <12000000>;
+		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+		enable-active-high;
+		regulator-boot-on;
+		pinctrl-names = "default";
+		pinctrl-0 = <&sata_pwr_en>;
+	};
+
+};
+
+&cpu0 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+	cpu-supply = <&vdd_cpu>;
+};
+
+&i2c0 {
+	status = "okay";
+
+	vdd_cpu: regulator@1c {
+		compatible = "tcs,tcs4525";
+		reg = <0x1c>;
+		fcs,suspend-voltage-selector = <1>;
+		regulator-name = "vdd_cpu";
+		regulator-always-on;
+		regulator-boot-on;
+		regulator-min-microvolt = <800000>;
+		regulator-max-microvolt = <1150000>;
+		regulator-ramp-delay = <2300>;
+		vin-supply = <&vcc5v0_sys>;
+
+		regulator-state-mem {
+			regulator-off-in-suspend;
+		};
+	};
+
+	rk809: pmic@20 {
+		compatible = "rockchip,rk809";
+		reg = <0x20>;
+		interrupt-parent = <&gpio0>;
+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+		#clock-cells = <1>;
+		clock-names = "mclk";
+		clocks = <&cru I2S1_MCLKOUT_TX>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&pmic_int>;
+		rockchip,system-power-controller;
+		#sound-dai-cells = <0>;
+		vcc1-supply = <&vcc3v3_sys>;
+		vcc2-supply = <&vcc3v3_sys>;
+		vcc3-supply = <&vcc3v3_sys>;
+		vcc4-supply = <&vcc3v3_sys>;
+		vcc5-supply = <&vcc3v3_sys>;
+		vcc6-supply = <&vcc3v3_sys>;
+		vcc7-supply = <&vcc3v3_sys>;
+		vcc8-supply = <&vcc3v3_sys>;
+		vcc9-supply = <&vcc3v3_sys>;
+		wakeup-source;
+
+		regulators {
+			vdd_logic: DCDC_REG1 {
+				regulator-name = "vdd_logic";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdd_gpu: DCDC_REG2 {
+				regulator-name = "vdd_gpu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_ddr: DCDC_REG3 {
+				regulator-name = "vcc_ddr";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+				};
+			};
+
+			vdd_npu: DCDC_REG4 {
+				regulator-name = "vdd_npu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <500000>;
+				regulator-max-microvolt = <1350000>;
+				regulator-init-microvolt = <900000>;
+				regulator-ramp-delay = <6001>;
+				regulator-initial-mode = <0x2>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_1v8: DCDC_REG5 {
+				regulator-name = "vcc_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_image: LDO_REG1 {
+				regulator-name = "vdda0v9_image";
+				regulator-boot-on;
+				regulator-always-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda_0v9: LDO_REG2 {
+				regulator-name = "vdda_0v9";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vdda0v9_pmu: LDO_REG3 {
+				regulator-name = "vdda0v9_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <900000>;
+				regulator-max-microvolt = <900000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <900000>;
+				};
+			};
+
+			vccio_acodec: LDO_REG4 {
+				regulator-name = "vccio_acodec";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vccio_sd: LDO_REG5 {
+				regulator-name = "vccio_sd";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_pmu: LDO_REG6 {
+				regulator-name = "vcc3v3_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <3300000>;
+				regulator-max-microvolt = <3300000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <3300000>;
+				};
+			};
+
+			vcca_1v8: LDO_REG7 {
+				regulator-name = "vcca_1v8";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcca1v8_pmu: LDO_REG8 {
+				regulator-name = "vcca1v8_pmu";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-on-in-suspend;
+					regulator-suspend-microvolt = <1800000>;
+				};
+			};
+
+			vcca1v8_image: LDO_REG9 {
+				regulator-name = "vcca1v8_image";
+				regulator-always-on;
+				regulator-boot-on;
+				regulator-min-microvolt = <1800000>;
+				regulator-max-microvolt = <1800000>;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc_3v3: SWITCH_REG1 {
+				regulator-name = "vcc_3v3";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+
+			vcc3v3_sd: SWITCH_REG2 {
+				regulator-name = "vcc3v3_sd";
+				regulator-always-on;
+				regulator-boot-on;
+
+				regulator-state-mem {
+					regulator-off-in-suspend;
+				};
+			};
+		};
+	};
+};
+
+&i2s1_8ch {
+	rockchip,trcm-sync-tx-only;
+	status = "okay";
+};
+
+// ETH0
+&gmac0 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 20ms, 100ms for rtl8211f */
+    snps,reset-delays-us = <0 20000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
+    assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac0_miim
+             &gmac0_tx_bus2
+             &gmac0_rx_bus2
+             &gmac0_rgmii_clk
+             &gmac0_rgmii_bus>;
+
+    tx_delay = <0x19>;
+    rx_delay = <0x10>;
+
+    phy-handle = <&rgmii_phy0>;
+    status = "okay";
+};
+
+&mdio0 {
+    rgmii_phy0: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+// ETH1
+&gmac1 {
+    phy-mode = "rgmii";
+    clock_in_out = "output";
+
+    snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
+    snps,reset-active-low;
+    /* Reset time is 20ms, 100ms for rtl8211f */
+    snps,reset-delays-us = <0 20000 100000>;
+
+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
+
+    pinctrl-names = "default";
+    pinctrl-0 = <&gmac1m1_miim
+             &gmac1m1_tx_bus2
+             &gmac1m1_rx_bus2
+             &gmac1m1_rgmii_clk
+             &gmac1m1_rgmii_bus>;
+
+    tx_delay = <0x1f>;
+    rx_delay = <0x0c>;
+
+    phy-handle = <&rgmii_phy1>;
+    status = "okay";
+};
+
+&mdio1 {
+    rgmii_phy1: phy@0 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <0x0>;
+    };
+};
+
+&pmu_io_domains {
+	pmuio2-supply = <&vcc3v3_pmu>;
+	vccio1-supply = <&vccio_acodec>;
+	vccio3-supply = <&vccio_sd>;
+	vccio4-supply = <&vcc_1v8>;
+	vccio5-supply = <&vcc_3v3>;
+	vccio6-supply = <&vcc_1v8>;
+	vccio7-supply = <&vcc_3v3>;
+	status = "okay";
+};
+
+&pwm8 {
+	status = "okay";
+};
+
+&uart2 {
+	status = "okay";
+};
+
+&saradc {
+	vref-supply = <&vcca_1v8>;
+	status = "okay";
+};
+
+&tsadc {
+	rockchip,hw-tshut-mode = <1>;
+	rockchip,hw-tshut-polarity = <0>;
+	status = "okay";
+};
+
+&sdhci {
+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
+	bus-width = <8>;
+	max-frequency = <200000000>;
+	mmc-hs200-1_8v;		
+	non-removable;	
+	pinctrl-names = "default";
+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
+	supports-emmc;
+	status = "okay";
+};
+
+&sdmmc0 {
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
+};
+
+/* USB OTG/USB Host_1 USB 2.0 Comb */
+&u2phy0 {
+	status = "okay";
+};
+
+&u2phy0_host {
+	phy-supply = <&vcc5v0_usb30_host>;
+	status = "okay";
+};
+
+&u2phy0_otg {
+	phy-supply = <&vcc5v0_otg_vbus>;
+	status = "okay";
+};
+
+&usb_host0_ehci {
+	status = "okay";
+};
+
+&usb_host0_ohci {
+	status = "okay";
+};
+
+/* USB Host_2/USB Host_3 USB 2.0 Comb */
+&u2phy1 {
+	status = "okay";
+};
+
+&u2phy1_host {
+	status = "okay";
+};
+
+&u2phy1_otg {
+	phy-supply = <&vcc5v0_usb20_host>;
+	status = "okay";
+};
+
+&usb_host1_ehci {
+	status = "okay";
+};
+
+&usb_host1_ohci {
+	status = "okay";
+};
+
+&sata0 {
+	target-supply = <&sata_power>;
+	status = "okay";
+};
+
+&pinctrl {
+	leds {
+		sys_led_pin: sys-status-led-pin {
+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	usb {
+		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
+			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
+			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
+			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
+	pmic {
+		pmic_int: pmic_int {
+			rockchip,pins =
+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+		};
+	};
+
+	sata {
+		sata_pwr_en: sata-pwr-en {
+			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+};
diff --git a/package/boot/uboot-rockchip/src/configs/lubancat-zero-n-rk3566_defconfig b/package/boot/uboot-rockchip/src/configs/lubancat-zero-n-rk3566_defconfig
index 8a7a7838606..8be03a796a0 100644
--- a/package/boot/uboot-rockchip/src/configs/lubancat-zero-n-rk3566_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/lubancat-zero-n-rk3566_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
@@ -78,17 +79,4 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_ERRNO_STR=y
\ No newline at end of file
+CONFIG_ERRNO_STR=y
diff --git a/package/boot/uboot-rockchip/src/configs/lubancat1-rk3566_defconfig b/package/boot/uboot-rockchip/src/configs/lubancat1-rk3566_defconfig
index d9135f14ecb..c713885e11c 100644
--- a/package/boot/uboot-rockchip/src/configs/lubancat1-rk3566_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/lubancat1-rk3566_defconfig
@@ -5,13 +5,14 @@ CONFIG_SYS_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3566-lubancat1n"
+CONFIG_DEFAULT_DEVICE_TREE="rk3566-lubancat1"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
@@ -21,7 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-lubancat1n.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3566-lubancat1.dtb"
 # CONFIG_SYS_DEVICE_NULLDEV is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -78,17 +79,4 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_ERRNO_STR=y
\ No newline at end of file
+CONFIG_ERRNO_STR=y
diff --git a/package/boot/uboot-rockchip/src/configs/lubancat1n-rk3566_defconfig b/package/boot/uboot-rockchip/src/configs/lubancat1n-rk3566_defconfig
index d9135f14ecb..4aea0867858 100644
--- a/package/boot/uboot-rockchip/src/configs/lubancat1n-rk3566_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/lubancat1n-rk3566_defconfig
@@ -12,6 +12,7 @@ CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
@@ -78,17 +79,4 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_ERRNO_STR=y
\ No newline at end of file
+CONFIG_ERRNO_STR=y
diff --git a/package/boot/uboot-rockchip/src/configs/lubancat2-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/lubancat2-rk3568_defconfig
index fe95383c48d..3a6229447ce 100644
--- a/package/boot/uboot-rockchip/src/configs/lubancat2-rk3568_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/lubancat2-rk3568_defconfig
@@ -5,13 +5,14 @@ CONFIG_SYS_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat2"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
@@ -21,7 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat2.dtb"
 # CONFIG_SYS_DEVICE_NULLDEV is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -78,17 +79,4 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_ERRNO_STR=y
\ No newline at end of file
diff --git a/package/boot/uboot-rockchip/src/configs/lubancat2io-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/lubancat2io-rk3568_defconfig
index a636b58c5c5..e779e36fdf6 100644
--- a/package/boot/uboot-rockchip/src/configs/lubancat2io-rk3568_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/lubancat2io-rk3568_defconfig
@@ -5,13 +5,14 @@ CONFIG_SYS_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat2io"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
@@ -21,7 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat2io.dtb"
 # CONFIG_SYS_DEVICE_NULLDEV is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -78,17 +79,4 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
-CONFIG_ERRNO_STR=y
\ No newline at end of file
+CONFIG_ERRNO_STR=y
diff --git a/package/boot/uboot-rockchip/src/configs/lubancat2n-rk3568_defconfig b/package/boot/uboot-rockchip/src/configs/lubancat2n-rk3568_defconfig
index 63720b04f77..5142c5bace3 100644
--- a/package/boot/uboot-rockchip/src/configs/lubancat2n-rk3568_defconfig
+++ b/package/boot/uboot-rockchip/src/configs/lubancat2n-rk3568_defconfig
@@ -5,13 +5,14 @@ CONFIG_SYS_TEXT_BASE=0x00a00000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_DEFAULT_DEVICE_TREE="rk3568-evb"
+CONFIG_DEFAULT_DEVICE_TREE="rk3568-lubancat2n"
 CONFIG_ROCKCHIP_RK3568=y
 CONFIG_SPL_ROCKCHIP_BACK_TO_BROM=y
 CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y
 CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_STACK_R_ADDR=0x600000
+CONFIG_TARGET_EVB_RK3568=y
 CONFIG_DEBUG_UART_BASE=0xFE660000
 CONFIG_DEBUG_UART_CLOCK=24000000
 CONFIG_DEBUG_UART=y
@@ -21,7 +22,7 @@ CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_OF_SYSTEM_SETUP=y
-CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-evb.dtb"
+CONFIG_DEFAULT_FDT_FILE="rockchip/rk3568-lubancat2n.dtb"
 # CONFIG_SYS_DEVICE_NULLDEV is not set
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
@@ -56,16 +57,16 @@ CONFIG_MMC_HS200_SUPPORT=y
 CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_DM_PMIC=y
-CONFIG_PMIC_RK8XX=y
-CONFIG_SPL_PMIC_RK8XX=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_SDMA=y
 CONFIG_MMC_SDHCI_ROCKCHIP=y
 CONFIG_DM_ETH=y
 CONFIG_ETH_DESIGNWARE=y
 CONFIG_GMAC_ROCKCHIP=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_RK8XX=y
+CONFIG_SPL_PMIC_RK8XX=y
 CONFIG_REGULATOR_PWM=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPL_DM_REGULATOR_FIXED=y
@@ -78,17 +79,4 @@ CONFIG_BAUDRATE=1500000
 CONFIG_DEBUG_UART_SHIFT=2
 CONFIG_SYSRESET=y
 CONFIG_SYSRESET_PSCI=y
-CONFIG_USB=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_USB_EHCI_HCD=y
-CONFIG_USB_EHCI_GENERIC=y
-CONFIG_USB_DWC3=y
-CONFIG_USB_DWC3_GENERIC=y
-CONFIG_ROCKCHIP_USB2_PHY=y
-CONFIG_USB_KEYBOARD=y
-CONFIG_USB_HOST_ETHER=y
-CONFIG_USB_ETHER_LAN75XX=y
-CONFIG_USB_ETHER_LAN78XX=y
-CONFIG_USB_ETHER_SMSC95XX=y
 CONFIG_ERRNO_STR=y
\ No newline at end of file
diff --git a/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch
index 73acadd804c..865da6b1828 100644
--- a/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch
+++ b/target/linux/generic/backport-5.15/020-v6.1-01-mm-x86-arm64-add-arch_has_hw_pte_young.patch
@@ -329,7 +329,7 @@ Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
 
 --- a/arch/arm64/include/asm/pgtable.h
 +++ b/arch/arm64/include/asm/pgtable.h
-@@ -999,23 +999,13 @@ static inline void update_mmu_cache(stru
+@@ -1005,23 +1005,13 @@ static inline void update_mmu_cache(stru
   * page after fork() + CoW for pfn mappings. We don't always have a
   * hardware-managed access flag on arm64.
   */
diff --git a/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch b/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch
index 51c23b6e349..819cc292e86 100644
--- a/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch
+++ b/target/linux/generic/backport-5.15/080-v5.17-clk-gate-Add-devm_clk_hw_register_gate.patch
@@ -66,7 +66,7 @@ Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchi
 +EXPORT_SYMBOL_GPL(__devm_clk_hw_register_gate);
 --- a/include/linux/clk-provider.h
 +++ b/include/linux/clk-provider.h
-@@ -490,6 +490,13 @@ struct clk_hw *__clk_hw_register_gate(st
+@@ -517,6 +517,13 @@ struct clk_hw *__clk_hw_register_gate(st
  		unsigned long flags,
  		void __iomem *reg, u8 bit_idx,
  		u8 clk_gate_flags, spinlock_t *lock);
@@ -80,7 +80,7 @@ Link: https://lore.kernel.org/r/20211103085102.1656081-2-horatiu.vultur@microchi
  struct clk *clk_register_gate(struct device *dev, const char *name,
  		const char *parent_name, unsigned long flags,
  		void __iomem *reg, u8 bit_idx,
-@@ -544,6 +551,22 @@ struct clk *clk_register_gate(struct dev
+@@ -571,6 +578,22 @@ struct clk *clk_register_gate(struct dev
  	__clk_hw_register_gate((dev), NULL, (name), NULL, NULL, (parent_data), \
  			       (flags), (reg), (bit_idx),		      \
  			       (clk_gate_flags), (lock))
diff --git a/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch b/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch
index 284a6d07225..eca3c7ff9fd 100644
--- a/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch
+++ b/target/linux/generic/backport-5.15/703-00-v5.16-net-convert-users-of-bitmap_foo-to-linkmode_foo.patch
@@ -554,7 +554,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void xrs700x_mac_link_up(struct dsa_switch *ds, int port,
 --- a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
 +++ b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
-@@ -369,9 +369,8 @@ static int xgbe_set_link_ksettings(struc
+@@ -374,9 +374,8 @@ static int xgbe_set_link_ksettings(struc
  		  __ETHTOOL_LINK_MODE_MASK_NBITS, cmd->link_modes.advertising,
  		  __ETHTOOL_LINK_MODE_MASK_NBITS, lks->link_modes.supported);
  
@@ -566,7 +566,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	if ((cmd->base.autoneg == AUTONEG_ENABLE) &&
  	    bitmap_empty(advertising, __ETHTOOL_LINK_MODE_MASK_NBITS)) {
-@@ -384,8 +383,7 @@ static int xgbe_set_link_ksettings(struc
+@@ -389,8 +388,7 @@ static int xgbe_set_link_ksettings(struc
  	pdata->phy.autoneg = cmd->base.autoneg;
  	pdata->phy.speed = speed;
  	pdata->phy.duplex = cmd->base.duplex;
@@ -747,7 +747,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void mvpp2_xlg_config(struct mvpp2_port *port, unsigned int mode,
 --- a/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
 +++ b/drivers/net/ethernet/marvell/octeontx2/nic/otx2_ethtool.c
-@@ -1168,9 +1168,8 @@ static int otx2_set_link_ksettings(struc
+@@ -1172,9 +1172,8 @@ static int otx2_set_link_ksettings(struc
  	otx2_get_link_ksettings(netdev, &cur_ks);
  
  	/* Check requested modes against supported modes by hardware */
diff --git a/target/linux/generic/backport-5.15/722-v6.0-net-ethernet-mtk_eth_wed-add-axi-bus-support.patch b/target/linux/generic/backport-5.15/722-v6.0-net-ethernet-mtk_eth_wed-add-axi-bus-support.patch
index 70b7bad31f2..f4b78a27989 100644
--- a/target/linux/generic/backport-5.15/722-v6.0-net-ethernet-mtk_eth_wed-add-axi-bus-support.patch
+++ b/target/linux/generic/backport-5.15/722-v6.0-net-ethernet-mtk_eth_wed-add-axi-bus-support.patch
@@ -82,7 +82,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  
  	if (!hw_list[!hw->index]->wed_dev &&
  	    hw->eth->dma_dev != hw->eth->dev)
-@@ -356,40 +380,54 @@ mtk_wed_detach(struct mtk_wed_device *de
+@@ -356,40 +380,47 @@ mtk_wed_detach(struct mtk_wed_device *de
  static void
  mtk_wed_bus_init(struct mtk_wed_device *dev)
  {
@@ -97,7 +97,6 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 +	case MTK_WED_BUS_PCIE: {
 +		struct device_node *np = dev->hw->eth->dev->of_node;
 +		struct regmap *regs;
-+		u32 val;
 +
 +		regs = syscon_regmap_lookup_by_phandle(np,
 +						       "mediatek,wed-pcie");
@@ -139,20 +138,14 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
 +			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
 +		wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
 +
-+		val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
-+		val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
 +		wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
 +		wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
 +
-+		val = wed_r32(dev, MTK_WED_PCIE_CFG_INTM);
-+		val = wed_r32(dev, MTK_WED_PCIE_CFG_BASE);
-+
 +		/* pcie interrupt status trigger register */
 +		wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
 +		wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
 +
 +		/* pola setting */
-+		val = wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
 +		wed_set(dev, MTK_WED_PCIE_INT_CTRL,
 +			MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
 +		break;
@@ -168,7 +161,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  }
  
  static void
-@@ -800,12 +838,14 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -800,12 +831,14 @@ mtk_wed_attach(struct mtk_wed_device *de
  	__releases(RCU)
  {
  	struct mtk_wed_hw *hw;
@@ -184,7 +177,7 @@ Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
  	    !try_module_get(THIS_MODULE))
  		ret = -ENODEV;
  
-@@ -823,8 +863,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -823,8 +856,10 @@ mtk_wed_attach(struct mtk_wed_device *de
  		goto out;
  	}
  
diff --git a/target/linux/generic/backport-5.15/728-v6.1-02-net-ethernet-mtk_eth_wed-add-missing-put_device-in-m.patch b/target/linux/generic/backport-5.15/728-v6.1-02-net-ethernet-mtk_eth_wed-add-missing-put_device-in-m.patch
index ef5374dcc57..4f0b78f1107 100644
--- a/target/linux/generic/backport-5.15/728-v6.1-02-net-ethernet-mtk_eth_wed-add-missing-put_device-in-m.patch
+++ b/target/linux/generic/backport-5.15/728-v6.1-02-net-ethernet-mtk_eth_wed-add-missing-put_device-in-m.patch
@@ -16,7 +16,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1084,11 +1084,11 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1077,11 +1077,11 @@ void mtk_wed_add_hw(struct device_node *
  	get_device(&pdev->dev);
  	irq = platform_get_irq(pdev, 0);
  	if (irq < 0)
@@ -30,7 +30,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	rcu_assign_pointer(mtk_soc_wed_ops, &wed_ops);
  
-@@ -1131,8 +1131,14 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1124,8 +1124,14 @@ void mtk_wed_add_hw(struct device_node *
  
  	hw_list[index] = hw;
  
diff --git a/target/linux/generic/backport-5.15/728-v6.1-03-net-ethernet-mtk_eth_wed-add-missing-of_node_put.patch b/target/linux/generic/backport-5.15/728-v6.1-03-net-ethernet-mtk_eth_wed-add-missing-of_node_put.patch
index 0a452d4a7d4..32f62aaed29 100644
--- a/target/linux/generic/backport-5.15/728-v6.1-03-net-ethernet-mtk_eth_wed-add-missing-of_node_put.patch
+++ b/target/linux/generic/backport-5.15/728-v6.1-03-net-ethernet-mtk_eth_wed-add-missing-of_node_put.patch
@@ -15,7 +15,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1079,7 +1079,7 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1072,7 +1072,7 @@ void mtk_wed_add_hw(struct device_node *
  
  	pdev = of_find_device_by_node(np);
  	if (!pdev)
@@ -24,7 +24,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	get_device(&pdev->dev);
  	irq = platform_get_irq(pdev, 0);
-@@ -1139,6 +1139,8 @@ unlock:
+@@ -1132,6 +1132,8 @@ unlock:
  	mutex_unlock(&hw_lock);
  err_put_device:
  	put_device(&pdev->dev);
@@ -33,7 +33,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  void mtk_wed_exit(void)
-@@ -1159,6 +1161,7 @@ void mtk_wed_exit(void)
+@@ -1152,6 +1154,7 @@ void mtk_wed_exit(void)
  		hw_list[i] = NULL;
  		debugfs_remove(hw->debugfs_dir);
  		put_device(hw->dev);
diff --git a/target/linux/generic/backport-5.15/729-02-v6.1-net-ethernet-mtk_wed-introduce-wed-wo-support.patch b/target/linux/generic/backport-5.15/729-02-v6.1-net-ethernet-mtk_wed-introduce-wed-wo-support.patch
index dbd7e30fbb8..fd5f45df2aa 100644
--- a/target/linux/generic/backport-5.15/729-02-v6.1-net-ethernet-mtk_wed-introduce-wed-wo-support.patch
+++ b/target/linux/generic/backport-5.15/729-02-v6.1-net-ethernet-mtk_wed-introduce-wed-wo-support.patch
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
  		struct device_node *wlan_node;
-@@ -885,9 +888,11 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -878,9 +881,11 @@ mtk_wed_attach(struct mtk_wed_device *de
  	}
  
  	mtk_wed_hw_init_early(dev);
diff --git a/target/linux/generic/backport-5.15/729-03-v6.1-net-ethernet-mtk_wed-rename-tx_wdma-array-in-rx_wdma.patch b/target/linux/generic/backport-5.15/729-03-v6.1-net-ethernet-mtk_wed-rename-tx_wdma-array-in-rx_wdma.patch
index ffd6bc3589d..a002a5f8516 100644
--- a/target/linux/generic/backport-5.15/729-03-v6.1-net-ethernet-mtk_wed-rename-tx_wdma-array-in-rx_wdma.patch
+++ b/target/linux/generic/backport-5.15/729-03-v6.1-net-ethernet-mtk_wed-rename-tx_wdma-array-in-rx_wdma.patch
@@ -23,7 +23,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -695,10 +695,10 @@ mtk_wed_ring_alloc(struct mtk_wed_device
+@@ -688,10 +688,10 @@ mtk_wed_ring_alloc(struct mtk_wed_device
  }
  
  static int
@@ -36,7 +36,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	if (mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE, desc_size))
  		return -ENOMEM;
-@@ -812,9 +812,9 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -805,9 +805,9 @@ mtk_wed_start(struct mtk_wed_device *dev
  {
  	int i;
  
@@ -49,7 +49,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	mtk_wed_hw_init(dev);
  	mtk_wed_configure_irq(dev, irq_mask);
-@@ -923,7 +923,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -916,7 +916,7 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
  			       sizeof(*ring->desc)))
  		return -ENOMEM;
  
diff --git a/target/linux/generic/backport-5.15/729-04-v6.1-net-ethernet-mtk_wed-add-configure-wed-wo-support.patch b/target/linux/generic/backport-5.15/729-04-v6.1-net-ethernet-mtk_wed-add-configure-wed-wo-support.patch
index 4c34d0cb33b..eca29739b4a 100644
--- a/target/linux/generic/backport-5.15/729-04-v6.1-net-ethernet-mtk_wed-add-configure-wed-wo-support.patch
+++ b/target/linux/generic/backport-5.15/729-04-v6.1-net-ethernet-mtk_wed-add-configure-wed-wo-support.patch
@@ -409,7 +409,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
  		struct device_node *wlan_node;
-@@ -441,10 +667,12 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+@@ -434,10 +660,12 @@ mtk_wed_set_wpdma(struct mtk_wed_device
  	} else {
  		mtk_wed_bus_init(dev);
  
@@ -426,7 +426,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  }
  
-@@ -494,6 +722,132 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+@@ -487,6 +715,132 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
  	}
  }
  
@@ -559,7 +559,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void
  mtk_wed_hw_init(struct mtk_wed_device *dev)
  {
-@@ -505,11 +859,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -498,11 +852,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  	wed_w32(dev, MTK_WED_TX_BM_CTRL,
  		MTK_WED_TX_BM_CTRL_PAUSE |
  		FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
@@ -573,7 +573,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
  
-@@ -536,9 +890,9 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -529,9 +883,9 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  		wed_w32(dev, MTK_WED_TX_TKID_CTRL,
  			MTK_WED_TX_TKID_CTRL_PAUSE |
  			FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM,
@@ -585,7 +585,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
  			FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
  			MTK_WED_TX_TKID_DYN_THR_HI);
-@@ -546,18 +900,28 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+@@ -539,18 +893,28 @@ mtk_wed_hw_init(struct mtk_wed_device *d
  
  	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
  
@@ -617,7 +617,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  {
  	void *head = (void *)ring->desc;
  	int i;
-@@ -567,7 +931,10 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+@@ -560,7 +924,10 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
  
  		desc = (struct mtk_wdma_desc *)(head + i * ring->desc_size);
  		desc->buf0 = 0;
@@ -629,7 +629,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		desc->buf1 = 0;
  		desc->info = 0;
  	}
-@@ -623,7 +990,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -616,7 +983,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
  		if (!dev->tx_ring[i].desc)
  			continue;
  
@@ -639,7 +639,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	if (mtk_wed_poll_busy(dev))
-@@ -641,6 +1009,9 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -634,6 +1002,9 @@ mtk_wed_reset_dma(struct mtk_wed_device
  	wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
  	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
  
@@ -649,7 +649,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (busy) {
  		mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
  		mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
-@@ -675,12 +1046,11 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -668,12 +1039,11 @@ mtk_wed_reset_dma(struct mtk_wed_device
  			MTK_WED_WPDMA_RESET_IDX_RX);
  		wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
  	}
@@ -663,7 +663,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  {
  	ring->desc = dma_alloc_coherent(dev->hw->dev, size * desc_size,
  					&ring->desc_phys, GFP_KERNEL);
-@@ -689,7 +1059,7 @@ mtk_wed_ring_alloc(struct mtk_wed_device
+@@ -682,7 +1052,7 @@ mtk_wed_ring_alloc(struct mtk_wed_device
  
  	ring->desc_size = desc_size;
  	ring->size = size;
@@ -672,7 +672,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	return 0;
  }
-@@ -698,9 +1068,14 @@ static int
+@@ -691,9 +1061,14 @@ static int
  mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size)
  {
  	u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
@@ -689,7 +689,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		return -ENOMEM;
  
  	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -717,6 +1092,60 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -710,6 +1085,60 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
  	return 0;
  }
  
@@ -750,7 +750,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void
  mtk_wed_configure_irq(struct mtk_wed_device *dev, u32 irq_mask)
  {
-@@ -739,6 +1168,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -732,6 +1161,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  
  		wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
  	} else {
@@ -759,7 +759,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		/* initail tx interrupt trigger */
  		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
  			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
-@@ -757,6 +1188,16 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+@@ -750,6 +1181,16 @@ mtk_wed_configure_irq(struct mtk_wed_dev
  			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
  				   dev->wlan.txfree_tbit));
  
@@ -776,7 +776,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
  		wed_set(dev, MTK_WED_WDMA_INT_CTRL,
  			FIELD_PREP(MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL,
-@@ -794,9 +1235,15 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -787,9 +1228,15 @@ mtk_wed_dma_enable(struct mtk_wed_device
  		wdma_set(dev, MTK_WDMA_GLO_CFG,
  			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
  	} else {
@@ -792,7 +792,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
  			MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
  			MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
-@@ -804,6 +1251,15 @@ mtk_wed_dma_enable(struct mtk_wed_device
+@@ -797,6 +1244,15 @@ mtk_wed_dma_enable(struct mtk_wed_device
  		wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
  			MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
  			MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
@@ -808,7 +808,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  }
  
-@@ -829,7 +1285,19 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -822,7 +1278,19 @@ mtk_wed_start(struct mtk_wed_device *dev
  		val |= BIT(0) | (BIT(1) * !!dev->hw->index);
  		regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
  	} else {
@@ -829,7 +829,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	mtk_wed_dma_enable(dev);
-@@ -863,7 +1331,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -856,7 +1324,7 @@ mtk_wed_attach(struct mtk_wed_device *de
  	if (!hw) {
  		module_put(THIS_MODULE);
  		ret = -ENODEV;
@@ -838,7 +838,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	device = dev->wlan.bus_type == MTK_WED_BUS_PCIE
-@@ -876,15 +1344,24 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -869,15 +1337,24 @@ mtk_wed_attach(struct mtk_wed_device *de
  	dev->dev = hw->dev;
  	dev->irq = hw->irq;
  	dev->wdma_idx = hw->index;
@@ -866,7 +866,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	}
  
  	mtk_wed_hw_init_early(dev);
-@@ -893,8 +1370,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -886,8 +1363,10 @@ mtk_wed_attach(struct mtk_wed_device *de
  				   BIT(hw->index), 0);
  	else
  		ret = mtk_wed_wo_init(hw);
@@ -878,7 +878,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	mutex_unlock(&hw_lock);
  
  	return ret;
-@@ -917,10 +1396,11 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -910,10 +1389,11 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
  	 * WDMA RX.
  	 */
  
@@ -892,7 +892,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		return -ENOMEM;
  
  	if (mtk_wed_wdma_rx_ring_setup(dev, idx, MTK_WED_WDMA_RING_SIZE))
-@@ -967,6 +1447,37 @@ mtk_wed_txfree_ring_setup(struct mtk_wed
+@@ -960,6 +1440,37 @@ mtk_wed_txfree_ring_setup(struct mtk_wed
  	return 0;
  }
  
@@ -930,7 +930,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static u32
  mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
  {
-@@ -1063,7 +1574,9 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1056,7 +1567,9 @@ void mtk_wed_add_hw(struct device_node *
  	static const struct mtk_wed_ops wed_ops = {
  		.attach = mtk_wed_attach,
  		.tx_ring_setup = mtk_wed_tx_ring_setup,
@@ -940,7 +940,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		.start = mtk_wed_start,
  		.stop = mtk_wed_stop,
  		.reset_dma = mtk_wed_reset_dma,
-@@ -1072,6 +1585,7 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1065,6 +1578,7 @@ void mtk_wed_add_hw(struct device_node *
  		.irq_get = mtk_wed_irq_get,
  		.irq_set_mask = mtk_wed_irq_set_mask,
  		.detach = mtk_wed_detach,
diff --git a/target/linux/generic/backport-5.15/729-09-v6.2-net-ethernet-mtk_wed-add-wcid-overwritten-support-fo.patch b/target/linux/generic/backport-5.15/729-09-v6.2-net-ethernet-mtk_wed-add-wcid-overwritten-support-fo.patch
index d91d8299111..117ccc09025 100644
--- a/target/linux/generic/backport-5.15/729-09-v6.2-net-ethernet-mtk_wed-add-wcid-overwritten-support-fo.patch
+++ b/target/linux/generic/backport-5.15/729-09-v6.2-net-ethernet-mtk_wed-add-wcid-overwritten-support-fo.patch
@@ -27,7 +27,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static void
-@@ -1297,9 +1297,10 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1290,9 +1290,10 @@ mtk_wed_start(struct mtk_wed_device *dev
  		if (mtk_wed_rro_cfg(dev))
  			return;
  
@@ -39,7 +39,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	mtk_wed_dma_enable(dev);
  	dev->running = true;
  }
-@@ -1365,11 +1366,13 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1358,11 +1359,13 @@ mtk_wed_attach(struct mtk_wed_device *de
  	}
  
  	mtk_wed_hw_init_early(dev);
diff --git a/target/linux/generic/backport-5.15/729-10-v6.2-net-ethernet-mtk_wed-return-status-value-in-mtk_wdma.patch b/target/linux/generic/backport-5.15/729-10-v6.2-net-ethernet-mtk_wed-return-status-value-in-mtk_wdma.patch
index d97bb715e0f..ec58c3fc572 100644
--- a/target/linux/generic/backport-5.15/729-10-v6.2-net-ethernet-mtk_wed-return-status-value-in-mtk_wdma.patch
+++ b/target/linux/generic/backport-5.15/729-10-v6.2-net-ethernet-mtk_wed-return-status-value-in-mtk_wdma.patch
@@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	if (dev->wlan.bus_type == MTK_WED_BUS_PCIE) {
-@@ -1006,11 +1009,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -999,11 +1002,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
  		wed_w32(dev, MTK_WED_RESET_IDX, 0);
  	}
  
diff --git a/target/linux/generic/backport-5.15/729-12-v6.2-net-ethernet-mtk_wed-update-mtk_wed_stop.patch b/target/linux/generic/backport-5.15/729-12-v6.2-net-ethernet-mtk_wed-update-mtk_wed_stop.patch
index dfc0f8c3f38..f4e842d515a 100644
--- a/target/linux/generic/backport-5.15/729-12-v6.2-net-ethernet-mtk_wed-update-mtk_wed_stop.patch
+++ b/target/linux/generic/backport-5.15/729-12-v6.2-net-ethernet-mtk_wed-update-mtk_wed_stop.patch
@@ -67,7 +67,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	mtk_wdma_rx_reset(dev);
  	mtk_wed_reset(dev, MTK_WED_RESET_WED);
-@@ -677,7 +691,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+@@ -670,7 +684,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
  {
  	u32 mask, set;
  
diff --git a/target/linux/generic/backport-5.15/729-13-v6.2-net-ethernet-mtk_wed-add-mtk_wed_rx_reset-routine.patch b/target/linux/generic/backport-5.15/729-13-v6.2-net-ethernet-mtk_wed-add-mtk_wed_rx_reset-routine.patch
index 2205fea513d..a0fc9da99e7 100644
--- a/target/linux/generic/backport-5.15/729-13-v6.2-net-ethernet-mtk_wed-add-mtk_wed_rx_reset-routine.patch
+++ b/target/linux/generic/backport-5.15/729-13-v6.2-net-ethernet-mtk_wed-add-mtk_wed_rx_reset-routine.patch
@@ -13,7 +13,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -951,42 +951,130 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+@@ -944,42 +944,130 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
  }
  
  static u32
@@ -170,7 +170,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static void
-@@ -1004,19 +1092,23 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -997,19 +1085,23 @@ mtk_wed_reset_dma(struct mtk_wed_device
  				   true);
  	}
  
@@ -201,7 +201,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (busy) {
  		mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
-@@ -1033,6 +1125,9 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1026,6 +1118,9 @@ mtk_wed_reset_dma(struct mtk_wed_device
  			MTK_WED_WDMA_GLO_CFG_RST_INIT_COMPLETE);
  	}
  
@@ -211,7 +211,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	for (i = 0; i < 100; i++) {
  		val = wed_r32(dev, MTK_WED_TX_BM_INTF);
  		if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
-@@ -1040,8 +1135,19 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1033,8 +1128,19 @@ mtk_wed_reset_dma(struct mtk_wed_device
  	}
  
  	mtk_wed_reset(dev, MTK_WED_RESET_TX_FREE_AGENT);
@@ -231,7 +231,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	if (busy) {
  		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
  		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
-@@ -1052,6 +1158,17 @@ mtk_wed_reset_dma(struct mtk_wed_device
+@@ -1045,6 +1151,17 @@ mtk_wed_reset_dma(struct mtk_wed_device
  			MTK_WED_WPDMA_RESET_IDX_RX);
  		wed_w32(dev, MTK_WED_WPDMA_RESET_IDX, 0);
  	}
@@ -249,7 +249,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  }
  
  static int
-@@ -1274,6 +1391,9 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1267,6 +1384,9 @@ mtk_wed_start(struct mtk_wed_device *dev
  {
  	int i;
  
@@ -259,7 +259,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
  		if (!dev->rx_wdma[i].desc)
  			mtk_wed_wdma_rx_ring_setup(dev, i, 16);
-@@ -1362,10 +1482,6 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1355,10 +1475,6 @@ mtk_wed_attach(struct mtk_wed_device *de
  		goto out;
  
  	if (mtk_wed_get_rx_capa(dev)) {
diff --git a/target/linux/generic/backport-5.15/729-14-v6.2-net-ethernet-mtk_wed-add-reset-to-tx_ring_setup-call.patch b/target/linux/generic/backport-5.15/729-14-v6.2-net-ethernet-mtk_wed-add-reset-to-tx_ring_setup-call.patch
index 602483bcb8d..4404971cc74 100644
--- a/target/linux/generic/backport-5.15/729-14-v6.2-net-ethernet-mtk_wed-add-reset-to-tx_ring_setup-call.patch
+++ b/target/linux/generic/backport-5.15/729-14-v6.2-net-ethernet-mtk_wed-add-reset-to-tx_ring_setup-call.patch
@@ -14,7 +14,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1188,7 +1188,8 @@ mtk_wed_ring_alloc(struct mtk_wed_device
+@@ -1181,7 +1181,8 @@ mtk_wed_ring_alloc(struct mtk_wed_device
  }
  
  static int
@@ -24,7 +24,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
  	struct mtk_wed_ring *wdma;
-@@ -1197,8 +1198,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -1190,8 +1191,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
  		return -EINVAL;
  
  	wdma = &dev->rx_wdma[idx];
@@ -35,7 +35,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  		return -ENOMEM;
  
  	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1396,7 +1397,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+@@ -1389,7 +1390,7 @@ mtk_wed_start(struct mtk_wed_device *dev
  
  	for (i = 0; i < ARRAY_SIZE(dev->rx_wdma); i++)
  		if (!dev->rx_wdma[i].desc)
@@ -44,7 +44,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	mtk_wed_hw_init(dev);
  	mtk_wed_configure_irq(dev, irq_mask);
-@@ -1505,7 +1506,8 @@ unlock:
+@@ -1498,7 +1499,8 @@ unlock:
  }
  
  static int
@@ -54,7 +54,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	struct mtk_wed_ring *ring = &dev->tx_ring[idx];
  
-@@ -1524,11 +1526,12 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+@@ -1517,11 +1519,12 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
  	if (WARN_ON(idx >= ARRAY_SIZE(dev->tx_ring)))
  		return -EINVAL;
  
diff --git a/target/linux/generic/backport-5.15/729-23-v6.3-net-ethernet-mtk_wed-add-reset-to-rx_ring_setup-call.patch b/target/linux/generic/backport-5.15/729-23-v6.3-net-ethernet-mtk_wed-add-reset-to-rx_ring_setup-call.patch
index cf81acf4919..c63628da99d 100644
--- a/target/linux/generic/backport-5.15/729-23-v6.3-net-ethernet-mtk_wed-add-reset-to-rx_ring_setup-call.patch
+++ b/target/linux/generic/backport-5.15/729-23-v6.3-net-ethernet-mtk_wed-add-reset-to-rx_ring_setup-call.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1259,7 +1259,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+@@ -1252,7 +1252,8 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
  }
  
  static int
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
  	struct mtk_wed_ring *wdma;
-@@ -1268,8 +1269,8 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1261,8 +1262,8 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
  		return -EINVAL;
  
  	wdma = &dev->tx_wdma[idx];
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		return -ENOMEM;
  
  	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
-@@ -1279,6 +1280,9 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+@@ -1272,6 +1273,9 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
  	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_CPU_IDX, 0);
  	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_DMA_IDX, 0);
  
@@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!idx)  {
  		wed_w32(dev, MTK_WED_WDMA_RING_TX + MTK_WED_RING_OFS_BASE,
  			wdma->desc_phys);
-@@ -1618,18 +1622,20 @@ mtk_wed_txfree_ring_setup(struct mtk_wed
+@@ -1611,18 +1615,20 @@ mtk_wed_txfree_ring_setup(struct mtk_wed
  }
  
  static int
diff --git a/target/linux/generic/backport-5.15/730-15-v6.3-net-ethernet-mtk_wed-No-need-to-clear-memory-after-a.patch b/target/linux/generic/backport-5.15/730-15-v6.3-net-ethernet-mtk_wed-No-need-to-clear-memory-after-a.patch
index 74a77ddaca2..a3bb1c5db77 100644
--- a/target/linux/generic/backport-5.15/730-15-v6.3-net-ethernet-mtk_wed-No-need-to-clear-memory-after-a.patch
+++ b/target/linux/generic/backport-5.15/730-15-v6.3-net-ethernet-mtk_wed-No-need-to-clear-memory-after-a.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -786,7 +786,6 @@ mtk_wed_rro_ring_alloc(struct mtk_wed_de
+@@ -779,7 +779,6 @@ mtk_wed_rro_ring_alloc(struct mtk_wed_de
  
  	ring->desc_size = sizeof(*ring->desc);
  	ring->size = size;
diff --git a/target/linux/generic/backport-5.15/730-17-v6.3-net-ethernet-mtk_wed-fix-possible-deadlock-if-mtk_we.patch b/target/linux/generic/backport-5.15/730-17-v6.3-net-ethernet-mtk_wed-fix-possible-deadlock-if-mtk_we.patch
index d1c5fb6656d..0afe7106e54 100644
--- a/target/linux/generic/backport-5.15/730-17-v6.3-net-ethernet-mtk_wed-fix-possible-deadlock-if-mtk_we.patch
+++ b/target/linux/generic/backport-5.15/730-17-v6.3-net-ethernet-mtk_wed-fix-possible-deadlock-if-mtk_we.patch
@@ -43,7 +43,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	mutex_unlock(&hw_lock);
  }
  
-@@ -1545,8 +1550,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+@@ -1538,8 +1543,10 @@ mtk_wed_attach(struct mtk_wed_device *de
  		ret = mtk_wed_wo_init(hw);
  	}
  out:
diff --git a/target/linux/generic/backport-5.15/731-v6.1-0001-net-phy-Introduce-QUSGMII-PHY-mode.patch b/target/linux/generic/backport-5.15/731-v6.1-0001-net-phy-Introduce-QUSGMII-PHY-mode.patch
new file mode 100644
index 00000000000..40b14fc36ae
--- /dev/null
+++ b/target/linux/generic/backport-5.15/731-v6.1-0001-net-phy-Introduce-QUSGMII-PHY-mode.patch
@@ -0,0 +1,99 @@
+From 5e61fe157a27afc7c0d4f7bcbceefdca536c015f Mon Sep 17 00:00:00 2001
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Date: Wed, 17 Aug 2022 14:32:52 +0200
+Subject: [PATCH] net: phy: Introduce QUSGMII PHY mode
+
+The QUSGMII mode is a derivative of Cisco's USXGMII standard. This
+standard is pretty similar to SGMII, but allows for faster speeds, and
+has the build-in bits for Quad and Octa variants (like QSGMII).
+
+The main difference with SGMII/QSGMII is that USXGMII/QUSGMII re-uses
+the preamble to carry various information, named 'Extensions'.
+
+As of today, the USXGMII standard only mentions the "PCH" extension,
+which is used to convey timestamps, allowing in-band signaling of PTP
+timestamps without having to modify the frame itself.
+
+This commit adds support for that mode. When no extension is in use, it
+behaves exactly like QSGMII, although it's not compatible with QSGMII.
+
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ Documentation/networking/phy.rst | 9 +++++++++
+ drivers/net/phy/phylink.c        | 3 +++
+ include/linux/phy.h              | 4 ++++
+ 3 files changed, 16 insertions(+)
+
+--- a/Documentation/networking/phy.rst
++++ b/Documentation/networking/phy.rst
+@@ -303,6 +303,15 @@ Some of the interface modes are describe
+     rate of 125Mpbs using a 4B/5B encoding scheme, resulting in an underlying
+     data rate of 100Mpbs.
+ 
++``PHY_INTERFACE_MODE_QUSGMII``
++    This defines the Cisco the Quad USGMII mode, which is the Quad variant of
++    the USGMII (Universal SGMII) link. It's very similar to QSGMII, but uses
++    a Packet Control Header (PCH) instead of the 7 bytes preamble to carry not
++    only the port id, but also so-called "extensions". The only documented
++    extension so-far in the specification is the inclusion of timestamps, for
++    PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
++    same capabilities in terms of link speed and negociation.
++
+ Pause frames / flow control
+ ===========================
+ 
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -367,6 +367,7 @@ void phylink_get_linkmodes(unsigned long
+ 	case PHY_INTERFACE_MODE_RGMII_ID:
+ 	case PHY_INTERFACE_MODE_RGMII:
+ 	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_QUSGMII:
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_GMII:
+ 		caps |= MAC_1000HD | MAC_1000FD;
+@@ -630,6 +631,7 @@ static int phylink_parse_mode(struct phy
+ 		switch (pl->link_config.interface) {
+ 		case PHY_INTERFACE_MODE_SGMII:
+ 		case PHY_INTERFACE_MODE_QSGMII:
++		case PHY_INTERFACE_MODE_QUSGMII:
+ 			phylink_set(pl->supported, 10baseT_Half);
+ 			phylink_set(pl->supported, 10baseT_Full);
+ 			phylink_set(pl->supported, 100baseT_Half);
+@@ -2956,6 +2958,7 @@ void phylink_mii_c22_pcs_get_state(struc
+ 
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_QUSGMII:
+ 		phylink_decode_sgmii_word(state, lpa);
+ 		break;
+ 
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -115,6 +115,7 @@ extern const int phy_10gbit_features_arr
+  * @PHY_INTERFACE_MODE_25GBASER: 25G BaseR
+  * @PHY_INTERFACE_MODE_USXGMII:  Universal Serial 10GE MII
+  * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
++ * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
+  * @PHY_INTERFACE_MODE_MAX: Book keeping
+  *
+  * Describes the interface between the MAC and PHY.
+@@ -152,6 +153,7 @@ typedef enum {
+ 	PHY_INTERFACE_MODE_USXGMII,
+ 	/* 10GBASE-KR - with Clause 73 AN */
+ 	PHY_INTERFACE_MODE_10GKR,
++	PHY_INTERFACE_MODE_QUSGMII,
+ 	PHY_INTERFACE_MODE_MAX,
+ } phy_interface_t;
+ 
+@@ -267,6 +269,8 @@ static inline const char *phy_modes(phy_
+ 		return "10gbase-kr";
+ 	case PHY_INTERFACE_MODE_100BASEX:
+ 		return "100base-x";
++	case PHY_INTERFACE_MODE_QUSGMII:
++		return "qusgmii";
+ 	default:
+ 		return "unknown";
+ 	}
diff --git a/target/linux/generic/backport-5.15/731-v6.1-0002-net-phy-Add-helper-to-derive-the-number-of-ports-fro.patch b/target/linux/generic/backport-5.15/731-v6.1-0002-net-phy-Add-helper-to-derive-the-number-of-ports-fro.patch
new file mode 100644
index 00000000000..a9706af8937
--- /dev/null
+++ b/target/linux/generic/backport-5.15/731-v6.1-0002-net-phy-Add-helper-to-derive-the-number-of-ports-fro.patch
@@ -0,0 +1,93 @@
+From c04ade27cb7b952b6b9b9a0efa0a6129cc63f2ae Mon Sep 17 00:00:00 2001
+From: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Date: Wed, 17 Aug 2022 14:32:54 +0200
+Subject: [PATCH] net: phy: Add helper to derive the number of ports from a phy
+ mode
+
+Some phy modes such as QSGMII multiplex several MAC<->PHY links on one
+single physical interface. QSGMII used to be the only one supported, but
+other modes such as QUSGMII also carry multiple links.
+
+This helper allows getting the number of links that are multiplexed
+on a given interface.
+
+Signed-off-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy-core.c | 52 ++++++++++++++++++++++++++++++++++++++
+ include/linux/phy.h        |  2 ++
+ 2 files changed, 54 insertions(+)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -74,6 +74,58 @@ const char *phy_duplex_to_str(unsigned i
+ }
+ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
+ 
++/**
++ * phy_interface_num_ports - Return the number of links that can be carried by
++ *			     a given MAC-PHY physical link. Returns 0 if this is
++ *			     unknown, the number of links else.
++ *
++ * @interface: The interface mode we want to get the number of ports
++ */
++int phy_interface_num_ports(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_NA:
++		return 0;
++	case PHY_INTERFACE_MODE_INTERNAL:
++	case PHY_INTERFACE_MODE_MII:
++	case PHY_INTERFACE_MODE_GMII:
++	case PHY_INTERFACE_MODE_TBI:
++	case PHY_INTERFACE_MODE_REVMII:
++	case PHY_INTERFACE_MODE_RMII:
++	case PHY_INTERFACE_MODE_REVRMII:
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++	case PHY_INTERFACE_MODE_RTBI:
++	case PHY_INTERFACE_MODE_XGMII:
++	case PHY_INTERFACE_MODE_XLGMII:
++	case PHY_INTERFACE_MODE_MOCA:
++	case PHY_INTERFACE_MODE_TRGMII:
++	case PHY_INTERFACE_MODE_USXGMII:
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_SMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++	case PHY_INTERFACE_MODE_5GBASER:
++	case PHY_INTERFACE_MODE_10GBASER:
++	case PHY_INTERFACE_MODE_25GBASER:
++	case PHY_INTERFACE_MODE_10GKR:
++	case PHY_INTERFACE_MODE_100BASEX:
++	case PHY_INTERFACE_MODE_RXAUI:
++	case PHY_INTERFACE_MODE_XAUI:
++		return 1;
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_QUSGMII:
++		return 4;
++	case PHY_INTERFACE_MODE_MAX:
++		WARN_ONCE(1, "PHY_INTERFACE_MODE_MAX isn't a valid interface mode");
++		return 0;
++	}
++	return 0;
++}
++EXPORT_SYMBOL_GPL(phy_interface_num_ports);
++
+ /* A mapping of all SUPPORTED settings to speed/duplex.  This table
+  * must be grouped by speed and sorted in descending match priority
+  * - iow, descending speed.
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -964,6 +964,8 @@ struct phy_fixup {
+ const char *phy_speed_to_str(int speed);
+ const char *phy_duplex_to_str(unsigned int duplex);
+ 
++int phy_interface_num_ports(phy_interface_t interface);
++
+ /* A structure for mapping a particular speed and duplex
+  * combination to a particular SUPPORTED and ADVERTISED value
+  */
diff --git a/target/linux/generic/backport-5.15/731-v6.1-0003-net-phy-Add-1000BASE-KX-interface-mode.patch b/target/linux/generic/backport-5.15/731-v6.1-0003-net-phy-Add-1000BASE-KX-interface-mode.patch
new file mode 100644
index 00000000000..70669dde3a3
--- /dev/null
+++ b/target/linux/generic/backport-5.15/731-v6.1-0003-net-phy-Add-1000BASE-KX-interface-mode.patch
@@ -0,0 +1,96 @@
+From 05ad5d4581c3c1cc724fe50d4652833fb9f3037b Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Fri, 2 Sep 2022 18:02:39 -0400
+Subject: [PATCH] net: phy: Add 1000BASE-KX interface mode
+
+Add 1000BASE-KX interface mode. This 1G backplane ethernet as described in
+clause 70. Clause 73 autonegotiation is mandatory, and only full duplex
+operation is supported.
+
+Although at the PMA level this interface mode is identical to
+1000BASE-X, it uses a different form of in-band autonegation. This
+justifies a separate interface mode, since the interface mode (along
+with the MLO_AN_* autonegotiation mode) sets the type of autonegotiation
+which will be used on a link. This results in more than just electrical
+differences between the link modes.
+
+With regard to 1000BASE-X, 1000BASE-KX holds a similar position to
+SGMII: same signaling, but different autonegotiation. PCS drivers
+(which typically handle in-band autonegotiation) may only support
+1000BASE-X, and not 1000BASE-KX. Similarly, the phy mode is used to
+configure serdes phys with phy_set_mode_ext. Due to the different
+electrical standards (SFI or XFI vs Clause 70), they will likely want to
+use different configuration. Adding a phy interface mode for
+1000BASE-KX helps simplify configuration in these areas.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ Documentation/networking/phy.rst | 6 ++++++
+ drivers/net/phy/phy-core.c       | 1 +
+ drivers/net/phy/phylink.c        | 1 +
+ include/linux/phy.h              | 4 ++++
+ 4 files changed, 12 insertions(+)
+
+--- a/Documentation/networking/phy.rst
++++ b/Documentation/networking/phy.rst
+@@ -312,6 +312,12 @@ Some of the interface modes are describe
+     PTP-enabled PHYs. This mode isn't compatible with QSGMII, but offers the
+     same capabilities in terms of link speed and negociation.
+ 
++``PHY_INTERFACE_MODE_1000BASEKX``
++    This is 1000BASE-X as defined by IEEE 802.3 Clause 36 with Clause 73
++    autonegotiation. Generally, it will be used with a Clause 70 PMD. To
++    contrast with the 1000BASE-X phy mode used for Clause 38 and 39 PMDs, this
++    interface mode has different autonegotiation and only supports full duplex.
++
+ Pause frames / flow control
+ ===========================
+ 
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -114,6 +114,7 @@ int phy_interface_num_ports(phy_interfac
+ 	case PHY_INTERFACE_MODE_100BASEX:
+ 	case PHY_INTERFACE_MODE_RXAUI:
+ 	case PHY_INTERFACE_MODE_XAUI:
++	case PHY_INTERFACE_MODE_1000BASEKX:
+ 		return 1;
+ 	case PHY_INTERFACE_MODE_QSGMII:
+ 	case PHY_INTERFACE_MODE_QUSGMII:
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -390,6 +390,7 @@ void phylink_get_linkmodes(unsigned long
+ 	case PHY_INTERFACE_MODE_1000BASEX:
+ 		caps |= MAC_1000HD;
+ 		fallthrough;
++	case PHY_INTERFACE_MODE_1000BASEKX:
+ 	case PHY_INTERFACE_MODE_TRGMII:
+ 		caps |= MAC_1000FD;
+ 		break;
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -116,6 +116,7 @@ extern const int phy_10gbit_features_arr
+  * @PHY_INTERFACE_MODE_USXGMII:  Universal Serial 10GE MII
+  * @PHY_INTERFACE_MODE_10GKR: 10GBASE-KR - with Clause 73 AN
+  * @PHY_INTERFACE_MODE_QUSGMII: Quad Universal SGMII
++ * @PHY_INTERFACE_MODE_1000BASEKX: 1000Base-KX - with Clause 73 AN
+  * @PHY_INTERFACE_MODE_MAX: Book keeping
+  *
+  * Describes the interface between the MAC and PHY.
+@@ -154,6 +155,7 @@ typedef enum {
+ 	/* 10GBASE-KR - with Clause 73 AN */
+ 	PHY_INTERFACE_MODE_10GKR,
+ 	PHY_INTERFACE_MODE_QUSGMII,
++	PHY_INTERFACE_MODE_1000BASEKX,
+ 	PHY_INTERFACE_MODE_MAX,
+ } phy_interface_t;
+ 
+@@ -251,6 +253,8 @@ static inline const char *phy_modes(phy_
+ 		return "trgmii";
+ 	case PHY_INTERFACE_MODE_1000BASEX:
+ 		return "1000base-x";
++	case PHY_INTERFACE_MODE_1000BASEKX:
++		return "1000base-kx";
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+ 		return "2500base-x";
+ 	case PHY_INTERFACE_MODE_5GBASER:
diff --git a/target/linux/generic/backport-5.15/731-v6.1-0004-net-phy-Add-support-for-rate-matching.patch b/target/linux/generic/backport-5.15/731-v6.1-0004-net-phy-Add-support-for-rate-matching.patch
new file mode 100644
index 00000000000..fc02d7a4eab
--- /dev/null
+++ b/target/linux/generic/backport-5.15/731-v6.1-0004-net-phy-Add-support-for-rate-matching.patch
@@ -0,0 +1,294 @@
+From 0c3e10cb44232833a50cb8e3e784c432906a60c1 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Tue, 20 Sep 2022 18:12:31 -0400
+Subject: [PATCH] net: phy: Add support for rate matching
+
+This adds support for rate matching (also known as rate adaptation) to
+the phy subsystem. The general idea is that the phy interface runs at
+one speed, and the MAC throttles the rate at which it sends packets to
+the link speed. There's a good overview of several techniques for
+achieving this at [1]. This patch adds support for three: pause-frame
+based (such as in Aquantia phys), CRS-based (such as in 10PASS-TS and
+2BASE-TL), and open-loop-based (such as in 10GBASE-W).
+
+This patch makes a few assumptions and a few non assumptions about the
+types of rate matching available. First, it assumes that different phys
+may use different forms of rate matching. Second, it assumes that phys
+can use rate matching for any of their supported link speeds (e.g. if a
+phy supports 10BASE-T and XGMII, then it can adapt XGMII to 10BASE-T).
+Third, it does not assume that all interface modes will use the same
+form of rate matching. Fourth, it does not assume that all phy devices
+will support rate matching (even if some do). Relaxing or strengthening
+these (non-)assumptions could result in a different API. For example, if
+all interface modes were assumed to use the same form of rate matching,
+then a bitmask of interface modes supportting rate matching would
+suffice.
+
+For some better visibility into the process, the current rate matching
+mode is exposed as part of the ethtool ksettings. For the moment, only
+read access is supported. I'm not sure what userspace might want to
+configure yet (disable it altogether, disable just one mode, specify the
+mode to use, etc.). For the moment, since only pause-based rate
+adaptation support is added in the next few commits, rate matching can
+be disabled altogether by adjusting the advertisement.
+
+802.3 calls this feature "rate adaptation" in clause 49 (10GBASE-R) and
+"rate matching" in clause 61 (10PASS-TL and 2BASE-TS). Aquantia also calls
+this feature "rate adaptation". I chose "rate matching" because it is
+shorter, and because Russell doesn't think "adaptation" is correct in this
+context.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ Documentation/networking/ethtool-netlink.rst |  2 ++
+ drivers/net/phy/phy-core.c                   | 21 +++++++++++++++
+ drivers/net/phy/phy.c                        | 28 ++++++++++++++++++++
+ include/linux/phy.h                          | 22 ++++++++++++++-
+ include/uapi/linux/ethtool.h                 | 18 +++++++++++--
+ include/uapi/linux/ethtool_netlink.h         |  1 +
+ net/ethtool/ioctl.c                          |  1 +
+ net/ethtool/linkmodes.c                      |  5 ++++
+ 8 files changed, 95 insertions(+), 3 deletions(-)
+
+--- a/Documentation/networking/ethtool-netlink.rst
++++ b/Documentation/networking/ethtool-netlink.rst
+@@ -418,6 +418,7 @@ Kernel response contents:
+   ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
+   ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
+   ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE``  u8      Master/slave port state
++  ``ETHTOOL_A_LINKMODES_RATE_MATCHING``       u8      PHY rate matching
+   ==========================================  ======  ==========================
+ 
+ For ``ETHTOOL_A_LINKMODES_OURS``, value represents advertised modes and mask
+@@ -441,6 +442,7 @@ Request contents:
+   ``ETHTOOL_A_LINKMODES_SPEED``               u32     link speed (Mb/s)
+   ``ETHTOOL_A_LINKMODES_DUPLEX``              u8      duplex mode
+   ``ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG``    u8      Master/slave port mode
++  ``ETHTOOL_A_LINKMODES_RATE_MATCHING``       u8      PHY rate matching
+   ``ETHTOOL_A_LINKMODES_LANES``               u32     lanes
+   ==========================================  ======  ==========================
+ 
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -75,6 +75,27 @@ const char *phy_duplex_to_str(unsigned i
+ EXPORT_SYMBOL_GPL(phy_duplex_to_str);
+ 
+ /**
++ * phy_rate_matching_to_str - Return a string describing the rate matching
++ *
++ * @rate_matching: Type of rate matching to describe
++ */
++const char *phy_rate_matching_to_str(int rate_matching)
++{
++	switch (rate_matching) {
++	case RATE_MATCH_NONE:
++		return "none";
++	case RATE_MATCH_PAUSE:
++		return "pause";
++	case RATE_MATCH_CRS:
++		return "crs";
++	case RATE_MATCH_OPEN_LOOP:
++		return "open-loop";
++	}
++	return "Unsupported (update phy-core.c)";
++}
++EXPORT_SYMBOL_GPL(phy_rate_matching_to_str);
++
++/**
+  * phy_interface_num_ports - Return the number of links that can be carried by
+  *			     a given MAC-PHY physical link. Returns 0 if this is
+  *			     unknown, the number of links else.
+--- a/drivers/net/phy/phy.c
++++ b/drivers/net/phy/phy.c
+@@ -127,6 +127,33 @@ void phy_print_status(struct phy_device
+ EXPORT_SYMBOL(phy_print_status);
+ 
+ /**
++ * phy_get_rate_matching - determine if rate matching is supported
++ * @phydev: The phy device to return rate matching for
++ * @iface: The interface mode to use
++ *
++ * This determines the type of rate matching (if any) that @phy supports
++ * using @iface. @iface may be %PHY_INTERFACE_MODE_NA to determine if any
++ * interface supports rate matching.
++ *
++ * Return: The type of rate matching @phy supports for @iface, or
++ *         %RATE_MATCH_NONE.
++ */
++int phy_get_rate_matching(struct phy_device *phydev,
++			  phy_interface_t iface)
++{
++	int ret = RATE_MATCH_NONE;
++
++	if (phydev->drv->get_rate_matching) {
++		mutex_lock(&phydev->lock);
++		ret = phydev->drv->get_rate_matching(phydev, iface);
++		mutex_unlock(&phydev->lock);
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(phy_get_rate_matching);
++
++/**
+  * phy_config_interrupt - configure the PHY device for the requested interrupts
+  * @phydev: the phy_device struct
+  * @interrupts: interrupt flags to configure for this @phydev
+@@ -268,6 +295,7 @@ void phy_ethtool_ksettings_get(struct ph
+ 	cmd->base.duplex = phydev->duplex;
+ 	cmd->base.master_slave_cfg = phydev->master_slave_get;
+ 	cmd->base.master_slave_state = phydev->master_slave_state;
++	cmd->base.rate_matching = phydev->rate_matching;
+ 	if (phydev->interface == PHY_INTERFACE_MODE_MOCA)
+ 		cmd->base.port = PORT_BNC;
+ 	else
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -280,7 +280,6 @@ static inline const char *phy_modes(phy_
+ 	}
+ }
+ 
+-
+ #define PHY_INIT_TIMEOUT	100000
+ #define PHY_FORCE_TIMEOUT	10
+ 
+@@ -573,6 +572,7 @@ struct macsec_ops;
+  * @lp_advertising: Current link partner advertised linkmodes
+  * @eee_broken_modes: Energy efficient ethernet modes which should be prohibited
+  * @autoneg: Flag autoneg being used
++ * @rate_matching: Current rate matching mode
+  * @link: Current link state
+  * @autoneg_complete: Flag auto negotiation of the link has completed
+  * @mdix: Current crossover
+@@ -639,6 +639,8 @@ struct phy_device {
+ 	unsigned irq_suspended:1;
+ 	unsigned irq_rerun:1;
+ 
++	int rate_matching;
++
+ 	enum phy_state state;
+ 
+ 	u32 dev_flags;
+@@ -801,6 +803,21 @@ struct phy_driver {
+ 	 */
+ 	int (*get_features)(struct phy_device *phydev);
+ 
++	/**
++	 * @get_rate_matching: Get the supported type of rate matching for a
++	 * particular phy interface. This is used by phy consumers to determine
++	 * whether to advertise lower-speed modes for that interface. It is
++	 * assumed that if a rate matching mode is supported on an interface,
++	 * then that interface's rate can be adapted to all slower link speeds
++	 * supported by the phy. If iface is %PHY_INTERFACE_MODE_NA, and the phy
++	 * supports any kind of rate matching for any interface, then it must
++	 * return that rate matching mode (preferring %RATE_MATCH_PAUSE to
++	 * %RATE_MATCH_CRS). If the interface is not supported, this should
++	 * return %RATE_MATCH_NONE.
++	 */
++	int (*get_rate_matching)(struct phy_device *phydev,
++				   phy_interface_t iface);
++
+ 	/* PHY Power Management */
+ 	/** @suspend: Suspend the hardware, saving state if needed */
+ 	int (*suspend)(struct phy_device *phydev);
+@@ -967,6 +984,7 @@ struct phy_fixup {
+ 
+ const char *phy_speed_to_str(int speed);
+ const char *phy_duplex_to_str(unsigned int duplex);
++const char *phy_rate_matching_to_str(int rate_matching);
+ 
+ int phy_interface_num_ports(phy_interface_t interface);
+ 
+@@ -1675,6 +1693,8 @@ int phy_disable_interrupts(struct phy_de
+ void phy_request_interrupt(struct phy_device *phydev);
+ void phy_free_interrupt(struct phy_device *phydev);
+ void phy_print_status(struct phy_device *phydev);
++int phy_get_rate_matching(struct phy_device *phydev,
++			    phy_interface_t iface);
+ int phy_set_max_speed(struct phy_device *phydev, u32 max_speed);
+ void phy_remove_link_mode(struct phy_device *phydev, u32 link_mode);
+ void phy_advertise_supported(struct phy_device *phydev);
+--- a/include/uapi/linux/ethtool.h
++++ b/include/uapi/linux/ethtool.h
+@@ -1809,6 +1809,20 @@ static inline int ethtool_validate_duple
+ #define MASTER_SLAVE_STATE_SLAVE		3
+ #define MASTER_SLAVE_STATE_ERR			4
+ 
++/* These are used to throttle the rate of data on the phy interface when the
++ * native speed of the interface is higher than the link speed. These should
++ * not be used for phy interfaces which natively support multiple speeds (e.g.
++ * MII or SGMII).
++ */
++/* No rate matching performed. */
++#define RATE_MATCH_NONE		0
++/* The phy sends pause frames to throttle the MAC. */
++#define RATE_MATCH_PAUSE	1
++/* The phy asserts CRS to prevent the MAC from transmitting. */
++#define RATE_MATCH_CRS		2
++/* The MAC is programmed with a sufficiently-large IPG. */
++#define RATE_MATCH_OPEN_LOOP	3
++
+ /* Which connector port. */
+ #define PORT_TP			0x00
+ #define PORT_AUI		0x01
+@@ -2002,8 +2016,8 @@ enum ethtool_reset_flags {
+  *	reported consistently by PHYLIB.  Read-only.
+  * @master_slave_cfg: Master/slave port mode.
+  * @master_slave_state: Master/slave port state.
++ * @rate_matching: Rate adaptation performed by the PHY
+  * @reserved: Reserved for future use; see the note on reserved space.
+- * @reserved1: Reserved for future use; see the note on reserved space.
+  * @link_mode_masks: Variable length bitmaps.
+  *
+  * If autonegotiation is disabled, the speed and @duplex represent the
+@@ -2054,7 +2068,7 @@ struct ethtool_link_settings {
+ 	__u8	transceiver;
+ 	__u8	master_slave_cfg;
+ 	__u8	master_slave_state;
+-	__u8	reserved1[1];
++	__u8	rate_matching;
+ 	__u32	reserved[7];
+ 	__u32	link_mode_masks[0];
+ 	/* layout of link_mode_masks fields:
+--- a/include/uapi/linux/ethtool_netlink.h
++++ b/include/uapi/linux/ethtool_netlink.h
+@@ -238,6 +238,7 @@ enum {
+ 	ETHTOOL_A_LINKMODES_MASTER_SLAVE_CFG,	/* u8 */
+ 	ETHTOOL_A_LINKMODES_MASTER_SLAVE_STATE,	/* u8 */
+ 	ETHTOOL_A_LINKMODES_LANES,		/* u32 */
++	ETHTOOL_A_LINKMODES_RATE_MATCHING,	/* u8 */
+ 
+ 	/* add new constants above here */
+ 	__ETHTOOL_A_LINKMODES_CNT,
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -559,6 +559,7 @@ static int ethtool_get_link_ksettings(st
+ 		= __ETHTOOL_LINK_MODE_MASK_NU32;
+ 	link_ksettings.base.master_slave_cfg = MASTER_SLAVE_CFG_UNSUPPORTED;
+ 	link_ksettings.base.master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++	link_ksettings.base.rate_matching = RATE_MATCH_NONE;
+ 
+ 	return store_link_ksettings_for_user(useraddr, &link_ksettings);
+ }
+--- a/net/ethtool/linkmodes.c
++++ b/net/ethtool/linkmodes.c
+@@ -70,6 +70,7 @@ static int linkmodes_reply_size(const st
+ 		+ nla_total_size(sizeof(u32)) /* LINKMODES_SPEED */
+ 		+ nla_total_size(sizeof(u32)) /* LINKMODES_LANES */
+ 		+ nla_total_size(sizeof(u8)) /* LINKMODES_DUPLEX */
++		+ nla_total_size(sizeof(u8)) /* LINKMODES_RATE_MATCHING */
+ 		+ 0;
+ 	ret = ethnl_bitset_size(ksettings->link_modes.advertising,
+ 				ksettings->link_modes.supported,
+@@ -143,6 +144,10 @@ static int linkmodes_fill_reply(struct s
+ 		       lsettings->master_slave_state))
+ 		return -EMSGSIZE;
+ 
++	if (nla_put_u8(skb, ETHTOOL_A_LINKMODES_RATE_MATCHING,
++		       lsettings->rate_matching))
++		return -EMSGSIZE;
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/generic/backport-5.15/735-v6.0-0001-net-phy-Add-support-for-AQR113C-EPHY.patch b/target/linux/generic/backport-5.15/735-v6.0-0001-net-phy-Add-support-for-AQR113C-EPHY.patch
new file mode 100644
index 00000000000..6090a40eaee
--- /dev/null
+++ b/target/linux/generic/backport-5.15/735-v6.0-0001-net-phy-Add-support-for-AQR113C-EPHY.patch
@@ -0,0 +1,58 @@
+From 12cf1b89a66828719b2135891b65bd5d03eedea9 Mon Sep 17 00:00:00 2001
+From: Bhadram Varka <vbhadram@nvidia.com>
+Date: Tue, 21 Jun 2022 09:10:27 +0530
+Subject: [PATCH] net: phy: Add support for AQR113C EPHY
+
+Add support multi-gigabit and single-port Ethernet
+PHY transceiver (AQR113C).
+
+Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
+Link: https://lore.kernel.org/r/20220621034027.56508-1-vbhadram@nvidia.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia_main.c | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -22,6 +22,7 @@
+ #define PHY_ID_AQR107	0x03a1b4e0
+ #define PHY_ID_AQCS109	0x03a1b5c2
+ #define PHY_ID_AQR405	0x03a1b4b0
++#define PHY_ID_AQR113C	0x31c31c12
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+@@ -744,6 +745,24 @@ static struct phy_driver aqr_driver[] =
+ 	.handle_interrupt = aqr_handle_interrupt,
+ 	.read_status	= aqr_read_status,
+ },
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
++	.name           = "Aquantia AQR113C",
++	.probe          = aqr107_probe,
++	.config_init    = aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr    = aqr_config_intr,
++	.handle_interrupt       = aqr_handle_interrupt,
++	.read_status    = aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend        = aqr107_suspend,
++	.resume         = aqr107_resume,
++	.get_sset_count = aqr107_get_sset_count,
++	.get_strings    = aqr107_get_strings,
++	.get_stats      = aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
+ };
+ 
+ module_phy_driver(aqr_driver);
+@@ -756,6 +775,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ }
+ };
+ 
diff --git a/target/linux/generic/backport-5.15/736-v6.1-0001-net-phy-aquantia-Add-some-additional-phy-interfaces.patch b/target/linux/generic/backport-5.15/736-v6.1-0001-net-phy-aquantia-Add-some-additional-phy-interfaces.patch
new file mode 100644
index 00000000000..ec8485e0a74
--- /dev/null
+++ b/target/linux/generic/backport-5.15/736-v6.1-0001-net-phy-aquantia-Add-some-additional-phy-interfaces.patch
@@ -0,0 +1,71 @@
+From 7de26bf144f6a72858ab60afb2bd2b43265ee0ad Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Tue, 20 Sep 2022 18:12:34 -0400
+Subject: [PATCH] net: phy: aquantia: Add some additional phy interfaces
+
+These are documented in the AQR115 register reference. I haven't tested
+them, but perhaps they'll be useful to someone.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia_main.c | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -27,9 +27,12 @@
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR	0
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX	1
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI	2
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII	3
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI	4
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII	6
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI	7
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII	10
+ 
+ #define MDIO_AN_VEND_PROV			0xc400
+@@ -401,15 +404,24 @@ static int aqr107_read_status(struct phy
+ 	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
+ 		phydev->interface = PHY_INTERFACE_MODE_10GKR;
+ 		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
++		phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
++		break;
+ 	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
+ 		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+ 		break;
+ 	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
+ 		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
+ 		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
++		phydev->interface = PHY_INTERFACE_MODE_XAUI;
++		break;
+ 	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
+ 		phydev->interface = PHY_INTERFACE_MODE_SGMII;
+ 		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
++		phydev->interface = PHY_INTERFACE_MODE_RXAUI;
++		break;
+ 	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
+ 		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+ 		break;
+@@ -522,11 +534,14 @@ static int aqr107_config_init(struct phy
+ 
+ 	/* Check that the PHY interface type is compatible */
+ 	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++	    phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
+ 	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+ 	    phydev->interface != PHY_INTERFACE_MODE_XGMII &&
+ 	    phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
+ 	    phydev->interface != PHY_INTERFACE_MODE_10GKR &&
+-	    phydev->interface != PHY_INTERFACE_MODE_10GBASER)
++	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
++	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
++	    phydev->interface != PHY_INTERFACE_MODE_RXAUI)
+ 		return -ENODEV;
+ 
+ 	WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
diff --git a/target/linux/generic/backport-5.15/736-v6.1-0002-net-phy-aquantia-Add-support-for-rate-matching.patch b/target/linux/generic/backport-5.15/736-v6.1-0002-net-phy-aquantia-Add-support-for-rate-matching.patch
new file mode 100644
index 00000000000..d5d58762ce3
--- /dev/null
+++ b/target/linux/generic/backport-5.15/736-v6.1-0002-net-phy-aquantia-Add-support-for-rate-matching.patch
@@ -0,0 +1,148 @@
+From 3c42563b30417afc8855a3b4c1b38c2f36f78657 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Tue, 20 Sep 2022 18:12:35 -0400
+Subject: [PATCH] net: phy: aquantia: Add support for rate matching
+
+This adds support for rate matching for phys similar to the AQR107. We
+assume that all phys using aqr107_read_status support rate matching.
+However, it could be possible to determine support based on the firmware
+revision if there are phys discovered which do not support rate
+matching.  However, as rate matching is advertised in the datasheets for
+these phys, I suspect it is supported most boards.
+
+Despite the name, the "config" registers are updated with the current
+rate matching method (if any). Because they appear to be updated
+automatically, I don't know if these registers can be used to disable
+rate matching.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia_main.c | 51 ++++++++++++++++++++++++++++++---
+ 1 file changed, 47 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/aquantia_main.c
++++ b/drivers/net/phy/aquantia_main.c
+@@ -97,6 +97,19 @@
+ #define VEND1_GLOBAL_GEN_STAT2			0xc831
+ #define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)
+ 
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M			0x0310
++#define VEND1_GLOBAL_CFG_100M			0x031b
++#define VEND1_GLOBAL_CFG_1G			0x031c
++#define VEND1_GLOBAL_CFG_2_5G			0x031d
++#define VEND1_GLOBAL_CFG_5G			0x031e
++#define VEND1_GLOBAL_CFG_10G			0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
++
+ #define VEND1_GLOBAL_RSVD_STAT1			0xc885
+ #define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
+ #define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
+@@ -347,40 +360,57 @@ static int aqr_read_status(struct phy_de
+ 
+ static int aqr107_read_rate(struct phy_device *phydev)
+ {
++	u32 config_reg;
+ 	int val;
+ 
+ 	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
+ 	if (val < 0)
+ 		return val;
+ 
++	if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
++		phydev->duplex = DUPLEX_FULL;
++	else
++		phydev->duplex = DUPLEX_HALF;
++
+ 	switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
+ 	case MDIO_AN_TX_VEND_STATUS1_10BASET:
+ 		phydev->speed = SPEED_10;
++		config_reg = VEND1_GLOBAL_CFG_10M;
+ 		break;
+ 	case MDIO_AN_TX_VEND_STATUS1_100BASETX:
+ 		phydev->speed = SPEED_100;
++		config_reg = VEND1_GLOBAL_CFG_100M;
+ 		break;
+ 	case MDIO_AN_TX_VEND_STATUS1_1000BASET:
+ 		phydev->speed = SPEED_1000;
++		config_reg = VEND1_GLOBAL_CFG_1G;
+ 		break;
+ 	case MDIO_AN_TX_VEND_STATUS1_2500BASET:
+ 		phydev->speed = SPEED_2500;
++		config_reg = VEND1_GLOBAL_CFG_2_5G;
+ 		break;
+ 	case MDIO_AN_TX_VEND_STATUS1_5000BASET:
+ 		phydev->speed = SPEED_5000;
++		config_reg = VEND1_GLOBAL_CFG_5G;
+ 		break;
+ 	case MDIO_AN_TX_VEND_STATUS1_10GBASET:
+ 		phydev->speed = SPEED_10000;
++		config_reg = VEND1_GLOBAL_CFG_10G;
+ 		break;
+ 	default:
+ 		phydev->speed = SPEED_UNKNOWN;
+-		break;
++		return 0;
+ 	}
+ 
+-	if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
+-		phydev->duplex = DUPLEX_FULL;
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
++	if (val < 0)
++		return val;
++
++	if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
++	    VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
++		phydev->rate_matching = RATE_MATCH_PAUSE;
+ 	else
+-		phydev->duplex = DUPLEX_HALF;
++		phydev->rate_matching = RATE_MATCH_NONE;
+ 
+ 	return 0;
+ }
+@@ -647,6 +677,16 @@ static int aqr107_wait_processor_intensi
+ 	return 0;
+ }
+ 
++static int aqr107_get_rate_matching(struct phy_device *phydev,
++				    phy_interface_t iface)
++{
++	if (iface == PHY_INTERFACE_MODE_10GBASER ||
++	    iface == PHY_INTERFACE_MODE_2500BASEX ||
++	    iface == PHY_INTERFACE_MODE_NA)
++		return RATE_MATCH_PAUSE;
++	return RATE_MATCH_NONE;
++}
++
+ static int aqr107_suspend(struct phy_device *phydev)
+ {
+ 	int err;
+@@ -720,6 +760,7 @@ static struct phy_driver aqr_driver[] =
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
+ 	.name		= "Aquantia AQR107",
+ 	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
+ 	.config_init	= aqr107_config_init,
+ 	.config_aneg    = aqr_config_aneg,
+ 	.config_intr	= aqr_config_intr,
+@@ -738,6 +779,7 @@ static struct phy_driver aqr_driver[] =
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+ 	.name		= "Aquantia AQCS109",
+ 	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
+ 	.config_init	= aqcs109_config_init,
+ 	.config_aneg    = aqr_config_aneg,
+ 	.config_intr	= aqr_config_intr,
+@@ -764,6 +806,7 @@ static struct phy_driver aqr_driver[] =
+ 	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+ 	.name           = "Aquantia AQR113C",
+ 	.probe          = aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
+ 	.config_init    = aqr107_config_init,
+ 	.config_aneg    = aqr_config_aneg,
+ 	.config_intr    = aqr_config_intr,
diff --git a/target/linux/generic/backport-5.15/737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch b/target/linux/generic/backport-5.15/737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch
new file mode 100644
index 00000000000..4bb786e7901
--- /dev/null
+++ b/target/linux/generic/backport-5.15/737-01-v6.7-net-phy-aquantia-move-to-separate-directory.patch
@@ -0,0 +1,2310 @@
+From d2213db3f49bce8e7a87c8de05b9a091f78f654e Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 14 Nov 2023 15:08:41 +0100
+Subject: [PATCH 1/3] net: phy: aquantia: move to separate directory
+
+Move aquantia PHY driver to separate driectory in preparation for
+firmware loading support to keep things tidy.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/Kconfig                         | 5 +----
+ drivers/net/phy/Makefile                        | 6 +-----
+ drivers/net/phy/aquantia/Kconfig                | 5 +++++
+ drivers/net/phy/aquantia/Makefile               | 6 ++++++
+ drivers/net/phy/{ => aquantia}/aquantia.h       | 0
+ drivers/net/phy/{ => aquantia}/aquantia_hwmon.c | 0
+ drivers/net/phy/{ => aquantia}/aquantia_main.c  | 0
+ 7 files changed, 13 insertions(+), 9 deletions(-)
+ create mode 100644 drivers/net/phy/aquantia/Kconfig
+ create mode 100644 drivers/net/phy/aquantia/Makefile
+ rename drivers/net/phy/{ => aquantia}/aquantia.h (100%)
+ rename drivers/net/phy/{ => aquantia}/aquantia_hwmon.c (100%)
+ rename drivers/net/phy/{ => aquantia}/aquantia_main.c (100%)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -83,10 +83,7 @@ config ADIN_PHY
+ 	  - ADIN1300 - Robust,Industrial, Low Latency 10/100/1000 Gigabit
+ 	    Ethernet PHY
+ 
+-config AQUANTIA_PHY
+-	tristate "Aquantia PHYs"
+-	help
+-	  Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
++source "drivers/net/phy/aquantia/Kconfig"
+ 
+ config AX88796B_PHY
+ 	tristate "Asix PHYs"
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,11 +32,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+-aquantia-objs			+= aquantia_main.o
+-ifdef CONFIG_HWMON
+-aquantia-objs			+= aquantia_hwmon.o
+-endif
+-obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o
++obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+ obj-$(CONFIG_BCM54140_PHY)	+= bcm54140.o
+--- /dev/null
++++ b/drivers/net/phy/aquantia/Kconfig
+@@ -0,0 +1,5 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config AQUANTIA_PHY
++	tristate "Aquantia PHYs"
++	help
++	  Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
+--- /dev/null
++++ b/drivers/net/phy/aquantia/Makefile
+@@ -0,0 +1,6 @@
++# SPDX-License-Identifier: GPL-2.0
++aquantia-objs			+= aquantia_main.o
++ifdef CONFIG_HWMON
++aquantia-objs			+= aquantia_hwmon.o
++endif
++obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia.o
+--- a/drivers/net/phy/aquantia.h
++++ /dev/null
+@@ -1,16 +0,0 @@
+-/* SPDX-License-Identifier: GPL-2.0 */
+-/* HWMON driver for Aquantia PHY
+- *
+- * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
+- * Author: Andrew Lunn <andrew@lunn.ch>
+- * Author: Heiner Kallweit <hkallweit1@gmail.com>
+- */
+-
+-#include <linux/device.h>
+-#include <linux/phy.h>
+-
+-#if IS_REACHABLE(CONFIG_HWMON)
+-int aqr_hwmon_probe(struct phy_device *phydev);
+-#else
+-static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
+-#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -0,0 +1,16 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++/* HWMON driver for Aquantia PHY
++ *
++ * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
++ * Author: Andrew Lunn <andrew@lunn.ch>
++ * Author: Heiner Kallweit <hkallweit1@gmail.com>
++ */
++
++#include <linux/device.h>
++#include <linux/phy.h>
++
++#if IS_REACHABLE(CONFIG_HWMON)
++int aqr_hwmon_probe(struct phy_device *phydev);
++#else
++static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
++#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
+@@ -0,0 +1,250 @@
++// SPDX-License-Identifier: GPL-2.0
++/* HWMON driver for Aquantia PHY
++ *
++ * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
++ * Author: Andrew Lunn <andrew@lunn.ch>
++ * Author: Heiner Kallweit <hkallweit1@gmail.com>
++ */
++
++#include <linux/phy.h>
++#include <linux/device.h>
++#include <linux/ctype.h>
++#include <linux/hwmon.h>
++
++#include "aquantia.h"
++
++/* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
++#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
++#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
++#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
++#define VEND1_THERMAL_STAT1			0xc820
++#define VEND1_THERMAL_STAT2			0xc821
++#define VEND1_THERMAL_STAT2_VALID		BIT(0)
++#define VEND1_GENERAL_STAT1			0xc830
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)
++
++#if IS_REACHABLE(CONFIG_HWMON)
++
++static umode_t aqr_hwmon_is_visible(const void *data,
++				    enum hwmon_sensor_types type,
++				    u32 attr, int channel)
++{
++	if (type != hwmon_temp)
++		return 0;
++
++	switch (attr) {
++	case hwmon_temp_input:
++	case hwmon_temp_min_alarm:
++	case hwmon_temp_max_alarm:
++	case hwmon_temp_lcrit_alarm:
++	case hwmon_temp_crit_alarm:
++		return 0444;
++	case hwmon_temp_min:
++	case hwmon_temp_max:
++	case hwmon_temp_lcrit:
++	case hwmon_temp_crit:
++		return 0644;
++	default:
++		return 0;
++	}
++}
++
++static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
++{
++	int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
++
++	if (temp < 0)
++		return temp;
++
++	/* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
++	*value = (s16)temp * 1000 / 256;
++
++	return 0;
++}
++
++static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
++{
++	int temp;
++
++	if (value >= 128000 || value < -128000)
++		return -ERANGE;
++
++	temp = value * 256 / 1000;
++
++	/* temp is in s16 range and we're interested in lower 16 bits only */
++	return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
++}
++
++static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
++{
++	int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
++
++	if (val < 0)
++		return val;
++
++	return !!(val & bit);
++}
++
++static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
++{
++	int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
++
++	if (val < 0)
++		return val;
++
++	*value = val;
++
++	return 0;
++}
++
++static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
++			  u32 attr, int channel, long *value)
++{
++	struct phy_device *phydev = dev_get_drvdata(dev);
++	int reg;
++
++	if (type != hwmon_temp)
++		return -EOPNOTSUPP;
++
++	switch (attr) {
++	case hwmon_temp_input:
++		reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
++					 VEND1_THERMAL_STAT2_VALID);
++		if (reg < 0)
++			return reg;
++		if (!reg)
++			return -EBUSY;
++
++		return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
++
++	case hwmon_temp_lcrit:
++		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
++				     value);
++	case hwmon_temp_min:
++		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
++				     value);
++	case hwmon_temp_max:
++		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
++				     value);
++	case hwmon_temp_crit:
++		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
++				     value);
++	case hwmon_temp_lcrit_alarm:
++		return aqr_hwmon_status1(phydev,
++					 VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
++					 value);
++	case hwmon_temp_min_alarm:
++		return aqr_hwmon_status1(phydev,
++					 VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
++					 value);
++	case hwmon_temp_max_alarm:
++		return aqr_hwmon_status1(phydev,
++					 VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
++					 value);
++	case hwmon_temp_crit_alarm:
++		return aqr_hwmon_status1(phydev,
++					 VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
++					 value);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
++			   u32 attr, int channel, long value)
++{
++	struct phy_device *phydev = dev_get_drvdata(dev);
++
++	if (type != hwmon_temp)
++		return -EOPNOTSUPP;
++
++	switch (attr) {
++	case hwmon_temp_lcrit:
++		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
++				     value);
++	case hwmon_temp_min:
++		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
++				     value);
++	case hwmon_temp_max:
++		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
++				     value);
++	case hwmon_temp_crit:
++		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
++				     value);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static const struct hwmon_ops aqr_hwmon_ops = {
++	.is_visible = aqr_hwmon_is_visible,
++	.read = aqr_hwmon_read,
++	.write = aqr_hwmon_write,
++};
++
++static u32 aqr_hwmon_chip_config[] = {
++	HWMON_C_REGISTER_TZ,
++	0,
++};
++
++static const struct hwmon_channel_info aqr_hwmon_chip = {
++	.type = hwmon_chip,
++	.config = aqr_hwmon_chip_config,
++};
++
++static u32 aqr_hwmon_temp_config[] = {
++	HWMON_T_INPUT |
++	HWMON_T_MAX | HWMON_T_MIN |
++	HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
++	HWMON_T_CRIT | HWMON_T_LCRIT |
++	HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
++	0,
++};
++
++static const struct hwmon_channel_info aqr_hwmon_temp = {
++	.type = hwmon_temp,
++	.config = aqr_hwmon_temp_config,
++};
++
++static const struct hwmon_channel_info *aqr_hwmon_info[] = {
++	&aqr_hwmon_chip,
++	&aqr_hwmon_temp,
++	NULL,
++};
++
++static const struct hwmon_chip_info aqr_hwmon_chip_info = {
++	.ops = &aqr_hwmon_ops,
++	.info = aqr_hwmon_info,
++};
++
++int aqr_hwmon_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct device *hwmon_dev;
++	char *hwmon_name;
++	int i, j;
++
++	hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
++	if (!hwmon_name)
++		return -ENOMEM;
++
++	for (i = j = 0; hwmon_name[i]; i++) {
++		if (isalnum(hwmon_name[i])) {
++			if (i != j)
++				hwmon_name[j] = hwmon_name[i];
++			j++;
++		}
++	}
++	hwmon_name[j] = '\0';
++
++	hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
++					phydev, &aqr_hwmon_chip_info, NULL);
++
++	return PTR_ERR_OR_ZERO(hwmon_dev);
++}
++
++#endif
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -0,0 +1,844 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Driver for Aquantia PHY
++ *
++ * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
++ *
++ * Copyright 2015 Freescale Semiconductor, Inc.
++ */
++
++#include <linux/kernel.h>
++#include <linux/module.h>
++#include <linux/delay.h>
++#include <linux/bitfield.h>
++#include <linux/phy.h>
++
++#include "aquantia.h"
++
++#define PHY_ID_AQ1202	0x03a1b445
++#define PHY_ID_AQ2104	0x03a1b460
++#define PHY_ID_AQR105	0x03a1b4a2
++#define PHY_ID_AQR106	0x03a1b4d0
++#define PHY_ID_AQR107	0x03a1b4e0
++#define PHY_ID_AQCS109	0x03a1b5c2
++#define PHY_ID_AQR405	0x03a1b4b0
++#define PHY_ID_AQR113C	0x31c31c12
++
++#define MDIO_PHYXS_VEND_IF_STATUS		0xe812
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR	0
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX	1
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI	2
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII	3
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI	4
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII	6
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI	7
++#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII	10
++
++#define MDIO_AN_VEND_PROV			0xc400
++#define MDIO_AN_VEND_PROV_1000BASET_FULL	BIT(15)
++#define MDIO_AN_VEND_PROV_1000BASET_HALF	BIT(14)
++#define MDIO_AN_VEND_PROV_5000BASET_FULL	BIT(11)
++#define MDIO_AN_VEND_PROV_2500BASET_FULL	BIT(10)
++#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN		BIT(4)
++#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
++#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT	4
++
++#define MDIO_AN_TX_VEND_STATUS1			0xc800
++#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK	GENMASK(3, 1)
++#define MDIO_AN_TX_VEND_STATUS1_10BASET		0
++#define MDIO_AN_TX_VEND_STATUS1_100BASETX	1
++#define MDIO_AN_TX_VEND_STATUS1_1000BASET	2
++#define MDIO_AN_TX_VEND_STATUS1_10GBASET	3
++#define MDIO_AN_TX_VEND_STATUS1_2500BASET	4
++#define MDIO_AN_TX_VEND_STATUS1_5000BASET	5
++#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX	BIT(0)
++
++#define MDIO_AN_TX_VEND_INT_STATUS1		0xcc00
++#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT	BIT(1)
++
++#define MDIO_AN_TX_VEND_INT_STATUS2		0xcc01
++#define MDIO_AN_TX_VEND_INT_STATUS2_MASK	BIT(0)
++
++#define MDIO_AN_TX_VEND_INT_MASK2		0xd401
++#define MDIO_AN_TX_VEND_INT_MASK2_LINK		BIT(0)
++
++#define MDIO_AN_RX_LP_STAT1			0xe820
++#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL	BIT(15)
++#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF	BIT(14)
++#define MDIO_AN_RX_LP_STAT1_SHORT_REACH		BIT(13)
++#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT	BIT(12)
++#define MDIO_AN_RX_LP_STAT1_AQ_PHY		BIT(2)
++
++#define MDIO_AN_RX_LP_STAT4			0xe823
++#define MDIO_AN_RX_LP_STAT4_FW_MAJOR		GENMASK(15, 8)
++#define MDIO_AN_RX_LP_STAT4_FW_MINOR		GENMASK(7, 0)
++
++#define MDIO_AN_RX_VEND_STAT3			0xe832
++#define MDIO_AN_RX_VEND_STAT3_AFR		BIT(0)
++
++/* MDIO_MMD_C22EXT */
++#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES		0xd292
++#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES		0xd294
++#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER		0xd297
++#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES		0xd313
++#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES		0xd315
++#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER		0xd317
++#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS		0xd318
++#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS	0xd319
++#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
++#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
++
++/* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_FW_ID			0x0020
++#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
++#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
++
++#define VEND1_GLOBAL_GEN_STAT2			0xc831
++#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)
++
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M			0x0310
++#define VEND1_GLOBAL_CFG_100M			0x031b
++#define VEND1_GLOBAL_CFG_1G			0x031c
++#define VEND1_GLOBAL_CFG_2_5G			0x031d
++#define VEND1_GLOBAL_CFG_5G			0x031e
++#define VEND1_GLOBAL_CFG_10G			0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
++
++#define VEND1_GLOBAL_RSVD_STAT1			0xc885
++#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
++#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
++
++#define VEND1_GLOBAL_RSVD_STAT9			0xc88d
++#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
++#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
++
++#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
++#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
++
++#define VEND1_GLOBAL_INT_STD_MASK		0xff00
++#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)
++#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)
++#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)
++#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)
++#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)
++#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
++
++#define VEND1_GLOBAL_INT_VEND_MASK		0xff01
++#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)
++#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)
++#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)
++#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)
++#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
++
++/* Sleep and timeout for checking if the Processor-Intensive
++ * MDIO operation is finished
++ */
++#define AQR107_OP_IN_PROG_SLEEP		1000
++#define AQR107_OP_IN_PROG_TIMEOUT	100000
++
++struct aqr107_hw_stat {
++	const char *name;
++	int reg;
++	int size;
++};
++
++#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
++static const struct aqr107_hw_stat aqr107_hw_stats[] = {
++	SGMII_STAT("sgmii_rx_good_frames",	    RX_GOOD_FRAMES,	26),
++	SGMII_STAT("sgmii_rx_bad_frames",	    RX_BAD_FRAMES,	26),
++	SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER,	 8),
++	SGMII_STAT("sgmii_tx_good_frames",	    TX_GOOD_FRAMES,	26),
++	SGMII_STAT("sgmii_tx_bad_frames",	    TX_BAD_FRAMES,	26),
++	SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER,	 8),
++	SGMII_STAT("sgmii_tx_collisions",	    TX_COLLISIONS,	 8),
++	SGMII_STAT("sgmii_tx_line_collisions",	    TX_LINE_COLLISIONS,	 8),
++	SGMII_STAT("sgmii_tx_frame_alignment_err",  TX_FRAME_ALIGN_ERR,	16),
++	SGMII_STAT("sgmii_tx_runt_frames",	    TX_RUNT_FRAMES,	22),
++};
++#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
++
++struct aqr107_priv {
++	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
++};
++
++static int aqr107_get_sset_count(struct phy_device *phydev)
++{
++	return AQR107_SGMII_STAT_SZ;
++}
++
++static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
++{
++	int i;
++
++	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
++		strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
++			ETH_GSTRING_LEN);
++}
++
++static u64 aqr107_get_stat(struct phy_device *phydev, int index)
++{
++	const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
++	int len_l = min(stat->size, 16);
++	int len_h = stat->size - len_l;
++	u64 ret;
++	int val;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
++	if (val < 0)
++		return U64_MAX;
++
++	ret = val & GENMASK(len_l - 1, 0);
++	if (len_h) {
++		val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
++		if (val < 0)
++			return U64_MAX;
++
++		ret += (val & GENMASK(len_h - 1, 0)) << 16;
++	}
++
++	return ret;
++}
++
++static void aqr107_get_stats(struct phy_device *phydev,
++			     struct ethtool_stats *stats, u64 *data)
++{
++	struct aqr107_priv *priv = phydev->priv;
++	u64 val;
++	int i;
++
++	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
++		val = aqr107_get_stat(phydev, i);
++		if (val == U64_MAX)
++			phydev_err(phydev, "Reading HW Statistics failed for %s\n",
++				   aqr107_hw_stats[i].name);
++		else
++			priv->sgmii_stats[i] += val;
++
++		data[i] = priv->sgmii_stats[i];
++	}
++}
++
++static int aqr_config_aneg(struct phy_device *phydev)
++{
++	bool changed = false;
++	u16 reg;
++	int ret;
++
++	if (phydev->autoneg == AUTONEG_DISABLE)
++		return genphy_c45_pma_setup_forced(phydev);
++
++	ret = genphy_c45_an_config_aneg(phydev);
++	if (ret < 0)
++		return ret;
++	if (ret > 0)
++		changed = true;
++
++	/* Clause 45 has no standardized support for 1000BaseT, therefore
++	 * use vendor registers for this mode.
++	 */
++	reg = 0;
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
++			      phydev->advertising))
++		reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
++
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
++			      phydev->advertising))
++		reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
++
++	/* Handle the case when the 2.5G and 5G speeds are not advertised */
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			      phydev->advertising))
++		reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
++
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
++			      phydev->advertising))
++		reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
++				     MDIO_AN_VEND_PROV_1000BASET_HALF |
++				     MDIO_AN_VEND_PROV_1000BASET_FULL |
++				     MDIO_AN_VEND_PROV_2500BASET_FULL |
++				     MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
++	if (ret < 0)
++		return ret;
++	if (ret > 0)
++		changed = true;
++
++	return genphy_c45_check_and_restart_aneg(phydev, changed);
++}
++
++static int aqr_config_intr(struct phy_device *phydev)
++{
++	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
++	int err;
++
++	if (en) {
++		/* Clear any pending interrupts before enabling them */
++		err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
++		if (err < 0)
++			return err;
++	}
++
++	err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
++			    en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
++	if (err < 0)
++		return err;
++
++	err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
++			    en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
++	if (err < 0)
++		return err;
++
++	err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
++			    en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
++			    VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
++	if (err < 0)
++		return err;
++
++	if (!en) {
++		/* Clear any pending interrupts after we have disabled them */
++		err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
++		if (err < 0)
++			return err;
++	}
++
++	return 0;
++}
++
++static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
++{
++	int irq_status;
++
++	irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
++				  MDIO_AN_TX_VEND_INT_STATUS2);
++	if (irq_status < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
++		return IRQ_NONE;
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static int aqr_read_status(struct phy_device *phydev)
++{
++	int val;
++
++	if (phydev->autoneg == AUTONEG_ENABLE) {
++		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
++		if (val < 0)
++			return val;
++
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
++				 phydev->lp_advertising,
++				 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
++				 phydev->lp_advertising,
++				 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
++	}
++
++	return genphy_c45_read_status(phydev);
++}
++
++static int aqr107_read_rate(struct phy_device *phydev)
++{
++	u32 config_reg;
++	int val;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
++	if (val < 0)
++		return val;
++
++	if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
++		phydev->duplex = DUPLEX_FULL;
++	else
++		phydev->duplex = DUPLEX_HALF;
++
++	switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
++	case MDIO_AN_TX_VEND_STATUS1_10BASET:
++		phydev->speed = SPEED_10;
++		config_reg = VEND1_GLOBAL_CFG_10M;
++		break;
++	case MDIO_AN_TX_VEND_STATUS1_100BASETX:
++		phydev->speed = SPEED_100;
++		config_reg = VEND1_GLOBAL_CFG_100M;
++		break;
++	case MDIO_AN_TX_VEND_STATUS1_1000BASET:
++		phydev->speed = SPEED_1000;
++		config_reg = VEND1_GLOBAL_CFG_1G;
++		break;
++	case MDIO_AN_TX_VEND_STATUS1_2500BASET:
++		phydev->speed = SPEED_2500;
++		config_reg = VEND1_GLOBAL_CFG_2_5G;
++		break;
++	case MDIO_AN_TX_VEND_STATUS1_5000BASET:
++		phydev->speed = SPEED_5000;
++		config_reg = VEND1_GLOBAL_CFG_5G;
++		break;
++	case MDIO_AN_TX_VEND_STATUS1_10GBASET:
++		phydev->speed = SPEED_10000;
++		config_reg = VEND1_GLOBAL_CFG_10G;
++		break;
++	default:
++		phydev->speed = SPEED_UNKNOWN;
++		return 0;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
++	if (val < 0)
++		return val;
++
++	if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
++	    VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
++		phydev->rate_matching = RATE_MATCH_PAUSE;
++	else
++		phydev->rate_matching = RATE_MATCH_NONE;
++
++	return 0;
++}
++
++static int aqr107_read_status(struct phy_device *phydev)
++{
++	int val, ret;
++
++	ret = aqr_read_status(phydev);
++	if (ret)
++		return ret;
++
++	if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
++		return 0;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
++	if (val < 0)
++		return val;
++
++	switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
++		phydev->interface = PHY_INTERFACE_MODE_10GKR;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
++		phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
++		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
++		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
++		phydev->interface = PHY_INTERFACE_MODE_XAUI;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
++		phydev->interface = PHY_INTERFACE_MODE_SGMII;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
++		phydev->interface = PHY_INTERFACE_MODE_RXAUI;
++		break;
++	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
++		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++		break;
++	default:
++		phydev->interface = PHY_INTERFACE_MODE_NA;
++		break;
++	}
++
++	/* Read possibly downshifted rate from vendor register */
++	return aqr107_read_rate(phydev);
++}
++
++static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
++{
++	int val, cnt, enable;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
++	if (val < 0)
++		return val;
++
++	enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
++	cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
++
++	*data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
++
++	return 0;
++}
++
++static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
++{
++	int val = 0;
++
++	if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
++		return -E2BIG;
++
++	if (cnt != DOWNSHIFT_DEV_DISABLE) {
++		val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
++		val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
++	}
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
++			      MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
++			      MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
++}
++
++static int aqr107_get_tunable(struct phy_device *phydev,
++			      struct ethtool_tunable *tuna, void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return aqr107_get_downshift(phydev, data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static int aqr107_set_tunable(struct phy_device *phydev,
++			      struct ethtool_tunable *tuna, const void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return aqr107_set_downshift(phydev, *(const u8 *)data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++/* If we configure settings whilst firmware is still initializing the chip,
++ * then these settings may be overwritten. Therefore make sure chip
++ * initialization has completed. Use presence of the firmware ID as
++ * indicator for initialization having completed.
++ * The chip also provides a "reset completed" bit, but it's cleared after
++ * read. Therefore function would time out if called again.
++ */
++static int aqr107_wait_reset_complete(struct phy_device *phydev)
++{
++	int val;
++
++	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					 VEND1_GLOBAL_FW_ID, val, val != 0,
++					 20000, 2000000, false);
++}
++
++static void aqr107_chip_info(struct phy_device *phydev)
++{
++	u8 fw_major, fw_minor, build_id, prov_id;
++	int val;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
++	if (val < 0)
++		return;
++
++	fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
++	fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
++	if (val < 0)
++		return;
++
++	build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
++	prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
++
++	phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
++		   fw_major, fw_minor, build_id, prov_id);
++}
++
++static int aqr107_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Check that the PHY interface type is compatible */
++	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++	    phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
++	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
++	    phydev->interface != PHY_INTERFACE_MODE_XGMII &&
++	    phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
++	    phydev->interface != PHY_INTERFACE_MODE_10GKR &&
++	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
++	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
++	    phydev->interface != PHY_INTERFACE_MODE_RXAUI)
++		return -ENODEV;
++
++	WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
++	     "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
++
++	ret = aqr107_wait_reset_complete(phydev);
++	if (!ret)
++		aqr107_chip_info(phydev);
++
++	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
++}
++
++static int aqcs109_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Check that the PHY interface type is compatible */
++	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
++	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
++		return -ENODEV;
++
++	ret = aqr107_wait_reset_complete(phydev);
++	if (!ret)
++		aqr107_chip_info(phydev);
++
++	/* AQCS109 belongs to a chip family partially supporting 10G and 5G.
++	 * PMA speed ability bits are the same for all members of the family,
++	 * AQCS109 however supports speeds up to 2.5G only.
++	 */
++	ret = phy_set_max_speed(phydev, SPEED_2500);
++	if (ret)
++		return ret;
++
++	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
++}
++
++static void aqr107_link_change_notify(struct phy_device *phydev)
++{
++	u8 fw_major, fw_minor;
++	bool downshift, short_reach, afr;
++	int mode, val;
++
++	if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
++		return;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
++	/* call failed or link partner is no Aquantia PHY */
++	if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
++		return;
++
++	short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
++	downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
++	if (val < 0)
++		return;
++
++	fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
++	fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
++	if (val < 0)
++		return;
++
++	afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
++
++	phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
++		   fw_major, fw_minor,
++		   short_reach ? ", short reach mode" : "",
++		   downshift ? ", fast-retrain downshift advertised" : "",
++		   afr ? ", fast reframe advertised" : "");
++
++	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
++	if (val < 0)
++		return;
++
++	mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
++	if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
++		phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
++}
++
++static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
++{
++	int val, err;
++
++	/* The datasheet notes to wait at least 1ms after issuing a
++	 * processor intensive operation before checking.
++	 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
++	 * because that just determines the maximum time slept, not the minimum.
++	 */
++	usleep_range(1000, 5000);
++
++	err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					VEND1_GLOBAL_GEN_STAT2, val,
++					!(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
++					AQR107_OP_IN_PROG_SLEEP,
++					AQR107_OP_IN_PROG_TIMEOUT, false);
++	if (err) {
++		phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
++		return err;
++	}
++
++	return 0;
++}
++
++static int aqr107_get_rate_matching(struct phy_device *phydev,
++				    phy_interface_t iface)
++{
++	if (iface == PHY_INTERFACE_MODE_10GBASER ||
++	    iface == PHY_INTERFACE_MODE_2500BASEX ||
++	    iface == PHY_INTERFACE_MODE_NA)
++		return RATE_MATCH_PAUSE;
++	return RATE_MATCH_NONE;
++}
++
++static int aqr107_suspend(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
++			       MDIO_CTRL1_LPOWER);
++	if (err)
++		return err;
++
++	return aqr107_wait_processor_intensive_op(phydev);
++}
++
++static int aqr107_resume(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
++				 MDIO_CTRL1_LPOWER);
++	if (err)
++		return err;
++
++	return aqr107_wait_processor_intensive_op(phydev);
++}
++
++static int aqr107_probe(struct phy_device *phydev)
++{
++	phydev->priv = devm_kzalloc(&phydev->mdio.dev,
++				    sizeof(struct aqr107_priv), GFP_KERNEL);
++	if (!phydev->priv)
++		return -ENOMEM;
++
++	return aqr_hwmon_probe(phydev);
++}
++
++static struct phy_driver aqr_driver[] = {
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
++	.name		= "Aquantia AQ1202",
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr_read_status,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
++	.name		= "Aquantia AQ2104",
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr_read_status,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
++	.name		= "Aquantia AQR105",
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr_read_status,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
++	.name		= "Aquantia AQR106",
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr_read_status,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
++	.name		= "Aquantia AQR107",
++	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init	= aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
++	.name		= "Aquantia AQCS109",
++	.probe		= aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init	= aqcs109_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend	= aqr107_suspend,
++	.resume		= aqr107_resume,
++	.get_sset_count	= aqr107_get_sset_count,
++	.get_strings	= aqr107_get_strings,
++	.get_stats	= aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
++	.name		= "Aquantia AQR405",
++	.config_aneg    = aqr_config_aneg,
++	.config_intr	= aqr_config_intr,
++	.handle_interrupt = aqr_handle_interrupt,
++	.read_status	= aqr_read_status,
++},
++{
++	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
++	.name           = "Aquantia AQR113C",
++	.probe          = aqr107_probe,
++	.get_rate_matching = aqr107_get_rate_matching,
++	.config_init    = aqr107_config_init,
++	.config_aneg    = aqr_config_aneg,
++	.config_intr    = aqr_config_intr,
++	.handle_interrupt       = aqr_handle_interrupt,
++	.read_status    = aqr107_read_status,
++	.get_tunable    = aqr107_get_tunable,
++	.set_tunable    = aqr107_set_tunable,
++	.suspend        = aqr107_suspend,
++	.resume         = aqr107_resume,
++	.get_sset_count = aqr107_get_sset_count,
++	.get_strings    = aqr107_get_strings,
++	.get_stats      = aqr107_get_stats,
++	.link_change_notify = aqr107_link_change_notify,
++},
++};
++
++module_phy_driver(aqr_driver);
++
++static struct mdio_device_id __maybe_unused aqr_tbl[] = {
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, aqr_tbl);
++
++MODULE_DESCRIPTION("Aquantia PHY driver");
++MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
++MODULE_LICENSE("GPL v2");
+--- a/drivers/net/phy/aquantia_hwmon.c
++++ /dev/null
+@@ -1,250 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/* HWMON driver for Aquantia PHY
+- *
+- * Author: Nikita Yushchenko <nikita.yoush@cogentembedded.com>
+- * Author: Andrew Lunn <andrew@lunn.ch>
+- * Author: Heiner Kallweit <hkallweit1@gmail.com>
+- */
+-
+-#include <linux/phy.h>
+-#include <linux/device.h>
+-#include <linux/ctype.h>
+-#include <linux/hwmon.h>
+-
+-#include "aquantia.h"
+-
+-/* Vendor specific 1, MDIO_MMD_VEND2 */
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
+-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
+-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
+-#define VEND1_THERMAL_STAT1			0xc820
+-#define VEND1_THERMAL_STAT2			0xc821
+-#define VEND1_THERMAL_STAT2_VALID		BIT(0)
+-#define VEND1_GENERAL_STAT1			0xc830
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)
+-
+-#if IS_REACHABLE(CONFIG_HWMON)
+-
+-static umode_t aqr_hwmon_is_visible(const void *data,
+-				    enum hwmon_sensor_types type,
+-				    u32 attr, int channel)
+-{
+-	if (type != hwmon_temp)
+-		return 0;
+-
+-	switch (attr) {
+-	case hwmon_temp_input:
+-	case hwmon_temp_min_alarm:
+-	case hwmon_temp_max_alarm:
+-	case hwmon_temp_lcrit_alarm:
+-	case hwmon_temp_crit_alarm:
+-		return 0444;
+-	case hwmon_temp_min:
+-	case hwmon_temp_max:
+-	case hwmon_temp_lcrit:
+-	case hwmon_temp_crit:
+-		return 0644;
+-	default:
+-		return 0;
+-	}
+-}
+-
+-static int aqr_hwmon_get(struct phy_device *phydev, int reg, long *value)
+-{
+-	int temp = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
+-
+-	if (temp < 0)
+-		return temp;
+-
+-	/* 16 bit value is 2's complement with LSB = 1/256th degree Celsius */
+-	*value = (s16)temp * 1000 / 256;
+-
+-	return 0;
+-}
+-
+-static int aqr_hwmon_set(struct phy_device *phydev, int reg, long value)
+-{
+-	int temp;
+-
+-	if (value >= 128000 || value < -128000)
+-		return -ERANGE;
+-
+-	temp = value * 256 / 1000;
+-
+-	/* temp is in s16 range and we're interested in lower 16 bits only */
+-	return phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, (u16)temp);
+-}
+-
+-static int aqr_hwmon_test_bit(struct phy_device *phydev, int reg, int bit)
+-{
+-	int val = phy_read_mmd(phydev, MDIO_MMD_VEND1, reg);
+-
+-	if (val < 0)
+-		return val;
+-
+-	return !!(val & bit);
+-}
+-
+-static int aqr_hwmon_status1(struct phy_device *phydev, int bit, long *value)
+-{
+-	int val = aqr_hwmon_test_bit(phydev, VEND1_GENERAL_STAT1, bit);
+-
+-	if (val < 0)
+-		return val;
+-
+-	*value = val;
+-
+-	return 0;
+-}
+-
+-static int aqr_hwmon_read(struct device *dev, enum hwmon_sensor_types type,
+-			  u32 attr, int channel, long *value)
+-{
+-	struct phy_device *phydev = dev_get_drvdata(dev);
+-	int reg;
+-
+-	if (type != hwmon_temp)
+-		return -EOPNOTSUPP;
+-
+-	switch (attr) {
+-	case hwmon_temp_input:
+-		reg = aqr_hwmon_test_bit(phydev, VEND1_THERMAL_STAT2,
+-					 VEND1_THERMAL_STAT2_VALID);
+-		if (reg < 0)
+-			return reg;
+-		if (!reg)
+-			return -EBUSY;
+-
+-		return aqr_hwmon_get(phydev, VEND1_THERMAL_STAT1, value);
+-
+-	case hwmon_temp_lcrit:
+-		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
+-				     value);
+-	case hwmon_temp_min:
+-		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
+-				     value);
+-	case hwmon_temp_max:
+-		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
+-				     value);
+-	case hwmon_temp_crit:
+-		return aqr_hwmon_get(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
+-				     value);
+-	case hwmon_temp_lcrit_alarm:
+-		return aqr_hwmon_status1(phydev,
+-					 VEND1_GENERAL_STAT1_LOW_TEMP_FAIL,
+-					 value);
+-	case hwmon_temp_min_alarm:
+-		return aqr_hwmon_status1(phydev,
+-					 VEND1_GENERAL_STAT1_LOW_TEMP_WARN,
+-					 value);
+-	case hwmon_temp_max_alarm:
+-		return aqr_hwmon_status1(phydev,
+-					 VEND1_GENERAL_STAT1_HIGH_TEMP_WARN,
+-					 value);
+-	case hwmon_temp_crit_alarm:
+-		return aqr_hwmon_status1(phydev,
+-					 VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL,
+-					 value);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int aqr_hwmon_write(struct device *dev, enum hwmon_sensor_types type,
+-			   u32 attr, int channel, long value)
+-{
+-	struct phy_device *phydev = dev_get_drvdata(dev);
+-
+-	if (type != hwmon_temp)
+-		return -EOPNOTSUPP;
+-
+-	switch (attr) {
+-	case hwmon_temp_lcrit:
+-		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_FAIL,
+-				     value);
+-	case hwmon_temp_min:
+-		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_LOW_TEMP_WARN,
+-				     value);
+-	case hwmon_temp_max:
+-		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_WARN,
+-				     value);
+-	case hwmon_temp_crit:
+-		return aqr_hwmon_set(phydev, VEND1_THERMAL_PROV_HIGH_TEMP_FAIL,
+-				     value);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static const struct hwmon_ops aqr_hwmon_ops = {
+-	.is_visible = aqr_hwmon_is_visible,
+-	.read = aqr_hwmon_read,
+-	.write = aqr_hwmon_write,
+-};
+-
+-static u32 aqr_hwmon_chip_config[] = {
+-	HWMON_C_REGISTER_TZ,
+-	0,
+-};
+-
+-static const struct hwmon_channel_info aqr_hwmon_chip = {
+-	.type = hwmon_chip,
+-	.config = aqr_hwmon_chip_config,
+-};
+-
+-static u32 aqr_hwmon_temp_config[] = {
+-	HWMON_T_INPUT |
+-	HWMON_T_MAX | HWMON_T_MIN |
+-	HWMON_T_MAX_ALARM | HWMON_T_MIN_ALARM |
+-	HWMON_T_CRIT | HWMON_T_LCRIT |
+-	HWMON_T_CRIT_ALARM | HWMON_T_LCRIT_ALARM,
+-	0,
+-};
+-
+-static const struct hwmon_channel_info aqr_hwmon_temp = {
+-	.type = hwmon_temp,
+-	.config = aqr_hwmon_temp_config,
+-};
+-
+-static const struct hwmon_channel_info *aqr_hwmon_info[] = {
+-	&aqr_hwmon_chip,
+-	&aqr_hwmon_temp,
+-	NULL,
+-};
+-
+-static const struct hwmon_chip_info aqr_hwmon_chip_info = {
+-	.ops = &aqr_hwmon_ops,
+-	.info = aqr_hwmon_info,
+-};
+-
+-int aqr_hwmon_probe(struct phy_device *phydev)
+-{
+-	struct device *dev = &phydev->mdio.dev;
+-	struct device *hwmon_dev;
+-	char *hwmon_name;
+-	int i, j;
+-
+-	hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL);
+-	if (!hwmon_name)
+-		return -ENOMEM;
+-
+-	for (i = j = 0; hwmon_name[i]; i++) {
+-		if (isalnum(hwmon_name[i])) {
+-			if (i != j)
+-				hwmon_name[j] = hwmon_name[i];
+-			j++;
+-		}
+-	}
+-	hwmon_name[j] = '\0';
+-
+-	hwmon_dev = devm_hwmon_device_register_with_info(dev, hwmon_name,
+-					phydev, &aqr_hwmon_chip_info, NULL);
+-
+-	return PTR_ERR_OR_ZERO(hwmon_dev);
+-}
+-
+-#endif
+--- a/drivers/net/phy/aquantia_main.c
++++ /dev/null
+@@ -1,844 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0
+-/*
+- * Driver for Aquantia PHY
+- *
+- * Author: Shaohui Xie <Shaohui.Xie@freescale.com>
+- *
+- * Copyright 2015 Freescale Semiconductor, Inc.
+- */
+-
+-#include <linux/kernel.h>
+-#include <linux/module.h>
+-#include <linux/delay.h>
+-#include <linux/bitfield.h>
+-#include <linux/phy.h>
+-
+-#include "aquantia.h"
+-
+-#define PHY_ID_AQ1202	0x03a1b445
+-#define PHY_ID_AQ2104	0x03a1b460
+-#define PHY_ID_AQR105	0x03a1b4a2
+-#define PHY_ID_AQR106	0x03a1b4d0
+-#define PHY_ID_AQR107	0x03a1b4e0
+-#define PHY_ID_AQCS109	0x03a1b5c2
+-#define PHY_ID_AQR405	0x03a1b4b0
+-#define PHY_ID_AQR113C	0x31c31c12
+-
+-#define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR	0
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX	1
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI	2
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII	3
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI	4
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII	6
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI	7
+-#define MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII	10
+-
+-#define MDIO_AN_VEND_PROV			0xc400
+-#define MDIO_AN_VEND_PROV_1000BASET_FULL	BIT(15)
+-#define MDIO_AN_VEND_PROV_1000BASET_HALF	BIT(14)
+-#define MDIO_AN_VEND_PROV_5000BASET_FULL	BIT(11)
+-#define MDIO_AN_VEND_PROV_2500BASET_FULL	BIT(10)
+-#define MDIO_AN_VEND_PROV_DOWNSHIFT_EN		BIT(4)
+-#define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
+-#define MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT	4
+-
+-#define MDIO_AN_TX_VEND_STATUS1			0xc800
+-#define MDIO_AN_TX_VEND_STATUS1_RATE_MASK	GENMASK(3, 1)
+-#define MDIO_AN_TX_VEND_STATUS1_10BASET		0
+-#define MDIO_AN_TX_VEND_STATUS1_100BASETX	1
+-#define MDIO_AN_TX_VEND_STATUS1_1000BASET	2
+-#define MDIO_AN_TX_VEND_STATUS1_10GBASET	3
+-#define MDIO_AN_TX_VEND_STATUS1_2500BASET	4
+-#define MDIO_AN_TX_VEND_STATUS1_5000BASET	5
+-#define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX	BIT(0)
+-
+-#define MDIO_AN_TX_VEND_INT_STATUS1		0xcc00
+-#define MDIO_AN_TX_VEND_INT_STATUS1_DOWNSHIFT	BIT(1)
+-
+-#define MDIO_AN_TX_VEND_INT_STATUS2		0xcc01
+-#define MDIO_AN_TX_VEND_INT_STATUS2_MASK	BIT(0)
+-
+-#define MDIO_AN_TX_VEND_INT_MASK2		0xd401
+-#define MDIO_AN_TX_VEND_INT_MASK2_LINK		BIT(0)
+-
+-#define MDIO_AN_RX_LP_STAT1			0xe820
+-#define MDIO_AN_RX_LP_STAT1_1000BASET_FULL	BIT(15)
+-#define MDIO_AN_RX_LP_STAT1_1000BASET_HALF	BIT(14)
+-#define MDIO_AN_RX_LP_STAT1_SHORT_REACH		BIT(13)
+-#define MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT	BIT(12)
+-#define MDIO_AN_RX_LP_STAT1_AQ_PHY		BIT(2)
+-
+-#define MDIO_AN_RX_LP_STAT4			0xe823
+-#define MDIO_AN_RX_LP_STAT4_FW_MAJOR		GENMASK(15, 8)
+-#define MDIO_AN_RX_LP_STAT4_FW_MINOR		GENMASK(7, 0)
+-
+-#define MDIO_AN_RX_VEND_STAT3			0xe832
+-#define MDIO_AN_RX_VEND_STAT3_AFR		BIT(0)
+-
+-/* MDIO_MMD_C22EXT */
+-#define MDIO_C22EXT_STAT_SGMII_RX_GOOD_FRAMES		0xd292
+-#define MDIO_C22EXT_STAT_SGMII_RX_BAD_FRAMES		0xd294
+-#define MDIO_C22EXT_STAT_SGMII_RX_FALSE_CARRIER		0xd297
+-#define MDIO_C22EXT_STAT_SGMII_TX_GOOD_FRAMES		0xd313
+-#define MDIO_C22EXT_STAT_SGMII_TX_BAD_FRAMES		0xd315
+-#define MDIO_C22EXT_STAT_SGMII_TX_FALSE_CARRIER		0xd317
+-#define MDIO_C22EXT_STAT_SGMII_TX_COLLISIONS		0xd318
+-#define MDIO_C22EXT_STAT_SGMII_TX_LINE_COLLISIONS	0xd319
+-#define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
+-#define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
+-
+-/* Vendor specific 1, MDIO_MMD_VEND1 */
+-#define VEND1_GLOBAL_FW_ID			0x0020
+-#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
+-#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
+-
+-#define VEND1_GLOBAL_GEN_STAT2			0xc831
+-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)
+-
+-/* The following registers all have similar layouts; first the registers... */
+-#define VEND1_GLOBAL_CFG_10M			0x0310
+-#define VEND1_GLOBAL_CFG_100M			0x031b
+-#define VEND1_GLOBAL_CFG_1G			0x031c
+-#define VEND1_GLOBAL_CFG_2_5G			0x031d
+-#define VEND1_GLOBAL_CFG_5G			0x031e
+-#define VEND1_GLOBAL_CFG_10G			0x031f
+-/* ...and now the fields */
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
+-
+-#define VEND1_GLOBAL_RSVD_STAT1			0xc885
+-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
+-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
+-
+-#define VEND1_GLOBAL_RSVD_STAT9			0xc88d
+-#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
+-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
+-
+-#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
+-#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
+-
+-#define VEND1_GLOBAL_INT_STD_MASK		0xff00
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)
+-#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)
+-#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
+-
+-#define VEND1_GLOBAL_INT_VEND_MASK		0xff01
+-#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)
+-#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
+-
+-/* Sleep and timeout for checking if the Processor-Intensive
+- * MDIO operation is finished
+- */
+-#define AQR107_OP_IN_PROG_SLEEP		1000
+-#define AQR107_OP_IN_PROG_TIMEOUT	100000
+-
+-struct aqr107_hw_stat {
+-	const char *name;
+-	int reg;
+-	int size;
+-};
+-
+-#define SGMII_STAT(n, r, s) { n, MDIO_C22EXT_STAT_SGMII_ ## r, s }
+-static const struct aqr107_hw_stat aqr107_hw_stats[] = {
+-	SGMII_STAT("sgmii_rx_good_frames",	    RX_GOOD_FRAMES,	26),
+-	SGMII_STAT("sgmii_rx_bad_frames",	    RX_BAD_FRAMES,	26),
+-	SGMII_STAT("sgmii_rx_false_carrier_events", RX_FALSE_CARRIER,	 8),
+-	SGMII_STAT("sgmii_tx_good_frames",	    TX_GOOD_FRAMES,	26),
+-	SGMII_STAT("sgmii_tx_bad_frames",	    TX_BAD_FRAMES,	26),
+-	SGMII_STAT("sgmii_tx_false_carrier_events", TX_FALSE_CARRIER,	 8),
+-	SGMII_STAT("sgmii_tx_collisions",	    TX_COLLISIONS,	 8),
+-	SGMII_STAT("sgmii_tx_line_collisions",	    TX_LINE_COLLISIONS,	 8),
+-	SGMII_STAT("sgmii_tx_frame_alignment_err",  TX_FRAME_ALIGN_ERR,	16),
+-	SGMII_STAT("sgmii_tx_runt_frames",	    TX_RUNT_FRAMES,	22),
+-};
+-#define AQR107_SGMII_STAT_SZ ARRAY_SIZE(aqr107_hw_stats)
+-
+-struct aqr107_priv {
+-	u64 sgmii_stats[AQR107_SGMII_STAT_SZ];
+-};
+-
+-static int aqr107_get_sset_count(struct phy_device *phydev)
+-{
+-	return AQR107_SGMII_STAT_SZ;
+-}
+-
+-static void aqr107_get_strings(struct phy_device *phydev, u8 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)
+-		strscpy(data + i * ETH_GSTRING_LEN, aqr107_hw_stats[i].name,
+-			ETH_GSTRING_LEN);
+-}
+-
+-static u64 aqr107_get_stat(struct phy_device *phydev, int index)
+-{
+-	const struct aqr107_hw_stat *stat = aqr107_hw_stats + index;
+-	int len_l = min(stat->size, 16);
+-	int len_h = stat->size - len_l;
+-	u64 ret;
+-	int val;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg);
+-	if (val < 0)
+-		return U64_MAX;
+-
+-	ret = val & GENMASK(len_l - 1, 0);
+-	if (len_h) {
+-		val = phy_read_mmd(phydev, MDIO_MMD_C22EXT, stat->reg + 1);
+-		if (val < 0)
+-			return U64_MAX;
+-
+-		ret += (val & GENMASK(len_h - 1, 0)) << 16;
+-	}
+-
+-	return ret;
+-}
+-
+-static void aqr107_get_stats(struct phy_device *phydev,
+-			     struct ethtool_stats *stats, u64 *data)
+-{
+-	struct aqr107_priv *priv = phydev->priv;
+-	u64 val;
+-	int i;
+-
+-	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {
+-		val = aqr107_get_stat(phydev, i);
+-		if (val == U64_MAX)
+-			phydev_err(phydev, "Reading HW Statistics failed for %s\n",
+-				   aqr107_hw_stats[i].name);
+-		else
+-			priv->sgmii_stats[i] += val;
+-
+-		data[i] = priv->sgmii_stats[i];
+-	}
+-}
+-
+-static int aqr_config_aneg(struct phy_device *phydev)
+-{
+-	bool changed = false;
+-	u16 reg;
+-	int ret;
+-
+-	if (phydev->autoneg == AUTONEG_DISABLE)
+-		return genphy_c45_pma_setup_forced(phydev);
+-
+-	ret = genphy_c45_an_config_aneg(phydev);
+-	if (ret < 0)
+-		return ret;
+-	if (ret > 0)
+-		changed = true;
+-
+-	/* Clause 45 has no standardized support for 1000BaseT, therefore
+-	 * use vendor registers for this mode.
+-	 */
+-	reg = 0;
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+-			      phydev->advertising))
+-		reg |= MDIO_AN_VEND_PROV_1000BASET_FULL;
+-
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+-			      phydev->advertising))
+-		reg |= MDIO_AN_VEND_PROV_1000BASET_HALF;
+-
+-	/* Handle the case when the 2.5G and 5G speeds are not advertised */
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
+-			      phydev->advertising))
+-		reg |= MDIO_AN_VEND_PROV_2500BASET_FULL;
+-
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_5000baseT_Full_BIT,
+-			      phydev->advertising))
+-		reg |= MDIO_AN_VEND_PROV_5000BASET_FULL;
+-
+-	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
+-				     MDIO_AN_VEND_PROV_1000BASET_HALF |
+-				     MDIO_AN_VEND_PROV_1000BASET_FULL |
+-				     MDIO_AN_VEND_PROV_2500BASET_FULL |
+-				     MDIO_AN_VEND_PROV_5000BASET_FULL, reg);
+-	if (ret < 0)
+-		return ret;
+-	if (ret > 0)
+-		changed = true;
+-
+-	return genphy_c45_check_and_restart_aneg(phydev, changed);
+-}
+-
+-static int aqr_config_intr(struct phy_device *phydev)
+-{
+-	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
+-	int err;
+-
+-	if (en) {
+-		/* Clear any pending interrupts before enabling them */
+-		err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
+-		if (err < 0)
+-			return err;
+-	}
+-
+-	err = phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_MASK2,
+-			    en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);
+-	if (err < 0)
+-		return err;
+-
+-	err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_STD_MASK,
+-			    en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);
+-	if (err < 0)
+-		return err;
+-
+-	err = phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_INT_VEND_MASK,
+-			    en ? VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3 |
+-			    VEND1_GLOBAL_INT_VEND_MASK_AN : 0);
+-	if (err < 0)
+-		return err;
+-
+-	if (!en) {
+-		/* Clear any pending interrupts after we have disabled them */
+-		err = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_INT_STATUS2);
+-		if (err < 0)
+-			return err;
+-	}
+-
+-	return 0;
+-}
+-
+-static irqreturn_t aqr_handle_interrupt(struct phy_device *phydev)
+-{
+-	int irq_status;
+-
+-	irq_status = phy_read_mmd(phydev, MDIO_MMD_AN,
+-				  MDIO_AN_TX_VEND_INT_STATUS2);
+-	if (irq_status < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	if (!(irq_status & MDIO_AN_TX_VEND_INT_STATUS2_MASK))
+-		return IRQ_NONE;
+-
+-	phy_trigger_machine(phydev);
+-
+-	return IRQ_HANDLED;
+-}
+-
+-static int aqr_read_status(struct phy_device *phydev)
+-{
+-	int val;
+-
+-	if (phydev->autoneg == AUTONEG_ENABLE) {
+-		val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
+-		if (val < 0)
+-			return val;
+-
+-		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
+-				 phydev->lp_advertising,
+-				 val & MDIO_AN_RX_LP_STAT1_1000BASET_FULL);
+-		linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
+-				 phydev->lp_advertising,
+-				 val & MDIO_AN_RX_LP_STAT1_1000BASET_HALF);
+-	}
+-
+-	return genphy_c45_read_status(phydev);
+-}
+-
+-static int aqr107_read_rate(struct phy_device *phydev)
+-{
+-	u32 config_reg;
+-	int val;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_TX_VEND_STATUS1);
+-	if (val < 0)
+-		return val;
+-
+-	if (val & MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX)
+-		phydev->duplex = DUPLEX_FULL;
+-	else
+-		phydev->duplex = DUPLEX_HALF;
+-
+-	switch (FIELD_GET(MDIO_AN_TX_VEND_STATUS1_RATE_MASK, val)) {
+-	case MDIO_AN_TX_VEND_STATUS1_10BASET:
+-		phydev->speed = SPEED_10;
+-		config_reg = VEND1_GLOBAL_CFG_10M;
+-		break;
+-	case MDIO_AN_TX_VEND_STATUS1_100BASETX:
+-		phydev->speed = SPEED_100;
+-		config_reg = VEND1_GLOBAL_CFG_100M;
+-		break;
+-	case MDIO_AN_TX_VEND_STATUS1_1000BASET:
+-		phydev->speed = SPEED_1000;
+-		config_reg = VEND1_GLOBAL_CFG_1G;
+-		break;
+-	case MDIO_AN_TX_VEND_STATUS1_2500BASET:
+-		phydev->speed = SPEED_2500;
+-		config_reg = VEND1_GLOBAL_CFG_2_5G;
+-		break;
+-	case MDIO_AN_TX_VEND_STATUS1_5000BASET:
+-		phydev->speed = SPEED_5000;
+-		config_reg = VEND1_GLOBAL_CFG_5G;
+-		break;
+-	case MDIO_AN_TX_VEND_STATUS1_10GBASET:
+-		phydev->speed = SPEED_10000;
+-		config_reg = VEND1_GLOBAL_CFG_10G;
+-		break;
+-	default:
+-		phydev->speed = SPEED_UNKNOWN;
+-		return 0;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, config_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (FIELD_GET(VEND1_GLOBAL_CFG_RATE_ADAPT, val) ==
+-	    VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE)
+-		phydev->rate_matching = RATE_MATCH_PAUSE;
+-	else
+-		phydev->rate_matching = RATE_MATCH_NONE;
+-
+-	return 0;
+-}
+-
+-static int aqr107_read_status(struct phy_device *phydev)
+-{
+-	int val, ret;
+-
+-	ret = aqr_read_status(phydev);
+-	if (ret)
+-		return ret;
+-
+-	if (!phydev->link || phydev->autoneg == AUTONEG_DISABLE)
+-		return 0;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PHYXS, MDIO_PHYXS_VEND_IF_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	switch (FIELD_GET(MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK, val)) {
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR:
+-		phydev->interface = PHY_INTERFACE_MODE_10GKR;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_KX:
+-		phydev->interface = PHY_INTERFACE_MODE_1000BASEKX;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XFI:
+-		phydev->interface = PHY_INTERFACE_MODE_10GBASER;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_USXGMII:
+-		phydev->interface = PHY_INTERFACE_MODE_USXGMII;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_XAUI:
+-		phydev->interface = PHY_INTERFACE_MODE_XAUI;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_SGMII:
+-		phydev->interface = PHY_INTERFACE_MODE_SGMII;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_RXAUI:
+-		phydev->interface = PHY_INTERFACE_MODE_RXAUI;
+-		break;
+-	case MDIO_PHYXS_VEND_IF_STATUS_TYPE_OCSGMII:
+-		phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+-		break;
+-	default:
+-		phydev->interface = PHY_INTERFACE_MODE_NA;
+-		break;
+-	}
+-
+-	/* Read possibly downshifted rate from vendor register */
+-	return aqr107_read_rate(phydev);
+-}
+-
+-static int aqr107_get_downshift(struct phy_device *phydev, u8 *data)
+-{
+-	int val, cnt, enable;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV);
+-	if (val < 0)
+-		return val;
+-
+-	enable = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_EN, val);
+-	cnt = FIELD_GET(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
+-
+-	*data = enable && cnt ? cnt : DOWNSHIFT_DEV_DISABLE;
+-
+-	return 0;
+-}
+-
+-static int aqr107_set_downshift(struct phy_device *phydev, u8 cnt)
+-{
+-	int val = 0;
+-
+-	if (!FIELD_FIT(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt))
+-		return -E2BIG;
+-
+-	if (cnt != DOWNSHIFT_DEV_DISABLE) {
+-		val = MDIO_AN_VEND_PROV_DOWNSHIFT_EN;
+-		val |= FIELD_PREP(MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, cnt);
+-	}
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, MDIO_AN_VEND_PROV,
+-			      MDIO_AN_VEND_PROV_DOWNSHIFT_EN |
+-			      MDIO_AN_VEND_PROV_DOWNSHIFT_MASK, val);
+-}
+-
+-static int aqr107_get_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return aqr107_get_downshift(phydev, data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int aqr107_set_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, const void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return aqr107_set_downshift(phydev, *(const u8 *)data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-/* If we configure settings whilst firmware is still initializing the chip,
+- * then these settings may be overwritten. Therefore make sure chip
+- * initialization has completed. Use presence of the firmware ID as
+- * indicator for initialization having completed.
+- * The chip also provides a "reset completed" bit, but it's cleared after
+- * read. Therefore function would time out if called again.
+- */
+-static int aqr107_wait_reset_complete(struct phy_device *phydev)
+-{
+-	int val;
+-
+-	return phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+-					 VEND1_GLOBAL_FW_ID, val, val != 0,
+-					 20000, 2000000, false);
+-}
+-
+-static void aqr107_chip_info(struct phy_device *phydev)
+-{
+-	u8 fw_major, fw_minor, build_id, prov_id;
+-	int val;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
+-	if (val < 0)
+-		return;
+-
+-	fw_major = FIELD_GET(VEND1_GLOBAL_FW_ID_MAJOR, val);
+-	fw_minor = FIELD_GET(VEND1_GLOBAL_FW_ID_MINOR, val);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT1);
+-	if (val < 0)
+-		return;
+-
+-	build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
+-	prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
+-
+-	phydev_dbg(phydev, "FW %u.%u, Build %u, Provisioning %u\n",
+-		   fw_major, fw_minor, build_id, prov_id);
+-}
+-
+-static int aqr107_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Check that the PHY interface type is compatible */
+-	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+-	    phydev->interface != PHY_INTERFACE_MODE_1000BASEKX &&
+-	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX &&
+-	    phydev->interface != PHY_INTERFACE_MODE_XGMII &&
+-	    phydev->interface != PHY_INTERFACE_MODE_USXGMII &&
+-	    phydev->interface != PHY_INTERFACE_MODE_10GKR &&
+-	    phydev->interface != PHY_INTERFACE_MODE_10GBASER &&
+-	    phydev->interface != PHY_INTERFACE_MODE_XAUI &&
+-	    phydev->interface != PHY_INTERFACE_MODE_RXAUI)
+-		return -ENODEV;
+-
+-	WARN(phydev->interface == PHY_INTERFACE_MODE_XGMII,
+-	     "Your devicetree is out of date, please update it. The AQR107 family doesn't support XGMII, maybe you mean USXGMII.\n");
+-
+-	ret = aqr107_wait_reset_complete(phydev);
+-	if (!ret)
+-		aqr107_chip_info(phydev);
+-
+-	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+-}
+-
+-static int aqcs109_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Check that the PHY interface type is compatible */
+-	if (phydev->interface != PHY_INTERFACE_MODE_SGMII &&
+-	    phydev->interface != PHY_INTERFACE_MODE_2500BASEX)
+-		return -ENODEV;
+-
+-	ret = aqr107_wait_reset_complete(phydev);
+-	if (!ret)
+-		aqr107_chip_info(phydev);
+-
+-	/* AQCS109 belongs to a chip family partially supporting 10G and 5G.
+-	 * PMA speed ability bits are the same for all members of the family,
+-	 * AQCS109 however supports speeds up to 2.5G only.
+-	 */
+-	ret = phy_set_max_speed(phydev, SPEED_2500);
+-	if (ret)
+-		return ret;
+-
+-	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
+-}
+-
+-static void aqr107_link_change_notify(struct phy_device *phydev)
+-{
+-	u8 fw_major, fw_minor;
+-	bool downshift, short_reach, afr;
+-	int mode, val;
+-
+-	if (phydev->state != PHY_RUNNING || phydev->autoneg == AUTONEG_DISABLE)
+-		return;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT1);
+-	/* call failed or link partner is no Aquantia PHY */
+-	if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))
+-		return;
+-
+-	short_reach = val & MDIO_AN_RX_LP_STAT1_SHORT_REACH;
+-	downshift = val & MDIO_AN_RX_LP_STAT1_AQRATE_DOWNSHIFT;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_LP_STAT4);
+-	if (val < 0)
+-		return;
+-
+-	fw_major = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MAJOR, val);
+-	fw_minor = FIELD_GET(MDIO_AN_RX_LP_STAT4_FW_MINOR, val);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_RX_VEND_STAT3);
+-	if (val < 0)
+-		return;
+-
+-	afr = val & MDIO_AN_RX_VEND_STAT3_AFR;
+-
+-	phydev_dbg(phydev, "Link partner is Aquantia PHY, FW %u.%u%s%s%s\n",
+-		   fw_major, fw_minor,
+-		   short_reach ? ", short reach mode" : "",
+-		   downshift ? ", fast-retrain downshift advertised" : "",
+-		   afr ? ", fast reframe advertised" : "");
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_RSVD_STAT9);
+-	if (val < 0)
+-		return;
+-
+-	mode = FIELD_GET(VEND1_GLOBAL_RSVD_STAT9_MODE, val);
+-	if (mode == VEND1_GLOBAL_RSVD_STAT9_1000BT2)
+-		phydev_info(phydev, "Aquantia 1000Base-T2 mode active\n");
+-}
+-
+-static int aqr107_wait_processor_intensive_op(struct phy_device *phydev)
+-{
+-	int val, err;
+-
+-	/* The datasheet notes to wait at least 1ms after issuing a
+-	 * processor intensive operation before checking.
+-	 * We cannot use the 'sleep_before_read' parameter of read_poll_timeout
+-	 * because that just determines the maximum time slept, not the minimum.
+-	 */
+-	usleep_range(1000, 5000);
+-
+-	err = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
+-					VEND1_GLOBAL_GEN_STAT2, val,
+-					!(val & VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG),
+-					AQR107_OP_IN_PROG_SLEEP,
+-					AQR107_OP_IN_PROG_TIMEOUT, false);
+-	if (err) {
+-		phydev_err(phydev, "timeout: processor-intensive MDIO operation\n");
+-		return err;
+-	}
+-
+-	return 0;
+-}
+-
+-static int aqr107_get_rate_matching(struct phy_device *phydev,
+-				    phy_interface_t iface)
+-{
+-	if (iface == PHY_INTERFACE_MODE_10GBASER ||
+-	    iface == PHY_INTERFACE_MODE_2500BASEX ||
+-	    iface == PHY_INTERFACE_MODE_NA)
+-		return RATE_MATCH_PAUSE;
+-	return RATE_MATCH_NONE;
+-}
+-
+-static int aqr107_suspend(struct phy_device *phydev)
+-{
+-	int err;
+-
+-	err = phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
+-			       MDIO_CTRL1_LPOWER);
+-	if (err)
+-		return err;
+-
+-	return aqr107_wait_processor_intensive_op(phydev);
+-}
+-
+-static int aqr107_resume(struct phy_device *phydev)
+-{
+-	int err;
+-
+-	err = phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MDIO_CTRL1,
+-				 MDIO_CTRL1_LPOWER);
+-	if (err)
+-		return err;
+-
+-	return aqr107_wait_processor_intensive_op(phydev);
+-}
+-
+-static int aqr107_probe(struct phy_device *phydev)
+-{
+-	phydev->priv = devm_kzalloc(&phydev->mdio.dev,
+-				    sizeof(struct aqr107_priv), GFP_KERNEL);
+-	if (!phydev->priv)
+-		return -ENOMEM;
+-
+-	return aqr_hwmon_probe(phydev);
+-}
+-
+-static struct phy_driver aqr_driver[] = {
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQ1202),
+-	.name		= "Aquantia AQ1202",
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr_read_status,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQ2104),
+-	.name		= "Aquantia AQ2104",
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr_read_status,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQR105),
+-	.name		= "Aquantia AQR105",
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr_read_status,
+-	.suspend	= aqr107_suspend,
+-	.resume		= aqr107_resume,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQR106),
+-	.name		= "Aquantia AQR106",
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr_read_status,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQR107),
+-	.name		= "Aquantia AQR107",
+-	.probe		= aqr107_probe,
+-	.get_rate_matching = aqr107_get_rate_matching,
+-	.config_init	= aqr107_config_init,
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr107_read_status,
+-	.get_tunable    = aqr107_get_tunable,
+-	.set_tunable    = aqr107_set_tunable,
+-	.suspend	= aqr107_suspend,
+-	.resume		= aqr107_resume,
+-	.get_sset_count	= aqr107_get_sset_count,
+-	.get_strings	= aqr107_get_strings,
+-	.get_stats	= aqr107_get_stats,
+-	.link_change_notify = aqr107_link_change_notify,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
+-	.name		= "Aquantia AQCS109",
+-	.probe		= aqr107_probe,
+-	.get_rate_matching = aqr107_get_rate_matching,
+-	.config_init	= aqcs109_config_init,
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr107_read_status,
+-	.get_tunable    = aqr107_get_tunable,
+-	.set_tunable    = aqr107_set_tunable,
+-	.suspend	= aqr107_suspend,
+-	.resume		= aqr107_resume,
+-	.get_sset_count	= aqr107_get_sset_count,
+-	.get_strings	= aqr107_get_strings,
+-	.get_stats	= aqr107_get_stats,
+-	.link_change_notify = aqr107_link_change_notify,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQR405),
+-	.name		= "Aquantia AQR405",
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr	= aqr_config_intr,
+-	.handle_interrupt = aqr_handle_interrupt,
+-	.read_status	= aqr_read_status,
+-},
+-{
+-	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
+-	.name           = "Aquantia AQR113C",
+-	.probe          = aqr107_probe,
+-	.get_rate_matching = aqr107_get_rate_matching,
+-	.config_init    = aqr107_config_init,
+-	.config_aneg    = aqr_config_aneg,
+-	.config_intr    = aqr_config_intr,
+-	.handle_interrupt       = aqr_handle_interrupt,
+-	.read_status    = aqr107_read_status,
+-	.get_tunable    = aqr107_get_tunable,
+-	.set_tunable    = aqr107_set_tunable,
+-	.suspend        = aqr107_suspend,
+-	.resume         = aqr107_resume,
+-	.get_sset_count = aqr107_get_sset_count,
+-	.get_strings    = aqr107_get_strings,
+-	.get_stats      = aqr107_get_stats,
+-	.link_change_notify = aqr107_link_change_notify,
+-},
+-};
+-
+-module_phy_driver(aqr_driver);
+-
+-static struct mdio_device_id __maybe_unused aqr_tbl[] = {
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQ1202) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQ2104) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+-	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+-	{ }
+-};
+-
+-MODULE_DEVICE_TABLE(mdio, aqr_tbl);
+-
+-MODULE_DESCRIPTION("Aquantia PHY driver");
+-MODULE_AUTHOR("Shaohui Xie <Shaohui.Xie@freescale.com>");
+-MODULE_LICENSE("GPL v2");
diff --git a/target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch b/target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch
new file mode 100644
index 00000000000..2b945227237
--- /dev/null
+++ b/target/linux/generic/backport-5.15/737-02-v6.7-net-phy-aquantia-move-MMD_VEND-define-to-header.patch
@@ -0,0 +1,183 @@
+From e1fbfa4a995d42e02e22b0dff2f8b4fdee1504b3 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 14 Nov 2023 15:08:42 +0100
+Subject: [PATCH 2/3] net: phy: aquantia: move MMD_VEND define to header
+
+Move MMD_VEND define to header to clean things up and in preparation for
+firmware loading support that require some define placed in
+aquantia_main.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/aquantia.h       | 69 +++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_hwmon.c | 14 -----
+ drivers/net/phy/aquantia/aquantia_main.c  | 55 ------------------
+ 3 files changed, 69 insertions(+), 69 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -9,6 +9,75 @@
+ #include <linux/device.h>
+ #include <linux/phy.h>
+ 
++/* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_FW_ID			0x0020
++#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
++#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
++
++/* The following registers all have similar layouts; first the registers... */
++#define VEND1_GLOBAL_CFG_10M			0x0310
++#define VEND1_GLOBAL_CFG_100M			0x031b
++#define VEND1_GLOBAL_CFG_1G			0x031c
++#define VEND1_GLOBAL_CFG_2_5G			0x031d
++#define VEND1_GLOBAL_CFG_5G			0x031e
++#define VEND1_GLOBAL_CFG_10G			0x031f
++/* ...and now the fields */
++#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
++#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
++
++/* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
++#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
++#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
++#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
++#define VEND1_THERMAL_STAT1			0xc820
++#define VEND1_THERMAL_STAT2			0xc821
++#define VEND1_THERMAL_STAT2_VALID		BIT(0)
++#define VEND1_GENERAL_STAT1			0xc830
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)
++#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)
++#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)
++
++#define VEND1_GLOBAL_GEN_STAT2			0xc831
++#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)
++
++#define VEND1_GLOBAL_RSVD_STAT1			0xc885
++#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
++#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
++
++#define VEND1_GLOBAL_RSVD_STAT9			0xc88d
++#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
++#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
++
++#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
++#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
++
++#define VEND1_GLOBAL_INT_STD_MASK		0xff00
++#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)
++#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)
++#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)
++#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)
++#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)
++#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)
++#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)
++#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
++
++#define VEND1_GLOBAL_INT_VEND_MASK		0xff01
++#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)
++#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)
++#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)
++#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)
++#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
++#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
++
+ #if IS_REACHABLE(CONFIG_HWMON)
+ int aqr_hwmon_probe(struct phy_device *phydev);
+ #else
+--- a/drivers/net/phy/aquantia/aquantia_hwmon.c
++++ b/drivers/net/phy/aquantia/aquantia_hwmon.c
+@@ -13,20 +13,6 @@
+ 
+ #include "aquantia.h"
+ 
+-/* Vendor specific 1, MDIO_MMD_VEND2 */
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
+-#define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
+-#define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
+-#define VEND1_THERMAL_PROV_LOW_TEMP_WARN	0xc424
+-#define VEND1_THERMAL_STAT1			0xc820
+-#define VEND1_THERMAL_STAT2			0xc821
+-#define VEND1_THERMAL_STAT2_VALID		BIT(0)
+-#define VEND1_GENERAL_STAT1			0xc830
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_FAIL	BIT(14)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_FAIL	BIT(13)
+-#define VEND1_GENERAL_STAT1_HIGH_TEMP_WARN	BIT(12)
+-#define VEND1_GENERAL_STAT1_LOW_TEMP_WARN	BIT(11)
+-
+ #if IS_REACHABLE(CONFIG_HWMON)
+ 
+ static umode_t aqr_hwmon_is_visible(const void *data,
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -89,61 +89,6 @@
+ #define MDIO_C22EXT_STAT_SGMII_TX_FRAME_ALIGN_ERR	0xd31a
+ #define MDIO_C22EXT_STAT_SGMII_TX_RUNT_FRAMES		0xd31b
+ 
+-/* Vendor specific 1, MDIO_MMD_VEND1 */
+-#define VEND1_GLOBAL_FW_ID			0x0020
+-#define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
+-#define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
+-
+-#define VEND1_GLOBAL_GEN_STAT2			0xc831
+-#define VEND1_GLOBAL_GEN_STAT2_OP_IN_PROG	BIT(15)
+-
+-/* The following registers all have similar layouts; first the registers... */
+-#define VEND1_GLOBAL_CFG_10M			0x0310
+-#define VEND1_GLOBAL_CFG_100M			0x031b
+-#define VEND1_GLOBAL_CFG_1G			0x031c
+-#define VEND1_GLOBAL_CFG_2_5G			0x031d
+-#define VEND1_GLOBAL_CFG_5G			0x031e
+-#define VEND1_GLOBAL_CFG_10G			0x031f
+-/* ...and now the fields */
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT		GENMASK(8, 7)
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_NONE	0
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_USX		1
+-#define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
+-
+-#define VEND1_GLOBAL_RSVD_STAT1			0xc885
+-#define VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID	GENMASK(7, 4)
+-#define VEND1_GLOBAL_RSVD_STAT1_PROV_ID		GENMASK(3, 0)
+-
+-#define VEND1_GLOBAL_RSVD_STAT9			0xc88d
+-#define VEND1_GLOBAL_RSVD_STAT9_MODE		GENMASK(7, 0)
+-#define VEND1_GLOBAL_RSVD_STAT9_1000BT2		0x23
+-
+-#define VEND1_GLOBAL_INT_STD_STATUS		0xfc00
+-#define VEND1_GLOBAL_INT_VEND_STATUS		0xfc01
+-
+-#define VEND1_GLOBAL_INT_STD_MASK		0xff00
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA1		BIT(15)
+-#define VEND1_GLOBAL_INT_STD_MASK_PMA2		BIT(14)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS1		BIT(13)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS2		BIT(12)
+-#define VEND1_GLOBAL_INT_STD_MASK_PCS3		BIT(11)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS1	BIT(10)
+-#define VEND1_GLOBAL_INT_STD_MASK_PHY_XS2	BIT(9)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN1		BIT(8)
+-#define VEND1_GLOBAL_INT_STD_MASK_AN2		BIT(7)
+-#define VEND1_GLOBAL_INT_STD_MASK_GBE		BIT(6)
+-#define VEND1_GLOBAL_INT_STD_MASK_ALL		BIT(0)
+-
+-#define VEND1_GLOBAL_INT_VEND_MASK		0xff01
+-#define VEND1_GLOBAL_INT_VEND_MASK_PMA		BIT(15)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PCS		BIT(14)
+-#define VEND1_GLOBAL_INT_VEND_MASK_PHY_XS	BIT(13)
+-#define VEND1_GLOBAL_INT_VEND_MASK_AN		BIT(12)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GBE		BIT(11)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL1	BIT(2)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL2	BIT(1)
+-#define VEND1_GLOBAL_INT_VEND_MASK_GLOBAL3	BIT(0)
+-
+ /* Sleep and timeout for checking if the Processor-Intensive
+  * MDIO operation is finished
+  */
diff --git a/target/linux/generic/backport-5.15/737-03-v6.7-net-phy-aquantia-add-firmware-load-support.patch b/target/linux/generic/backport-5.15/737-03-v6.7-net-phy-aquantia-add-firmware-load-support.patch
new file mode 100644
index 00000000000..1ae5966df6c
--- /dev/null
+++ b/target/linux/generic/backport-5.15/737-03-v6.7-net-phy-aquantia-add-firmware-load-support.patch
@@ -0,0 +1,504 @@
+From e93984ebc1c82bd34f7a1b3391efaceee0a8ae96 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Tue, 14 Nov 2023 15:08:43 +0100
+Subject: [PATCH 3/3] net: phy: aquantia: add firmware load support
+
+Aquantia PHY-s require firmware to be loaded before they start operating.
+It can be automatically loaded in case when there is a SPI-NOR connected
+to Aquantia PHY-s or can be loaded from the host via MDIO.
+
+This patch adds support for loading the firmware via MDIO as in most cases
+there is no SPI-NOR being used to save on cost.
+Firmware loading code itself is ported from mainline U-boot with cleanups.
+
+The firmware has mixed values both in big and little endian.
+PHY core itself is big-endian but it expects values to be in little-endian.
+The firmware is little-endian but CRC-16 value for it is stored at the end
+of firmware in big-endian.
+
+It seems the PHY does the conversion internally from firmware that is
+little-endian to the PHY that is big-endian on using the mailbox
+but mailbox returns a big-endian CRC-16 to verify the written data
+integrity.
+
+Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/aquantia/Kconfig             |   1 +
+ drivers/net/phy/aquantia/Makefile            |   2 +-
+ drivers/net/phy/aquantia/aquantia.h          |  32 ++
+ drivers/net/phy/aquantia/aquantia_firmware.c | 370 +++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c     |   6 +
+ 5 files changed, 410 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/net/phy/aquantia/aquantia_firmware.c
+
+--- a/drivers/net/phy/aquantia/Kconfig
++++ b/drivers/net/phy/aquantia/Kconfig
+@@ -1,5 +1,6 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ config AQUANTIA_PHY
+ 	tristate "Aquantia PHYs"
++	select CRC_CCITT
+ 	help
+ 	  Currently supports the Aquantia AQ1202, AQ2104, AQR105, AQR405
+--- a/drivers/net/phy/aquantia/Makefile
++++ b/drivers/net/phy/aquantia/Makefile
+@@ -1,5 +1,5 @@
+ # SPDX-License-Identifier: GPL-2.0
+-aquantia-objs			+= aquantia_main.o
++aquantia-objs			+= aquantia_main.o aquantia_firmware.o
+ ifdef CONFIG_HWMON
+ aquantia-objs			+= aquantia_hwmon.o
+ endif
+--- a/drivers/net/phy/aquantia/aquantia.h
++++ b/drivers/net/phy/aquantia/aquantia.h
+@@ -10,10 +10,35 @@
+ #include <linux/phy.h>
+ 
+ /* Vendor specific 1, MDIO_MMD_VEND1 */
++#define VEND1_GLOBAL_SC				0x0
++#define VEND1_GLOBAL_SC_SOFT_RESET		BIT(15)
++#define VEND1_GLOBAL_SC_LOW_POWER		BIT(11)
++
+ #define VEND1_GLOBAL_FW_ID			0x0020
+ #define VEND1_GLOBAL_FW_ID_MAJOR		GENMASK(15, 8)
+ #define VEND1_GLOBAL_FW_ID_MINOR		GENMASK(7, 0)
+ 
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1			0x0200
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE		BIT(15)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE		BIT(14)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET	BIT(12)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE1_BUSY		BIT(8)
++
++#define VEND1_GLOBAL_MAILBOX_INTERFACE2			0x0201
++#define VEND1_GLOBAL_MAILBOX_INTERFACE3			0x0202
++#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK	GENMASK(15, 0)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR_MASK, (u16)((x) >> 16))
++#define VEND1_GLOBAL_MAILBOX_INTERFACE4			0x0203
++#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK	GENMASK(15, 2)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR_MASK, (u16)(x))
++
++#define VEND1_GLOBAL_MAILBOX_INTERFACE5			0x0204
++#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK	GENMASK(15, 0)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA_MASK, (u16)((x) >> 16))
++#define VEND1_GLOBAL_MAILBOX_INTERFACE6			0x0205
++#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK	GENMASK(15, 0)
++#define VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(x)	FIELD_PREP(VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA_MASK, (u16)(x))
++
+ /* The following registers all have similar layouts; first the registers... */
+ #define VEND1_GLOBAL_CFG_10M			0x0310
+ #define VEND1_GLOBAL_CFG_100M			0x031b
+@@ -28,6 +53,11 @@
+ #define VEND1_GLOBAL_CFG_RATE_ADAPT_PAUSE	2
+ 
+ /* Vendor specific 1, MDIO_MMD_VEND2 */
++#define VEND1_GLOBAL_CONTROL2			0xc001
++#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST	BIT(15)
++#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD	BIT(6)
++#define VEND1_GLOBAL_CONTROL2_UP_RUN_STALL	BIT(0)
++
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_FAIL	0xc421
+ #define VEND1_THERMAL_PROV_LOW_TEMP_FAIL	0xc422
+ #define VEND1_THERMAL_PROV_HIGH_TEMP_WARN	0xc423
+@@ -83,3 +113,5 @@ int aqr_hwmon_probe(struct phy_device *p
+ #else
+ static inline int aqr_hwmon_probe(struct phy_device *phydev) { return 0; }
+ #endif
++
++int aqr_firmware_load(struct phy_device *phydev);
+--- /dev/null
++++ b/drivers/net/phy/aquantia/aquantia_firmware.c
+@@ -0,0 +1,370 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/bitfield.h>
++#include <linux/of.h>
++#include <linux/firmware.h>
++#include <linux/crc-ccitt.h>
++#include <linux/nvmem-consumer.h>
++
++#include <asm/unaligned.h>
++
++#include "aquantia.h"
++
++#define UP_RESET_SLEEP		100
++
++/* addresses of memory segments in the phy */
++#define DRAM_BASE_ADDR		0x3FFE0000
++#define IRAM_BASE_ADDR		0x40000000
++
++/* firmware image format constants */
++#define VERSION_STRING_SIZE		0x40
++#define VERSION_STRING_OFFSET		0x0200
++/* primary offset is written at an offset from the start of the fw blob */
++#define PRIMARY_OFFSET_OFFSET		0x8
++/* primary offset needs to be then added to a base offset */
++#define PRIMARY_OFFSET_SHIFT		12
++#define PRIMARY_OFFSET(x)		((x) << PRIMARY_OFFSET_SHIFT)
++#define HEADER_OFFSET			0x300
++
++struct aqr_fw_header {
++	u32 padding;
++	u8 iram_offset[3];
++	u8 iram_size[3];
++	u8 dram_offset[3];
++	u8 dram_size[3];
++} __packed;
++
++enum aqr_fw_src {
++	AQR_FW_SRC_NVMEM = 0,
++	AQR_FW_SRC_FS,
++};
++
++static const char * const aqr_fw_src_string[] = {
++	[AQR_FW_SRC_NVMEM] = "NVMEM",
++	[AQR_FW_SRC_FS] = "FS",
++};
++
++/* AQR firmware doesn't have fixed offsets for iram and dram section
++ * but instead provide an header with the offset to use on reading
++ * and parsing the firmware.
++ *
++ * AQR firmware can't be trusted and each offset is validated to be
++ * not negative and be in the size of the firmware itself.
++ */
++static bool aqr_fw_validate_get(size_t size, size_t offset, size_t get_size)
++{
++	return offset + get_size <= size;
++}
++
++static int aqr_fw_get_be16(const u8 *data, size_t offset, size_t size, u16 *value)
++{
++	if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
++		return -EINVAL;
++
++	*value = get_unaligned_be16(data + offset);
++
++	return 0;
++}
++
++static int aqr_fw_get_le16(const u8 *data, size_t offset, size_t size, u16 *value)
++{
++	if (!aqr_fw_validate_get(size, offset, sizeof(u16)))
++		return -EINVAL;
++
++	*value = get_unaligned_le16(data + offset);
++
++	return 0;
++}
++
++static int aqr_fw_get_le24(const u8 *data, size_t offset, size_t size, u32 *value)
++{
++	if (!aqr_fw_validate_get(size, offset, sizeof(u8) * 3))
++		return -EINVAL;
++
++	*value = get_unaligned_le24(data + offset);
++
++	return 0;
++}
++
++/* load data into the phy's memory */
++static int aqr_fw_load_memory(struct phy_device *phydev, u32 addr,
++			      const u8 *data, size_t len)
++{
++	u16 crc = 0, up_crc;
++	size_t pos;
++
++	/* PHY expect addr in LE */
++	addr = (__force u32)cpu_to_le32(addr);
++
++	phy_write_mmd(phydev, MDIO_MMD_VEND1,
++		      VEND1_GLOBAL_MAILBOX_INTERFACE1,
++		      VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
++	phy_write_mmd(phydev, MDIO_MMD_VEND1,
++		      VEND1_GLOBAL_MAILBOX_INTERFACE3,
++		      VEND1_GLOBAL_MAILBOX_INTERFACE3_MSW_ADDR(addr));
++	phy_write_mmd(phydev, MDIO_MMD_VEND1,
++		      VEND1_GLOBAL_MAILBOX_INTERFACE4,
++		      VEND1_GLOBAL_MAILBOX_INTERFACE4_LSW_ADDR(addr));
++
++	/* We assume and enforce the size to be word aligned.
++	 * If a firmware that is not word aligned is found, please report upstream.
++	 */
++	for (pos = 0; pos < len; pos += sizeof(u32)) {
++		u32 word;
++
++		/* FW data is always stored in little-endian */
++		word = get_unaligned((const u32 *)(data + pos));
++
++		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
++			      VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
++		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE6,
++			      VEND1_GLOBAL_MAILBOX_INTERFACE6_LSW_DATA(word));
++
++		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE1,
++			      VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
++			      VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
++
++		/* calculate CRC as we load data to the mailbox.
++		 * We convert word to big-endian as PHY is BE and mailbox will
++		 * return a BE CRC.
++		 */
++		word = (__force u32)cpu_to_be32(word);
++		crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
++	}
++
++	up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
++	if (crc != up_crc) {
++		phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
++			   crc, up_crc);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int aqr_fw_boot(struct phy_device *phydev, const u8 *data, size_t size,
++		       enum aqr_fw_src fw_src)
++{
++	u16 calculated_crc, read_crc, read_primary_offset;
++	u32 iram_offset = 0, iram_size = 0;
++	u32 dram_offset = 0, dram_size = 0;
++	char version[VERSION_STRING_SIZE];
++	u32 primary_offset = 0;
++	int ret;
++
++	/* extract saved CRC at the end of the fw
++	 * CRC is saved in big-endian as PHY is BE
++	 */
++	ret = aqr_fw_get_be16(data, size - sizeof(u16), size, &read_crc);
++	if (ret) {
++		phydev_err(phydev, "bad firmware CRC in firmware\n");
++		return ret;
++	}
++	calculated_crc = crc_ccitt_false(0, data, size - sizeof(u16));
++	if (read_crc != calculated_crc) {
++		phydev_err(phydev, "bad firmware CRC: file 0x%04x calculated 0x%04x\n",
++			   read_crc, calculated_crc);
++		return -EINVAL;
++	}
++
++	/* Get the primary offset to extract DRAM and IRAM sections. */
++	ret = aqr_fw_get_le16(data, PRIMARY_OFFSET_OFFSET, size, &read_primary_offset);
++	if (ret) {
++		phydev_err(phydev, "bad primary offset in firmware\n");
++		return ret;
++	}
++	primary_offset = PRIMARY_OFFSET(read_primary_offset);
++
++	/* Find the DRAM and IRAM sections within the firmware file.
++	 * Make sure the fw_header is correctly in the firmware.
++	 */
++	if (!aqr_fw_validate_get(size, primary_offset + HEADER_OFFSET,
++				 sizeof(struct aqr_fw_header))) {
++		phydev_err(phydev, "bad fw_header in firmware\n");
++		return -EINVAL;
++	}
++
++	/* offset are in LE and values needs to be converted to cpu endian */
++	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++			      offsetof(struct aqr_fw_header, iram_offset),
++			      size, &iram_offset);
++	if (ret) {
++		phydev_err(phydev, "bad iram offset in firmware\n");
++		return ret;
++	}
++	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++			      offsetof(struct aqr_fw_header, iram_size),
++			      size, &iram_size);
++	if (ret) {
++		phydev_err(phydev, "invalid iram size in firmware\n");
++		return ret;
++	}
++	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++			      offsetof(struct aqr_fw_header, dram_offset),
++			      size, &dram_offset);
++	if (ret) {
++		phydev_err(phydev, "bad dram offset in firmware\n");
++		return ret;
++	}
++	ret = aqr_fw_get_le24(data, primary_offset + HEADER_OFFSET +
++			      offsetof(struct aqr_fw_header, dram_size),
++			      size, &dram_size);
++	if (ret) {
++		phydev_err(phydev, "invalid dram size in firmware\n");
++		return ret;
++	}
++
++	/* Increment the offset with the primary offset.
++	 * Validate iram/dram offset and size.
++	 */
++	iram_offset += primary_offset;
++	if (iram_size % sizeof(u32)) {
++		phydev_err(phydev, "iram size if not aligned to word size. Please report this upstream!\n");
++		return -EINVAL;
++	}
++	if (!aqr_fw_validate_get(size, iram_offset, iram_size)) {
++		phydev_err(phydev, "invalid iram offset for iram size\n");
++		return -EINVAL;
++	}
++
++	dram_offset += primary_offset;
++	if (dram_size % sizeof(u32)) {
++		phydev_err(phydev, "dram size if not aligned to word size. Please report this upstream!\n");
++		return -EINVAL;
++	}
++	if (!aqr_fw_validate_get(size, dram_offset, dram_size)) {
++		phydev_err(phydev, "invalid iram offset for iram size\n");
++		return -EINVAL;
++	}
++
++	phydev_dbg(phydev, "primary %d IRAM offset=%d size=%d DRAM offset=%d size=%d\n",
++		   primary_offset, iram_offset, iram_size, dram_offset, dram_size);
++
++	if (!aqr_fw_validate_get(size, dram_offset + VERSION_STRING_OFFSET,
++				 VERSION_STRING_SIZE)) {
++		phydev_err(phydev, "invalid version in firmware\n");
++		return -EINVAL;
++	}
++	strscpy(version, (char *)data + dram_offset + VERSION_STRING_OFFSET,
++		VERSION_STRING_SIZE);
++	if (version[0] == '\0') {
++		phydev_err(phydev, "invalid version in firmware\n");
++		return -EINVAL;
++	}
++	phydev_info(phydev, "loading firmware version '%s' from '%s'\n", version,
++		    aqr_fw_src_string[fw_src]);
++
++	/* stall the microcprocessor */
++	phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
++		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL | VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
++
++	phydev_dbg(phydev, "loading DRAM 0x%08x from offset=%d size=%d\n",
++		   DRAM_BASE_ADDR, dram_offset, dram_size);
++	ret = aqr_fw_load_memory(phydev, DRAM_BASE_ADDR, data + dram_offset,
++				 dram_size);
++	if (ret)
++		return ret;
++
++	phydev_dbg(phydev, "loading IRAM 0x%08x from offset=%d size=%d\n",
++		   IRAM_BASE_ADDR, iram_offset, iram_size);
++	ret = aqr_fw_load_memory(phydev, IRAM_BASE_ADDR, data + iram_offset,
++				 iram_size);
++	if (ret)
++		return ret;
++
++	/* make sure soft reset and low power mode are clear */
++	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_SC,
++			   VEND1_GLOBAL_SC_SOFT_RESET | VEND1_GLOBAL_SC_LOW_POWER);
++
++	/* Release the microprocessor. UP_RESET must be held for 100 usec. */
++	phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
++		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL |
++		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD |
++		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_RST);
++	usleep_range(UP_RESET_SLEEP, UP_RESET_SLEEP * 2);
++
++	phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_CONTROL2,
++		      VEND1_GLOBAL_CONTROL2_UP_RUN_STALL_OVD);
++
++	return 0;
++}
++
++static int aqr_firmware_load_nvmem(struct phy_device *phydev)
++{
++	struct nvmem_cell *cell;
++	size_t size;
++	u8 *buf;
++	int ret;
++
++	cell = nvmem_cell_get(&phydev->mdio.dev, "firmware");
++	if (IS_ERR(cell))
++		return PTR_ERR(cell);
++
++	buf = nvmem_cell_read(cell, &size);
++	if (IS_ERR(buf)) {
++		ret = PTR_ERR(buf);
++		goto exit;
++	}
++
++	ret = aqr_fw_boot(phydev, buf, size, AQR_FW_SRC_NVMEM);
++	if (ret)
++		phydev_err(phydev, "firmware loading failed: %d\n", ret);
++
++	kfree(buf);
++exit:
++	nvmem_cell_put(cell);
++
++	return ret;
++}
++
++static int aqr_firmware_load_fs(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	const struct firmware *fw;
++	const char *fw_name;
++	int ret;
++
++	ret = of_property_read_string(dev->of_node, "firmware-name",
++				      &fw_name);
++	if (ret)
++		return ret;
++
++	ret = request_firmware(&fw, fw_name, dev);
++	if (ret) {
++		phydev_err(phydev, "failed to find FW file %s (%d)\n",
++			   fw_name, ret);
++		return ret;
++	}
++
++	ret = aqr_fw_boot(phydev, fw->data, fw->size, AQR_FW_SRC_FS);
++	if (ret)
++		phydev_err(phydev, "firmware loading failed: %d\n", ret);
++
++	release_firmware(fw);
++
++	return ret;
++}
++
++int aqr_firmware_load(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Check if the firmware is not already loaded by pooling
++	 * the current version returned by the PHY. If 0 is returned,
++	 * no firmware is loaded.
++	 */
++	ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_FW_ID);
++	if (ret > 0)
++		goto exit;
++
++	ret = aqr_firmware_load_nvmem(phydev);
++	if (!ret)
++		goto exit;
++
++	ret = aqr_firmware_load_fs(phydev);
++	if (ret)
++		return ret;
++
++exit:
++	return 0;
++}
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -658,11 +658,17 @@ static int aqr107_resume(struct phy_devi
+ 
+ static int aqr107_probe(struct phy_device *phydev)
+ {
++	int ret;
++
+ 	phydev->priv = devm_kzalloc(&phydev->mdio.dev,
+ 				    sizeof(struct aqr107_priv), GFP_KERNEL);
+ 	if (!phydev->priv)
+ 		return -ENOMEM;
+ 
++	ret = aqr_firmware_load(phydev);
++	if (ret)
++		return ret;
++
+ 	return aqr_hwmon_probe(phydev);
+ }
+ 
diff --git a/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch b/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
index d1d692002d1..40f27d4febf 100644
--- a/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
+++ b/target/linux/generic/backport-5.15/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
@@ -530,7 +530,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				pse_port = 8;
 --- a/drivers/net/ethernet/mediatek/mtk_wed.c
 +++ b/drivers/net/ethernet/mediatek/mtk_wed.c
-@@ -1091,7 +1091,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+@@ -1084,7 +1084,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
  	} else {
  		struct mtk_eth *eth = dev->hw->eth;
  
@@ -539,7 +539,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			wed_set(dev, MTK_WED_RESET_IDX,
  				MTK_WED_RESET_IDX_RX_V2);
  		else
-@@ -1813,7 +1813,7 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1806,7 +1806,7 @@ void mtk_wed_add_hw(struct device_node *
  	hw->wdma = wdma;
  	hw->index = index;
  	hw->irq = irq;
diff --git a/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch b/target/linux/generic/backport-5.15/751-01-v6.4-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
similarity index 94%
rename from target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
rename to target/linux/generic/backport-5.15/751-01-v6.4-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
index caee22d2e9e..21d0f045d9f 100644
--- a/target/linux/generic/pending-5.15/736-01-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
+++ b/target/linux/generic/backport-5.15/751-01-v6.4-net-ethernet-mtk_eth_soc-add-code-for-offloading-flo.patch
@@ -11,10 +11,15 @@ PPE device.
 
 Signed-off-by: Felix Fietkau <nbd@nbd.name>
 ---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h   |   3 +
+ .../net/ethernet/mediatek/mtk_ppe_offload.c   |  37 ++++---
+ drivers/net/ethernet/mediatek/mtk_wed.c       | 101 ++++++++++++++++++
+ include/linux/soc/mediatek/mtk_wed.h          |   6 ++
+ 4 files changed, 133 insertions(+), 14 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -1448,6 +1448,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
+@@ -1432,6 +1432,9 @@ int mtk_gmac_rgmii_path_setup(struct mtk
  int mtk_eth_offload_init(struct mtk_eth *eth);
  int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
  		     void *type_data);
@@ -120,7 +125,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static void
  wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
  {
-@@ -1760,6 +1767,99 @@ out:
+@@ -1753,6 +1760,99 @@ out:
  	mutex_unlock(&hw_lock);
  }
  
@@ -220,7 +225,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
  		    void __iomem *wdma, phys_addr_t wdma_phy,
  		    int index)
-@@ -1779,6 +1879,7 @@ void mtk_wed_add_hw(struct device_node *
+@@ -1772,6 +1872,7 @@ void mtk_wed_add_hw(struct device_node *
  		.irq_set_mask = mtk_wed_irq_set_mask,
  		.detach = mtk_wed_detach,
  		.ppe_check = mtk_wed_ppe_check,
diff --git a/target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch b/target/linux/generic/backport-5.15/751-02-v6.4-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch
similarity index 94%
rename from target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch
rename to target/linux/generic/backport-5.15/751-02-v6.4-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch
index e89d4cd97b9..84b768bd798 100644
--- a/target/linux/generic/pending-5.15/736-02-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch
+++ b/target/linux/generic/backport-5.15/751-02-v6.4-net-ethernet-mediatek-mtk_ppe-prefer-newly-added-l2-.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -663,10 +663,20 @@ void mtk_foe_entry_clear(struct mtk_ppe
+@@ -662,10 +662,20 @@ void mtk_foe_entry_clear(struct mtk_ppe
  static int
  mtk_foe_entry_commit_l2(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
  {
diff --git a/target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch b/target/linux/generic/backport-5.15/751-03-v6.4-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch
similarity index 92%
rename from target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch
rename to target/linux/generic/backport-5.15/751-03-v6.4-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch
index c8be7a9e2b2..a9f82ca3cb6 100644
--- a/target/linux/generic/pending-5.15/736-03-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch
+++ b/target/linux/generic/backport-5.15/751-03-v6.4-net-ethernet-mtk_eth_soc-improve-keeping-track-of-of.patch
@@ -9,10 +9,13 @@ flow accounting support.
 
 Signed-off-by: Felix Fietkau <nbd@nbd.name>
 ---
+ drivers/net/ethernet/mediatek/mtk_ppe.c | 162 ++++++++++++------------
+ drivers/net/ethernet/mediatek/mtk_ppe.h |  15 +--
+ 2 files changed, 86 insertions(+), 91 deletions(-)
 
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -483,42 +483,43 @@ int mtk_foe_entry_set_queue(struct mtk_e
+@@ -482,42 +482,43 @@ int mtk_foe_entry_set_queue(struct mtk_e
  	return 0;
  }
  
@@ -72,7 +75,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		struct mtk_foe_entry *hwe = mtk_foe_get_entry(ppe, entry->hash);
  
  		hwe->ib1 &= ~MTK_FOE_IB1_STATE;
-@@ -538,7 +539,8 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
+@@ -537,7 +538,8 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
  	if (entry->type != MTK_FLOW_TYPE_L2_SUBFLOW)
  		return;
  
@@ -82,7 +85,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	kfree(entry);
  }
  
-@@ -554,66 +556,55 @@ static int __mtk_foe_entry_idle_time(str
+@@ -553,66 +555,55 @@ static int __mtk_foe_entry_idle_time(str
  		return now - timestamp;
  }
  
@@ -178,7 +181,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static void
-@@ -656,7 +647,8 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -655,7 +646,8 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  void mtk_foe_entry_clear(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
  {
  	spin_lock_bh(&ppe_lock);
@@ -188,7 +191,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	spin_unlock_bh(&ppe_lock);
  }
  
-@@ -703,8 +695,8 @@ mtk_foe_entry_commit_subflow(struct mtk_
+@@ -702,8 +694,8 @@ mtk_foe_entry_commit_subflow(struct mtk_
  {
  	const struct mtk_soc_data *soc = ppe->eth->soc;
  	struct mtk_flow_entry *flow_info;
@@ -198,7 +201,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	u32 ib1_mask = mtk_get_ib1_pkt_type_mask(ppe->eth) | MTK_FOE_IB1_UDP;
  	int type;
  
-@@ -712,30 +704,30 @@ mtk_foe_entry_commit_subflow(struct mtk_
+@@ -711,30 +703,30 @@ mtk_foe_entry_commit_subflow(struct mtk_
  	if (!flow_info)
  		return;
  
@@ -239,7 +242,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  void __mtk_ppe_check_skb(struct mtk_ppe *ppe, struct sk_buff *skb, u16 hash)
-@@ -745,9 +737,11 @@ void __mtk_ppe_check_skb(struct mtk_ppe
+@@ -744,9 +736,11 @@ void __mtk_ppe_check_skb(struct mtk_ppe
  	struct mtk_foe_entry *hwe = mtk_foe_get_entry(ppe, hash);
  	struct mtk_flow_entry *entry;
  	struct mtk_foe_bridge key = {};
@@ -251,7 +254,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	u8 *tag;
  
  	spin_lock_bh(&ppe_lock);
-@@ -755,20 +749,14 @@ void __mtk_ppe_check_skb(struct mtk_ppe
+@@ -754,20 +748,14 @@ void __mtk_ppe_check_skb(struct mtk_ppe
  	if (FIELD_GET(MTK_FOE_IB1_STATE, hwe->ib1) == MTK_FOE_STATE_BIND)
  		goto out;
  
@@ -278,7 +281,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			continue;
  		}
  
-@@ -819,9 +807,17 @@ out:
+@@ -816,9 +804,17 @@ out:
  
  int mtk_foe_entry_idle_time(struct mtk_ppe *ppe, struct mtk_flow_entry *entry)
  {
diff --git a/target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch b/target/linux/generic/backport-5.15/751-04-v6.4-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch
similarity index 93%
rename from target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch
rename to target/linux/generic/backport-5.15/751-04-v6.4-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch
index 983b77d6097..2ea6d341b06 100644
--- a/target/linux/generic/pending-5.15/736-04-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch
+++ b/target/linux/generic/backport-5.15/751-04-v6.4-net-ethernet-mediatek-fix-ppe-flow-accounting-for-L2.patch
@@ -14,7 +14,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_ppe.c
 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
-@@ -80,9 +80,9 @@ static int mtk_ppe_mib_wait_busy(struct
+@@ -79,9 +79,9 @@ static int mtk_ppe_mib_wait_busy(struct
  	int ret;
  	u32 val;
  
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (ret)
  		dev_err(ppe->dev, "MIB table busy");
-@@ -90,17 +90,31 @@ static int mtk_ppe_mib_wait_busy(struct
+@@ -89,17 +89,31 @@ static int mtk_ppe_mib_wait_busy(struct
  	return ret;
  }
  
@@ -61,7 +61,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	cnt_r0 = readl(ppe->base + MTK_PPE_MIB_SER_R0);
  	cnt_r1 = readl(ppe->base + MTK_PPE_MIB_SER_R1);
-@@ -109,19 +123,19 @@ static int mtk_mib_entry_read(struct mtk
+@@ -108,19 +122,19 @@ static int mtk_mib_entry_read(struct mtk
  	if (mtk_is_netsys_v3_or_greater(ppe->eth)) {
  		/* 64 bit for each counter */
  		u32 cnt_r3 = readl(ppe->base + MTK_PPE_MIB_SER_R3);
@@ -86,7 +86,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
-@@ -526,13 +540,6 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
+@@ -525,13 +539,6 @@ __mtk_foe_entry_clear(struct mtk_ppe *pp
  		hwe->ib1 |= FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_INVALID);
  		dma_wmb();
  		mtk_ppe_cache_clear(ppe);
@@ -100,7 +100,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  	entry->hash = 0xffff;
  
-@@ -557,11 +564,14 @@ static int __mtk_foe_entry_idle_time(str
+@@ -556,11 +563,14 @@ static int __mtk_foe_entry_idle_time(str
  }
  
  static bool
@@ -116,7 +116,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	int len;
  
  	if (hash == 0xffff)
-@@ -572,18 +582,35 @@ mtk_flow_entry_update(struct mtk_ppe *pp
+@@ -571,18 +581,35 @@ mtk_flow_entry_update(struct mtk_ppe *pp
  	memcpy(&foe, hwe, len);
  
  	if (!mtk_flow_entry_match(ppe->eth, entry, &foe, len) ||
@@ -155,7 +155,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct mtk_flow_entry *cur;
  	struct hlist_node *tmp;
  	int idle;
-@@ -592,7 +619,9 @@ mtk_flow_entry_update_l2(struct mtk_ppe
+@@ -591,7 +618,9 @@ mtk_flow_entry_update_l2(struct mtk_ppe
  	hlist_for_each_entry_safe(cur, tmp, &entry->l2_flows, l2_list) {
  		int cur_idle;
  
@@ -166,7 +166,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			__mtk_foe_entry_clear(ppe, entry, false);
  			continue;
  		}
-@@ -607,10 +636,29 @@ mtk_flow_entry_update_l2(struct mtk_ppe
+@@ -606,10 +635,29 @@ mtk_flow_entry_update_l2(struct mtk_ppe
  	}
  }
  
@@ -196,7 +196,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct mtk_eth *eth = ppe->eth;
  	u16 timestamp = mtk_eth_timestamp(eth);
  	struct mtk_foe_entry *hwe;
-@@ -641,6 +689,12 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
+@@ -640,6 +688,12 @@ __mtk_foe_entry_commit(struct mtk_ppe *p
  
  	dma_wmb();
  
@@ -209,7 +209,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	mtk_ppe_cache_clear(ppe);
  }
  
-@@ -805,21 +859,6 @@ out:
+@@ -802,21 +856,6 @@ out:
  	spin_unlock_bh(&ppe_lock);
  }
  
@@ -231,7 +231,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  int mtk_ppe_prepare_reset(struct mtk_ppe *ppe)
  {
  	if (!ppe)
-@@ -847,32 +886,6 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
+@@ -844,32 +883,6 @@ int mtk_ppe_prepare_reset(struct mtk_ppe
  	return mtk_ppe_wait_busy(ppe);
  }
  
diff --git a/target/linux/generic/backport-5.15/752-01-v6.6-net-ethernet-mtk_wed-add-some-more-info-in-wed_txinf.patch b/target/linux/generic/backport-5.15/752-01-v6.6-net-ethernet-mtk_wed-add-some-more-info-in-wed_txinf.patch
new file mode 100644
index 00000000000..a224b626243
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-01-v6.6-net-ethernet-mtk_wed-add-some-more-info-in-wed_txinf.patch
@@ -0,0 +1,45 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sun, 27 Aug 2023 19:31:41 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: add some more info in wed_txinfo_show
+ handler
+
+Add some new info in Wireless Ethernet Dispatcher wed_txinfo_show
+debugfs handler useful during debugging.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/3390292655d568180b73d2a25576f61aa63310e5.1693157377.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
+@@ -127,8 +127,17 @@ wed_txinfo_show(struct seq_file *s, void
+ 		DUMP_WDMA_RING(WDMA_RING_RX(0)),
+ 		DUMP_WDMA_RING(WDMA_RING_RX(1)),
+ 
+-		DUMP_STR("TX FREE"),
++		DUMP_STR("WED TX FREE"),
+ 		DUMP_WED(WED_RX_MIB(0)),
++		DUMP_WED_RING(WED_RING_RX(0)),
++		DUMP_WED(WED_WPDMA_RX_COHERENT_MIB(0)),
++		DUMP_WED(WED_RX_MIB(1)),
++		DUMP_WED_RING(WED_RING_RX(1)),
++		DUMP_WED(WED_WPDMA_RX_COHERENT_MIB(1)),
++
++		DUMP_STR("WED WPDMA TX FREE"),
++		DUMP_WED_RING(WED_WPDMA_RING_RX(0)),
++		DUMP_WED_RING(WED_WPDMA_RING_RX(1)),
+ 	};
+ 	struct mtk_wed_hw *hw = s->private;
+ 	struct mtk_wed_device *dev = hw->wed_dev;
+--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
+@@ -266,6 +266,8 @@ struct mtk_wdma_desc {
+ 
+ #define MTK_WED_WPDMA_TX_MIB(_n)			(0x5a0 + (_n) * 4)
+ #define MTK_WED_WPDMA_TX_COHERENT_MIB(_n)		(0x5d0 + (_n) * 4)
++#define MTK_WED_WPDMA_RX_MIB(_n)			(0x5e0 + (_n) * 4)
++#define MTK_WED_WPDMA_RX_COHERENT_MIB(_n)		(0x5f0 + (_n) * 4)
+ 
+ #define MTK_WED_WPDMA_RING_TX(_n)			(0x600 + (_n) * 0x10)
+ #define MTK_WED_WPDMA_RING_RX(_n)			(0x700 + (_n) * 0x10)
diff --git a/target/linux/generic/backport-5.15/752-02-v6.6-net-ethernet-mtk_wed-minor-change-in-wed_-tx-rx-info.patch b/target/linux/generic/backport-5.15/752-02-v6.6-net-ethernet-mtk_wed-minor-change-in-wed_-tx-rx-info.patch
new file mode 100644
index 00000000000..df6edfdf943
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-02-v6.6-net-ethernet-mtk_wed-minor-change-in-wed_-tx-rx-info.patch
@@ -0,0 +1,47 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Sun, 27 Aug 2023 19:33:47 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: minor change in wed_{tx,rx}info_show
+
+No functional changes, just cosmetic ones.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Link: https://lore.kernel.org/r/71e046c72a978745f0435af265dda610aa9bfbcf.1693157578.git.lorenzo@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
+@@ -84,7 +84,6 @@ dump_wed_regs(struct seq_file *s, struct
+ 	}
+ }
+ 
+-
+ static int
+ wed_txinfo_show(struct seq_file *s, void *data)
+ {
+@@ -142,10 +141,8 @@ wed_txinfo_show(struct seq_file *s, void
+ 	struct mtk_wed_hw *hw = s->private;
+ 	struct mtk_wed_device *dev = hw->wed_dev;
+ 
+-	if (!dev)
+-		return 0;
+-
+-	dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
++	if (dev)
++		dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
+ 
+ 	return 0;
+ }
+@@ -217,10 +214,8 @@ wed_rxinfo_show(struct seq_file *s, void
+ 	struct mtk_wed_hw *hw = s->private;
+ 	struct mtk_wed_device *dev = hw->wed_dev;
+ 
+-	if (!dev)
+-		return 0;
+-
+-	dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
++	if (dev)
++		dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
+ 
+ 	return 0;
+ }
diff --git a/target/linux/generic/backport-5.15/752-03-v6.6-net-ethernet-mtk_eth_soc-rely-on-mtk_pse_port-defini.patch b/target/linux/generic/backport-5.15/752-03-v6.6-net-ethernet-mtk_eth_soc-rely-on-mtk_pse_port-defini.patch
new file mode 100644
index 00000000000..0bf9dea24f0
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-03-v6.6-net-ethernet-mtk_eth_soc-rely-on-mtk_pse_port-defini.patch
@@ -0,0 +1,29 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 12 Sep 2023 10:22:56 +0200
+Subject: [PATCH] net: ethernet: mtk_eth_soc: rely on mtk_pse_port definitions
+ in mtk_flow_set_output_device
+
+Similar to ethernet ports, rely on mtk_pse_port definitions for
+pse wdma ports as well.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/b86bdb717e963e3246c1dec5f736c810703cf056.1694506814.git.lorenzo@kernel.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -196,10 +196,10 @@ mtk_flow_set_output_device(struct mtk_et
+ 		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			switch (info.wdma_idx) {
+ 			case 0:
+-				pse_port = 8;
++				pse_port = PSE_WDMA0_PORT;
+ 				break;
+ 			case 1:
+-				pse_port = 9;
++				pse_port = PSE_WDMA1_PORT;
+ 				break;
+ 			default:
+ 				return -EINVAL;
diff --git a/target/linux/generic/backport-5.15/752-04-v6.6-net-ethernet-mtk_wed-check-update_wo_rx_stats-in-mtk.patch b/target/linux/generic/backport-5.15/752-04-v6.6-net-ethernet-mtk_wed-check-update_wo_rx_stats-in-mtk.patch
new file mode 100644
index 00000000000..c99e1334d41
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-04-v6.6-net-ethernet-mtk_wed-check-update_wo_rx_stats-in-mtk.patch
@@ -0,0 +1,26 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Tue, 12 Sep 2023 10:28:00 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: check update_wo_rx_stats in
+ mtk_wed_update_rx_stats()
+
+Check if update_wo_rx_stats function pointer is properly set in
+mtk_wed_update_rx_stats routine before accessing it.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Link: https://lore.kernel.org/r/b0d233386e059bccb59f18f69afb79a7806e5ded.1694507226.git.lorenzo@kernel.org
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -68,6 +68,9 @@ mtk_wed_update_rx_stats(struct mtk_wed_d
+ 	struct mtk_wed_wo_rx_stats *stats;
+ 	int i;
+ 
++	if (!wed->wlan.update_wo_rx_stats)
++		return;
++
+ 	if (count * sizeof(*stats) > skb->len - sizeof(u32))
+ 		return;
+ 
diff --git a/target/linux/generic/backport-5.15/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch b/target/linux/generic/backport-5.15/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch
new file mode 100644
index 00000000000..cd7fb92e209
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-05-v6.7-net-ethernet-mtk_wed-do-not-assume-offload-callbacks.patch
@@ -0,0 +1,68 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Wed, 13 Sep 2023 20:42:47 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: do not assume offload callbacks are
+ always set
+
+Check if wlan.offload_enable and wlan.offload_disable callbacks are set
+in mtk_wed_flow_add/mtk_wed_flow_remove since mt7996 will not rely
+on them.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Reviewed-by: Simon Horman <horms@kernel.org>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -1712,19 +1712,20 @@ mtk_wed_irq_set_mask(struct mtk_wed_devi
+ int mtk_wed_flow_add(int index)
+ {
+ 	struct mtk_wed_hw *hw = hw_list[index];
+-	int ret;
++	int ret = 0;
+ 
+-	if (!hw || !hw->wed_dev)
+-		return -ENODEV;
++	mutex_lock(&hw_lock);
+ 
+-	if (hw->num_flows) {
+-		hw->num_flows++;
+-		return 0;
++	if (!hw || !hw->wed_dev) {
++		ret = -ENODEV;
++		goto out;
+ 	}
+ 
+-	mutex_lock(&hw_lock);
+-	if (!hw->wed_dev) {
+-		ret = -ENODEV;
++	if (!hw->wed_dev->wlan.offload_enable)
++		goto out;
++
++	if (hw->num_flows) {
++		hw->num_flows++;
+ 		goto out;
+ 	}
+ 
+@@ -1743,14 +1744,15 @@ void mtk_wed_flow_remove(int index)
+ {
+ 	struct mtk_wed_hw *hw = hw_list[index];
+ 
+-	if (!hw)
+-		return;
++	mutex_lock(&hw_lock);
+ 
+-	if (--hw->num_flows)
+-		return;
++	if (!hw || !hw->wed_dev)
++		goto out;
+ 
+-	mutex_lock(&hw_lock);
+-	if (!hw->wed_dev)
++	if (!hw->wed_dev->wlan.offload_disable)
++		goto out;
++
++	if (--hw->num_flows)
+ 		goto out;
+ 
+ 	hw->wed_dev->wlan.offload_disable(hw->wed_dev);
diff --git a/target/linux/generic/backport-5.15/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch b/target/linux/generic/backport-5.15/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch
new file mode 100644
index 00000000000..29481886503
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-06-v6.7-net-ethernet-mtk_wed-introduce-versioning-utility-ro.patch
@@ -0,0 +1,232 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:05 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: introduce versioning utility routines
+
+Similar to mtk_eth_soc, introduce the following wed versioning
+utility routines:
+- mtk_wed_is_v1
+- mtk_wed_is_v2
+
+This is a preliminary patch to introduce WED support for MT7988 SoC
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -277,7 +277,7 @@ mtk_wed_assign(struct mtk_wed_device *de
+ 		if (!hw->wed_dev)
+ 			goto out;
+ 
+-		if (hw->version == 1)
++		if (mtk_wed_is_v1(hw))
+ 			return NULL;
+ 
+ 		/* MT7986 WED devices do not have any pcie slot restrictions */
+@@ -358,7 +358,7 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 			desc->buf0 = cpu_to_le32(buf_phys);
+ 			desc->buf1 = cpu_to_le32(buf_phys + txd_size);
+ 
+-			if (dev->hw->version == 1)
++			if (mtk_wed_is_v1(dev->hw))
+ 				ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
+ 				       FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
+ 						  MTK_WED_BUF_SIZE - txd_size) |
+@@ -497,7 +497,7 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
+ {
+ 	u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
+ 
+-	if (dev->hw->version == 1)
++	if (mtk_wed_is_v1(dev->hw))
+ 		mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
+ 	else
+ 		mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
+@@ -576,7 +576,7 @@ mtk_wed_dma_disable(struct mtk_wed_devic
+ 		 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
+ 		 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		regmap_write(dev->hw->mirror, dev->hw->index * 4, 0);
+ 		wdma_clr(dev, MTK_WDMA_GLO_CFG,
+ 			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
+@@ -605,7 +605,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
+ 	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
+ 
+-	if (dev->hw->version == 1)
++	if (mtk_wed_is_v1(dev->hw))
+ 		return;
+ 
+ 	wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
+@@ -624,7 +624,7 @@ mtk_wed_deinit(struct mtk_wed_device *de
+ 		MTK_WED_CTRL_WED_TX_BM_EN |
+ 		MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
+ 
+-	if (dev->hw->version == 1)
++	if (mtk_wed_is_v1(dev->hw))
+ 		return;
+ 
+ 	wed_clr(dev, MTK_WED_CTRL,
+@@ -730,7 +730,7 @@ mtk_wed_bus_init(struct mtk_wed_device *
+ static void
+ mtk_wed_set_wpdma(struct mtk_wed_device *dev)
+ {
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
+ 	} else {
+ 		mtk_wed_bus_init(dev);
+@@ -761,7 +761,7 @@ mtk_wed_hw_init_early(struct mtk_wed_dev
+ 	      MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
+ 	wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		u32 offset = dev->hw->index ? 0x04000400 : 0;
+ 
+ 		wdma_set(dev, MTK_WDMA_GLO_CFG,
+@@ -934,7 +934,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 
+ 	wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_w32(dev, MTK_WED_TX_BM_TKID,
+ 			FIELD_PREP(MTK_WED_TX_BM_TKID_START,
+ 				   dev->wlan.token_start) |
+@@ -967,7 +967,7 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 
+ 	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_set(dev, MTK_WED_CTRL,
+ 			MTK_WED_CTRL_WED_TX_BM_EN |
+ 			MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
+@@ -1217,7 +1217,7 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 	}
+ 
+ 	dev->init_done = false;
+-	if (dev->hw->version == 1)
++	if (mtk_wed_is_v1(dev->hw))
+ 		return;
+ 
+ 	if (!busy) {
+@@ -1343,7 +1343,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+ 		MTK_WED_CTRL_WED_TX_BM_EN |
+ 		MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER,
+ 			MTK_WED_PCIE_INT_TRIGGER_STATUS);
+ 
+@@ -1416,7 +1416,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ 		 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
+ 		 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		wdma_set(dev, MTK_WDMA_GLO_CFG,
+ 			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
+ 	} else {
+@@ -1465,7 +1465,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+ 
+ 	mtk_wed_set_ext_int(dev, true);
+ 
+-	if (dev->hw->version == 1) {
++	if (mtk_wed_is_v1(dev->hw)) {
+ 		u32 val = dev->wlan.wpdma_phys | MTK_PCIE_MIRROR_MAP_EN |
+ 			  FIELD_PREP(MTK_PCIE_MIRROR_MAP_WED_ID,
+ 				     dev->hw->index);
+@@ -1550,7 +1550,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+ 	}
+ 
+ 	mtk_wed_hw_init_early(dev);
+-	if (hw->version == 1) {
++	if (mtk_wed_is_v1(hw)) {
+ 		regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
+ 				   BIT(hw->index), 0);
+ 	} else {
+@@ -1618,7 +1618,7 @@ static int
+ mtk_wed_txfree_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
+ {
+ 	struct mtk_wed_ring *ring = &dev->txfree_ring;
+-	int i, index = dev->hw->version == 1;
++	int i, index = mtk_wed_is_v1(dev->hw);
+ 
+ 	/*
+ 	 * For txfree event handling, the same DMA ring is shared between WED
+@@ -1676,7 +1676,7 @@ mtk_wed_irq_get(struct mtk_wed_device *d
+ {
+ 	u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
+ 
+-	if (dev->hw->version == 1)
++	if (mtk_wed_is_v1(dev->hw))
+ 		ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
+ 	else
+ 		ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
+@@ -1843,7 +1843,7 @@ mtk_wed_setup_tc(struct mtk_wed_device *
+ {
+ 	struct mtk_wed_hw *hw = wed->hw;
+ 
+-	if (hw->version < 2)
++	if (mtk_wed_is_v1(hw))
+ 		return -EOPNOTSUPP;
+ 
+ 	switch (type) {
+@@ -1917,9 +1917,9 @@ void mtk_wed_add_hw(struct device_node *
+ 	hw->wdma = wdma;
+ 	hw->index = index;
+ 	hw->irq = irq;
+-	hw->version = mtk_is_netsys_v1(eth) ? 1 : 2;
++	hw->version = eth->soc->version;
+ 
+-	if (hw->version == 1) {
++	if (mtk_wed_is_v1(hw)) {
+ 		hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
+ 				"mediatek,pcie-mirror");
+ 		hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
+@@ -40,6 +40,16 @@ struct mtk_wdma_info {
+ };
+ 
+ #ifdef CONFIG_NET_MEDIATEK_SOC_WED
++static inline bool mtk_wed_is_v1(struct mtk_wed_hw *hw)
++{
++	return hw->version == 1;
++}
++
++static inline bool mtk_wed_is_v2(struct mtk_wed_hw *hw)
++{
++	return hw->version == 2;
++}
++
+ static inline void
+ wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
+ {
+--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
+@@ -263,7 +263,7 @@ void mtk_wed_hw_add_debugfs(struct mtk_w
+ 	debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
+ 	debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
+ 	debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
+-	if (hw->version != 1)
++	if (!mtk_wed_is_v1(hw))
+ 		debugfs_create_file_unsafe("rxinfo", 0400, dir, hw,
+ 					   &wed_rxinfo_fops);
+ }
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -207,7 +207,7 @@ int mtk_wed_mcu_msg_update(struct mtk_we
+ {
+ 	struct mtk_wed_wo *wo = dev->hw->wed_wo;
+ 
+-	if (dev->hw->version == 1)
++	if (mtk_wed_is_v1(dev->hw))
+ 		return 0;
+ 
+ 	if (WARN_ON(!wo))
diff --git a/target/linux/generic/backport-5.15/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch b/target/linux/generic/backport-5.15/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch
new file mode 100644
index 00000000000..bc34aa33a9f
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-07-v6.7-net-ethernet-mtk_wed-do-not-configure-rx-offload-if-.patch
@@ -0,0 +1,234 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:06 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: do not configure rx offload if not
+ supported
+
+Check if rx offload is supported running mtk_wed_get_rx_capa routine
+before configuring it. This is a preliminary patch to introduce Wireless
+Ethernet Dispatcher (WED) support for MT7988 SoC.
+
+Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -605,7 +605,7 @@ mtk_wed_stop(struct mtk_wed_device *dev)
+ 	wdma_w32(dev, MTK_WDMA_INT_GRP2, 0);
+ 	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, 0);
+ 
+-	if (mtk_wed_is_v1(dev->hw))
++	if (!mtk_wed_get_rx_capa(dev))
+ 		return;
+ 
+ 	wed_w32(dev, MTK_WED_EXT_INT_MASK1, 0);
+@@ -732,16 +732,21 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+ {
+ 	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
+-	} else {
+-		mtk_wed_bus_init(dev);
+-
+-		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
+-		wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
+-		wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
+-		wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
+-		wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
+-		wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
++		return;
+ 	}
++
++	mtk_wed_bus_init(dev);
++
++	wed_w32(dev, MTK_WED_WPDMA_CFG_BASE, dev->wlan.wpdma_int);
++	wed_w32(dev, MTK_WED_WPDMA_CFG_INT_MASK, dev->wlan.wpdma_mask);
++	wed_w32(dev, MTK_WED_WPDMA_CFG_TX, dev->wlan.wpdma_tx);
++	wed_w32(dev, MTK_WED_WPDMA_CFG_TX_FREE, dev->wlan.wpdma_txfree);
++
++	if (!mtk_wed_get_rx_capa(dev))
++		return;
++
++	wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
++	wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
+ }
+ 
+ static void
+@@ -973,15 +978,17 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 			MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
+ 	} else {
+ 		wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
+-		/* rx hw init */
+-		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
+-			MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
+-			MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
+-		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
+-
+-		mtk_wed_rx_buffer_hw_init(dev);
+-		mtk_wed_rro_hw_init(dev);
+-		mtk_wed_route_qm_hw_init(dev);
++		if (mtk_wed_get_rx_capa(dev)) {
++			/* rx hw init */
++			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
++				MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
++				MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
++			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
++
++			mtk_wed_rx_buffer_hw_init(dev);
++			mtk_wed_rro_hw_init(dev);
++			mtk_wed_route_qm_hw_init(dev);
++		}
+ 	}
+ 
+ 	wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
+@@ -1353,8 +1360,6 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+ 
+ 		wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
+ 	} else {
+-		wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
+-					GENMASK(1, 0));
+ 		/* initail tx interrupt trigger */
+ 		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
+ 			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
+@@ -1373,15 +1378,20 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+ 			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_TX_FREE_DONE_TRIG,
+ 				   dev->wlan.txfree_tbit));
+ 
+-		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
+-			MTK_WED_WPDMA_INT_CTRL_RX0_EN |
+-			MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
+-			MTK_WED_WPDMA_INT_CTRL_RX1_EN |
+-			MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
+-			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
+-				   dev->wlan.rx_tbit[0]) |
+-			FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
+-				   dev->wlan.rx_tbit[1]));
++		if (mtk_wed_get_rx_capa(dev)) {
++			wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RX,
++				MTK_WED_WPDMA_INT_CTRL_RX0_EN |
++				MTK_WED_WPDMA_INT_CTRL_RX0_CLR |
++				MTK_WED_WPDMA_INT_CTRL_RX1_EN |
++				MTK_WED_WPDMA_INT_CTRL_RX1_CLR |
++				FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX0_DONE_TRIG,
++					   dev->wlan.rx_tbit[0]) |
++				FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RX1_DONE_TRIG,
++					   dev->wlan.rx_tbit[1]));
++
++			wdma_mask |= FIELD_PREP(MTK_WDMA_INT_MASK_TX_DONE,
++						GENMASK(1, 0));
++		}
+ 
+ 		wed_w32(dev, MTK_WED_WDMA_INT_CLR, wdma_mask);
+ 		wed_set(dev, MTK_WED_WDMA_INT_CTRL,
+@@ -1400,6 +1410,8 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+ static void
+ mtk_wed_dma_enable(struct mtk_wed_device *dev)
+ {
++	int i;
++
+ 	wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
+ 
+ 	wed_set(dev, MTK_WED_GLO_CFG,
+@@ -1419,33 +1431,33 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ 	if (mtk_wed_is_v1(dev->hw)) {
+ 		wdma_set(dev, MTK_WDMA_GLO_CFG,
+ 			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
+-	} else {
+-		int i;
++		return;
++	}
+ 
+-		wed_set(dev, MTK_WED_WPDMA_CTRL,
+-			MTK_WED_WPDMA_CTRL_SDL1_FIXED);
++	wed_set(dev, MTK_WED_WPDMA_CTRL,
++		MTK_WED_WPDMA_CTRL_SDL1_FIXED);
++	wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
++		MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
++		MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
++	wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
++		MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
++		MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
+ 
+-		wed_set(dev, MTK_WED_WDMA_GLO_CFG,
+-			MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
+-			MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
++	if (!mtk_wed_get_rx_capa(dev))
++		return;
+ 
+-		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
+-			MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
+-			MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
+-
+-		wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
+-			MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
+-			MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
++	wed_set(dev, MTK_WED_WDMA_GLO_CFG,
++		MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
++		MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
+ 
+-		wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
+-			MTK_WED_WPDMA_RX_D_RX_DRV_EN |
+-			FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
+-			FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
+-				   0x2));
++	wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
++		MTK_WED_WPDMA_RX_D_RX_DRV_EN |
++		FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
++		FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
++			   0x2));
+ 
+-		for (i = 0; i < MTK_WED_RX_QUEUES; i++)
+-			mtk_wed_check_wfdma_rx_fill(dev, i);
+-	}
++	for (i = 0; i < MTK_WED_RX_QUEUES; i++)
++		mtk_wed_check_wfdma_rx_fill(dev, i);
+ }
+ 
+ static void
+@@ -1472,7 +1484,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+ 
+ 		val |= BIT(0) | (BIT(1) * !!dev->hw->index);
+ 		regmap_write(dev->hw->mirror, dev->hw->index * 4, val);
+-	} else {
++	} else if (mtk_wed_get_rx_capa(dev)) {
+ 		/* driver set mid ready and only once */
+ 		wed_w32(dev, MTK_WED_EXT_INT_MASK1,
+ 			MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
+@@ -1484,7 +1496,6 @@ mtk_wed_start(struct mtk_wed_device *dev
+ 
+ 		if (mtk_wed_rro_cfg(dev))
+ 			return;
+-
+ 	}
+ 
+ 	mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
+@@ -1550,13 +1561,14 @@ mtk_wed_attach(struct mtk_wed_device *de
+ 	}
+ 
+ 	mtk_wed_hw_init_early(dev);
+-	if (mtk_wed_is_v1(hw)) {
++	if (mtk_wed_is_v1(hw))
+ 		regmap_update_bits(hw->hifsys, HIFSYS_DMA_AG_MAP,
+ 				   BIT(hw->index), 0);
+-	} else {
++	else
+ 		dev->rev_id = wed_r32(dev, MTK_WED_REV_ID);
++
++	if (mtk_wed_get_rx_capa(dev))
+ 		ret = mtk_wed_wo_init(hw);
+-	}
+ out:
+ 	if (ret) {
+ 		dev_err(dev->hw->dev, "failed to attach wed device\n");
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -207,7 +207,7 @@ int mtk_wed_mcu_msg_update(struct mtk_we
+ {
+ 	struct mtk_wed_wo *wo = dev->hw->wed_wo;
+ 
+-	if (mtk_wed_is_v1(dev->hw))
++	if (!mtk_wed_get_rx_capa(dev))
+ 		return 0;
+ 
+ 	if (WARN_ON(!wo))
diff --git a/target/linux/generic/backport-5.15/752-08-v6.7-net-ethernet-mtk_wed-rename-mtk_rxbm_desc-in-mtk_wed.patch b/target/linux/generic/backport-5.15/752-08-v6.7-net-ethernet-mtk_wed-rename-mtk_rxbm_desc-in-mtk_wed.patch
new file mode 100644
index 00000000000..d83434fb2c7
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-08-v6.7-net-ethernet-mtk_wed-rename-mtk_rxbm_desc-in-mtk_wed.patch
@@ -0,0 +1,52 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:07 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: rename mtk_rxbm_desc in
+ mtk_wed_bm_desc
+
+Rename mtk_rxbm_desc structure in mtk_wed_bm_desc since it will be used
+even on tx side by MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -421,7 +421,7 @@ free_pagelist:
+ static int
+ mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
+ {
+-	struct mtk_rxbm_desc *desc;
++	struct mtk_wed_bm_desc *desc;
+ 	dma_addr_t desc_phys;
+ 
+ 	dev->rx_buf_ring.size = dev->wlan.rx_nbuf;
+@@ -441,7 +441,7 @@ mtk_wed_rx_buffer_alloc(struct mtk_wed_d
+ static void
+ mtk_wed_free_rx_buffer(struct mtk_wed_device *dev)
+ {
+-	struct mtk_rxbm_desc *desc = dev->rx_buf_ring.desc;
++	struct mtk_wed_bm_desc *desc = dev->rx_buf_ring.desc;
+ 
+ 	if (!desc)
+ 		return;
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -45,7 +45,7 @@ enum mtk_wed_wo_cmd {
+ 	MTK_WED_WO_CMD_WED_END
+ };
+ 
+-struct mtk_rxbm_desc {
++struct mtk_wed_bm_desc {
+ 	__le32 buf0;
+ 	__le32 token;
+ } __packed __aligned(4);
+@@ -105,7 +105,7 @@ struct mtk_wed_device {
+ 	struct {
+ 		int size;
+ 		struct page_frag_cache rx_page;
+-		struct mtk_rxbm_desc *desc;
++		struct mtk_wed_bm_desc *desc;
+ 		dma_addr_t desc_phys;
+ 	} rx_buf_ring;
+ 
diff --git a/target/linux/generic/backport-5.15/752-09-v6.7-net-ethernet-mtk_wed-introduce-mtk_wed_buf-structure.patch b/target/linux/generic/backport-5.15/752-09-v6.7-net-ethernet-mtk_wed-introduce-mtk_wed_buf-structure.patch
new file mode 100644
index 00000000000..8000a8759e5
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-09-v6.7-net-ethernet-mtk_wed-introduce-mtk_wed_buf-structure.patch
@@ -0,0 +1,87 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:08 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: introduce mtk_wed_buf structure
+
+Introduce mtk_wed_buf structure to store both virtual and physical
+addresses allocated in mtk_wed_tx_buffer_alloc() routine. This is a
+preliminary patch to add WED support for MT7988 SoC since it relies on a
+different dma descriptor layout not storing page dma addresses.
+
+Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -299,9 +299,9 @@ out:
+ static int
+ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
+ {
++	struct mtk_wed_buf *page_list;
+ 	struct mtk_wdma_desc *desc;
+ 	dma_addr_t desc_phys;
+-	void **page_list;
+ 	int token = dev->wlan.token_start;
+ 	int ring_size;
+ 	int n_pages;
+@@ -342,7 +342,8 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 			return -ENOMEM;
+ 		}
+ 
+-		page_list[page_idx++] = page;
++		page_list[page_idx].p = page;
++		page_list[page_idx++].phy_addr = page_phys;
+ 		dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
+ 					DMA_BIDIRECTIONAL);
+ 
+@@ -386,8 +387,8 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ static void
+ mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
+ {
++	struct mtk_wed_buf *page_list = dev->tx_buf_ring.pages;
+ 	struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc;
+-	void **page_list = dev->tx_buf_ring.pages;
+ 	int page_idx;
+ 	int i;
+ 
+@@ -399,13 +400,12 @@ mtk_wed_free_tx_buffer(struct mtk_wed_de
+ 
+ 	for (i = 0, page_idx = 0; i < dev->tx_buf_ring.size;
+ 	     i += MTK_WED_BUF_PER_PAGE) {
+-		void *page = page_list[page_idx++];
+-		dma_addr_t buf_addr;
++		dma_addr_t buf_addr = page_list[page_idx].phy_addr;
++		void *page = page_list[page_idx++].p;
+ 
+ 		if (!page)
+ 			break;
+ 
+-		buf_addr = le32_to_cpu(desc[i].buf0);
+ 		dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
+ 			       DMA_BIDIRECTIONAL);
+ 		__free_page(page);
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -76,6 +76,11 @@ struct mtk_wed_wo_rx_stats {
+ 	__le32 rx_drop_cnt;
+ };
+ 
++struct mtk_wed_buf {
++	void *p;
++	dma_addr_t phy_addr;
++};
++
+ struct mtk_wed_device {
+ #ifdef CONFIG_NET_MEDIATEK_SOC_WED
+ 	const struct mtk_wed_ops *ops;
+@@ -97,7 +102,7 @@ struct mtk_wed_device {
+ 
+ 	struct {
+ 		int size;
+-		void **pages;
++		struct mtk_wed_buf *pages;
+ 		struct mtk_wdma_desc *desc;
+ 		dma_addr_t desc_phys;
+ 	} tx_buf_ring;
diff --git a/target/linux/generic/backport-5.15/752-10-v6.7-net-ethernet-mtk_wed-move-mem_region-array-out-of-mt.patch b/target/linux/generic/backport-5.15/752-10-v6.7-net-ethernet-mtk_wed-move-mem_region-array-out-of-mt.patch
new file mode 100644
index 00000000000..98d782b1d07
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-10-v6.7-net-ethernet-mtk_wed-move-mem_region-array-out-of-mt.patch
@@ -0,0 +1,88 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:09 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: move mem_region array out of
+ mtk_wed_mcu_load_firmware
+
+Remove mtk_wed_wo_memory_region boot structure in mtk_wed_wo.
+This is a preliminary patch to introduce WED support for MT7988 SoC.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -16,14 +16,30 @@
+ #include "mtk_wed_wo.h"
+ #include "mtk_wed.h"
+ 
++static struct mtk_wed_wo_memory_region mem_region[] = {
++	[MTK_WED_WO_REGION_EMI] = {
++		.name = "wo-emi",
++	},
++	[MTK_WED_WO_REGION_ILM] = {
++		.name = "wo-ilm",
++	},
++	[MTK_WED_WO_REGION_DATA] = {
++		.name = "wo-data",
++		.shared = true,
++	},
++	[MTK_WED_WO_REGION_BOOT] = {
++		.name = "wo-boot",
++	},
++};
++
+ static u32 wo_r32(struct mtk_wed_wo *wo, u32 reg)
+ {
+-	return readl(wo->boot.addr + reg);
++	return readl(mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+ 
+ static void wo_w32(struct mtk_wed_wo *wo, u32 reg, u32 val)
+ {
+-	writel(val, wo->boot.addr + reg);
++	writel(val, mem_region[MTK_WED_WO_REGION_BOOT].addr + reg);
+ }
+ 
+ static struct sk_buff *
+@@ -294,18 +310,6 @@ next:
+ static int
+ mtk_wed_mcu_load_firmware(struct mtk_wed_wo *wo)
+ {
+-	static struct mtk_wed_wo_memory_region mem_region[] = {
+-		[MTK_WED_WO_REGION_EMI] = {
+-			.name = "wo-emi",
+-		},
+-		[MTK_WED_WO_REGION_ILM] = {
+-			.name = "wo-ilm",
+-		},
+-		[MTK_WED_WO_REGION_DATA] = {
+-			.name = "wo-data",
+-			.shared = true,
+-		},
+-	};
+ 	const struct mtk_wed_fw_trailer *trailer;
+ 	const struct firmware *fw;
+ 	const char *fw_name;
+@@ -319,11 +323,6 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 			return ret;
+ 	}
+ 
+-	wo->boot.name = "wo-boot";
+-	ret = mtk_wed_get_memory_region(wo, &wo->boot);
+-	if (ret)
+-		return ret;
+-
+ 	/* set dummy cr */
+ 	wed_w32(wo->hw->wed_dev, MTK_WED_SCR0 + 4 * MTK_WED_DUMMY_CR_FWDL,
+ 		wo->hw->index + 1);
+--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
+@@ -228,7 +228,6 @@ struct mtk_wed_wo_queue {
+ 
+ struct mtk_wed_wo {
+ 	struct mtk_wed_hw *hw;
+-	struct mtk_wed_wo_memory_region boot;
+ 
+ 	struct mtk_wed_wo_queue q_tx;
+ 	struct mtk_wed_wo_queue q_rx;
diff --git a/target/linux/generic/backport-5.15/752-11-v6.7-net-ethernet-mtk_wed-make-memory-region-optional.patch b/target/linux/generic/backport-5.15/752-11-v6.7-net-ethernet-mtk_wed-make-memory-region-optional.patch
new file mode 100644
index 00000000000..48b0d020491
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-11-v6.7-net-ethernet-mtk_wed-make-memory-region-optional.patch
@@ -0,0 +1,71 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:10 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: make memory region optional
+
+Make mtk_wed_wo_memory_region optionals.
+This is a preliminary patch to introduce Wireless Ethernet Dispatcher
+support for MT7988 SoC since MT7988 WED fw image will have a different
+layout.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -234,19 +234,13 @@ int mtk_wed_mcu_msg_update(struct mtk_we
+ }
+ 
+ static int
+-mtk_wed_get_memory_region(struct mtk_wed_wo *wo,
++mtk_wed_get_memory_region(struct mtk_wed_hw *hw, int index,
+ 			  struct mtk_wed_wo_memory_region *region)
+ {
+ 	struct reserved_mem *rmem;
+ 	struct device_node *np;
+-	int index;
+ 
+-	index = of_property_match_string(wo->hw->node, "memory-region-names",
+-					 region->name);
+-	if (index < 0)
+-		return index;
+-
+-	np = of_parse_phandle(wo->hw->node, "memory-region", index);
++	np = of_parse_phandle(hw->node, "memory-region", index);
+ 	if (!np)
+ 		return -ENODEV;
+ 
+@@ -258,7 +252,7 @@ mtk_wed_get_memory_region(struct mtk_wed
+ 
+ 	region->phy_addr = rmem->base;
+ 	region->size = rmem->size;
+-	region->addr = devm_ioremap(wo->hw->dev, region->phy_addr, region->size);
++	region->addr = devm_ioremap(hw->dev, region->phy_addr, region->size);
+ 
+ 	return !region->addr ? -EINVAL : 0;
+ }
+@@ -271,6 +265,9 @@ mtk_wed_mcu_run_firmware(struct mtk_wed_
+ 	const struct mtk_wed_fw_trailer *trailer;
+ 	const struct mtk_wed_fw_region *fw_region;
+ 
++	if (!region->phy_addr || !region->size)
++		return 0;
++
+ 	trailer_ptr = fw->data + fw->size - sizeof(*trailer);
+ 	trailer = (const struct mtk_wed_fw_trailer *)trailer_ptr;
+ 	region_ptr = trailer_ptr - trailer->num_region * sizeof(*fw_region);
+@@ -318,7 +315,13 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 
+ 	/* load firmware region metadata */
+ 	for (i = 0; i < ARRAY_SIZE(mem_region); i++) {
+-		ret = mtk_wed_get_memory_region(wo, &mem_region[i]);
++		int index = of_property_match_string(wo->hw->node,
++						     "memory-region-names",
++						     mem_region[i].name);
++		if (index < 0)
++			continue;
++
++		ret = mtk_wed_get_memory_region(wo->hw, index, &mem_region[i]);
+ 		if (ret)
+ 			return ret;
+ 	}
diff --git a/target/linux/generic/backport-5.15/752-12-v6.7-net-ethernet-mtk_wed-fix-EXT_INT_STATUS_RX_FBUF-defi.patch b/target/linux/generic/backport-5.15/752-12-v6.7-net-ethernet-mtk_wed-fix-EXT_INT_STATUS_RX_FBUF-defi.patch
new file mode 100644
index 00000000000..878e8fe996d
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-12-v6.7-net-ethernet-mtk_wed-fix-EXT_INT_STATUS_RX_FBUF-defi.patch
@@ -0,0 +1,27 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:11 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: fix EXT_INT_STATUS_RX_FBUF
+ definitions for MT7986 SoC
+
+Fix MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH and
+MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH definitions for MT7986 (MT7986 is
+the only SoC to use them).
+
+Fixes: de84a090d99a ("net: ethernet: mtk_eth_wed: add wed support for mt7986 chipset")
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
+@@ -64,8 +64,8 @@ struct mtk_wdma_desc {
+ #define MTK_WED_EXT_INT_STATUS_TKID_TITO_INVALID	BIT(4)
+ #define MTK_WED_EXT_INT_STATUS_TX_FBUF_LO_TH		BIT(8)
+ #define MTK_WED_EXT_INT_STATUS_TX_FBUF_HI_TH		BIT(9)
+-#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH		BIT(12)
+-#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH		BIT(13)
++#define MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH		BIT(10) /* wed v2 */
++#define MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH		BIT(11) /* wed v2 */
+ #define MTK_WED_EXT_INT_STATUS_RX_DRV_R_RESP_ERR	BIT(16)
+ #define MTK_WED_EXT_INT_STATUS_RX_DRV_W_RESP_ERR	BIT(17)
+ #define MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT		BIT(18)
diff --git a/target/linux/generic/backport-5.15/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch b/target/linux/generic/backport-5.15/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch
new file mode 100644
index 00000000000..c43114fb5b1
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-13-v6.7-net-ethernet-mtk_wed-add-mtk_wed_soc_data-structure.patch
@@ -0,0 +1,217 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:12 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: add mtk_wed_soc_data structure
+
+Introduce mtk_wed_soc_data utility structure to contain per-SoC
+definitions.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -48,6 +48,26 @@ struct mtk_wed_flow_block_priv {
+ 	struct net_device *dev;
+ };
+ 
++static const struct mtk_wed_soc_data mt7622_data = {
++	.regmap = {
++		.tx_bm_tkid		= 0x088,
++		.wpdma_rx_ring0		= 0x770,
++		.reset_idx_tx_mask	= GENMASK(3, 0),
++		.reset_idx_rx_mask	= GENMASK(17, 16),
++	},
++	.wdma_desc_size = sizeof(struct mtk_wdma_desc),
++};
++
++static const struct mtk_wed_soc_data mt7986_data = {
++	.regmap = {
++		.tx_bm_tkid		= 0x0c8,
++		.wpdma_rx_ring0		= 0x770,
++		.reset_idx_tx_mask	= GENMASK(1, 0),
++		.reset_idx_rx_mask	= GENMASK(7, 6),
++	},
++	.wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
++};
++
+ static void
+ wed_m32(struct mtk_wed_device *dev, u32 reg, u32 mask, u32 val)
+ {
+@@ -746,7 +766,7 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+ 		return;
+ 
+ 	wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
+-	wed_w32(dev, MTK_WED_WPDMA_RX_RING, dev->wlan.wpdma_rx);
++	wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
+ }
+ 
+ static void
+@@ -940,22 +960,10 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 	wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
+ 
+ 	if (mtk_wed_is_v1(dev->hw)) {
+-		wed_w32(dev, MTK_WED_TX_BM_TKID,
+-			FIELD_PREP(MTK_WED_TX_BM_TKID_START,
+-				   dev->wlan.token_start) |
+-			FIELD_PREP(MTK_WED_TX_BM_TKID_END,
+-				   dev->wlan.token_start +
+-				   dev->wlan.nbuf - 1));
+ 		wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
+ 			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
+ 			MTK_WED_TX_BM_DYN_THR_HI);
+ 	} else {
+-		wed_w32(dev, MTK_WED_TX_BM_TKID_V2,
+-			FIELD_PREP(MTK_WED_TX_BM_TKID_START,
+-				   dev->wlan.token_start) |
+-			FIELD_PREP(MTK_WED_TX_BM_TKID_END,
+-				   dev->wlan.token_start +
+-				   dev->wlan.nbuf - 1));
+ 		wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
+ 			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
+ 			MTK_WED_TX_BM_DYN_THR_HI_V2);
+@@ -970,6 +978,11 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 			MTK_WED_TX_TKID_DYN_THR_HI);
+ 	}
+ 
++	wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
++		FIELD_PREP(MTK_WED_TX_BM_TKID_START, dev->wlan.token_start) |
++		FIELD_PREP(MTK_WED_TX_BM_TKID_END,
++			   dev->wlan.token_start + dev->wlan.nbuf - 1));
++
+ 	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
+ 
+ 	if (mtk_wed_is_v1(dev->hw)) {
+@@ -1104,13 +1117,8 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 	if (ret) {
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WED_RX_DMA);
+ 	} else {
+-		struct mtk_eth *eth = dev->hw->eth;
+-
+-		if (mtk_is_netsys_v2_or_greater(eth))
+-			wed_set(dev, MTK_WED_RESET_IDX,
+-				MTK_WED_RESET_IDX_RX_V2);
+-		else
+-			wed_set(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_RX);
++		wed_set(dev, MTK_WED_RESET_IDX,
++			dev->hw->soc->regmap.reset_idx_rx_mask);
+ 		wed_w32(dev, MTK_WED_RESET_IDX, 0);
+ 	}
+ 
+@@ -1163,7 +1171,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 	if (busy) {
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WED_TX_DMA);
+ 	} else {
+-		wed_w32(dev, MTK_WED_RESET_IDX, MTK_WED_RESET_IDX_TX);
++		wed_w32(dev, MTK_WED_RESET_IDX,
++			dev->hw->soc->regmap.reset_idx_tx_mask);
+ 		wed_w32(dev, MTK_WED_RESET_IDX, 0);
+ 	}
+ 
+@@ -1255,7 +1264,6 @@ static int
+ mtk_wed_wdma_rx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
+ 			   bool reset)
+ {
+-	u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
+ 	struct mtk_wed_ring *wdma;
+ 
+ 	if (idx >= ARRAY_SIZE(dev->rx_wdma))
+@@ -1263,7 +1271,7 @@ mtk_wed_wdma_rx_ring_setup(struct mtk_we
+ 
+ 	wdma = &dev->rx_wdma[idx];
+ 	if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
+-					 desc_size, true))
++					 dev->hw->soc->wdma_desc_size, true))
+ 		return -ENOMEM;
+ 
+ 	wdma_w32(dev, MTK_WDMA_RING_RX(idx) + MTK_WED_RING_OFS_BASE,
+@@ -1284,7 +1292,6 @@ static int
+ mtk_wed_wdma_tx_ring_setup(struct mtk_wed_device *dev, int idx, int size,
+ 			   bool reset)
+ {
+-	u32 desc_size = sizeof(struct mtk_wdma_desc) * dev->hw->version;
+ 	struct mtk_wed_ring *wdma;
+ 
+ 	if (idx >= ARRAY_SIZE(dev->tx_wdma))
+@@ -1292,7 +1299,7 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+ 
+ 	wdma = &dev->tx_wdma[idx];
+ 	if (!reset && mtk_wed_ring_alloc(dev, wdma, MTK_WED_WDMA_RING_SIZE,
+-					 desc_size, true))
++					 dev->hw->soc->wdma_desc_size, true))
+ 		return -ENOMEM;
+ 
+ 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
+@@ -1931,7 +1938,12 @@ void mtk_wed_add_hw(struct device_node *
+ 	hw->irq = irq;
+ 	hw->version = eth->soc->version;
+ 
+-	if (mtk_wed_is_v1(hw)) {
++	switch (hw->version) {
++	case 2:
++		hw->soc = &mt7986_data;
++		break;
++	default:
++	case 1:
+ 		hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
+ 				"mediatek,pcie-mirror");
+ 		hw->hifsys = syscon_regmap_lookup_by_phandle(eth_np,
+@@ -1945,6 +1957,8 @@ void mtk_wed_add_hw(struct device_node *
+ 			regmap_write(hw->mirror, 0, 0);
+ 			regmap_write(hw->mirror, 4, 0);
+ 		}
++		hw->soc = &mt7622_data;
++		break;
+ 	}
+ 
+ 	mtk_wed_hw_add_debugfs(hw);
+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
+@@ -12,7 +12,18 @@
+ struct mtk_eth;
+ struct mtk_wed_wo;
+ 
++struct mtk_wed_soc_data {
++	struct {
++		u32 tx_bm_tkid;
++		u32 wpdma_rx_ring0;
++		u32 reset_idx_tx_mask;
++		u32 reset_idx_rx_mask;
++	} regmap;
++	u32 wdma_desc_size;
++};
++
+ struct mtk_wed_hw {
++	const struct mtk_wed_soc_data *soc;
+ 	struct device_node *node;
+ 	struct mtk_eth *eth;
+ 	struct regmap *regs;
+--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
+@@ -100,8 +100,6 @@ struct mtk_wdma_desc {
+ 
+ #define MTK_WED_TX_BM_BASE				0x084
+ 
+-#define MTK_WED_TX_BM_TKID				0x088
+-#define MTK_WED_TX_BM_TKID_V2				0x0c8
+ #define MTK_WED_TX_BM_TKID_START			GENMASK(15, 0)
+ #define MTK_WED_TX_BM_TKID_END				GENMASK(31, 16)
+ 
+@@ -160,9 +158,6 @@ struct mtk_wdma_desc {
+ #define MTK_WED_GLO_CFG_RX_2B_OFFSET			BIT(31)
+ 
+ #define MTK_WED_RESET_IDX				0x20c
+-#define MTK_WED_RESET_IDX_TX				GENMASK(3, 0)
+-#define MTK_WED_RESET_IDX_RX				GENMASK(17, 16)
+-#define MTK_WED_RESET_IDX_RX_V2				GENMASK(7, 6)
+ #define MTK_WED_RESET_WPDMA_IDX_RX			GENMASK(31, 30)
+ 
+ #define MTK_WED_TX_MIB(_n)				(0x2a0 + (_n) * 4)
+@@ -286,7 +281,6 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX			GENMASK(25, 24)
+ 
+ #define MTK_WED_WPDMA_RX_GLO_CFG			0x76c
+-#define MTK_WED_WPDMA_RX_RING				0x770
+ 
+ #define MTK_WED_WPDMA_RX_D_MIB(_n)			(0x774 + (_n) * 4)
+ #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n)		(0x784 + (_n) * 4)
diff --git a/target/linux/generic/backport-5.15/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch b/target/linux/generic/backport-5.15/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch
new file mode 100644
index 00000000000..f53b822224c
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-14-v6.7-net-ethernet-mtk_wed-introduce-WED-support-for-MT798.patch
@@ -0,0 +1,1280 @@
+From: Sujuan Chen <sujuan.chen@mediatek.com>
+Date: Mon, 18 Sep 2023 12:29:13 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: introduce WED support for MT7988
+
+Similar to MT7986 and MT7622, enable Wireless Ethernet Ditpatcher for
+MT7988 in order to offload traffic forwarded from LAN/WLAN to WLAN/LAN
+
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -195,6 +195,7 @@ static const struct mtk_reg_map mt7988_r
+ 	.wdma_base = {
+ 		[0]		= 0x4800,
+ 		[1]		= 0x4c00,
++		[2]		= 0x5000,
+ 	},
+ 	.pse_iq_sta		= 0x0180,
+ 	.pse_oq_sta		= 0x01a0,
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
+@@ -1129,7 +1129,7 @@ struct mtk_reg_map {
+ 	u32	gdm1_cnt;
+ 	u32	gdma_to_ppe0;
+ 	u32	ppe_base;
+-	u32	wdma_base[2];
++	u32	wdma_base[3];
+ 	u32	pse_iq_sta;
+ 	u32	pse_oq_sta;
+ };
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -201,6 +201,9 @@ mtk_flow_set_output_device(struct mtk_et
+ 			case 1:
+ 				pse_port = PSE_WDMA1_PORT;
+ 				break;
++			case 2:
++				pse_port = PSE_WDMA2_PORT;
++				break;
+ 			default:
+ 				return -EINVAL;
+ 			}
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -16,17 +16,19 @@
+ #include <net/flow_offload.h>
+ #include <net/pkt_cls.h>
+ #include "mtk_eth_soc.h"
+-#include "mtk_wed_regs.h"
+ #include "mtk_wed.h"
+ #include "mtk_ppe.h"
+ #include "mtk_wed_wo.h"
+ 
+ #define MTK_PCIE_BASE(n)		(0x1a143000 + (n) * 0x2000)
+ 
+-#define MTK_WED_PKT_SIZE		1900
++#define MTK_WED_PKT_SIZE		1920
+ #define MTK_WED_BUF_SIZE		2048
++#define MTK_WED_PAGE_BUF_SIZE		128
+ #define MTK_WED_BUF_PER_PAGE		(PAGE_SIZE / 2048)
++#define MTK_WED_RX_PAGE_BUF_PER_PAGE	(PAGE_SIZE / 128)
+ #define MTK_WED_RX_RING_SIZE		1536
++#define MTK_WED_RX_PG_BM_CNT		8192
+ 
+ #define MTK_WED_TX_RING_SIZE		2048
+ #define MTK_WED_WDMA_RING_SIZE		1024
+@@ -40,7 +42,10 @@
+ #define MTK_WED_RRO_QUE_CNT		8192
+ #define MTK_WED_MIOD_ENTRY_CNT		128
+ 
+-static struct mtk_wed_hw *hw_list[2];
++#define MTK_WED_TX_BM_DMA_SIZE		65536
++#define MTK_WED_TX_BM_PKT_CNT		32768
++
++static struct mtk_wed_hw *hw_list[3];
+ static DEFINE_MUTEX(hw_lock);
+ 
+ struct mtk_wed_flow_block_priv {
+@@ -55,6 +60,7 @@ static const struct mtk_wed_soc_data mt7
+ 		.reset_idx_tx_mask	= GENMASK(3, 0),
+ 		.reset_idx_rx_mask	= GENMASK(17, 16),
+ 	},
++	.tx_ring_desc_size = sizeof(struct mtk_wdma_desc),
+ 	.wdma_desc_size = sizeof(struct mtk_wdma_desc),
+ };
+ 
+@@ -65,6 +71,18 @@ static const struct mtk_wed_soc_data mt7
+ 		.reset_idx_tx_mask	= GENMASK(1, 0),
+ 		.reset_idx_rx_mask	= GENMASK(7, 6),
+ 	},
++	.tx_ring_desc_size = sizeof(struct mtk_wdma_desc),
++	.wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
++};
++
++static const struct mtk_wed_soc_data mt7988_data = {
++	.regmap = {
++		.tx_bm_tkid		= 0x0c8,
++		.wpdma_rx_ring0		= 0x7d0,
++		.reset_idx_tx_mask	= GENMASK(1, 0),
++		.reset_idx_rx_mask	= GENMASK(7, 6),
++	},
++	.tx_ring_desc_size = sizeof(struct mtk_wed_bm_desc),
+ 	.wdma_desc_size = 2 * sizeof(struct mtk_wdma_desc),
+ };
+ 
+@@ -319,33 +337,38 @@ out:
+ static int
+ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
+ {
++	u32 desc_size = dev->hw->soc->tx_ring_desc_size;
++	int i, page_idx = 0, n_pages, ring_size;
++	int token = dev->wlan.token_start;
+ 	struct mtk_wed_buf *page_list;
+-	struct mtk_wdma_desc *desc;
+ 	dma_addr_t desc_phys;
+-	int token = dev->wlan.token_start;
+-	int ring_size;
+-	int n_pages;
+-	int i, page_idx;
++	void *desc_ptr;
+ 
+-	ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
+-	n_pages = ring_size / MTK_WED_BUF_PER_PAGE;
++	if (!mtk_wed_is_v3_or_greater(dev->hw)) {
++		ring_size = dev->wlan.nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
++		dev->tx_buf_ring.size = ring_size;
++	} else {
++		dev->tx_buf_ring.size = MTK_WED_TX_BM_DMA_SIZE;
++		ring_size = MTK_WED_TX_BM_PKT_CNT;
++	}
++	n_pages = dev->tx_buf_ring.size / MTK_WED_BUF_PER_PAGE;
+ 
+ 	page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
+ 	if (!page_list)
+ 		return -ENOMEM;
+ 
+-	dev->tx_buf_ring.size = ring_size;
+ 	dev->tx_buf_ring.pages = page_list;
+ 
+-	desc = dma_alloc_coherent(dev->hw->dev, ring_size * sizeof(*desc),
+-				  &desc_phys, GFP_KERNEL);
+-	if (!desc)
++	desc_ptr = dma_alloc_coherent(dev->hw->dev,
++				      dev->tx_buf_ring.size * desc_size,
++				      &desc_phys, GFP_KERNEL);
++	if (!desc_ptr)
+ 		return -ENOMEM;
+ 
+-	dev->tx_buf_ring.desc = desc;
++	dev->tx_buf_ring.desc = desc_ptr;
+ 	dev->tx_buf_ring.desc_phys = desc_phys;
+ 
+-	for (i = 0, page_idx = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
++	for (i = 0; i < ring_size; i += MTK_WED_BUF_PER_PAGE) {
+ 		dma_addr_t page_phys, buf_phys;
+ 		struct page *page;
+ 		void *buf;
+@@ -371,28 +394,31 @@ mtk_wed_tx_buffer_alloc(struct mtk_wed_d
+ 		buf_phys = page_phys;
+ 
+ 		for (s = 0; s < MTK_WED_BUF_PER_PAGE; s++) {
+-			u32 txd_size;
+-			u32 ctrl;
+-
+-			txd_size = dev->wlan.init_buf(buf, buf_phys, token++);
++			struct mtk_wdma_desc *desc = desc_ptr;
+ 
+ 			desc->buf0 = cpu_to_le32(buf_phys);
+-			desc->buf1 = cpu_to_le32(buf_phys + txd_size);
++			if (!mtk_wed_is_v3_or_greater(dev->hw)) {
++				u32 txd_size, ctrl;
+ 
+-			if (mtk_wed_is_v1(dev->hw))
+-				ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
+-				       FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
+-						  MTK_WED_BUF_SIZE - txd_size) |
+-				       MTK_WDMA_DESC_CTRL_LAST_SEG1;
+-			else
+-				ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size) |
+-				       FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
+-						  MTK_WED_BUF_SIZE - txd_size) |
+-				       MTK_WDMA_DESC_CTRL_LAST_SEG0;
+-			desc->ctrl = cpu_to_le32(ctrl);
+-			desc->info = 0;
+-			desc++;
++				txd_size = dev->wlan.init_buf(buf, buf_phys,
++							      token++);
++				desc->buf1 = cpu_to_le32(buf_phys + txd_size);
++				ctrl = FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN0, txd_size);
++				if (mtk_wed_is_v1(dev->hw))
++					ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG1 |
++						FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1,
++							   MTK_WED_BUF_SIZE - txd_size);
++				else
++					ctrl |= MTK_WDMA_DESC_CTRL_LAST_SEG0 |
++						FIELD_PREP(MTK_WDMA_DESC_CTRL_LEN1_V2,
++							   MTK_WED_BUF_SIZE - txd_size);
++				desc->ctrl = cpu_to_le32(ctrl);
++				desc->info = 0;
++			} else {
++				desc->ctrl = cpu_to_le32(token << 16);
++			}
+ 
++			desc_ptr += desc_size;
+ 			buf += MTK_WED_BUF_SIZE;
+ 			buf_phys += MTK_WED_BUF_SIZE;
+ 		}
+@@ -408,31 +434,31 @@ static void
+ mtk_wed_free_tx_buffer(struct mtk_wed_device *dev)
+ {
+ 	struct mtk_wed_buf *page_list = dev->tx_buf_ring.pages;
+-	struct mtk_wdma_desc *desc = dev->tx_buf_ring.desc;
+-	int page_idx;
+-	int i;
++	struct mtk_wed_hw *hw = dev->hw;
++	int i, page_idx = 0;
+ 
+ 	if (!page_list)
+ 		return;
+ 
+-	if (!desc)
++	if (!dev->tx_buf_ring.desc)
+ 		goto free_pagelist;
+ 
+-	for (i = 0, page_idx = 0; i < dev->tx_buf_ring.size;
+-	     i += MTK_WED_BUF_PER_PAGE) {
+-		dma_addr_t buf_addr = page_list[page_idx].phy_addr;
++	for (i = 0; i < dev->tx_buf_ring.size; i += MTK_WED_BUF_PER_PAGE) {
++		dma_addr_t page_phy = page_list[page_idx].phy_addr;
+ 		void *page = page_list[page_idx++].p;
+ 
+ 		if (!page)
+ 			break;
+ 
+-		dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
++		dma_unmap_page(dev->hw->dev, page_phy, PAGE_SIZE,
+ 			       DMA_BIDIRECTIONAL);
+ 		__free_page(page);
+ 	}
+ 
+-	dma_free_coherent(dev->hw->dev, dev->tx_buf_ring.size * sizeof(*desc),
+-			  desc, dev->tx_buf_ring.desc_phys);
++	dma_free_coherent(dev->hw->dev,
++			  dev->tx_buf_ring.size * hw->soc->tx_ring_desc_size,
++			  dev->tx_buf_ring.desc,
++			  dev->tx_buf_ring.desc_phys);
+ 
+ free_pagelist:
+ 	kfree(page_list);
+@@ -517,13 +543,23 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
+ {
+ 	u32 mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
+ 
+-	if (mtk_wed_is_v1(dev->hw))
++	switch (dev->hw->version) {
++	case 1:
+ 		mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
+-	else
++		break;
++	case 2:
+ 		mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
+ 			MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
+ 			MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
+ 			MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
++		break;
++	case 3:
++		mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
++		       MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
++		break;
++	default:
++		break;
++	}
+ 
+ 	if (!dev->hw->num_flows)
+ 		mask &= ~MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
+@@ -535,6 +571,9 @@ mtk_wed_set_ext_int(struct mtk_wed_devic
+ static void
+ mtk_wed_set_512_support(struct mtk_wed_device *dev, bool enable)
+ {
++	if (!mtk_wed_is_v2(dev->hw))
++		return;
++
+ 	if (enable) {
+ 		wed_w32(dev, MTK_WED_TXDP_CTRL, MTK_WED_TXDP_DW9_OVERWR);
+ 		wed_w32(dev, MTK_WED_TXP_DW1,
+@@ -609,6 +648,14 @@ mtk_wed_dma_disable(struct mtk_wed_devic
+ 			MTK_WED_WPDMA_RX_D_RX_DRV_EN);
+ 		wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
+ 			MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
++
++		if (mtk_wed_is_v3_or_greater(dev->hw) &&
++		    mtk_wed_get_rx_capa(dev)) {
++			wdma_clr(dev, MTK_WDMA_PREF_TX_CFG,
++				 MTK_WDMA_PREF_TX_CFG_PREF_EN);
++			wdma_clr(dev, MTK_WDMA_PREF_RX_CFG,
++				 MTK_WDMA_PREF_RX_CFG_PREF_EN);
++		}
+ 	}
+ 
+ 	mtk_wed_set_512_support(dev, false);
+@@ -651,6 +698,14 @@ mtk_wed_deinit(struct mtk_wed_device *de
+ 		MTK_WED_CTRL_RX_ROUTE_QM_EN |
+ 		MTK_WED_CTRL_WED_RX_BM_EN |
+ 		MTK_WED_CTRL_RX_RRO_QM_EN);
++
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
++		wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_TX_AMSDU);
++		wed_clr(dev, MTK_WED_PCIE_INT_CTRL,
++			MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
++			MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER);
++	}
+ }
+ 
+ static void
+@@ -700,21 +755,37 @@ mtk_wed_detach(struct mtk_wed_device *de
+ 	mutex_unlock(&hw_lock);
+ }
+ 
+-#define PCIE_BASE_ADDR0		0x11280000
+ static void
+ mtk_wed_bus_init(struct mtk_wed_device *dev)
+ {
+ 	switch (dev->wlan.bus_type) {
+ 	case MTK_WED_BUS_PCIE: {
+ 		struct device_node *np = dev->hw->eth->dev->of_node;
+-		struct regmap *regs;
+ 
+-		regs = syscon_regmap_lookup_by_phandle(np,
+-						       "mediatek,wed-pcie");
+-		if (IS_ERR(regs))
+-			break;
++		if (mtk_wed_is_v2(dev->hw)) {
++			struct regmap *regs;
++
++			regs = syscon_regmap_lookup_by_phandle(np,
++							       "mediatek,wed-pcie");
++			if (IS_ERR(regs))
++				break;
+ 
+-		regmap_update_bits(regs, 0, BIT(0), BIT(0));
++			regmap_update_bits(regs, 0, BIT(0), BIT(0));
++		}
++
++		if (dev->wlan.msi) {
++			wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
++				dev->hw->pcie_base | 0xc08);
++			wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
++				dev->hw->pcie_base | 0xc04);
++			wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(8));
++		} else {
++			wed_w32(dev, MTK_WED_PCIE_CFG_INTM,
++				dev->hw->pcie_base | 0x180);
++			wed_w32(dev, MTK_WED_PCIE_CFG_BASE,
++				dev->hw->pcie_base | 0x184);
++			wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
++		}
+ 
+ 		wed_w32(dev, MTK_WED_PCIE_INT_CTRL,
+ 			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_POLL_EN, 2));
+@@ -722,19 +793,9 @@ mtk_wed_bus_init(struct mtk_wed_device *
+ 		/* pcie interrupt control: pola/source selection */
+ 		wed_set(dev, MTK_WED_PCIE_INT_CTRL,
+ 			MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA |
+-			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL, 1));
+-		wed_r32(dev, MTK_WED_PCIE_INT_CTRL);
+-
+-		wed_w32(dev, MTK_WED_PCIE_CFG_INTM, PCIE_BASE_ADDR0 | 0x180);
+-		wed_w32(dev, MTK_WED_PCIE_CFG_BASE, PCIE_BASE_ADDR0 | 0x184);
+-
+-		/* pcie interrupt status trigger register */
+-		wed_w32(dev, MTK_WED_PCIE_INT_TRIGGER, BIT(24));
+-		wed_r32(dev, MTK_WED_PCIE_INT_TRIGGER);
+-
+-		/* pola setting */
+-		wed_set(dev, MTK_WED_PCIE_INT_CTRL,
+-			MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA);
++			MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER  |
++			FIELD_PREP(MTK_WED_PCIE_INT_CTRL_SRC_SEL,
++				   dev->hw->index));
+ 		break;
+ 	}
+ 	case MTK_WED_BUS_AXI:
+@@ -772,18 +833,19 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+ static void
+ mtk_wed_hw_init_early(struct mtk_wed_device *dev)
+ {
+-	u32 mask, set;
++	u32 set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2);
++	u32 mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE;
+ 
+ 	mtk_wed_deinit(dev);
+ 	mtk_wed_reset(dev, MTK_WED_RESET_WED);
+ 	mtk_wed_set_wpdma(dev);
+ 
+-	mask = MTK_WED_WDMA_GLO_CFG_BT_SIZE |
+-	       MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
+-	       MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
+-	set = FIELD_PREP(MTK_WED_WDMA_GLO_CFG_BT_SIZE, 2) |
+-	      MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
+-	      MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
++	if (!mtk_wed_is_v3_or_greater(dev->hw)) {
++		mask |= MTK_WED_WDMA_GLO_CFG_DYNAMIC_DMAD_RECYCLE |
++			MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE;
++		set |= MTK_WED_WDMA_GLO_CFG_DYNAMIC_SKIP_DMAD_PREP |
++		       MTK_WED_WDMA_GLO_CFG_IDLE_DMAD_SUPPLY;
++	}
+ 	wed_m32(dev, MTK_WED_WDMA_GLO_CFG, mask, set);
+ 
+ 	if (mtk_wed_is_v1(dev->hw)) {
+@@ -931,11 +993,18 @@ mtk_wed_route_qm_hw_init(struct mtk_wed_
+ 	}
+ 
+ 	/* configure RX_ROUTE_QM */
+-	wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
+-	wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
+-	wed_set(dev, MTK_WED_RTQM_GLO_CFG,
+-		FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT, 0x3 + dev->hw->index));
+-	wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
++	if (mtk_wed_is_v2(dev->hw)) {
++		wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
++		wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_TXDMAD_FPORT);
++		wed_set(dev, MTK_WED_RTQM_GLO_CFG,
++			FIELD_PREP(MTK_WED_RTQM_TXDMAD_FPORT,
++				   0x3 + dev->hw->index));
++		wed_clr(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
++	} else {
++		wed_set(dev, MTK_WED_RTQM_ENQ_CFG0,
++			FIELD_PREP(MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT,
++				   0x3 + dev->hw->index));
++	}
+ 	/* enable RX_ROUTE_QM */
+ 	wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
+ }
+@@ -948,22 +1017,30 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 
+ 	dev->init_done = true;
+ 	mtk_wed_set_ext_int(dev, false);
+-	wed_w32(dev, MTK_WED_TX_BM_CTRL,
+-		MTK_WED_TX_BM_CTRL_PAUSE |
+-		FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
+-			   dev->tx_buf_ring.size / 128) |
+-		FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
+-			   MTK_WED_TX_RING_SIZE / 256));
+ 
+ 	wed_w32(dev, MTK_WED_TX_BM_BASE, dev->tx_buf_ring.desc_phys);
+-
+ 	wed_w32(dev, MTK_WED_TX_BM_BUF_LEN, MTK_WED_PKT_SIZE);
+ 
+ 	if (mtk_wed_is_v1(dev->hw)) {
++		wed_w32(dev, MTK_WED_TX_BM_CTRL,
++			MTK_WED_TX_BM_CTRL_PAUSE |
++			FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
++				   dev->tx_buf_ring.size / 128) |
++			FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
++				   MTK_WED_TX_RING_SIZE / 256));
+ 		wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
+ 			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO, 1) |
+ 			MTK_WED_TX_BM_DYN_THR_HI);
+-	} else {
++	} else if (mtk_wed_is_v2(dev->hw)) {
++		wed_w32(dev, MTK_WED_TX_BM_CTRL,
++			MTK_WED_TX_BM_CTRL_PAUSE |
++			FIELD_PREP(MTK_WED_TX_BM_CTRL_VLD_GRP_NUM,
++				   dev->tx_buf_ring.size / 128) |
++			FIELD_PREP(MTK_WED_TX_BM_CTRL_RSV_GRP_NUM,
++				   MTK_WED_TX_RING_SIZE / 256));
++		wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
++			FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
++			MTK_WED_TX_TKID_DYN_THR_HI);
+ 		wed_w32(dev, MTK_WED_TX_BM_DYN_THR,
+ 			FIELD_PREP(MTK_WED_TX_BM_DYN_THR_LO_V2, 0) |
+ 			MTK_WED_TX_BM_DYN_THR_HI_V2);
+@@ -973,9 +1050,6 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 				   dev->tx_buf_ring.size / 128) |
+ 			FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM,
+ 				   dev->tx_buf_ring.size / 128));
+-		wed_w32(dev, MTK_WED_TX_TKID_DYN_THR,
+-			FIELD_PREP(MTK_WED_TX_TKID_DYN_THR_LO, 0) |
+-			MTK_WED_TX_TKID_DYN_THR_HI);
+ 	}
+ 
+ 	wed_w32(dev, dev->hw->soc->regmap.tx_bm_tkid,
+@@ -985,26 +1059,62 @@ mtk_wed_hw_init(struct mtk_wed_device *d
+ 
+ 	mtk_wed_reset(dev, MTK_WED_RESET_TX_BM);
+ 
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		/* switch to new bm architecture */
++		wed_clr(dev, MTK_WED_TX_BM_CTRL,
++			MTK_WED_TX_BM_CTRL_LEGACY_EN);
++
++		wed_w32(dev, MTK_WED_TX_TKID_CTRL,
++			MTK_WED_TX_TKID_CTRL_PAUSE |
++			FIELD_PREP(MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3,
++				   dev->wlan.nbuf / 128) |
++			FIELD_PREP(MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3,
++				   dev->wlan.nbuf / 128));
++		/* return SKBID + SDP back to bm */
++		wed_set(dev, MTK_WED_TX_TKID_CTRL,
++			MTK_WED_TX_TKID_CTRL_FREE_FORMAT);
++
++		wed_w32(dev, MTK_WED_TX_BM_INIT_PTR,
++			MTK_WED_TX_BM_PKT_CNT |
++			MTK_WED_TX_BM_INIT_SW_TAIL_IDX);
++	}
++
+ 	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_set(dev, MTK_WED_CTRL,
+ 			MTK_WED_CTRL_WED_TX_BM_EN |
+ 			MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
+-	} else {
+-		wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
+-		if (mtk_wed_get_rx_capa(dev)) {
+-			/* rx hw init */
+-			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
+-				MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
+-				MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
+-			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
+-
+-			mtk_wed_rx_buffer_hw_init(dev);
+-			mtk_wed_rro_hw_init(dev);
+-			mtk_wed_route_qm_hw_init(dev);
+-		}
++	} else if (mtk_wed_get_rx_capa(dev)) {
++		/* rx hw init */
++		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
++			MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
++			MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
++		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX, 0);
++
++		/* reset prefetch index of ring */
++		wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
++			MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
++		wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX,
++			MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
++
++		wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
++			MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
++		wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX,
++			MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR);
++
++		/* reset prefetch FIFO of ring */
++		wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG,
++			MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR |
++			MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR);
++		wed_w32(dev, MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG, 0);
++
++		mtk_wed_rx_buffer_hw_init(dev);
++		mtk_wed_rro_hw_init(dev);
++		mtk_wed_route_qm_hw_init(dev);
+ 	}
+ 
+ 	wed_clr(dev, MTK_WED_TX_BM_CTRL, MTK_WED_TX_BM_CTRL_PAUSE);
++	if (!mtk_wed_is_v1(dev->hw))
++		wed_clr(dev, MTK_WED_TX_TKID_CTRL, MTK_WED_TX_TKID_CTRL_PAUSE);
+ }
+ 
+ static void
+@@ -1302,6 +1412,24 @@ mtk_wed_wdma_tx_ring_setup(struct mtk_we
+ 					 dev->hw->soc->wdma_desc_size, true))
+ 		return -ENOMEM;
+ 
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		struct mtk_wdma_desc *desc = wdma->desc;
++		int i;
++
++		for (i = 0; i < MTK_WED_WDMA_RING_SIZE; i++) {
++			desc->buf0 = 0;
++			desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
++			desc->buf1 = 0;
++			desc->info = cpu_to_le32(MTK_WDMA_TXD0_DESC_INFO_DMA_DONE);
++			desc++;
++			desc->buf0 = 0;
++			desc->ctrl = cpu_to_le32(MTK_WDMA_DESC_CTRL_DMA_DONE);
++			desc->buf1 = 0;
++			desc->info = cpu_to_le32(MTK_WDMA_TXD1_DESC_INFO_DMA_DONE);
++			desc++;
++		}
++	}
++
+ 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_BASE,
+ 		 wdma->desc_phys);
+ 	wdma_w32(dev, MTK_WDMA_RING_TX(idx) + MTK_WED_RING_OFS_COUNT,
+@@ -1367,6 +1495,9 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+ 
+ 		wed_clr(dev, MTK_WED_WDMA_INT_CTRL, wdma_mask);
+ 	} else {
++		if (mtk_wed_is_v3_or_greater(dev->hw))
++			wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_TKID_ALI_EN);
++
+ 		/* initail tx interrupt trigger */
+ 		wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_TX,
+ 			MTK_WED_WPDMA_INT_CTRL_TX0_DONE_EN |
+@@ -1419,33 +1550,60 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ {
+ 	int i;
+ 
+-	wed_set(dev, MTK_WED_WPDMA_INT_CTRL, MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
++	if (!mtk_wed_is_v3_or_greater(dev->hw)) {
++		wed_set(dev, MTK_WED_WPDMA_INT_CTRL,
++			MTK_WED_WPDMA_INT_CTRL_SUBRT_ADV);
++		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
++			MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
++			MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
++		wdma_set(dev, MTK_WDMA_GLO_CFG,
++			 MTK_WDMA_GLO_CFG_TX_DMA_EN |
++			 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
++			 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
++		wed_set(dev, MTK_WED_WPDMA_CTRL, MTK_WED_WPDMA_CTRL_SDL1_FIXED);
++	} else {
++		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
++			MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
++			MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN |
++			MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR);
++		wdma_set(dev, MTK_WDMA_GLO_CFG, MTK_WDMA_GLO_CFG_TX_DMA_EN);
++	}
+ 
+ 	wed_set(dev, MTK_WED_GLO_CFG,
+ 		MTK_WED_GLO_CFG_TX_DMA_EN |
+ 		MTK_WED_GLO_CFG_RX_DMA_EN);
+-	wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
+-		MTK_WED_WPDMA_GLO_CFG_TX_DRV_EN |
+-		MTK_WED_WPDMA_GLO_CFG_RX_DRV_EN);
++
+ 	wed_set(dev, MTK_WED_WDMA_GLO_CFG,
+ 		MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
+ 
+-	wdma_set(dev, MTK_WDMA_GLO_CFG,
+-		 MTK_WDMA_GLO_CFG_TX_DMA_EN |
+-		 MTK_WDMA_GLO_CFG_RX_INFO1_PRERES |
+-		 MTK_WDMA_GLO_CFG_RX_INFO2_PRERES);
+-
+ 	if (mtk_wed_is_v1(dev->hw)) {
+ 		wdma_set(dev, MTK_WDMA_GLO_CFG,
+ 			 MTK_WDMA_GLO_CFG_RX_INFO3_PRERES);
+ 		return;
+ 	}
+ 
+-	wed_set(dev, MTK_WED_WPDMA_CTRL,
+-		MTK_WED_WPDMA_CTRL_SDL1_FIXED);
+ 	wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
+ 		MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_PKT_PROC |
+ 		MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC);
++
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
++			FIELD_PREP(MTK_WED_WDMA_RX_PREF_BURST_SIZE, 0x10) |
++			FIELD_PREP(MTK_WED_WDMA_RX_PREF_LOW_THRES, 0x8));
++		wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
++			MTK_WED_WDMA_RX_PREF_DDONE2_EN);
++		wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG, MTK_WED_WDMA_RX_PREF_EN);
++
++		wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
++			MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST);
++		wed_set(dev, MTK_WED_WPDMA_GLO_CFG,
++			MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK |
++			MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK |
++			MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
++
++		wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
++	}
++
+ 	wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
+ 		MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP |
+ 		MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV);
+@@ -1457,11 +1615,22 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ 		MTK_WED_WDMA_GLO_CFG_TX_DRV_EN |
+ 		MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK);
+ 
++	wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RXD_READ_LEN);
+ 	wed_set(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
+ 		MTK_WED_WPDMA_RX_D_RX_DRV_EN |
+ 		FIELD_PREP(MTK_WED_WPDMA_RX_D_RXD_READ_LEN, 0x18) |
+-		FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL,
+-			   0x2));
++		FIELD_PREP(MTK_WED_WPDMA_RX_D_INIT_PHASE_RXEN_SEL, 0x2));
++
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		wed_set(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
++			MTK_WED_WPDMA_RX_D_PREF_EN |
++			FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE, 0x10) |
++			FIELD_PREP(MTK_WED_WPDMA_RX_D_PREF_LOW_THRES, 0x8));
++
++		wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
++		wdma_set(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
++		wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
++	}
+ 
+ 	for (i = 0; i < MTK_WED_RX_QUEUES; i++)
+ 		mtk_wed_check_wfdma_rx_fill(dev, i);
+@@ -1501,6 +1670,12 @@ mtk_wed_start(struct mtk_wed_device *dev
+ 		wed_r32(dev, MTK_WED_EXT_INT_MASK1);
+ 		wed_r32(dev, MTK_WED_EXT_INT_MASK2);
+ 
++		if (mtk_wed_is_v3_or_greater(dev->hw)) {
++			wed_w32(dev, MTK_WED_EXT_INT_MASK3,
++				MTK_WED_EXT_INT_STATUS_WPDMA_MID_RDY);
++			wed_r32(dev, MTK_WED_EXT_INT_MASK3);
++		}
++
+ 		if (mtk_wed_rro_cfg(dev))
+ 			return;
+ 	}
+@@ -1552,6 +1727,7 @@ mtk_wed_attach(struct mtk_wed_device *de
+ 	dev->irq = hw->irq;
+ 	dev->wdma_idx = hw->index;
+ 	dev->version = hw->version;
++	dev->hw->pcie_base = mtk_wed_get_pcie_base(dev);
+ 
+ 	if (hw->eth->dma_dev == hw->eth->dev &&
+ 	    of_dma_is_coherent(hw->eth->dev->of_node))
+@@ -1619,6 +1795,23 @@ mtk_wed_tx_ring_setup(struct mtk_wed_dev
+ 	ring->reg_base = MTK_WED_RING_TX(idx);
+ 	ring->wpdma = regs;
+ 
++	if (mtk_wed_is_v3_or_greater(dev->hw) && idx == 1) {
++		/* reset prefetch index */
++		wed_set(dev, MTK_WED_WDMA_RX_PREF_CFG,
++			MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
++			MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
++
++		wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
++			MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR |
++			MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR);
++
++		/* reset prefetch FIFO */
++		wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG,
++			MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR |
++			MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR);
++		wed_w32(dev, MTK_WED_WDMA_RX_PREF_FIFO_CFG, 0);
++	}
++
+ 	/* WED -> WPDMA */
+ 	wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_BASE, ring->desc_phys);
+ 	wpdma_tx_w32(dev, idx, MTK_WED_RING_OFS_COUNT, MTK_WED_TX_RING_SIZE);
+@@ -1693,15 +1886,13 @@ mtk_wed_rx_ring_setup(struct mtk_wed_dev
+ static u32
+ mtk_wed_irq_get(struct mtk_wed_device *dev, u32 mask)
+ {
+-	u32 val, ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
++	u32 val, ext_mask;
+ 
+-	if (mtk_wed_is_v1(dev->hw))
+-		ext_mask |= MTK_WED_EXT_INT_STATUS_TX_DRV_R_RESP_ERR;
++	if (mtk_wed_is_v3_or_greater(dev->hw))
++		ext_mask = MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
++			   MTK_WED_EXT_INT_STATUS_TKID_WO_PYLD;
+ 	else
+-		ext_mask |= MTK_WED_EXT_INT_STATUS_RX_FBUF_LO_TH |
+-			    MTK_WED_EXT_INT_STATUS_RX_FBUF_HI_TH |
+-			    MTK_WED_EXT_INT_STATUS_RX_DRV_COHERENT |
+-			    MTK_WED_EXT_INT_STATUS_TX_DMA_W_RESP_ERR;
++		ext_mask = MTK_WED_EXT_INT_STATUS_ERROR_MASK;
+ 
+ 	val = wed_r32(dev, MTK_WED_EXT_INT_STATUS);
+ 	wed_w32(dev, MTK_WED_EXT_INT_STATUS, val);
+@@ -1942,6 +2133,9 @@ void mtk_wed_add_hw(struct device_node *
+ 	case 2:
+ 		hw->soc = &mt7986_data;
+ 		break;
++	case 3:
++		hw->soc = &mt7988_data;
++		break;
+ 	default:
+ 	case 1:
+ 		hw->mirror = syscon_regmap_lookup_by_phandle(eth_np,
+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
+@@ -9,6 +9,8 @@
+ #include <linux/regmap.h>
+ #include <linux/netdevice.h>
+ 
++#include "mtk_wed_regs.h"
++
+ struct mtk_eth;
+ struct mtk_wed_wo;
+ 
+@@ -19,6 +21,7 @@ struct mtk_wed_soc_data {
+ 		u32 reset_idx_tx_mask;
+ 		u32 reset_idx_rx_mask;
+ 	} regmap;
++	u32 tx_ring_desc_size;
+ 	u32 wdma_desc_size;
+ };
+ 
+@@ -35,6 +38,7 @@ struct mtk_wed_hw {
+ 	struct dentry *debugfs_dir;
+ 	struct mtk_wed_device *wed_dev;
+ 	struct mtk_wed_wo *wed_wo;
++	u32 pcie_base;
+ 	u32 debugfs_reg;
+ 	u32 num_flows;
+ 	u8 version;
+@@ -61,6 +65,16 @@ static inline bool mtk_wed_is_v2(struct
+ 	return hw->version == 2;
+ }
+ 
++static inline bool mtk_wed_is_v3(struct mtk_wed_hw *hw)
++{
++	return hw->version == 3;
++}
++
++static inline bool mtk_wed_is_v3_or_greater(struct mtk_wed_hw *hw)
++{
++	return hw->version > 2;
++}
++
+ static inline void
+ wed_w32(struct mtk_wed_device *dev, u32 reg, u32 val)
+ {
+@@ -143,6 +157,21 @@ wpdma_txfree_w32(struct mtk_wed_device *
+ 	writel(val, dev->txfree_ring.wpdma + reg);
+ }
+ 
++static inline u32 mtk_wed_get_pcie_base(struct mtk_wed_device *dev)
++{
++	if (!mtk_wed_is_v3_or_greater(dev->hw))
++		return MTK_WED_PCIE_BASE;
++
++	switch (dev->hw->index) {
++	case 1:
++		return MTK_WED_PCIE_BASE1;
++	case 2:
++		return MTK_WED_PCIE_BASE2;
++	default:
++		return MTK_WED_PCIE_BASE0;
++	}
++}
++
+ void mtk_wed_add_hw(struct device_node *np, struct mtk_eth *eth,
+ 		    void __iomem *wdma, phys_addr_t wdma_phy,
+ 		    int index);
+--- a/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_mcu.c
+@@ -331,10 +331,22 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 		wo->hw->index + 1);
+ 
+ 	/* load firmware */
+-	if (of_device_is_compatible(wo->hw->node, "mediatek,mt7981-wed"))
+-		fw_name = MT7981_FIRMWARE_WO;
+-	else
+-		fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1 : MT7986_FIRMWARE_WO0;
++	switch (wo->hw->version) {
++	case 2:
++		if (of_device_is_compatible(wo->hw->node,
++					    "mediatek,mt7981-wed"))
++			fw_name = MT7981_FIRMWARE_WO;
++		else
++			fw_name = wo->hw->index ? MT7986_FIRMWARE_WO1
++						: MT7986_FIRMWARE_WO0;
++		break;
++	case 3:
++		fw_name = wo->hw->index ? MT7988_FIRMWARE_WO1
++					: MT7988_FIRMWARE_WO0;
++		break;
++	default:
++		return -EINVAL;
++	}
+ 
+ 	ret = request_firmware(&fw, fw_name, wo->hw->dev);
+ 	if (ret)
+@@ -355,15 +367,16 @@ mtk_wed_mcu_load_firmware(struct mtk_wed
+ 	}
+ 
+ 	/* set the start address */
+-	boot_cr = wo->hw->index ? MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR
+-				: MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
++	if (!mtk_wed_is_v3_or_greater(wo->hw) && wo->hw->index)
++		boot_cr = MTK_WO_MCU_CFG_LS_WA_BOOT_ADDR_ADDR;
++	else
++		boot_cr = MTK_WO_MCU_CFG_LS_WM_BOOT_ADDR_ADDR;
+ 	wo_w32(wo, boot_cr, mem_region[MTK_WED_WO_REGION_EMI].phy_addr >> 16);
+ 	/* wo firmware reset */
+ 	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCCR_CLR_ADDR, 0xc00);
+ 
+-	val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR);
+-	val |= wo->hw->index ? MTK_WO_MCU_CFG_LS_WF_WM_WA_WA_CPU_RSTB_MASK
+-			     : MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
++	val = wo_r32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR) |
++	      MTK_WO_MCU_CFG_LS_WF_WM_WA_WM_CPU_RSTB_MASK;
+ 	wo_w32(wo, MTK_WO_MCU_CFG_LS_WF_MCU_CFG_WM_WA_ADDR, val);
+ out:
+ 	release_firmware(fw);
+@@ -398,3 +411,5 @@ int mtk_wed_mcu_init(struct mtk_wed_wo *
+ MODULE_FIRMWARE(MT7981_FIRMWARE_WO);
+ MODULE_FIRMWARE(MT7986_FIRMWARE_WO0);
+ MODULE_FIRMWARE(MT7986_FIRMWARE_WO1);
++MODULE_FIRMWARE(MT7988_FIRMWARE_WO0);
++MODULE_FIRMWARE(MT7988_FIRMWARE_WO1);
+--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
+@@ -13,6 +13,9 @@
+ #define MTK_WDMA_DESC_CTRL_LAST_SEG0		BIT(30)
+ #define MTK_WDMA_DESC_CTRL_DMA_DONE		BIT(31)
+ 
++#define MTK_WDMA_TXD0_DESC_INFO_DMA_DONE	BIT(29)
++#define MTK_WDMA_TXD1_DESC_INFO_DMA_DONE	BIT(31)
++
+ struct mtk_wdma_desc {
+ 	__le32 buf0;
+ 	__le32 ctrl;
+@@ -37,6 +40,7 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RESET_WDMA_INT_AGENT			BIT(19)
+ #define MTK_WED_RESET_RX_RRO_QM				BIT(20)
+ #define MTK_WED_RESET_RX_ROUTE_QM			BIT(21)
++#define MTK_WED_RESET_TX_AMSDU				BIT(22)
+ #define MTK_WED_RESET_WED				BIT(31)
+ 
+ #define MTK_WED_CTRL					0x00c
+@@ -44,6 +48,9 @@ struct mtk_wdma_desc {
+ #define MTK_WED_CTRL_WPDMA_INT_AGENT_BUSY		BIT(1)
+ #define MTK_WED_CTRL_WDMA_INT_AGENT_EN			BIT(2)
+ #define MTK_WED_CTRL_WDMA_INT_AGENT_BUSY		BIT(3)
++#define MTK_WED_CTRL_WED_RX_IND_CMD_EN			BIT(5)
++#define MTK_WED_CTRL_WED_RX_PG_BM_EN			BIT(6)
++#define MTK_WED_CTRL_WED_RX_PG_BM_BUSY			BIT(7)
+ #define MTK_WED_CTRL_WED_TX_BM_EN			BIT(8)
+ #define MTK_WED_CTRL_WED_TX_BM_BUSY			BIT(9)
+ #define MTK_WED_CTRL_WED_TX_FREE_AGENT_EN		BIT(10)
+@@ -54,9 +61,14 @@ struct mtk_wdma_desc {
+ #define MTK_WED_CTRL_RX_RRO_QM_BUSY			BIT(15)
+ #define MTK_WED_CTRL_RX_ROUTE_QM_EN			BIT(16)
+ #define MTK_WED_CTRL_RX_ROUTE_QM_BUSY			BIT(17)
++#define MTK_WED_CTRL_TX_TKID_ALI_EN			BIT(20)
++#define MTK_WED_CTRL_TX_TKID_ALI_BUSY			BIT(21)
++#define MTK_WED_CTRL_TX_AMSDU_EN			BIT(22)
++#define MTK_WED_CTRL_TX_AMSDU_BUSY			BIT(23)
+ #define MTK_WED_CTRL_FINAL_DIDX_READ			BIT(24)
+ #define MTK_WED_CTRL_ETH_DMAD_FMT			BIT(25)
+ #define MTK_WED_CTRL_MIB_READ_CLEAR			BIT(28)
++#define MTK_WED_CTRL_FLD_MIB_RD_CLR			BIT(28)
+ 
+ #define MTK_WED_EXT_INT_STATUS				0x020
+ #define MTK_WED_EXT_INT_STATUS_TF_LEN_ERR		BIT(0)
+@@ -89,6 +101,7 @@ struct mtk_wdma_desc {
+ #define MTK_WED_EXT_INT_MASK				0x028
+ #define MTK_WED_EXT_INT_MASK1				0x02c
+ #define MTK_WED_EXT_INT_MASK2				0x030
++#define MTK_WED_EXT_INT_MASK3				0x034
+ 
+ #define MTK_WED_STATUS					0x060
+ #define MTK_WED_STATUS_TX				GENMASK(15, 8)
+@@ -96,9 +109,14 @@ struct mtk_wdma_desc {
+ #define MTK_WED_TX_BM_CTRL				0x080
+ #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM			GENMASK(6, 0)
+ #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM			GENMASK(22, 16)
++#define MTK_WED_TX_BM_CTRL_LEGACY_EN			BIT(26)
++#define MTK_WED_TX_TKID_CTRL_FREE_FORMAT		BIT(27)
+ #define MTK_WED_TX_BM_CTRL_PAUSE			BIT(28)
+ 
+ #define MTK_WED_TX_BM_BASE				0x084
++#define MTK_WED_TX_BM_INIT_PTR				0x088
++#define MTK_WED_TX_BM_SW_TAIL_IDX			GENMASK(16, 0)
++#define MTK_WED_TX_BM_INIT_SW_TAIL_IDX			BIT(16)
+ 
+ #define MTK_WED_TX_BM_TKID_START			GENMASK(15, 0)
+ #define MTK_WED_TX_BM_TKID_END				GENMASK(31, 16)
+@@ -122,6 +140,9 @@ struct mtk_wdma_desc {
+ #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM		GENMASK(22, 16)
+ #define MTK_WED_TX_TKID_CTRL_PAUSE			BIT(28)
+ 
++#define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3		GENMASK(7, 0)
++#define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3		GENMASK(23, 16)
++
+ #define MTK_WED_TX_TKID_DYN_THR				0x0e0
+ #define MTK_WED_TX_TKID_DYN_THR_LO			GENMASK(6, 0)
+ #define MTK_WED_TX_TKID_DYN_THR_HI			GENMASK(22, 16)
+@@ -199,12 +220,15 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_PKT_PROC	BIT(5)
+ #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R0_CRX_SYNC	BIT(6)
+ #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_R1_CRX_SYNC	BIT(7)
+-#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER	GENMASK(18, 16)
++#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_VER	GENMASK(15, 12)
++#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4	BIT(18)
+ #define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNSUPPORT_FMT	BIT(19)
+-#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_UEVENT_PKT_FMT_CHK BIT(20)
++#define MTK_WED_WPDMA_GLO_CFG_RX_DRV_EVENT_PKT_FMT_CHK	BIT(20)
+ #define MTK_WED_WPDMA_GLO_CFG_RX_DDONE2_WR		BIT(21)
+ #define MTK_WED_WPDMA_GLO_CFG_TX_TKID_KEEP		BIT(24)
++#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK_LAST		BIT(25)
+ #define MTK_WED_WPDMA_GLO_CFG_TX_DMAD_DW3_PREV		BIT(28)
++#define MTK_WED_WPDMA_GLO_CFG_TX_DDONE_CHK		BIT(30)
+ 
+ #define MTK_WED_WPDMA_RESET_IDX				0x50c
+ #define MTK_WED_WPDMA_RESET_IDX_TX			GENMASK(3, 0)
+@@ -250,9 +274,10 @@ struct mtk_wdma_desc {
+ #define MTK_WED_PCIE_INT_TRIGGER_STATUS			BIT(16)
+ 
+ #define MTK_WED_PCIE_INT_CTRL				0x57c
+-#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA		BIT(20)
+-#define MTK_WED_PCIE_INT_CTRL_SRC_SEL			GENMASK(17, 16)
+ #define MTK_WED_PCIE_INT_CTRL_POLL_EN			GENMASK(13, 12)
++#define MTK_WED_PCIE_INT_CTRL_SRC_SEL			GENMASK(17, 16)
++#define MTK_WED_PCIE_INT_CTRL_MSK_EN_POLA		BIT(20)
++#define MTK_WED_PCIE_INT_CTRL_MSK_IRQ_FILTER		BIT(21)
+ 
+ #define MTK_WED_WPDMA_CFG_BASE				0x580
+ #define MTK_WED_WPDMA_CFG_INT_MASK			0x584
+@@ -286,6 +311,20 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WPDMA_RX_D_PROCESSED_MIB(_n)		(0x784 + (_n) * 4)
+ #define MTK_WED_WPDMA_RX_D_COHERENT_MIB			0x78c
+ 
++#define MTK_WED_WPDMA_RX_D_PREF_CFG			0x7b4
++#define MTK_WED_WPDMA_RX_D_PREF_EN			BIT(0)
++#define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE		GENMASK(12, 8)
++#define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES		GENMASK(21, 16)
++
++#define MTK_WED_WPDMA_RX_D_PREF_RX0_SIDX		0x7b8
++#define MTK_WED_WPDMA_RX_D_PREF_SIDX_IDX_CLR		BIT(15)
++
++#define MTK_WED_WPDMA_RX_D_PREF_RX1_SIDX		0x7bc
++
++#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG		0x7c0
++#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R0_CLR		BIT(0)
++#define MTK_WED_WPDMA_RX_D_PREF_FIFO_CFG_R1_CLR		BIT(16)
++
+ #define MTK_WED_WDMA_RING_TX				0x800
+ 
+ #define MTK_WED_WDMA_TX_MIB				0x810
+@@ -293,6 +332,18 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WDMA_RING_RX(_n)			(0x900 + (_n) * 0x10)
+ #define MTK_WED_WDMA_RX_THRES(_n)			(0x940 + (_n) * 0x4)
+ 
++#define MTK_WED_WDMA_RX_PREF_CFG			0x950
++#define MTK_WED_WDMA_RX_PREF_EN				BIT(0)
++#define MTK_WED_WDMA_RX_PREF_BURST_SIZE			GENMASK(12, 8)
++#define MTK_WED_WDMA_RX_PREF_LOW_THRES			GENMASK(21, 16)
++#define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR		BIT(24)
++#define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR		BIT(25)
++#define MTK_WED_WDMA_RX_PREF_DDONE2_EN			BIT(26)
++
++#define MTK_WED_WDMA_RX_PREF_FIFO_CFG			0x95C
++#define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR		BIT(0)
++#define MTK_WED_WDMA_RX_PREF_FIFO_RX1_CLR		BIT(16)
++
+ #define MTK_WED_WDMA_GLO_CFG				0xa04
+ #define MTK_WED_WDMA_GLO_CFG_TX_DRV_EN			BIT(0)
+ #define MTK_WED_WDMA_GLO_CFG_TX_DDONE_CHK		BIT(1)
+@@ -325,6 +376,7 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WDMA_INT_TRIGGER_RX_DONE		GENMASK(17, 16)
+ 
+ #define MTK_WED_WDMA_INT_CTRL				0xa2c
++#define MTK_WED_WDMA_INT_POLL_PRD			GENMASK(7, 0)
+ #define MTK_WED_WDMA_INT_CTRL_POLL_SRC_SEL		GENMASK(17, 16)
+ 
+ #define MTK_WED_WDMA_CFG_BASE				0xaa0
+@@ -388,6 +440,18 @@ struct mtk_wdma_desc {
+ #define MTK_WDMA_INT_GRP1				0x250
+ #define MTK_WDMA_INT_GRP2				0x254
+ 
++#define MTK_WDMA_PREF_TX_CFG				0x2d0
++#define MTK_WDMA_PREF_TX_CFG_PREF_EN			BIT(0)
++
++#define MTK_WDMA_PREF_RX_CFG				0x2dc
++#define MTK_WDMA_PREF_RX_CFG_PREF_EN			BIT(0)
++
++#define MTK_WDMA_WRBK_TX_CFG				0x300
++#define MTK_WDMA_WRBK_TX_CFG_WRBK_EN			BIT(30)
++
++#define MTK_WDMA_WRBK_RX_CFG				0x344
++#define MTK_WDMA_WRBK_RX_CFG_WRBK_EN			BIT(30)
++
+ #define MTK_PCIE_MIRROR_MAP(n)				((n) ? 0x4 : 0x0)
+ #define MTK_PCIE_MIRROR_MAP_EN				BIT(0)
+ #define MTK_PCIE_MIRROR_MAP_WED_ID			BIT(1)
+@@ -401,6 +465,30 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RTQM_Q_DBG_BYPASS			BIT(5)
+ #define MTK_WED_RTQM_TXDMAD_FPORT			GENMASK(23, 20)
+ 
++#define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT		0xb1c
++#define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n)		(0xb20 + (_n) * 0x4)
++#define	MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT			0xb28
++#define MTK_WED_RTQM_IGRS0_I2H_PKT_CNT(_n)		(0xb2c + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS0_FDROP_CNT			0xb34
++
++#define MTK_WED_RTQM_IGRS1_I2HW_DMAD_CNT		0xb44
++#define MTK_WED_RTQM_IGRS1_I2H_DMAD_CNT(_n)		(0xb48 + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS1_I2HW_PKT_CNT			0xb50
++#define MTK_WED_RTQM_IGRS1_I2H_PKT_CNT(_n)		(0xb54 + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS1_FDROP_CNT			0xb5c
++
++#define MTK_WED_RTQM_IGRS2_I2HW_DMAD_CNT		0xb6c
++#define MTK_WED_RTQM_IGRS2_I2H_DMAD_CNT(_n)		(0xb70 + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS2_I2HW_PKT_CNT			0xb78
++#define MTK_WED_RTQM_IGRS2_I2H_PKT_CNT(_n)		(0xb7c + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS2_FDROP_CNT			0xb84
++
++#define MTK_WED_RTQM_IGRS3_I2HW_DMAD_CNT		0xb94
++#define MTK_WED_RTQM_IGRS3_I2H_DMAD_CNT(_n)		(0xb98 + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS3_I2HW_PKT_CNT			0xba0
++#define MTK_WED_RTQM_IGRS3_I2H_PKT_CNT(_n)		(0xba4 + (_n) * 0x4)
++#define MTK_WED_RTQM_IGRS3_FDROP_CNT			0xbac
++
+ #define MTK_WED_RTQM_R2H_MIB(_n)			(0xb70 + (_n) * 0x4)
+ #define MTK_WED_RTQM_R2Q_MIB(_n)			(0xb78 + (_n) * 0x4)
+ #define MTK_WED_RTQM_Q2N_MIB				0xb80
+@@ -409,6 +497,24 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RTQM_Q2B_MIB				0xb8c
+ #define MTK_WED_RTQM_PFDBK_MIB				0xb90
+ 
++#define MTK_WED_RTQM_ENQ_CFG0				0xbb8
++#define MTK_WED_RTQM_ENQ_CFG_TXDMAD_FPORT		GENMASK(15, 12)
++
++#define MTK_WED_RTQM_FDROP_MIB				0xb84
++#define MTK_WED_RTQM_ENQ_I2Q_DMAD_CNT			0xbbc
++#define MTK_WED_RTQM_ENQ_I2N_DMAD_CNT			0xbc0
++#define MTK_WED_RTQM_ENQ_I2Q_PKT_CNT			0xbc4
++#define MTK_WED_RTQM_ENQ_I2N_PKT_CNT			0xbc8
++#define MTK_WED_RTQM_ENQ_USED_ENTRY_CNT			0xbcc
++#define MTK_WED_RTQM_ENQ_ERR_CNT			0xbd0
++
++#define MTK_WED_RTQM_DEQ_DMAD_CNT			0xbd8
++#define MTK_WED_RTQM_DEQ_Q2I_DMAD_CNT			0xbdc
++#define MTK_WED_RTQM_DEQ_PKT_CNT			0xbe0
++#define MTK_WED_RTQM_DEQ_Q2I_PKT_CNT			0xbe4
++#define MTK_WED_RTQM_DEQ_USED_PFDBK_CNT			0xbe8
++#define MTK_WED_RTQM_DEQ_ERR_CNT			0xbec
++
+ #define MTK_WED_RROQM_GLO_CFG				0xc04
+ #define MTK_WED_RROQM_RST_IDX				0xc08
+ #define MTK_WED_RROQM_RST_IDX_MIOD			BIT(0)
+@@ -458,7 +564,116 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RX_BM_INTF				0xd9c
+ #define MTK_WED_RX_BM_ERR_STS				0xda8
+ 
++#define MTK_RRO_IND_CMD_SIGNATURE			0xe00
++#define MTK_RRO_IND_CMD_DMA_IDX				GENMASK(11, 0)
++#define MTK_RRO_IND_CMD_MAGIC_CNT			GENMASK(30, 28)
++
++#define MTK_WED_IND_CMD_RX_CTRL0			0xe04
++#define MTK_WED_IND_CMD_PROC_IDX			GENMASK(11, 0)
++#define MTK_WED_IND_CMD_PREFETCH_FREE_CNT		GENMASK(19, 16)
++#define MTK_WED_IND_CMD_MAGIC_CNT			GENMASK(30, 28)
++
++#define MTK_WED_IND_CMD_RX_CTRL1			0xe08
++#define MTK_WED_IND_CMD_RX_CTRL2			0xe0c
++#define MTK_WED_IND_CMD_MAX_CNT				GENMASK(11, 0)
++#define MTK_WED_IND_CMD_BASE_M				GENMASK(19, 16)
++
++#define MTK_WED_RRO_CFG0				0xe10
++#define MTK_WED_RRO_CFG1				0xe14
++#define MTK_WED_RRO_CFG1_MAX_WIN_SZ			GENMASK(31, 29)
++#define MTK_WED_RRO_CFG1_ACK_SN_BASE_M			GENMASK(19, 16)
++#define MTK_WED_RRO_CFG1_PARTICL_SE_ID			GENMASK(11, 0)
++
++#define MTK_WED_ADDR_ELEM_CFG0				0xe18
++#define MTK_WED_ADDR_ELEM_CFG1				0xe1c
++#define MTK_WED_ADDR_ELEM_PREFETCH_FREE_CNT		GENMASK(19, 16)
++
++#define MTK_WED_ADDR_ELEM_TBL_CFG			0xe20
++#define MTK_WED_ADDR_ELEM_TBL_OFFSET			GENMASK(6, 0)
++#define MTK_WED_ADDR_ELEM_TBL_RD_RDY			BIT(28)
++#define MTK_WED_ADDR_ELEM_TBL_WR_RDY			BIT(29)
++#define MTK_WED_ADDR_ELEM_TBL_RD			BIT(30)
++#define MTK_WED_ADDR_ELEM_TBL_WR			BIT(31)
++
++#define MTK_WED_RADDR_ELEM_TBL_WDATA			0xe24
++#define MTK_WED_RADDR_ELEM_TBL_RDATA			0xe28
++
++#define MTK_WED_PN_CHECK_CFG				0xe30
++#define MTK_WED_PN_CHECK_SE_ID				GENMASK(11, 0)
++#define MTK_WED_PN_CHECK_RD_RDY				BIT(28)
++#define MTK_WED_PN_CHECK_WR_RDY				BIT(29)
++#define MTK_WED_PN_CHECK_RD				BIT(30)
++#define MTK_WED_PN_CHECK_WR				BIT(31)
++
++#define MTK_WED_PN_CHECK_WDATA_M			0xe38
++#define MTK_WED_PN_CHECK_IS_FIRST			BIT(17)
++
++#define MTK_WED_RRO_MSDU_PG_RING_CFG(_n)		(0xe44 + (_n) * 0x8)
++
++#define MTK_WED_RRO_MSDU_PG_RING2_CFG			0xe58
++#define MTK_WED_RRO_MSDU_PG_DRV_CLR			BIT(26)
++#define MTK_WED_RRO_MSDU_PG_DRV_EN			BIT(31)
++
++#define MTK_WED_RRO_MSDU_PG_CTRL0(_n)			(0xe5c + (_n) * 0xc)
++#define MTK_WED_RRO_MSDU_PG_CTRL1(_n)			(0xe60 + (_n) * 0xc)
++#define MTK_WED_RRO_MSDU_PG_CTRL2(_n)			(0xe64 + (_n) * 0xc)
++
++#define MTK_WED_RRO_RX_D_RX(_n)				(0xe80 + (_n) * 0x10)
++
++#define MTK_WED_RRO_RX_MAGIC_CNT			BIT(13)
++
++#define MTK_WED_RRO_RX_D_CFG(_n)			(0xea0 + (_n) * 0x4)
++#define MTK_WED_RRO_RX_D_DRV_CLR			BIT(26)
++#define MTK_WED_RRO_RX_D_DRV_EN				BIT(31)
++
++#define MTK_WED_RRO_PG_BM_RX_DMAM			0xeb0
++#define MTK_WED_RRO_PG_BM_RX_SDL0			GENMASK(13, 0)
++
++#define MTK_WED_RRO_PG_BM_BASE				0xeb4
++#define MTK_WED_RRO_PG_BM_INIT_PTR			0xeb8
++#define MTK_WED_RRO_PG_BM_SW_TAIL_IDX			GENMASK(15, 0)
++#define MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX		BIT(16)
++
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX			0xeec
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN		BIT(0)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR		BIT(1)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG	GENMASK(6, 2)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN		BIT(8)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR		BIT(9)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG	GENMASK(14, 10)
++
++#define MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG		0xef4
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN		BIT(0)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR		BIT(1)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG	GENMASK(6, 2)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN		BIT(8)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR		BIT(9)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG	GENMASK(14, 10)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN		BIT(16)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR		BIT(17)
++#define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG	GENMASK(22, 18)
++
++#define MTK_WED_RX_IND_CMD_CNT0				0xf20
++#define MTK_WED_RX_IND_CMD_DBG_CNT_EN			BIT(31)
++
++#define MTK_WED_RX_IND_CMD_CNT(_n)			(0xf20 + (_n) * 0x4)
++#define MTK_WED_IND_CMD_MAGIC_CNT_FAIL_CNT		GENMASK(15, 0)
++
++#define MTK_WED_RX_ADDR_ELEM_CNT(_n)			(0xf48 + (_n) * 0x4)
++#define MTK_WED_ADDR_ELEM_SIG_FAIL_CNT			GENMASK(15, 0)
++#define MTK_WED_ADDR_ELEM_FIRST_SIG_FAIL_CNT		GENMASK(31, 16)
++#define MTK_WED_ADDR_ELEM_ACKSN_CNT			GENMASK(27, 0)
++
++#define MTK_WED_RX_MSDU_PG_CNT(_n)			(0xf5c + (_n) * 0x4)
++
++#define MTK_WED_RX_PN_CHK_CNT				0xf70
++#define MTK_WED_PN_CHK_FAIL_CNT				GENMASK(15, 0)
++
+ #define MTK_WED_WOCPU_VIEW_MIOD_BASE			0x8000
+ #define MTK_WED_PCIE_INT_MASK				0x0
+ 
++#define MTK_WED_PCIE_BASE			0x11280000
++#define MTK_WED_PCIE_BASE0			0x11300000
++#define MTK_WED_PCIE_BASE1			0x11310000
++#define MTK_WED_PCIE_BASE2			0x11290000
+ #endif
+--- a/drivers/net/ethernet/mediatek/mtk_wed_wo.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_wo.h
+@@ -91,6 +91,8 @@ enum mtk_wed_dummy_cr_idx {
+ #define MT7981_FIRMWARE_WO	"mediatek/mt7981_wo.bin"
+ #define MT7986_FIRMWARE_WO0	"mediatek/mt7986_wo_0.bin"
+ #define MT7986_FIRMWARE_WO1	"mediatek/mt7986_wo_1.bin"
++#define MT7988_FIRMWARE_WO0	"mediatek/mt7988_wo_0.bin"
++#define MT7988_FIRMWARE_WO1	"mediatek/mt7988_wo_1.bin"
+ 
+ #define MTK_WO_MCU_CFG_LS_BASE				0
+ #define MTK_WO_MCU_CFG_LS_HW_VER_ADDR			(MTK_WO_MCU_CFG_LS_BASE + 0x000)
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -139,6 +139,8 @@ struct mtk_wed_device {
+ 		u32 wpdma_rx;
+ 
+ 		bool wcid_512;
++		bool hw_rro;
++		bool msi;
+ 
+ 		u16 token_start;
+ 		unsigned int nbuf;
+@@ -212,10 +214,12 @@ mtk_wed_device_attach(struct mtk_wed_dev
+ 	return ret;
+ }
+ 
+-static inline bool
+-mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
++static inline bool mtk_wed_get_rx_capa(struct mtk_wed_device *dev)
+ {
+ #ifdef CONFIG_NET_MEDIATEK_SOC_WED
++	if (dev->version == 3)
++		return dev->wlan.hw_rro;
++
+ 	return dev->version != 1;
+ #else
+ 	return false;
diff --git a/target/linux/generic/backport-5.15/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch b/target/linux/generic/backport-5.15/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch
new file mode 100644
index 00000000000..e91ae69d081
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-15-v6.7-net-ethernet-mtk_wed-refactor-mtk_wed_check_wfdma_rx.patch
@@ -0,0 +1,95 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:14 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: refactor mtk_wed_check_wfdma_rx_fill
+ routine
+
+Refactor mtk_wed_check_wfdma_rx_fill() in order to be reused adding HW
+receive offload support for MT7988 SoC.
+
+Co-developed-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -585,22 +585,15 @@ mtk_wed_set_512_support(struct mtk_wed_d
+ 	}
+ }
+ 
+-#define MTK_WFMDA_RX_DMA_EN	BIT(2)
+-static void
+-mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev, int idx)
++static int
++mtk_wed_check_wfdma_rx_fill(struct mtk_wed_device *dev,
++			    struct mtk_wed_ring *ring)
+ {
+-	u32 val;
+ 	int i;
+ 
+-	if (!(dev->rx_ring[idx].flags & MTK_WED_RING_CONFIGURED))
+-		return; /* queue is not configured by mt76 */
+-
+ 	for (i = 0; i < 3; i++) {
+-		u32 cur_idx;
++		u32 cur_idx = readl(ring->wpdma + MTK_WED_RING_OFS_CPU_IDX);
+ 
+-		cur_idx = wed_r32(dev,
+-				  MTK_WED_WPDMA_RING_RX_DATA(idx) +
+-				  MTK_WED_RING_OFS_CPU_IDX);
+ 		if (cur_idx == MTK_WED_RX_RING_SIZE - 1)
+ 			break;
+ 
+@@ -609,12 +602,10 @@ mtk_wed_check_wfdma_rx_fill(struct mtk_w
+ 
+ 	if (i == 3) {
+ 		dev_err(dev->hw->dev, "rx dma enable failed\n");
+-		return;
++		return -ETIMEDOUT;
+ 	}
+ 
+-	val = wifi_r32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base) |
+-	      MTK_WFMDA_RX_DMA_EN;
+-	wifi_w32(dev, dev->wlan.wpdma_rx_glo - dev->wlan.phy_base, val);
++	return 0;
+ }
+ 
+ static void
+@@ -1545,6 +1536,7 @@ mtk_wed_configure_irq(struct mtk_wed_dev
+ 	wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
+ }
+ 
++#define MTK_WFMDA_RX_DMA_EN	BIT(2)
+ static void
+ mtk_wed_dma_enable(struct mtk_wed_device *dev)
+ {
+@@ -1632,8 +1624,26 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ 		wdma_set(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
+ 	}
+ 
+-	for (i = 0; i < MTK_WED_RX_QUEUES; i++)
+-		mtk_wed_check_wfdma_rx_fill(dev, i);
++	for (i = 0; i < MTK_WED_RX_QUEUES; i++) {
++		struct mtk_wed_ring *ring = &dev->rx_ring[i];
++		u32 val;
++
++		if (!(ring->flags & MTK_WED_RING_CONFIGURED))
++			continue; /* queue is not configured by mt76 */
++
++		if (mtk_wed_check_wfdma_rx_fill(dev, ring)) {
++			dev_err(dev->hw->dev,
++				"rx_ring(%d) dma enable failed\n", i);
++			continue;
++		}
++
++		val = wifi_r32(dev,
++			       dev->wlan.wpdma_rx_glo -
++			       dev->wlan.phy_base) | MTK_WFMDA_RX_DMA_EN;
++		wifi_w32(dev,
++			 dev->wlan.wpdma_rx_glo - dev->wlan.phy_base,
++			 val);
++	}
+ }
+ 
+ static void
diff --git a/target/linux/generic/backport-5.15/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch b/target/linux/generic/backport-5.15/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch
new file mode 100644
index 00000000000..21a4e0759f0
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-16-v6.7-net-ethernet-mtk_wed-introduce-partial-AMSDU-offload.patch
@@ -0,0 +1,465 @@
+From: Sujuan Chen <sujuan.chen@mediatek.com>
+Date: Mon, 18 Sep 2023 12:29:15 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: introduce partial AMSDU offload
+ support for MT7988
+
+Introduce partial AMSDU offload support for MT7988 SoC in order to merge
+in hw packets belonging to the same AMSDU before passing them to the
+WLAN nic.
+
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
+@@ -438,7 +438,8 @@ int mtk_foe_entry_set_pppoe(struct mtk_e
+ }
+ 
+ int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry,
+-			   int wdma_idx, int txq, int bss, int wcid)
++			   int wdma_idx, int txq, int bss, int wcid,
++			   bool amsdu_en)
+ {
+ 	struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(eth, entry);
+ 	u32 *ib2 = mtk_foe_entry_ib2(eth, entry);
+@@ -450,6 +451,7 @@ int mtk_foe_entry_set_wdma(struct mtk_et
+ 			 MTK_FOE_IB2_WDMA_WINFO_V2;
+ 		l2->w3info = FIELD_PREP(MTK_FOE_WINFO_WCID_V3, wcid) |
+ 			     FIELD_PREP(MTK_FOE_WINFO_BSS_V3, bss);
++		l2->amsdu = FIELD_PREP(MTK_FOE_WINFO_AMSDU_EN, amsdu_en);
+ 		break;
+ 	case 2:
+ 		*ib2 &= ~MTK_FOE_IB2_PORT_MG_V2;
+--- a/drivers/net/ethernet/mediatek/mtk_ppe.h
++++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
+@@ -88,13 +88,13 @@ enum {
+ #define MTK_FOE_WINFO_BSS_V3		GENMASK(23, 16)
+ #define MTK_FOE_WINFO_WCID_V3		GENMASK(15, 0)
+ 
+-#define MTK_FOE_WINFO_PAO_USR_INFO	GENMASK(15, 0)
+-#define MTK_FOE_WINFO_PAO_TID		GENMASK(19, 16)
+-#define MTK_FOE_WINFO_PAO_IS_FIXEDRATE	BIT(20)
+-#define MTK_FOE_WINFO_PAO_IS_PRIOR	BIT(21)
+-#define MTK_FOE_WINFO_PAO_IS_SP		BIT(22)
+-#define MTK_FOE_WINFO_PAO_HF		BIT(23)
+-#define MTK_FOE_WINFO_PAO_AMSDU_EN	BIT(24)
++#define MTK_FOE_WINFO_AMSDU_USR_INFO	GENMASK(15, 0)
++#define MTK_FOE_WINFO_AMSDU_TID		GENMASK(19, 16)
++#define MTK_FOE_WINFO_AMSDU_IS_FIXEDRATE	BIT(20)
++#define MTK_FOE_WINFO_AMSDU_IS_PRIOR	BIT(21)
++#define MTK_FOE_WINFO_AMSDU_IS_SP	BIT(22)
++#define MTK_FOE_WINFO_AMSDU_HF		BIT(23)
++#define MTK_FOE_WINFO_AMSDU_EN		BIT(24)
+ 
+ enum {
+ 	MTK_FOE_STATE_INVALID,
+@@ -123,7 +123,7 @@ struct mtk_foe_mac_info {
+ 
+ 	/* netsys_v3 */
+ 	u32 w3info;
+-	u32 wpao;
++	u32 amsdu;
+ };
+ 
+ /* software-only entry type */
+@@ -393,7 +393,8 @@ int mtk_foe_entry_set_vlan(struct mtk_et
+ int mtk_foe_entry_set_pppoe(struct mtk_eth *eth, struct mtk_foe_entry *entry,
+ 			    int sid);
+ int mtk_foe_entry_set_wdma(struct mtk_eth *eth, struct mtk_foe_entry *entry,
+-			   int wdma_idx, int txq, int bss, int wcid);
++			   int wdma_idx, int txq, int bss, int wcid,
++			   bool amsdu_en);
+ int mtk_foe_entry_set_queue(struct mtk_eth *eth, struct mtk_foe_entry *entry,
+ 			    unsigned int queue);
+ int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_flow_entry *entry);
+--- a/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
++++ b/drivers/net/ethernet/mediatek/mtk_ppe_offload.c
+@@ -111,6 +111,7 @@ mtk_flow_get_wdma_info(struct net_device
+ 	info->queue = path->mtk_wdma.queue;
+ 	info->bss = path->mtk_wdma.bss;
+ 	info->wcid = path->mtk_wdma.wcid;
++	info->amsdu = path->mtk_wdma.amsdu;
+ 
+ 	return 0;
+ }
+@@ -192,7 +193,7 @@ mtk_flow_set_output_device(struct mtk_et
+ 
+ 	if (mtk_flow_get_wdma_info(dev, dest_mac, &info) == 0) {
+ 		mtk_foe_entry_set_wdma(eth, foe, info.wdma_idx, info.queue,
+-				       info.bss, info.wcid);
++				       info.bss, info.wcid, info.amsdu);
+ 		if (mtk_is_netsys_v2_or_greater(eth)) {
+ 			switch (info.wdma_idx) {
+ 			case 0:
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -29,6 +29,8 @@
+ #define MTK_WED_RX_PAGE_BUF_PER_PAGE	(PAGE_SIZE / 128)
+ #define MTK_WED_RX_RING_SIZE		1536
+ #define MTK_WED_RX_PG_BM_CNT		8192
++#define MTK_WED_AMSDU_BUF_SIZE		(PAGE_SIZE << 4)
++#define MTK_WED_AMSDU_NPAGES		32
+ 
+ #define MTK_WED_TX_RING_SIZE		2048
+ #define MTK_WED_WDMA_RING_SIZE		1024
+@@ -172,6 +174,23 @@ mtk_wdma_rx_reset(struct mtk_wed_device
+ 	return ret;
+ }
+ 
++static u32
++mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
++{
++	return !!(wed_r32(dev, reg) & mask);
++}
++
++static int
++mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
++{
++	int sleep = 15000;
++	int timeout = 100 * sleep;
++	u32 val;
++
++	return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
++				 timeout, false, dev, reg, mask);
++}
++
+ static void
+ mtk_wdma_tx_reset(struct mtk_wed_device *dev)
+ {
+@@ -335,6 +354,118 @@ out:
+ }
+ 
+ static int
++mtk_wed_amsdu_buffer_alloc(struct mtk_wed_device *dev)
++{
++	struct mtk_wed_hw *hw = dev->hw;
++	struct mtk_wed_amsdu *wed_amsdu;
++	int i;
++
++	if (!mtk_wed_is_v3_or_greater(hw))
++		return 0;
++
++	wed_amsdu = devm_kcalloc(hw->dev, MTK_WED_AMSDU_NPAGES,
++				 sizeof(*wed_amsdu), GFP_KERNEL);
++	if (!wed_amsdu)
++		return -ENOMEM;
++
++	for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++) {
++		void *ptr;
++
++		/* each segment is 64K */
++		ptr = (void *)__get_free_pages(GFP_KERNEL | __GFP_NOWARN |
++					       __GFP_ZERO | __GFP_COMP |
++					       GFP_DMA32,
++					       get_order(MTK_WED_AMSDU_BUF_SIZE));
++		if (!ptr)
++			goto error;
++
++		wed_amsdu[i].txd = ptr;
++		wed_amsdu[i].txd_phy = dma_map_single(hw->dev, ptr,
++						      MTK_WED_AMSDU_BUF_SIZE,
++						      DMA_TO_DEVICE);
++		if (dma_mapping_error(hw->dev, wed_amsdu[i].txd_phy))
++			goto error;
++	}
++	dev->hw->wed_amsdu = wed_amsdu;
++
++	return 0;
++
++error:
++	for (i--; i >= 0; i--)
++		dma_unmap_single(hw->dev, wed_amsdu[i].txd_phy,
++				 MTK_WED_AMSDU_BUF_SIZE, DMA_TO_DEVICE);
++	return -ENOMEM;
++}
++
++static void
++mtk_wed_amsdu_free_buffer(struct mtk_wed_device *dev)
++{
++	struct mtk_wed_amsdu *wed_amsdu = dev->hw->wed_amsdu;
++	int i;
++
++	if (!wed_amsdu)
++		return;
++
++	for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++) {
++		dma_unmap_single(dev->hw->dev, wed_amsdu[i].txd_phy,
++				 MTK_WED_AMSDU_BUF_SIZE, DMA_TO_DEVICE);
++		free_pages((unsigned long)wed_amsdu[i].txd,
++			   get_order(MTK_WED_AMSDU_BUF_SIZE));
++	}
++}
++
++static int
++mtk_wed_amsdu_init(struct mtk_wed_device *dev)
++{
++	struct mtk_wed_amsdu *wed_amsdu = dev->hw->wed_amsdu;
++	int i, ret;
++
++	if (!wed_amsdu)
++		return 0;
++
++	for (i = 0; i < MTK_WED_AMSDU_NPAGES; i++)
++		wed_w32(dev, MTK_WED_AMSDU_HIFTXD_BASE_L(i),
++			wed_amsdu[i].txd_phy);
++
++	/* init all sta parameter */
++	wed_w32(dev, MTK_WED_AMSDU_STA_INFO_INIT, MTK_WED_AMSDU_STA_RMVL |
++		MTK_WED_AMSDU_STA_WTBL_HDRT_MODE |
++		FIELD_PREP(MTK_WED_AMSDU_STA_MAX_AMSDU_LEN,
++			   dev->wlan.amsdu_max_len >> 8) |
++		FIELD_PREP(MTK_WED_AMSDU_STA_MAX_AMSDU_NUM,
++			   dev->wlan.amsdu_max_subframes));
++
++	wed_w32(dev, MTK_WED_AMSDU_STA_INFO, MTK_WED_AMSDU_STA_INFO_DO_INIT);
++
++	ret = mtk_wed_poll_busy(dev, MTK_WED_AMSDU_STA_INFO,
++				MTK_WED_AMSDU_STA_INFO_DO_INIT);
++	if (ret) {
++		dev_err(dev->hw->dev, "amsdu initialization failed\n");
++		return ret;
++	}
++
++	/* init partial amsdu offload txd src */
++	wed_set(dev, MTK_WED_AMSDU_HIFTXD_CFG,
++		FIELD_PREP(MTK_WED_AMSDU_HIFTXD_SRC, dev->hw->index));
++
++	/* init qmem */
++	wed_set(dev, MTK_WED_AMSDU_PSE, MTK_WED_AMSDU_PSE_RESET);
++	ret = mtk_wed_poll_busy(dev, MTK_WED_MON_AMSDU_QMEM_STS1, BIT(29));
++	if (ret) {
++		pr_info("%s: amsdu qmem initialization failed\n", __func__);
++		return ret;
++	}
++
++	/* eagle E1 PCIE1 tx ring 22 flow control issue */
++	if (dev->wlan.id == 0x7991)
++		wed_clr(dev, MTK_WED_AMSDU_FIFO, MTK_WED_AMSDU_IS_PRIOR0_RING);
++
++	wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
++
++	return 0;
++}
++
++static int
+ mtk_wed_tx_buffer_alloc(struct mtk_wed_device *dev)
+ {
+ 	u32 desc_size = dev->hw->soc->tx_ring_desc_size;
+@@ -708,6 +839,7 @@ __mtk_wed_detach(struct mtk_wed_device *
+ 
+ 	mtk_wdma_rx_reset(dev);
+ 	mtk_wed_reset(dev, MTK_WED_RESET_WED);
++	mtk_wed_amsdu_free_buffer(dev);
+ 	mtk_wed_free_tx_buffer(dev);
+ 	mtk_wed_free_tx_rings(dev);
+ 
+@@ -1128,23 +1260,6 @@ mtk_wed_ring_reset(struct mtk_wed_ring *
+ 	}
+ }
+ 
+-static u32
+-mtk_wed_check_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
+-{
+-	return !!(wed_r32(dev, reg) & mask);
+-}
+-
+-static int
+-mtk_wed_poll_busy(struct mtk_wed_device *dev, u32 reg, u32 mask)
+-{
+-	int sleep = 15000;
+-	int timeout = 100 * sleep;
+-	u32 val;
+-
+-	return read_poll_timeout(mtk_wed_check_busy, val, !val, sleep,
+-				 timeout, false, dev, reg, mask);
+-}
+-
+ static int
+ mtk_wed_rx_reset(struct mtk_wed_device *dev)
+ {
+@@ -1691,6 +1806,7 @@ mtk_wed_start(struct mtk_wed_device *dev
+ 	}
+ 
+ 	mtk_wed_set_512_support(dev, dev->wlan.wcid_512);
++	mtk_wed_amsdu_init(dev);
+ 
+ 	mtk_wed_dma_enable(dev);
+ 	dev->running = true;
+@@ -1747,6 +1863,10 @@ mtk_wed_attach(struct mtk_wed_device *de
+ 	if (ret)
+ 		goto out;
+ 
++	ret = mtk_wed_amsdu_buffer_alloc(dev);
++	if (ret)
++		goto out;
++
+ 	if (mtk_wed_get_rx_capa(dev)) {
+ 		ret = mtk_wed_rro_alloc(dev);
+ 		if (ret)
+--- a/drivers/net/ethernet/mediatek/mtk_wed.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed.h
+@@ -25,6 +25,11 @@ struct mtk_wed_soc_data {
+ 	u32 wdma_desc_size;
+ };
+ 
++struct mtk_wed_amsdu {
++	void *txd;
++	dma_addr_t txd_phy;
++};
++
+ struct mtk_wed_hw {
+ 	const struct mtk_wed_soc_data *soc;
+ 	struct device_node *node;
+@@ -38,6 +43,7 @@ struct mtk_wed_hw {
+ 	struct dentry *debugfs_dir;
+ 	struct mtk_wed_device *wed_dev;
+ 	struct mtk_wed_wo *wed_wo;
++	struct mtk_wed_amsdu *wed_amsdu;
+ 	u32 pcie_base;
+ 	u32 debugfs_reg;
+ 	u32 num_flows;
+@@ -52,6 +58,7 @@ struct mtk_wdma_info {
+ 	u8 queue;
+ 	u16 wcid;
+ 	u8 bss;
++	u8 amsdu;
+ };
+ 
+ #ifdef CONFIG_NET_MEDIATEK_SOC_WED
+--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
+@@ -672,6 +672,82 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WOCPU_VIEW_MIOD_BASE			0x8000
+ #define MTK_WED_PCIE_INT_MASK				0x0
+ 
++#define MTK_WED_AMSDU_FIFO				0x1800
++#define MTK_WED_AMSDU_IS_PRIOR0_RING			BIT(10)
++
++#define MTK_WED_AMSDU_STA_INFO				0x01810
++#define MTK_WED_AMSDU_STA_INFO_DO_INIT			BIT(0)
++#define MTK_WED_AMSDU_STA_INFO_SET_INIT			BIT(1)
++
++#define MTK_WED_AMSDU_STA_INFO_INIT			0x01814
++#define MTK_WED_AMSDU_STA_WTBL_HDRT_MODE		BIT(0)
++#define MTK_WED_AMSDU_STA_RMVL				BIT(1)
++#define MTK_WED_AMSDU_STA_MAX_AMSDU_LEN			GENMASK(7, 2)
++#define MTK_WED_AMSDU_STA_MAX_AMSDU_NUM			GENMASK(11, 8)
++
++#define MTK_WED_AMSDU_HIFTXD_BASE_L(_n)			(0x1980 + (_n) * 0x4)
++
++#define MTK_WED_AMSDU_PSE				0x1910
++#define MTK_WED_AMSDU_PSE_RESET				BIT(16)
++
++#define MTK_WED_AMSDU_HIFTXD_CFG			0x1968
++#define MTK_WED_AMSDU_HIFTXD_SRC			GENMASK(16, 15)
++
++#define MTK_WED_MON_AMSDU_FIFO_DMAD			0x1a34
++
++#define MTK_WED_MON_AMSDU_ENG_DMAD(_n)			(0x1a80 + (_n) * 0x50)
++#define MTK_WED_MON_AMSDU_ENG_QFPL(_n)			(0x1a84 + (_n) * 0x50)
++#define MTK_WED_MON_AMSDU_ENG_QENI(_n)			(0x1a88 + (_n) * 0x50)
++#define MTK_WED_MON_AMSDU_ENG_QENO(_n)			(0x1a8c + (_n) * 0x50)
++#define MTK_WED_MON_AMSDU_ENG_MERG(_n)			(0x1a90 + (_n) * 0x50)
++
++#define MTK_WED_MON_AMSDU_ENG_CNT8(_n)			(0x1a94 + (_n) * 0x50)
++#define MTK_WED_AMSDU_ENG_MAX_QGPP_CNT			GENMASK(10, 0)
++#define MTK_WED_AMSDU_ENG_MAX_PL_CNT			GENMASK(27, 16)
++
++#define MTK_WED_MON_AMSDU_ENG_CNT9(_n)			(0x1a98 + (_n) * 0x50)
++#define MTK_WED_AMSDU_ENG_CUR_ENTRY			GENMASK(10, 0)
++#define MTK_WED_AMSDU_ENG_MAX_BUF_MERGED		GENMASK(20, 16)
++#define MTK_WED_AMSDU_ENG_MAX_MSDU_MERGED		GENMASK(28, 24)
++
++#define MTK_WED_MON_AMSDU_QMEM_STS1			0x1e04
++
++#define MTK_WED_MON_AMSDU_QMEM_CNT(_n)			(0x1e0c + (_n) * 0x4)
++#define MTK_WED_AMSDU_QMEM_FQ_CNT			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_SP_QCNT			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID0_QCNT			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID1_QCNT			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID2_QCNT			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID3_QCNT			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID4_QCNT			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID5_QCNT			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID6_QCNT			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID7_QCNT			GENMASK(11, 0)
++
++#define MTK_WED_MON_AMSDU_QMEM_PTR(_n)			(0x1e20 + (_n) * 0x4)
++#define MTK_WED_AMSDU_QMEM_FQ_HEAD			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_SP_QHEAD			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID0_QHEAD			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID1_QHEAD			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID2_QHEAD			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID3_QHEAD			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID4_QHEAD			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID5_QHEAD			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID6_QHEAD			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID7_QHEAD			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_FQ_TAIL			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_SP_QTAIL			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID0_QTAIL			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID1_QTAIL			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID2_QTAIL			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID3_QTAIL			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID4_QTAIL			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID5_QTAIL			GENMASK(11, 0)
++#define MTK_WED_AMSDU_QMEM_TID6_QTAIL			GENMASK(27, 16)
++#define MTK_WED_AMSDU_QMEM_TID7_QTAIL			GENMASK(11, 0)
++
++#define MTK_WED_MON_AMSDU_HIFTXD_FETCH_MSDU(_n)		(0x1ec4 + (_n) * 0x4)
++
+ #define MTK_WED_PCIE_BASE			0x11280000
+ #define MTK_WED_PCIE_BASE0			0x11300000
+ #define MTK_WED_PCIE_BASE1			0x11310000
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -906,6 +906,7 @@ struct net_device_path {
+ 			u8 queue;
+ 			u16 wcid;
+ 			u8 bss;
++			u8 amsdu;
+ 		} mtk_wdma;
+ 	};
+ };
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -129,6 +129,7 @@ struct mtk_wed_device {
+ 		enum mtk_wed_bus_tye bus_type;
+ 		void __iomem *base;
+ 		u32 phy_base;
++		u32 id;
+ 
+ 		u32 wpdma_phys;
+ 		u32 wpdma_int;
+@@ -147,10 +148,12 @@ struct mtk_wed_device {
+ 		unsigned int rx_nbuf;
+ 		unsigned int rx_npkt;
+ 		unsigned int rx_size;
++		unsigned int amsdu_max_len;
+ 
+ 		u8 tx_tbit[MTK_WED_TX_QUEUES];
+ 		u8 rx_tbit[MTK_WED_RX_QUEUES];
+ 		u8 txfree_tbit;
++		u8 amsdu_max_subframes;
+ 
+ 		u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
+ 		int (*offload_enable)(struct mtk_wed_device *wed);
+@@ -224,6 +227,15 @@ static inline bool mtk_wed_get_rx_capa(s
+ #else
+ 	return false;
+ #endif
++}
++
++static inline bool mtk_wed_is_amsdu_supported(struct mtk_wed_device *dev)
++{
++#ifdef CONFIG_NET_MEDIATEK_SOC_WED
++	return dev->version == 3;
++#else
++	return false;
++#endif
+ }
+ 
+ #ifdef CONFIG_NET_MEDIATEK_SOC_WED
diff --git a/target/linux/generic/backport-5.15/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch b/target/linux/generic/backport-5.15/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch
new file mode 100644
index 00000000000..0cf4c188757
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-17-v6.7-net-ethernet-mtk_wed-introduce-hw_rro-support-for-MT.patch
@@ -0,0 +1,483 @@
+From: Sujuan Chen <sujuan.chen@mediatek.com>
+Date: Mon, 18 Sep 2023 12:29:16 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: introduce hw_rro support for MT7988
+
+MT7988 SoC support 802.11 receive reordering offload in hw while
+MT7986 SoC implements it through the firmware running on the mcu.
+
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -26,7 +26,7 @@
+ #define MTK_WED_BUF_SIZE		2048
+ #define MTK_WED_PAGE_BUF_SIZE		128
+ #define MTK_WED_BUF_PER_PAGE		(PAGE_SIZE / 2048)
+-#define MTK_WED_RX_PAGE_BUF_PER_PAGE	(PAGE_SIZE / 128)
++#define MTK_WED_RX_BUF_PER_PAGE		(PAGE_SIZE / MTK_WED_PAGE_BUF_SIZE)
+ #define MTK_WED_RX_RING_SIZE		1536
+ #define MTK_WED_RX_PG_BM_CNT		8192
+ #define MTK_WED_AMSDU_BUF_SIZE		(PAGE_SIZE << 4)
+@@ -596,6 +596,68 @@ free_pagelist:
+ }
+ 
+ static int
++mtk_wed_hwrro_buffer_alloc(struct mtk_wed_device *dev)
++{
++	int n_pages = MTK_WED_RX_PG_BM_CNT / MTK_WED_RX_BUF_PER_PAGE;
++	struct mtk_wed_buf *page_list;
++	struct mtk_wed_bm_desc *desc;
++	dma_addr_t desc_phys;
++	int i, page_idx = 0;
++
++	if (!dev->wlan.hw_rro)
++		return 0;
++
++	page_list = kcalloc(n_pages, sizeof(*page_list), GFP_KERNEL);
++	if (!page_list)
++		return -ENOMEM;
++
++	dev->hw_rro.size = dev->wlan.rx_nbuf & ~(MTK_WED_BUF_PER_PAGE - 1);
++	dev->hw_rro.pages = page_list;
++	desc = dma_alloc_coherent(dev->hw->dev,
++				  dev->wlan.rx_nbuf * sizeof(*desc),
++				  &desc_phys, GFP_KERNEL);
++	if (!desc)
++		return -ENOMEM;
++
++	dev->hw_rro.desc = desc;
++	dev->hw_rro.desc_phys = desc_phys;
++
++	for (i = 0; i < MTK_WED_RX_PG_BM_CNT; i += MTK_WED_RX_BUF_PER_PAGE) {
++		dma_addr_t page_phys, buf_phys;
++		struct page *page;
++		int s;
++
++		page = __dev_alloc_page(GFP_KERNEL);
++		if (!page)
++			return -ENOMEM;
++
++		page_phys = dma_map_page(dev->hw->dev, page, 0, PAGE_SIZE,
++					 DMA_BIDIRECTIONAL);
++		if (dma_mapping_error(dev->hw->dev, page_phys)) {
++			__free_page(page);
++			return -ENOMEM;
++		}
++
++		page_list[page_idx].p = page;
++		page_list[page_idx++].phy_addr = page_phys;
++		dma_sync_single_for_cpu(dev->hw->dev, page_phys, PAGE_SIZE,
++					DMA_BIDIRECTIONAL);
++
++		buf_phys = page_phys;
++		for (s = 0; s < MTK_WED_RX_BUF_PER_PAGE; s++) {
++			desc->buf0 = cpu_to_le32(buf_phys);
++			buf_phys += MTK_WED_PAGE_BUF_SIZE;
++			desc++;
++		}
++
++		dma_sync_single_for_device(dev->hw->dev, page_phys, PAGE_SIZE,
++					   DMA_BIDIRECTIONAL);
++	}
++
++	return 0;
++}
++
++static int
+ mtk_wed_rx_buffer_alloc(struct mtk_wed_device *dev)
+ {
+ 	struct mtk_wed_bm_desc *desc;
+@@ -612,7 +674,42 @@ mtk_wed_rx_buffer_alloc(struct mtk_wed_d
+ 	dev->rx_buf_ring.desc_phys = desc_phys;
+ 	dev->wlan.init_rx_buf(dev, dev->wlan.rx_npkt);
+ 
+-	return 0;
++	return mtk_wed_hwrro_buffer_alloc(dev);
++}
++
++static void
++mtk_wed_hwrro_free_buffer(struct mtk_wed_device *dev)
++{
++	struct mtk_wed_buf *page_list = dev->hw_rro.pages;
++	struct mtk_wed_bm_desc *desc = dev->hw_rro.desc;
++	int i, page_idx = 0;
++
++	if (!dev->wlan.hw_rro)
++		return;
++
++	if (!page_list)
++		return;
++
++	if (!desc)
++		goto free_pagelist;
++
++	for (i = 0; i < MTK_WED_RX_PG_BM_CNT; i += MTK_WED_RX_BUF_PER_PAGE) {
++		dma_addr_t buf_addr = page_list[page_idx].phy_addr;
++		void *page = page_list[page_idx++].p;
++
++		if (!page)
++			break;
++
++		dma_unmap_page(dev->hw->dev, buf_addr, PAGE_SIZE,
++			       DMA_BIDIRECTIONAL);
++		__free_page(page);
++	}
++
++	dma_free_coherent(dev->hw->dev, dev->hw_rro.size * sizeof(*desc),
++			  desc, dev->hw_rro.desc_phys);
++
++free_pagelist:
++	kfree(page_list);
+ }
+ 
+ static void
+@@ -626,6 +723,28 @@ mtk_wed_free_rx_buffer(struct mtk_wed_de
+ 	dev->wlan.release_rx_buf(dev);
+ 	dma_free_coherent(dev->hw->dev, dev->rx_buf_ring.size * sizeof(*desc),
+ 			  desc, dev->rx_buf_ring.desc_phys);
++
++	mtk_wed_hwrro_free_buffer(dev);
++}
++
++static void
++mtk_wed_hwrro_init(struct mtk_wed_device *dev)
++{
++	if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
++		return;
++
++	wed_set(dev, MTK_WED_RRO_PG_BM_RX_DMAM,
++		FIELD_PREP(MTK_WED_RRO_PG_BM_RX_SDL0, 128));
++
++	wed_w32(dev, MTK_WED_RRO_PG_BM_BASE, dev->hw_rro.desc_phys);
++
++	wed_w32(dev, MTK_WED_RRO_PG_BM_INIT_PTR,
++		MTK_WED_RRO_PG_BM_INIT_SW_TAIL_IDX |
++		FIELD_PREP(MTK_WED_RRO_PG_BM_SW_TAIL_IDX,
++			   MTK_WED_RX_PG_BM_CNT));
++
++	/* enable rx_page_bm to fetch dmad */
++	wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
+ }
+ 
+ static void
+@@ -639,6 +758,8 @@ mtk_wed_rx_buffer_hw_init(struct mtk_wed
+ 	wed_w32(dev, MTK_WED_RX_BM_DYN_ALLOC_TH,
+ 		FIELD_PREP(MTK_WED_RX_BM_DYN_ALLOC_TH_H, 0xffff));
+ 	wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_BM_EN);
++
++	mtk_wed_hwrro_init(dev);
+ }
+ 
+ static void
+@@ -934,6 +1055,8 @@ mtk_wed_bus_init(struct mtk_wed_device *
+ static void
+ mtk_wed_set_wpdma(struct mtk_wed_device *dev)
+ {
++	int i;
++
+ 	if (mtk_wed_is_v1(dev->hw)) {
+ 		wed_w32(dev, MTK_WED_WPDMA_CFG_BASE,  dev->wlan.wpdma_phys);
+ 		return;
+@@ -951,6 +1074,15 @@ mtk_wed_set_wpdma(struct mtk_wed_device
+ 
+ 	wed_w32(dev, MTK_WED_WPDMA_RX_GLO_CFG, dev->wlan.wpdma_rx_glo);
+ 	wed_w32(dev, dev->hw->soc->regmap.wpdma_rx_ring0, dev->wlan.wpdma_rx);
++
++	if (!dev->wlan.hw_rro)
++		return;
++
++	wed_w32(dev, MTK_WED_RRO_RX_D_CFG(0), dev->wlan.wpdma_rx_rro[0]);
++	wed_w32(dev, MTK_WED_RRO_RX_D_CFG(1), dev->wlan.wpdma_rx_rro[1]);
++	for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++)
++		wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING_CFG(i),
++			dev->wlan.wpdma_rx_pg + i * 0x10);
+ }
+ 
+ static void
+@@ -1762,6 +1894,165 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ }
+ 
+ static void
++mtk_wed_start_hw_rro(struct mtk_wed_device *dev, u32 irq_mask, bool reset)
++{
++	int i;
++
++	wed_w32(dev, MTK_WED_WPDMA_INT_MASK, irq_mask);
++	wed_w32(dev, MTK_WED_INT_MASK, irq_mask);
++
++	if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
++		return;
++
++	wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR);
++	wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
++		MTK_WED_RRO_MSDU_PG_DRV_CLR);
++
++	wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_RX,
++		MTK_WED_WPDMA_INT_CTRL_RRO_RX0_EN |
++		MTK_WED_WPDMA_INT_CTRL_RRO_RX0_CLR |
++		MTK_WED_WPDMA_INT_CTRL_RRO_RX1_EN |
++		MTK_WED_WPDMA_INT_CTRL_RRO_RX1_CLR |
++		FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX0_DONE_TRIG,
++			   dev->wlan.rro_rx_tbit[0]) |
++		FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_RX1_DONE_TRIG,
++			   dev->wlan.rro_rx_tbit[1]));
++
++	wed_w32(dev, MTK_WED_WPDMA_INT_CTRL_RRO_MSDU_PG,
++		MTK_WED_WPDMA_INT_CTRL_RRO_PG0_EN |
++		MTK_WED_WPDMA_INT_CTRL_RRO_PG0_CLR |
++		MTK_WED_WPDMA_INT_CTRL_RRO_PG1_EN |
++		MTK_WED_WPDMA_INT_CTRL_RRO_PG1_CLR |
++		MTK_WED_WPDMA_INT_CTRL_RRO_PG2_EN |
++		MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR |
++		FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG0_DONE_TRIG,
++			   dev->wlan.rx_pg_tbit[0]) |
++		FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG1_DONE_TRIG,
++			   dev->wlan.rx_pg_tbit[1]) |
++		FIELD_PREP(MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG,
++			   dev->wlan.rx_pg_tbit[2]));
++
++	/* RRO_MSDU_PG_RING2_CFG1_FLD_DRV_EN should be enabled after
++	 * WM FWDL completed, otherwise RRO_MSDU_PG ring may broken
++	 */
++	wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
++		MTK_WED_RRO_MSDU_PG_DRV_EN);
++
++	for (i = 0; i < MTK_WED_RX_QUEUES; i++) {
++		struct mtk_wed_ring *ring = &dev->rx_rro_ring[i];
++
++		if (!(ring->flags & MTK_WED_RING_CONFIGURED))
++			continue;
++
++		if (mtk_wed_check_wfdma_rx_fill(dev, ring))
++			dev_err(dev->hw->dev,
++				"rx_rro_ring(%d) initialization failed\n", i);
++	}
++
++	for (i = 0; i < MTK_WED_RX_PAGE_QUEUES; i++) {
++		struct mtk_wed_ring *ring = &dev->rx_page_ring[i];
++
++		if (!(ring->flags & MTK_WED_RING_CONFIGURED))
++			continue;
++
++		if (mtk_wed_check_wfdma_rx_fill(dev, ring))
++			dev_err(dev->hw->dev,
++				"rx_page_ring(%d) initialization failed\n", i);
++	}
++}
++
++static void
++mtk_wed_rro_rx_ring_setup(struct mtk_wed_device *dev, int idx,
++			  void __iomem *regs)
++{
++	struct mtk_wed_ring *ring = &dev->rx_rro_ring[idx];
++
++	ring->wpdma = regs;
++	wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_BASE,
++		readl(regs));
++	wed_w32(dev, MTK_WED_RRO_RX_D_RX(idx) + MTK_WED_RING_OFS_COUNT,
++		readl(regs + MTK_WED_RING_OFS_COUNT));
++	ring->flags |= MTK_WED_RING_CONFIGURED;
++}
++
++static void
++mtk_wed_msdu_pg_rx_ring_setup(struct mtk_wed_device *dev, int idx, void __iomem *regs)
++{
++	struct mtk_wed_ring *ring = &dev->rx_page_ring[idx];
++
++	ring->wpdma = regs;
++	wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_BASE,
++		readl(regs));
++	wed_w32(dev, MTK_WED_RRO_MSDU_PG_CTRL0(idx) + MTK_WED_RING_OFS_COUNT,
++		readl(regs + MTK_WED_RING_OFS_COUNT));
++	ring->flags |= MTK_WED_RING_CONFIGURED;
++}
++
++static int
++mtk_wed_ind_rx_ring_setup(struct mtk_wed_device *dev, void __iomem *regs)
++{
++	struct mtk_wed_ring *ring = &dev->ind_cmd_ring;
++	u32 val = readl(regs + MTK_WED_RING_OFS_COUNT);
++	int i, count = 0;
++
++	ring->wpdma = regs;
++	wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_BASE,
++		readl(regs) & 0xfffffff0);
++
++	wed_w32(dev, MTK_WED_IND_CMD_RX_CTRL1 + MTK_WED_RING_OFS_COUNT,
++		readl(regs + MTK_WED_RING_OFS_COUNT));
++
++	/* ack sn cr */
++	wed_w32(dev, MTK_WED_RRO_CFG0, dev->wlan.phy_base +
++		dev->wlan.ind_cmd.ack_sn_addr);
++	wed_w32(dev, MTK_WED_RRO_CFG1,
++		FIELD_PREP(MTK_WED_RRO_CFG1_MAX_WIN_SZ,
++			   dev->wlan.ind_cmd.win_size) |
++		FIELD_PREP(MTK_WED_RRO_CFG1_PARTICL_SE_ID,
++			   dev->wlan.ind_cmd.particular_sid));
++
++	/* particular session addr element */
++	wed_w32(dev, MTK_WED_ADDR_ELEM_CFG0,
++		dev->wlan.ind_cmd.particular_se_phys);
++
++	for (i = 0; i < dev->wlan.ind_cmd.se_group_nums; i++) {
++		wed_w32(dev, MTK_WED_RADDR_ELEM_TBL_WDATA,
++			dev->wlan.ind_cmd.addr_elem_phys[i] >> 4);
++		wed_w32(dev, MTK_WED_ADDR_ELEM_TBL_CFG,
++			MTK_WED_ADDR_ELEM_TBL_WR | (i & 0x7f));
++
++		val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
++		while (!(val & MTK_WED_ADDR_ELEM_TBL_WR_RDY) && count++ < 100)
++			val = wed_r32(dev, MTK_WED_ADDR_ELEM_TBL_CFG);
++		if (count >= 100)
++			dev_err(dev->hw->dev,
++				"write ba session base failed\n");
++	}
++
++	/* pn check init */
++	for (i = 0; i < dev->wlan.ind_cmd.particular_sid; i++) {
++		wed_w32(dev, MTK_WED_PN_CHECK_WDATA_M,
++			MTK_WED_PN_CHECK_IS_FIRST);
++
++		wed_w32(dev, MTK_WED_PN_CHECK_CFG, MTK_WED_PN_CHECK_WR |
++			FIELD_PREP(MTK_WED_PN_CHECK_SE_ID, i));
++
++		count = 0;
++		val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
++		while (!(val & MTK_WED_PN_CHECK_WR_RDY) && count++ < 100)
++			val = wed_r32(dev, MTK_WED_PN_CHECK_CFG);
++		if (count >= 100)
++			dev_err(dev->hw->dev,
++				"session(%d) initialization failed\n", i);
++	}
++
++	wed_w32(dev, MTK_WED_RX_IND_CMD_CNT0, MTK_WED_RX_IND_CMD_DBG_CNT_EN);
++	wed_set(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
++
++	return 0;
++}
++
++static void
+ mtk_wed_start(struct mtk_wed_device *dev, u32 irq_mask)
+ {
+ 	int i;
+@@ -2215,6 +2506,10 @@ void mtk_wed_add_hw(struct device_node *
+ 		.detach = mtk_wed_detach,
+ 		.ppe_check = mtk_wed_ppe_check,
+ 		.setup_tc = mtk_wed_setup_tc,
++		.start_hw_rro = mtk_wed_start_hw_rro,
++		.rro_rx_ring_setup = mtk_wed_rro_rx_ring_setup,
++		.msdu_pg_rx_ring_setup = mtk_wed_msdu_pg_rx_ring_setup,
++		.ind_rx_ring_setup = mtk_wed_ind_rx_ring_setup,
+ 	};
+ 	struct device_node *eth_np = eth->dev->of_node;
+ 	struct platform_device *pdev;
+--- a/include/linux/soc/mediatek/mtk_wed.h
++++ b/include/linux/soc/mediatek/mtk_wed.h
+@@ -10,6 +10,7 @@
+ 
+ #define MTK_WED_TX_QUEUES		2
+ #define MTK_WED_RX_QUEUES		2
++#define MTK_WED_RX_PAGE_QUEUES		3
+ 
+ #define WED_WO_STA_REC			0x6
+ 
+@@ -99,6 +100,9 @@ struct mtk_wed_device {
+ 	struct mtk_wed_ring txfree_ring;
+ 	struct mtk_wed_ring tx_wdma[MTK_WED_TX_QUEUES];
+ 	struct mtk_wed_ring rx_wdma[MTK_WED_RX_QUEUES];
++	struct mtk_wed_ring rx_rro_ring[MTK_WED_RX_QUEUES];
++	struct mtk_wed_ring rx_page_ring[MTK_WED_RX_PAGE_QUEUES];
++	struct mtk_wed_ring ind_cmd_ring;
+ 
+ 	struct {
+ 		int size;
+@@ -120,6 +124,13 @@ struct mtk_wed_device {
+ 		dma_addr_t fdbk_phys;
+ 	} rro;
+ 
++	struct {
++		int size;
++		struct mtk_wed_buf *pages;
++		struct mtk_wed_bm_desc *desc;
++		dma_addr_t desc_phys;
++	} hw_rro;
++
+ 	/* filled by driver: */
+ 	struct {
+ 		union {
+@@ -138,6 +149,8 @@ struct mtk_wed_device {
+ 		u32 wpdma_txfree;
+ 		u32 wpdma_rx_glo;
+ 		u32 wpdma_rx;
++		u32 wpdma_rx_rro[MTK_WED_RX_QUEUES];
++		u32 wpdma_rx_pg;
+ 
+ 		bool wcid_512;
+ 		bool hw_rro;
+@@ -152,9 +165,20 @@ struct mtk_wed_device {
+ 
+ 		u8 tx_tbit[MTK_WED_TX_QUEUES];
+ 		u8 rx_tbit[MTK_WED_RX_QUEUES];
++		u8 rro_rx_tbit[MTK_WED_RX_QUEUES];
++		u8 rx_pg_tbit[MTK_WED_RX_PAGE_QUEUES];
+ 		u8 txfree_tbit;
+ 		u8 amsdu_max_subframes;
+ 
++		struct {
++			u8 se_group_nums;
++			u16 win_size;
++			u16 particular_sid;
++			u32 ack_sn_addr;
++			dma_addr_t particular_se_phys;
++			dma_addr_t addr_elem_phys[1024];
++		} ind_cmd;
++
+ 		u32 (*init_buf)(void *ptr, dma_addr_t phys, int token_id);
+ 		int (*offload_enable)(struct mtk_wed_device *wed);
+ 		void (*offload_disable)(struct mtk_wed_device *wed);
+@@ -193,6 +217,14 @@ struct mtk_wed_ops {
+ 	void (*irq_set_mask)(struct mtk_wed_device *dev, u32 mask);
+ 	int (*setup_tc)(struct mtk_wed_device *wed, struct net_device *dev,
+ 			enum tc_setup_type type, void *type_data);
++	void (*start_hw_rro)(struct mtk_wed_device *dev, u32 irq_mask,
++			     bool reset);
++	void (*rro_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
++				  void __iomem *regs);
++	void (*msdu_pg_rx_ring_setup)(struct mtk_wed_device *dev, int ring,
++				      void __iomem *regs);
++	int (*ind_rx_ring_setup)(struct mtk_wed_device *dev,
++				 void __iomem *regs);
+ };
+ 
+ extern const struct mtk_wed_ops __rcu *mtk_soc_wed_ops;
+@@ -264,6 +296,15 @@ static inline bool mtk_wed_is_amsdu_supp
+ #define mtk_wed_device_dma_reset(_dev) (_dev)->ops->reset_dma(_dev)
+ #define mtk_wed_device_setup_tc(_dev, _netdev, _type, _type_data) \
+ 	(_dev)->ops->setup_tc(_dev, _netdev, _type, _type_data)
++#define mtk_wed_device_start_hw_rro(_dev, _mask, _reset) \
++	(_dev)->ops->start_hw_rro(_dev, _mask, _reset)
++#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) \
++	(_dev)->ops->rro_rx_ring_setup(_dev, _ring, _regs)
++#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) \
++	(_dev)->ops->msdu_pg_rx_ring_setup(_dev, _ring, _regs)
++#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) \
++	(_dev)->ops->ind_rx_ring_setup(_dev, _regs)
++
+ #else
+ static inline bool mtk_wed_device_active(struct mtk_wed_device *dev)
+ {
+@@ -283,6 +324,10 @@ static inline bool mtk_wed_device_active
+ #define mtk_wed_device_stop(_dev) do {} while (0)
+ #define mtk_wed_device_dma_reset(_dev) do {} while (0)
+ #define mtk_wed_device_setup_tc(_dev, _netdev, _type, _type_data) -EOPNOTSUPP
++#define mtk_wed_device_start_hw_rro(_dev, _mask, _reset) do {} while (0)
++#define mtk_wed_device_rro_rx_ring_setup(_dev, _ring, _regs) -ENODEV
++#define mtk_wed_device_msdu_pg_rx_ring_setup(_dev, _ring, _regs) -ENODEV
++#define mtk_wed_device_ind_rx_ring_setup(_dev, _regs) -ENODEV
+ #endif
+ 
+ #endif
diff --git a/target/linux/generic/backport-5.15/752-18-v6.7-net-ethernet-mtk_wed-debugfs-move-wed_v2-specific-re.patch b/target/linux/generic/backport-5.15/752-18-v6.7-net-ethernet-mtk_wed-debugfs-move-wed_v2-specific-re.patch
new file mode 100644
index 00000000000..5ea43a44456
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-18-v6.7-net-ethernet-mtk_wed-debugfs-move-wed_v2-specific-re.patch
@@ -0,0 +1,78 @@
+From: Lorenzo Bianconi <lorenzo@kernel.org>
+Date: Mon, 18 Sep 2023 12:29:17 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: debugfs: move wed_v2 specific regs
+ out of regs array
+
+Move specific WED2.0 debugfs entries out of regs array. This is a
+preliminary patch to introduce WED 3.0 debugfs info.
+
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
+@@ -151,7 +151,7 @@ DEFINE_SHOW_ATTRIBUTE(wed_txinfo);
+ static int
+ wed_rxinfo_show(struct seq_file *s, void *data)
+ {
+-	static const struct reg_dump regs[] = {
++	static const struct reg_dump regs_common[] = {
+ 		DUMP_STR("WPDMA RX"),
+ 		DUMP_WPDMA_RX_RING(0),
+ 		DUMP_WPDMA_RX_RING(1),
+@@ -169,7 +169,7 @@ wed_rxinfo_show(struct seq_file *s, void
+ 		DUMP_WED_RING(WED_RING_RX_DATA(0)),
+ 		DUMP_WED_RING(WED_RING_RX_DATA(1)),
+ 
+-		DUMP_STR("WED RRO"),
++		DUMP_STR("WED WO RRO"),
+ 		DUMP_WED_RRO_RING(WED_RROQM_MIOD_CTRL0),
+ 		DUMP_WED(WED_RROQM_MID_MIB),
+ 		DUMP_WED(WED_RROQM_MOD_MIB),
+@@ -180,17 +180,6 @@ wed_rxinfo_show(struct seq_file *s, void
+ 		DUMP_WED(WED_RROQM_FDBK_ANC_MIB),
+ 		DUMP_WED(WED_RROQM_FDBK_ANC2H_MIB),
+ 
+-		DUMP_STR("WED Route QM"),
+-		DUMP_WED(WED_RTQM_R2H_MIB(0)),
+-		DUMP_WED(WED_RTQM_R2Q_MIB(0)),
+-		DUMP_WED(WED_RTQM_Q2H_MIB(0)),
+-		DUMP_WED(WED_RTQM_R2H_MIB(1)),
+-		DUMP_WED(WED_RTQM_R2Q_MIB(1)),
+-		DUMP_WED(WED_RTQM_Q2H_MIB(1)),
+-		DUMP_WED(WED_RTQM_Q2N_MIB),
+-		DUMP_WED(WED_RTQM_Q2B_MIB),
+-		DUMP_WED(WED_RTQM_PFDBK_MIB),
+-
+ 		DUMP_STR("WED WDMA TX"),
+ 		DUMP_WED(WED_WDMA_TX_MIB),
+ 		DUMP_WED_RING(WED_WDMA_RING_TX),
+@@ -211,11 +200,25 @@ wed_rxinfo_show(struct seq_file *s, void
+ 		DUMP_WED(WED_RX_BM_INTF),
+ 		DUMP_WED(WED_RX_BM_ERR_STS),
+ 	};
++	static const struct reg_dump regs_wed_v2[] = {
++		DUMP_STR("WED Route QM"),
++		DUMP_WED(WED_RTQM_R2H_MIB(0)),
++		DUMP_WED(WED_RTQM_R2Q_MIB(0)),
++		DUMP_WED(WED_RTQM_Q2H_MIB(0)),
++		DUMP_WED(WED_RTQM_R2H_MIB(1)),
++		DUMP_WED(WED_RTQM_R2Q_MIB(1)),
++		DUMP_WED(WED_RTQM_Q2H_MIB(1)),
++		DUMP_WED(WED_RTQM_Q2N_MIB),
++		DUMP_WED(WED_RTQM_Q2B_MIB),
++		DUMP_WED(WED_RTQM_PFDBK_MIB),
++	};
+ 	struct mtk_wed_hw *hw = s->private;
+ 	struct mtk_wed_device *dev = hw->wed_dev;
+ 
+-	if (dev)
+-		dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
++	if (dev) {
++		dump_wed_regs(s, dev, regs_common, ARRAY_SIZE(regs_common));
++		dump_wed_regs(s, dev, regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
++	}
+ 
+ 	return 0;
+ }
diff --git a/target/linux/generic/backport-5.15/752-19-v6.7-net-ethernet-mtk_wed-debugfs-add-WED-3.0-debugfs-ent.patch b/target/linux/generic/backport-5.15/752-19-v6.7-net-ethernet-mtk_wed-debugfs-add-WED-3.0-debugfs-ent.patch
new file mode 100644
index 00000000000..f491d2fd80c
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-19-v6.7-net-ethernet-mtk_wed-debugfs-add-WED-3.0-debugfs-ent.patch
@@ -0,0 +1,432 @@
+From: Sujuan Chen <sujuan.chen@mediatek.com>
+Date: Mon, 18 Sep 2023 12:29:18 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: debugfs: add WED 3.0 debugfs entries
+
+Introduce WED3.0 debugfs entries useful for debugging.
+
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed_debugfs.c
+@@ -11,6 +11,7 @@ struct reg_dump {
+ 	u16 offset;
+ 	u8 type;
+ 	u8 base;
++	u32 mask;
+ };
+ 
+ enum {
+@@ -25,6 +26,8 @@ enum {
+ 
+ #define DUMP_STR(_str) { _str, 0, DUMP_TYPE_STRING }
+ #define DUMP_REG(_reg, ...) { #_reg, MTK_##_reg, __VA_ARGS__ }
++#define DUMP_REG_MASK(_reg, _mask)	\
++	{ #_mask, MTK_##_reg, DUMP_TYPE_WED, 0, MTK_##_mask }
+ #define DUMP_RING(_prefix, _base, ...)				\
+ 	{ _prefix " BASE", _base, __VA_ARGS__ },		\
+ 	{ _prefix " CNT",  _base + 0x4, __VA_ARGS__ },	\
+@@ -32,6 +35,7 @@ enum {
+ 	{ _prefix " DIDX", _base + 0xc, __VA_ARGS__ }
+ 
+ #define DUMP_WED(_reg) DUMP_REG(_reg, DUMP_TYPE_WED)
++#define DUMP_WED_MASK(_reg, _mask) DUMP_REG_MASK(_reg, _mask)
+ #define DUMP_WED_RING(_base) DUMP_RING(#_base, MTK_##_base, DUMP_TYPE_WED)
+ 
+ #define DUMP_WDMA(_reg) DUMP_REG(_reg, DUMP_TYPE_WDMA)
+@@ -212,12 +216,58 @@ wed_rxinfo_show(struct seq_file *s, void
+ 		DUMP_WED(WED_RTQM_Q2B_MIB),
+ 		DUMP_WED(WED_RTQM_PFDBK_MIB),
+ 	};
++	static const struct reg_dump regs_wed_v3[] = {
++		DUMP_STR("WED RX RRO DATA"),
++		DUMP_WED_RING(WED_RRO_RX_D_RX(0)),
++		DUMP_WED_RING(WED_RRO_RX_D_RX(1)),
++
++		DUMP_STR("WED RX MSDU PAGE"),
++		DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(0)),
++		DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(1)),
++		DUMP_WED_RING(WED_RRO_MSDU_PG_CTRL0(2)),
++
++		DUMP_STR("WED RX IND CMD"),
++		DUMP_WED(WED_IND_CMD_RX_CTRL1),
++		DUMP_WED_MASK(WED_IND_CMD_RX_CTRL2, WED_IND_CMD_MAX_CNT),
++		DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_PROC_IDX),
++		DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_DMA_IDX),
++		DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0, WED_IND_CMD_MAGIC_CNT),
++		DUMP_WED_MASK(RRO_IND_CMD_SIGNATURE, RRO_IND_CMD_MAGIC_CNT),
++		DUMP_WED_MASK(WED_IND_CMD_RX_CTRL0,
++			      WED_IND_CMD_PREFETCH_FREE_CNT),
++		DUMP_WED_MASK(WED_RRO_CFG1, WED_RRO_CFG1_PARTICL_SE_ID),
++
++		DUMP_STR("WED ADDR ELEM"),
++		DUMP_WED(WED_ADDR_ELEM_CFG0),
++		DUMP_WED_MASK(WED_ADDR_ELEM_CFG1,
++			      WED_ADDR_ELEM_PREFETCH_FREE_CNT),
++
++		DUMP_STR("WED Route QM"),
++		DUMP_WED(WED_RTQM_ENQ_I2Q_DMAD_CNT),
++		DUMP_WED(WED_RTQM_ENQ_I2N_DMAD_CNT),
++		DUMP_WED(WED_RTQM_ENQ_I2Q_PKT_CNT),
++		DUMP_WED(WED_RTQM_ENQ_I2N_PKT_CNT),
++		DUMP_WED(WED_RTQM_ENQ_USED_ENTRY_CNT),
++		DUMP_WED(WED_RTQM_ENQ_ERR_CNT),
++
++		DUMP_WED(WED_RTQM_DEQ_DMAD_CNT),
++		DUMP_WED(WED_RTQM_DEQ_Q2I_DMAD_CNT),
++		DUMP_WED(WED_RTQM_DEQ_PKT_CNT),
++		DUMP_WED(WED_RTQM_DEQ_Q2I_PKT_CNT),
++		DUMP_WED(WED_RTQM_DEQ_USED_PFDBK_CNT),
++		DUMP_WED(WED_RTQM_DEQ_ERR_CNT),
++	};
+ 	struct mtk_wed_hw *hw = s->private;
+ 	struct mtk_wed_device *dev = hw->wed_dev;
+ 
+ 	if (dev) {
+ 		dump_wed_regs(s, dev, regs_common, ARRAY_SIZE(regs_common));
+-		dump_wed_regs(s, dev, regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
++		if (mtk_wed_is_v2(hw))
++			dump_wed_regs(s, dev,
++				      regs_wed_v2, ARRAY_SIZE(regs_wed_v2));
++		else
++			dump_wed_regs(s, dev,
++				      regs_wed_v3, ARRAY_SIZE(regs_wed_v3));
+ 	}
+ 
+ 	return 0;
+@@ -225,6 +275,314 @@ wed_rxinfo_show(struct seq_file *s, void
+ DEFINE_SHOW_ATTRIBUTE(wed_rxinfo);
+ 
+ static int
++wed_amsdu_show(struct seq_file *s, void *data)
++{
++	static const struct reg_dump regs[] = {
++		DUMP_STR("WED AMDSU INFO"),
++		DUMP_WED(WED_MON_AMSDU_FIFO_DMAD),
++
++		DUMP_STR("WED AMDSU ENG0 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(0)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(0)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(0)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(0)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(0)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(0),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(0),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(0),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG1 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(1)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(1)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(1)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(1)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(1)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(1),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(1),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(1),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG2 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(2)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(2)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(2)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(2)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(2)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(2),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(2),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(2),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG3 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(3)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(3)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(3)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(3)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(3)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(3),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(3),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(3),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG4 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(4)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(4)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(4)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(4)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(4)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(4),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(4),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG5 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(5)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(5)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(5)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(5)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(5)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(5),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(5),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(5),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG6 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(6)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(6)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(6)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(6)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(6)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(6),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(6),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(6),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG7 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(7)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(7)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(7)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(7)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(7)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(7),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(7),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(7),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(7),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(4),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED AMDSU ENG8 INFO"),
++		DUMP_WED(WED_MON_AMSDU_ENG_DMAD(8)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QFPL(8)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENI(8)),
++		DUMP_WED(WED_MON_AMSDU_ENG_QENO(8)),
++		DUMP_WED(WED_MON_AMSDU_ENG_MERG(8)),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(8),
++			      WED_AMSDU_ENG_MAX_PL_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT8(8),
++			      WED_AMSDU_ENG_MAX_QGPP_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
++			      WED_AMSDU_ENG_CUR_ENTRY),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
++			      WED_AMSDU_ENG_MAX_BUF_MERGED),
++		DUMP_WED_MASK(WED_MON_AMSDU_ENG_CNT9(8),
++			      WED_AMSDU_ENG_MAX_MSDU_MERGED),
++
++		DUMP_STR("WED QMEM INFO"),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(0), WED_AMSDU_QMEM_FQ_CNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(0), WED_AMSDU_QMEM_SP_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(1), WED_AMSDU_QMEM_TID0_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(1), WED_AMSDU_QMEM_TID1_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(2), WED_AMSDU_QMEM_TID2_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(2), WED_AMSDU_QMEM_TID3_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(3), WED_AMSDU_QMEM_TID4_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(3), WED_AMSDU_QMEM_TID5_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(4), WED_AMSDU_QMEM_TID6_QCNT),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_CNT(4), WED_AMSDU_QMEM_TID7_QCNT),
++
++		DUMP_STR("WED QMEM HEAD INFO"),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(0), WED_AMSDU_QMEM_FQ_HEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(0), WED_AMSDU_QMEM_SP_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(1), WED_AMSDU_QMEM_TID0_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(1), WED_AMSDU_QMEM_TID1_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(2), WED_AMSDU_QMEM_TID2_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(2), WED_AMSDU_QMEM_TID3_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(3), WED_AMSDU_QMEM_TID4_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(3), WED_AMSDU_QMEM_TID5_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(4), WED_AMSDU_QMEM_TID6_QHEAD),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(4), WED_AMSDU_QMEM_TID7_QHEAD),
++
++		DUMP_STR("WED QMEM TAIL INFO"),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(5), WED_AMSDU_QMEM_FQ_TAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(5), WED_AMSDU_QMEM_SP_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(6), WED_AMSDU_QMEM_TID0_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(6), WED_AMSDU_QMEM_TID1_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(7), WED_AMSDU_QMEM_TID2_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(7), WED_AMSDU_QMEM_TID3_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(8), WED_AMSDU_QMEM_TID4_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(8), WED_AMSDU_QMEM_TID5_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(9), WED_AMSDU_QMEM_TID6_QTAIL),
++		DUMP_WED_MASK(WED_MON_AMSDU_QMEM_PTR(9), WED_AMSDU_QMEM_TID7_QTAIL),
++
++		DUMP_STR("WED HIFTXD MSDU INFO"),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(1)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(2)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(3)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(4)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(5)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(6)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(7)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(8)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(9)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(10)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(11)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(12)),
++		DUMP_WED(WED_MON_AMSDU_HIFTXD_FETCH_MSDU(13)),
++	};
++	struct mtk_wed_hw *hw = s->private;
++	struct mtk_wed_device *dev = hw->wed_dev;
++
++	if (dev)
++		dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(wed_amsdu);
++
++static int
++wed_rtqm_show(struct seq_file *s, void *data)
++{
++	static const struct reg_dump regs[] = {
++		DUMP_STR("WED Route QM IGRS0(N2H + Recycle)"),
++		DUMP_WED(WED_RTQM_IGRS0_I2HW_DMAD_CNT),
++		DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS0_I2H_DMAD_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS0_I2HW_PKT_CNT),
++		DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS0_I2H_PKT_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS0_FDROP_CNT),
++
++		DUMP_STR("WED Route QM IGRS1(Legacy)"),
++		DUMP_WED(WED_RTQM_IGRS1_I2HW_DMAD_CNT),
++		DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS1_I2H_DMAD_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS1_I2HW_PKT_CNT),
++		DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS1_I2H_PKT_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS1_FDROP_CNT),
++
++		DUMP_STR("WED Route QM IGRS2(RRO3.0)"),
++		DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
++		DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS2_I2H_DMAD_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS2_I2HW_PKT_CNT),
++		DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS2_I2H_PKT_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS2_FDROP_CNT),
++
++		DUMP_STR("WED Route QM IGRS3(DEBUG)"),
++		DUMP_WED(WED_RTQM_IGRS2_I2HW_DMAD_CNT),
++		DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS3_I2H_DMAD_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS3_I2HW_PKT_CNT),
++		DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(0)),
++		DUMP_WED(WED_RTQM_IGRS3_I2H_PKT_CNT(1)),
++		DUMP_WED(WED_RTQM_IGRS3_FDROP_CNT),
++	};
++	struct mtk_wed_hw *hw = s->private;
++	struct mtk_wed_device *dev = hw->wed_dev;
++
++	if (dev)
++		dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(wed_rtqm);
++
++static int
++wed_rro_show(struct seq_file *s, void *data)
++{
++	static const struct reg_dump regs[] = {
++		DUMP_STR("RRO/IND CMD CNT"),
++		DUMP_WED(WED_RX_IND_CMD_CNT(1)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(2)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(3)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(4)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(5)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(6)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(7)),
++		DUMP_WED(WED_RX_IND_CMD_CNT(8)),
++		DUMP_WED_MASK(WED_RX_IND_CMD_CNT(9),
++			      WED_IND_CMD_MAGIC_CNT_FAIL_CNT),
++
++		DUMP_WED(WED_RX_ADDR_ELEM_CNT(0)),
++		DUMP_WED_MASK(WED_RX_ADDR_ELEM_CNT(1),
++			      WED_ADDR_ELEM_SIG_FAIL_CNT),
++		DUMP_WED(WED_RX_MSDU_PG_CNT(1)),
++		DUMP_WED(WED_RX_MSDU_PG_CNT(2)),
++		DUMP_WED(WED_RX_MSDU_PG_CNT(3)),
++		DUMP_WED(WED_RX_MSDU_PG_CNT(4)),
++		DUMP_WED(WED_RX_MSDU_PG_CNT(5)),
++		DUMP_WED_MASK(WED_RX_PN_CHK_CNT,
++			      WED_PN_CHK_FAIL_CNT),
++	};
++	struct mtk_wed_hw *hw = s->private;
++	struct mtk_wed_device *dev = hw->wed_dev;
++
++	if (dev)
++		dump_wed_regs(s, dev, regs, ARRAY_SIZE(regs));
++
++	return 0;
++}
++DEFINE_SHOW_ATTRIBUTE(wed_rro);
++
++static int
+ mtk_wed_reg_set(void *data, u64 val)
+ {
+ 	struct mtk_wed_hw *hw = data;
+@@ -266,7 +624,16 @@ void mtk_wed_hw_add_debugfs(struct mtk_w
+ 	debugfs_create_u32("regidx", 0600, dir, &hw->debugfs_reg);
+ 	debugfs_create_file_unsafe("regval", 0600, dir, hw, &fops_regval);
+ 	debugfs_create_file_unsafe("txinfo", 0400, dir, hw, &wed_txinfo_fops);
+-	if (!mtk_wed_is_v1(hw))
++	if (!mtk_wed_is_v1(hw)) {
+ 		debugfs_create_file_unsafe("rxinfo", 0400, dir, hw,
+ 					   &wed_rxinfo_fops);
++		if (mtk_wed_is_v3_or_greater(hw)) {
++			debugfs_create_file_unsafe("amsdu", 0400, dir, hw,
++						   &wed_amsdu_fops);
++			debugfs_create_file_unsafe("rtqm", 0400, dir, hw,
++						   &wed_rtqm_fops);
++			debugfs_create_file_unsafe("rro", 0400, dir, hw,
++						   &wed_rro_fops);
++		}
++	}
+ }
diff --git a/target/linux/generic/backport-5.15/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch b/target/linux/generic/backport-5.15/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch
new file mode 100644
index 00000000000..aaaabf05e8b
--- /dev/null
+++ b/target/linux/generic/backport-5.15/752-20-v6.7-net-ethernet-mtk_wed-add-wed-3.0-reset-support.patch
@@ -0,0 +1,587 @@
+From: Sujuan Chen <sujuan.chen@mediatek.com>
+Date: Mon, 18 Sep 2023 12:29:19 +0200
+Subject: [PATCH] net: ethernet: mtk_wed: add wed 3.0 reset support
+
+Introduce support for resetting Wireless Ethernet Dispatcher 3.0
+available on MT988 SoC.
+
+Co-developed-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
+Signed-off-by: Sujuan Chen <sujuan.chen@mediatek.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+
+--- a/drivers/net/ethernet/mediatek/mtk_wed.c
++++ b/drivers/net/ethernet/mediatek/mtk_wed.c
+@@ -148,6 +148,90 @@ mtk_wdma_read_reset(struct mtk_wed_devic
+ 	return wdma_r32(dev, MTK_WDMA_GLO_CFG);
+ }
+ 
++static void
++mtk_wdma_v3_rx_reset(struct mtk_wed_device *dev)
++{
++	u32 status;
++
++	if (!mtk_wed_is_v3_or_greater(dev->hw))
++		return;
++
++	wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
++	wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))
++		dev_err(dev->hw->dev, "rx reset failed\n");
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))
++		dev_err(dev->hw->dev, "rx reset failed\n");
++
++	wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
++	wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))
++		dev_err(dev->hw->dev, "rx reset failed\n");
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))
++		dev_err(dev->hw->dev, "rx reset failed\n");
++
++	/* prefetch FIFO */
++	wdma_w32(dev, MTK_WDMA_PREF_RX_FIFO_CFG,
++		 MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR |
++		 MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR);
++	wdma_clr(dev, MTK_WDMA_PREF_RX_FIFO_CFG,
++		 MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR |
++		 MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR);
++
++	/* core FIFO */
++	wdma_w32(dev, MTK_WDMA_XDMA_RX_FIFO_CFG,
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR);
++	wdma_clr(dev, MTK_WDMA_XDMA_RX_FIFO_CFG,
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR);
++
++	/* writeback FIFO */
++	wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),
++		 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
++	wdma_w32(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1),
++		 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
++
++	wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(0),
++		 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
++	wdma_clr(dev, MTK_WDMA_WRBK_RX_FIFO_CFG(1),
++		 MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR);
++
++	/* prefetch ring status */
++	wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG,
++		 MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR);
++	wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG,
++		 MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR);
++
++	/* writeback ring status */
++	wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG,
++		 MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR);
++	wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG,
++		 MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR);
++}
++
+ static int
+ mtk_wdma_rx_reset(struct mtk_wed_device *dev)
+ {
+@@ -160,6 +244,7 @@ mtk_wdma_rx_reset(struct mtk_wed_device
+ 	if (ret)
+ 		dev_err(dev->hw->dev, "rx reset failed\n");
+ 
++	mtk_wdma_v3_rx_reset(dev);
+ 	wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_RX);
+ 	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
+ 
+@@ -192,6 +277,84 @@ mtk_wed_poll_busy(struct mtk_wed_device
+ }
+ 
+ static void
++mtk_wdma_v3_tx_reset(struct mtk_wed_device *dev)
++{
++	u32 status;
++
++	if (!mtk_wed_is_v3_or_greater(dev->hw))
++		return;
++
++	wdma_clr(dev, MTK_WDMA_PREF_TX_CFG, MTK_WDMA_PREF_TX_CFG_PREF_EN);
++	wdma_clr(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_PREF_TX_CFG_PREF_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_PREF_TX_CFG))
++		dev_err(dev->hw->dev, "tx reset failed\n");
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_PREF_RX_CFG_PREF_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_PREF_RX_CFG))
++		dev_err(dev->hw->dev, "tx reset failed\n");
++
++	wdma_clr(dev, MTK_WDMA_WRBK_TX_CFG, MTK_WDMA_WRBK_TX_CFG_WRBK_EN);
++	wdma_clr(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_WRBK_TX_CFG))
++		dev_err(dev->hw->dev, "tx reset failed\n");
++
++	if (read_poll_timeout(wdma_r32, status,
++			      !(status & MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY),
++			      0, 10000, false, dev, MTK_WDMA_WRBK_RX_CFG))
++		dev_err(dev->hw->dev, "tx reset failed\n");
++
++	/* prefetch FIFO */
++	wdma_w32(dev, MTK_WDMA_PREF_TX_FIFO_CFG,
++		 MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR |
++		 MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR);
++	wdma_clr(dev, MTK_WDMA_PREF_TX_FIFO_CFG,
++		 MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR |
++		 MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR);
++
++	/* core FIFO */
++	wdma_w32(dev, MTK_WDMA_XDMA_TX_FIFO_CFG,
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR);
++	wdma_clr(dev, MTK_WDMA_XDMA_TX_FIFO_CFG,
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR |
++		 MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR);
++
++	/* writeback FIFO */
++	wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),
++		 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
++	wdma_w32(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1),
++		 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
++
++	wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(0),
++		 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
++	wdma_clr(dev, MTK_WDMA_WRBK_TX_FIFO_CFG(1),
++		 MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR);
++
++	/* prefetch ring status */
++	wdma_w32(dev, MTK_WDMA_PREF_SIDX_CFG,
++		 MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR);
++	wdma_clr(dev, MTK_WDMA_PREF_SIDX_CFG,
++		 MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR);
++
++	/* writeback ring status */
++	wdma_w32(dev, MTK_WDMA_WRBK_SIDX_CFG,
++		 MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR);
++	wdma_clr(dev, MTK_WDMA_WRBK_SIDX_CFG,
++		 MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR);
++}
++
++static void
+ mtk_wdma_tx_reset(struct mtk_wed_device *dev)
+ {
+ 	u32 status, mask = MTK_WDMA_GLO_CFG_TX_DMA_BUSY;
+@@ -202,6 +365,7 @@ mtk_wdma_tx_reset(struct mtk_wed_device
+ 			       !(status & mask), 0, 10000))
+ 		dev_err(dev->hw->dev, "tx reset failed\n");
+ 
++	mtk_wdma_v3_tx_reset(dev);
+ 	wdma_w32(dev, MTK_WDMA_RESET_IDX, MTK_WDMA_RESET_IDX_TX);
+ 	wdma_w32(dev, MTK_WDMA_RESET_IDX, 0);
+ 
+@@ -1405,13 +1569,33 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 	if (ret)
+ 		return ret;
+ 
++	if (dev->wlan.hw_rro) {
++		wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_IND_CMD_EN);
++		mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_HW_STS,
++				  MTK_WED_RX_IND_CMD_BUSY);
++		mtk_wed_reset(dev, MTK_WED_RESET_RRO_RX_TO_PG);
++	}
++
+ 	wed_clr(dev, MTK_WED_WPDMA_RX_D_GLO_CFG, MTK_WED_WPDMA_RX_D_RX_DRV_EN);
+ 	ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_GLO_CFG,
+ 				MTK_WED_WPDMA_RX_D_RX_DRV_BUSY);
++	if (!ret && mtk_wed_is_v3_or_greater(dev->hw))
++		ret = mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
++					MTK_WED_WPDMA_RX_D_PREF_BUSY);
+ 	if (ret) {
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_D_DRV);
+ 	} else {
++		if (mtk_wed_is_v3_or_greater(dev->hw)) {
++			/* 1.a. disable prefetch HW */
++			wed_clr(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
++				MTK_WED_WPDMA_RX_D_PREF_EN);
++			mtk_wed_poll_busy(dev, MTK_WED_WPDMA_RX_D_PREF_CFG,
++					  MTK_WED_WPDMA_RX_D_PREF_BUSY);
++			wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
++				MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL);
++		}
++
+ 		wed_w32(dev, MTK_WED_WPDMA_RX_D_RST_IDX,
+ 			MTK_WED_WPDMA_RX_D_RST_CRX_IDX |
+ 			MTK_WED_WPDMA_RX_D_RST_DRV_IDX);
+@@ -1439,23 +1623,52 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 		wed_w32(dev, MTK_WED_RROQM_RST_IDX, 0);
+ 	}
+ 
++	if (dev->wlan.hw_rro) {
++		/* disable rro msdu page drv */
++		wed_clr(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
++			MTK_WED_RRO_MSDU_PG_DRV_EN);
++
++		/* disable rro data drv */
++		wed_clr(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_RX_D_DRV_EN);
++
++		/* rro msdu page drv reset */
++		wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
++			MTK_WED_RRO_MSDU_PG_DRV_CLR);
++		mtk_wed_poll_busy(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
++				  MTK_WED_RRO_MSDU_PG_DRV_CLR);
++
++		/* rro data drv reset */
++		wed_w32(dev, MTK_WED_RRO_RX_D_CFG(2),
++			MTK_WED_RRO_RX_D_DRV_CLR);
++		mtk_wed_poll_busy(dev, MTK_WED_RRO_RX_D_CFG(2),
++				  MTK_WED_RRO_RX_D_DRV_CLR);
++	}
++
+ 	/* reset route qm */
+ 	wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_RX_ROUTE_QM_EN);
+ 	ret = mtk_wed_poll_busy(dev, MTK_WED_CTRL,
+ 				MTK_WED_CTRL_RX_ROUTE_QM_BUSY);
+-	if (ret)
++	if (ret) {
+ 		mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
+-	else
+-		wed_set(dev, MTK_WED_RTQM_GLO_CFG,
+-			MTK_WED_RTQM_Q_RST);
++	} else if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		wed_set(dev, MTK_WED_RTQM_RST, BIT(0));
++		wed_clr(dev, MTK_WED_RTQM_RST, BIT(0));
++		mtk_wed_reset(dev, MTK_WED_RESET_RX_ROUTE_QM);
++	} else {
++		wed_set(dev, MTK_WED_RTQM_GLO_CFG, MTK_WED_RTQM_Q_RST);
++	}
+ 
+ 	/* reset tx wdma */
+ 	mtk_wdma_tx_reset(dev);
+ 
+ 	/* reset tx wdma drv */
+ 	wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_TX_DRV_EN);
+-	mtk_wed_poll_busy(dev, MTK_WED_CTRL,
+-			  MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
++	if (mtk_wed_is_v3_or_greater(dev->hw))
++		mtk_wed_poll_busy(dev, MTK_WED_WPDMA_STATUS,
++				  MTK_WED_WPDMA_STATUS_TX_DRV);
++	else
++		mtk_wed_poll_busy(dev, MTK_WED_CTRL,
++				  MTK_WED_CTRL_WDMA_INT_AGENT_BUSY);
+ 	mtk_wed_reset(dev, MTK_WED_RESET_WDMA_TX_DRV);
+ 
+ 	/* reset wed rx dma */
+@@ -1476,6 +1689,14 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 			  MTK_WED_CTRL_WED_RX_BM_BUSY);
+ 	mtk_wed_reset(dev, MTK_WED_RESET_RX_BM);
+ 
++	if (dev->wlan.hw_rro) {
++		wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_RX_PG_BM_EN);
++		mtk_wed_poll_busy(dev, MTK_WED_CTRL,
++				  MTK_WED_CTRL_WED_RX_PG_BM_BUSY);
++		wed_set(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM);
++		wed_clr(dev, MTK_WED_RESET, MTK_WED_RESET_RX_PG_BM);
++	}
++
+ 	/* wo change to enable state */
+ 	val = MTK_WED_WO_STATE_ENABLE;
+ 	ret = mtk_wed_mcu_send_msg(wo, MTK_WED_MODULE_ID_WO,
+@@ -1493,6 +1714,7 @@ mtk_wed_rx_reset(struct mtk_wed_device *
+ 				   false);
+ 	}
+ 	mtk_wed_free_rx_buffer(dev);
++	mtk_wed_hwrro_free_buffer(dev);
+ 
+ 	return 0;
+ }
+@@ -1526,15 +1748,41 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 
+ 	/* 2. reset WDMA rx DMA */
+ 	busy = !!mtk_wdma_rx_reset(dev);
+-	wed_clr(dev, MTK_WED_WDMA_GLO_CFG, MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		val = MTK_WED_WDMA_GLO_CFG_RX_DIS_FSM_AUTO_IDLE |
++		      wed_r32(dev, MTK_WED_WDMA_GLO_CFG);
++		val &= ~MTK_WED_WDMA_GLO_CFG_RX_DRV_EN;
++		wed_w32(dev, MTK_WED_WDMA_GLO_CFG, val);
++	} else {
++		wed_clr(dev, MTK_WED_WDMA_GLO_CFG,
++			MTK_WED_WDMA_GLO_CFG_RX_DRV_EN);
++	}
++
+ 	if (!busy)
+ 		busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_GLO_CFG,
+ 					 MTK_WED_WDMA_GLO_CFG_RX_DRV_BUSY);
++	if (!busy && mtk_wed_is_v3_or_greater(dev->hw))
++		busy = mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG,
++					 MTK_WED_WDMA_RX_PREF_BUSY);
+ 
+ 	if (busy) {
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WDMA_INT_AGENT);
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WDMA_RX_DRV);
+ 	} else {
++		if (mtk_wed_is_v3_or_greater(dev->hw)) {
++			/* 1.a. disable prefetch HW */
++			wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
++				MTK_WED_WDMA_RX_PREF_EN);
++			mtk_wed_poll_busy(dev, MTK_WED_WDMA_RX_PREF_CFG,
++					  MTK_WED_WDMA_RX_PREF_BUSY);
++			wed_clr(dev, MTK_WED_WDMA_RX_PREF_CFG,
++				MTK_WED_WDMA_RX_PREF_DDONE2_EN);
++
++			/* 2. Reset dma index */
++			wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
++				MTK_WED_WDMA_RESET_IDX_RX_ALL);
++		}
++
+ 		wed_w32(dev, MTK_WED_WDMA_RESET_IDX,
+ 			MTK_WED_WDMA_RESET_IDX_RX | MTK_WED_WDMA_RESET_IDX_DRV);
+ 		wed_w32(dev, MTK_WED_WDMA_RESET_IDX, 0);
+@@ -1550,8 +1798,13 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 	wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_WED_TX_FREE_AGENT_EN);
+ 
+ 	for (i = 0; i < 100; i++) {
+-		val = wed_r32(dev, MTK_WED_TX_BM_INTF);
+-		if (FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP, val) == 0x40)
++		if (mtk_wed_is_v1(dev->hw))
++			val = FIELD_GET(MTK_WED_TX_BM_INTF_TKFIFO_FDEP,
++					wed_r32(dev, MTK_WED_TX_BM_INTF));
++		else
++			val = FIELD_GET(MTK_WED_TX_TKID_INTF_TKFIFO_FDEP,
++					wed_r32(dev, MTK_WED_TX_TKID_INTF));
++		if (val == 0x40)
+ 			break;
+ 	}
+ 
+@@ -1573,6 +1826,8 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_INT_AGENT);
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_TX_DRV);
+ 		mtk_wed_reset(dev, MTK_WED_RESET_WPDMA_RX_DRV);
++		if (mtk_wed_is_v3_or_greater(dev->hw))
++			wed_w32(dev, MTK_WED_RX1_CTRL2, 0);
+ 	} else {
+ 		wed_w32(dev, MTK_WED_WPDMA_RESET_IDX,
+ 			MTK_WED_WPDMA_RESET_IDX_TX |
+@@ -1589,7 +1844,14 @@ mtk_wed_reset_dma(struct mtk_wed_device
+ 		wed_w32(dev, MTK_WED_RESET_IDX, 0);
+ 	}
+ 
+-	mtk_wed_rx_reset(dev);
++	if (mtk_wed_is_v3_or_greater(dev->hw)) {
++		/* reset amsdu engine */
++		wed_clr(dev, MTK_WED_CTRL, MTK_WED_CTRL_TX_AMSDU_EN);
++		mtk_wed_reset(dev, MTK_WED_RESET_TX_AMSDU);
++	}
++
++	if (mtk_wed_get_rx_capa(dev))
++		mtk_wed_rx_reset(dev);
+ }
+ 
+ static int
+@@ -1841,6 +2103,7 @@ mtk_wed_dma_enable(struct mtk_wed_device
+ 			MTK_WED_WPDMA_GLO_CFG_RX_DRV_UNS_VER_FORCE_4);
+ 
+ 		wdma_set(dev, MTK_WDMA_PREF_RX_CFG, MTK_WDMA_PREF_RX_CFG_PREF_EN);
++		wdma_set(dev, MTK_WDMA_WRBK_RX_CFG, MTK_WDMA_WRBK_RX_CFG_WRBK_EN);
+ 	}
+ 
+ 	wed_clr(dev, MTK_WED_WPDMA_GLO_CFG,
+@@ -1904,6 +2167,12 @@ mtk_wed_start_hw_rro(struct mtk_wed_devi
+ 	if (!mtk_wed_get_rx_capa(dev) || !dev->wlan.hw_rro)
+ 		return;
+ 
++	if (reset) {
++		wed_set(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
++			MTK_WED_RRO_MSDU_PG_DRV_EN);
++		return;
++	}
++
+ 	wed_set(dev, MTK_WED_RRO_RX_D_CFG(2), MTK_WED_RRO_MSDU_PG_DRV_CLR);
+ 	wed_w32(dev, MTK_WED_RRO_MSDU_PG_RING2_CFG,
+ 		MTK_WED_RRO_MSDU_PG_DRV_CLR);
+--- a/drivers/net/ethernet/mediatek/mtk_wed_regs.h
++++ b/drivers/net/ethernet/mediatek/mtk_wed_regs.h
+@@ -28,6 +28,8 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RESET					0x008
+ #define MTK_WED_RESET_TX_BM				BIT(0)
+ #define MTK_WED_RESET_RX_BM				BIT(1)
++#define MTK_WED_RESET_RX_PG_BM				BIT(2)
++#define MTK_WED_RESET_RRO_RX_TO_PG			BIT(3)
+ #define MTK_WED_RESET_TX_FREE_AGENT			BIT(4)
+ #define MTK_WED_RESET_WPDMA_TX_DRV			BIT(8)
+ #define MTK_WED_RESET_WPDMA_RX_DRV			BIT(9)
+@@ -106,6 +108,9 @@ struct mtk_wdma_desc {
+ #define MTK_WED_STATUS					0x060
+ #define MTK_WED_STATUS_TX				GENMASK(15, 8)
+ 
++#define MTK_WED_WPDMA_STATUS				0x068
++#define MTK_WED_WPDMA_STATUS_TX_DRV			GENMASK(15, 8)
++
+ #define MTK_WED_TX_BM_CTRL				0x080
+ #define MTK_WED_TX_BM_CTRL_VLD_GRP_NUM			GENMASK(6, 0)
+ #define MTK_WED_TX_BM_CTRL_RSV_GRP_NUM			GENMASK(22, 16)
+@@ -140,6 +145,9 @@ struct mtk_wdma_desc {
+ #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM		GENMASK(22, 16)
+ #define MTK_WED_TX_TKID_CTRL_PAUSE			BIT(28)
+ 
++#define MTK_WED_TX_TKID_INTF				0x0dc
++#define MTK_WED_TX_TKID_INTF_TKFIFO_FDEP		GENMASK(25, 16)
++
+ #define MTK_WED_TX_TKID_CTRL_VLD_GRP_NUM_V3		GENMASK(7, 0)
+ #define MTK_WED_TX_TKID_CTRL_RSV_GRP_NUM_V3		GENMASK(23, 16)
+ 
+@@ -190,6 +198,7 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RING_RX_DATA(_n)			(0x420 + (_n) * 0x10)
+ 
+ #define MTK_WED_SCR0					0x3c0
++#define MTK_WED_RX1_CTRL2				0x418
+ #define MTK_WED_WPDMA_INT_TRIGGER			0x504
+ #define MTK_WED_WPDMA_INT_TRIGGER_RX_DONE		BIT(1)
+ #define MTK_WED_WPDMA_INT_TRIGGER_TX_DONE		GENMASK(5, 4)
+@@ -303,6 +312,7 @@ struct mtk_wdma_desc {
+ 
+ #define MTK_WED_WPDMA_RX_D_RST_IDX			0x760
+ #define MTK_WED_WPDMA_RX_D_RST_CRX_IDX			GENMASK(17, 16)
++#define MTK_WED_WPDMA_RX_D_RST_DRV_IDX_ALL		BIT(20)
+ #define MTK_WED_WPDMA_RX_D_RST_DRV_IDX			GENMASK(25, 24)
+ 
+ #define MTK_WED_WPDMA_RX_GLO_CFG			0x76c
+@@ -313,6 +323,7 @@ struct mtk_wdma_desc {
+ 
+ #define MTK_WED_WPDMA_RX_D_PREF_CFG			0x7b4
+ #define MTK_WED_WPDMA_RX_D_PREF_EN			BIT(0)
++#define MTK_WED_WPDMA_RX_D_PREF_BUSY			BIT(1)
+ #define MTK_WED_WPDMA_RX_D_PREF_BURST_SIZE		GENMASK(12, 8)
+ #define MTK_WED_WPDMA_RX_D_PREF_LOW_THRES		GENMASK(21, 16)
+ 
+@@ -334,11 +345,13 @@ struct mtk_wdma_desc {
+ 
+ #define MTK_WED_WDMA_RX_PREF_CFG			0x950
+ #define MTK_WED_WDMA_RX_PREF_EN				BIT(0)
++#define MTK_WED_WDMA_RX_PREF_BUSY			BIT(1)
+ #define MTK_WED_WDMA_RX_PREF_BURST_SIZE			GENMASK(12, 8)
+ #define MTK_WED_WDMA_RX_PREF_LOW_THRES			GENMASK(21, 16)
+ #define MTK_WED_WDMA_RX_PREF_RX0_SIDX_CLR		BIT(24)
+ #define MTK_WED_WDMA_RX_PREF_RX1_SIDX_CLR		BIT(25)
+ #define MTK_WED_WDMA_RX_PREF_DDONE2_EN			BIT(26)
++#define MTK_WED_WDMA_RX_PREF_DDONE2_BUSY		BIT(27)
+ 
+ #define MTK_WED_WDMA_RX_PREF_FIFO_CFG			0x95C
+ #define MTK_WED_WDMA_RX_PREF_FIFO_RX0_CLR		BIT(0)
+@@ -367,6 +380,7 @@ struct mtk_wdma_desc {
+ 
+ #define MTK_WED_WDMA_RESET_IDX				0xa08
+ #define MTK_WED_WDMA_RESET_IDX_RX			GENMASK(17, 16)
++#define MTK_WED_WDMA_RESET_IDX_RX_ALL			BIT(20)
+ #define MTK_WED_WDMA_RESET_IDX_DRV			GENMASK(25, 24)
+ 
+ #define MTK_WED_WDMA_INT_CLR				0xa24
+@@ -437,21 +451,62 @@ struct mtk_wdma_desc {
+ #define MTK_WDMA_INT_MASK_RX_DELAY			BIT(30)
+ #define MTK_WDMA_INT_MASK_RX_COHERENT			BIT(31)
+ 
++#define MTK_WDMA_XDMA_TX_FIFO_CFG			0x238
++#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_PAR_FIFO_CLEAR	BIT(0)
++#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_CMD_FIFO_CLEAR	BIT(4)
++#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_DMAD_FIFO_CLEAR	BIT(8)
++#define MTK_WDMA_XDMA_TX_FIFO_CFG_TX_ARR_FIFO_CLEAR	BIT(12)
++
++#define MTK_WDMA_XDMA_RX_FIFO_CFG			0x23c
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_PAR_FIFO_CLEAR	BIT(0)
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_CMD_FIFO_CLEAR	BIT(4)
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_DMAD_FIFO_CLEAR	BIT(8)
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_ARR_FIFO_CLEAR	BIT(12)
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_LEN_FIFO_CLEAR	BIT(15)
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_WID_FIFO_CLEAR	BIT(18)
++#define MTK_WDMA_XDMA_RX_FIFO_CFG_RX_BID_FIFO_CLEAR	BIT(21)
++
+ #define MTK_WDMA_INT_GRP1				0x250
+ #define MTK_WDMA_INT_GRP2				0x254
+ 
+ #define MTK_WDMA_PREF_TX_CFG				0x2d0
+ #define MTK_WDMA_PREF_TX_CFG_PREF_EN			BIT(0)
++#define MTK_WDMA_PREF_TX_CFG_PREF_BUSY			BIT(1)
+ 
+ #define MTK_WDMA_PREF_RX_CFG				0x2dc
+ #define MTK_WDMA_PREF_RX_CFG_PREF_EN			BIT(0)
++#define MTK_WDMA_PREF_RX_CFG_PREF_BUSY			BIT(1)
++
++#define MTK_WDMA_PREF_RX_FIFO_CFG			0x2e0
++#define MTK_WDMA_PREF_RX_FIFO_CFG_RING0_CLEAR		BIT(0)
++#define MTK_WDMA_PREF_RX_FIFO_CFG_RING1_CLEAR		BIT(16)
++
++#define MTK_WDMA_PREF_TX_FIFO_CFG			0x2d4
++#define MTK_WDMA_PREF_TX_FIFO_CFG_RING0_CLEAR		BIT(0)
++#define MTK_WDMA_PREF_TX_FIFO_CFG_RING1_CLEAR		BIT(16)
++
++#define MTK_WDMA_PREF_SIDX_CFG				0x2e4
++#define MTK_WDMA_PREF_SIDX_CFG_TX_RING_CLEAR		GENMASK(3, 0)
++#define MTK_WDMA_PREF_SIDX_CFG_RX_RING_CLEAR		GENMASK(5, 4)
+ 
+ #define MTK_WDMA_WRBK_TX_CFG				0x300
++#define MTK_WDMA_WRBK_TX_CFG_WRBK_BUSY			BIT(0)
+ #define MTK_WDMA_WRBK_TX_CFG_WRBK_EN			BIT(30)
+ 
++#define MTK_WDMA_WRBK_TX_FIFO_CFG(_n)			(0x304 + (_n) * 0x4)
++#define MTK_WDMA_WRBK_TX_FIFO_CFG_RING_CLEAR		BIT(0)
++
+ #define MTK_WDMA_WRBK_RX_CFG				0x344
++#define MTK_WDMA_WRBK_RX_CFG_WRBK_BUSY			BIT(0)
+ #define MTK_WDMA_WRBK_RX_CFG_WRBK_EN			BIT(30)
+ 
++#define MTK_WDMA_WRBK_RX_FIFO_CFG(_n)			(0x348 + (_n) * 0x4)
++#define MTK_WDMA_WRBK_RX_FIFO_CFG_RING_CLEAR		BIT(0)
++
++#define MTK_WDMA_WRBK_SIDX_CFG				0x388
++#define MTK_WDMA_WRBK_SIDX_CFG_TX_RING_CLEAR		GENMASK(3, 0)
++#define MTK_WDMA_WRBK_SIDX_CFG_RX_RING_CLEAR		GENMASK(5, 4)
++
+ #define MTK_PCIE_MIRROR_MAP(n)				((n) ? 0x4 : 0x0)
+ #define MTK_PCIE_MIRROR_MAP_EN				BIT(0)
+ #define MTK_PCIE_MIRROR_MAP_WED_ID			BIT(1)
+@@ -465,6 +520,8 @@ struct mtk_wdma_desc {
+ #define MTK_WED_RTQM_Q_DBG_BYPASS			BIT(5)
+ #define MTK_WED_RTQM_TXDMAD_FPORT			GENMASK(23, 20)
+ 
++#define MTK_WED_RTQM_RST				0xb04
++
+ #define MTK_WED_RTQM_IGRS0_I2HW_DMAD_CNT		0xb1c
+ #define MTK_WED_RTQM_IGRS0_I2H_DMAD_CNT(_n)		(0xb20 + (_n) * 0x4)
+ #define	MTK_WED_RTQM_IGRS0_I2HW_PKT_CNT			0xb28
+@@ -653,6 +710,9 @@ struct mtk_wdma_desc {
+ #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_CLR		BIT(17)
+ #define MTK_WED_WPDMA_INT_CTRL_RRO_PG2_DONE_TRIG	GENMASK(22, 18)
+ 
++#define MTK_WED_RRO_RX_HW_STS				0xf00
++#define MTK_WED_RX_IND_CMD_BUSY				GENMASK(31, 0)
++
+ #define MTK_WED_RX_IND_CMD_CNT0				0xf20
+ #define MTK_WED_RX_IND_CMD_DBG_CNT_EN			BIT(31)
+ 
diff --git a/target/linux/generic/backport-5.15/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch b/target/linux/generic/backport-5.15/764-01-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/751-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch
rename to target/linux/generic/backport-5.15/764-01-v5.16-net-dsa-qca8k-fix-internal-delay-applied-to-the-wrong-PAD.patch
diff --git a/target/linux/generic/backport-5.15/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch b/target/linux/generic/backport-5.15/764-02-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/752-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch
rename to target/linux/generic/backport-5.15/764-02-v5.16-net-dsa-qca8k-fix-MTU-calculation.patch
diff --git a/target/linux/generic/backport-5.15/753-v5.17-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch b/target/linux/generic/backport-5.15/764-03-v5.17-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/753-v5.17-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch
rename to target/linux/generic/backport-5.15/764-03-v5.17-net-next-net-dsa-qca8k-remove-redundant-check-in-parse_port_config.patch
diff --git a/target/linux/generic/backport-5.15/754-v5.17-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch b/target/linux/generic/backport-5.15/764-04-v5.17-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/754-v5.17-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch
rename to target/linux/generic/backport-5.15/764-04-v5.17-net-next-net-dsa-qca8k-convert-to-GENMASK_FIELD_PREP_FIELD_GET.patch
diff --git a/target/linux/generic/backport-5.15/755-v5.17-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch b/target/linux/generic/backport-5.15/764-05-v5.17-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/755-v5.17-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch
rename to target/linux/generic/backport-5.15/764-05-v5.17-net-next-net-dsa-qca8k-remove-extra-mutex_init-in-qca8k_setup.patch
diff --git a/target/linux/generic/backport-5.15/756-v5.17-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch b/target/linux/generic/backport-5.15/764-06-v5.17-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/756-v5.17-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch
rename to target/linux/generic/backport-5.15/764-06-v5.17-net-next-net-dsa-qca8k-move-regmap-init-in-probe-and-set-it.patch
diff --git a/target/linux/generic/backport-5.15/757-v5.17-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch b/target/linux/generic/backport-5.15/764-07-v5.17-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/757-v5.17-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch
rename to target/linux/generic/backport-5.15/764-07-v5.17-net-next-net-dsa-qca8k-initial-conversion-to-regmap-heper.patch
diff --git a/target/linux/generic/backport-5.15/758-v5.17-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch b/target/linux/generic/backport-5.15/764-08-v5.17-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/758-v5.17-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch
rename to target/linux/generic/backport-5.15/764-08-v5.17-net-next-net-dsa-qca8k-add-additional-MIB-counter-and-.patch
diff --git a/target/linux/generic/backport-5.15/759-v5.17-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch b/target/linux/generic/backport-5.15/764-09-v5.17-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/759-v5.17-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch
rename to target/linux/generic/backport-5.15/764-09-v5.17-net-next-net-dsa-qca8k-add-support-for-port-fast-aging.patch
diff --git a/target/linux/generic/backport-5.15/760-v5.17-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch b/target/linux/generic/backport-5.15/764-10-v5.17-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/760-v5.17-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch
rename to target/linux/generic/backport-5.15/764-10-v5.17-net-next-net-dsa-qca8k-add-set_ageing_time-support.patch
diff --git a/target/linux/generic/backport-5.15/761-v5.17-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch b/target/linux/generic/backport-5.15/764-11-v5.17-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/761-v5.17-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch
rename to target/linux/generic/backport-5.15/764-11-v5.17-net-next-net-dsa-qca8k-add-support-for-mdb_add-del.patch
diff --git a/target/linux/generic/backport-5.15/762-v5.17-net-next-net-dsa-qca8k-add-support-for-mirror-mode.patch b/target/linux/generic/backport-5.15/764-12-v5.17-net-next-net-dsa-qca8k-add-support-for-mirror-mode.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/762-v5.17-net-next-net-dsa-qca8k-add-support-for-mirror-mode.patch
rename to target/linux/generic/backport-5.15/764-12-v5.17-net-next-net-dsa-qca8k-add-support-for-mirror-mode.patch
diff --git a/target/linux/generic/backport-5.15/763-v5.17-net-next-net-dsa-qca8k-add-LAG-support.patch b/target/linux/generic/backport-5.15/764-13-v5.17-net-next-net-dsa-qca8k-add-LAG-support.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/763-v5.17-net-next-net-dsa-qca8k-add-LAG-support.patch
rename to target/linux/generic/backport-5.15/764-13-v5.17-net-next-net-dsa-qca8k-add-LAG-support.patch
diff --git a/target/linux/generic/backport-5.15/764-v5.17-net-next-net-dsa-qca8k-fix-warning-in-LAG-feature.patch b/target/linux/generic/backport-5.15/764-14-v5.17-net-next-net-dsa-qca8k-fix-warning-in-LAG-feature.patch
similarity index 100%
rename from target/linux/generic/backport-5.15/764-v5.17-net-next-net-dsa-qca8k-fix-warning-in-LAG-feature.patch
rename to target/linux/generic/backport-5.15/764-14-v5.17-net-next-net-dsa-qca8k-fix-warning-in-LAG-feature.patch
diff --git a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
index 3c9d4e72e85..931c589cfa3 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-01-net-ethernet-stmicro-stmmac-move-queue-reset-to-dedi.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue);
  static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue);
  
-@@ -1712,9 +1715,6 @@ static int __init_dma_rx_desc_rings(stru
+@@ -1713,9 +1716,6 @@ static int __init_dma_rx_desc_rings(stru
  			return -ENOMEM;
  	}
  
@@ -37,7 +37,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	/* Setup the chained descriptor addresses */
  	if (priv->mode == STMMAC_CHAIN_MODE) {
  		if (priv->extend_desc)
-@@ -1820,12 +1820,6 @@ static int __init_dma_tx_desc_rings(stru
+@@ -1821,12 +1821,6 @@ static int __init_dma_tx_desc_rings(stru
  		tx_q->tx_skbuff[i] = NULL;
  	}
  
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return 0;
  }
  
-@@ -2694,10 +2688,7 @@ static void stmmac_tx_err(struct stmmac_
+@@ -2695,10 +2689,7 @@ static void stmmac_tx_err(struct stmmac_
  	stmmac_stop_tx_dma(priv, chan);
  	dma_free_tx_skbufs(priv, chan);
  	stmmac_clear_tx_descriptors(priv, chan);
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, chan);
  	stmmac_start_tx_dma(priv, chan);
-@@ -3781,6 +3772,8 @@ static int stmmac_open(struct net_device
+@@ -3783,6 +3774,8 @@ static int stmmac_open(struct net_device
  		}
  	}
  
@@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_clear_tx_descriptors(priv, queue);
  
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
-@@ -7411,6 +7406,25 @@ int stmmac_suspend(struct device *dev)
+@@ -7415,6 +7410,25 @@ int stmmac_suspend(struct device *dev)
  }
  EXPORT_SYMBOL_GPL(stmmac_suspend);
  
@@ -113,7 +113,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  /**
   * stmmac_reset_queues_param - reset queue parameters
   * @priv: device pointer
-@@ -7421,22 +7435,11 @@ static void stmmac_reset_queues_param(st
+@@ -7425,22 +7439,11 @@ static void stmmac_reset_queues_param(st
  	u32 tx_cnt = priv->plat->tx_queues_to_use;
  	u32 queue;
  
diff --git a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
index 8eca92a5c54..8bdeef7a696 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-02-net-ethernet-stmicro-stmmac-first-disable-all-queues.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -3833,8 +3833,6 @@ static int stmmac_release(struct net_dev
+@@ -3835,8 +3835,6 @@ static int stmmac_release(struct net_dev
  	struct stmmac_priv *priv = netdev_priv(dev);
  	u32 chan;
  
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (device_may_wakeup(priv->device))
  		phylink_speed_down(priv->phylink, false);
  	/* Stop and disconnect the PHY */
-@@ -3846,6 +3844,8 @@ static int stmmac_release(struct net_dev
+@@ -3848,6 +3846,8 @@ static int stmmac_release(struct net_dev
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
  		hrtimer_cancel(&priv->tx_queue[chan].txtimer);
  
diff --git a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
index 34b7e1fd8d1..c59a5d1fe17 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-03-net-ethernet-stmicro-stmmac-move-dma-conf-to-dedicat.patch
@@ -189,7 +189,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (tx_q->dirty_tx != tx_q->cur_tx)
  			return -EBUSY; /* still unfinished work */
-@@ -1309,7 +1309,7 @@ static void stmmac_display_rx_rings(stru
+@@ -1310,7 +1310,7 @@ static void stmmac_display_rx_rings(stru
  
  	/* Display RX rings */
  	for (queue = 0; queue < rx_cnt; queue++) {
@@ -198,7 +198,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		pr_info("\tRX Queue %u rings\n", queue);
  
-@@ -1322,7 +1322,7 @@ static void stmmac_display_rx_rings(stru
+@@ -1323,7 +1323,7 @@ static void stmmac_display_rx_rings(stru
  		}
  
  		/* Display RX ring */
@@ -207,7 +207,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  }
-@@ -1336,7 +1336,7 @@ static void stmmac_display_tx_rings(stru
+@@ -1337,7 +1337,7 @@ static void stmmac_display_tx_rings(stru
  
  	/* Display TX rings */
  	for (queue = 0; queue < tx_cnt; queue++) {
@@ -216,7 +216,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		pr_info("\tTX Queue %d rings\n", queue);
  
-@@ -1351,7 +1351,7 @@ static void stmmac_display_tx_rings(stru
+@@ -1352,7 +1352,7 @@ static void stmmac_display_tx_rings(stru
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -225,7 +225,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    tx_q->dma_tx_phy, desc_size);
  	}
  }
-@@ -1392,21 +1392,21 @@ static int stmmac_set_bfsize(int mtu, in
+@@ -1393,21 +1393,21 @@ static int stmmac_set_bfsize(int mtu, in
   */
  static void stmmac_clear_rx_descriptors(struct stmmac_priv *priv, u32 queue)
  {
@@ -253,7 +253,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  /**
-@@ -1418,12 +1418,12 @@ static void stmmac_clear_rx_descriptors(
+@@ -1419,12 +1419,12 @@ static void stmmac_clear_rx_descriptors(
   */
  static void stmmac_clear_tx_descriptors(struct stmmac_priv *priv, u32 queue)
  {
@@ -269,7 +269,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct dma_desc *p;
  
  		if (priv->extend_desc)
-@@ -1471,7 +1471,7 @@ static void stmmac_clear_descriptors(str
+@@ -1472,7 +1472,7 @@ static void stmmac_clear_descriptors(str
  static int stmmac_init_rx_buffers(struct stmmac_priv *priv, struct dma_desc *p,
  				  int i, gfp_t flags, u32 queue)
  {
@@ -278,7 +278,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
  
  	if (!buf->page) {
-@@ -1496,7 +1496,7 @@ static int stmmac_init_rx_buffers(struct
+@@ -1497,7 +1497,7 @@ static int stmmac_init_rx_buffers(struct
  	buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
  
  	stmmac_set_desc_addr(priv, p, buf->addr);
@@ -287,7 +287,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		stmmac_init_desc3(priv, p);
  
  	return 0;
-@@ -1510,7 +1510,7 @@ static int stmmac_init_rx_buffers(struct
+@@ -1511,7 +1511,7 @@ static int stmmac_init_rx_buffers(struct
   */
  static void stmmac_free_rx_buffer(struct stmmac_priv *priv, u32 queue, int i)
  {
@@ -296,7 +296,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
  
  	if (buf->page)
-@@ -1530,7 +1530,7 @@ static void stmmac_free_rx_buffer(struct
+@@ -1531,7 +1531,7 @@ static void stmmac_free_rx_buffer(struct
   */
  static void stmmac_free_tx_buffer(struct stmmac_priv *priv, u32 queue, int i)
  {
@@ -305,7 +305,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (tx_q->tx_skbuff_dma[i].buf &&
  	    tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
-@@ -1575,17 +1575,17 @@ static void dma_free_rx_skbufs(struct st
+@@ -1576,17 +1576,17 @@ static void dma_free_rx_skbufs(struct st
  {
  	int i;
  
@@ -326,7 +326,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct dma_desc *p;
  		int ret;
  
-@@ -1612,10 +1612,10 @@ static int stmmac_alloc_rx_buffers(struc
+@@ -1613,10 +1613,10 @@ static int stmmac_alloc_rx_buffers(struc
   */
  static void dma_free_rx_xskbufs(struct stmmac_priv *priv, u32 queue)
  {
@@ -339,7 +339,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
  
  		if (!buf->xdp)
-@@ -1628,10 +1628,10 @@ static void dma_free_rx_xskbufs(struct s
+@@ -1629,10 +1629,10 @@ static void dma_free_rx_xskbufs(struct s
  
  static int stmmac_alloc_rx_buffers_zc(struct stmmac_priv *priv, u32 queue)
  {
@@ -352,7 +352,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct stmmac_rx_buffer *buf;
  		dma_addr_t dma_addr;
  		struct dma_desc *p;
-@@ -1674,7 +1674,7 @@ static struct xsk_buff_pool *stmmac_get_
+@@ -1675,7 +1675,7 @@ static struct xsk_buff_pool *stmmac_get_
   */
  static int __init_dma_rx_desc_rings(struct stmmac_priv *priv, u32 queue, gfp_t flags)
  {
@@ -361,7 +361,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int ret;
  
  	netif_dbg(priv, probe, priv->dev,
-@@ -1720,11 +1720,11 @@ static int __init_dma_rx_desc_rings(stru
+@@ -1721,11 +1721,11 @@ static int __init_dma_rx_desc_rings(stru
  		if (priv->extend_desc)
  			stmmac_mode_init(priv, rx_q->dma_erx,
  					 rx_q->dma_rx_phy,
@@ -375,7 +375,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	return 0;
-@@ -1751,7 +1751,7 @@ static int init_dma_rx_desc_rings(struct
+@@ -1752,7 +1752,7 @@ static int init_dma_rx_desc_rings(struct
  
  err_init_rx_buffers:
  	while (queue >= 0) {
@@ -384,7 +384,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (rx_q->xsk_pool)
  			dma_free_rx_xskbufs(priv, queue);
-@@ -1780,7 +1780,7 @@ err_init_rx_buffers:
+@@ -1781,7 +1781,7 @@ err_init_rx_buffers:
   */
  static int __init_dma_tx_desc_rings(struct stmmac_priv *priv, u32 queue)
  {
@@ -393,7 +393,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int i;
  
  	netif_dbg(priv, probe, priv->dev,
-@@ -1792,16 +1792,16 @@ static int __init_dma_tx_desc_rings(stru
+@@ -1793,16 +1793,16 @@ static int __init_dma_tx_desc_rings(stru
  		if (priv->extend_desc)
  			stmmac_mode_init(priv, tx_q->dma_etx,
  					 tx_q->dma_tx_phy,
@@ -413,7 +413,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct dma_desc *p;
  
  		if (priv->extend_desc)
-@@ -1871,12 +1871,12 @@ static int init_dma_desc_rings(struct ne
+@@ -1872,12 +1872,12 @@ static int init_dma_desc_rings(struct ne
   */
  static void dma_free_tx_skbufs(struct stmmac_priv *priv, u32 queue)
  {
@@ -428,7 +428,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		stmmac_free_tx_buffer(priv, queue, i);
  
  	if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
-@@ -1906,7 +1906,7 @@ static void stmmac_free_tx_skbufs(struct
+@@ -1907,7 +1907,7 @@ static void stmmac_free_tx_skbufs(struct
   */
  static void __free_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
  {
@@ -437,7 +437,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* Release the DMA RX socket buffers */
  	if (rx_q->xsk_pool)
-@@ -1919,11 +1919,11 @@ static void __free_dma_rx_desc_resources
+@@ -1920,11 +1920,11 @@ static void __free_dma_rx_desc_resources
  
  	/* Free DMA regions of consistent memory previously allocated */
  	if (!priv->extend_desc)
@@ -451,7 +451,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				  sizeof(struct dma_extended_desc),
  				  rx_q->dma_erx, rx_q->dma_rx_phy);
  
-@@ -1952,7 +1952,7 @@ static void free_dma_rx_desc_resources(s
+@@ -1953,7 +1953,7 @@ static void free_dma_rx_desc_resources(s
   */
  static void __free_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
  {
@@ -460,7 +460,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	size_t size;
  	void *addr;
  
-@@ -1970,7 +1970,7 @@ static void __free_dma_tx_desc_resources
+@@ -1971,7 +1971,7 @@ static void __free_dma_tx_desc_resources
  		addr = tx_q->dma_tx;
  	}
  
@@ -469,7 +469,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
  
-@@ -1999,7 +1999,7 @@ static void free_dma_tx_desc_resources(s
+@@ -2000,7 +2000,7 @@ static void free_dma_tx_desc_resources(s
   */
  static int __alloc_dma_rx_desc_resources(struct stmmac_priv *priv, u32 queue)
  {
@@ -478,7 +478,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	bool xdp_prog = stmmac_xdp_is_enabled(priv);
  	struct page_pool_params pp_params = { 0 };
-@@ -2011,8 +2011,8 @@ static int __alloc_dma_rx_desc_resources
+@@ -2012,8 +2012,8 @@ static int __alloc_dma_rx_desc_resources
  	rx_q->priv_data = priv;
  
  	pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
@@ -489,7 +489,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	pp_params.order = ilog2(num_pages);
  	pp_params.nid = dev_to_node(priv->device);
  	pp_params.dev = priv->device;
-@@ -2027,7 +2027,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2028,7 +2028,7 @@ static int __alloc_dma_rx_desc_resources
  		return ret;
  	}
  
@@ -498,7 +498,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				 sizeof(*rx_q->buf_pool),
  				 GFP_KERNEL);
  	if (!rx_q->buf_pool)
-@@ -2035,7 +2035,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2036,7 +2036,7 @@ static int __alloc_dma_rx_desc_resources
  
  	if (priv->extend_desc) {
  		rx_q->dma_erx = dma_alloc_coherent(priv->device,
@@ -507,7 +507,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  						   sizeof(struct dma_extended_desc),
  						   &rx_q->dma_rx_phy,
  						   GFP_KERNEL);
-@@ -2044,7 +2044,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2045,7 +2045,7 @@ static int __alloc_dma_rx_desc_resources
  
  	} else {
  		rx_q->dma_rx = dma_alloc_coherent(priv->device,
@@ -516,7 +516,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  						  sizeof(struct dma_desc),
  						  &rx_q->dma_rx_phy,
  						  GFP_KERNEL);
-@@ -2101,20 +2101,20 @@ err_dma:
+@@ -2102,20 +2102,20 @@ err_dma:
   */
  static int __alloc_dma_tx_desc_resources(struct stmmac_priv *priv, u32 queue)
  {
@@ -540,7 +540,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				  sizeof(struct sk_buff *),
  				  GFP_KERNEL);
  	if (!tx_q->tx_skbuff)
-@@ -2127,7 +2127,7 @@ static int __alloc_dma_tx_desc_resources
+@@ -2128,7 +2128,7 @@ static int __alloc_dma_tx_desc_resources
  	else
  		size = sizeof(struct dma_desc);
  
@@ -549,7 +549,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	addr = dma_alloc_coherent(priv->device, size,
  				  &tx_q->dma_tx_phy, GFP_KERNEL);
-@@ -2371,7 +2371,7 @@ static void stmmac_dma_operation_mode(st
+@@ -2372,7 +2372,7 @@ static void stmmac_dma_operation_mode(st
  
  	/* configure all channels */
  	for (chan = 0; chan < rx_channels_count; chan++) {
@@ -558,7 +558,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		u32 buf_size;
  
  		qmode = priv->plat->rx_queues_cfg[chan].mode_to_use;
-@@ -2386,7 +2386,7 @@ static void stmmac_dma_operation_mode(st
+@@ -2387,7 +2387,7 @@ static void stmmac_dma_operation_mode(st
  					      chan);
  		} else {
  			stmmac_set_dma_bfsize(priv, priv->ioaddr,
@@ -567,7 +567,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					      chan);
  		}
  	}
-@@ -2402,7 +2402,7 @@ static void stmmac_dma_operation_mode(st
+@@ -2403,7 +2403,7 @@ static void stmmac_dma_operation_mode(st
  static bool stmmac_xdp_xmit_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
  {
  	struct netdev_queue *nq = netdev_get_tx_queue(priv->dev, queue);
@@ -576,7 +576,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct xsk_buff_pool *pool = tx_q->xsk_pool;
  	unsigned int entry = tx_q->cur_tx;
  	struct dma_desc *tx_desc = NULL;
-@@ -2477,7 +2477,7 @@ static bool stmmac_xdp_xmit_zc(struct st
+@@ -2478,7 +2478,7 @@ static bool stmmac_xdp_xmit_zc(struct st
  
  		stmmac_enable_dma_transmission(priv, priv->ioaddr);
  
@@ -585,7 +585,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		entry = tx_q->cur_tx;
  	}
  
-@@ -2503,7 +2503,7 @@ static bool stmmac_xdp_xmit_zc(struct st
+@@ -2504,7 +2504,7 @@ static bool stmmac_xdp_xmit_zc(struct st
   */
  static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
  {
@@ -594,7 +594,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int bytes_compl = 0, pkts_compl = 0;
  	unsigned int entry, xmits = 0, count = 0;
  
-@@ -2516,7 +2516,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2517,7 +2517,7 @@ static int stmmac_tx_clean(struct stmmac
  	entry = tx_q->dirty_tx;
  
  	/* Try to clean all TX complete frame in 1 shot */
@@ -603,7 +603,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct xdp_frame *xdpf;
  		struct sk_buff *skb;
  		struct dma_desc *p;
-@@ -2616,7 +2616,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2617,7 +2617,7 @@ static int stmmac_tx_clean(struct stmmac
  
  		stmmac_release_tx_desc(priv, p, priv->mode);
  
@@ -612,7 +612,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	tx_q->dirty_tx = entry;
  
-@@ -2681,7 +2681,7 @@ static int stmmac_tx_clean(struct stmmac
+@@ -2682,7 +2682,7 @@ static int stmmac_tx_clean(struct stmmac
   */
  static void stmmac_tx_err(struct stmmac_priv *priv, u32 chan)
  {
@@ -621,7 +621,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
  
-@@ -2748,8 +2748,8 @@ static int stmmac_napi_check(struct stmm
+@@ -2749,8 +2749,8 @@ static int stmmac_napi_check(struct stmm
  {
  	int status = stmmac_dma_interrupt_status(priv, priv->ioaddr,
  						 &priv->xstats, chan, dir);
@@ -632,7 +632,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[chan];
  	struct napi_struct *rx_napi;
  	struct napi_struct *tx_napi;
-@@ -2925,7 +2925,7 @@ static int stmmac_init_dma_engine(struct
+@@ -2926,7 +2926,7 @@ static int stmmac_init_dma_engine(struct
  
  	/* DMA RX Channel Configuration */
  	for (chan = 0; chan < rx_channels_count; chan++) {
@@ -641,7 +641,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		stmmac_init_rx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  				    rx_q->dma_rx_phy, chan);
-@@ -2939,7 +2939,7 @@ static int stmmac_init_dma_engine(struct
+@@ -2940,7 +2940,7 @@ static int stmmac_init_dma_engine(struct
  
  	/* DMA TX Channel Configuration */
  	for (chan = 0; chan < tx_channels_count; chan++) {
@@ -650,7 +650,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  				    tx_q->dma_tx_phy, chan);
-@@ -2954,7 +2954,7 @@ static int stmmac_init_dma_engine(struct
+@@ -2955,7 +2955,7 @@ static int stmmac_init_dma_engine(struct
  
  static void stmmac_tx_timer_arm(struct stmmac_priv *priv, u32 queue)
  {
@@ -659,7 +659,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	hrtimer_start(&tx_q->txtimer,
  		      STMMAC_COAL_TIMER(priv->tx_coal_timer[queue]),
-@@ -3004,7 +3004,7 @@ static void stmmac_init_coalesce(struct
+@@ -3005,7 +3005,7 @@ static void stmmac_init_coalesce(struct
  	u32 chan;
  
  	for (chan = 0; chan < tx_channel_count; chan++) {
@@ -668,7 +668,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		priv->tx_coal_frames[chan] = STMMAC_TX_FRAMES;
  		priv->tx_coal_timer[chan] = STMMAC_COAL_TX_TIMER;
-@@ -3026,12 +3026,12 @@ static void stmmac_set_rings_length(stru
+@@ -3027,12 +3027,12 @@ static void stmmac_set_rings_length(stru
  	/* set TX ring length */
  	for (chan = 0; chan < tx_channels_count; chan++)
  		stmmac_set_tx_ring_len(priv, priv->ioaddr,
@@ -683,7 +683,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  /**
-@@ -3366,7 +3366,7 @@ static int stmmac_hw_setup(struct net_de
+@@ -3367,7 +3367,7 @@ static int stmmac_hw_setup(struct net_de
  	/* Enable TSO */
  	if (priv->tso) {
  		for (chan = 0; chan < tx_cnt; chan++) {
@@ -692,7 +692,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			/* TSO and TBS cannot co-exist */
  			if (tx_q->tbs & STMMAC_TBS_AVAIL)
-@@ -3388,7 +3388,7 @@ static int stmmac_hw_setup(struct net_de
+@@ -3389,7 +3389,7 @@ static int stmmac_hw_setup(struct net_de
  
  	/* TBS */
  	for (chan = 0; chan < tx_cnt; chan++) {
@@ -701,7 +701,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		int enable = tx_q->tbs & STMMAC_TBS_AVAIL;
  
  		stmmac_enable_tbs(priv, priv->ioaddr, enable, chan);
-@@ -3432,7 +3432,7 @@ static void stmmac_free_irq(struct net_d
+@@ -3433,7 +3433,7 @@ static void stmmac_free_irq(struct net_d
  		for (j = irq_idx - 1; j >= 0; j--) {
  			if (priv->tx_irq[j] > 0) {
  				irq_set_affinity_hint(priv->tx_irq[j], NULL);
@@ -710,7 +710,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			}
  		}
  		irq_idx = priv->plat->rx_queues_to_use;
-@@ -3441,7 +3441,7 @@ static void stmmac_free_irq(struct net_d
+@@ -3442,7 +3442,7 @@ static void stmmac_free_irq(struct net_d
  		for (j = irq_idx - 1; j >= 0; j--) {
  			if (priv->rx_irq[j] > 0) {
  				irq_set_affinity_hint(priv->rx_irq[j], NULL);
@@ -719,7 +719,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			}
  		}
  
-@@ -3574,7 +3574,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3576,7 +3576,7 @@ static int stmmac_request_irq_multi_msi(
  		sprintf(int_name, "%s:%s-%d", dev->name, "rx", i);
  		ret = request_irq(priv->rx_irq[i],
  				  stmmac_msi_intr_rx,
@@ -728,7 +728,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (unlikely(ret < 0)) {
  			netdev_err(priv->dev,
  				   "%s: alloc rx-%d  MSI %d (error: %d)\n",
-@@ -3597,7 +3597,7 @@ static int stmmac_request_irq_multi_msi(
+@@ -3599,7 +3599,7 @@ static int stmmac_request_irq_multi_msi(
  		sprintf(int_name, "%s:%s-%d", dev->name, "tx", i);
  		ret = request_irq(priv->tx_irq[i],
  				  stmmac_msi_intr_tx,
@@ -737,7 +737,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (unlikely(ret < 0)) {
  			netdev_err(priv->dev,
  				   "%s: alloc tx-%d  MSI %d (error: %d)\n",
-@@ -3728,21 +3728,21 @@ static int stmmac_open(struct net_device
+@@ -3730,21 +3730,21 @@ static int stmmac_open(struct net_device
  		bfsize = 0;
  
  	if (bfsize < BUF_SIZE_16KiB)
@@ -766,7 +766,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		int tbs_en = priv->plat->tx_queues_cfg[chan].tbs_en;
  
  		/* Setup per-TXQ tbs flag before TX descriptor alloc */
-@@ -3800,7 +3800,7 @@ irq_error:
+@@ -3802,7 +3802,7 @@ irq_error:
  	phylink_stop(priv->phylink);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -775,7 +775,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	stmmac_hw_teardown(dev);
  init_error:
-@@ -3842,7 +3842,7 @@ static int stmmac_release(struct net_dev
+@@ -3844,7 +3844,7 @@ static int stmmac_release(struct net_dev
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	netif_tx_disable(dev);
  
-@@ -3906,7 +3906,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3908,7 +3908,7 @@ static bool stmmac_vlan_insert(struct st
  		return false;
  
  	stmmac_set_tx_owner(priv, p);
@@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return true;
  }
  
-@@ -3924,7 +3924,7 @@ static bool stmmac_vlan_insert(struct st
+@@ -3926,7 +3926,7 @@ static bool stmmac_vlan_insert(struct st
  static void stmmac_tso_allocator(struct stmmac_priv *priv, dma_addr_t des,
  				 int total_len, bool last_segment, u32 queue)
  {
@@ -802,7 +802,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct dma_desc *desc;
  	u32 buff_size;
  	int tmp_len;
-@@ -3935,7 +3935,7 @@ static void stmmac_tso_allocator(struct
+@@ -3937,7 +3937,7 @@ static void stmmac_tso_allocator(struct
  		dma_addr_t curr_addr;
  
  		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
@@ -811,7 +811,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
  
  		if (tx_q->tbs & STMMAC_TBS_AVAIL)
-@@ -3963,7 +3963,7 @@ static void stmmac_tso_allocator(struct
+@@ -3965,7 +3965,7 @@ static void stmmac_tso_allocator(struct
  
  static void stmmac_flush_tx_descriptors(struct stmmac_priv *priv, int queue)
  {
@@ -820,7 +820,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int desc_size;
  
  	if (likely(priv->extend_desc))
-@@ -4025,7 +4025,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4027,7 +4027,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  	dma_addr_t des;
  	int i;
  
@@ -829,7 +829,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	first_tx = tx_q->cur_tx;
  
  	/* Compute header lengths */
-@@ -4065,7 +4065,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4067,7 +4067,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  		stmmac_set_mss(priv, mss_desc, mss);
  		tx_q->mss = mss;
  		tx_q->cur_tx = STMMAC_GET_ENTRY(tx_q->cur_tx,
@@ -838,7 +838,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[tx_q->cur_tx]);
  	}
  
-@@ -4177,7 +4177,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
+@@ -4179,7 +4179,7 @@ static netdev_tx_t stmmac_tso_xmit(struc
  	 * ndo_start_xmit will fill this descriptor the next time it's
  	 * called and stmmac_tx_clean may clean up to this descriptor.
  	 */
@@ -847,7 +847,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (unlikely(stmmac_tx_avail(priv, queue) <= (MAX_SKB_FRAGS + 1))) {
  		netif_dbg(priv, hw, priv->dev, "%s: stop transmitted packets\n",
-@@ -4265,7 +4265,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4267,7 +4267,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  	int entry, first_tx;
  	dma_addr_t des;
  
@@ -856,7 +856,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	first_tx = tx_q->cur_tx;
  
  	if (priv->tx_path_in_lpi_mode && priv->eee_sw_timer_en)
-@@ -4328,7 +4328,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4330,7 +4330,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  		int len = skb_frag_size(frag);
  		bool last_segment = (i == (nfrags - 1));
  
@@ -865,7 +865,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		WARN_ON(tx_q->tx_skbuff[entry]);
  
  		if (likely(priv->extend_desc))
-@@ -4399,7 +4399,7 @@ static netdev_tx_t stmmac_xmit(struct sk
+@@ -4401,7 +4401,7 @@ static netdev_tx_t stmmac_xmit(struct sk
  	 * ndo_start_xmit will fill this descriptor the next time it's
  	 * called and stmmac_tx_clean may clean up to this descriptor.
  	 */
@@ -874,7 +874,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_q->cur_tx = entry;
  
  	if (netif_msg_pktdata(priv)) {
-@@ -4514,7 +4514,7 @@ static void stmmac_rx_vlan(struct net_de
+@@ -4513,7 +4513,7 @@ static void stmmac_rx_vlan(struct net_de
   */
  static inline void stmmac_rx_refill(struct stmmac_priv *priv, u32 queue)
  {
@@ -883,7 +883,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int entry = rx_q->dirty_rx;
  
-@@ -4564,7 +4564,7 @@ static inline void stmmac_rx_refill(stru
+@@ -4563,7 +4563,7 @@ static inline void stmmac_rx_refill(stru
  		dma_wmb();
  		stmmac_set_rx_owner(priv, p, use_rx_wd);
  
@@ -892,7 +892,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	rx_q->dirty_rx = entry;
  	rx_q->rx_tail_addr = rx_q->dma_rx_phy +
-@@ -4592,12 +4592,12 @@ static unsigned int stmmac_rx_buf1_len(s
+@@ -4591,12 +4591,12 @@ static unsigned int stmmac_rx_buf1_len(s
  
  	/* First descriptor, not last descriptor and not split header */
  	if (status & rx_not_ls)
@@ -907,7 +907,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static unsigned int stmmac_rx_buf2_len(struct stmmac_priv *priv,
-@@ -4613,7 +4613,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4612,7 +4612,7 @@ static unsigned int stmmac_rx_buf2_len(s
  
  	/* Not last descriptor */
  	if (status & rx_not_ls)
@@ -916,7 +916,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	plen = stmmac_get_rx_frame_len(priv, p, coe);
  
-@@ -4624,7 +4624,7 @@ static unsigned int stmmac_rx_buf2_len(s
+@@ -4623,7 +4623,7 @@ static unsigned int stmmac_rx_buf2_len(s
  static int stmmac_xdp_xmit_xdpf(struct stmmac_priv *priv, int queue,
  				struct xdp_frame *xdpf, bool dma_map)
  {
@@ -925,7 +925,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int entry = tx_q->cur_tx;
  	struct dma_desc *tx_desc;
  	dma_addr_t dma_addr;
-@@ -4687,7 +4687,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
+@@ -4686,7 +4686,7 @@ static int stmmac_xdp_xmit_xdpf(struct s
  
  	stmmac_enable_dma_transmission(priv, priv->ioaddr);
  
@@ -934,7 +934,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_q->cur_tx = entry;
  
  	return STMMAC_XDP_TX;
-@@ -4861,7 +4861,7 @@ static void stmmac_dispatch_skb_zc(struc
+@@ -4860,7 +4860,7 @@ static void stmmac_dispatch_skb_zc(struc
  
  static bool stmmac_rx_refill_zc(struct stmmac_priv *priv, u32 queue, u32 budget)
  {
@@ -943,7 +943,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int entry = rx_q->dirty_rx;
  	struct dma_desc *rx_desc = NULL;
  	bool ret = true;
-@@ -4904,7 +4904,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4903,7 +4903,7 @@ static bool stmmac_rx_refill_zc(struct s
  		dma_wmb();
  		stmmac_set_rx_owner(priv, rx_desc, use_rx_wd);
  
@@ -952,7 +952,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	if (rx_desc) {
-@@ -4919,7 +4919,7 @@ static bool stmmac_rx_refill_zc(struct s
+@@ -4918,7 +4918,7 @@ static bool stmmac_rx_refill_zc(struct s
  
  static int stmmac_rx_zc(struct stmmac_priv *priv, int limit, u32 queue)
  {
@@ -961,7 +961,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	unsigned int count = 0, error = 0, len = 0;
  	int dirty = stmmac_rx_dirty(priv, queue);
  	unsigned int next_entry = rx_q->cur_rx;
-@@ -4941,7 +4941,7 @@ static int stmmac_rx_zc(struct stmmac_pr
+@@ -4940,7 +4940,7 @@ static int stmmac_rx_zc(struct stmmac_pr
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -970,7 +970,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  	while (count < limit) {
-@@ -4988,7 +4988,7 @@ read_again:
+@@ -4987,7 +4987,7 @@ read_again:
  
  		/* Prefetch the next RX descriptor */
  		rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
@@ -979,7 +979,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		next_entry = rx_q->cur_rx;
  
  		if (priv->extend_desc)
-@@ -5109,7 +5109,7 @@ read_again:
+@@ -5108,7 +5108,7 @@ read_again:
   */
  static int stmmac_rx(struct stmmac_priv *priv, int limit, u32 queue)
  {
@@ -988,7 +988,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	unsigned int count = 0, error = 0, len = 0;
  	int status = 0, coe = priv->hw->rx_csum;
-@@ -5122,7 +5122,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5121,7 +5121,7 @@ static int stmmac_rx(struct stmmac_priv
  	int buf_sz;
  
  	dma_dir = page_pool_get_dma_dir(rx_q->page_pool);
@@ -997,7 +997,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (netif_msg_rx_status(priv)) {
  		void *rx_head;
-@@ -5136,7 +5136,7 @@ static int stmmac_rx(struct stmmac_priv
+@@ -5135,7 +5135,7 @@ static int stmmac_rx(struct stmmac_priv
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -1006,7 +1006,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				    rx_q->dma_rx_phy, desc_size);
  	}
  	while (count < limit) {
-@@ -5180,7 +5180,7 @@ read_again:
+@@ -5179,7 +5179,7 @@ read_again:
  			break;
  
  		rx_q->cur_rx = STMMAC_GET_ENTRY(rx_q->cur_rx,
@@ -1015,7 +1015,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		next_entry = rx_q->cur_rx;
  
  		if (priv->extend_desc)
-@@ -5314,7 +5314,7 @@ read_again:
+@@ -5313,7 +5313,7 @@ read_again:
  						buf1_len, dma_dir);
  			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
  					buf->page, buf->page_offset, buf1_len,
@@ -1024,7 +1024,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			/* Data payload appended into SKB */
  			page_pool_release_page(rx_q->page_pool, buf->page);
-@@ -5326,7 +5326,7 @@ read_again:
+@@ -5325,7 +5325,7 @@ read_again:
  						buf2_len, dma_dir);
  			skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags,
  					buf->sec_page, 0, buf2_len,
@@ -1210,7 +1210,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (netif_running(dev))
  		ret = stmmac_open(dev);
-@@ -7357,7 +7361,7 @@ int stmmac_suspend(struct device *dev)
+@@ -7360,7 +7364,7 @@ int stmmac_suspend(struct device *dev)
  	stmmac_disable_all_queues(priv);
  
  	for (chan = 0; chan < priv->plat->tx_queues_to_use; chan++)
@@ -1219,7 +1219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->eee_enabled) {
  		priv->tx_path_in_lpi_mode = false;
-@@ -7408,7 +7412,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
+@@ -7412,7 +7416,7 @@ EXPORT_SYMBOL_GPL(stmmac_suspend);
  
  static void stmmac_reset_rx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1228,7 +1228,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	rx_q->cur_rx = 0;
  	rx_q->dirty_rx = 0;
-@@ -7416,7 +7420,7 @@ static void stmmac_reset_rx_queue(struct
+@@ -7420,7 +7424,7 @@ static void stmmac_reset_rx_queue(struct
  
  static void stmmac_reset_tx_queue(struct stmmac_priv *priv, u32 queue)
  {
@@ -1270,7 +1270,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (i >= priv->plat->tx_queues_to_use)
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_tc.c
-@@ -970,13 +970,13 @@ static int tc_setup_etf(struct stmmac_pr
+@@ -971,13 +971,13 @@ static int tc_setup_etf(struct stmmac_pr
  		return -EOPNOTSUPP;
  	if (qopt->queue >= priv->plat->tx_queues_to_use)
  		return -EINVAL;
diff --git a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
index a7ee50ddd02..bdf8b8585e2 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-04-net-ethernet-stmicro-stmmac-generate-stmmac-dma-conf.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -1300,7 +1300,8 @@ static int stmmac_phy_setup(struct stmma
+@@ -1301,7 +1301,8 @@ static int stmmac_phy_setup(struct stmma
  	return 0;
  }
  
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	u32 rx_cnt = priv->plat->rx_queues_to_use;
  	unsigned int desc_size;
-@@ -1309,7 +1310,7 @@ static void stmmac_display_rx_rings(stru
+@@ -1310,7 +1311,7 @@ static void stmmac_display_rx_rings(stru
  
  	/* Display RX rings */
  	for (queue = 0; queue < rx_cnt; queue++) {
@@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		pr_info("\tRX Queue %u rings\n", queue);
  
-@@ -1322,12 +1323,13 @@ static void stmmac_display_rx_rings(stru
+@@ -1323,12 +1324,13 @@ static void stmmac_display_rx_rings(stru
  		}
  
  		/* Display RX ring */
@@ -52,7 +52,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	u32 tx_cnt = priv->plat->tx_queues_to_use;
  	unsigned int desc_size;
-@@ -1336,7 +1338,7 @@ static void stmmac_display_tx_rings(stru
+@@ -1337,7 +1339,7 @@ static void stmmac_display_tx_rings(stru
  
  	/* Display TX rings */
  	for (queue = 0; queue < tx_cnt; queue++) {
@@ -61,7 +61,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		pr_info("\tTX Queue %d rings\n", queue);
  
-@@ -1351,18 +1353,19 @@ static void stmmac_display_tx_rings(stru
+@@ -1352,18 +1354,19 @@ static void stmmac_display_tx_rings(stru
  			desc_size = sizeof(struct dma_desc);
  		}
  
@@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static int stmmac_set_bfsize(int mtu, int bufsize)
-@@ -1386,44 +1389,50 @@ static int stmmac_set_bfsize(int mtu, in
+@@ -1387,44 +1390,50 @@ static int stmmac_set_bfsize(int mtu, in
  /**
   * stmmac_clear_rx_descriptors - clear RX descriptors
   * @priv: driver private structure
@@ -147,7 +147,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct dma_desc *p;
  
  		if (priv->extend_desc)
-@@ -1440,10 +1449,12 @@ static void stmmac_clear_tx_descriptors(
+@@ -1441,10 +1450,12 @@ static void stmmac_clear_tx_descriptors(
  /**
   * stmmac_clear_descriptors - clear descriptors
   * @priv: driver private structure
@@ -161,7 +161,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	u32 rx_queue_cnt = priv->plat->rx_queues_to_use;
  	u32 tx_queue_cnt = priv->plat->tx_queues_to_use;
-@@ -1451,16 +1462,17 @@ static void stmmac_clear_descriptors(str
+@@ -1452,16 +1463,17 @@ static void stmmac_clear_descriptors(str
  
  	/* Clear the RX descriptors */
  	for (queue = 0; queue < rx_queue_cnt; queue++)
@@ -181,7 +181,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
   * @p: descriptor pointer
   * @i: descriptor index
   * @flags: gfp flag
-@@ -1468,10 +1480,12 @@ static void stmmac_clear_descriptors(str
+@@ -1469,10 +1481,12 @@ static void stmmac_clear_descriptors(str
   * Description: this function is called to allocate a receive buffer, perform
   * the DMA mapping and init the descriptor.
   */
@@ -196,7 +196,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
  
  	if (!buf->page) {
-@@ -1496,7 +1510,7 @@ static int stmmac_init_rx_buffers(struct
+@@ -1497,7 +1511,7 @@ static int stmmac_init_rx_buffers(struct
  	buf->addr = page_pool_get_dma_addr(buf->page) + buf->page_offset;
  
  	stmmac_set_desc_addr(priv, p, buf->addr);
@@ -205,7 +205,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		stmmac_init_desc3(priv, p);
  
  	return 0;
-@@ -1505,12 +1519,13 @@ static int stmmac_init_rx_buffers(struct
+@@ -1506,12 +1520,13 @@ static int stmmac_init_rx_buffers(struct
  /**
   * stmmac_free_rx_buffer - free RX dma buffers
   * @priv: private structure
@@ -222,7 +222,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
  
  	if (buf->page)
-@@ -1525,12 +1540,15 @@ static void stmmac_free_rx_buffer(struct
+@@ -1526,12 +1541,15 @@ static void stmmac_free_rx_buffer(struct
  /**
   * stmmac_free_tx_buffer - free RX dma buffers
   * @priv: private structure
@@ -240,7 +240,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (tx_q->tx_skbuff_dma[i].buf &&
  	    tx_q->tx_skbuff_dma[i].buf_type != STMMAC_TXBUF_T_XDP_TX) {
-@@ -1569,23 +1587,28 @@ static void stmmac_free_tx_buffer(struct
+@@ -1570,23 +1588,28 @@ static void stmmac_free_tx_buffer(struct
  /**
   * dma_free_rx_skbufs - free RX dma buffers
   * @priv: private structure
@@ -276,7 +276,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct dma_desc *p;
  		int ret;
  
-@@ -1594,7 +1617,7 @@ static int stmmac_alloc_rx_buffers(struc
+@@ -1595,7 +1618,7 @@ static int stmmac_alloc_rx_buffers(struc
  		else
  			p = rx_q->dma_rx + i;
  
@@ -285,7 +285,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					     queue);
  		if (ret)
  			return ret;
-@@ -1608,14 +1631,17 @@ static int stmmac_alloc_rx_buffers(struc
+@@ -1609,14 +1632,17 @@ static int stmmac_alloc_rx_buffers(struc
  /**
   * dma_free_rx_xskbufs - free RX dma buffers from XSK pool
   * @priv: private structure
@@ -306,7 +306,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct stmmac_rx_buffer *buf = &rx_q->buf_pool[i];
  
  		if (!buf->xdp)
-@@ -1626,12 +1652,14 @@ static void dma_free_rx_xskbufs(struct s
+@@ -1627,12 +1653,14 @@ static void dma_free_rx_xskbufs(struct s
  	}
  }
  
@@ -324,7 +324,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct stmmac_rx_buffer *buf;
  		dma_addr_t dma_addr;
  		struct dma_desc *p;
-@@ -1666,22 +1694,25 @@ static struct xsk_buff_pool *stmmac_get_
+@@ -1667,22 +1695,25 @@ static struct xsk_buff_pool *stmmac_get_
  /**
   * __init_dma_rx_desc_rings - init the RX descriptor ring (per queue)
   * @priv: driver private structure
@@ -353,7 +353,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	xdp_rxq_info_unreg_mem_model(&rx_q->xdp_rxq);
  
-@@ -1708,9 +1739,9 @@ static int __init_dma_rx_desc_rings(stru
+@@ -1709,9 +1740,9 @@ static int __init_dma_rx_desc_rings(stru
  		/* RX XDP ZC buffer pool may not be populated, e.g.
  		 * xdpsock TX-only.
  		 */
@@ -365,7 +365,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (ret < 0)
  			return -ENOMEM;
  	}
-@@ -1720,17 +1751,19 @@ static int __init_dma_rx_desc_rings(stru
+@@ -1721,17 +1752,19 @@ static int __init_dma_rx_desc_rings(stru
  		if (priv->extend_desc)
  			stmmac_mode_init(priv, rx_q->dma_erx,
  					 rx_q->dma_rx_phy,
@@ -388,7 +388,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	struct stmmac_priv *priv = netdev_priv(dev);
  	u32 rx_count = priv->plat->rx_queues_to_use;
-@@ -1742,7 +1775,7 @@ static int init_dma_rx_desc_rings(struct
+@@ -1743,7 +1776,7 @@ static int init_dma_rx_desc_rings(struct
  		  "SKB addresses:\nskb\t\tskb data\tdma data\n");
  
  	for (queue = 0; queue < rx_count; queue++) {
@@ -397,7 +397,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (ret)
  			goto err_init_rx_buffers;
  	}
-@@ -1751,12 +1784,12 @@ static int init_dma_rx_desc_rings(struct
+@@ -1752,12 +1785,12 @@ static int init_dma_rx_desc_rings(struct
  
  err_init_rx_buffers:
  	while (queue >= 0) {
@@ -413,7 +413,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		rx_q->buf_alloc_num = 0;
  		rx_q->xsk_pool = NULL;
-@@ -1773,14 +1806,17 @@ err_init_rx_buffers:
+@@ -1774,14 +1807,17 @@ err_init_rx_buffers:
  /**
   * __init_dma_tx_desc_rings - init the TX descriptor ring (per queue)
   * @priv: driver private structure
@@ -434,7 +434,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int i;
  
  	netif_dbg(priv, probe, priv->dev,
-@@ -1792,16 +1828,16 @@ static int __init_dma_tx_desc_rings(stru
+@@ -1793,16 +1829,16 @@ static int __init_dma_tx_desc_rings(stru
  		if (priv->extend_desc)
  			stmmac_mode_init(priv, tx_q->dma_etx,
  					 tx_q->dma_tx_phy,
@@ -454,7 +454,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct dma_desc *p;
  
  		if (priv->extend_desc)
-@@ -1823,7 +1859,8 @@ static int __init_dma_tx_desc_rings(stru
+@@ -1824,7 +1860,8 @@ static int __init_dma_tx_desc_rings(stru
  	return 0;
  }
  
@@ -464,7 +464,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	struct stmmac_priv *priv = netdev_priv(dev);
  	u32 tx_queue_cnt;
-@@ -1832,7 +1869,7 @@ static int init_dma_tx_desc_rings(struct
+@@ -1833,7 +1870,7 @@ static int init_dma_tx_desc_rings(struct
  	tx_queue_cnt = priv->plat->tx_queues_to_use;
  
  	for (queue = 0; queue < tx_queue_cnt; queue++)
@@ -473,7 +473,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	return 0;
  }
-@@ -1840,26 +1877,29 @@ static int init_dma_tx_desc_rings(struct
+@@ -1841,26 +1878,29 @@ static int init_dma_tx_desc_rings(struct
  /**
   * init_dma_desc_rings - init the RX/TX descriptor rings
   * @dev: net device structure
@@ -508,7 +508,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	return ret;
  }
-@@ -1867,17 +1907,20 @@ static int init_dma_desc_rings(struct ne
+@@ -1868,17 +1908,20 @@ static int init_dma_desc_rings(struct ne
  /**
   * dma_free_tx_skbufs - free TX dma buffers
   * @priv: private structure
@@ -533,7 +533,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (tx_q->xsk_pool && tx_q->xsk_frames_done) {
  		xsk_tx_completed(tx_q->xsk_pool, tx_q->xsk_frames_done);
-@@ -1896,34 +1939,37 @@ static void stmmac_free_tx_skbufs(struct
+@@ -1897,34 +1940,37 @@ static void stmmac_free_tx_skbufs(struct
  	u32 queue;
  
  	for (queue = 0; queue < tx_queue_cnt; queue++)
@@ -578,7 +578,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				  sizeof(struct dma_extended_desc),
  				  rx_q->dma_erx, rx_q->dma_rx_phy);
  
-@@ -1935,29 +1981,33 @@ static void __free_dma_rx_desc_resources
+@@ -1936,29 +1982,33 @@ static void __free_dma_rx_desc_resources
  		page_pool_destroy(rx_q->page_pool);
  }
  
@@ -617,7 +617,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->extend_desc) {
  		size = sizeof(struct dma_extended_desc);
-@@ -1970,7 +2020,7 @@ static void __free_dma_tx_desc_resources
+@@ -1971,7 +2021,7 @@ static void __free_dma_tx_desc_resources
  		addr = tx_q->dma_tx;
  	}
  
@@ -626,7 +626,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	dma_free_coherent(priv->device, size, addr, tx_q->dma_tx_phy);
  
-@@ -1978,28 +2028,32 @@ static void __free_dma_tx_desc_resources
+@@ -1979,28 +2029,32 @@ static void __free_dma_tx_desc_resources
  	kfree(tx_q->tx_skbuff);
  }
  
@@ -663,7 +663,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct stmmac_channel *ch = &priv->channel[queue];
  	bool xdp_prog = stmmac_xdp_is_enabled(priv);
  	struct page_pool_params pp_params = { 0 };
-@@ -2011,8 +2065,8 @@ static int __alloc_dma_rx_desc_resources
+@@ -2012,8 +2066,8 @@ static int __alloc_dma_rx_desc_resources
  	rx_q->priv_data = priv;
  
  	pp_params.flags = PP_FLAG_DMA_MAP | PP_FLAG_DMA_SYNC_DEV;
@@ -674,7 +674,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	pp_params.order = ilog2(num_pages);
  	pp_params.nid = dev_to_node(priv->device);
  	pp_params.dev = priv->device;
-@@ -2027,7 +2081,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2028,7 +2082,7 @@ static int __alloc_dma_rx_desc_resources
  		return ret;
  	}
  
@@ -683,7 +683,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				 sizeof(*rx_q->buf_pool),
  				 GFP_KERNEL);
  	if (!rx_q->buf_pool)
-@@ -2035,7 +2089,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2036,7 +2090,7 @@ static int __alloc_dma_rx_desc_resources
  
  	if (priv->extend_desc) {
  		rx_q->dma_erx = dma_alloc_coherent(priv->device,
@@ -692,7 +692,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  						   sizeof(struct dma_extended_desc),
  						   &rx_q->dma_rx_phy,
  						   GFP_KERNEL);
-@@ -2044,7 +2098,7 @@ static int __alloc_dma_rx_desc_resources
+@@ -2045,7 +2099,7 @@ static int __alloc_dma_rx_desc_resources
  
  	} else {
  		rx_q->dma_rx = dma_alloc_coherent(priv->device,
@@ -701,7 +701,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  						  sizeof(struct dma_desc),
  						  &rx_q->dma_rx_phy,
  						  GFP_KERNEL);
-@@ -2069,7 +2123,8 @@ static int __alloc_dma_rx_desc_resources
+@@ -2070,7 +2124,8 @@ static int __alloc_dma_rx_desc_resources
  	return 0;
  }
  
@@ -711,7 +711,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	u32 rx_count = priv->plat->rx_queues_to_use;
  	u32 queue;
-@@ -2077,7 +2132,7 @@ static int alloc_dma_rx_desc_resources(s
+@@ -2078,7 +2133,7 @@ static int alloc_dma_rx_desc_resources(s
  
  	/* RX queues buffers and DMA */
  	for (queue = 0; queue < rx_count; queue++) {
@@ -720,7 +720,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (ret)
  			goto err_dma;
  	}
-@@ -2085,7 +2140,7 @@ static int alloc_dma_rx_desc_resources(s
+@@ -2086,7 +2141,7 @@ static int alloc_dma_rx_desc_resources(s
  	return 0;
  
  err_dma:
@@ -729,7 +729,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	return ret;
  }
-@@ -2093,28 +2148,31 @@ err_dma:
+@@ -2094,28 +2149,31 @@ err_dma:
  /**
   * __alloc_dma_tx_desc_resources - alloc TX resources (per queue).
   * @priv: private structure
@@ -765,7 +765,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  				  sizeof(struct sk_buff *),
  				  GFP_KERNEL);
  	if (!tx_q->tx_skbuff)
-@@ -2127,7 +2185,7 @@ static int __alloc_dma_tx_desc_resources
+@@ -2128,7 +2186,7 @@ static int __alloc_dma_tx_desc_resources
  	else
  		size = sizeof(struct dma_desc);
  
@@ -774,7 +774,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	addr = dma_alloc_coherent(priv->device, size,
  				  &tx_q->dma_tx_phy, GFP_KERNEL);
-@@ -2144,7 +2202,8 @@ static int __alloc_dma_tx_desc_resources
+@@ -2145,7 +2203,8 @@ static int __alloc_dma_tx_desc_resources
  	return 0;
  }
  
@@ -784,7 +784,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	u32 tx_count = priv->plat->tx_queues_to_use;
  	u32 queue;
-@@ -2152,7 +2211,7 @@ static int alloc_dma_tx_desc_resources(s
+@@ -2153,7 +2212,7 @@ static int alloc_dma_tx_desc_resources(s
  
  	/* TX queues buffers and DMA */
  	for (queue = 0; queue < tx_count; queue++) {
@@ -793,7 +793,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (ret)
  			goto err_dma;
  	}
-@@ -2160,27 +2219,29 @@ static int alloc_dma_tx_desc_resources(s
+@@ -2161,27 +2220,29 @@ static int alloc_dma_tx_desc_resources(s
  	return 0;
  
  err_dma:
@@ -827,7 +827,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	return ret;
  }
-@@ -2188,16 +2249,18 @@ static int alloc_dma_desc_resources(stru
+@@ -2189,16 +2250,18 @@ static int alloc_dma_desc_resources(stru
  /**
   * free_dma_desc_resources - free dma desc resources
   * @priv: private structure
@@ -849,7 +849,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  /**
-@@ -2686,8 +2749,8 @@ static void stmmac_tx_err(struct stmmac_
+@@ -2687,8 +2750,8 @@ static void stmmac_tx_err(struct stmmac_
  	netif_tx_stop_queue(netdev_get_tx_queue(priv->dev, chan));
  
  	stmmac_stop_tx_dma(priv, chan);
@@ -860,7 +860,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	stmmac_reset_tx_queue(priv, chan);
  	stmmac_init_tx_chan(priv, priv->ioaddr, priv->plat->dma_cfg,
  			    tx_q->dma_tx_phy, chan);
-@@ -3684,19 +3747,93 @@ static int stmmac_request_irq(struct net
+@@ -3686,19 +3749,93 @@ static int stmmac_request_irq(struct net
  }
  
  /**
@@ -957,7 +957,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u32 chan;
  	int ret;
  
-@@ -3723,45 +3860,10 @@ static int stmmac_open(struct net_device
+@@ -3725,45 +3862,10 @@ static int stmmac_open(struct net_device
  	memset(&priv->xstats, 0, sizeof(struct stmmac_extra_stats));
  	priv->xstats.threshold = tc;
  
@@ -1005,7 +1005,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	if (priv->plat->serdes_powerup) {
  		ret = priv->plat->serdes_powerup(dev, priv->plat->bsp_priv);
-@@ -3804,14 +3906,28 @@ irq_error:
+@@ -3806,14 +3908,28 @@ irq_error:
  
  	stmmac_hw_teardown(dev);
  init_error:
@@ -1036,7 +1036,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void stmmac_fpe_stop_wq(struct stmmac_priv *priv)
  {
  	set_bit(__FPE_REMOVING, &priv->fpe_task_state);
-@@ -3858,7 +3974,7 @@ static int stmmac_release(struct net_dev
+@@ -3860,7 +3976,7 @@ static int stmmac_release(struct net_dev
  	stmmac_stop_all_dma(priv);
  
  	/* Release and free the Rx/Tx resources */
@@ -1150,7 +1150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  dma_desc_error:
  	return ret;
  }
-@@ -7503,7 +7619,7 @@ int stmmac_resume(struct device *dev)
+@@ -7507,7 +7623,7 @@ int stmmac_resume(struct device *dev)
  	stmmac_reset_queues_param(priv);
  
  	stmmac_free_tx_skbufs(priv);
diff --git a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
index 8fccc716597..2576df45224 100644
--- a/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
+++ b/target/linux/generic/backport-5.15/775-v6.0-05-net-ethernet-stmicro-stmmac-permit-MTU-change-with-i.patch
@@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
 +++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
-@@ -5626,18 +5626,15 @@ static int stmmac_change_mtu(struct net_
+@@ -5625,18 +5625,15 @@ static int stmmac_change_mtu(struct net_
  {
  	struct stmmac_priv *priv = netdev_priv(dev);
  	int txfifosz = priv->plat->tx_fifo_size;
@@ -40,7 +40,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (stmmac_xdp_is_enabled(priv) && new_mtu > ETH_DATA_LEN) {
  		netdev_dbg(priv->dev, "Jumbo frames not supported for XDP\n");
  		return -EINVAL;
-@@ -5649,8 +5646,29 @@ static int stmmac_change_mtu(struct net_
+@@ -5648,8 +5645,29 @@ static int stmmac_change_mtu(struct net_
  	if ((txfifosz < new_mtu) || (new_mtu > BUF_SIZE_16KiB))
  		return -EINVAL;
  
diff --git a/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch b/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
index 7eb097f86d0..7c0a4906957 100644
--- a/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
+++ b/target/linux/generic/backport-5.15/791-v6.2-01-net-phy-Add-driver-for-Motorcomm-yt8521-gigabit-ethernet.patch
@@ -31,7 +31,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  F:	drivers/net/phy/motorcomm.c
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
+@@ -242,7 +242,7 @@ config MOTORCOMM_PHY
  	tristate "Motorcomm PHYs"
  	help
  	  Enables support for Motorcomm network PHYs.
diff --git a/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch b/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch
index da60c63905d..94d09092cfd 100644
--- a/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch
+++ b/target/linux/generic/backport-5.15/791-v6.2-03-net-phy-add-Motorcomm-YT8531S-phy-id.patch
@@ -22,7 +22,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
+@@ -242,7 +242,7 @@ config MOTORCOMM_PHY
  	tristate "Motorcomm PHYs"
  	help
  	  Enables support for Motorcomm network PHYs.
diff --git a/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch b/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch
index 9dce5a8add9..a8b9e3d13b0 100644
--- a/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch
+++ b/target/linux/generic/backport-5.15/791-v6.3-09-net-phy-Add-driver-for-Motorcomm-yt8531-gigabit-ethernet.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -245,7 +245,7 @@ config MOTORCOMM_PHY
+@@ -242,7 +242,7 @@ config MOTORCOMM_PHY
  	tristate "Motorcomm PHYs"
  	help
  	  Enables support for Motorcomm network PHYs.
diff --git a/target/linux/generic/backport-5.15/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch b/target/linux/generic/backport-5.15/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch
new file mode 100644
index 00000000000..010ca9b68aa
--- /dev/null
+++ b/target/linux/generic/backport-5.15/791-v6.6-11-net-phy-motorcomm-Add-pad-drive-strength-cfg-support.patch
@@ -0,0 +1,170 @@
+From 7a561e9351ae7e3fb1f08584d40b49c1e55dde60 Mon Sep 17 00:00:00 2001
+From: Samin Guo <samin.guo@starfivetech.com>
+Date: Thu, 20 Jul 2023 19:15:09 +0800
+Subject: [PATCH] net: phy: motorcomm: Add pad drive strength cfg support
+
+The motorcomm phy (YT8531) supports the ability to adjust the drive
+strength of the rx_clk/rx_data, and the default strength may not be
+suitable for all boards. So add configurable options to better match
+the boards.(e.g. StarFive VisionFive 2)
+
+When we configure the drive strength, we need to read the current
+LDO voltage value to ensure that it is a legal value at that LDO
+voltage.
+
+Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
+Signed-off-by: Samin Guo <samin.guo@starfivetech.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/motorcomm.c | 118 ++++++++++++++++++++++++++++++++++++
+ 1 file changed, 118 insertions(+)
+
+--- a/drivers/net/phy/motorcomm.c
++++ b/drivers/net/phy/motorcomm.c
+@@ -163,6 +163,10 @@
+ 
+ #define YT8521_CHIP_CONFIG_REG			0xA001
+ #define YT8521_CCR_SW_RST			BIT(15)
++#define YT8531_RGMII_LDO_VOL_MASK		GENMASK(5, 4)
++#define YT8531_LDO_VOL_3V3			0x0
++#define YT8531_LDO_VOL_1V8			0x2
++
+ /* 1b0 disable 1.9ns rxc clock delay  *default*
+  * 1b1 enable 1.9ns rxc clock delay
+  */
+@@ -236,6 +240,12 @@
+  */
+ #define YTPHY_WCR_TYPE_PULSE			BIT(0)
+ 
++#define YTPHY_PAD_DRIVE_STRENGTH_REG		0xA010
++#define YT8531_RGMII_RXC_DS_MASK		GENMASK(15, 13)
++#define YT8531_RGMII_RXD_DS_HI_MASK		BIT(12)		/* Bit 2 of rxd_ds */
++#define YT8531_RGMII_RXD_DS_LOW_MASK		GENMASK(5, 4)	/* Bit 1/0 of rxd_ds */
++#define YT8531_RGMII_RX_DS_DEFAULT		0x3
++
+ #define YTPHY_SYNCE_CFG_REG			0xA012
+ #define YT8521_SCR_SYNCE_ENABLE			BIT(5)
+ /* 1b0 output 25m clock
+@@ -835,6 +845,110 @@ static int ytphy_rgmii_clk_delay_config_
+ }
+ 
+ /**
++ * struct ytphy_ldo_vol_map - map a current value to a register value
++ * @vol: ldo voltage
++ * @ds:  value in the register
++ * @cur: value in device configuration
++ */
++struct ytphy_ldo_vol_map {
++	u32 vol;
++	u32 ds;
++	u32 cur;
++};
++
++static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = {
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970},
++	{.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740},
++	{.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140},
++};
++
++static u32 yt8531_get_ldo_vol(struct phy_device *phydev)
++{
++	u32 val;
++
++	val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG);
++	val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val);
++
++	return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8;
++}
++
++static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur)
++{
++	u32 vol;
++	int i;
++
++	vol = yt8531_get_ldo_vol(phydev);
++	for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) {
++		if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur)
++			return yt8531_ldo_vol[i].ds;
++	}
++
++	return -EINVAL;
++}
++
++static int yt8531_set_ds(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	u32 ds_field_low, ds_field_hi, val;
++	int ret, ds;
++
++	/* set rgmii rx clk driver strength */
++	if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) {
++		ds = yt8531_get_ds_map(phydev, val);
++		if (ds < 0)
++			return dev_err_probe(&phydev->mdio.dev, ds,
++					     "No matching current value was found.\n");
++	} else {
++		ds = YT8531_RGMII_RX_DS_DEFAULT;
++	}
++
++	ret = ytphy_modify_ext_with_lock(phydev,
++					 YTPHY_PAD_DRIVE_STRENGTH_REG,
++					 YT8531_RGMII_RXC_DS_MASK,
++					 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds));
++	if (ret < 0)
++		return ret;
++
++	/* set rgmii rx data driver strength */
++	if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) {
++		ds = yt8531_get_ds_map(phydev, val);
++		if (ds < 0)
++			return dev_err_probe(&phydev->mdio.dev, ds,
++					     "No matching current value was found.\n");
++	} else {
++		ds = YT8531_RGMII_RX_DS_DEFAULT;
++	}
++
++	ds_field_hi = FIELD_GET(BIT(2), ds);
++	ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi);
++
++	ds_field_low = FIELD_GET(GENMASK(1, 0), ds);
++	ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low);
++
++	ret = ytphy_modify_ext_with_lock(phydev,
++					 YTPHY_PAD_DRIVE_STRENGTH_REG,
++					 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK,
++					 ds_field_low | ds_field_hi);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++/**
+  * yt8521_probe() - read chip config then set suitable polling_mode
+  * @phydev: a pointer to a &struct phy_device
+  *
+@@ -1518,6 +1632,10 @@ static int yt8531_config_init(struct phy
+ 			return ret;
+ 	}
+ 
++	ret = yt8531_set_ds(phydev);
++	if (ret < 0)
++		return ret;
++
+ 	return 0;
+ }
+ 
diff --git a/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch b/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch
index cda77e3e2d8..a0cb367ba7d 100644
--- a/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch
+++ b/target/linux/generic/backport-5.15/792-01-v6.0-net-phylink-disable-PCS-polling-over-major-configura.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -756,6 +756,18 @@ static void phylink_resolve_flow(struct
+@@ -759,6 +759,18 @@ static void phylink_resolve_flow(struct
  	}
  }
  
@@ -36,7 +36,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void phylink_mac_config(struct phylink *pl,
  			       const struct phylink_link_state *state)
  {
-@@ -787,6 +799,7 @@ static void phylink_major_config(struct
+@@ -790,6 +802,7 @@ static void phylink_major_config(struct
  				  const struct phylink_link_state *state)
  {
  	struct phylink_pcs *pcs = NULL;
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int err;
  
  	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
-@@ -799,8 +812,12 @@ static void phylink_major_config(struct
+@@ -802,8 +815,12 @@ static void phylink_major_config(struct
  				    pcs);
  			return;
  		}
@@ -57,7 +57,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (pl->mac_ops->mac_prepare) {
  		err = pl->mac_ops->mac_prepare(pl->config, pl->cur_link_an_mode,
  					       state->interface);
-@@ -814,8 +831,10 @@ static void phylink_major_config(struct
+@@ -817,8 +834,10 @@ static void phylink_major_config(struct
  	/* If we have a new PCS, switch to the new PCS after preparing the MAC
  	 * for the change.
  	 */
@@ -70,7 +70,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	phylink_mac_config(pl, state);
  
-@@ -841,6 +860,8 @@ static void phylink_major_config(struct
+@@ -844,6 +863,8 @@ static void phylink_major_config(struct
  			phylink_err(pl, "mac_finish failed: %pe\n",
  				    ERR_PTR(err));
  	}
diff --git a/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch b/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch
index f1f359bad7a..fec2fddfda8 100644
--- a/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch
+++ b/target/linux/generic/backport-5.15/792-02-v6.0-net-phylink-fix-NULL-pl-pcs-dereference-during-phyli.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -764,7 +764,7 @@ static void phylink_pcs_poll_stop(struct
+@@ -767,7 +767,7 @@ static void phylink_pcs_poll_stop(struct
  
  static void phylink_pcs_poll_start(struct phylink *pl)
  {
diff --git a/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch b/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
index c8176c90f52..71b09cbe759 100644
--- a/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
+++ b/target/linux/generic/backport-5.15/792-03-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	bool mac_link_dropped;
  	bool using_mac_select_pcs;
-@@ -795,6 +800,22 @@ static void phylink_mac_pcs_an_restart(s
+@@ -798,6 +803,22 @@ static void phylink_mac_pcs_an_restart(s
  	}
  }
  
@@ -58,7 +58,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static void phylink_major_config(struct phylink *pl, bool restart,
  				  const struct phylink_link_state *state)
  {
-@@ -832,12 +853,16 @@ static void phylink_major_config(struct
+@@ -835,12 +856,16 @@ static void phylink_major_config(struct
  	 * for the change.
  	 */
  	if (pcs_changed) {
@@ -75,7 +75,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (pl->pcs_ops) {
  		err = pl->pcs_ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
  					      state->interface,
-@@ -1261,6 +1286,7 @@ struct phylink *phylink_create(struct ph
+@@ -1264,6 +1289,7 @@ struct phylink *phylink_create(struct ph
  	pl->link_config.speed = SPEED_UNKNOWN;
  	pl->link_config.duplex = DUPLEX_UNKNOWN;
  	pl->link_config.an_enabled = true;
@@ -83,7 +83,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	pl->mac_ops = mac_ops;
  	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
  	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
-@@ -1652,6 +1678,8 @@ void phylink_start(struct phylink *pl)
+@@ -1655,6 +1681,8 @@ void phylink_start(struct phylink *pl)
  	if (pl->netdev)
  		netif_carrier_off(pl->netdev);
  
@@ -92,7 +92,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* Apply the link configuration to the MAC when starting. This allows
  	 * a fixed-link to start with the correct parameters, and also
  	 * ensures that we set the appropriate advertisement for Serdes links.
-@@ -1662,6 +1690,8 @@ void phylink_start(struct phylink *pl)
+@@ -1665,6 +1693,8 @@ void phylink_start(struct phylink *pl)
  	 */
  	phylink_mac_initial_config(pl, true);
  
@@ -101,7 +101,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	clear_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
  	phylink_run_resolve(pl);
  
-@@ -1681,16 +1711,9 @@ void phylink_start(struct phylink *pl)
+@@ -1684,16 +1714,9 @@ void phylink_start(struct phylink *pl)
  			poll = true;
  	}
  
@@ -120,7 +120,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (poll)
  		mod_timer(&pl->link_poll, jiffies + HZ);
  	if (pl->phydev)
-@@ -1727,6 +1750,10 @@ void phylink_stop(struct phylink *pl)
+@@ -1730,6 +1753,10 @@ void phylink_stop(struct phylink *pl)
  	}
  
  	phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED);
diff --git a/target/linux/generic/backport-5.15/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch b/target/linux/generic/backport-5.15/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch
index 582e1ce2efd..b0860db2669 100644
--- a/target/linux/generic/backport-5.15/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch
+++ b/target/linux/generic/backport-5.15/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch
@@ -46,7 +46,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -1642,7 +1642,6 @@ struct net_device_ops {
+@@ -1643,7 +1643,6 @@ struct net_device_ops {
   * @IFF_FAILOVER: device is a failover master device
   * @IFF_FAILOVER_SLAVE: device is lower dev of a failover master device
   * @IFF_L3MDEV_RX_HANDLER: only invoke the rx handler of L3 master device
@@ -54,7 +54,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @IFF_TX_SKB_NO_LINEAR: device/driver is capable of xmitting frames with
   *	skb_headlen(skb) == 0 (data starts from frag0)
   */
-@@ -1677,7 +1676,7 @@ enum netdev_priv_flags {
+@@ -1678,7 +1677,7 @@ enum netdev_priv_flags {
  	IFF_FAILOVER			= 1<<27,
  	IFF_FAILOVER_SLAVE		= 1<<28,
  	IFF_L3MDEV_RX_HANDLER		= 1<<29,
@@ -63,7 +63,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	IFF_TX_SKB_NO_LINEAR		= BIT_ULL(31),
  };
  
-@@ -1711,7 +1710,6 @@ enum netdev_priv_flags {
+@@ -1712,7 +1711,6 @@ enum netdev_priv_flags {
  #define IFF_FAILOVER			IFF_FAILOVER
  #define IFF_FAILOVER_SLAVE		IFF_FAILOVER_SLAVE
  #define IFF_L3MDEV_RX_HANDLER		IFF_L3MDEV_RX_HANDLER
diff --git a/target/linux/generic/backport-5.15/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch b/target/linux/generic/backport-5.15/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch
deleted file mode 100644
index 38ddcb5714c..00000000000
--- a/target/linux/generic/backport-5.15/795-v6.3-01-r8152-add-USB-device-driver-for-config-selection.patch
+++ /dev/null
@@ -1,229 +0,0 @@
-From ec51fbd1b8a2bca2948dede99c14ec63dc57ff6b Mon Sep 17 00:00:00 2001
-From: Bjørn Mork <bjorn@mork.no>
-Date: Fri, 6 Jan 2023 17:07:38 +0100
-Subject: [PATCH] r8152: add USB device driver for config selection
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Subclassing the generic USB device driver to override the
-default configuration selection regardless of matching interface
-drivers.
-
-The r815x family devices expose a vendor specific function which
-the r8152 interface driver wants to handle.  This is the preferred
-device mode. Additionally one or more USB class functions are
-usually supported for hosts lacking a vendor specific driver. The
-choice is USB configuration based, with one alternate function per
-configuration.
-
-Example device with both NCM and ECM alternate cfgs:
-
-T:  Bus=02 Lev=01 Prnt=01 Port=00 Cnt=01 Dev#=  4 Spd=5000 MxCh= 0
-D:  Ver= 3.20 Cls=00(>ifc ) Sub=00 Prot=00 MxPS= 9 #Cfgs=  3
-P:  Vendor=0bda ProdID=8156 Rev=31.00
-S:  Manufacturer=Realtek
-S:  Product=USB 10/100/1G/2.5G LAN
-S:  SerialNumber=001000001
-C:* #Ifs= 1 Cfg#= 1 Atr=a0 MxPwr=256mA
-I:* If#= 0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=00 Driver=r8152
-E:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
-E:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
-E:  Ad=83(I) Atr=03(Int.) MxPS=   2 Ivl=128ms
-C:  #Ifs= 2 Cfg#= 2 Atr=a0 MxPwr=256mA
-I:  If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=0d Prot=00 Driver=
-E:  Ad=83(I) Atr=03(Int.) MxPS=  16 Ivl=128ms
-I:  If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=01 Driver=
-I:  If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=01 Driver=
-E:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
-E:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
-C:  #Ifs= 2 Cfg#= 3 Atr=a0 MxPwr=256mA
-I:  If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=
-E:  Ad=83(I) Atr=03(Int.) MxPS=  16 Ivl=128ms
-I:  If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=
-I:  If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=
-E:  Ad=81(I) Atr=02(Bulk) MxPS=1024 Ivl=0ms
-E:  Ad=02(O) Atr=02(Bulk) MxPS=1024 Ivl=0ms
-
-A problem with this is that Linux will prefer class functions over
-vendor specific functions. Using the above example, Linux defaults
-to cfg #2, running the device in a sub-optimal NCM mode.
-
-Previously we've attempted to work around the problem by
-blacklisting the devices in the ECM class driver "cdc_ether", and
-matching on the ECM class function in the vendor specific interface
-driver. The latter has been used to switch back to the vendor
-specific configuration when the driver is probed for a class
-function.
-
-This workaround has several issues;
-- class driver blacklists is additional maintanence cruft in an
-  unrelated driver
-- class driver blacklists prevents users from optionally running
-  the devices in class mode
-- each device needs double match entries in the vendor driver
-- the initial probing as a class function slows down device
-  discovery
-
-Now these issues have become even worse with the introduction of
-firmware supporting both NCM and ECM, where NCM ends up as the
-default mode in Linux. To use the same workaround, we now have
-to blacklist the devices in to two different class drivers and
-add yet another match entry to the vendor specific driver.
-
-This patch implements an alternative workaround strategy -
-independent of the interface drivers.  It avoids adding a
-blacklist to the cdc_ncm driver and will let us remove the
-existing blacklist from the cdc_ether driver.
-
-As an additional bonus, removing the blacklists allow users to
-select one of the other device modes if wanted.
-
-Signed-off-by: Bjørn Mork <bjorn@mork.no>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/usb/r8152.c | 113 ++++++++++++++++++++++++++++------------
- 1 file changed, 81 insertions(+), 32 deletions(-)
-
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -9625,6 +9625,9 @@ static int rtl8152_probe(struct usb_inte
- 	if (version == RTL_VER_UNKNOWN)
- 		return -ENODEV;
- 
-+	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
-+		return -ENODEV;
-+
- 	if (!rtl_vendor_mode(intf))
- 		return -ENODEV;
- 
-@@ -9834,43 +9837,35 @@ static void rtl8152_disconnect(struct us
- 	}
- }
- 
--#define REALTEK_USB_DEVICE(vend, prod)	{ \
--	USB_DEVICE_INTERFACE_CLASS(vend, prod, USB_CLASS_VENDOR_SPEC), \
--}, \
--{ \
--	USB_DEVICE_AND_INTERFACE_INFO(vend, prod, USB_CLASS_COMM, \
--			USB_CDC_SUBCLASS_ETHERNET, USB_CDC_PROTO_NONE), \
--}
- 
- /* table of devices that work with this driver */
- static const struct usb_device_id rtl8152_table[] = {
- 	/* Realtek */
--	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050),
--	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053),
--	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152),
--	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153),
--	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155),
--	REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156),
-+	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) },
-+	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) },
-+	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) },
-+	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) },
-+	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) },
-+	{ USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) },
- 
- 	/* Microsoft */
--	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab),
--	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6),
--	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927),
--	REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e),
--	REALTEK_USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x304f),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3054),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3062),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3069),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x3082),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7205),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x720c),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x7214),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0x721e),
--	REALTEK_USB_DEVICE(VENDOR_ID_LENOVO,  0xa387),
--	REALTEK_USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041),
--	REALTEK_USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff),
--	REALTEK_USB_DEVICE(VENDOR_ID_TPLINK,  0x0601),
-+	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) },
-+	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) },
-+	{ USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) },
-+	{ USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x304f) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3054) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3062) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3069) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x3082) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7205) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x720c) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x7214) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0x721e) },
-+	{ USB_DEVICE(VENDOR_ID_LENOVO,  0xa387) },
-+	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
-+	{ USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff) },
-+	{ USB_DEVICE(VENDOR_ID_TPLINK,  0x0601) },
- 	{}
- };
- 
-@@ -9890,7 +9885,61 @@ static struct usb_driver rtl8152_driver
- 	.disable_hub_initiated_lpm = 1,
- };
- 
--module_usb_driver(rtl8152_driver);
-+static int rtl8152_cfgselector_probe(struct usb_device *udev)
-+{
-+	struct usb_host_config *c;
-+	int i, num_configs;
-+
-+	/* The vendor mode is not always config #1, so to find it out. */
-+	c = udev->config;
-+	num_configs = udev->descriptor.bNumConfigurations;
-+	for (i = 0; i < num_configs; (i++, c++)) {
-+		struct usb_interface_descriptor	*desc = NULL;
-+
-+		if (!c->desc.bNumInterfaces)
-+			continue;
-+		desc = &c->intf_cache[0]->altsetting->desc;
-+		if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC)
-+			break;
-+	}
-+
-+	if (i == num_configs)
-+		return -ENODEV;
-+
-+	if (usb_set_configuration(udev, c->desc.bConfigurationValue)) {
-+		dev_err(&udev->dev, "Failed to set configuration %d\n",
-+			c->desc.bConfigurationValue);
-+		return -ENODEV;
-+	}
-+
-+	return 0;
-+}
-+
-+static struct usb_device_driver rtl8152_cfgselector_driver = {
-+	.name =		MODULENAME "-cfgselector",
-+	.probe =	rtl8152_cfgselector_probe,
-+	.id_table =	rtl8152_table,
-+	.generic_subclass = 1,
-+};
-+
-+static int __init rtl8152_driver_init(void)
-+{
-+	int ret;
-+
-+	ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE);
-+	if (ret)
-+		return ret;
-+	return usb_register(&rtl8152_driver);
-+}
-+
-+static void __exit rtl8152_driver_exit(void)
-+{
-+	usb_deregister(&rtl8152_driver);
-+	usb_deregister_device_driver(&rtl8152_cfgselector_driver);
-+}
-+
-+module_init(rtl8152_driver_init);
-+module_exit(rtl8152_driver_exit);
- 
- MODULE_AUTHOR(DRIVER_AUTHOR);
- MODULE_DESCRIPTION(DRIVER_DESC);
diff --git a/target/linux/generic/backport-5.15/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch b/target/linux/generic/backport-5.15/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch
deleted file mode 100644
index 8bbf0be802b..00000000000
--- a/target/linux/generic/backport-5.15/795-v6.3-03-r8152-avoid-to-change-cfg-for-all-devices.patch
+++ /dev/null
@@ -1,64 +0,0 @@
-From 0d4cda805a183bbe523f2407edb5c14ade50b841 Mon Sep 17 00:00:00 2001
-From: Hayes Wang <hayeswang@realtek.com>
-Date: Tue, 17 Jan 2023 11:03:44 +0800
-Subject: [PATCH] r8152: avoid to change cfg for all devices
-
-The rtl8152_cfgselector_probe() should set the USB configuration to the
-vendor mode only for the devices which the driver (r8152) supports.
-Otherwise, no driver would be used for such devices.
-
-Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection")
-Signed-off-by: Hayes Wang <hayeswang@realtek.com>
-Reviewed-by: Simon Horman <simon.horman@corigine.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/usb/r8152.c | 20 +++++++++++++++++---
- 1 file changed, 17 insertions(+), 3 deletions(-)
-
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -9531,9 +9531,8 @@ static int rtl_fw_init(struct r8152 *tp)
- 	return 0;
- }
- 
--u8 rtl8152_get_version(struct usb_interface *intf)
-+static u8 __rtl_get_hw_ver(struct usb_device *udev)
- {
--	struct usb_device *udev = interface_to_usbdev(intf);
- 	u32 ocp_data = 0;
- 	__le32 *tmp;
- 	u8 version;
-@@ -9603,10 +9602,19 @@ u8 rtl8152_get_version(struct usb_interf
- 		break;
- 	default:
- 		version = RTL_VER_UNKNOWN;
--		dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
-+		dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data);
- 		break;
- 	}
- 
-+	return version;
-+}
-+
-+u8 rtl8152_get_version(struct usb_interface *intf)
-+{
-+	u8 version;
-+
-+	version = __rtl_get_hw_ver(interface_to_usbdev(intf));
-+
- 	dev_dbg(&intf->dev, "Detected version 0x%04x\n", version);
- 
- 	return version;
-@@ -9890,6 +9898,12 @@ static int rtl8152_cfgselector_probe(str
- 	struct usb_host_config *c;
- 	int i, num_configs;
- 
-+	/* Switch the device to vendor mode, if and only if the vendor mode
-+	 * driver supports it.
-+	 */
-+	if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN)
-+		return 0;
-+
- 	/* The vendor mode is not always config #1, so to find it out. */
- 	c = udev->config;
- 	num_configs = udev->descriptor.bNumConfigurations;
diff --git a/target/linux/generic/backport-5.15/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch b/target/linux/generic/backport-5.15/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch
deleted file mode 100644
index c9bd0df202f..00000000000
--- a/target/linux/generic/backport-5.15/795-v6.3-04-r8152-remove-rtl_vendor_mode-function.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From 95a4c1d617b92cdc4522297741b56e8f6cd01a1e Mon Sep 17 00:00:00 2001
-From: Hayes Wang <hayeswang@realtek.com>
-Date: Thu, 19 Jan 2023 15:40:42 +0800
-Subject: [PATCH] r8152: remove rtl_vendor_mode function
-
-After commit ec51fbd1b8a2 ("r8152: add USB device driver for
-config selection"), the code about changing USB configuration
-in rtl_vendor_mode() wouldn't be run anymore. Therefore, the
-function could be removed.
-
-Signed-off-by: Hayes Wang <hayeswang@realtek.com>
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/usb/r8152.c | 39 +--------------------------------------
- 1 file changed, 1 insertion(+), 38 deletions(-)
-
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -8267,43 +8267,6 @@ static bool rtl_check_vendor_ok(struct u
- 	return true;
- }
- 
--static bool rtl_vendor_mode(struct usb_interface *intf)
--{
--	struct usb_host_interface *alt = intf->cur_altsetting;
--	struct usb_device *udev;
--	struct usb_host_config *c;
--	int i, num_configs;
--
--	if (alt->desc.bInterfaceClass == USB_CLASS_VENDOR_SPEC)
--		return rtl_check_vendor_ok(intf);
--
--	/* The vendor mode is not always config #1, so to find it out. */
--	udev = interface_to_usbdev(intf);
--	c = udev->config;
--	num_configs = udev->descriptor.bNumConfigurations;
--	if (num_configs < 2)
--		return false;
--
--	for (i = 0; i < num_configs; (i++, c++)) {
--		struct usb_interface_descriptor	*desc = NULL;
--
--		if (c->desc.bNumInterfaces > 0)
--			desc = &c->intf_cache[0]->altsetting->desc;
--		else
--			continue;
--
--		if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) {
--			usb_driver_set_configuration(udev, c->desc.bConfigurationValue);
--			break;
--		}
--	}
--
--	if (i == num_configs)
--		dev_err(&intf->dev, "Unexpected Device\n");
--
--	return false;
--}
--
- static int rtl8152_pre_reset(struct usb_interface *intf)
- {
- 	struct r8152 *tp = usb_get_intfdata(intf);
-@@ -9636,7 +9599,7 @@ static int rtl8152_probe(struct usb_inte
- 	if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC)
- 		return -ENODEV;
- 
--	if (!rtl_vendor_mode(intf))
-+	if (!rtl_check_vendor_ok(intf))
- 		return -ENODEV;
- 
- 	usb_reset_device(udev);
diff --git a/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch b/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch
index 7d1053aea5a..482c6c6f133 100644
--- a/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch
+++ b/target/linux/generic/backport-5.15/795-v6.3-05-r8152-reduce-the-control-transfer-of-rtl8152_get_ver.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/usb/r8152.c
 +++ b/drivers/net/usb/r8152.c
-@@ -9588,20 +9588,21 @@ static int rtl8152_probe(struct usb_inte
+@@ -9602,20 +9602,21 @@ static int rtl8152_probe(struct usb_inte
  			 const struct usb_device_id *id)
  {
  	struct usb_device *udev = interface_to_usbdev(intf);
diff --git a/target/linux/generic/backport-5.15/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch b/target/linux/generic/backport-5.15/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch
deleted file mode 100644
index df881e26083..00000000000
--- a/target/linux/generic/backport-5.15/795-v6.4-07-r8152-fix-the-autosuspend-doesn-t-work.patch
+++ /dev/null
@@ -1,24 +0,0 @@
-From 0fbd79c01a9a657348f7032df70c57a406468c86 Mon Sep 17 00:00:00 2001
-From: Hayes Wang <hayeswang@realtek.com>
-Date: Tue, 2 May 2023 11:36:27 +0800
-Subject: [PATCH] r8152: fix the autosuspend doesn't work
-
-Set supports_autosuspend = 1 for the rtl8152_cfgselector_driver.
-
-Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection")
-Signed-off-by: Hayes Wang <hayeswang@realtek.com>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/usb/r8152.c | 1 +
- 1 file changed, 1 insertion(+)
-
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -9898,6 +9898,7 @@ static struct usb_device_driver rtl8152_
- 	.probe =	rtl8152_cfgselector_probe,
- 	.id_table =	rtl8152_table,
- 	.generic_subclass = 1,
-+	.supports_autosuspend = 1,
- };
- 
- static int __init rtl8152_driver_init(void)
diff --git a/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch b/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch
index cfc31daf126..6c7efd7f2bc 100644
--- a/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch
+++ b/target/linux/generic/backport-5.15/795-v6.6-09-r8152-set-bp-in-bulk.patch
@@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/usb/r8152.c
 +++ b/drivers/net/usb/r8152.c
-@@ -3977,29 +3977,10 @@ static void rtl_reset_bmu(struct r8152 *
+@@ -3983,29 +3983,10 @@ static void rtl_reset_bmu(struct r8152 *
  /* Clear the bp to stop the firmware before loading a new one */
  static void rtl_clear_bp(struct r8152 *tp, u16 type)
  {
@@ -48,7 +48,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	case RTL_VER_08:
  	case RTL_VER_09:
  	case RTL_VER_10:
-@@ -4007,32 +3988,31 @@ static void rtl_clear_bp(struct r8152 *t
+@@ -4013,32 +3994,31 @@ static void rtl_clear_bp(struct r8152 *t
  	case RTL_VER_12:
  	case RTL_VER_13:
  	case RTL_VER_15:
@@ -100,7 +100,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* wait 3 ms to make sure the firmware is stopped */
  	usleep_range(3000, 6000);
-@@ -5009,10 +4989,9 @@ static void rtl8152_fw_phy_nc_apply(stru
+@@ -5015,10 +4995,9 @@ static void rtl8152_fw_phy_nc_apply(stru
  
  static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac)
  {
@@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	switch (__le32_to_cpu(mac->blk_hdr.type)) {
  	case RTL_FW_PLA:
-@@ -5054,12 +5033,8 @@ static void rtl8152_fw_mac_apply(struct
+@@ -5060,12 +5039,8 @@ static void rtl8152_fw_mac_apply(struct
  	ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr),
  		       __le16_to_cpu(mac->bp_ba_value));
  
diff --git a/target/linux/generic/backport-5.15/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch b/target/linux/generic/backport-5.15/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch
deleted file mode 100644
index 4d1b177ff20..00000000000
--- a/target/linux/generic/backport-5.15/795-v6.6-11-r8152-add-vendor-device-ID-pair-for-D-Link-DUB-E250.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From 72f93a3136ee18fd59fa6579f84c07e93424681e Mon Sep 17 00:00:00 2001
-From: Antonio Napolitano <anton@polit.no>
-Date: Sat, 26 Aug 2023 01:05:50 +0200
-Subject: [PATCH] r8152: add vendor/device ID pair for D-Link DUB-E250
-
-The D-Link DUB-E250 is an RTL8156 based 2.5G Ethernet controller.
-
-Add the vendor and product ID values to the driver. This makes Ethernet
-work with the adapter.
-
-Signed-off-by: Antonio Napolitano <anton@polit.no>
-Link: https://lore.kernel.org/r/CV200KJEEUPC.WPKAHXCQJ05I@mercurius
-Signed-off-by: Jakub Kicinski <kuba@kernel.org>
----
- drivers/net/usb/r8152.c   | 1 +
- include/linux/usb/r8152.h | 1 +
- 2 files changed, 2 insertions(+)
-
-
---- a/include/linux/usb/r8152.h
-+++ b/include/linux/usb/r8152.h
-@@ -29,6 +29,7 @@
- #define VENDOR_ID_LINKSYS		0x13b1
- #define VENDOR_ID_NVIDIA		0x0955
- #define VENDOR_ID_TPLINK		0x2357
-+#define VENDOR_ID_DLINK			0x2001
- 
- #if IS_REACHABLE(CONFIG_USB_RTL8152)
- extern u8 rtl8152_get_version(struct usb_interface *intf);
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -9820,6 +9820,7 @@ static const struct usb_device_id rtl815
- 	{ USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) },
- 	{ USB_DEVICE(VENDOR_ID_NVIDIA,  0x09ff) },
- 	{ USB_DEVICE(VENDOR_ID_TPLINK,  0x0601) },
-+	{ USB_DEVICE(VENDOR_ID_DLINK,   0xb301) },
- 	{}
- };
- 
diff --git a/target/linux/generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch b/target/linux/generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch
deleted file mode 100644
index 4f0e0e1c658..00000000000
--- a/target/linux/generic/backport-5.15/795-v6.6-12-r8152-Rename-RTL8152_UNPLUG-to-RTL8152_INACCESSIBLE.patch
+++ /dev/null
@@ -1,447 +0,0 @@
-From 715f67f33af45ce2cc3a5b1ef133cc8c8e7787b0 Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Fri, 20 Oct 2023 14:06:58 -0700
-Subject: [PATCH] r8152: Rename RTL8152_UNPLUG to RTL8152_INACCESSIBLE
-
-Whenever the RTL8152_UNPLUG is set that just tells the driver that all
-accesses will fail and we should just immediately bail. A future patch
-will use this same concept at a time when the driver hasn't actually
-been unplugged but is about to be reset. Rename the flag in
-preparation for the future patch.
-
-This is a no-op change and just a search and replace.
-
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Grant Grundler <grundler@chromium.org>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/usb/r8152.c | 96 ++++++++++++++++++++---------------------
- 1 file changed, 48 insertions(+), 48 deletions(-)
-
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -763,7 +763,7 @@ enum rtl_register_content {
- 
- /* rtl8152 flags */
- enum rtl8152_flags {
--	RTL8152_UNPLUG = 0,
-+	RTL8152_INACCESSIBLE = 0,
- 	RTL8152_SET_RX_MODE,
- 	WORK_ENABLE,
- 	RTL8152_LINK_CHG,
-@@ -1241,7 +1241,7 @@ int set_registers(struct r8152 *tp, u16
- static void rtl_set_unplug(struct r8152 *tp)
- {
- 	if (tp->udev->state == USB_STATE_NOTATTACHED) {
--		set_bit(RTL8152_UNPLUG, &tp->flags);
-+		set_bit(RTL8152_INACCESSIBLE, &tp->flags);
- 		smp_mb__after_atomic();
- 	}
- }
-@@ -1252,7 +1252,7 @@ static int generic_ocp_read(struct r8152
- 	u16 limit = 64;
- 	int ret = 0;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	/* both size and indix must be 4 bytes align */
-@@ -1296,7 +1296,7 @@ static int generic_ocp_write(struct r815
- 	u16 byteen_start, byteen_end, byen;
- 	u16 limit = 512;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	/* both size and indix must be 4 bytes align */
-@@ -1533,7 +1533,7 @@ static int read_mii_word(struct net_devi
- 	struct r8152 *tp = netdev_priv(netdev);
- 	int ret;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	if (phy_id != R8152_PHY_ID)
-@@ -1549,7 +1549,7 @@ void write_mii_word(struct net_device *n
- {
- 	struct r8152 *tp = netdev_priv(netdev);
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	if (phy_id != R8152_PHY_ID)
-@@ -1754,7 +1754,7 @@ static void read_bulk_callback(struct ur
- 	if (!tp)
- 		return;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	if (!test_bit(WORK_ENABLE, &tp->flags))
-@@ -1846,7 +1846,7 @@ static void write_bulk_callback(struct u
- 	if (!test_bit(WORK_ENABLE, &tp->flags))
- 		return;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	if (!skb_queue_empty(&tp->tx_queue))
-@@ -1867,7 +1867,7 @@ static void intr_callback(struct urb *ur
- 	if (!test_bit(WORK_ENABLE, &tp->flags))
- 		return;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	switch (status) {
-@@ -2611,7 +2611,7 @@ static void bottom_half(struct tasklet_s
- {
- 	struct r8152 *tp = from_tasklet(tp, t, tx_tl);
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	if (!test_bit(WORK_ENABLE, &tp->flags))
-@@ -2654,7 +2654,7 @@ int r8152_submit_rx(struct r8152 *tp, st
- 	int ret;
- 
- 	/* The rx would be stopped, so skip submitting */
--	if (test_bit(RTL8152_UNPLUG, &tp->flags) ||
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) ||
- 	    !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev))
- 		return 0;
- 
-@@ -3050,7 +3050,7 @@ static int rtl_enable(struct r8152 *tp)
- 
- static int rtl8152_enable(struct r8152 *tp)
- {
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	set_tx_qlen(tp);
-@@ -3137,7 +3137,7 @@ static int rtl8153_enable(struct r8152 *
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	set_tx_qlen(tp);
-@@ -3169,7 +3169,7 @@ static void rtl_disable(struct r8152 *tp
- 	u32 ocp_data;
- 	int i;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
- 		rtl_drop_queued_tx(tp);
- 		return;
- 	}
-@@ -3623,7 +3623,7 @@ static u16 r8153_phy_status(struct r8152
- 		}
- 
- 		msleep(20);
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 			break;
- 	}
- 
-@@ -3655,7 +3655,7 @@ static void r8153b_ups_en(struct r8152 *
- 			int i;
- 
- 			for (i = 0; i < 500; i++) {
--				if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 					return;
- 				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
- 				    AUTOLOAD_DONE)
-@@ -3697,7 +3697,7 @@ static void r8153c_ups_en(struct r8152 *
- 			int i;
- 
- 			for (i = 0; i < 500; i++) {
--				if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+				if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 					return;
- 				if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
- 				    AUTOLOAD_DONE)
-@@ -4042,8 +4042,8 @@ static int rtl_phy_patch_request(struct
- 	for (i = 0; wait && i < 5000; i++) {
- 		u32 ocp_data;
- 
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
--			break;
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
-+			return -ENODEV;
- 
- 		usleep_range(1000, 2000);
- 		ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT);
-@@ -6001,7 +6001,7 @@ static int rtl8156_enable(struct r8152 *
- 	u32 ocp_data;
- 	u16 speed;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	r8156_fc_parameter(tp);
-@@ -6059,7 +6059,7 @@ static int rtl8156b_enable(struct r8152
- 	u32 ocp_data;
- 	u16 speed;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	set_tx_qlen(tp);
-@@ -6245,7 +6245,7 @@ out:
- 
- static void rtl8152_up(struct r8152 *tp)
- {
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8152_aldps_en(tp, false);
-@@ -6255,7 +6255,7 @@ static void rtl8152_up(struct r8152 *tp)
- 
- static void rtl8152_down(struct r8152 *tp)
- {
--	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
- 		rtl_drop_queued_tx(tp);
- 		return;
- 	}
-@@ -6270,7 +6270,7 @@ static void rtl8153_up(struct r8152 *tp)
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153_u1u2en(tp, false);
-@@ -6310,7 +6310,7 @@ static void rtl8153_down(struct r8152 *t
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
- 		rtl_drop_queued_tx(tp);
- 		return;
- 	}
-@@ -6331,7 +6331,7 @@ static void rtl8153b_up(struct r8152 *tp
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153b_u1u2en(tp, false);
-@@ -6355,7 +6355,7 @@ static void rtl8153b_down(struct r8152 *
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
- 		rtl_drop_queued_tx(tp);
- 		return;
- 	}
-@@ -6392,7 +6392,7 @@ static void rtl8153c_up(struct r8152 *tp
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153b_u1u2en(tp, false);
-@@ -6473,7 +6473,7 @@ static void rtl8156_up(struct r8152 *tp)
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153b_u1u2en(tp, false);
-@@ -6546,7 +6546,7 @@ static void rtl8156_down(struct r8152 *t
- {
- 	u32 ocp_data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
- 		rtl_drop_queued_tx(tp);
- 		return;
- 	}
-@@ -6684,7 +6684,7 @@ static void rtl_work_func_t(struct work_
- 	/* If the device is unplugged or !netif_running(), the workqueue
- 	 * doesn't need to wake the device, and could return directly.
- 	 */
--	if (test_bit(RTL8152_UNPLUG, &tp->flags) || !netif_running(tp->netdev))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev))
- 		return;
- 
- 	if (usb_autopm_get_interface(tp->intf) < 0)
-@@ -6723,7 +6723,7 @@ static void rtl_hw_phy_work_func_t(struc
- {
- 	struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work);
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	if (usb_autopm_get_interface(tp->intf) < 0)
-@@ -6850,7 +6850,7 @@ static int rtl8152_close(struct net_devi
- 	netif_stop_queue(netdev);
- 
- 	res = usb_autopm_get_interface(tp->intf);
--	if (res < 0 || test_bit(RTL8152_UNPLUG, &tp->flags)) {
-+	if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) {
- 		rtl_drop_queued_tx(tp);
- 		rtl_stop_rx(tp);
- 	} else {
-@@ -6883,7 +6883,7 @@ static void r8152b_init(struct r8152 *tp
- 	u32 ocp_data;
- 	u16 data;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	data = r8152_mdio_read(tp, MII_BMCR);
-@@ -6927,7 +6927,7 @@ static void r8153_init(struct r8152 *tp)
- 	u16 data;
- 	int i;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153_u1u2en(tp, false);
-@@ -6938,7 +6938,7 @@ static void r8153_init(struct r8152 *tp)
- 			break;
- 
- 		msleep(20);
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 			break;
- 	}
- 
-@@ -7067,7 +7067,7 @@ static void r8153b_init(struct r8152 *tp
- 	u16 data;
- 	int i;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153b_u1u2en(tp, false);
-@@ -7078,7 +7078,7 @@ static void r8153b_init(struct r8152 *tp
- 			break;
- 
- 		msleep(20);
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 			break;
- 	}
- 
-@@ -7149,7 +7149,7 @@ static void r8153c_init(struct r8152 *tp
- 	u16 data;
- 	int i;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153b_u1u2en(tp, false);
-@@ -7169,7 +7169,7 @@ static void r8153c_init(struct r8152 *tp
- 			break;
- 
- 		msleep(20);
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 			return;
- 	}
- 
-@@ -7998,7 +7998,7 @@ static void r8156_init(struct r8152 *tp)
- 	u16 data;
- 	int i;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
-@@ -8019,7 +8019,7 @@ static void r8156_init(struct r8152 *tp)
- 			break;
- 
- 		msleep(20);
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 			return;
- 	}
- 
-@@ -8094,7 +8094,7 @@ static void r8156b_init(struct r8152 *tp
- 	u16 data;
- 	int i;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
-@@ -8128,7 +8128,7 @@ static void r8156b_init(struct r8152 *tp
- 			break;
- 
- 		msleep(20);
--		if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+		if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 			return;
- 	}
- 
-@@ -9153,7 +9153,7 @@ static int rtl8152_ioctl(struct net_devi
- 	struct mii_ioctl_data *data = if_mii(rq);
- 	int res;
- 
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return -ENODEV;
- 
- 	res = usb_autopm_get_interface(tp->intf);
-@@ -9255,7 +9255,7 @@ static const struct net_device_ops rtl81
- 
- static void rtl8152_unload(struct r8152 *tp)
- {
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	if (tp->version != RTL_VER_01)
-@@ -9264,7 +9264,7 @@ static void rtl8152_unload(struct r8152
- 
- static void rtl8153_unload(struct r8152 *tp)
- {
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153_power_cut_en(tp, false);
-@@ -9272,7 +9272,7 @@ static void rtl8153_unload(struct r8152
- 
- static void rtl8153b_unload(struct r8152 *tp)
- {
--	if (test_bit(RTL8152_UNPLUG, &tp->flags))
-+	if (test_bit(RTL8152_INACCESSIBLE, &tp->flags))
- 		return;
- 
- 	r8153b_power_cut_en(tp, false);
diff --git a/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch b/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch
index 0ce8206657a..3ef8f379119 100644
--- a/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch
+++ b/target/linux/generic/backport-5.15/795-v6.6-13-r8152-Block-future-register-access-if-register-acces.patch
@@ -232,7 +232,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
-@@ -8254,7 +8348,7 @@ static int rtl8152_pre_reset(struct usb_
+@@ -8268,7 +8362,7 @@ static int rtl8152_pre_reset(struct usb_
  	struct r8152 *tp = usb_get_intfdata(intf);
  	struct net_device *netdev;
  
@@ -241,7 +241,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		return 0;
  
  	netdev = tp->netdev;
-@@ -8269,7 +8363,9 @@ static int rtl8152_pre_reset(struct usb_
+@@ -8283,7 +8377,9 @@ static int rtl8152_pre_reset(struct usb_
  	napi_disable(&tp->napi);
  	if (netif_carrier_ok(netdev)) {
  		mutex_lock(&tp->control);
@@ -251,7 +251,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		mutex_unlock(&tp->control);
  	}
  
-@@ -8282,9 +8378,11 @@ static int rtl8152_post_reset(struct usb
+@@ -8296,9 +8392,11 @@ static int rtl8152_post_reset(struct usb
  	struct net_device *netdev;
  	struct sockaddr sa;
  
@@ -264,7 +264,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* reset the MAC address in case of policy change */
  	if (determine_ethernet_addr(tp, &sa) >= 0) {
  		rtnl_lock();
-@@ -9482,17 +9580,29 @@ static u8 __rtl_get_hw_ver(struct usb_de
+@@ -9496,17 +9594,29 @@ static u8 __rtl_get_hw_ver(struct usb_de
  	__le32 *tmp;
  	u8 version;
  	int ret;
@@ -300,7 +300,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	kfree(tmp);
  
-@@ -9566,25 +9676,14 @@ u8 rtl8152_get_version(struct usb_interf
+@@ -9580,25 +9690,14 @@ u8 rtl8152_get_version(struct usb_interf
  }
  EXPORT_SYMBOL_GPL(rtl8152_get_version);
  
@@ -328,7 +328,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	usb_reset_device(udev);
  	netdev = alloc_etherdev(sizeof(struct r8152));
  	if (!netdev) {
-@@ -9757,10 +9856,20 @@ static int rtl8152_probe(struct usb_inte
+@@ -9771,10 +9870,20 @@ static int rtl8152_probe(struct usb_inte
  	else
  		device_set_wakeup_enable(&udev->dev, false);
  
@@ -349,7 +349,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  out1:
  	tasklet_kill(&tp->tx_tl);
  	cancel_delayed_work_sync(&tp->hw_phy_work);
-@@ -9769,10 +9878,46 @@ out1:
+@@ -9783,10 +9892,46 @@ out1:
  	rtl8152_release_firmware(tp);
  	usb_set_intfdata(intf, NULL);
  out:
diff --git a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
index a2168aaba5f..698e524c356 100644
--- a/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
+++ b/target/linux/generic/backport-5.15/797-v5.17-net-usb-ax88179_178a-add-TSO-feature.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/usb/ax88179_178a.c
 +++ b/drivers/net/usb/ax88179_178a.c
-@@ -1377,11 +1377,12 @@ static int ax88179_bind(struct usbnet *d
+@@ -1333,11 +1333,12 @@ static int ax88179_bind(struct usbnet *d
  	dev->mii.phy_id = 0x03;
  	dev->mii.supports_gmii = 1;
  
@@ -33,9 +33,9 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +
 +	netif_set_gso_max_size(dev->net, 16384);
  
- 	/* Enable checksum offload */
- 	*tmp = AX_RXCOE_IP | AX_RXCOE_TCP | AX_RXCOE_UDP |
-@@ -1587,17 +1588,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
+ 	ax88179_reset(dev);
+ 
+@@ -1507,17 +1508,19 @@ ax88179_tx_fixup(struct usbnet *dev, str
  {
  	u32 tx_hdr1, tx_hdr2;
  	int frame_size = dev->maxpacket;
@@ -57,7 +57,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if ((skb_header_cloned(skb) || headroom < 0) &&
  	    pskb_expand_head(skb, headroom < 0 ? 8 : 0, 0, GFP_ATOMIC)) {
  		dev_kfree_skb_any(skb);
-@@ -1608,6 +1611,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
+@@ -1528,6 +1531,8 @@ ax88179_tx_fixup(struct usbnet *dev, str
  	put_unaligned_le32(tx_hdr1, ptr);
  	put_unaligned_le32(tx_hdr2, ptr + 4);
  
diff --git a/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch
index 41d3e121de1..dbd734e9cf4 100644
--- a/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch
+++ b/target/linux/generic/backport-5.15/810-v5.17-net-qmi_wwan-add-ZTE-MF286D-modem-19d2-1485.patch
@@ -49,7 +49,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/usb/qmi_wwan.c
 +++ b/drivers/net/usb/qmi_wwan.c
-@@ -1316,6 +1316,7 @@ static const struct usb_device_id produc
+@@ -1317,6 +1317,7 @@ static const struct usb_device_id produc
  	{QMI_FIXED_INTF(0x19d2, 0x1426, 2)},	/* ZTE MF91 */
  	{QMI_FIXED_INTF(0x19d2, 0x1428, 2)},	/* Telewell TW-LTE 4G v2 */
  	{QMI_FIXED_INTF(0x19d2, 0x1432, 3)},	/* ZTE ME3620 */
diff --git a/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch b/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
index 3e60f91a2a9..6e5ac8b249e 100644
--- a/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
+++ b/target/linux/generic/backport-5.15/815-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
@@ -153,7 +153,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #include <linux/linkmode.h>
  #include <linux/netlink.h>
  #include <linux/mdio.h>
-@@ -582,6 +583,7 @@ struct macsec_ops;
+@@ -590,6 +591,7 @@ struct macsec_ops;
   * @phy_num_led_triggers: Number of triggers in @phy_led_triggers
   * @led_link_trigger: LED trigger for link up/down
   * @last_triggered: last LED trigger for link speed
@@ -161,7 +161,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @master_slave_set: User requested master/slave configuration
   * @master_slave_get: Current master/slave advertisement
   * @master_slave_state: Current master/slave configuration
-@@ -668,6 +670,7 @@ struct phy_device {
+@@ -678,6 +680,7 @@ struct phy_device {
  
  	struct phy_led_trigger *led_link_trigger;
  #endif
@@ -169,7 +169,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/*
  	 * Interrupt number for this PHY
-@@ -739,6 +742,19 @@ struct phy_tdr_config {
+@@ -749,6 +752,19 @@ struct phy_tdr_config {
  #define PHY_PAIR_ALL -1
  
  /**
diff --git a/target/linux/generic/backport-5.15/815-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-5.15/815-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index f990557cc73..3968a884b8b 100644
--- a/target/linux/generic/backport-5.15/815-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-5.15/815-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -59,7 +59,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -745,15 +745,19 @@ struct phy_tdr_config {
+@@ -755,15 +755,19 @@ struct phy_tdr_config {
   * struct phy_led: An LED driven by the PHY
   *
   * @list: List of LEDs
@@ -79,7 +79,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /**
   * struct phy_driver - Driver structure for a particular PHY type
   *
-@@ -953,6 +957,15 @@ struct phy_driver {
+@@ -978,6 +982,15 @@ struct phy_driver {
  	int (*get_sqi)(struct phy_device *dev);
  	/** @get_sqi_max: Get the maximum signal quality indication */
  	int (*get_sqi_max)(struct phy_device *dev);
diff --git a/target/linux/generic/backport-5.15/815-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-5.15/815-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index 4814688de45..35e1a1c7238 100644
--- a/target/linux/generic/backport-5.15/815-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-5.15/815-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -52,7 +52,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -966,6 +966,18 @@ struct phy_driver {
+@@ -991,6 +991,18 @@ struct phy_driver {
  	 */
  	int (*led_brightness_set)(struct phy_device *dev,
  				  u8 index, enum led_brightness value);
diff --git a/target/linux/generic/backport-5.15/820-v6.7-0005-nvmem-Do-not-expect-fixed-layouts-to-grab-a-layout-d.patch b/target/linux/generic/backport-5.15/820-v6.7-0005-nvmem-Do-not-expect-fixed-layouts-to-grab-a-layout-d.patch
new file mode 100644
index 00000000000..bd5ceaabf7d
--- /dev/null
+++ b/target/linux/generic/backport-5.15/820-v6.7-0005-nvmem-Do-not-expect-fixed-layouts-to-grab-a-layout-d.patch
@@ -0,0 +1,45 @@
+From b7c1e53751cb3990153084f31c41f25fde3b629c Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 24 Nov 2023 20:38:14 +0100
+Subject: [PATCH] nvmem: Do not expect fixed layouts to grab a layout driver
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Two series lived in parallel for some time, which led to this situation:
+- The nvmem-layout container is used for dynamic layouts
+- We now expect fixed layouts to also use the nvmem-layout container but
+this does not require any additional driver, the support is built-in the
+nvmem core.
+
+Ensure we don't refuse to probe for wrong reasons.
+
+Fixes: 27f699e578b1 ("nvmem: core: add support for fixed cells *layout*")
+Cc: stable@vger.kernel.org
+Reported-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Tested-by: Rafał Miłecki <rafal@milecki.pl>
+Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
+Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
+
+Link: https://lore.kernel.org/r/20231124193814.360552-1-miquel.raynal@bootlin.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -797,6 +797,12 @@ static struct nvmem_layout *nvmem_layout
+ 	if (!layout_np)
+ 		return NULL;
+ 
++	/* Fixed layouts don't have a matching driver */
++	if (of_device_is_compatible(layout_np, "fixed-layout")) {
++		of_node_put(layout_np);
++		return NULL;
++	}
++
+ 	/*
+ 	 * In case the nvmem device was built-in while the layout was built as a
+ 	 * module, we shall manually request the layout driver loading otherwise
diff --git a/target/linux/generic/backport-5.15/820-v6.7-0006-nvmem-brcm_nvram-store-a-copy-of-NVRAM-content.patch b/target/linux/generic/backport-5.15/820-v6.7-0006-nvmem-brcm_nvram-store-a-copy-of-NVRAM-content.patch
new file mode 100644
index 00000000000..d49a20599dc
--- /dev/null
+++ b/target/linux/generic/backport-5.15/820-v6.7-0006-nvmem-brcm_nvram-store-a-copy-of-NVRAM-content.patch
@@ -0,0 +1,261 @@
+From 1e37bf84afacd5ba17b7a13a18ca2bc78aff05c0 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Fri, 15 Dec 2023 11:13:58 +0000
+Subject: [PATCH] nvmem: brcm_nvram: store a copy of NVRAM content
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This driver uses MMIO access for reading NVRAM from a flash device.
+Underneath there is a flash controller that reads data and provides
+mapping window.
+
+Using MMIO interface affects controller configuration and may break real
+controller driver. It was reported by multiple users of devices with
+NVRAM stored on NAND.
+
+Modify driver to read & cache NVRAM content during init and use that
+copy to provide NVMEM data when requested. On NAND flashes due to their
+alignment NVRAM partitions can be quite big (1 MiB and more) while
+actual NVRAM content stays quite small (usually 16 to 32 KiB). To avoid
+allocating so much memory check for actual data length.
+
+Link: https://lore.kernel.org/linux-mtd/CACna6rwf3_9QVjYcM+847biTX=K0EoWXuXcSMkJO1Vy_5vmVqA@mail.gmail.com/
+Fixes: 3fef9ed0627a ("nvmem: brcm_nvram: new driver exposing Broadcom's NVRAM")
+Cc:  <Stable@vger.kernel.org>
+Cc: Arınç ÜNAL <arinc.unal@arinc9.com>
+Cc: Florian Fainelli <florian.fainelli@broadcom.com>
+Cc: Scott Branden <scott.branden@broadcom.com>
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Arınç ÜNAL <arinc.unal@arinc9.com>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111358.316727-3-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/brcm_nvram.c | 134 ++++++++++++++++++++++++++-----------
+ 1 file changed, 94 insertions(+), 40 deletions(-)
+
+--- a/drivers/nvmem/brcm_nvram.c
++++ b/drivers/nvmem/brcm_nvram.c
+@@ -17,9 +17,23 @@
+ 
+ #define NVRAM_MAGIC			"FLSH"
+ 
++/**
++ * struct brcm_nvram - driver state internal struct
++ *
++ * @dev:		NVMEM device pointer
++ * @nvmem_size:		Size of the whole space available for NVRAM
++ * @data:		NVRAM data copy stored to avoid poking underlaying flash controller
++ * @data_len:		NVRAM data size
++ * @padding_byte:	Padding value used to fill remaining space
++ * @cells:		Array of discovered NVMEM cells
++ * @ncells:		Number of elements in cells
++ */
+ struct brcm_nvram {
+ 	struct device *dev;
+-	void __iomem *base;
++	size_t nvmem_size;
++	uint8_t *data;
++	size_t data_len;
++	uint8_t padding_byte;
+ 	struct nvmem_cell_info *cells;
+ 	int ncells;
+ };
+@@ -36,10 +50,47 @@ static int brcm_nvram_read(void *context
+ 			   size_t bytes)
+ {
+ 	struct brcm_nvram *priv = context;
+-	u8 *dst = val;
++	size_t to_copy;
++
++	if (offset + bytes > priv->data_len)
++		to_copy = max_t(ssize_t, (ssize_t)priv->data_len - offset, 0);
++	else
++		to_copy = bytes;
++
++	memcpy(val, priv->data + offset, to_copy);
++
++	memset((uint8_t *)val + to_copy, priv->padding_byte, bytes - to_copy);
++
++	return 0;
++}
++
++static int brcm_nvram_copy_data(struct brcm_nvram *priv, struct platform_device *pdev)
++{
++	struct resource *res;
++	void __iomem *base;
++
++	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	priv->nvmem_size = resource_size(res);
++
++	priv->padding_byte = readb(base + priv->nvmem_size - 1);
++	for (priv->data_len = priv->nvmem_size;
++	     priv->data_len;
++	     priv->data_len--) {
++		if (readb(base + priv->data_len - 1) != priv->padding_byte)
++			break;
++	}
++	WARN(priv->data_len > SZ_128K, "Unexpected (big) NVRAM size: %zu B\n", priv->data_len);
+ 
+-	while (bytes--)
+-		*dst++ = readb(priv->base + offset++);
++	priv->data = devm_kzalloc(priv->dev, priv->data_len, GFP_KERNEL);
++	if (!priv->data)
++		return -ENOMEM;
++
++	memcpy_fromio(priv->data, base, priv->data_len);
++
++	bcm47xx_nvram_init_from_iomem(base, priv->data_len);
+ 
+ 	return 0;
+ }
+@@ -67,8 +118,13 @@ static int brcm_nvram_add_cells(struct b
+ 				size_t len)
+ {
+ 	struct device *dev = priv->dev;
+-	char *var, *value, *eq;
++	char *var, *value;
++	uint8_t tmp;
+ 	int idx;
++	int err = 0;
++
++	tmp = priv->data[len - 1];
++	priv->data[len - 1] = '\0';
+ 
+ 	priv->ncells = 0;
+ 	for (var = data + sizeof(struct brcm_nvram_header);
+@@ -78,67 +134,68 @@ static int brcm_nvram_add_cells(struct b
+ 	}
+ 
+ 	priv->cells = devm_kcalloc(dev, priv->ncells, sizeof(*priv->cells), GFP_KERNEL);
+-	if (!priv->cells)
+-		return -ENOMEM;
++	if (!priv->cells) {
++		err = -ENOMEM;
++		goto out;
++	}
+ 
+ 	for (var = data + sizeof(struct brcm_nvram_header), idx = 0;
+ 	     var < (char *)data + len && *var;
+ 	     var = value + strlen(value) + 1, idx++) {
++		char *eq, *name;
++
+ 		eq = strchr(var, '=');
+ 		if (!eq)
+ 			break;
+ 		*eq = '\0';
++		name = devm_kstrdup(dev, var, GFP_KERNEL);
++		*eq = '=';
++		if (!name) {
++			err = -ENOMEM;
++			goto out;
++		}
+ 		value = eq + 1;
+ 
+-		priv->cells[idx].name = devm_kstrdup(dev, var, GFP_KERNEL);
+-		if (!priv->cells[idx].name)
+-			return -ENOMEM;
++		priv->cells[idx].name = name;
+ 		priv->cells[idx].offset = value - (char *)data;
+ 		priv->cells[idx].bytes = strlen(value);
+ 		priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name);
+-		if (!strcmp(var, "et0macaddr") ||
+-		    !strcmp(var, "et1macaddr") ||
+-		    !strcmp(var, "et2macaddr")) {
++		if (!strcmp(name, "et0macaddr") ||
++		    !strcmp(name, "et1macaddr") ||
++		    !strcmp(name, "et2macaddr")) {
+ 			priv->cells[idx].raw_len = strlen(value);
+ 			priv->cells[idx].bytes = ETH_ALEN;
+ 			priv->cells[idx].read_post_process = brcm_nvram_read_post_process_macaddr;
+ 		}
+ 	}
+ 
+-	return 0;
++out:
++	priv->data[len - 1] = tmp;
++	return err;
+ }
+ 
+ static int brcm_nvram_parse(struct brcm_nvram *priv)
+ {
++	struct brcm_nvram_header *header = (struct brcm_nvram_header *)priv->data;
+ 	struct device *dev = priv->dev;
+-	struct brcm_nvram_header header;
+-	uint8_t *data;
+ 	size_t len;
+ 	int err;
+ 
+-	memcpy_fromio(&header, priv->base, sizeof(header));
+-
+-	if (memcmp(header.magic, NVRAM_MAGIC, 4)) {
++	if (memcmp(header->magic, NVRAM_MAGIC, 4)) {
+ 		dev_err(dev, "Invalid NVRAM magic\n");
+ 		return -EINVAL;
+ 	}
+ 
+-	len = le32_to_cpu(header.len);
+-
+-	data = kzalloc(len, GFP_KERNEL);
+-	if (!data)
+-		return -ENOMEM;
+-
+-	memcpy_fromio(data, priv->base, len);
+-	data[len - 1] = '\0';
+-
+-	err = brcm_nvram_add_cells(priv, data, len);
+-	if (err) {
+-		dev_err(dev, "Failed to add cells: %d\n", err);
+-		return err;
++	len = le32_to_cpu(header->len);
++	if (len > priv->nvmem_size) {
++		dev_err(dev, "NVRAM length (%zd) exceeds mapped size (%zd)\n", len,
++			priv->nvmem_size);
++		return -EINVAL;
+ 	}
+ 
+-	kfree(data);
++	err = brcm_nvram_add_cells(priv, priv->data, len);
++	if (err)
++		dev_err(dev, "Failed to add cells: %d\n", err);
+ 
+ 	return 0;
+ }
+@@ -150,7 +207,6 @@ static int brcm_nvram_probe(struct platf
+ 		.reg_read = brcm_nvram_read,
+ 	};
+ 	struct device *dev = &pdev->dev;
+-	struct resource *res;
+ 	struct brcm_nvram *priv;
+ 	int err;
+ 
+@@ -159,21 +215,19 @@ static int brcm_nvram_probe(struct platf
+ 		return -ENOMEM;
+ 	priv->dev = dev;
+ 
+-	priv->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
+-	if (IS_ERR(priv->base))
+-		return PTR_ERR(priv->base);
++	err = brcm_nvram_copy_data(priv, pdev);
++	if (err)
++		return err;
+ 
+ 	err = brcm_nvram_parse(priv);
+ 	if (err)
+ 		return err;
+ 
+-	bcm47xx_nvram_init_from_iomem(priv->base, resource_size(res));
+-
+ 	config.dev = dev;
+ 	config.cells = priv->cells;
+ 	config.ncells = priv->ncells;
+ 	config.priv = priv;
+-	config.size = resource_size(res);
++	config.size = priv->nvmem_size;
+ 
+ 	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config));
+ }
diff --git a/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch b/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch
index b00cf574199..0ad89de5600 100644
--- a/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch
+++ b/target/linux/generic/backport-5.15/826-v5.17-of-base-make-small-of_parse_phandle-variants-static-.patch
@@ -128,7 +128,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  
  /**
   * of_parse_phandle_with_args_map() - Find a node pointed by phandle in a list and remap it
-@@ -1684,47 +1612,6 @@ free:
+@@ -1685,47 +1613,6 @@ free:
  EXPORT_SYMBOL(of_parse_phandle_with_args_map);
  
  /**
@@ -200,7 +200,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  extern int of_count_phandle_with_args(const struct device_node *np,
  	const char *list_name, const char *cells_name);
  
-@@ -864,18 +858,12 @@ static inline int of_property_read_strin
+@@ -714,18 +708,12 @@ static inline int of_property_read_strin
  	return -ENOSYS;
  }
  
@@ -225,7 +225,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  {
  	return -ENOSYS;
  }
-@@ -889,13 +877,6 @@ static inline int of_parse_phandle_with_
+@@ -739,13 +727,6 @@ static inline int of_parse_phandle_with_
  	return -ENOSYS;
  }
  
@@ -239,7 +239,7 @@ Link: https://lore.kernel.org/r/20220118173504.2867523-2-michael@walle.cc
  static inline int of_count_phandle_with_args(const struct device_node *np,
  					     const char *list_name,
  					     const char *cells_name)
-@@ -1077,6 +1058,117 @@ static inline bool of_node_is_type(const
+@@ -927,6 +908,117 @@ static inline bool of_node_is_type(const
  }
  
  /**
diff --git a/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch b/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch
index 2b2a60e096b..97f4c6981e2 100644
--- a/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch
+++ b/target/linux/generic/backport-5.15/827-v6.3-0001-of-base-add-of_parse_phandle_with_optional_args.patch
@@ -24,7 +24,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 
 --- a/include/linux/of.h
 +++ b/include/linux/of.h
-@@ -1169,6 +1169,31 @@ static inline int of_parse_phandle_with_
+@@ -1019,6 +1019,31 @@ static inline int of_parse_phandle_with_
  }
  
  /**
diff --git a/target/linux/generic/backport-5.15/828-v6.4-0003-of-Rename-of_modalias_node.patch b/target/linux/generic/backport-5.15/828-v6.4-0003-of-Rename-of_modalias_node.patch
index 6c205217018..855d45311e6 100644
--- a/target/linux/generic/backport-5.15/828-v6.4-0003-of-Rename-of_modalias_node.patch
+++ b/target/linux/generic/backport-5.15/828-v6.4-0003-of-Rename-of_modalias_node.patch
@@ -148,7 +148,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
   * of_find_node_by_phandle - Find a node given a phandle
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -2128,8 +2128,8 @@ of_register_spi_device(struct spi_contro
+@@ -2140,8 +2140,8 @@ of_register_spi_device(struct spi_contro
  	}
  
  	/* Select device driver */
diff --git a/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch b/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch
index a70c6f2eec8..b4554b2ecad 100644
--- a/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch
+++ b/target/linux/generic/backport-5.15/828-v6.4-0004-of-Move-of_modalias-to-module.c.patch
@@ -145,7 +145,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  /* phandle iterator functions */
  extern int of_phandle_iterator_init(struct of_phandle_iterator *it,
  				    const struct device_node *np,
-@@ -885,6 +888,12 @@ static inline int of_count_phandle_with_
+@@ -735,6 +738,12 @@ static inline int of_count_phandle_with_
  	return -ENOSYS;
  }
  
diff --git a/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch b/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch
index 06bc24ca6e3..ad42039e112 100644
--- a/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch
+++ b/target/linux/generic/backport-5.15/828-v6.4-0005-of-Move-the-request-module-helper-logic-to-module.c.patch
@@ -117,7 +117,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
  
  /* phandle iterator functions */
  extern int of_phandle_iterator_init(struct of_phandle_iterator *it,
-@@ -893,6 +894,11 @@ static inline ssize_t of_modalias(const
+@@ -743,6 +744,11 @@ static inline ssize_t of_modalias(const
  {
  	return -ENODEV;
  }
diff --git a/target/linux/generic/backport-5.15/829-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch b/target/linux/generic/backport-5.15/829-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch
new file mode 100644
index 00000000000..1365834563b
--- /dev/null
+++ b/target/linux/generic/backport-5.15/829-v6.3-i915-Move-list_count-to-list.h-as-list_count_nodes-f.patch
@@ -0,0 +1,75 @@
+From 4d70c74659d9746502b23d055dba03d1d28ec388 Mon Sep 17 00:00:00 2001
+From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Date: Wed, 30 Nov 2022 15:48:35 +0200
+Subject: [PATCH] i915: Move list_count() to list.h as list_count_nodes() for
+ broader use
+
+Some of the existing users, and definitely will be new ones, want to
+count existing nodes in the list. Provide a generic API for that by
+moving code from i915 to list.h.
+
+Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
+Acked-by: Jani Nikula <jani.nikula@intel.com>
+Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
+Link: https://lore.kernel.org/r/20221130134838.23805-1-andriy.shevchenko@linux.intel.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/gpu/drm/i915/gt/intel_engine_cs.c | 15 ++-------------
+ include/linux/list.h                      | 15 +++++++++++++++
+ 2 files changed, 17 insertions(+), 13 deletions(-)
+
+--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
++++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+@@ -1639,17 +1639,6 @@ static void print_request_ring(struct dr
+ 	}
+ }
+ 
+-static unsigned long list_count(struct list_head *list)
+-{
+-	struct list_head *pos;
+-	unsigned long count = 0;
+-
+-	list_for_each(pos, list)
+-		count++;
+-
+-	return count;
+-}
+-
+ static unsigned long read_ul(void *p, size_t x)
+ {
+ 	return *(unsigned long *)(p + x);
+@@ -1824,8 +1813,8 @@ void intel_engine_dump(struct intel_engi
+ 	spin_lock_irqsave(&engine->sched_engine->lock, flags);
+ 	engine_dump_active_requests(engine, m);
+ 
+-	drm_printf(m, "\tOn hold?: %lu\n",
+-		   list_count(&engine->sched_engine->hold));
++	drm_printf(m, "\tOn hold?: %zu\n",
++		   list_count_nodes(&engine->sched_engine->hold));
+ 	spin_unlock_irqrestore(&engine->sched_engine->lock, flags);
+ 
+ 	drm_printf(m, "\tMMIO base:  0x%08x\n", engine->mmio_base);
+--- a/include/linux/list.h
++++ b/include/linux/list.h
+@@ -628,6 +628,21 @@ static inline void list_splice_tail_init
+ 	     pos = n, n = pos->prev)
+ 
+ /**
++ * list_count_nodes - count nodes in the list
++ * @head:	the head for your list.
++ */
++static inline size_t list_count_nodes(struct list_head *head)
++{
++	struct list_head *pos;
++	size_t count = 0;
++
++	list_for_each(pos, head)
++		count++;
++
++	return count;
++}
++
++/**
+  * list_entry_is_head - test if the entry points to the head of the list
+  * @pos:	the type * to cursor
+  * @head:	the head for your list.
diff --git a/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch b/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
index dd2b310d66f..7f6bac37dd1 100644
--- a/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
+++ b/target/linux/generic/backport-5.15/830-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
@@ -48,7 +48,7 @@ Signed-off-by: Lee Jones <lee@kernel.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA
+@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA
  	depends on I2C
  	depends on MACH_ARMADA_38X || COMPILE_TEST
  	depends on OF
diff --git a/target/linux/generic/backport-5.15/832-v6.8-of-device-Export-of_device_make_bus_id.patch b/target/linux/generic/backport-5.15/832-v6.8-of-device-Export-of_device_make_bus_id.patch
new file mode 100644
index 00000000000..d097c1b0f45
--- /dev/null
+++ b/target/linux/generic/backport-5.15/832-v6.8-of-device-Export-of_device_make_bus_id.patch
@@ -0,0 +1,128 @@
+From 7f38b70042fcaa49219045bd1a9a2836e27a58ac Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:27 +0000
+Subject: [PATCH] of: device: Export of_device_make_bus_id()
+
+This helper is really handy to create unique device names based on their
+device tree path, we may need it outside of the OF core (in the NVMEM
+subsystem) so let's export it. As this helper has nothing patform
+specific, let's move it to of/device.c instead of of/platform.c so we
+can add its prototype to of_device.h.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-2-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/of/device.c       | 41 +++++++++++++++++++++++++++++++++++++++
+ drivers/of/platform.c     | 40 --------------------------------------
+ include/linux/of_device.h |  6 ++++++
+ 3 files changed, 47 insertions(+), 40 deletions(-)
+
+--- a/drivers/of/device.c
++++ b/drivers/of/device.c
+@@ -337,3 +337,38 @@ int of_device_uevent_modalias(struct dev
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(of_device_uevent_modalias);
++
++/**
++ * of_device_make_bus_id - Use the device node data to assign a unique name
++ * @dev: pointer to device structure that is linked to a device tree node
++ *
++ * This routine will first try using the translated bus address to
++ * derive a unique name. If it cannot, then it will prepend names from
++ * parent nodes until a unique name can be derived.
++ */
++void of_device_make_bus_id(struct device *dev)
++{
++	struct device_node *node = dev->of_node;
++	const __be32 *reg;
++	u64 addr;
++
++	/* Construct the name, using parent nodes if necessary to ensure uniqueness */
++	while (node->parent) {
++		/*
++		 * If the address can be translated, then that is as much
++		 * uniqueness as we need. Make it the first component and return
++		 */
++		reg = of_get_property(node, "reg", NULL);
++		if (reg && (addr = of_translate_address(node, reg)) != OF_BAD_ADDR) {
++			dev_set_name(dev, dev_name(dev) ? "%llx.%pOFn:%s" : "%llx.%pOFn",
++				     addr, node, dev_name(dev));
++			return;
++		}
++
++		/* format arguments only used if dev_name() resolves to NULL */
++		dev_set_name(dev, dev_name(dev) ? "%s:%s" : "%s",
++			     kbasename(node->full_name), dev_name(dev));
++		node = node->parent;
++	}
++}
++EXPORT_SYMBOL_GPL(of_device_make_bus_id);
+--- a/drivers/of/platform.c
++++ b/drivers/of/platform.c
+@@ -64,40 +64,6 @@ EXPORT_SYMBOL(of_find_device_by_node);
+  */
+ 
+ /**
+- * of_device_make_bus_id - Use the device node data to assign a unique name
+- * @dev: pointer to device structure that is linked to a device tree node
+- *
+- * This routine will first try using the translated bus address to
+- * derive a unique name. If it cannot, then it will prepend names from
+- * parent nodes until a unique name can be derived.
+- */
+-static void of_device_make_bus_id(struct device *dev)
+-{
+-	struct device_node *node = dev->of_node;
+-	const __be32 *reg;
+-	u64 addr;
+-
+-	/* Construct the name, using parent nodes if necessary to ensure uniqueness */
+-	while (node->parent) {
+-		/*
+-		 * If the address can be translated, then that is as much
+-		 * uniqueness as we need. Make it the first component and return
+-		 */
+-		reg = of_get_property(node, "reg", NULL);
+-		if (reg && (addr = of_translate_address(node, reg)) != OF_BAD_ADDR) {
+-			dev_set_name(dev, dev_name(dev) ? "%llx.%pOFn:%s" : "%llx.%pOFn",
+-				     addr, node, dev_name(dev));
+-			return;
+-		}
+-
+-		/* format arguments only used if dev_name() resolves to NULL */
+-		dev_set_name(dev, dev_name(dev) ? "%s:%s" : "%s",
+-			     kbasename(node->full_name), dev_name(dev));
+-		node = node->parent;
+-	}
+-}
+-
+-/**
+  * of_device_alloc - Allocate and initialize an of_device
+  * @np: device node to assign to device
+  * @bus_id: Name to assign to the device.  May be null to use default name.
+--- a/include/linux/of_device.h
++++ b/include/linux/of_device.h
+@@ -56,6 +56,9 @@ static inline int of_dma_configure(struc
+ {
+ 	return of_dma_configure_id(dev, np, force_dma, NULL);
+ }
++
++void of_device_make_bus_id(struct device *dev);
++
+ #else /* CONFIG_OF */
+ 
+ static inline int of_driver_match_device(struct device *dev,
+@@ -113,6 +116,9 @@ static inline int of_dma_configure(struc
+ {
+ 	return 0;
+ }
++
++static inline void of_device_make_bus_id(struct device *dev) {}
++
+ #endif /* CONFIG_OF */
+ 
+ #endif /* _LINUX_OF_DEVICE_H */
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0001-nvmem-Move-of_nvmem_layout_get_container-in-another-.patch b/target/linux/generic/backport-5.15/834-v6.8-0001-nvmem-Move-of_nvmem_layout_get_container-in-another-.patch
new file mode 100644
index 00000000000..2093fac8a12
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0001-nvmem-Move-of_nvmem_layout_get_container-in-another-.patch
@@ -0,0 +1,95 @@
+From 4a1a40233b4a9fc159a5c7a27dc34c5c7bc5be55 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:28 +0000
+Subject: [PATCH] nvmem: Move of_nvmem_layout_get_container() in another header
+
+nvmem-consumer.h is included by consumer devices, extracting data from
+NVMEM devices whereas nvmem-provider.h is included by devices providing
+NVMEM content.
+
+The only users of of_nvmem_layout_get_container() outside of the core
+are layout drivers, so better move its prototype to nvmem-provider.h.
+
+While we do so, we also move the kdoc associated with the function to
+the header rather than the .c file.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-3-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c           |  8 --------
+ include/linux/nvmem-consumer.h |  7 -------
+ include/linux/nvmem-provider.h | 21 +++++++++++++++++++++
+ 3 files changed, 21 insertions(+), 15 deletions(-)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -848,14 +848,6 @@ static int nvmem_add_cells_from_layout(s
+ }
+ 
+ #if IS_ENABLED(CONFIG_OF)
+-/**
+- * of_nvmem_layout_get_container() - Get OF node to layout container.
+- *
+- * @nvmem: nvmem device.
+- *
+- * Return: a node pointer with refcount incremented or NULL if no
+- * container exists. Use of_node_put() on it when done.
+- */
+ struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem)
+ {
+ 	return of_get_child_by_name(nvmem->dev.of_node, "nvmem-layout");
+--- a/include/linux/nvmem-consumer.h
++++ b/include/linux/nvmem-consumer.h
+@@ -241,7 +241,6 @@ struct nvmem_cell *of_nvmem_cell_get(str
+ 				     const char *id);
+ struct nvmem_device *of_nvmem_device_get(struct device_node *np,
+ 					 const char *name);
+-struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem);
+ #else
+ static inline struct nvmem_cell *of_nvmem_cell_get(struct device_node *np,
+ 						   const char *id)
+@@ -254,12 +253,6 @@ static inline struct nvmem_device *of_nv
+ {
+ 	return ERR_PTR(-EOPNOTSUPP);
+ }
+-
+-static inline struct device_node *
+-of_nvmem_layout_get_container(struct nvmem_device *nvmem)
+-{
+-	return NULL;
+-}
+ #endif /* CONFIG_NVMEM && CONFIG_OF */
+ 
+ #endif  /* ifndef _LINUX_NVMEM_CONSUMER_H */
+--- a/include/linux/nvmem-provider.h
++++ b/include/linux/nvmem-provider.h
+@@ -244,6 +244,27 @@ nvmem_layout_get_match_data(struct nvmem
+ 
+ #endif /* CONFIG_NVMEM */
+ 
++#if IS_ENABLED(CONFIG_NVMEM) && IS_ENABLED(CONFIG_OF)
++
++/**
++ * of_nvmem_layout_get_container() - Get OF node of layout container
++ *
++ * @nvmem: nvmem device
++ *
++ * Return: a node pointer with refcount incremented or NULL if no
++ * container exists. Use of_node_put() on it when done.
++ */
++struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem);
++
++#else  /* CONFIG_NVMEM && CONFIG_OF */
++
++static inline struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem)
++{
++	return NULL;
++}
++
++#endif /* CONFIG_NVMEM && CONFIG_OF */
++
+ #define module_nvmem_layout_driver(__layout_driver)		\
+ 	module_driver(__layout_driver, nvmem_layout_register,	\
+ 		      nvmem_layout_unregister)
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0002-nvmem-Create-a-header-for-internal-sharing.patch b/target/linux/generic/backport-5.15/834-v6.8-0002-nvmem-Create-a-header-for-internal-sharing.patch
new file mode 100644
index 00000000000..e722109f919
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0002-nvmem-Create-a-header-for-internal-sharing.patch
@@ -0,0 +1,91 @@
+From ec9c08a1cb8dc5e8e003f95f5f62de41dde235bb Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:29 +0000
+Subject: [PATCH] nvmem: Create a header for internal sharing
+
+Before adding all the NVMEM layout bus infrastructure to the core, let's
+move the main nvmem_device structure in an internal header, only
+available to the core. This way all the additional code can be added in
+a dedicated file in order to keep the current core file tidy.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-4-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c      | 24 +-----------------------
+ drivers/nvmem/internals.h | 35 +++++++++++++++++++++++++++++++++++
+ 2 files changed, 36 insertions(+), 23 deletions(-)
+ create mode 100644 drivers/nvmem/internals.h
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -20,29 +20,7 @@
+ #include <linux/of_device.h>
+ #include <linux/slab.h>
+ 
+-struct nvmem_device {
+-	struct module		*owner;
+-	struct device		dev;
+-	int			stride;
+-	int			word_size;
+-	int			id;
+-	struct kref		refcnt;
+-	size_t			size;
+-	bool			read_only;
+-	bool			root_only;
+-	int			flags;
+-	enum nvmem_type		type;
+-	struct bin_attribute	eeprom;
+-	struct device		*base_dev;
+-	struct list_head	cells;
+-	const struct nvmem_keepout *keepout;
+-	unsigned int		nkeepout;
+-	nvmem_reg_read_t	reg_read;
+-	nvmem_reg_write_t	reg_write;
+-	struct gpio_desc	*wp_gpio;
+-	struct nvmem_layout	*layout;
+-	void *priv;
+-};
++#include "internals.h"
+ 
+ #define to_nvmem_device(d) container_of(d, struct nvmem_device, dev)
+ 
+--- /dev/null
++++ b/drivers/nvmem/internals.h
+@@ -0,0 +1,35 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#ifndef _LINUX_NVMEM_INTERNALS_H
++#define _LINUX_NVMEM_INTERNALS_H
++
++#include <linux/device.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/nvmem-provider.h>
++
++struct nvmem_device {
++	struct module		*owner;
++	struct device		dev;
++	struct list_head	node;
++	int			stride;
++	int			word_size;
++	int			id;
++	struct kref		refcnt;
++	size_t			size;
++	bool			read_only;
++	bool			root_only;
++	int			flags;
++	enum nvmem_type		type;
++	struct bin_attribute	eeprom;
++	struct device		*base_dev;
++	struct list_head	cells;
++	const struct nvmem_keepout *keepout;
++	unsigned int		nkeepout;
++	nvmem_reg_read_t	reg_read;
++	nvmem_reg_write_t	reg_write;
++	struct gpio_desc	*wp_gpio;
++	struct nvmem_layout	*layout;
++	void *priv;
++};
++
++#endif  /* ifndef _LINUX_NVMEM_INTERNALS_H */
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0003-nvmem-Simplify-the-add_cells-hook.patch b/target/linux/generic/backport-5.15/834-v6.8-0003-nvmem-Simplify-the-add_cells-hook.patch
new file mode 100644
index 00000000000..db2d8c1b46e
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0003-nvmem-Simplify-the-add_cells-hook.patch
@@ -0,0 +1,79 @@
+From 1b7c298a4ecbc28cc6ee94005734bff55eb83d22 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:30 +0000
+Subject: [PATCH] nvmem: Simplify the ->add_cells() hook
+
+The layout entry is not used and will anyway be made useless by the new
+layout bus infrastructure coming next, so drop it. While at it, clarify
+the kdoc entry.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-5-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c             | 2 +-
+ drivers/nvmem/layouts/onie-tlv.c | 3 +--
+ drivers/nvmem/layouts/sl28vpd.c  | 3 +--
+ include/linux/nvmem-provider.h   | 8 +++-----
+ 4 files changed, 6 insertions(+), 10 deletions(-)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -817,7 +817,7 @@ static int nvmem_add_cells_from_layout(s
+ 	int ret;
+ 
+ 	if (layout && layout->add_cells) {
+-		ret = layout->add_cells(&nvmem->dev, nvmem, layout);
++		ret = layout->add_cells(&nvmem->dev, nvmem);
+ 		if (ret)
+ 			return ret;
+ 	}
+--- a/drivers/nvmem/layouts/onie-tlv.c
++++ b/drivers/nvmem/layouts/onie-tlv.c
+@@ -182,8 +182,7 @@ static bool onie_tlv_crc_is_valid(struct
+ 	return true;
+ }
+ 
+-static int onie_tlv_parse_table(struct device *dev, struct nvmem_device *nvmem,
+-				struct nvmem_layout *layout)
++static int onie_tlv_parse_table(struct device *dev, struct nvmem_device *nvmem)
+ {
+ 	struct onie_tlv_hdr hdr;
+ 	size_t table_len, data_len, hdr_len;
+--- a/drivers/nvmem/layouts/sl28vpd.c
++++ b/drivers/nvmem/layouts/sl28vpd.c
+@@ -80,8 +80,7 @@ static int sl28vpd_v1_check_crc(struct d
+ 	return 0;
+ }
+ 
+-static int sl28vpd_add_cells(struct device *dev, struct nvmem_device *nvmem,
+-			     struct nvmem_layout *layout)
++static int sl28vpd_add_cells(struct device *dev, struct nvmem_device *nvmem)
+ {
+ 	const struct nvmem_cell_info *pinfo;
+ 	struct nvmem_cell_info info = {0};
+--- a/include/linux/nvmem-provider.h
++++ b/include/linux/nvmem-provider.h
+@@ -156,9 +156,8 @@ struct nvmem_cell_table {
+  *
+  * @name:		Layout name.
+  * @of_match_table:	Open firmware match table.
+- * @add_cells:		Will be called if a nvmem device is found which
+- *			has this layout. The function will add layout
+- *			specific cells with nvmem_add_one_cell().
++ * @add_cells:		Called to populate the layout using
++ *			nvmem_add_one_cell().
+  * @fixup_cell_info:	Will be called before a cell is added. Can be
+  *			used to modify the nvmem_cell_info.
+  * @owner:		Pointer to struct module.
+@@ -172,8 +171,7 @@ struct nvmem_cell_table {
+ struct nvmem_layout {
+ 	const char *name;
+ 	const struct of_device_id *of_match_table;
+-	int (*add_cells)(struct device *dev, struct nvmem_device *nvmem,
+-			 struct nvmem_layout *layout);
++	int (*add_cells)(struct device *dev, struct nvmem_device *nvmem);
+ 	void (*fixup_cell_info)(struct nvmem_device *nvmem,
+ 				struct nvmem_layout *layout,
+ 				struct nvmem_cell_info *cell);
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0004-nvmem-Move-and-rename-fixup_cell_info.patch b/target/linux/generic/backport-5.15/834-v6.8-0004-nvmem-Move-and-rename-fixup_cell_info.patch
new file mode 100644
index 00000000000..65aa37f8344
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0004-nvmem-Move-and-rename-fixup_cell_info.patch
@@ -0,0 +1,169 @@
+From 1172460e716784ac7e1049a537bdca8edbf97360 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:31 +0000
+Subject: [PATCH] nvmem: Move and rename ->fixup_cell_info()
+
+This hook is meant to be used by any provider and instantiating a layout
+just for this is useless. Let's instead move this hook to the nvmem
+device and add it to the config structure to be easily shared by the
+providers.
+
+While at moving this hook, rename it ->fixup_dt_cell_info() to clarify
+its main intended purpose.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-6-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c           |  6 +++---
+ drivers/nvmem/imx-ocotp.c      | 11 +++--------
+ drivers/nvmem/internals.h      |  2 ++
+ drivers/nvmem/mtk-efuse.c      | 11 +++--------
+ include/linux/nvmem-provider.h |  9 ++++-----
+ 5 files changed, 15 insertions(+), 24 deletions(-)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -676,7 +676,6 @@ static int nvmem_validate_keepouts(struc
+ 
+ static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np)
+ {
+-	struct nvmem_layout *layout = nvmem->layout;
+ 	struct device *dev = &nvmem->dev;
+ 	struct device_node *child;
+ 	const __be32 *addr;
+@@ -706,8 +705,8 @@ static int nvmem_add_cells_from_dt(struc
+ 
+ 		info.np = of_node_get(child);
+ 
+-		if (layout && layout->fixup_cell_info)
+-			layout->fixup_cell_info(nvmem, layout, &info);
++		if (nvmem->fixup_dt_cell_info)
++			nvmem->fixup_dt_cell_info(nvmem, &info);
+ 
+ 		ret = nvmem_add_one_cell(nvmem, &info);
+ 		kfree(info.name);
+@@ -896,6 +895,7 @@ struct nvmem_device *nvmem_register(cons
+ 
+ 	kref_init(&nvmem->refcnt);
+ 	INIT_LIST_HEAD(&nvmem->cells);
++	nvmem->fixup_dt_cell_info = config->fixup_dt_cell_info;
+ 
+ 	nvmem->owner = config->owner;
+ 	if (!nvmem->owner && config->dev->driver)
+--- a/drivers/nvmem/imx-ocotp.c
++++ b/drivers/nvmem/imx-ocotp.c
+@@ -584,17 +584,12 @@ static const struct of_device_id imx_oco
+ };
+ MODULE_DEVICE_TABLE(of, imx_ocotp_dt_ids);
+ 
+-static void imx_ocotp_fixup_cell_info(struct nvmem_device *nvmem,
+-				      struct nvmem_layout *layout,
+-				      struct nvmem_cell_info *cell)
++static void imx_ocotp_fixup_dt_cell_info(struct nvmem_device *nvmem,
++					 struct nvmem_cell_info *cell)
+ {
+ 	cell->read_post_process = imx_ocotp_cell_pp;
+ }
+ 
+-static struct nvmem_layout imx_ocotp_layout = {
+-	.fixup_cell_info = imx_ocotp_fixup_cell_info,
+-};
+-
+ static int imx_ocotp_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -620,7 +615,7 @@ static int imx_ocotp_probe(struct platfo
+ 	imx_ocotp_nvmem_config.size = 4 * priv->params->nregs;
+ 	imx_ocotp_nvmem_config.dev = dev;
+ 	imx_ocotp_nvmem_config.priv = priv;
+-	imx_ocotp_nvmem_config.layout = &imx_ocotp_layout;
++	imx_ocotp_nvmem_config.fixup_dt_cell_info = &imx_ocotp_fixup_dt_cell_info;
+ 
+ 	priv->config = &imx_ocotp_nvmem_config;
+ 
+--- a/drivers/nvmem/internals.h
++++ b/drivers/nvmem/internals.h
+@@ -23,6 +23,8 @@ struct nvmem_device {
+ 	struct bin_attribute	eeprom;
+ 	struct device		*base_dev;
+ 	struct list_head	cells;
++	void (*fixup_dt_cell_info)(struct nvmem_device *nvmem,
++				   struct nvmem_cell_info *cell);
+ 	const struct nvmem_keepout *keepout;
+ 	unsigned int		nkeepout;
+ 	nvmem_reg_read_t	reg_read;
+--- a/drivers/nvmem/mtk-efuse.c
++++ b/drivers/nvmem/mtk-efuse.c
+@@ -45,9 +45,8 @@ static int mtk_efuse_gpu_speedbin_pp(voi
+ 	return 0;
+ }
+ 
+-static void mtk_efuse_fixup_cell_info(struct nvmem_device *nvmem,
+-				      struct nvmem_layout *layout,
+-				      struct nvmem_cell_info *cell)
++static void mtk_efuse_fixup_dt_cell_info(struct nvmem_device *nvmem,
++					 struct nvmem_cell_info *cell)
+ {
+ 	size_t sz = strlen(cell->name);
+ 
+@@ -61,10 +60,6 @@ static void mtk_efuse_fixup_cell_info(st
+ 		cell->read_post_process = mtk_efuse_gpu_speedbin_pp;
+ }
+ 
+-static struct nvmem_layout mtk_efuse_layout = {
+-	.fixup_cell_info = mtk_efuse_fixup_cell_info,
+-};
+-
+ static int mtk_efuse_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+@@ -91,7 +86,7 @@ static int mtk_efuse_probe(struct platfo
+ 	econfig.priv = priv;
+ 	econfig.dev = dev;
+ 	if (pdata->uses_post_processing)
+-		econfig.layout = &mtk_efuse_layout;
++		econfig.fixup_dt_cell_info = &mtk_efuse_fixup_dt_cell_info;
+ 	nvmem = devm_nvmem_register(dev, &econfig);
+ 
+ 	return PTR_ERR_OR_ZERO(nvmem);
+--- a/include/linux/nvmem-provider.h
++++ b/include/linux/nvmem-provider.h
+@@ -83,6 +83,8 @@ struct nvmem_cell_info {
+  * @cells:	Optional array of pre-defined NVMEM cells.
+  * @ncells:	Number of elements in cells.
+  * @add_legacy_fixed_of_cells:	Read fixed NVMEM cells from old OF syntax.
++ * @fixup_dt_cell_info: Will be called before a cell is added. Can be
++ *		used to modify the nvmem_cell_info.
+  * @keepout:	Optional array of keepout ranges (sorted ascending by start).
+  * @nkeepout:	Number of elements in the keepout array.
+  * @type:	Type of the nvmem storage
+@@ -113,6 +115,8 @@ struct nvmem_config {
+ 	const struct nvmem_cell_info	*cells;
+ 	int			ncells;
+ 	bool			add_legacy_fixed_of_cells;
++	void (*fixup_dt_cell_info)(struct nvmem_device *nvmem,
++				   struct nvmem_cell_info *cell);
+ 	const struct nvmem_keepout *keepout;
+ 	unsigned int		nkeepout;
+ 	enum nvmem_type		type;
+@@ -158,8 +162,6 @@ struct nvmem_cell_table {
+  * @of_match_table:	Open firmware match table.
+  * @add_cells:		Called to populate the layout using
+  *			nvmem_add_one_cell().
+- * @fixup_cell_info:	Will be called before a cell is added. Can be
+- *			used to modify the nvmem_cell_info.
+  * @owner:		Pointer to struct module.
+  * @node:		List node.
+  *
+@@ -172,9 +174,6 @@ struct nvmem_layout {
+ 	const char *name;
+ 	const struct of_device_id *of_match_table;
+ 	int (*add_cells)(struct device *dev, struct nvmem_device *nvmem);
+-	void (*fixup_cell_info)(struct nvmem_device *nvmem,
+-				struct nvmem_layout *layout,
+-				struct nvmem_cell_info *cell);
+ 
+ 	/* private */
+ 	struct module *owner;
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0005-nvmem-core-Rework-layouts-to-become-regular-devices.patch b/target/linux/generic/backport-5.15/834-v6.8-0005-nvmem-core-Rework-layouts-to-become-regular-devices.patch
new file mode 100644
index 00000000000..18813323408
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0005-nvmem-core-Rework-layouts-to-become-regular-devices.patch
@@ -0,0 +1,763 @@
+From fc29fd821d9ac2ae3d32a722fac39ce874efb883 Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:32 +0000
+Subject: [PATCH] nvmem: core: Rework layouts to become regular devices
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Current layout support was initially written without modules support in
+mind. When the requirement for module support rose, the existing base
+was improved to adopt modularization support, but kind of a design flaw
+was introduced. With the existing implementation, when a storage device
+registers into NVMEM, the core tries to hook a layout (if any) and
+populates its cells immediately. This means, if the hardware description
+expects a layout to be hooked up, but no driver was provided for that,
+the storage medium will fail to probe and try later from
+scratch. Even if we consider that the hardware description shall be
+correct, we could still probe the storage device (especially if it
+contains the rootfs).
+
+One way to overcome this situation is to consider the layouts as
+devices, and leverage the native notifier mechanism. When a new NVMEM
+device is registered, we can populate its nvmem-layout child, if any,
+and wait for the matching to be done in order to get the cells (the
+waiting can be easily done with the NVMEM notifiers). If the layout
+driver is compiled as a module, it should automatically be loaded. This
+way, there is no strong order to enforce, any NVMEM device creation
+or NVMEM layout driver insertion will be observed as a new event which
+may lead to the creation of additional cells, without disturbing the
+probes with costly (and sometimes endless) deferrals.
+
+In order to achieve that goal we create a new bus for the nvmem-layouts
+with minimal logic to match nvmem-layout devices with nvmem-layout
+drivers. All this infrastructure code is created in the layouts.c file.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Tested-by: Rafał Miłecki <rafal@milecki.pl>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-7-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/Kconfig            |   1 +
+ drivers/nvmem/Makefile           |   2 +
+ drivers/nvmem/core.c             | 170 ++++++++++----------------
+ drivers/nvmem/internals.h        |  21 ++++
+ drivers/nvmem/layouts.c          | 201 +++++++++++++++++++++++++++++++
+ drivers/nvmem/layouts/Kconfig    |   8 ++
+ drivers/nvmem/layouts/onie-tlv.c |  24 +++-
+ drivers/nvmem/layouts/sl28vpd.c  |  24 +++-
+ include/linux/nvmem-provider.h   |  38 +++---
+ 9 files changed, 354 insertions(+), 135 deletions(-)
+ create mode 100644 drivers/nvmem/layouts.c
+
+--- a/drivers/nvmem/Kconfig
++++ b/drivers/nvmem/Kconfig
+@@ -1,6 +1,7 @@
+ # SPDX-License-Identifier: GPL-2.0-only
+ menuconfig NVMEM
+ 	bool "NVMEM Support"
++	imply NVMEM_LAYOUTS
+ 	help
+ 	  Support for NVMEM(Non Volatile Memory) devices like EEPROM, EFUSES...
+ 
+--- a/drivers/nvmem/Makefile
++++ b/drivers/nvmem/Makefile
+@@ -5,6 +5,8 @@
+ 
+ obj-$(CONFIG_NVMEM)		+= nvmem_core.o
+ nvmem_core-y			:= core.o
++obj-$(CONFIG_NVMEM_LAYOUTS)	+= nvmem_layouts.o
++nvmem_layouts-y			:= layouts.o
+ obj-y				+= layouts/
+ 
+ # Devices
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -56,9 +56,6 @@ static LIST_HEAD(nvmem_lookup_list);
+ 
+ static BLOCKING_NOTIFIER_HEAD(nvmem_notifier);
+ 
+-static DEFINE_SPINLOCK(nvmem_layout_lock);
+-static LIST_HEAD(nvmem_layouts);
+-
+ static int __nvmem_reg_read(struct nvmem_device *nvmem, unsigned int offset,
+ 			    void *val, size_t bytes)
+ {
+@@ -741,97 +738,22 @@ static int nvmem_add_cells_from_fixed_la
+ 	return err;
+ }
+ 
+-int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner)
++int nvmem_layout_register(struct nvmem_layout *layout)
+ {
+-	layout->owner = owner;
+-
+-	spin_lock(&nvmem_layout_lock);
+-	list_add(&layout->node, &nvmem_layouts);
+-	spin_unlock(&nvmem_layout_lock);
+-
+-	blocking_notifier_call_chain(&nvmem_notifier, NVMEM_LAYOUT_ADD, layout);
++	if (!layout->add_cells)
++		return -EINVAL;
+ 
+-	return 0;
++	/* Populate the cells */
++	return layout->add_cells(&layout->nvmem->dev, layout->nvmem);
+ }
+-EXPORT_SYMBOL_GPL(__nvmem_layout_register);
++EXPORT_SYMBOL_GPL(nvmem_layout_register);
+ 
+ void nvmem_layout_unregister(struct nvmem_layout *layout)
+ {
+-	blocking_notifier_call_chain(&nvmem_notifier, NVMEM_LAYOUT_REMOVE, layout);
+-
+-	spin_lock(&nvmem_layout_lock);
+-	list_del(&layout->node);
+-	spin_unlock(&nvmem_layout_lock);
++	/* Keep the API even with an empty stub in case we need it later */
+ }
+ EXPORT_SYMBOL_GPL(nvmem_layout_unregister);
+ 
+-static struct nvmem_layout *nvmem_layout_get(struct nvmem_device *nvmem)
+-{
+-	struct device_node *layout_np;
+-	struct nvmem_layout *l, *layout = ERR_PTR(-EPROBE_DEFER);
+-
+-	layout_np = of_nvmem_layout_get_container(nvmem);
+-	if (!layout_np)
+-		return NULL;
+-
+-	/* Fixed layouts don't have a matching driver */
+-	if (of_device_is_compatible(layout_np, "fixed-layout")) {
+-		of_node_put(layout_np);
+-		return NULL;
+-	}
+-
+-	/*
+-	 * In case the nvmem device was built-in while the layout was built as a
+-	 * module, we shall manually request the layout driver loading otherwise
+-	 * we'll never have any match.
+-	 */
+-	of_request_module(layout_np);
+-
+-	spin_lock(&nvmem_layout_lock);
+-
+-	list_for_each_entry(l, &nvmem_layouts, node) {
+-		if (of_match_node(l->of_match_table, layout_np)) {
+-			if (try_module_get(l->owner))
+-				layout = l;
+-
+-			break;
+-		}
+-	}
+-
+-	spin_unlock(&nvmem_layout_lock);
+-	of_node_put(layout_np);
+-
+-	return layout;
+-}
+-
+-static void nvmem_layout_put(struct nvmem_layout *layout)
+-{
+-	if (layout)
+-		module_put(layout->owner);
+-}
+-
+-static int nvmem_add_cells_from_layout(struct nvmem_device *nvmem)
+-{
+-	struct nvmem_layout *layout = nvmem->layout;
+-	int ret;
+-
+-	if (layout && layout->add_cells) {
+-		ret = layout->add_cells(&nvmem->dev, nvmem);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	return 0;
+-}
+-
+-#if IS_ENABLED(CONFIG_OF)
+-struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem)
+-{
+-	return of_get_child_by_name(nvmem->dev.of_node, "nvmem-layout");
+-}
+-EXPORT_SYMBOL_GPL(of_nvmem_layout_get_container);
+-#endif
+-
+ const void *nvmem_layout_get_match_data(struct nvmem_device *nvmem,
+ 					struct nvmem_layout *layout)
+ {
+@@ -839,7 +761,7 @@ const void *nvmem_layout_get_match_data(
+ 	const struct of_device_id *match;
+ 
+ 	layout_np = of_nvmem_layout_get_container(nvmem);
+-	match = of_match_node(layout->of_match_table, layout_np);
++	match = of_match_node(layout->dev.driver->of_match_table, layout_np);
+ 
+ 	return match ? match->data : NULL;
+ }
+@@ -951,19 +873,6 @@ struct nvmem_device *nvmem_register(cons
+ 			goto err_put_device;
+ 	}
+ 
+-	/*
+-	 * If the driver supplied a layout by config->layout, the module
+-	 * pointer will be NULL and nvmem_layout_put() will be a noop.
+-	 */
+-	nvmem->layout = config->layout ?: nvmem_layout_get(nvmem);
+-	if (IS_ERR(nvmem->layout)) {
+-		rval = PTR_ERR(nvmem->layout);
+-		nvmem->layout = NULL;
+-
+-		if (rval == -EPROBE_DEFER)
+-			goto err_teardown_compat;
+-	}
+-
+ 	if (config->cells) {
+ 		rval = nvmem_add_cells(nvmem, config->cells, config->ncells);
+ 		if (rval)
+@@ -984,24 +893,24 @@ struct nvmem_device *nvmem_register(cons
+ 	if (rval)
+ 		goto err_remove_cells;
+ 
+-	rval = nvmem_add_cells_from_layout(nvmem);
+-	if (rval)
+-		goto err_remove_cells;
+-
+ 	dev_dbg(&nvmem->dev, "Registering nvmem device %s\n", config->name);
+ 
+ 	rval = device_add(&nvmem->dev);
+ 	if (rval)
+ 		goto err_remove_cells;
+ 
++	rval = nvmem_populate_layout(nvmem);
++	if (rval)
++		goto err_remove_dev;
++
+ 	blocking_notifier_call_chain(&nvmem_notifier, NVMEM_ADD, nvmem);
+ 
+ 	return nvmem;
+ 
++err_remove_dev:
++	device_del(&nvmem->dev);
+ err_remove_cells:
+ 	nvmem_device_remove_all_cells(nvmem);
+-	nvmem_layout_put(nvmem->layout);
+-err_teardown_compat:
+ 	if (config->compat)
+ 		nvmem_sysfs_remove_compat(nvmem, config);
+ err_put_device:
+@@ -1023,7 +932,7 @@ static void nvmem_device_release(struct
+ 		device_remove_bin_file(nvmem->base_dev, &nvmem->eeprom);
+ 
+ 	nvmem_device_remove_all_cells(nvmem);
+-	nvmem_layout_put(nvmem->layout);
++	nvmem_destroy_layout(nvmem);
+ 	device_unregister(&nvmem->dev);
+ }
+ 
+@@ -1325,6 +1234,12 @@ nvmem_cell_get_from_lookup(struct device
+ 	return cell;
+ }
+ 
++static void nvmem_layout_module_put(struct nvmem_device *nvmem)
++{
++	if (nvmem->layout && nvmem->layout->dev.driver)
++		module_put(nvmem->layout->dev.driver->owner);
++}
++
+ #if IS_ENABLED(CONFIG_OF)
+ static struct nvmem_cell_entry *
+ nvmem_find_cell_entry_by_node(struct nvmem_device *nvmem, struct device_node *np)
+@@ -1343,6 +1258,18 @@ nvmem_find_cell_entry_by_node(struct nvm
+ 	return cell;
+ }
+ 
++static int nvmem_layout_module_get_optional(struct nvmem_device *nvmem)
++{
++	if (!nvmem->layout)
++		return 0;
++
++	if (!nvmem->layout->dev.driver ||
++	    !try_module_get(nvmem->layout->dev.driver->owner))
++		return -EPROBE_DEFER;
++
++	return 0;
++}
++
+ /**
+  * of_nvmem_cell_get() - Get a nvmem cell from given device node and cell id
+  *
+@@ -1405,16 +1332,29 @@ struct nvmem_cell *of_nvmem_cell_get(str
+ 		return ERR_CAST(nvmem);
+ 	}
+ 
++	ret = nvmem_layout_module_get_optional(nvmem);
++	if (ret) {
++		of_node_put(cell_np);
++		__nvmem_device_put(nvmem);
++		return ERR_PTR(ret);
++	}
++
+ 	cell_entry = nvmem_find_cell_entry_by_node(nvmem, cell_np);
+ 	of_node_put(cell_np);
+ 	if (!cell_entry) {
+ 		__nvmem_device_put(nvmem);
+-		return ERR_PTR(-ENOENT);
++		nvmem_layout_module_put(nvmem);
++		if (nvmem->layout)
++			return ERR_PTR(-EPROBE_DEFER);
++		else
++			return ERR_PTR(-ENOENT);
+ 	}
+ 
+ 	cell = nvmem_create_cell(cell_entry, id, cell_index);
+-	if (IS_ERR(cell))
++	if (IS_ERR(cell)) {
+ 		__nvmem_device_put(nvmem);
++		nvmem_layout_module_put(nvmem);
++	}
+ 
+ 	return cell;
+ }
+@@ -1528,6 +1468,7 @@ void nvmem_cell_put(struct nvmem_cell *c
+ 
+ 	kfree(cell);
+ 	__nvmem_device_put(nvmem);
++	nvmem_layout_module_put(nvmem);
+ }
+ EXPORT_SYMBOL_GPL(nvmem_cell_put);
+ 
+@@ -2105,11 +2046,22 @@ EXPORT_SYMBOL_GPL(nvmem_dev_name);
+ 
+ static int __init nvmem_init(void)
+ {
+-	return bus_register(&nvmem_bus_type);
++	int ret;
++
++	ret = bus_register(&nvmem_bus_type);
++	if (ret)
++		return ret;
++
++	ret = nvmem_layout_bus_register();
++	if (ret)
++		bus_unregister(&nvmem_bus_type);
++
++	return ret;
+ }
+ 
+ static void __exit nvmem_exit(void)
+ {
++	nvmem_layout_bus_unregister();
+ 	bus_unregister(&nvmem_bus_type);
+ }
+ 
+--- a/drivers/nvmem/internals.h
++++ b/drivers/nvmem/internals.h
+@@ -34,4 +34,25 @@ struct nvmem_device {
+ 	void *priv;
+ };
+ 
++#if IS_ENABLED(CONFIG_OF)
++int nvmem_layout_bus_register(void);
++void nvmem_layout_bus_unregister(void);
++int nvmem_populate_layout(struct nvmem_device *nvmem);
++void nvmem_destroy_layout(struct nvmem_device *nvmem);
++#else /* CONFIG_OF */
++static inline int nvmem_layout_bus_register(void)
++{
++	return 0;
++}
++
++static inline void nvmem_layout_bus_unregister(void) {}
++
++static inline int nvmem_populate_layout(struct nvmem_device *nvmem)
++{
++	return 0;
++}
++
++static inline void nvmem_destroy_layout(struct nvmem_device *nvmem) { }
++#endif /* CONFIG_OF */
++
+ #endif  /* ifndef _LINUX_NVMEM_INTERNALS_H */
+--- /dev/null
++++ b/drivers/nvmem/layouts.c
+@@ -0,0 +1,201 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * NVMEM layout bus handling
++ *
++ * Copyright (C) 2023 Bootlin
++ * Author: Miquel Raynal <miquel.raynal@bootlin.com
++ */
++
++#include <linux/device.h>
++#include <linux/dma-mapping.h>
++#include <linux/nvmem-consumer.h>
++#include <linux/nvmem-provider.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_irq.h>
++
++#include "internals.h"
++
++#define to_nvmem_layout_driver(drv) \
++	(container_of((drv), struct nvmem_layout_driver, driver))
++#define to_nvmem_layout_device(_dev) \
++	container_of((_dev), struct nvmem_layout, dev)
++
++static int nvmem_layout_bus_match(struct device *dev, struct device_driver *drv)
++{
++	return of_driver_match_device(dev, drv);
++}
++
++static int nvmem_layout_bus_probe(struct device *dev)
++{
++	struct nvmem_layout_driver *drv = to_nvmem_layout_driver(dev->driver);
++	struct nvmem_layout *layout = to_nvmem_layout_device(dev);
++
++	if (!drv->probe || !drv->remove)
++		return -EINVAL;
++
++	return drv->probe(layout);
++}
++
++static void nvmem_layout_bus_remove(struct device *dev)
++{
++	struct nvmem_layout_driver *drv = to_nvmem_layout_driver(dev->driver);
++	struct nvmem_layout *layout = to_nvmem_layout_device(dev);
++
++	return drv->remove(layout);
++}
++
++static struct bus_type nvmem_layout_bus_type = {
++	.name		= "nvmem-layout",
++	.match		= nvmem_layout_bus_match,
++	.probe		= nvmem_layout_bus_probe,
++	.remove		= nvmem_layout_bus_remove,
++};
++
++int nvmem_layout_driver_register(struct nvmem_layout_driver *drv)
++{
++	drv->driver.bus = &nvmem_layout_bus_type;
++
++	return driver_register(&drv->driver);
++}
++EXPORT_SYMBOL_GPL(nvmem_layout_driver_register);
++
++void nvmem_layout_driver_unregister(struct nvmem_layout_driver *drv)
++{
++	driver_unregister(&drv->driver);
++}
++EXPORT_SYMBOL_GPL(nvmem_layout_driver_unregister);
++
++static void nvmem_layout_release_device(struct device *dev)
++{
++	struct nvmem_layout *layout = to_nvmem_layout_device(dev);
++
++	of_node_put(layout->dev.of_node);
++	kfree(layout);
++}
++
++static int nvmem_layout_create_device(struct nvmem_device *nvmem,
++				      struct device_node *np)
++{
++	struct nvmem_layout *layout;
++	struct device *dev;
++	int ret;
++
++	layout = kzalloc(sizeof(*layout), GFP_KERNEL);
++	if (!layout)
++		return -ENOMEM;
++
++	/* Create a bidirectional link */
++	layout->nvmem = nvmem;
++	nvmem->layout = layout;
++
++	/* Device model registration */
++	dev = &layout->dev;
++	device_initialize(dev);
++	dev->parent = &nvmem->dev;
++	dev->bus = &nvmem_layout_bus_type;
++	dev->release = nvmem_layout_release_device;
++	dev->coherent_dma_mask = DMA_BIT_MASK(32);
++	dev->dma_mask = &dev->coherent_dma_mask;
++	device_set_node(dev, of_fwnode_handle(of_node_get(np)));
++	of_device_make_bus_id(dev);
++	of_msi_configure(dev, dev->of_node);
++
++	ret = device_add(dev);
++	if (ret) {
++		put_device(dev);
++		return ret;
++	}
++
++	return 0;
++}
++
++static const struct of_device_id of_nvmem_layout_skip_table[] = {
++	{ .compatible = "fixed-layout", },
++	{}
++};
++
++static int nvmem_layout_bus_populate(struct nvmem_device *nvmem,
++				     struct device_node *layout_dn)
++{
++	int ret;
++
++	/* Make sure it has a compatible property */
++	if (!of_get_property(layout_dn, "compatible", NULL)) {
++		pr_debug("%s() - skipping %pOF, no compatible prop\n",
++			 __func__, layout_dn);
++		return 0;
++	}
++
++	/* Fixed layouts are parsed manually somewhere else for now */
++	if (of_match_node(of_nvmem_layout_skip_table, layout_dn)) {
++		pr_debug("%s() - skipping %pOF node\n", __func__, layout_dn);
++		return 0;
++	}
++
++	if (of_node_check_flag(layout_dn, OF_POPULATED_BUS)) {
++		pr_debug("%s() - skipping %pOF, already populated\n",
++			 __func__, layout_dn);
++
++		return 0;
++	}
++
++	/* NVMEM layout buses expect only a single device representing the layout */
++	ret = nvmem_layout_create_device(nvmem, layout_dn);
++	if (ret)
++		return ret;
++
++	of_node_set_flag(layout_dn, OF_POPULATED_BUS);
++
++	return 0;
++}
++
++struct device_node *of_nvmem_layout_get_container(struct nvmem_device *nvmem)
++{
++	return of_get_child_by_name(nvmem->dev.of_node, "nvmem-layout");
++}
++EXPORT_SYMBOL_GPL(of_nvmem_layout_get_container);
++
++/*
++ * Returns the number of devices populated, 0 if the operation was not relevant
++ * for this nvmem device, an error code otherwise.
++ */
++int nvmem_populate_layout(struct nvmem_device *nvmem)
++{
++	struct device_node *layout_dn;
++	int ret;
++
++	layout_dn = of_nvmem_layout_get_container(nvmem);
++	if (!layout_dn)
++		return 0;
++
++	/* Populate the layout device */
++	device_links_supplier_sync_state_pause();
++	ret = nvmem_layout_bus_populate(nvmem, layout_dn);
++	device_links_supplier_sync_state_resume();
++
++	of_node_put(layout_dn);
++	return ret;
++}
++
++void nvmem_destroy_layout(struct nvmem_device *nvmem)
++{
++	struct device *dev;
++
++	if (!nvmem->layout)
++		return;
++
++	dev = &nvmem->layout->dev;
++	of_node_clear_flag(dev->of_node, OF_POPULATED_BUS);
++	device_unregister(dev);
++}
++
++int nvmem_layout_bus_register(void)
++{
++	return bus_register(&nvmem_layout_bus_type);
++}
++
++void nvmem_layout_bus_unregister(void)
++{
++	bus_unregister(&nvmem_layout_bus_type);
++}
+--- a/drivers/nvmem/layouts/Kconfig
++++ b/drivers/nvmem/layouts/Kconfig
+@@ -1,5 +1,11 @@
+ # SPDX-License-Identifier: GPL-2.0
+ 
++config NVMEM_LAYOUTS
++	bool
++	depends on OF
++
++if NVMEM_LAYOUTS
++
+ menu "Layout Types"
+ 
+ config NVMEM_LAYOUT_SL28_VPD
+@@ -21,3 +27,5 @@ config NVMEM_LAYOUT_ONIE_TLV
+ 	  If unsure, say N.
+ 
+ endmenu
++
++endif
+--- a/drivers/nvmem/layouts/onie-tlv.c
++++ b/drivers/nvmem/layouts/onie-tlv.c
+@@ -225,16 +225,32 @@ static int onie_tlv_parse_table(struct d
+ 	return 0;
+ }
+ 
++static int onie_tlv_probe(struct nvmem_layout *layout)
++{
++	layout->add_cells = onie_tlv_parse_table;
++
++	return nvmem_layout_register(layout);
++}
++
++static void onie_tlv_remove(struct nvmem_layout *layout)
++{
++	nvmem_layout_unregister(layout);
++}
++
+ static const struct of_device_id onie_tlv_of_match_table[] = {
+ 	{ .compatible = "onie,tlv-layout", },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, onie_tlv_of_match_table);
+ 
+-static struct nvmem_layout onie_tlv_layout = {
+-	.name = "ONIE tlv layout",
+-	.of_match_table = onie_tlv_of_match_table,
+-	.add_cells = onie_tlv_parse_table,
++static struct nvmem_layout_driver onie_tlv_layout = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "onie-tlv-layout",
++		.of_match_table = onie_tlv_of_match_table,
++	},
++	.probe = onie_tlv_probe,
++	.remove = onie_tlv_remove,
+ };
+ module_nvmem_layout_driver(onie_tlv_layout);
+ 
+--- a/drivers/nvmem/layouts/sl28vpd.c
++++ b/drivers/nvmem/layouts/sl28vpd.c
+@@ -134,16 +134,32 @@ static int sl28vpd_add_cells(struct devi
+ 	return 0;
+ }
+ 
++static int sl28vpd_probe(struct nvmem_layout *layout)
++{
++	layout->add_cells = sl28vpd_add_cells;
++
++	return nvmem_layout_register(layout);
++}
++
++static void sl28vpd_remove(struct nvmem_layout *layout)
++{
++	nvmem_layout_unregister(layout);
++}
++
+ static const struct of_device_id sl28vpd_of_match_table[] = {
+ 	{ .compatible = "kontron,sl28-vpd" },
+ 	{},
+ };
+ MODULE_DEVICE_TABLE(of, sl28vpd_of_match_table);
+ 
+-static struct nvmem_layout sl28vpd_layout = {
+-	.name = "sl28-vpd",
+-	.of_match_table = sl28vpd_of_match_table,
+-	.add_cells = sl28vpd_add_cells,
++static struct nvmem_layout_driver sl28vpd_layout = {
++	.driver = {
++		.owner = THIS_MODULE,
++		.name = "kontron-sl28vpd-layout",
++		.of_match_table = sl28vpd_of_match_table,
++	},
++	.probe = sl28vpd_probe,
++	.remove = sl28vpd_remove,
+ };
+ module_nvmem_layout_driver(sl28vpd_layout);
+ 
+--- a/include/linux/nvmem-provider.h
++++ b/include/linux/nvmem-provider.h
+@@ -9,6 +9,7 @@
+ #ifndef _LINUX_NVMEM_PROVIDER_H
+ #define _LINUX_NVMEM_PROVIDER_H
+ 
++#include <linux/device.h>
+ #include <linux/device/driver.h>
+ #include <linux/err.h>
+ #include <linux/errno.h>
+@@ -158,12 +159,11 @@ struct nvmem_cell_table {
+ /**
+  * struct nvmem_layout - NVMEM layout definitions
+  *
+- * @name:		Layout name.
+- * @of_match_table:	Open firmware match table.
+- * @add_cells:		Called to populate the layout using
+- *			nvmem_add_one_cell().
+- * @owner:		Pointer to struct module.
+- * @node:		List node.
++ * @dev:		Device-model layout device.
++ * @nvmem:		The underlying NVMEM device
++ * @add_cells:		Will be called if a nvmem device is found which
++ *			has this layout. The function will add layout
++ *			specific cells with nvmem_add_one_cell().
+  *
+  * A nvmem device can hold a well defined structure which can just be
+  * evaluated during runtime. For example a TLV list, or a list of "name=val"
+@@ -171,13 +171,15 @@ struct nvmem_cell_table {
+  * cells.
+  */
+ struct nvmem_layout {
+-	const char *name;
+-	const struct of_device_id *of_match_table;
++	struct device dev;
++	struct nvmem_device *nvmem;
+ 	int (*add_cells)(struct device *dev, struct nvmem_device *nvmem);
++};
+ 
+-	/* private */
+-	struct module *owner;
+-	struct list_head node;
++struct nvmem_layout_driver {
++	struct device_driver driver;
++	int (*probe)(struct nvmem_layout *layout);
++	void (*remove)(struct nvmem_layout *layout);
+ };
+ 
+ #if IS_ENABLED(CONFIG_NVMEM)
+@@ -194,11 +196,15 @@ void nvmem_del_cell_table(struct nvmem_c
+ int nvmem_add_one_cell(struct nvmem_device *nvmem,
+ 		       const struct nvmem_cell_info *info);
+ 
+-int __nvmem_layout_register(struct nvmem_layout *layout, struct module *owner);
+-#define nvmem_layout_register(layout) \
+-	__nvmem_layout_register(layout, THIS_MODULE)
++int nvmem_layout_register(struct nvmem_layout *layout);
+ void nvmem_layout_unregister(struct nvmem_layout *layout);
+ 
++int nvmem_layout_driver_register(struct nvmem_layout_driver *drv);
++void nvmem_layout_driver_unregister(struct nvmem_layout_driver *drv);
++#define module_nvmem_layout_driver(__nvmem_layout_driver)		\
++	module_driver(__nvmem_layout_driver, nvmem_layout_driver_register, \
++		      nvmem_layout_driver_unregister)
++
+ const void *nvmem_layout_get_match_data(struct nvmem_device *nvmem,
+ 					struct nvmem_layout *layout);
+ 
+@@ -262,8 +268,4 @@ static inline struct device_node *of_nvm
+ 
+ #endif /* CONFIG_NVMEM && CONFIG_OF */
+ 
+-#define module_nvmem_layout_driver(__layout_driver)		\
+-	module_driver(__layout_driver, nvmem_layout_register,	\
+-		      nvmem_layout_unregister)
+-
+ #endif  /* ifndef _LINUX_NVMEM_PROVIDER_H */
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0006-nvmem-core-Expose-cells-through-sysfs.patch b/target/linux/generic/backport-5.15/834-v6.8-0006-nvmem-core-Expose-cells-through-sysfs.patch
new file mode 100644
index 00000000000..89872bec2e5
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0006-nvmem-core-Expose-cells-through-sysfs.patch
@@ -0,0 +1,240 @@
+From 0331c611949fffdf486652450901a4dc52bc5cca Mon Sep 17 00:00:00 2001
+From: Miquel Raynal <miquel.raynal@bootlin.com>
+Date: Fri, 15 Dec 2023 11:15:34 +0000
+Subject: [PATCH] nvmem: core: Expose cells through sysfs
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The binary content of nvmem devices is available to the user so in the
+easiest cases, finding the content of a cell is rather easy as it is
+just a matter of looking at a known and fixed offset. However, nvmem
+layouts have been recently introduced to cope with more advanced
+situations, where the offset and size of the cells is not known in
+advance or is dynamic. When using layouts, more advanced parsers are
+used by the kernel in order to give direct access to the content of each
+cell, regardless of its position/size in the underlying
+device. Unfortunately, these information are not accessible by users,
+unless by fully re-implementing the parser logic in userland.
+
+Let's expose the cells and their content through sysfs to avoid these
+situations. Of course the relevant NVMEM sysfs Kconfig option must be
+enabled for this support to be available.
+
+Not all nvmem devices expose cells. Indeed, the .bin_attrs attribute
+group member will be filled at runtime only when relevant and will
+remain empty otherwise. In this case, as the cells attribute group will
+be empty, it will not lead to any additional folder/file creation.
+
+Exposed cells are read-only. There is, in practice, everything in the
+core to support a write path, but as I don't see any need for that, I
+prefer to keep the interface simple (and probably safer). The interface
+is documented as being in the "testing" state which means we can later
+add a write attribute if though relevant.
+
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Tested-by: Rafał Miłecki <rafal@milecki.pl>
+Tested-by: Chen-Yu Tsai <wenst@chromium.org>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-9-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c      | 135 +++++++++++++++++++++++++++++++++++++-
+ drivers/nvmem/internals.h |   1 +
+ 2 files changed, 135 insertions(+), 1 deletion(-)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -300,6 +300,43 @@ static umode_t nvmem_bin_attr_is_visible
+ 	return nvmem_bin_attr_get_umode(nvmem);
+ }
+ 
++static struct nvmem_cell *nvmem_create_cell(struct nvmem_cell_entry *entry,
++					    const char *id, int index);
++
++static ssize_t nvmem_cell_attr_read(struct file *filp, struct kobject *kobj,
++				    struct bin_attribute *attr, char *buf,
++				    loff_t pos, size_t count)
++{
++	struct nvmem_cell_entry *entry;
++	struct nvmem_cell *cell = NULL;
++	size_t cell_sz, read_len;
++	void *content;
++
++	entry = attr->private;
++	cell = nvmem_create_cell(entry, entry->name, 0);
++	if (IS_ERR(cell))
++		return PTR_ERR(cell);
++
++	if (!cell)
++		return -EINVAL;
++
++	content = nvmem_cell_read(cell, &cell_sz);
++	if (IS_ERR(content)) {
++		read_len = PTR_ERR(content);
++		goto destroy_cell;
++	}
++
++	read_len = min_t(unsigned int, cell_sz - pos, count);
++	memcpy(buf, content + pos, read_len);
++	kfree(content);
++
++destroy_cell:
++	kfree_const(cell->id);
++	kfree(cell);
++
++	return read_len;
++}
++
+ /* default read/write permissions */
+ static struct bin_attribute bin_attr_rw_nvmem = {
+ 	.attr	= {
+@@ -321,11 +358,21 @@ static const struct attribute_group nvme
+ 	.is_bin_visible = nvmem_bin_attr_is_visible,
+ };
+ 
++/* Cell attributes will be dynamically allocated */
++static struct attribute_group nvmem_cells_group = {
++	.name		= "cells",
++};
++
+ static const struct attribute_group *nvmem_dev_groups[] = {
+ 	&nvmem_bin_group,
+ 	NULL,
+ };
+ 
++static const struct attribute_group *nvmem_cells_groups[] = {
++	&nvmem_cells_group,
++	NULL,
++};
++
+ static struct bin_attribute bin_attr_nvmem_eeprom_compat = {
+ 	.attr	= {
+ 		.name	= "eeprom",
+@@ -381,6 +428,68 @@ static void nvmem_sysfs_remove_compat(st
+ 		device_remove_bin_file(nvmem->base_dev, &nvmem->eeprom);
+ }
+ 
++static int nvmem_populate_sysfs_cells(struct nvmem_device *nvmem)
++{
++	struct bin_attribute **cells_attrs, *attrs;
++	struct nvmem_cell_entry *entry;
++	unsigned int ncells = 0, i = 0;
++	int ret = 0;
++
++	mutex_lock(&nvmem_mutex);
++
++	if (list_empty(&nvmem->cells) || nvmem->sysfs_cells_populated) {
++		nvmem_cells_group.bin_attrs = NULL;
++		goto unlock_mutex;
++	}
++
++	/* Allocate an array of attributes with a sentinel */
++	ncells = list_count_nodes(&nvmem->cells);
++	cells_attrs = devm_kcalloc(&nvmem->dev, ncells + 1,
++				   sizeof(struct bin_attribute *), GFP_KERNEL);
++	if (!cells_attrs) {
++		ret = -ENOMEM;
++		goto unlock_mutex;
++	}
++
++	attrs = devm_kcalloc(&nvmem->dev, ncells, sizeof(struct bin_attribute), GFP_KERNEL);
++	if (!attrs) {
++		ret = -ENOMEM;
++		goto unlock_mutex;
++	}
++
++	/* Initialize each attribute to take the name and size of the cell */
++	list_for_each_entry(entry, &nvmem->cells, node) {
++		sysfs_bin_attr_init(&attrs[i]);
++		attrs[i].attr.name = devm_kasprintf(&nvmem->dev, GFP_KERNEL,
++						    "%s@%x", entry->name,
++						    entry->offset);
++		attrs[i].attr.mode = 0444;
++		attrs[i].size = entry->bytes;
++		attrs[i].read = &nvmem_cell_attr_read;
++		attrs[i].private = entry;
++		if (!attrs[i].attr.name) {
++			ret = -ENOMEM;
++			goto unlock_mutex;
++		}
++
++		cells_attrs[i] = &attrs[i];
++		i++;
++	}
++
++	nvmem_cells_group.bin_attrs = cells_attrs;
++
++	ret = devm_device_add_groups(&nvmem->dev, nvmem_cells_groups);
++	if (ret)
++		goto unlock_mutex;
++
++	nvmem->sysfs_cells_populated = true;
++
++unlock_mutex:
++	mutex_unlock(&nvmem_mutex);
++
++	return ret;
++}
++
+ #else /* CONFIG_NVMEM_SYSFS */
+ 
+ static int nvmem_sysfs_setup_compat(struct nvmem_device *nvmem,
+@@ -740,11 +849,25 @@ static int nvmem_add_cells_from_fixed_la
+ 
+ int nvmem_layout_register(struct nvmem_layout *layout)
+ {
++	int ret;
++
+ 	if (!layout->add_cells)
+ 		return -EINVAL;
+ 
+ 	/* Populate the cells */
+-	return layout->add_cells(&layout->nvmem->dev, layout->nvmem);
++	ret = layout->add_cells(&layout->nvmem->dev, layout->nvmem);
++	if (ret)
++		return ret;
++
++#ifdef CONFIG_NVMEM_SYSFS
++	ret = nvmem_populate_sysfs_cells(layout->nvmem);
++	if (ret) {
++		nvmem_device_remove_all_cells(layout->nvmem);
++		return ret;
++	}
++#endif
++
++	return 0;
+ }
+ EXPORT_SYMBOL_GPL(nvmem_layout_register);
+ 
+@@ -903,10 +1026,20 @@ struct nvmem_device *nvmem_register(cons
+ 	if (rval)
+ 		goto err_remove_dev;
+ 
++#ifdef CONFIG_NVMEM_SYSFS
++	rval = nvmem_populate_sysfs_cells(nvmem);
++	if (rval)
++		goto err_destroy_layout;
++#endif
++
+ 	blocking_notifier_call_chain(&nvmem_notifier, NVMEM_ADD, nvmem);
+ 
+ 	return nvmem;
+ 
++#ifdef CONFIG_NVMEM_SYSFS
++err_destroy_layout:
++	nvmem_destroy_layout(nvmem);
++#endif
+ err_remove_dev:
+ 	device_del(&nvmem->dev);
+ err_remove_cells:
+--- a/drivers/nvmem/internals.h
++++ b/drivers/nvmem/internals.h
+@@ -32,6 +32,7 @@ struct nvmem_device {
+ 	struct gpio_desc	*wp_gpio;
+ 	struct nvmem_layout	*layout;
+ 	void *priv;
++	bool			sysfs_cells_populated;
+ };
+ 
+ #if IS_ENABLED(CONFIG_OF)
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0007-nvmem-stm32-add-support-for-STM32MP25-BSEC-to-contro.patch b/target/linux/generic/backport-5.15/834-v6.8-0007-nvmem-stm32-add-support-for-STM32MP25-BSEC-to-contro.patch
new file mode 100644
index 00000000000..f686222f881
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0007-nvmem-stm32-add-support-for-STM32MP25-BSEC-to-contro.patch
@@ -0,0 +1,65 @@
+From f0ac5b23039610619ca4a4805528553ecb6bc815 Mon Sep 17 00:00:00 2001
+From: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Date: Fri, 15 Dec 2023 11:15:36 +0000
+Subject: [PATCH] nvmem: stm32: add support for STM32MP25 BSEC to control OTP
+ data
+
+On STM32MP25, OTP area may be read/written by using BSEC (boot, security
+and OTP control). The BSEC internal peripheral is only managed by the
+secure world.
+
+The 12 Kbits of OTP (effective) are organized into the following regions:
+- lower OTP (OTP0 to OTP127) = 4096 lower OTP bits,
+  bitwise (1-bit) programmable
+- mid OTP (OTP128 to OTP255) = 4096 middle OTP bits,
+  bulk (32-bit) programmable
+- upper OTP (OTP256 to OTP383) = 4096 upper OTP bits,
+  bulk (32-bit) programmable,
+  only accessible when BSEC is in closed state.
+
+As HWKEY and ECIES key are only accessible by ROM code;
+only 368 OTP words are managed in this driver (OTP0 to OTP267).
+
+This patch adds the STM32MP25 configuration for reading and writing
+the OTP data using the OP-TEE BSEC TA services.
+
+Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
+Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
+Link: https://lore.kernel.org/r/20231215111536.316972-11-srinivas.kandagatla@linaro.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/stm32-romem.c | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/drivers/nvmem/stm32-romem.c
++++ b/drivers/nvmem/stm32-romem.c
+@@ -269,6 +269,19 @@ static const struct stm32_romem_cfg stm3
+ 	.ta = true,
+ };
+ 
++/*
++ * STM32MP25 BSEC OTP: 3 regions of 32-bits data words
++ *   lower OTP (OTP0 to OTP127), bitwise (1-bit) programmable
++ *   mid OTP (OTP128 to OTP255), bulk (32-bit) programmable
++ *   upper OTP (OTP256 to OTP383), bulk (32-bit) programmable
++ *              but no access to HWKEY and ECIES key: limited at OTP367
++ */
++static const struct stm32_romem_cfg stm32mp25_bsec_cfg = {
++	.size = 368 * 4,
++	.lower = 127,
++	.ta = true,
++};
++
+ static const struct of_device_id stm32_romem_of_match[] __maybe_unused = {
+ 	{ .compatible = "st,stm32f4-otp", }, {
+ 		.compatible = "st,stm32mp15-bsec",
+@@ -276,6 +289,9 @@ static const struct of_device_id stm32_r
+ 	}, {
+ 		.compatible = "st,stm32mp13-bsec",
+ 		.data = (void *)&stm32mp13_bsec_cfg,
++	}, {
++		.compatible = "st,stm32mp25-bsec",
++		.data = (void *)&stm32mp25_bsec_cfg,
+ 	},
+ 	{ /* sentinel */ },
+ };
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0008-nvmem-layouts-refactor-.add_cells-callback-arguments.patch b/target/linux/generic/backport-5.15/834-v6.8-0008-nvmem-layouts-refactor-.add_cells-callback-arguments.patch
new file mode 100644
index 00000000000..1bf3ba35b6d
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0008-nvmem-layouts-refactor-.add_cells-callback-arguments.patch
@@ -0,0 +1,94 @@
+From 401df0d4f4098ecc9c5278da2f50756d62e5b37d Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 19 Dec 2023 13:01:03 +0100
+Subject: [PATCH] nvmem: layouts: refactor .add_cells() callback arguments
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Simply pass whole "struct nvmem_layout" instead of single variables.
+There is nothing in "struct nvmem_layout" that we have to hide from
+layout drivers. They also access it during .probe() and .remove().
+
+Thanks to this change:
+
+1. API gets more consistent
+   All layouts drivers callbacks get the same argument
+
+2. Layouts get correct device
+   Before this change NVMEM core code was passing NVMEM device instead
+   of layout device. That resulted in:
+   * Confusing prints
+   * Calling devm_*() helpers on wrong device
+   * Helpers like of_device_get_match_data() dereferencing NULLs
+
+3. It gets possible to get match data
+   First of all nvmem_layout_get_match_data() requires passing "struct
+   nvmem_layout" which .add_cells() callback didn't have before this. It
+   doesn't matter much as it's rather useless now anyway (and will be
+   dropped).
+   What's more important however is that of_device_get_match_data() can
+   be used now thanks to owning a proper device pointer.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Reviewed-by: Michael Walle <michael@walle.cc>
+Link: https://lore.kernel.org/r/20231219120104.3422-1-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c             | 2 +-
+ drivers/nvmem/layouts/onie-tlv.c | 4 +++-
+ drivers/nvmem/layouts/sl28vpd.c  | 4 +++-
+ include/linux/nvmem-provider.h   | 2 +-
+ 4 files changed, 8 insertions(+), 4 deletions(-)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -855,7 +855,7 @@ int nvmem_layout_register(struct nvmem_l
+ 		return -EINVAL;
+ 
+ 	/* Populate the cells */
+-	ret = layout->add_cells(&layout->nvmem->dev, layout->nvmem);
++	ret = layout->add_cells(layout);
+ 	if (ret)
+ 		return ret;
+ 
+--- a/drivers/nvmem/layouts/onie-tlv.c
++++ b/drivers/nvmem/layouts/onie-tlv.c
+@@ -182,8 +182,10 @@ static bool onie_tlv_crc_is_valid(struct
+ 	return true;
+ }
+ 
+-static int onie_tlv_parse_table(struct device *dev, struct nvmem_device *nvmem)
++static int onie_tlv_parse_table(struct nvmem_layout *layout)
+ {
++	struct nvmem_device *nvmem = layout->nvmem;
++	struct device *dev = &layout->dev;
+ 	struct onie_tlv_hdr hdr;
+ 	size_t table_len, data_len, hdr_len;
+ 	u8 *table, *data;
+--- a/drivers/nvmem/layouts/sl28vpd.c
++++ b/drivers/nvmem/layouts/sl28vpd.c
+@@ -80,8 +80,10 @@ static int sl28vpd_v1_check_crc(struct d
+ 	return 0;
+ }
+ 
+-static int sl28vpd_add_cells(struct device *dev, struct nvmem_device *nvmem)
++static int sl28vpd_add_cells(struct nvmem_layout *layout)
+ {
++	struct nvmem_device *nvmem = layout->nvmem;
++	struct device *dev = &layout->dev;
+ 	const struct nvmem_cell_info *pinfo;
+ 	struct nvmem_cell_info info = {0};
+ 	struct device_node *layout_np;
+--- a/include/linux/nvmem-provider.h
++++ b/include/linux/nvmem-provider.h
+@@ -173,7 +173,7 @@ struct nvmem_cell_table {
+ struct nvmem_layout {
+ 	struct device dev;
+ 	struct nvmem_device *nvmem;
+-	int (*add_cells)(struct device *dev, struct nvmem_device *nvmem);
++	int (*add_cells)(struct nvmem_layout *layout);
+ };
+ 
+ struct nvmem_layout_driver {
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0009-nvmem-drop-nvmem_layout_get_match_data.patch b/target/linux/generic/backport-5.15/834-v6.8-0009-nvmem-drop-nvmem_layout_get_match_data.patch
new file mode 100644
index 00000000000..514b5f2de5c
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0009-nvmem-drop-nvmem_layout_get_match_data.patch
@@ -0,0 +1,72 @@
+From 43f60e3fb62edc7bd8891de8779fb422f4ae23ae Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 19 Dec 2023 13:01:04 +0100
+Subject: [PATCH] nvmem: drop nvmem_layout_get_match_data()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Thanks for layouts refactoring we now have "struct device" associated
+with layout. Also its OF pointer points directly to the "nvmem-layout"
+DT node.
+
+All it takes to get match data is a generic of_device_get_match_data().
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Reviewed-by: Michael Walle <michael@walle.cc>
+Link: https://lore.kernel.org/r/20231219120104.3422-2-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c           | 13 -------------
+ include/linux/nvmem-provider.h | 10 ----------
+ 2 files changed, 23 deletions(-)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -877,19 +877,6 @@ void nvmem_layout_unregister(struct nvme
+ }
+ EXPORT_SYMBOL_GPL(nvmem_layout_unregister);
+ 
+-const void *nvmem_layout_get_match_data(struct nvmem_device *nvmem,
+-					struct nvmem_layout *layout)
+-{
+-	struct device_node __maybe_unused *layout_np;
+-	const struct of_device_id *match;
+-
+-	layout_np = of_nvmem_layout_get_container(nvmem);
+-	match = of_match_node(layout->dev.driver->of_match_table, layout_np);
+-
+-	return match ? match->data : NULL;
+-}
+-EXPORT_SYMBOL_GPL(nvmem_layout_get_match_data);
+-
+ /**
+  * nvmem_register() - Register a nvmem device for given nvmem_config.
+  * Also creates a binary entry in /sys/bus/nvmem/devices/dev-name/nvmem
+--- a/include/linux/nvmem-provider.h
++++ b/include/linux/nvmem-provider.h
+@@ -205,9 +205,6 @@ void nvmem_layout_driver_unregister(stru
+ 	module_driver(__nvmem_layout_driver, nvmem_layout_driver_register, \
+ 		      nvmem_layout_driver_unregister)
+ 
+-const void *nvmem_layout_get_match_data(struct nvmem_device *nvmem,
+-					struct nvmem_layout *layout);
+-
+ #else
+ 
+ static inline struct nvmem_device *nvmem_register(const struct nvmem_config *c)
+@@ -238,13 +235,6 @@ static inline int nvmem_layout_register(
+ 
+ static inline void nvmem_layout_unregister(struct nvmem_layout *layout) {}
+ 
+-static inline const void *
+-nvmem_layout_get_match_data(struct nvmem_device *nvmem,
+-			    struct nvmem_layout *layout)
+-{
+-	return NULL;
+-}
+-
+ #endif /* CONFIG_NVMEM */
+ 
+ #if IS_ENABLED(CONFIG_NVMEM) && IS_ENABLED(CONFIG_OF)
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0010-nvmem-core-add-nvmem_dev_size-helper.patch b/target/linux/generic/backport-5.15/834-v6.8-0010-nvmem-core-add-nvmem_dev_size-helper.patch
new file mode 100644
index 00000000000..aa0bbaa0c55
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0010-nvmem-core-add-nvmem_dev_size-helper.patch
@@ -0,0 +1,53 @@
+From 33cf42e68efc8ff529a7eee08a4f0ba8c8d0a207 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Dec 2023 18:34:17 +0100
+Subject: [PATCH] nvmem: core: add nvmem_dev_size() helper
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This is required by layouts that need to read whole NVMEM content. It's
+especially useful for NVMEM devices without hardcoded layout (like
+U-Boot environment data block).
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/r/20231221173421.13737-2-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/core.c           | 13 +++++++++++++
+ include/linux/nvmem-consumer.h |  1 +
+ 2 files changed, 14 insertions(+)
+
+--- a/drivers/nvmem/core.c
++++ b/drivers/nvmem/core.c
+@@ -2164,6 +2164,19 @@ const char *nvmem_dev_name(struct nvmem_
+ }
+ EXPORT_SYMBOL_GPL(nvmem_dev_name);
+ 
++/**
++ * nvmem_dev_size() - Get the size of a given nvmem device.
++ *
++ * @nvmem: nvmem device.
++ *
++ * Return: size of the nvmem device.
++ */
++size_t nvmem_dev_size(struct nvmem_device *nvmem)
++{
++	return nvmem->size;
++}
++EXPORT_SYMBOL_GPL(nvmem_dev_size);
++
+ static int __init nvmem_init(void)
+ {
+ 	int ret;
+--- a/include/linux/nvmem-consumer.h
++++ b/include/linux/nvmem-consumer.h
+@@ -81,6 +81,7 @@ int nvmem_device_cell_write(struct nvmem
+ 			    struct nvmem_cell_info *info, void *buf);
+ 
+ const char *nvmem_dev_name(struct nvmem_device *nvmem);
++size_t nvmem_dev_size(struct nvmem_device *nvmem);
+ 
+ void nvmem_add_cell_lookups(struct nvmem_cell_lookup *entries,
+ 			    size_t nentries);
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0011-nvmem-u-boot-env-use-nvmem_add_one_cell-nvmem-subsys.patch b/target/linux/generic/backport-5.15/834-v6.8-0011-nvmem-u-boot-env-use-nvmem_add_one_cell-nvmem-subsys.patch
new file mode 100644
index 00000000000..fc826f3f7e4
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0011-nvmem-u-boot-env-use-nvmem_add_one_cell-nvmem-subsys.patch
@@ -0,0 +1,126 @@
+From 7c8979b42b1a9c5604f431ba804928e55919263c Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Dec 2023 18:34:18 +0100
+Subject: [PATCH] nvmem: u-boot-env: use nvmem_add_one_cell() nvmem subsystem
+ helper
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Simplify adding NVMEM cells.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/r/20231221173421.13737-3-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/u-boot-env.c | 55 +++++++++++++++-----------------------
+ 1 file changed, 21 insertions(+), 34 deletions(-)
+
+--- a/drivers/nvmem/u-boot-env.c
++++ b/drivers/nvmem/u-boot-env.c
+@@ -23,13 +23,10 @@ enum u_boot_env_format {
+ 
+ struct u_boot_env {
+ 	struct device *dev;
++	struct nvmem_device *nvmem;
+ 	enum u_boot_env_format format;
+ 
+ 	struct mtd_info *mtd;
+-
+-	/* Cells */
+-	struct nvmem_cell_info *cells;
+-	int ncells;
+ };
+ 
+ struct u_boot_env_image_single {
+@@ -94,43 +91,36 @@ static int u_boot_env_read_post_process_
+ static int u_boot_env_add_cells(struct u_boot_env *priv, uint8_t *buf,
+ 				size_t data_offset, size_t data_len)
+ {
++	struct nvmem_device *nvmem = priv->nvmem;
+ 	struct device *dev = priv->dev;
+ 	char *data = buf + data_offset;
+ 	char *var, *value, *eq;
+-	int idx;
+-
+-	priv->ncells = 0;
+-	for (var = data; var < data + data_len && *var; var += strlen(var) + 1)
+-		priv->ncells++;
+-
+-	priv->cells = devm_kcalloc(dev, priv->ncells, sizeof(*priv->cells), GFP_KERNEL);
+-	if (!priv->cells)
+-		return -ENOMEM;
+ 
+-	for (var = data, idx = 0;
++	for (var = data;
+ 	     var < data + data_len && *var;
+-	     var = value + strlen(value) + 1, idx++) {
++	     var = value + strlen(value) + 1) {
++		struct nvmem_cell_info info = {};
++
+ 		eq = strchr(var, '=');
+ 		if (!eq)
+ 			break;
+ 		*eq = '\0';
+ 		value = eq + 1;
+ 
+-		priv->cells[idx].name = devm_kstrdup(dev, var, GFP_KERNEL);
+-		if (!priv->cells[idx].name)
++		info.name = devm_kstrdup(dev, var, GFP_KERNEL);
++		if (!info.name)
+ 			return -ENOMEM;
+-		priv->cells[idx].offset = data_offset + value - data;
+-		priv->cells[idx].bytes = strlen(value);
+-		priv->cells[idx].np = of_get_child_by_name(dev->of_node, priv->cells[idx].name);
++		info.offset = data_offset + value - data;
++		info.bytes = strlen(value);
++		info.np = of_get_child_by_name(dev->of_node, info.name);
+ 		if (!strcmp(var, "ethaddr")) {
+-			priv->cells[idx].raw_len = strlen(value);
+-			priv->cells[idx].bytes = ETH_ALEN;
+-			priv->cells[idx].read_post_process = u_boot_env_read_post_process_ethaddr;
++			info.raw_len = strlen(value);
++			info.bytes = ETH_ALEN;
++			info.read_post_process = u_boot_env_read_post_process_ethaddr;
+ 		}
+-	}
+ 
+-	if (WARN_ON(idx != priv->ncells))
+-		priv->ncells = idx;
++		nvmem_add_one_cell(nvmem, &info);
++	}
+ 
+ 	return 0;
+ }
+@@ -209,7 +199,6 @@ static int u_boot_env_probe(struct platf
+ 	struct device *dev = &pdev->dev;
+ 	struct device_node *np = dev->of_node;
+ 	struct u_boot_env *priv;
+-	int err;
+ 
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+@@ -224,17 +213,15 @@ static int u_boot_env_probe(struct platf
+ 		return PTR_ERR(priv->mtd);
+ 	}
+ 
+-	err = u_boot_env_parse(priv);
+-	if (err)
+-		return err;
+-
+ 	config.dev = dev;
+-	config.cells = priv->cells;
+-	config.ncells = priv->ncells;
+ 	config.priv = priv;
+ 	config.size = priv->mtd->size;
+ 
+-	return PTR_ERR_OR_ZERO(devm_nvmem_register(dev, &config));
++	priv->nvmem = devm_nvmem_register(dev, &config);
++	if (IS_ERR(priv->nvmem))
++		return PTR_ERR(priv->nvmem);
++
++	return u_boot_env_parse(priv);
+ }
+ 
+ static const struct of_device_id u_boot_env_of_match_table[] = {
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0012-nvmem-u-boot-env-use-nvmem-device-helpers.patch b/target/linux/generic/backport-5.15/834-v6.8-0012-nvmem-u-boot-env-use-nvmem-device-helpers.patch
new file mode 100644
index 00000000000..70abc7cf143
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0012-nvmem-u-boot-env-use-nvmem-device-helpers.patch
@@ -0,0 +1,81 @@
+From a832556d23c5a11115f300011a5874d6107a0d62 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Dec 2023 18:34:19 +0100
+Subject: [PATCH] nvmem: u-boot-env: use nvmem device helpers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Use nvmem_dev_size() and nvmem_device_read() to make this driver less
+mtd dependent.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/r/20231221173421.13737-4-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/u-boot-env.c | 23 +++++++++++++++--------
+ 1 file changed, 15 insertions(+), 8 deletions(-)
+
+--- a/drivers/nvmem/u-boot-env.c
++++ b/drivers/nvmem/u-boot-env.c
+@@ -127,27 +127,34 @@ static int u_boot_env_add_cells(struct u
+ 
+ static int u_boot_env_parse(struct u_boot_env *priv)
+ {
++	struct nvmem_device *nvmem = priv->nvmem;
+ 	struct device *dev = priv->dev;
+ 	size_t crc32_data_offset;
+ 	size_t crc32_data_len;
+ 	size_t crc32_offset;
+ 	size_t data_offset;
+ 	size_t data_len;
++	size_t dev_size;
+ 	uint32_t crc32;
+ 	uint32_t calc;
+-	size_t bytes;
+ 	uint8_t *buf;
++	int bytes;
+ 	int err;
+ 
+-	buf = kcalloc(1, priv->mtd->size, GFP_KERNEL);
++	dev_size = nvmem_dev_size(nvmem);
++
++	buf = kcalloc(1, dev_size, GFP_KERNEL);
+ 	if (!buf) {
+ 		err = -ENOMEM;
+ 		goto err_out;
+ 	}
+ 
+-	err = mtd_read(priv->mtd, 0, priv->mtd->size, &bytes, buf);
+-	if ((err && !mtd_is_bitflip(err)) || bytes != priv->mtd->size) {
+-		dev_err(dev, "Failed to read from mtd: %d\n", err);
++	bytes = nvmem_device_read(nvmem, 0, dev_size, buf);
++	if (bytes < 0) {
++		err = bytes;
++		goto err_kfree;
++	} else if (bytes != dev_size) {
++		err = -EIO;
+ 		goto err_kfree;
+ 	}
+ 
+@@ -169,8 +176,8 @@ static int u_boot_env_parse(struct u_boo
+ 		break;
+ 	}
+ 	crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset));
+-	crc32_data_len = priv->mtd->size - crc32_data_offset;
+-	data_len = priv->mtd->size - data_offset;
++	crc32_data_len = dev_size - crc32_data_offset;
++	data_len = dev_size - data_offset;
+ 
+ 	calc = crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L;
+ 	if (calc != crc32) {
+@@ -179,7 +186,7 @@ static int u_boot_env_parse(struct u_boo
+ 		goto err_kfree;
+ 	}
+ 
+-	buf[priv->mtd->size - 1] = '\0';
++	buf[dev_size - 1] = '\0';
+ 	err = u_boot_env_add_cells(priv, buf, data_offset, data_len);
+ 	if (err)
+ 		dev_err(dev, "Failed to add cells: %d\n", err);
diff --git a/target/linux/generic/backport-5.15/834-v6.8-0013-nvmem-u-boot-env-improve-coding-style.patch b/target/linux/generic/backport-5.15/834-v6.8-0013-nvmem-u-boot-env-improve-coding-style.patch
new file mode 100644
index 00000000000..273cfed8743
--- /dev/null
+++ b/target/linux/generic/backport-5.15/834-v6.8-0013-nvmem-u-boot-env-improve-coding-style.patch
@@ -0,0 +1,62 @@
+From 6bafe07c930676d6430be471310958070816a595 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Thu, 21 Dec 2023 18:34:20 +0100
+Subject: [PATCH] nvmem: u-boot-env: improve coding style
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+1. Prefer kzalloc() over kcalloc()
+   See memory-allocation.rst which says: "to be on the safe side it's
+   best to use routines that set memory to zero, like kzalloc()"
+2. Drop dev_err() for u_boot_env_add_cells() fail
+   It can fail only on -ENOMEM. We don't want to print error then.
+3. Add extra "crc32_addr" variable
+   It makes code reading header's crc32 easier to understand / review.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/r/20231221173421.13737-5-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/nvmem/u-boot-env.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/nvmem/u-boot-env.c
++++ b/drivers/nvmem/u-boot-env.c
+@@ -132,6 +132,7 @@ static int u_boot_env_parse(struct u_boo
+ 	size_t crc32_data_offset;
+ 	size_t crc32_data_len;
+ 	size_t crc32_offset;
++	__le32 *crc32_addr;
+ 	size_t data_offset;
+ 	size_t data_len;
+ 	size_t dev_size;
+@@ -143,7 +144,7 @@ static int u_boot_env_parse(struct u_boo
+ 
+ 	dev_size = nvmem_dev_size(nvmem);
+ 
+-	buf = kcalloc(1, dev_size, GFP_KERNEL);
++	buf = kzalloc(dev_size, GFP_KERNEL);
+ 	if (!buf) {
+ 		err = -ENOMEM;
+ 		goto err_out;
+@@ -175,7 +176,8 @@ static int u_boot_env_parse(struct u_boo
+ 		data_offset = offsetof(struct u_boot_env_image_broadcom, data);
+ 		break;
+ 	}
+-	crc32 = le32_to_cpu(*(__le32 *)(buf + crc32_offset));
++	crc32_addr = (__le32 *)(buf + crc32_offset);
++	crc32 = le32_to_cpu(*crc32_addr);
+ 	crc32_data_len = dev_size - crc32_data_offset;
+ 	data_len = dev_size - data_offset;
+ 
+@@ -188,8 +190,6 @@ static int u_boot_env_parse(struct u_boo
+ 
+ 	buf[dev_size - 1] = '\0';
+ 	err = u_boot_env_add_cells(priv, buf, data_offset, data_len);
+-	if (err)
+-		dev_err(dev, "Failed to add cells: %d\n", err);
+ 
+ err_kfree:
+ 	kfree(buf);
diff --git a/target/linux/generic/backport-5.15/894-v6.8-net-ethtool-implement-ethtool_puts.patch b/target/linux/generic/backport-5.15/894-v6.8-net-ethtool-implement-ethtool_puts.patch
new file mode 100644
index 00000000000..283e226d16d
--- /dev/null
+++ b/target/linux/generic/backport-5.15/894-v6.8-net-ethtool-implement-ethtool_puts.patch
@@ -0,0 +1,139 @@
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+	Salil Mehta <salil.mehta@huawei.com>, Jesse Brandeburg <jesse.brandeburg@intel.com>, 
+	Tony Nguyen <anthony.l.nguyen@intel.com>, Louis Peens <louis.peens@corigine.com>, 
+	Shannon Nelson <shannon.nelson@amd.com>, Brett Creeley <brett.creeley@amd.com>, drivers@pensando.io, 
+	"K. Y. Srinivasan" <kys@microsoft.com>, Haiyang Zhang <haiyangz@microsoft.com>, Wei Liu <wei.liu@kernel.org>, 
+	Dexuan Cui <decui@microsoft.com>, Ronak Doshi <doshir@vmware.com>, 
+	VMware PV-Drivers Reviewers <pv-drivers@vmware.com>, Andy Whitcroft <apw@canonical.com>, Joe Perches <joe@perches.com>, 
+	Dwaipayan Ray <dwaipayanray1@gmail.com>, Lukas Bulwahn <lukas.bulwahn@gmail.com>, 
+	Hauke Mehrtens <hauke@hauke-m.de>, Andrew Lunn <andrew@lunn.ch>, 
+	Florian Fainelli <f.fainelli@gmail.com>, Vladimir Oltean <olteanv@gmail.com>, 
+	"=?utf-8?q?Ar=C4=B1n=C3=A7_=C3=9CNAL?=" <arinc.unal@arinc9.com>, Daniel Golle <daniel@makrotopia.org>, 
+	Landen Chao <Landen.Chao@mediatek.com>, DENG Qingfang <dqfext@gmail.com>, 
+	Sean Wang <sean.wang@mediatek.com>, Matthias Brugger <matthias.bgg@gmail.com>, 
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>, 
+	Linus Walleij <linus.walleij@linaro.org>, 
+	"=?utf-8?q?Alvin_=C5=A0ipraga?=" <alsi@bang-olufsen.dk>, Wei Fang <wei.fang@nxp.com>, 
+	Shenwei Wang <shenwei.wang@nxp.com>, Clark Wang <xiaoning.wang@nxp.com>, 
+	NXP Linux Team <linux-imx@nxp.com>, Lars Povlsen <lars.povlsen@microchip.com>, 
+	Steen Hegelund <Steen.Hegelund@microchip.com>, Daniel Machon <daniel.machon@microchip.com>, 
+	UNGLinuxDriver@microchip.com, Jiawen Wu <jiawenwu@trustnetic.com>, 
+	Mengyuan Lou <mengyuanlou@net-swift.com>, Heiner Kallweit <hkallweit1@gmail.com>, 
+	Russell King <linux@armlinux.org.uk>, Alexei Starovoitov <ast@kernel.org>, 
+	Daniel Borkmann <daniel@iogearbox.net>, Jesper Dangaard Brouer <hawk@kernel.org>, 
+	John Fastabend <john.fastabend@gmail.com>
+Cc: linux-kernel@vger.kernel.org, netdev@vger.kernel.org, 
+	Nick Desaulniers <ndesaulniers@google.com>, Nathan Chancellor <nathan@kernel.org>, 
+	Kees Cook <keescook@chromium.org>, intel-wired-lan@lists.osuosl.org, 
+	oss-drivers@corigine.com, linux-hyperv@vger.kernel.org, 
+	linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, 
+	bpf@vger.kernel.org, Justin Stitt <justinstitt@google.com>
+Content-Type: text/plain; charset="utf-8"
+
+Use strscpy() to implement ethtool_puts().
+
+Functionally the same as ethtool_sprintf() when it's used with two
+arguments or with just "%s" format specifier.
+
+Signed-off-by: Justin Stitt <justinstitt@google.com>
+---
+ include/linux/ethtool.h | 13 +++++++++++++
+ net/ethtool/ioctl.c     |  7 +++++++
+ 2 files changed, 20 insertions(+)
+
+--- a/include/linux/ethtool.h
++++ b/include/linux/ethtool.h
+@@ -788,4 +788,17 @@ int ethtool_get_phc_vclocks(struct net_d
+  * next string.
+  */
+ extern __printf(2, 3) void ethtool_sprintf(u8 **data, const char *fmt, ...);
++
++/**
++ * ethtool_puts - Write string to ethtool string data
++ * @data: Pointer to a pointer to the start of string to update
++ * @str: String to write
++ *
++ * Write string to *data without a trailing newline. Update *data
++ * to point at start of next string.
++ *
++ * Prefer this function to ethtool_sprintf() when given only
++ * two arguments or if @fmt is just "%s".
++ */
++extern void ethtool_puts(u8 **data, const char *str);
+ #endif /* _LINUX_ETHTOOL_H */
+--- a/net/ethtool/ioctl.c
++++ b/net/ethtool/ioctl.c
+@@ -1954,6 +1954,13 @@ __printf(2, 3) void ethtool_sprintf(u8 *
+ }
+ EXPORT_SYMBOL(ethtool_sprintf);
+ 
++void ethtool_puts(u8 **data, const char *str)
++{
++	strscpy(*data, str, ETH_GSTRING_LEN);
++	*data += ETH_GSTRING_LEN;
++}
++EXPORT_SYMBOL(ethtool_puts);
++
+ static int ethtool_phys_id(struct net_device *dev, void __user *useraddr)
+ {
+ 	struct ethtool_value id;
diff --git a/target/linux/generic/backport-6.1/200-v6.3-bitfield-add-FIELD_PREP_CONST.patch b/target/linux/generic/backport-6.1/200-v6.3-bitfield-add-FIELD_PREP_CONST.patch
new file mode 100644
index 00000000000..2e6d881fe9f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/200-v6.3-bitfield-add-FIELD_PREP_CONST.patch
@@ -0,0 +1,58 @@
+From e2192de59e457aef8d1f055a452131f0b3e5d097 Mon Sep 17 00:00:00 2001
+From: Johannes Berg <johannes.berg@intel.com>
+Date: Wed, 18 Jan 2023 14:26:53 +0100
+Subject: [PATCH] bitfield: add FIELD_PREP_CONST()
+
+Neither FIELD_PREP() nor *_encode_bits() can be used
+in constant contexts (such as initializers), but we
+don't want to define shift constants for all masks
+just for use in initializers, and having checks that
+the values fit is also useful.
+
+Therefore, add FIELD_PREP_CONST() which is a smaller
+version of FIELD_PREP() that can only take constant
+arguments and has less friendly (but not less strict)
+error checks, and expands to a constant value.
+
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+Link: https://lore.kernel.org/r/20230118142652.53f20593504b.Iaeea0aee77a6493d70e573b4aa55c91c00e01e4b@changeid
+Signed-off-by: Johannes Berg <johannes.berg@intel.com>
+---
+ include/linux/bitfield.h | 26 ++++++++++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/include/linux/bitfield.h
++++ b/include/linux/bitfield.h
+@@ -115,6 +115,32 @@
+ 		((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask);	\
+ 	})
+ 
++#define __BF_CHECK_POW2(n)	BUILD_BUG_ON_ZERO(((n) & ((n) - 1)) != 0)
++
++/**
++ * FIELD_PREP_CONST() - prepare a constant bitfield element
++ * @_mask: shifted mask defining the field's length and position
++ * @_val:  value to put in the field
++ *
++ * FIELD_PREP_CONST() masks and shifts up the value.  The result should
++ * be combined with other fields of the bitfield using logical OR.
++ *
++ * Unlike FIELD_PREP() this is a constant expression and can therefore
++ * be used in initializers. Error checking is less comfortable for this
++ * version, and non-constant masks cannot be used.
++ */
++#define FIELD_PREP_CONST(_mask, _val)					\
++	(								\
++		/* mask must be non-zero */				\
++		BUILD_BUG_ON_ZERO((_mask) == 0) +			\
++		/* check if value fits */				\
++		BUILD_BUG_ON_ZERO(~((_mask) >> __bf_shf(_mask)) & (_val)) + \
++		/* check if mask is contiguous */			\
++		__BF_CHECK_POW2((_mask) + (1ULL << __bf_shf(_mask))) +	\
++		/* and create the value */				\
++		(((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask))	\
++	)
++
+ /**
+  * FIELD_GET() - extract a bitfield element
+  * @_mask: shifted mask defining the field's length and position
diff --git a/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch b/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch
new file mode 100644
index 00000000000..657404196d3
--- /dev/null
+++ b/target/linux/generic/backport-6.1/424-v6.3-mtd-ubi-wire-up-parent-MTD-device.patch
@@ -0,0 +1,33 @@
+From 1ecf9e390452e73a362ea7fbde8f3f0db83de856 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 22 Dec 2022 19:33:04 +0000
+Subject: [PATCH] mtd: ubi: wire-up parent MTD device
+
+Wire up the device parent pointer of UBI devices to their lower MTD
+device, typically an MTD partition or whole-chip device.
+
+The most noticeable change is that in sysfs, previously ubi devices
+would be could in /sys/devices/virtual/ubi while after this change they
+would be correctly attached to their parent MTD device, e.g.
+
+/sys/devices/platform/1100d000.spi/spi_master/spi1/spi1.0/mtd/mtd2/ubi0.
+
+Locating UBI devices using /sys/class/ubi/ of course still works as
+well.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+---
+ drivers/mtd/ubi/build.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -929,6 +929,7 @@ int ubi_attach_mtd_dev(struct mtd_info *
+ 	ubi->dev.release = dev_release;
+ 	ubi->dev.class = &ubi_class;
+ 	ubi->dev.groups = ubi_dev_groups;
++	ubi->dev.parent = &mtd->dev;
+ 
+ 	ubi->mtd = mtd;
+ 	ubi->ubi_num = ubi_num;
diff --git a/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch b/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch
new file mode 100644
index 00000000000..48bf9861184
--- /dev/null
+++ b/target/linux/generic/backport-6.1/425-v6.3-mtd-ubi-block-wire-up-device-parent.patch
@@ -0,0 +1,49 @@
+From 05b8773ca33253ea562be145cf3145b05ef19f86 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 22 Dec 2022 19:33:31 +0000
+Subject: [PATCH] mtd: ubi: block: wire-up device parent
+
+ubiblock devices were previously only identifyable by their name, but
+not connected to their parent UBI volume device e.g. in sysfs.
+Properly parent ubiblock device as descendant of a UBI volume device
+to reflect device model hierachy.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Signed-off-by: Richard Weinberger <richard@nod.at>
+---
+ drivers/mtd/ubi/block.c | 2 +-
+ drivers/mtd/ubi/kapi.c  | 1 +
+ include/linux/mtd/ubi.h | 1 +
+ 3 files changed, 3 insertions(+), 1 deletion(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -452,7 +452,7 @@ int ubiblock_create(struct ubi_volume_in
+ 	list_add_tail(&dev->list, &ubiblock_devices);
+ 
+ 	/* Must be the last step: anyone can call file ops from now on */
+-	ret = add_disk(dev->gd);
++	ret = device_add_disk(vi->dev, dev->gd, NULL);
+ 	if (ret)
+ 		goto out_destroy_wq;
+ 
+--- a/drivers/mtd/ubi/kapi.c
++++ b/drivers/mtd/ubi/kapi.c
+@@ -79,6 +79,7 @@ void ubi_do_get_volume_info(struct ubi_d
+ 	vi->name_len = vol->name_len;
+ 	vi->name = vol->name;
+ 	vi->cdev = vol->cdev.dev;
++	vi->dev = &vol->dev;
+ }
+ 
+ /**
+--- a/include/linux/mtd/ubi.h
++++ b/include/linux/mtd/ubi.h
+@@ -110,6 +110,7 @@ struct ubi_volume_info {
+ 	int name_len;
+ 	const char *name;
+ 	dev_t cdev;
++	struct device *dev;
+ };
+ 
+ /**
diff --git a/target/linux/generic/backport-6.1/424-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch b/target/linux/generic/backport-6.1/426-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
similarity index 100%
rename from target/linux/generic/backport-6.1/424-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
rename to target/linux/generic/backport-6.1/426-v6.4-0004-mtd-core-prepare-mtd_otp_nvmem_add-to-handle-EPROBE_.patch
diff --git a/target/linux/generic/backport-6.1/707-v6.8-01-net-phy-at803x-fix-passing-the-wrong-reference-for-c.patch b/target/linux/generic/backport-6.1/707-v6.8-01-net-phy-at803x-fix-passing-the-wrong-reference-for-c.patch
deleted file mode 100644
index b206b180526..00000000000
--- a/target/linux/generic/backport-6.1/707-v6.8-01-net-phy-at803x-fix-passing-the-wrong-reference-for-c.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From f8fdbf3389f44c7026f16e36cb1f2ff017f7f5b2 Mon Sep 17 00:00:00 2001
-From: Christian Marangi <ansuelsmth@gmail.com>
-Date: Fri, 8 Dec 2023 15:51:48 +0100
-Subject: [PATCH 01/13] net: phy: at803x: fix passing the wrong reference for
- config_intr
-
-Fix passing the wrong reference for config_initr on passing the function
-pointer, drop the wrong & from at803x_config_intr in the PHY struct.
-
-Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
-Reviewed-by: Andrew Lunn <andrew@lunn.ch>
-Signed-off-by: David S. Miller <davem@davemloft.net>
----
- drivers/net/phy/at803x.c | 6 +++---
- 1 file changed, 3 insertions(+), 3 deletions(-)
-
---- a/drivers/net/phy/at803x.c
-+++ b/drivers/net/phy/at803x.c
-@@ -2104,7 +2104,7 @@ static struct phy_driver at803x_driver[]
- 	.write_page		= at803x_write_page,
- 	.get_features		= at803x_get_features,
- 	.read_status		= at803x_read_status,
--	.config_intr		= &at803x_config_intr,
-+	.config_intr		= at803x_config_intr,
- 	.handle_interrupt	= at803x_handle_interrupt,
- 	.get_tunable		= at803x_get_tunable,
- 	.set_tunable		= at803x_set_tunable,
-@@ -2134,7 +2134,7 @@ static struct phy_driver at803x_driver[]
- 	.resume			= at803x_resume,
- 	.flags			= PHY_POLL_CABLE_TEST,
- 	/* PHY_BASIC_FEATURES */
--	.config_intr		= &at803x_config_intr,
-+	.config_intr		= at803x_config_intr,
- 	.handle_interrupt	= at803x_handle_interrupt,
- 	.cable_test_start	= at803x_cable_test_start,
- 	.cable_test_get_status	= at803x_cable_test_get_status,
-@@ -2150,7 +2150,7 @@ static struct phy_driver at803x_driver[]
- 	.resume			= at803x_resume,
- 	.flags			= PHY_POLL_CABLE_TEST,
- 	/* PHY_BASIC_FEATURES */
--	.config_intr		= &at803x_config_intr,
-+	.config_intr		= at803x_config_intr,
- 	.handle_interrupt	= at803x_handle_interrupt,
- 	.cable_test_start	= at803x_cable_test_start,
- 	.cable_test_get_status	= at803x_cable_test_get_status,
diff --git a/target/linux/generic/backport-6.1/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch b/target/linux/generic/backport-6.1/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch
new file mode 100644
index 00000000000..36675e7588d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/712-v6.9-net-phy-at803x-add-LED-support-for-qca808x.patch
@@ -0,0 +1,408 @@
+From 7196062b64ee470b91015f3d2e82d225948258ea Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 25 Jan 2024 21:37:01 +0100
+Subject: [PATCH 5/5] net: phy: at803x: add LED support for qca808x
+
+Add LED support for QCA8081 PHY.
+
+Documentation for this LEDs PHY is very scarce even with NDA access
+to Documentation for OEMs. Only the blink pattern are documented and are
+very confusing most of the time. No documentation is present about
+forcing the LED on/off or to always blink.
+
+Those settings were reversed by poking the regs and trying to find the
+correct bits to trigger these modes. Some bits mode are not clear and
+maybe the documentation option are not 100% correct. For the sake of LED
+support the reversed option are enough to add support for current LED
+APIs.
+
+Supported HW control modes are:
+- tx
+- rx
+- link_10
+- link_100
+- link_1000
+- link_2500
+- half_duplex
+- full_duplex
+
+Also add support for LED polarity set to set LED polarity to active
+high or low. QSDK sets this value to high by default but PHY reset value
+doesn't have this enabled by default.
+
+QSDK also sets 2 additional bits but their usage is not clear, info about
+this is added in the header. It was verified that for correct function
+of the LED if active high is needed, only BIT 6 is needed.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240125203702.4552-6-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/at803x.c | 327 +++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 327 insertions(+)
+
+--- a/drivers/net/phy/at803x.c
++++ b/drivers/net/phy/at803x.c
+@@ -301,6 +301,87 @@
+ /* Added for reference of existence but should be handled by wait_for_completion already */
+ #define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+ 
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++#define QCA808X_MMD7_LED2_CTRL			0x8074
++#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
++#define QCA808X_MMD7_LED1_CTRL			0x8076
++#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
++#define QCA808X_MMD7_LED0_CTRL			0x8078
++#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
++#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
++#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
++ * LED to active high. It's not clear what BIT 3 and BIT 4 does.
++ */
++#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
++
+ /* QCA808X 1G chip type */
+ #define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
+ #define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
+@@ -346,6 +427,7 @@ struct at803x_priv {
+ 	struct regulator_dev *vddio_rdev;
+ 	struct regulator_dev *vddh_rdev;
+ 	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
++	int led_polarity_mode;
+ };
+ 
+ struct at803x_context {
+@@ -706,6 +788,9 @@ static int at803x_probe(struct phy_devic
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
++	/* Init LED polarity mode to -1 */
++	priv->led_polarity_mode = -1;
++
+ 	phydev->priv = priv;
+ 
+ 	ret = at803x_parse_dt(phydev);
+@@ -2235,6 +2320,242 @@ static void qca808x_link_change_notify(s
+ 				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
+ }
+ 
++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	if (test_bit(TRIGGER_NETDEV_TX, &rules))
++		*offload_trigger |= QCA808X_LED_TX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_RX, &rules))
++		*offload_trigger |= QCA808X_LED_RX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED10_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED100_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
++	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	/* Enable BLINK_CHECK_BYPASS by default to make the LED
++	 * blink even with duplex or speed mode not enabled.
++	 */
++	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 2)
++		return -EINVAL;
++
++	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, offload_trigger = 0;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca808x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_PATTERN_MASK,
++			      offload_trigger);
++}
++
++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return false;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca808x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	if (val & QCA808X_LED_TX_BLINK)
++		set_bit(TRIGGER_NETDEV_TX, rules);
++	if (val & QCA808X_LED_RX_BLINK)
++		set_bit(TRIGGER_NETDEV_RX, rules);
++	if (val & QCA808X_LED_SPEED10_ON)
++		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++	if (val & QCA808X_LED_SPEED100_ON)
++		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++	if (val & QCA808X_LED_SPEED1000_ON)
++		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++	if (val & QCA808X_LED_SPEED2500_ON)
++		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
++	if (val & QCA808X_LED_HALF_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++	if (val & QCA808X_LED_FULL_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_PATTERN_MASK);
++}
++
++static int qca808x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	if (!value) {
++		ret = qca808x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF);
++}
++
++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	int ret;
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++
++static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
++				    unsigned long modes)
++{
++	struct at803x_priv *priv = phydev->priv;
++	bool active_low = false;
++	u32 mode;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	/* PHY polarity is global and can't be set per LED.
++	 * To detect this, check if last requested polarity mode
++	 * match the new one.
++	 */
++	if (priv->led_polarity_mode >= 0 &&
++	    priv->led_polarity_mode != active_low) {
++		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
++		return -EINVAL;
++	}
++
++	/* Save the last PHY polarity mode */
++	priv->led_polarity_mode = active_low;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN,
++			      QCA808X_MMD7_LED_POLARITY_CTRL,
++			      QCA808X_LED_ACTIVE_HIGH,
++			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
++}
++
+ static struct phy_driver at803x_driver[] = {
+ {
+ 	/* Qualcomm Atheros AR8035 */
+@@ -2411,6 +2732,12 @@ static struct phy_driver at803x_driver[]
+ 	.cable_test_start	= qca808x_cable_test_start,
+ 	.cable_test_get_status	= qca808x_cable_test_get_status,
+ 	.link_change_notify	= qca808x_link_change_notify,
++	.led_brightness_set	= qca808x_led_brightness_set,
++	.led_blink_set		= qca808x_led_blink_set,
++	.led_hw_is_supported	= qca808x_led_hw_is_supported,
++	.led_hw_control_set	= qca808x_led_hw_control_set,
++	.led_hw_control_get	= qca808x_led_hw_control_get,
++	.led_polarity_set	= qca808x_led_polarity_set,
+ }, };
+ 
+ module_phy_driver(at803x_driver);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch b/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch
new file mode 100644
index 00000000000..8c9babea7b1
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-01-net-phy-move-at803x-PHY-driver-to-dedicated-director.patch
@@ -0,0 +1,5598 @@
+From 9e56ff53b4115875667760445b028357848b4748 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:19 +0100
+Subject: [PATCH 1/5] net: phy: move at803x PHY driver to dedicated directory
+
+In preparation for addition of other Qcom PHY and to tidy things up,
+move the at803x PHY driver to dedicated directory.
+
+The same order in the Kconfig selection is saved.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-2-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/Kconfig             | 7 +------
+ drivers/net/phy/Makefile            | 2 +-
+ drivers/net/phy/qcom/Kconfig        | 7 +++++++
+ drivers/net/phy/qcom/Makefile       | 2 ++
+ drivers/net/phy/{ => qcom}/at803x.c | 0
+ 5 files changed, 11 insertions(+), 7 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/Kconfig
+ create mode 100644 drivers/net/phy/qcom/Makefile
+ rename drivers/net/phy/{ => qcom}/at803x.c (100%)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -277,12 +277,7 @@ config NXP_TJA11XX_PHY
+ 	help
+ 	  Currently supports the NXP TJA1100 and TJA1101 PHY.
+ 
+-config AT803X_PHY
+-	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
+-	depends on REGULATOR
+-	help
+-	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+-	  QCA8337(Internal qca8k PHY) model
++source "drivers/net/phy/qcom/Kconfig"
+ 
+ config QSEMI_PHY
+ 	tristate "Quality Semiconductor PHYs"
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -34,7 +34,6 @@ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+-obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+ obj-$(CONFIG_BCM54140_PHY)	+= bcm54140.o
+ obj-$(CONFIG_BCM63XX_PHY)	+= bcm63xx.o
+@@ -75,6 +74,7 @@ obj-$(CONFIG_MOTORCOMM_PHY)	+= motorcomm
+ obj-$(CONFIG_NATIONAL_PHY)	+= national.o
+ obj-$(CONFIG_NXP_C45_TJA11XX_PHY)	+= nxp-c45-tja11xx.o
+ obj-$(CONFIG_NXP_TJA11XX_PHY)	+= nxp-tja11xx.o
++obj-y				+= qcom/
+ obj-$(CONFIG_QSEMI_PHY)		+= qsemi.o
+ obj-$(CONFIG_REALTEK_PHY)	+= realtek.o
+ obj-$(CONFIG_RENESAS_PHY)	+= uPD60620.o
+--- /dev/null
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -0,0 +1,7 @@
++# SPDX-License-Identifier: GPL-2.0-only
++config AT803X_PHY
++	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
++	depends on REGULATOR
++	help
++	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
++	  QCA8337(Internal qca8k PHY) model
+--- /dev/null
++++ b/drivers/net/phy/qcom/Makefile
+@@ -0,0 +1,2 @@
++# SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+--- a/drivers/net/phy/at803x.c
++++ /dev/null
+@@ -1,2759 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0+
+-/*
+- * drivers/net/phy/at803x.c
+- *
+- * Driver for Qualcomm Atheros AR803x PHY
+- *
+- * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
+- */
+-
+-#include <linux/phy.h>
+-#include <linux/module.h>
+-#include <linux/string.h>
+-#include <linux/netdevice.h>
+-#include <linux/etherdevice.h>
+-#include <linux/ethtool_netlink.h>
+-#include <linux/bitfield.h>
+-#include <linux/regulator/of_regulator.h>
+-#include <linux/regulator/driver.h>
+-#include <linux/regulator/consumer.h>
+-#include <linux/of.h>
+-#include <linux/phylink.h>
+-#include <linux/sfp.h>
+-#include <dt-bindings/net/qca-ar803x.h>
+-
+-#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
+-#define AT803X_SFC_ASSERT_CRS			BIT(11)
+-#define AT803X_SFC_FORCE_LINK			BIT(10)
+-#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
+-#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
+-#define AT803X_SFC_MANUAL_MDIX			0x1
+-#define AT803X_SFC_MANUAL_MDI			0x0
+-#define AT803X_SFC_SQE_TEST			BIT(2)
+-#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
+-#define AT803X_SFC_DISABLE_JABBER		BIT(0)
+-
+-#define AT803X_SPECIFIC_STATUS			0x11
+-#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
+-#define AT803X_SS_SPEED_1000			2
+-#define AT803X_SS_SPEED_100			1
+-#define AT803X_SS_SPEED_10			0
+-#define AT803X_SS_DUPLEX			BIT(13)
+-#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
+-#define AT803X_SS_MDIX				BIT(6)
+-
+-#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
+-#define QCA808X_SS_SPEED_2500			4
+-
+-#define AT803X_INTR_ENABLE			0x12
+-#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
+-#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
+-#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
+-#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
+-#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
+-#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
+-#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
+-#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
+-#define AT803X_INTR_ENABLE_WOL			BIT(0)
+-
+-#define AT803X_INTR_STATUS			0x13
+-
+-#define AT803X_SMART_SPEED			0x14
+-#define AT803X_SMART_SPEED_ENABLE		BIT(5)
+-#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
+-#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
+-#define AT803X_CDT				0x16
+-#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_ENABLE_TEST			BIT(0)
+-#define AT803X_CDT_STATUS			0x1c
+-#define AT803X_CDT_STATUS_STAT_NORMAL		0
+-#define AT803X_CDT_STATUS_STAT_SHORT		1
+-#define AT803X_CDT_STATUS_STAT_OPEN		2
+-#define AT803X_CDT_STATUS_STAT_FAIL		3
+-#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
+-#define AT803X_LED_CONTROL			0x18
+-
+-#define AT803X_PHY_MMD3_WOL_CTRL		0x8012
+-#define AT803X_WOL_EN				BIT(5)
+-#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+-#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+-#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
+-#define AT803X_REG_CHIP_CONFIG			0x1f
+-#define AT803X_BT_BX_REG_SEL			0x8000
+-
+-#define AT803X_DEBUG_ADDR			0x1D
+-#define AT803X_DEBUG_DATA			0x1E
+-
+-#define AT803X_MODE_CFG_MASK			0x0F
+-#define AT803X_MODE_CFG_BASET_RGMII		0x00
+-#define AT803X_MODE_CFG_BASET_SGMII		0x01
+-#define AT803X_MODE_CFG_BX1000_RGMII_50OHM	0x02
+-#define AT803X_MODE_CFG_BX1000_RGMII_75OHM	0x03
+-#define AT803X_MODE_CFG_BX1000_CONV_50OHM	0x04
+-#define AT803X_MODE_CFG_BX1000_CONV_75OHM	0x05
+-#define AT803X_MODE_CFG_FX100_RGMII_50OHM	0x06
+-#define AT803X_MODE_CFG_FX100_CONV_50OHM	0x07
+-#define AT803X_MODE_CFG_RGMII_AUTO_MDET		0x0B
+-#define AT803X_MODE_CFG_FX100_RGMII_75OHM	0x0E
+-#define AT803X_MODE_CFG_FX100_CONV_75OHM	0x0F
+-
+-#define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
+-#define AT803X_PSSR_MR_AN_COMPLETE		0x0200
+-
+-#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
+-#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
+-#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
+-#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
+-
+-#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
+-#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
+-
+-#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
+-#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
+-#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
+-#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
+-
+-#define AT803X_DEBUG_REG_3C			0x3C
+-
+-#define AT803X_DEBUG_REG_GREEN			0x3D
+-#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
+-
+-#define AT803X_DEBUG_REG_1F			0x1F
+-#define AT803X_DEBUG_PLL_ON			BIT(2)
+-#define AT803X_DEBUG_RGMII_1V8			BIT(3)
+-
+-#define MDIO_AZ_DEBUG				0x800D
+-
+-/* AT803x supports either the XTAL input pad, an internal PLL or the
+- * DSP as clock reference for the clock output pad. The XTAL reference
+- * is only used for 25 MHz output, all other frequencies need the PLL.
+- * The DSP as a clock reference is used in synchronous ethernet
+- * applications.
+- *
+- * By default the PLL is only enabled if there is a link. Otherwise
+- * the PHY will go into low power state and disabled the PLL. You can
+- * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
+- * enabled.
+- */
+-#define AT803X_MMD7_CLK25M			0x8016
+-#define AT803X_CLK_OUT_MASK			GENMASK(4, 2)
+-#define AT803X_CLK_OUT_25MHZ_XTAL		0
+-#define AT803X_CLK_OUT_25MHZ_DSP		1
+-#define AT803X_CLK_OUT_50MHZ_PLL		2
+-#define AT803X_CLK_OUT_50MHZ_DSP		3
+-#define AT803X_CLK_OUT_62_5MHZ_PLL		4
+-#define AT803X_CLK_OUT_62_5MHZ_DSP		5
+-#define AT803X_CLK_OUT_125MHZ_PLL		6
+-#define AT803X_CLK_OUT_125MHZ_DSP		7
+-
+-/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
+- * but doesn't support choosing between XTAL/PLL and DSP.
+- */
+-#define AT8035_CLK_OUT_MASK			GENMASK(4, 3)
+-
+-#define AT803X_CLK_OUT_STRENGTH_MASK		GENMASK(8, 7)
+-#define AT803X_CLK_OUT_STRENGTH_FULL		0
+-#define AT803X_CLK_OUT_STRENGTH_HALF		1
+-#define AT803X_CLK_OUT_STRENGTH_QUARTER		2
+-
+-#define AT803X_DEFAULT_DOWNSHIFT		5
+-#define AT803X_MIN_DOWNSHIFT			2
+-#define AT803X_MAX_DOWNSHIFT			9
+-
+-#define AT803X_MMD3_SMARTEEE_CTL1		0x805b
+-#define AT803X_MMD3_SMARTEEE_CTL2		0x805c
+-#define AT803X_MMD3_SMARTEEE_CTL3		0x805d
+-#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN	BIT(8)
+-
+-#define ATH9331_PHY_ID				0x004dd041
+-#define ATH8030_PHY_ID				0x004dd076
+-#define ATH8031_PHY_ID				0x004dd074
+-#define ATH8032_PHY_ID				0x004dd023
+-#define ATH8035_PHY_ID				0x004dd072
+-#define AT8030_PHY_ID_MASK			0xffffffef
+-
+-#define QCA8081_PHY_ID				0x004dd101
+-
+-#define QCA8327_A_PHY_ID			0x004dd033
+-#define QCA8327_B_PHY_ID			0x004dd034
+-#define QCA8337_PHY_ID				0x004dd036
+-#define QCA9561_PHY_ID				0x004dd042
+-#define QCA8K_PHY_ID_MASK			0xffffffff
+-
+-#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
+-
+-#define AT803X_PAGE_FIBER			0
+-#define AT803X_PAGE_COPPER			1
+-
+-/* don't turn off internal PLL */
+-#define AT803X_KEEP_PLL_ENABLED			BIT(0)
+-#define AT803X_DISABLE_SMARTEEE			BIT(1)
+-
+-/* disable hibernation mode */
+-#define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
+-
+-/* ADC threshold */
+-#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
+-#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
+-#define QCA808X_ADC_THRESHOLD_80MV		0
+-#define QCA808X_ADC_THRESHOLD_100MV		0xf0
+-#define QCA808X_ADC_THRESHOLD_200MV		0x0f
+-#define QCA808X_ADC_THRESHOLD_300MV		0xff
+-
+-/* CLD control */
+-#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
+-#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
+-#define QCA808X_8023AZ_AFE_EN			0x90
+-
+-/* AZ control */
+-#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
+-#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
+-#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
+-#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
+-#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
+-#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
+-#define QCA808X_TOP_OPTION1_DATA		0x0
+-
+-#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
+-#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
+-#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
+-#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
+-#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
+-#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
+-#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
+-#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
+-#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
+-#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
+-#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
+-#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
+-
+-/* master/slave seed config */
+-#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
+-#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
+-#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
+-#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
+-
+-/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
+- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
+- */
+-#define QCA808X_DBG_AN_TEST			0xb
+-#define QCA808X_HIBERNATION_EN			BIT(15)
+-
+-#define QCA808X_CDT_ENABLE_TEST			BIT(15)
+-#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
+-#define QCA808X_CDT_STATUS			BIT(11)
+-#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
+-
+-#define QCA808X_MMD3_CDT_STATUS			0x8064
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
+-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
+-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
+-
+-#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
+-#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
+-#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
+-#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
+-
+-#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
+-#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
+-#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
+-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
+-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
+-
+-#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
+-#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
+-
+-/* NORMAL are MDI with type set to 0 */
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-
+-/* Added for reference of existence but should be handled by wait_for_completion already */
+-#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+-
+-#define QCA808X_MMD7_LED_GLOBAL			0x8073
+-#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+-#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+-/* Values are the same for both BLINK_1 and BLINK_2 */
+-#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
+-#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
+-#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
+-#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
+-#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
+-#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
+-#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
+-#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
+-#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
+-#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
+-#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
+-#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
+-#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
+-#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
+-#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
+-#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
+-#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
+-#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
+-
+-#define QCA808X_MMD7_LED2_CTRL			0x8074
+-#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
+-#define QCA808X_MMD7_LED1_CTRL			0x8076
+-#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
+-#define QCA808X_MMD7_LED0_CTRL			0x8078
+-#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
+-
+-/* LED hw control pattern is the same for every LED */
+-#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
+-#define QCA808X_LED_SPEED2500_ON		BIT(15)
+-#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
+-/* Follow blink trigger even if duplex or speed condition doesn't match */
+-#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
+-#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
+-#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
+-#define QCA808X_LED_TX_BLINK			BIT(10)
+-#define QCA808X_LED_RX_BLINK			BIT(9)
+-#define QCA808X_LED_TX_ON_10MS			BIT(8)
+-#define QCA808X_LED_RX_ON_10MS			BIT(7)
+-#define QCA808X_LED_SPEED1000_ON		BIT(6)
+-#define QCA808X_LED_SPEED100_ON			BIT(5)
+-#define QCA808X_LED_SPEED10_ON			BIT(4)
+-#define QCA808X_LED_COLLISION_BLINK		BIT(3)
+-#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
+-#define QCA808X_LED_SPEED100_BLINK		BIT(1)
+-#define QCA808X_LED_SPEED10_BLINK		BIT(0)
+-
+-#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
+-#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
+-
+-/* LED force ctrl is the same for every LED
+- * No documentation exist for this, not even internal one
+- * with NDA as QCOM gives only info about configuring
+- * hw control pattern rules and doesn't indicate any way
+- * to force the LED to specific mode.
+- * These define comes from reverse and testing and maybe
+- * lack of some info or some info are not entirely correct.
+- * For the basic LED control and hw control these finding
+- * are enough to support LED control in all the required APIs.
+- *
+- * On doing some comparison with implementation with qca807x,
+- * it was found that it's 1:1 equal to it and confirms all the
+- * reverse done. It was also found further specification with the
+- * force mode and the blink modes.
+- */
+-#define QCA808X_LED_FORCE_EN			BIT(15)
+-#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
+-#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
+-#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
+-#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
+-#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
+-
+-#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
+-/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
+- * LED to active high. It's not clear what BIT 3 and BIT 4 does.
+- */
+-#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
+-
+-/* QCA808X 1G chip type */
+-#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
+-#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
+-
+-#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
+-#define QCA8081_PHY_FIFO_RSTN			BIT(11)
+-
+-MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
+-MODULE_AUTHOR("Matus Ujhelyi");
+-MODULE_LICENSE("GPL");
+-
+-enum stat_access_type {
+-	PHY,
+-	MMD
+-};
+-
+-struct at803x_hw_stat {
+-	const char *string;
+-	u8 reg;
+-	u32 mask;
+-	enum stat_access_type access_type;
+-};
+-
+-static struct at803x_hw_stat qca83xx_hw_stats[] = {
+-	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
+-	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
+-	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
+-};
+-
+-struct at803x_ss_mask {
+-	u16 speed_mask;
+-	u8 speed_shift;
+-};
+-
+-struct at803x_priv {
+-	int flags;
+-	u16 clk_25m_reg;
+-	u16 clk_25m_mask;
+-	u8 smarteee_lpi_tw_1g;
+-	u8 smarteee_lpi_tw_100m;
+-	bool is_fiber;
+-	bool is_1000basex;
+-	struct regulator_dev *vddio_rdev;
+-	struct regulator_dev *vddh_rdev;
+-	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
+-	int led_polarity_mode;
+-};
+-
+-struct at803x_context {
+-	u16 bmcr;
+-	u16 advertise;
+-	u16 control1000;
+-	u16 int_enable;
+-	u16 smart_speed;
+-	u16 led_control;
+-};
+-
+-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, data);
+-}
+-
+-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_read(phydev, AT803X_DEBUG_DATA);
+-}
+-
+-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+-				 u16 clear, u16 set)
+-{
+-	u16 val;
+-	int ret;
+-
+-	ret = at803x_debug_reg_read(phydev, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	val = ret & 0xffff;
+-	val &= ~clear;
+-	val |= set;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, val);
+-}
+-
+-static int at803x_write_page(struct phy_device *phydev, int page)
+-{
+-	int mask;
+-	int set;
+-
+-	if (page == AT803X_PAGE_COPPER) {
+-		set = AT803X_BT_BX_REG_SEL;
+-		mask = 0;
+-	} else {
+-		set = 0;
+-		mask = AT803X_BT_BX_REG_SEL;
+-	}
+-
+-	return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
+-}
+-
+-static int at803x_read_page(struct phy_device *phydev)
+-{
+-	int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
+-
+-	if (ccr < 0)
+-		return ccr;
+-
+-	if (ccr & AT803X_BT_BX_REG_SEL)
+-		return AT803X_PAGE_COPPER;
+-
+-	return AT803X_PAGE_FIBER;
+-}
+-
+-static int at803x_enable_rx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
+-				     AT803X_DEBUG_RX_CLK_DLY_EN);
+-}
+-
+-static int at803x_enable_tx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
+-				     AT803X_DEBUG_TX_CLK_DLY_EN);
+-}
+-
+-static int at803x_disable_rx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
+-}
+-
+-static int at803x_disable_tx_delay(struct phy_device *phydev)
+-{
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
+-				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
+-}
+-
+-/* save relevant PHY registers to private copy */
+-static void at803x_context_save(struct phy_device *phydev,
+-				struct at803x_context *context)
+-{
+-	context->bmcr = phy_read(phydev, MII_BMCR);
+-	context->advertise = phy_read(phydev, MII_ADVERTISE);
+-	context->control1000 = phy_read(phydev, MII_CTRL1000);
+-	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
+-	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
+-	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
+-}
+-
+-/* restore relevant PHY registers from private copy */
+-static void at803x_context_restore(struct phy_device *phydev,
+-				   const struct at803x_context *context)
+-{
+-	phy_write(phydev, MII_BMCR, context->bmcr);
+-	phy_write(phydev, MII_ADVERTISE, context->advertise);
+-	phy_write(phydev, MII_CTRL1000, context->control1000);
+-	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
+-	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
+-	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
+-}
+-
+-static int at803x_set_wol(struct phy_device *phydev,
+-			  struct ethtool_wolinfo *wol)
+-{
+-	int ret, irq_enabled;
+-
+-	if (wol->wolopts & WAKE_MAGIC) {
+-		struct net_device *ndev = phydev->attached_dev;
+-		const u8 *mac;
+-		unsigned int i;
+-		static const unsigned int offsets[] = {
+-			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
+-			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
+-			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
+-		};
+-
+-		if (!ndev)
+-			return -ENODEV;
+-
+-		mac = (const u8 *)ndev->dev_addr;
+-
+-		if (!is_valid_ether_addr(mac))
+-			return -EINVAL;
+-
+-		for (i = 0; i < 3; i++)
+-			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
+-				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
+-
+-		/* Enable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
+-		if (ret)
+-			return ret;
+-	} else {
+-		/* Disable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	/* Clear WOL status */
+-	ret = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Check if there are other interrupts except for WOL triggered when PHY is
+-	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
+-	 * be passed up to the interrupt PIN.
+-	 */
+-	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (irq_enabled < 0)
+-		return irq_enabled;
+-
+-	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
+-	if (ret & irq_enabled && !phy_polling_mode(phydev))
+-		phy_trigger_machine(phydev);
+-
+-	return 0;
+-}
+-
+-static void at803x_get_wol(struct phy_device *phydev,
+-			   struct ethtool_wolinfo *wol)
+-{
+-	int value;
+-
+-	wol->supported = WAKE_MAGIC;
+-	wol->wolopts = 0;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (value < 0)
+-		return;
+-
+-	if (value & AT803X_INTR_ENABLE_WOL)
+-		wol->wolopts |= WAKE_MAGIC;
+-}
+-
+-static int qca83xx_get_sset_count(struct phy_device *phydev)
+-{
+-	return ARRAY_SIZE(qca83xx_hw_stats);
+-}
+-
+-static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
+-		strscpy(data + i * ETH_GSTRING_LEN,
+-			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
+-	}
+-}
+-
+-static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
+-{
+-	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
+-	struct at803x_priv *priv = phydev->priv;
+-	int val;
+-	u64 ret;
+-
+-	if (stat.access_type == MMD)
+-		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
+-	else
+-		val = phy_read(phydev, stat.reg);
+-
+-	if (val < 0) {
+-		ret = U64_MAX;
+-	} else {
+-		val = val & stat.mask;
+-		priv->stats[i] += val;
+-		ret = priv->stats[i];
+-	}
+-
+-	return ret;
+-}
+-
+-static void qca83xx_get_stats(struct phy_device *phydev,
+-			      struct ethtool_stats *stats, u64 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
+-		data[i] = qca83xx_get_stat(phydev, i);
+-}
+-
+-static int at803x_suspend(struct phy_device *phydev)
+-{
+-	int value;
+-	int wol_enabled;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
+-
+-	if (wol_enabled)
+-		value = BMCR_ISOLATE;
+-	else
+-		value = BMCR_PDOWN;
+-
+-	phy_modify(phydev, MII_BMCR, 0, value);
+-
+-	return 0;
+-}
+-
+-static int at803x_resume(struct phy_device *phydev)
+-{
+-	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
+-}
+-
+-static int at803x_parse_dt(struct phy_device *phydev)
+-{
+-	struct device_node *node = phydev->mdio.dev.of_node;
+-	struct at803x_priv *priv = phydev->priv;
+-	u32 freq, strength, tw;
+-	unsigned int sel;
+-	int ret;
+-
+-	if (!IS_ENABLED(CONFIG_OF_MDIO))
+-		return 0;
+-
+-	if (of_property_read_bool(node, "qca,disable-smarteee"))
+-		priv->flags |= AT803X_DISABLE_SMARTEEE;
+-
+-	if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
+-		priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
+-
+-	if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
+-		if (!tw || tw > 255) {
+-			phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
+-			return -EINVAL;
+-		}
+-		priv->smarteee_lpi_tw_1g = tw;
+-	}
+-
+-	if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
+-		if (!tw || tw > 255) {
+-			phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
+-			return -EINVAL;
+-		}
+-		priv->smarteee_lpi_tw_100m = tw;
+-	}
+-
+-	ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
+-	if (!ret) {
+-		switch (freq) {
+-		case 25000000:
+-			sel = AT803X_CLK_OUT_25MHZ_XTAL;
+-			break;
+-		case 50000000:
+-			sel = AT803X_CLK_OUT_50MHZ_PLL;
+-			break;
+-		case 62500000:
+-			sel = AT803X_CLK_OUT_62_5MHZ_PLL;
+-			break;
+-		case 125000000:
+-			sel = AT803X_CLK_OUT_125MHZ_PLL;
+-			break;
+-		default:
+-			phydev_err(phydev, "invalid qca,clk-out-frequency\n");
+-			return -EINVAL;
+-		}
+-
+-		priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
+-		priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
+-	}
+-
+-	ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
+-	if (!ret) {
+-		priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
+-		switch (strength) {
+-		case AR803X_STRENGTH_FULL:
+-			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
+-			break;
+-		case AR803X_STRENGTH_HALF:
+-			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
+-			break;
+-		case AR803X_STRENGTH_QUARTER:
+-			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
+-			break;
+-		default:
+-			phydev_err(phydev, "invalid qca,clk-out-strength\n");
+-			return -EINVAL;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int at803x_probe(struct phy_device *phydev)
+-{
+-	struct device *dev = &phydev->mdio.dev;
+-	struct at803x_priv *priv;
+-	int ret;
+-
+-	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+-	if (!priv)
+-		return -ENOMEM;
+-
+-	/* Init LED polarity mode to -1 */
+-	priv->led_polarity_mode = -1;
+-
+-	phydev->priv = priv;
+-
+-	ret = at803x_parse_dt(phydev);
+-	if (ret)
+-		return ret;
+-
+-	return 0;
+-}
+-
+-static int at803x_get_features(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int err;
+-
+-	err = genphy_read_abilities(phydev);
+-	if (err)
+-		return err;
+-
+-	if (phydev->drv->phy_id != ATH8031_PHY_ID)
+-		return 0;
+-
+-	/* AR8031/AR8033 have different status registers
+-	 * for copper and fiber operation. However, the
+-	 * extended status register is the same for both
+-	 * operation modes.
+-	 *
+-	 * As a result of that, ESTATUS_1000_XFULL is set
+-	 * to 1 even when operating in copper TP mode.
+-	 *
+-	 * Remove this mode from the supported link modes
+-	 * when not operating in 1000BaseX mode.
+-	 */
+-	if (!priv->is_1000basex)
+-		linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
+-				   phydev->supported);
+-
+-	return 0;
+-}
+-
+-static int at803x_smarteee_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	u16 mask = 0, val = 0;
+-	int ret;
+-
+-	if (priv->flags & AT803X_DISABLE_SMARTEEE)
+-		return phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-				      AT803X_MMD3_SMARTEEE_CTL3,
+-				      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
+-
+-	if (priv->smarteee_lpi_tw_1g) {
+-		mask |= 0xff00;
+-		val |= priv->smarteee_lpi_tw_1g << 8;
+-	}
+-	if (priv->smarteee_lpi_tw_100m) {
+-		mask |= 0x00ff;
+-		val |= priv->smarteee_lpi_tw_100m;
+-	}
+-	if (!mask)
+-		return 0;
+-
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
+-			     mask, val);
+-	if (ret)
+-		return ret;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
+-			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
+-			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
+-}
+-
+-static int at803x_clk_out_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	if (!priv->clk_25m_mask)
+-		return 0;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
+-			      priv->clk_25m_mask, priv->clk_25m_reg);
+-}
+-
+-static int at8031_pll_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	/* The default after hardware reset is PLL OFF. After a soft reset, the
+-	 * values are retained.
+-	 */
+-	if (priv->flags & AT803X_KEEP_PLL_ENABLED)
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     0, AT803X_DEBUG_PLL_ON);
+-	else
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     AT803X_DEBUG_PLL_ON, 0);
+-}
+-
+-static int at803x_hibernation_mode_config(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	/* The default after hardware reset is hibernation mode enabled. After
+-	 * software reset, the value is retained.
+-	 */
+-	if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
+-		return 0;
+-
+-	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+-					 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
+-}
+-
+-static int at803x_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* The RX and TX delay default is:
+-	 *   after HW reset: RX delay enabled and TX delay disabled
+-	 *   after SW reset: RX delay enabled, while TX delay retains the
+-	 *   value before reset.
+-	 */
+-	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
+-		ret = at803x_enable_rx_delay(phydev);
+-	else
+-		ret = at803x_disable_rx_delay(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
+-		ret = at803x_enable_tx_delay(phydev);
+-	else
+-		ret = at803x_disable_tx_delay(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_smarteee_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_clk_out_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_hibernation_mode_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Ar803x extended next page bit is enabled by default. Cisco
+-	 * multigig switches read this bit and attempt to negotiate 10Gbps
+-	 * rates even if the next page bit is disabled. This is incorrect
+-	 * behaviour but we still need to accommodate it. XNP is only needed
+-	 * for 10Gbps support, so disable XNP.
+-	 */
+-	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
+-}
+-
+-static int at803x_ack_interrupt(struct phy_device *phydev)
+-{
+-	int err;
+-
+-	err = phy_read(phydev, AT803X_INTR_STATUS);
+-
+-	return (err < 0) ? err : 0;
+-}
+-
+-static int at803x_config_intr(struct phy_device *phydev)
+-{
+-	int err;
+-	int value;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-		if (err)
+-			return err;
+-
+-		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
+-		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
+-		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
+-		value |= AT803X_INTR_ENABLE_LINK_FAIL;
+-		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
+-
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
+-	} else {
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
+-		if (err)
+-			return err;
+-
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-	}
+-
+-	return err;
+-}
+-
+-static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
+-{
+-	int irq_status, int_enabled;
+-
+-	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (irq_status < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* Read the current enabled interrupts */
+-	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (int_enabled < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* See if this was one of our enabled interrupts */
+-	if (!(irq_status & int_enabled))
+-		return IRQ_NONE;
+-
+-	phy_trigger_machine(phydev);
+-
+-	return IRQ_HANDLED;
+-}
+-
+-static void at803x_link_change_notify(struct phy_device *phydev)
+-{
+-	/*
+-	 * Conduct a hardware reset for AT8030 every time a link loss is
+-	 * signalled. This is necessary to circumvent a hardware bug that
+-	 * occurs when the cable is unplugged while TX packets are pending
+-	 * in the FIFO. In such cases, the FIFO enters an error mode it
+-	 * cannot recover from by software.
+-	 */
+-	if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
+-		struct at803x_context context;
+-
+-		at803x_context_save(phydev, &context);
+-
+-		phy_device_reset(phydev, 1);
+-		usleep_range(1000, 2000);
+-		phy_device_reset(phydev, 0);
+-		usleep_range(1000, 2000);
+-
+-		at803x_context_restore(phydev, &context);
+-
+-		phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
+-	}
+-}
+-
+-static int at803x_read_specific_status(struct phy_device *phydev,
+-				       struct at803x_ss_mask ss_mask)
+-{
+-	int ss;
+-
+-	/* Read the AT8035 PHY-Specific Status register, which indicates the
+-	 * speed and duplex that the PHY is actually using, irrespective of
+-	 * whether we are in autoneg mode or not.
+-	 */
+-	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
+-	if (ss < 0)
+-		return ss;
+-
+-	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
+-		int sfc, speed;
+-
+-		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
+-		if (sfc < 0)
+-			return sfc;
+-
+-		speed = ss & ss_mask.speed_mask;
+-		speed >>= ss_mask.speed_shift;
+-
+-		switch (speed) {
+-		case AT803X_SS_SPEED_10:
+-			phydev->speed = SPEED_10;
+-			break;
+-		case AT803X_SS_SPEED_100:
+-			phydev->speed = SPEED_100;
+-			break;
+-		case AT803X_SS_SPEED_1000:
+-			phydev->speed = SPEED_1000;
+-			break;
+-		case QCA808X_SS_SPEED_2500:
+-			phydev->speed = SPEED_2500;
+-			break;
+-		}
+-		if (ss & AT803X_SS_DUPLEX)
+-			phydev->duplex = DUPLEX_FULL;
+-		else
+-			phydev->duplex = DUPLEX_HALF;
+-
+-		if (ss & AT803X_SS_MDIX)
+-			phydev->mdix = ETH_TP_MDI_X;
+-		else
+-			phydev->mdix = ETH_TP_MDI;
+-
+-		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
+-		case AT803X_SFC_MANUAL_MDI:
+-			phydev->mdix_ctrl = ETH_TP_MDI;
+-			break;
+-		case AT803X_SFC_MANUAL_MDIX:
+-			phydev->mdix_ctrl = ETH_TP_MDI_X;
+-			break;
+-		case AT803X_SFC_AUTOMATIC_CROSSOVER:
+-			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+-			break;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int at803x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int err, old_link = phydev->link;
+-
+-	/* Update the link, but return if there was an error */
+-	err = genphy_update_link(phydev);
+-	if (err)
+-		return err;
+-
+-	/* why bother the PHY if nothing can have changed */
+-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+-		return 0;
+-
+-	phydev->speed = SPEED_UNKNOWN;
+-	phydev->duplex = DUPLEX_UNKNOWN;
+-	phydev->pause = 0;
+-	phydev->asym_pause = 0;
+-
+-	err = genphy_read_lpa(phydev);
+-	if (err < 0)
+-		return err;
+-
+-	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
+-	err = at803x_read_specific_status(phydev, ss_mask);
+-	if (err < 0)
+-		return err;
+-
+-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
+-		phy_resolve_aneg_pause(phydev);
+-
+-	return 0;
+-}
+-
+-static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
+-{
+-	u16 val;
+-
+-	switch (ctrl) {
+-	case ETH_TP_MDI:
+-		val = AT803X_SFC_MANUAL_MDI;
+-		break;
+-	case ETH_TP_MDI_X:
+-		val = AT803X_SFC_MANUAL_MDIX;
+-		break;
+-	case ETH_TP_MDI_AUTO:
+-		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
+-		break;
+-	default:
+-		return 0;
+-	}
+-
+-	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
+-			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
+-			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
+-}
+-
+-static int at803x_prepare_config_aneg(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Changes of the midx bits are disruptive to the normal operation;
+-	 * therefore any changes to these registers must be followed by a
+-	 * software reset to take effect.
+-	 */
+-	if (ret == 1) {
+-		ret = genphy_soft_reset(phydev);
+-		if (ret < 0)
+-			return ret;
+-	}
+-
+-	return 0;
+-}
+-
+-static int at803x_config_aneg(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int ret;
+-
+-	ret = at803x_prepare_config_aneg(phydev);
+-	if (ret)
+-		return ret;
+-
+-	if (priv->is_1000basex)
+-		return genphy_c37_config_aneg(phydev);
+-
+-	return genphy_config_aneg(phydev);
+-}
+-
+-static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
+-{
+-	int val;
+-
+-	val = phy_read(phydev, AT803X_SMART_SPEED);
+-	if (val < 0)
+-		return val;
+-
+-	if (val & AT803X_SMART_SPEED_ENABLE)
+-		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
+-	else
+-		*d = DOWNSHIFT_DEV_DISABLE;
+-
+-	return 0;
+-}
+-
+-static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
+-{
+-	u16 mask, set;
+-	int ret;
+-
+-	switch (cnt) {
+-	case DOWNSHIFT_DEV_DEFAULT_COUNT:
+-		cnt = AT803X_DEFAULT_DOWNSHIFT;
+-		fallthrough;
+-	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
+-		set = AT803X_SMART_SPEED_ENABLE |
+-		      AT803X_SMART_SPEED_BYPASS_TIMER |
+-		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
+-		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
+-		break;
+-	case DOWNSHIFT_DEV_DISABLE:
+-		set = 0;
+-		mask = AT803X_SMART_SPEED_ENABLE |
+-		       AT803X_SMART_SPEED_BYPASS_TIMER;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
+-
+-	/* After changing the smart speed settings, we need to perform a
+-	 * software reset, use phy_init_hw() to make sure we set the
+-	 * reapply any values which might got lost during software reset.
+-	 */
+-	if (ret == 1)
+-		ret = phy_init_hw(phydev);
+-
+-	return ret;
+-}
+-
+-static int at803x_get_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_get_downshift(phydev, data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int at803x_set_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, const void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_set_downshift(phydev, *(const u8 *)data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int at803x_cable_test_result_trans(u16 status)
+-{
+-	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
+-	case AT803X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case AT803X_CDT_STATUS_STAT_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case AT803X_CDT_STATUS_STAT_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case AT803X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static bool at803x_cdt_test_failed(u16 status)
+-{
+-	return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
+-		AT803X_CDT_STATUS_STAT_FAIL;
+-}
+-
+-static bool at803x_cdt_fault_length_valid(u16 status)
+-{
+-	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
+-	case AT803X_CDT_STATUS_STAT_OPEN:
+-	case AT803X_CDT_STATUS_STAT_SHORT:
+-		return true;
+-	}
+-	return false;
+-}
+-
+-static int at803x_cdt_fault_length(int dt)
+-{
+-	/* According to the datasheet the distance to the fault is
+-	 * DELTA_TIME * 0.824 meters.
+-	 *
+-	 * The author suspect the correct formula is:
+-	 *
+-	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
+-	 *
+-	 * where c is the speed of light, VF is the velocity factor of
+-	 * the twisted pair cable, 125MHz the counter frequency and
+-	 * we need to divide by 2 because the hardware will measure the
+-	 * round trip time to the fault and back to the PHY.
+-	 *
+-	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
+-	 * datasheet.
+-	 */
+-	return (dt * 824) / 10;
+-}
+-
+-static int at803x_cdt_start(struct phy_device *phydev,
+-			    u32 cdt_start)
+-{
+-	return phy_write(phydev, AT803X_CDT, cdt_start);
+-}
+-
+-static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+-					  u32 cdt_en)
+-{
+-	int val, ret;
+-
+-	/* One test run takes about 25ms */
+-	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
+-				    !(val & cdt_en),
+-				    30000, 100000, true);
+-
+-	return ret < 0 ? ret : 0;
+-}
+-
+-static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
+-{
+-	static const int ethtool_pair[] = {
+-		ETHTOOL_A_CABLE_PAIR_A,
+-		ETHTOOL_A_CABLE_PAIR_B,
+-		ETHTOOL_A_CABLE_PAIR_C,
+-		ETHTOOL_A_CABLE_PAIR_D,
+-	};
+-	int ret, val;
+-
+-	val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
+-	      AT803X_CDT_ENABLE_TEST;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read(phydev, AT803X_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	if (at803x_cdt_test_failed(val))
+-		return 0;
+-
+-	ethnl_cable_test_result(phydev, ethtool_pair[pair],
+-				at803x_cable_test_result_trans(val));
+-
+-	if (at803x_cdt_fault_length_valid(val)) {
+-		val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
+-		ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
+-					      at803x_cdt_fault_length(val));
+-	}
+-
+-	return 1;
+-}
+-
+-static int at803x_cable_test_get_status(struct phy_device *phydev,
+-					bool *finished, unsigned long pair_mask)
+-{
+-	int retries = 20;
+-	int pair, ret;
+-
+-	*finished = false;
+-
+-	/* According to the datasheet the CDT can be performed when
+-	 * there is no link partner or when the link partner is
+-	 * auto-negotiating. Starting the test will restart the AN
+-	 * automatically. It seems that doing this repeatedly we will
+-	 * get a slot where our link partner won't disturb our
+-	 * measurement.
+-	 */
+-	while (pair_mask && retries--) {
+-		for_each_set_bit(pair, &pair_mask, 4) {
+-			ret = at803x_cable_test_one_pair(phydev, pair);
+-			if (ret < 0)
+-				return ret;
+-			if (ret)
+-				clear_bit(pair, &pair_mask);
+-		}
+-		if (pair_mask)
+-			msleep(250);
+-	}
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+-
+-static void at803x_cable_test_autoneg(struct phy_device *phydev)
+-{
+-	/* Enable auto-negotiation, but advertise no capabilities, no link
+-	 * will be established. A restart of the auto-negotiation is not
+-	 * required, because the cable test will automatically break the link.
+-	 */
+-	phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
+-	phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
+-}
+-
+-static int at803x_cable_test_start(struct phy_device *phydev)
+-{
+-	at803x_cable_test_autoneg(phydev);
+-	/* we do all the (time consuming) work later */
+-	return 0;
+-}
+-
+-static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
+-					    unsigned int selector)
+-{
+-	struct phy_device *phydev = rdev_get_drvdata(rdev);
+-
+-	if (selector)
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     0, AT803X_DEBUG_RGMII_1V8);
+-	else
+-		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
+-					     AT803X_DEBUG_RGMII_1V8, 0);
+-}
+-
+-static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
+-{
+-	struct phy_device *phydev = rdev_get_drvdata(rdev);
+-	int val;
+-
+-	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
+-	if (val < 0)
+-		return val;
+-
+-	return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
+-}
+-
+-static const struct regulator_ops vddio_regulator_ops = {
+-	.list_voltage = regulator_list_voltage_table,
+-	.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
+-	.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
+-};
+-
+-static const unsigned int vddio_voltage_table[] = {
+-	1500000,
+-	1800000,
+-};
+-
+-static const struct regulator_desc vddio_desc = {
+-	.name = "vddio",
+-	.of_match = of_match_ptr("vddio-regulator"),
+-	.n_voltages = ARRAY_SIZE(vddio_voltage_table),
+-	.volt_table = vddio_voltage_table,
+-	.ops = &vddio_regulator_ops,
+-	.type = REGULATOR_VOLTAGE,
+-	.owner = THIS_MODULE,
+-};
+-
+-static const struct regulator_ops vddh_regulator_ops = {
+-};
+-
+-static const struct regulator_desc vddh_desc = {
+-	.name = "vddh",
+-	.of_match = of_match_ptr("vddh-regulator"),
+-	.n_voltages = 1,
+-	.fixed_uV = 2500000,
+-	.ops = &vddh_regulator_ops,
+-	.type = REGULATOR_VOLTAGE,
+-	.owner = THIS_MODULE,
+-};
+-
+-static int at8031_register_regulators(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	struct device *dev = &phydev->mdio.dev;
+-	struct regulator_config config = { };
+-
+-	config.dev = dev;
+-	config.driver_data = phydev;
+-
+-	priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
+-	if (IS_ERR(priv->vddio_rdev)) {
+-		phydev_err(phydev, "failed to register VDDIO regulator\n");
+-		return PTR_ERR(priv->vddio_rdev);
+-	}
+-
+-	priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
+-	if (IS_ERR(priv->vddh_rdev)) {
+-		phydev_err(phydev, "failed to register VDDH regulator\n");
+-		return PTR_ERR(priv->vddh_rdev);
+-	}
+-
+-	return 0;
+-}
+-
+-static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
+-{
+-	struct phy_device *phydev = upstream;
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
+-	DECLARE_PHY_INTERFACE_MASK(interfaces);
+-	phy_interface_t iface;
+-
+-	linkmode_zero(phy_support);
+-	phylink_set(phy_support, 1000baseX_Full);
+-	phylink_set(phy_support, 1000baseT_Full);
+-	phylink_set(phy_support, Autoneg);
+-	phylink_set(phy_support, Pause);
+-	phylink_set(phy_support, Asym_Pause);
+-
+-	linkmode_zero(sfp_support);
+-	sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
+-	/* Some modules support 10G modes as well as others we support.
+-	 * Mask out non-supported modes so the correct interface is picked.
+-	 */
+-	linkmode_and(sfp_support, phy_support, sfp_support);
+-
+-	if (linkmode_empty(sfp_support)) {
+-		dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
+-		return -EINVAL;
+-	}
+-
+-	iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
+-
+-	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
+-	 * interface for use with SFP modules.
+-	 * However, some copper modules detected as having a preferred SGMII
+-	 * interface do default to and function in 1000Base-X mode, so just
+-	 * print a warning and allow such modules, as they may have some chance
+-	 * of working.
+-	 */
+-	if (iface == PHY_INTERFACE_MODE_SGMII)
+-		dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
+-	else if (iface != PHY_INTERFACE_MODE_1000BASEX)
+-		return -EINVAL;
+-
+-	return 0;
+-}
+-
+-static const struct sfp_upstream_ops at8031_sfp_ops = {
+-	.attach = phy_sfp_attach,
+-	.detach = phy_sfp_detach,
+-	.module_insert = at8031_sfp_insert,
+-};
+-
+-static int at8031_parse_dt(struct phy_device *phydev)
+-{
+-	struct device_node *node = phydev->mdio.dev.of_node;
+-	struct at803x_priv *priv = phydev->priv;
+-	int ret;
+-
+-	if (of_property_read_bool(node, "qca,keep-pll-enabled"))
+-		priv->flags |= AT803X_KEEP_PLL_ENABLED;
+-
+-	ret = at8031_register_regulators(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
+-						 "vddio");
+-	if (ret) {
+-		phydev_err(phydev, "failed to get VDDIO regulator\n");
+-		return ret;
+-	}
+-
+-	/* Only AR8031/8033 support 1000Base-X for SFP modules */
+-	return phy_sfp_probe(phydev, &at8031_sfp_ops);
+-}
+-
+-static int at8031_probe(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int mode_cfg;
+-	int ccr;
+-	int ret;
+-
+-	ret = at803x_probe(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
+-	 * options.
+-	 */
+-	ret = at8031_parse_dt(phydev);
+-	if (ret)
+-		return ret;
+-
+-	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
+-	if (ccr < 0)
+-		return ccr;
+-	mode_cfg = ccr & AT803X_MODE_CFG_MASK;
+-
+-	switch (mode_cfg) {
+-	case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
+-	case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
+-		priv->is_1000basex = true;
+-		fallthrough;
+-	case AT803X_MODE_CFG_FX100_RGMII_50OHM:
+-	case AT803X_MODE_CFG_FX100_RGMII_75OHM:
+-		priv->is_fiber = true;
+-		break;
+-	}
+-
+-	/* Disable WoL in 1588 register which is enabled
+-	 * by default
+-	 */
+-	return phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-			      AT803X_PHY_MMD3_WOL_CTRL,
+-			      AT803X_WOL_EN, 0);
+-}
+-
+-static int at8031_config_init(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int ret;
+-
+-	/* Some bootloaders leave the fiber page selected.
+-	 * Switch to the appropriate page (fiber or copper), as otherwise we
+-	 * read the PHY capabilities from the wrong page.
+-	 */
+-	phy_lock_mdio_bus(phydev);
+-	ret = at803x_write_page(phydev,
+-				priv->is_fiber ? AT803X_PAGE_FIBER :
+-						 AT803X_PAGE_COPPER);
+-	phy_unlock_mdio_bus(phydev);
+-	if (ret)
+-		return ret;
+-
+-	ret = at8031_pll_config(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	return at803x_config_init(phydev);
+-}
+-
+-static int at8031_set_wol(struct phy_device *phydev,
+-			  struct ethtool_wolinfo *wol)
+-{
+-	int ret;
+-
+-	/* First setup MAC address and enable WOL interrupt */
+-	ret = at803x_set_wol(phydev, wol);
+-	if (ret)
+-		return ret;
+-
+-	if (wol->wolopts & WAKE_MAGIC)
+-		/* Enable WOL function for 1588 */
+-		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-				     AT803X_PHY_MMD3_WOL_CTRL,
+-				     0, AT803X_WOL_EN);
+-	else
+-		/* Disable WoL function for 1588 */
+-		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
+-				     AT803X_PHY_MMD3_WOL_CTRL,
+-				     AT803X_WOL_EN, 0);
+-
+-	return ret;
+-}
+-
+-static int at8031_config_intr(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	int err, value = 0;
+-
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
+-	    priv->is_fiber) {
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-		if (err)
+-			return err;
+-
+-		value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
+-		value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
+-
+-		err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
+-		if (err)
+-			return err;
+-	}
+-
+-	return at803x_config_intr(phydev);
+-}
+-
+-/* AR8031 and AR8033 share the same read status logic */
+-static int at8031_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	if (priv->is_1000basex)
+-		return genphy_c37_read_status(phydev);
+-
+-	return at803x_read_status(phydev);
+-}
+-
+-/* AR8031 and AR8035 share the same cable test get status reg */
+-static int at8031_cable_test_get_status(struct phy_device *phydev,
+-					bool *finished)
+-{
+-	return at803x_cable_test_get_status(phydev, finished, 0xf);
+-}
+-
+-/* AR8031 and AR8035 share the same cable test start logic */
+-static int at8031_cable_test_start(struct phy_device *phydev)
+-{
+-	at803x_cable_test_autoneg(phydev);
+-	phy_write(phydev, MII_CTRL1000, 0);
+-	/* we do all the (time consuming) work later */
+-	return 0;
+-}
+-
+-/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
+-static int at8032_cable_test_get_status(struct phy_device *phydev,
+-					bool *finished)
+-{
+-	return at803x_cable_test_get_status(phydev, finished, 0x3);
+-}
+-
+-static int at8035_parse_dt(struct phy_device *phydev)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-
+-	/* Mask is set by the generic at803x_parse_dt
+-	 * if property is set. Assume property is set
+-	 * with the mask not zero.
+-	 */
+-	if (priv->clk_25m_mask) {
+-		/* Fixup for the AR8030/AR8035. This chip has another mask and
+-		 * doesn't support the DSP reference. Eg. the lowest bit of the
+-		 * mask. The upper two bits select the same frequencies. Mask
+-		 * the lowest bit here.
+-		 *
+-		 * Warning:
+-		 *   There was no datasheet for the AR8030 available so this is
+-		 *   just a guess. But the AR8035 is listed as pin compatible
+-		 *   to the AR8030 so there might be a good chance it works on
+-		 *   the AR8030 too.
+-		 */
+-		priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
+-		priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
+-	}
+-
+-	return 0;
+-}
+-
+-/* AR8030 and AR8035 shared the same special mask for clk_25m */
+-static int at8035_probe(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = at803x_probe(phydev);
+-	if (ret)
+-		return ret;
+-
+-	return at8035_parse_dt(phydev);
+-}
+-
+-static int qca83xx_config_init(struct phy_device *phydev)
+-{
+-	u8 switch_revision;
+-
+-	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
+-
+-	switch (switch_revision) {
+-	case 1:
+-		/* For 100M waveform */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
+-		/* Turn on Gigabit clock */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
+-		break;
+-
+-	case 2:
+-		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
+-		fallthrough;
+-	case 4:
+-		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
+-		break;
+-	}
+-
+-	/* Following original QCA sourcecode set port to prefer master */
+-	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
+-
+-	return 0;
+-}
+-
+-static int qca8327_config_init(struct phy_device *phydev)
+-{
+-	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
+-	 * Disable on init and enable only with 100m speed following
+-	 * qca original source code.
+-	 */
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-
+-	return qca83xx_config_init(phydev);
+-}
+-
+-static void qca83xx_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
+-	if (phydev->state == PHY_RUNNING) {
+-		if (phydev->speed == SPEED_100)
+-			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-					      QCA8327_DEBUG_MANU_CTRL_EN,
+-					      QCA8327_DEBUG_MANU_CTRL_EN);
+-	} else {
+-		/* Reset DAC Amplitude adjustment */
+-		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-	}
+-}
+-
+-static int qca83xx_resume(struct phy_device *phydev)
+-{
+-	int ret, val;
+-
+-	/* Skip reset if not suspended */
+-	if (!phydev->suspended)
+-		return 0;
+-
+-	/* Reinit the port, reset values set by suspend */
+-	qca83xx_config_init(phydev);
+-
+-	/* Reset the port on port resume */
+-	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+-
+-	/* On resume from suspend the switch execute a reset and
+-	 * restart auto-negotiation. Wait for reset to complete.
+-	 */
+-	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+-				    50000, 600000, true);
+-	if (ret)
+-		return ret;
+-
+-	usleep_range(1000, 2000);
+-
+-	return 0;
+-}
+-
+-static int qca83xx_suspend(struct phy_device *phydev)
+-{
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
+-			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
+-
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+-			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
+-			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
+-
+-	return 0;
+-}
+-
+-static int qca8337_suspend(struct phy_device *phydev)
+-{
+-	/* Only QCA8337 support actual suspend. */
+-	genphy_suspend(phydev);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+-static int qca8327_suspend(struct phy_device *phydev)
+-{
+-	u16 mask = 0;
+-
+-	/* QCA8327 cause port unreliability when phy suspend
+-	 * is set.
+-	 */
+-	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
+-	phy_modify(phydev, MII_BMCR, mask, 0);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+-static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Enable fast retrain */
+-	ret = genphy_c45_fast_retrain(phydev, true);
+-	if (ret)
+-		return ret;
+-
+-	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
+-		      QCA808X_TOP_OPTION1_DATA);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
+-		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
+-		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
+-		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
+-		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
+-		      QCA808X_MMD3_DEBUG_1_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
+-		      QCA808X_MMD3_DEBUG_4_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
+-		      QCA808X_MMD3_DEBUG_5_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
+-		      QCA808X_MMD3_DEBUG_3_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
+-		      QCA808X_MMD3_DEBUG_6_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
+-		      QCA808X_MMD3_DEBUG_2_VALUE);
+-
+-	return 0;
+-}
+-
+-static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
+-{
+-	u16 seed_value;
+-
+-	if (!enable)
+-		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
+-
+-	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
+-			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
+-			QCA808X_MASTER_SLAVE_SEED_ENABLE);
+-}
+-
+-static bool qca808x_is_prefer_master(struct phy_device *phydev)
+-{
+-	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
+-		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
+-}
+-
+-static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
+-{
+-	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-}
+-
+-static int qca808x_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Active adc&vga on 802.3az for the link 1000M and 100M */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
+-			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
+-	if (ret)
+-		return ret;
+-
+-	/* Adjust the threshold on 802.3az for the link 1000M */
+-	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
+-			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
+-			    QCA808X_MMD3_AZ_TRAINING_VAL);
+-	if (ret)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-		/* Config the fast retrain for the link 2500M */
+-		ret = qca808x_phy_fast_retrain_config(phydev);
+-		if (ret)
+-			return ret;
+-
+-		ret = genphy_read_master_slave(phydev);
+-		if (ret < 0)
+-			return ret;
+-
+-		if (!qca808x_is_prefer_master(phydev)) {
+-			/* Enable seed and configure lower ramdom seed to make phy
+-			 * linked as slave mode.
+-			 */
+-			ret = qca808x_phy_ms_seed_enable(phydev, true);
+-			if (ret)
+-				return ret;
+-		}
+-	}
+-
+-	/* Configure adc threshold as 100mv for the link 10M */
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
+-				     QCA808X_ADC_THRESHOLD_MASK,
+-				     QCA808X_ADC_THRESHOLD_100MV);
+-}
+-
+-static int qca808x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int ret;
+-
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
+-	if (ret < 0)
+-		return ret;
+-
+-	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
+-			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
+-
+-	ret = genphy_read_status(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* qca8081 takes the different bits for speed value from at803x */
+-	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
+-	ret = at803x_read_specific_status(phydev, ss_mask);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (phydev->link) {
+-		if (phydev->speed == SPEED_2500)
+-			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+-		else
+-			phydev->interface = PHY_INTERFACE_MODE_SGMII;
+-	} else {
+-		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
+-		 * except for master/slave configuration fault detected or the master mode
+-		 * preferred.
+-		 *
+-		 * the reason for not putting this code into the function link_change_notify is
+-		 * the corner case where the link partner is also the qca8081 PHY and the seed
+-		 * value is configured as the same value, the link can't be up and no link change
+-		 * occurs.
+-		 */
+-		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
+-			    qca808x_is_prefer_master(phydev)) {
+-				qca808x_phy_ms_seed_enable(phydev, false);
+-			} else {
+-				qca808x_phy_ms_seed_enable(phydev, true);
+-			}
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_soft_reset(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_soft_reset(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
+-		ret = qca808x_phy_ms_seed_enable(phydev, true);
+-
+-	return ret;
+-}
+-
+-static bool qca808x_cdt_fault_length_valid(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return true;
+-	default:
+-		return false;
+-	}
+-}
+-
+-static int qca808x_cable_test_result_trans(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
+-				    int result)
+-{
+-	int val;
+-	u32 cdt_length_reg = 0;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
+-	else
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
+-
+-	return at803x_cdt_fault_length(val);
+-}
+-
+-static int qca808x_cable_test_start(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* perform CDT with the following configs:
+-	 * 1. disable hibernation.
+-	 * 2. force PHY working in MDI mode.
+-	 * 3. for PHY working in 1000BaseT.
+-	 * 4. configure the threshold.
+-	 */
+-
+-	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
+-	phydev->duplex = DUPLEX_FULL;
+-	phydev->speed = SPEED_1000;
+-	ret = genphy_c45_pma_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = genphy_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* configure the thresholds for open, short, pair ok test */
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
+-					      u16 status)
+-{
+-	int length, result;
+-	u16 pair_code;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	result = qca808x_cable_test_result_trans(pair_code);
+-	ethnl_cable_test_result(phydev, pair, result);
+-
+-	if (qca808x_cdt_fault_length_valid(pair_code)) {
+-		length = qca808x_cdt_fault_length(phydev, pair, result);
+-		ethnl_cable_test_fault_length(phydev, pair, length);
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
+-{
+-	int ret, val;
+-
+-	*finished = false;
+-
+-	val = QCA808X_CDT_ENABLE_TEST |
+-	      QCA808X_CDT_LENGTH_UNIT;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
+-	if (ret)
+-		return ret;
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+-
+-static int qca808x_get_features(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_c45_pma_read_abilities(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The autoneg ability is not existed in bit3 of MMD7.1,
+-	 * but it is supported by qca808x PHY, so we add it here
+-	 * manually.
+-	 */
+-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
+-
+-	/* As for the qca8081 1G version chip, the 2500baseT ability is also
+-	 * existed in the bit0 of MMD1.21, we need to remove it manually if
+-	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
+-	 */
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+-		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-
+-	return 0;
+-}
+-
+-static int qca808x_config_aneg(struct phy_device *phydev)
+-{
+-	int phy_ctrl = 0;
+-	int ret;
+-
+-	ret = at803x_prepare_config_aneg(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The reg MII_BMCR also needs to be configured for force mode, the
+-	 * genphy_config_aneg is also needed.
+-	 */
+-	if (phydev->autoneg == AUTONEG_DISABLE)
+-		genphy_c45_pma_setup_forced(phydev);
+-
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
+-		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
+-
+-	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
+-				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	return __genphy_config_aneg(phydev, ret);
+-}
+-
+-static void qca808x_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Assert interface sgmii fifo on link down, deassert it on link up,
+-	 * the interface device address is always phy address added by 1.
+-	 */
+-	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
+-				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
+-				   QCA8081_PHY_FIFO_RSTN,
+-				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
+-}
+-
+-static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
+-				    u16 *offload_trigger)
+-{
+-	/* Parsing specific to netdev trigger */
+-	if (test_bit(TRIGGER_NETDEV_TX, &rules))
+-		*offload_trigger |= QCA808X_LED_TX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_RX, &rules))
+-		*offload_trigger |= QCA808X_LED_RX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED10_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED100_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
+-	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
+-	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
+-
+-	if (rules && !*offload_trigger)
+-		return -EOPNOTSUPP;
+-
+-	/* Enable BLINK_CHECK_BYPASS by default to make the LED
+-	 * blink even with duplex or speed mode not enabled.
+-	 */
+-	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+-				       unsigned long rules)
+-{
+-	u16 offload_trigger = 0;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-}
+-
+-static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
+-				      unsigned long rules)
+-{
+-	u16 reg, offload_trigger = 0;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_led_hw_control_enable(phydev, index);
+-	if (ret)
+-		return ret;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_PATTERN_MASK,
+-			      offload_trigger);
+-}
+-
+-static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return false;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-
+-	return !(val & QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
+-				      unsigned long *rules)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	/* Check if we have hw control enabled */
+-	if (qca808x_led_hw_control_status(phydev, index))
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-	if (val & QCA808X_LED_TX_BLINK)
+-		set_bit(TRIGGER_NETDEV_TX, rules);
+-	if (val & QCA808X_LED_RX_BLINK)
+-		set_bit(TRIGGER_NETDEV_RX, rules);
+-	if (val & QCA808X_LED_SPEED10_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_10, rules);
+-	if (val & QCA808X_LED_SPEED100_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_100, rules);
+-	if (val & QCA808X_LED_SPEED1000_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+-	if (val & QCA808X_LED_SPEED2500_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
+-	if (val & QCA808X_LED_HALF_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
+-	if (val & QCA808X_LED_FULL_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_PATTERN_MASK);
+-}
+-
+-static int qca808x_led_brightness_set(struct phy_device *phydev,
+-				      u8 index, enum led_brightness value)
+-{
+-	u16 reg;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	if (!value) {
+-		ret = qca808x_led_hw_control_reset(phydev, index);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF);
+-}
+-
+-static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
+-				 unsigned long *delay_on,
+-				 unsigned long *delay_off)
+-{
+-	int ret;
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	/* Set blink to 50% off, 50% on at 4Hz by default */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
+-			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
+-			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
+-	if (ret)
+-		return ret;
+-
+-	/* We use BLINK_1 for normal blinking */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
+-	if (ret)
+-		return ret;
+-
+-	/* We set blink to 4Hz, aka 250ms */
+-	*delay_on = 250 / 2;
+-	*delay_off = 250 / 2;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
+-				    unsigned long modes)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	bool active_low = false;
+-	u32 mode;
+-
+-	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+-		switch (mode) {
+-		case PHY_LED_ACTIVE_LOW:
+-			active_low = true;
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
+-	}
+-
+-	/* PHY polarity is global and can't be set per LED.
+-	 * To detect this, check if last requested polarity mode
+-	 * match the new one.
+-	 */
+-	if (priv->led_polarity_mode >= 0 &&
+-	    priv->led_polarity_mode != active_low) {
+-		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Save the last PHY polarity mode */
+-	priv->led_polarity_mode = active_low;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN,
+-			      QCA808X_MMD7_LED_POLARITY_CTRL,
+-			      QCA808X_LED_ACTIVE_HIGH,
+-			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
+-}
+-
+-static struct phy_driver at803x_driver[] = {
+-{
+-	/* Qualcomm Atheros AR8035 */
+-	PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
+-	.name			= "Qualcomm Atheros AR8035",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at8035_probe,
+-	.config_aneg		= at803x_config_aneg,
+-	.config_init		= at803x_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	/* PHY_GBIT_FEATURES */
+-	.read_status		= at803x_read_status,
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.cable_test_start	= at8031_cable_test_start,
+-	.cable_test_get_status	= at8031_cable_test_get_status,
+-}, {
+-	/* Qualcomm Atheros AR8030 */
+-	.phy_id			= ATH8030_PHY_ID,
+-	.name			= "Qualcomm Atheros AR8030",
+-	.phy_id_mask		= AT8030_PHY_ID_MASK,
+-	.probe			= at8035_probe,
+-	.config_init		= at803x_config_init,
+-	.link_change_notify	= at803x_link_change_notify,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-}, {
+-	/* Qualcomm Atheros AR8031/AR8033 */
+-	PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
+-	.name			= "Qualcomm Atheros AR8031/AR8033",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at8031_probe,
+-	.config_init		= at8031_config_init,
+-	.config_aneg		= at803x_config_aneg,
+-	.soft_reset		= genphy_soft_reset,
+-	.set_wol		= at8031_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	.read_page		= at803x_read_page,
+-	.write_page		= at803x_write_page,
+-	.get_features		= at803x_get_features,
+-	.read_status		= at8031_read_status,
+-	.config_intr		= at8031_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.cable_test_start	= at8031_cable_test_start,
+-	.cable_test_get_status	= at8031_cable_test_get_status,
+-}, {
+-	/* Qualcomm Atheros AR8032 */
+-	PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
+-	.name			= "Qualcomm Atheros AR8032",
+-	.probe			= at803x_probe,
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.config_init		= at803x_config_init,
+-	.link_change_notify	= at803x_link_change_notify,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.cable_test_start	= at803x_cable_test_start,
+-	.cable_test_get_status	= at8032_cable_test_get_status,
+-}, {
+-	/* ATHEROS AR9331 */
+-	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
+-	.name			= "Qualcomm Atheros AR9331 built-in PHY",
+-	.probe			= at803x_probe,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.cable_test_start	= at803x_cable_test_start,
+-	.cable_test_get_status	= at8032_cable_test_get_status,
+-	.read_status		= at803x_read_status,
+-	.soft_reset		= genphy_soft_reset,
+-	.config_aneg		= at803x_config_aneg,
+-}, {
+-	/* Qualcomm Atheros QCA9561 */
+-	PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
+-	.name			= "Qualcomm Atheros QCA9561 built-in PHY",
+-	.probe			= at803x_probe,
+-	.suspend		= at803x_suspend,
+-	.resume			= at803x_resume,
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	/* PHY_BASIC_FEATURES */
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.cable_test_start	= at803x_cable_test_start,
+-	.cable_test_get_status	= at8032_cable_test_get_status,
+-	.read_status		= at803x_read_status,
+-	.soft_reset		= genphy_soft_reset,
+-	.config_aneg		= at803x_config_aneg,
+-}, {
+-	/* QCA8337 */
+-	.phy_id			= QCA8337_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8337 internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca83xx_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8337_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-A from switch QCA8327-AL1A */
+-	.phy_id			= QCA8327_A_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-A internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-B from switch QCA8327-BL1A */
+-	.phy_id			= QCA8327_B_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-B internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* Qualcomm QCA8081 */
+-	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
+-	.name			= "Qualcomm QCA8081",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at803x_probe,
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.get_features		= qca808x_get_features,
+-	.config_aneg		= qca808x_config_aneg,
+-	.suspend		= genphy_suspend,
+-	.resume			= genphy_resume,
+-	.read_status		= qca808x_read_status,
+-	.config_init		= qca808x_config_init,
+-	.soft_reset		= qca808x_soft_reset,
+-	.cable_test_start	= qca808x_cable_test_start,
+-	.cable_test_get_status	= qca808x_cable_test_get_status,
+-	.link_change_notify	= qca808x_link_change_notify,
+-	.led_brightness_set	= qca808x_led_brightness_set,
+-	.led_blink_set		= qca808x_led_blink_set,
+-	.led_hw_is_supported	= qca808x_led_hw_is_supported,
+-	.led_hw_control_set	= qca808x_led_hw_control_set,
+-	.led_hw_control_get	= qca808x_led_hw_control_get,
+-	.led_polarity_set	= qca808x_led_polarity_set,
+-}, };
+-
+-module_phy_driver(at803x_driver);
+-
+-static struct mdio_device_id __maybe_unused atheros_tbl[] = {
+-	{ ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
+-	{ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+-	{ }
+-};
+-
+-MODULE_DEVICE_TABLE(mdio, atheros_tbl);
+--- /dev/null
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -0,0 +1,2759 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * drivers/net/phy/at803x.c
++ *
++ * Driver for Qualcomm Atheros AR803x PHY
++ *
++ * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
++ */
++
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/string.h>
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++#include <linux/ethtool_netlink.h>
++#include <linux/bitfield.h>
++#include <linux/regulator/of_regulator.h>
++#include <linux/regulator/driver.h>
++#include <linux/regulator/consumer.h>
++#include <linux/of.h>
++#include <linux/phylink.h>
++#include <linux/sfp.h>
++#include <dt-bindings/net/qca-ar803x.h>
++
++#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
++#define AT803X_SFC_ASSERT_CRS			BIT(11)
++#define AT803X_SFC_FORCE_LINK			BIT(10)
++#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
++#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
++#define AT803X_SFC_MANUAL_MDIX			0x1
++#define AT803X_SFC_MANUAL_MDI			0x0
++#define AT803X_SFC_SQE_TEST			BIT(2)
++#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
++#define AT803X_SFC_DISABLE_JABBER		BIT(0)
++
++#define AT803X_SPECIFIC_STATUS			0x11
++#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
++#define AT803X_SS_SPEED_1000			2
++#define AT803X_SS_SPEED_100			1
++#define AT803X_SS_SPEED_10			0
++#define AT803X_SS_DUPLEX			BIT(13)
++#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
++#define AT803X_SS_MDIX				BIT(6)
++
++#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
++#define QCA808X_SS_SPEED_2500			4
++
++#define AT803X_INTR_ENABLE			0x12
++#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
++#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
++#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
++#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
++#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
++#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
++#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
++#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
++#define AT803X_INTR_ENABLE_WOL			BIT(0)
++
++#define AT803X_INTR_STATUS			0x13
++
++#define AT803X_SMART_SPEED			0x14
++#define AT803X_SMART_SPEED_ENABLE		BIT(5)
++#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
++#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
++#define AT803X_CDT				0x16
++#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
++#define AT803X_CDT_ENABLE_TEST			BIT(0)
++#define AT803X_CDT_STATUS			0x1c
++#define AT803X_CDT_STATUS_STAT_NORMAL		0
++#define AT803X_CDT_STATUS_STAT_SHORT		1
++#define AT803X_CDT_STATUS_STAT_OPEN		2
++#define AT803X_CDT_STATUS_STAT_FAIL		3
++#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
++#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
++#define AT803X_LED_CONTROL			0x18
++
++#define AT803X_PHY_MMD3_WOL_CTRL		0x8012
++#define AT803X_WOL_EN				BIT(5)
++#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
++#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
++#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
++#define AT803X_REG_CHIP_CONFIG			0x1f
++#define AT803X_BT_BX_REG_SEL			0x8000
++
++#define AT803X_DEBUG_ADDR			0x1D
++#define AT803X_DEBUG_DATA			0x1E
++
++#define AT803X_MODE_CFG_MASK			0x0F
++#define AT803X_MODE_CFG_BASET_RGMII		0x00
++#define AT803X_MODE_CFG_BASET_SGMII		0x01
++#define AT803X_MODE_CFG_BX1000_RGMII_50OHM	0x02
++#define AT803X_MODE_CFG_BX1000_RGMII_75OHM	0x03
++#define AT803X_MODE_CFG_BX1000_CONV_50OHM	0x04
++#define AT803X_MODE_CFG_BX1000_CONV_75OHM	0x05
++#define AT803X_MODE_CFG_FX100_RGMII_50OHM	0x06
++#define AT803X_MODE_CFG_FX100_CONV_50OHM	0x07
++#define AT803X_MODE_CFG_RGMII_AUTO_MDET		0x0B
++#define AT803X_MODE_CFG_FX100_RGMII_75OHM	0x0E
++#define AT803X_MODE_CFG_FX100_CONV_75OHM	0x0F
++
++#define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
++#define AT803X_PSSR_MR_AN_COMPLETE		0x0200
++
++#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
++#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
++#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
++#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
++
++#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
++#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
++
++#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
++#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
++#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
++#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
++
++#define AT803X_DEBUG_REG_3C			0x3C
++
++#define AT803X_DEBUG_REG_GREEN			0x3D
++#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
++
++#define AT803X_DEBUG_REG_1F			0x1F
++#define AT803X_DEBUG_PLL_ON			BIT(2)
++#define AT803X_DEBUG_RGMII_1V8			BIT(3)
++
++#define MDIO_AZ_DEBUG				0x800D
++
++/* AT803x supports either the XTAL input pad, an internal PLL or the
++ * DSP as clock reference for the clock output pad. The XTAL reference
++ * is only used for 25 MHz output, all other frequencies need the PLL.
++ * The DSP as a clock reference is used in synchronous ethernet
++ * applications.
++ *
++ * By default the PLL is only enabled if there is a link. Otherwise
++ * the PHY will go into low power state and disabled the PLL. You can
++ * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
++ * enabled.
++ */
++#define AT803X_MMD7_CLK25M			0x8016
++#define AT803X_CLK_OUT_MASK			GENMASK(4, 2)
++#define AT803X_CLK_OUT_25MHZ_XTAL		0
++#define AT803X_CLK_OUT_25MHZ_DSP		1
++#define AT803X_CLK_OUT_50MHZ_PLL		2
++#define AT803X_CLK_OUT_50MHZ_DSP		3
++#define AT803X_CLK_OUT_62_5MHZ_PLL		4
++#define AT803X_CLK_OUT_62_5MHZ_DSP		5
++#define AT803X_CLK_OUT_125MHZ_PLL		6
++#define AT803X_CLK_OUT_125MHZ_DSP		7
++
++/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
++ * but doesn't support choosing between XTAL/PLL and DSP.
++ */
++#define AT8035_CLK_OUT_MASK			GENMASK(4, 3)
++
++#define AT803X_CLK_OUT_STRENGTH_MASK		GENMASK(8, 7)
++#define AT803X_CLK_OUT_STRENGTH_FULL		0
++#define AT803X_CLK_OUT_STRENGTH_HALF		1
++#define AT803X_CLK_OUT_STRENGTH_QUARTER		2
++
++#define AT803X_DEFAULT_DOWNSHIFT		5
++#define AT803X_MIN_DOWNSHIFT			2
++#define AT803X_MAX_DOWNSHIFT			9
++
++#define AT803X_MMD3_SMARTEEE_CTL1		0x805b
++#define AT803X_MMD3_SMARTEEE_CTL2		0x805c
++#define AT803X_MMD3_SMARTEEE_CTL3		0x805d
++#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN	BIT(8)
++
++#define ATH9331_PHY_ID				0x004dd041
++#define ATH8030_PHY_ID				0x004dd076
++#define ATH8031_PHY_ID				0x004dd074
++#define ATH8032_PHY_ID				0x004dd023
++#define ATH8035_PHY_ID				0x004dd072
++#define AT8030_PHY_ID_MASK			0xffffffef
++
++#define QCA8081_PHY_ID				0x004dd101
++
++#define QCA8327_A_PHY_ID			0x004dd033
++#define QCA8327_B_PHY_ID			0x004dd034
++#define QCA8337_PHY_ID				0x004dd036
++#define QCA9561_PHY_ID				0x004dd042
++#define QCA8K_PHY_ID_MASK			0xffffffff
++
++#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
++
++#define AT803X_PAGE_FIBER			0
++#define AT803X_PAGE_COPPER			1
++
++/* don't turn off internal PLL */
++#define AT803X_KEEP_PLL_ENABLED			BIT(0)
++#define AT803X_DISABLE_SMARTEEE			BIT(1)
++
++/* disable hibernation mode */
++#define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
++
++/* ADC threshold */
++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
++#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
++#define QCA808X_ADC_THRESHOLD_80MV		0
++#define QCA808X_ADC_THRESHOLD_100MV		0xf0
++#define QCA808X_ADC_THRESHOLD_200MV		0x0f
++#define QCA808X_ADC_THRESHOLD_300MV		0xff
++
++/* CLD control */
++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
++#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
++#define QCA808X_8023AZ_AFE_EN			0x90
++
++/* AZ control */
++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
++#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
++#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
++#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
++#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
++#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
++#define QCA808X_TOP_OPTION1_DATA		0x0
++
++#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
++#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
++#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
++#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
++#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
++#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
++#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
++#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
++#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
++#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
++#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
++#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
++
++/* master/slave seed config */
++#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
++#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
++#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
++#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
++
++/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
++ */
++#define QCA808X_DBG_AN_TEST			0xb
++#define QCA808X_HIBERNATION_EN			BIT(15)
++
++#define QCA808X_CDT_ENABLE_TEST			BIT(15)
++#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
++#define QCA808X_CDT_STATUS			BIT(11)
++#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
++
++#define QCA808X_MMD3_CDT_STATUS			0x8064
++#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
++#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
++#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
++#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
++
++#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
++#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
++#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
++#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
++
++#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
++#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
++#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
++
++#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
++#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
++
++/* NORMAL are MDI with type set to 0 */
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++
++/* Added for reference of existence but should be handled by wait_for_completion already */
++#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
++
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++#define QCA808X_MMD7_LED2_CTRL			0x8074
++#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
++#define QCA808X_MMD7_LED1_CTRL			0x8076
++#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
++#define QCA808X_MMD7_LED0_CTRL			0x8078
++#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
++#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
++#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
++ * LED to active high. It's not clear what BIT 3 and BIT 4 does.
++ */
++#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
++
++/* QCA808X 1G chip type */
++#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
++#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
++
++#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
++#define QCA8081_PHY_FIFO_RSTN			BIT(11)
++
++MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_LICENSE("GPL");
++
++enum stat_access_type {
++	PHY,
++	MMD
++};
++
++struct at803x_hw_stat {
++	const char *string;
++	u8 reg;
++	u32 mask;
++	enum stat_access_type access_type;
++};
++
++static struct at803x_hw_stat qca83xx_hw_stats[] = {
++	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
++	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
++	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
++};
++
++struct at803x_ss_mask {
++	u16 speed_mask;
++	u8 speed_shift;
++};
++
++struct at803x_priv {
++	int flags;
++	u16 clk_25m_reg;
++	u16 clk_25m_mask;
++	u8 smarteee_lpi_tw_1g;
++	u8 smarteee_lpi_tw_100m;
++	bool is_fiber;
++	bool is_1000basex;
++	struct regulator_dev *vddio_rdev;
++	struct regulator_dev *vddh_rdev;
++	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
++	int led_polarity_mode;
++};
++
++struct at803x_context {
++	u16 bmcr;
++	u16 advertise;
++	u16 control1000;
++	u16 int_enable;
++	u16 smart_speed;
++	u16 led_control;
++};
++
++static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, data);
++}
++
++static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_read(phydev, AT803X_DEBUG_DATA);
++}
++
++static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
++				 u16 clear, u16 set)
++{
++	u16 val;
++	int ret;
++
++	ret = at803x_debug_reg_read(phydev, reg);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
++	val &= ~clear;
++	val |= set;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, val);
++}
++
++static int at803x_write_page(struct phy_device *phydev, int page)
++{
++	int mask;
++	int set;
++
++	if (page == AT803X_PAGE_COPPER) {
++		set = AT803X_BT_BX_REG_SEL;
++		mask = 0;
++	} else {
++		set = 0;
++		mask = AT803X_BT_BX_REG_SEL;
++	}
++
++	return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
++}
++
++static int at803x_read_page(struct phy_device *phydev)
++{
++	int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
++
++	if (ccr < 0)
++		return ccr;
++
++	if (ccr & AT803X_BT_BX_REG_SEL)
++		return AT803X_PAGE_COPPER;
++
++	return AT803X_PAGE_FIBER;
++}
++
++static int at803x_enable_rx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
++				     AT803X_DEBUG_RX_CLK_DLY_EN);
++}
++
++static int at803x_enable_tx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
++				     AT803X_DEBUG_TX_CLK_DLY_EN);
++}
++
++static int at803x_disable_rx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
++}
++
++static int at803x_disable_tx_delay(struct phy_device *phydev)
++{
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
++				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
++}
++
++/* save relevant PHY registers to private copy */
++static void at803x_context_save(struct phy_device *phydev,
++				struct at803x_context *context)
++{
++	context->bmcr = phy_read(phydev, MII_BMCR);
++	context->advertise = phy_read(phydev, MII_ADVERTISE);
++	context->control1000 = phy_read(phydev, MII_CTRL1000);
++	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
++	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
++	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
++}
++
++/* restore relevant PHY registers from private copy */
++static void at803x_context_restore(struct phy_device *phydev,
++				   const struct at803x_context *context)
++{
++	phy_write(phydev, MII_BMCR, context->bmcr);
++	phy_write(phydev, MII_ADVERTISE, context->advertise);
++	phy_write(phydev, MII_CTRL1000, context->control1000);
++	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
++	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
++	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
++}
++
++static int at803x_set_wol(struct phy_device *phydev,
++			  struct ethtool_wolinfo *wol)
++{
++	int ret, irq_enabled;
++
++	if (wol->wolopts & WAKE_MAGIC) {
++		struct net_device *ndev = phydev->attached_dev;
++		const u8 *mac;
++		unsigned int i;
++		static const unsigned int offsets[] = {
++			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
++			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
++			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
++		};
++
++		if (!ndev)
++			return -ENODEV;
++
++		mac = (const u8 *)ndev->dev_addr;
++
++		if (!is_valid_ether_addr(mac))
++			return -EINVAL;
++
++		for (i = 0; i < 3; i++)
++			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
++				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
++
++		/* Enable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
++		if (ret)
++			return ret;
++	} else {
++		/* Disable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
++		if (ret)
++			return ret;
++	}
++
++	/* Clear WOL status */
++	ret = phy_read(phydev, AT803X_INTR_STATUS);
++	if (ret < 0)
++		return ret;
++
++	/* Check if there are other interrupts except for WOL triggered when PHY is
++	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
++	 * be passed up to the interrupt PIN.
++	 */
++	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (irq_enabled < 0)
++		return irq_enabled;
++
++	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
++	if (ret & irq_enabled && !phy_polling_mode(phydev))
++		phy_trigger_machine(phydev);
++
++	return 0;
++}
++
++static void at803x_get_wol(struct phy_device *phydev,
++			   struct ethtool_wolinfo *wol)
++{
++	int value;
++
++	wol->supported = WAKE_MAGIC;
++	wol->wolopts = 0;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (value < 0)
++		return;
++
++	if (value & AT803X_INTR_ENABLE_WOL)
++		wol->wolopts |= WAKE_MAGIC;
++}
++
++static int qca83xx_get_sset_count(struct phy_device *phydev)
++{
++	return ARRAY_SIZE(qca83xx_hw_stats);
++}
++
++static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
++		strscpy(data + i * ETH_GSTRING_LEN,
++			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
++	}
++}
++
++static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
++{
++	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
++	struct at803x_priv *priv = phydev->priv;
++	int val;
++	u64 ret;
++
++	if (stat.access_type == MMD)
++		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
++	else
++		val = phy_read(phydev, stat.reg);
++
++	if (val < 0) {
++		ret = U64_MAX;
++	} else {
++		val = val & stat.mask;
++		priv->stats[i] += val;
++		ret = priv->stats[i];
++	}
++
++	return ret;
++}
++
++static void qca83xx_get_stats(struct phy_device *phydev,
++			      struct ethtool_stats *stats, u64 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
++		data[i] = qca83xx_get_stat(phydev, i);
++}
++
++static int at803x_suspend(struct phy_device *phydev)
++{
++	int value;
++	int wol_enabled;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
++
++	if (wol_enabled)
++		value = BMCR_ISOLATE;
++	else
++		value = BMCR_PDOWN;
++
++	phy_modify(phydev, MII_BMCR, 0, value);
++
++	return 0;
++}
++
++static int at803x_resume(struct phy_device *phydev)
++{
++	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
++}
++
++static int at803x_parse_dt(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct at803x_priv *priv = phydev->priv;
++	u32 freq, strength, tw;
++	unsigned int sel;
++	int ret;
++
++	if (!IS_ENABLED(CONFIG_OF_MDIO))
++		return 0;
++
++	if (of_property_read_bool(node, "qca,disable-smarteee"))
++		priv->flags |= AT803X_DISABLE_SMARTEEE;
++
++	if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
++		priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
++
++	if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
++		if (!tw || tw > 255) {
++			phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
++			return -EINVAL;
++		}
++		priv->smarteee_lpi_tw_1g = tw;
++	}
++
++	if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
++		if (!tw || tw > 255) {
++			phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
++			return -EINVAL;
++		}
++		priv->smarteee_lpi_tw_100m = tw;
++	}
++
++	ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
++	if (!ret) {
++		switch (freq) {
++		case 25000000:
++			sel = AT803X_CLK_OUT_25MHZ_XTAL;
++			break;
++		case 50000000:
++			sel = AT803X_CLK_OUT_50MHZ_PLL;
++			break;
++		case 62500000:
++			sel = AT803X_CLK_OUT_62_5MHZ_PLL;
++			break;
++		case 125000000:
++			sel = AT803X_CLK_OUT_125MHZ_PLL;
++			break;
++		default:
++			phydev_err(phydev, "invalid qca,clk-out-frequency\n");
++			return -EINVAL;
++		}
++
++		priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
++		priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
++	}
++
++	ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
++	if (!ret) {
++		priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
++		switch (strength) {
++		case AR803X_STRENGTH_FULL:
++			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
++			break;
++		case AR803X_STRENGTH_HALF:
++			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
++			break;
++		case AR803X_STRENGTH_QUARTER:
++			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
++			break;
++		default:
++			phydev_err(phydev, "invalid qca,clk-out-strength\n");
++			return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int at803x_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct at803x_priv *priv;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	/* Init LED polarity mode to -1 */
++	priv->led_polarity_mode = -1;
++
++	phydev->priv = priv;
++
++	ret = at803x_parse_dt(phydev);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int at803x_get_features(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int err;
++
++	err = genphy_read_abilities(phydev);
++	if (err)
++		return err;
++
++	if (phydev->drv->phy_id != ATH8031_PHY_ID)
++		return 0;
++
++	/* AR8031/AR8033 have different status registers
++	 * for copper and fiber operation. However, the
++	 * extended status register is the same for both
++	 * operation modes.
++	 *
++	 * As a result of that, ESTATUS_1000_XFULL is set
++	 * to 1 even when operating in copper TP mode.
++	 *
++	 * Remove this mode from the supported link modes
++	 * when not operating in 1000BaseX mode.
++	 */
++	if (!priv->is_1000basex)
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
++				   phydev->supported);
++
++	return 0;
++}
++
++static int at803x_smarteee_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	u16 mask = 0, val = 0;
++	int ret;
++
++	if (priv->flags & AT803X_DISABLE_SMARTEEE)
++		return phy_modify_mmd(phydev, MDIO_MMD_PCS,
++				      AT803X_MMD3_SMARTEEE_CTL3,
++				      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
++
++	if (priv->smarteee_lpi_tw_1g) {
++		mask |= 0xff00;
++		val |= priv->smarteee_lpi_tw_1g << 8;
++	}
++	if (priv->smarteee_lpi_tw_100m) {
++		mask |= 0x00ff;
++		val |= priv->smarteee_lpi_tw_100m;
++	}
++	if (!mask)
++		return 0;
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
++			     mask, val);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
++			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
++			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
++}
++
++static int at803x_clk_out_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	if (!priv->clk_25m_mask)
++		return 0;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
++			      priv->clk_25m_mask, priv->clk_25m_reg);
++}
++
++static int at8031_pll_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	/* The default after hardware reset is PLL OFF. After a soft reset, the
++	 * values are retained.
++	 */
++	if (priv->flags & AT803X_KEEP_PLL_ENABLED)
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     0, AT803X_DEBUG_PLL_ON);
++	else
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     AT803X_DEBUG_PLL_ON, 0);
++}
++
++static int at803x_hibernation_mode_config(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	/* The default after hardware reset is hibernation mode enabled. After
++	 * software reset, the value is retained.
++	 */
++	if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE))
++		return 0;
++
++	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
++					 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
++}
++
++static int at803x_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* The RX and TX delay default is:
++	 *   after HW reset: RX delay enabled and TX delay disabled
++	 *   after SW reset: RX delay enabled, while TX delay retains the
++	 *   value before reset.
++	 */
++	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
++		ret = at803x_enable_rx_delay(phydev);
++	else
++		ret = at803x_disable_rx_delay(phydev);
++	if (ret < 0)
++		return ret;
++
++	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
++	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
++		ret = at803x_enable_tx_delay(phydev);
++	else
++		ret = at803x_disable_tx_delay(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_smarteee_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_clk_out_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_hibernation_mode_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Ar803x extended next page bit is enabled by default. Cisco
++	 * multigig switches read this bit and attempt to negotiate 10Gbps
++	 * rates even if the next page bit is disabled. This is incorrect
++	 * behaviour but we still need to accommodate it. XNP is only needed
++	 * for 10Gbps support, so disable XNP.
++	 */
++	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
++}
++
++static int at803x_ack_interrupt(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_read(phydev, AT803X_INTR_STATUS);
++
++	return (err < 0) ? err : 0;
++}
++
++static int at803x_config_intr(struct phy_device *phydev)
++{
++	int err;
++	int value;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++		if (err)
++			return err;
++
++		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
++		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
++		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
++		value |= AT803X_INTR_ENABLE_LINK_FAIL;
++		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
++
++		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
++	} else {
++		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
++		if (err)
++			return err;
++
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++	}
++
++	return err;
++}
++
++static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
++{
++	int irq_status, int_enabled;
++
++	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
++	if (irq_status < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* Read the current enabled interrupts */
++	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (int_enabled < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* See if this was one of our enabled interrupts */
++	if (!(irq_status & int_enabled))
++		return IRQ_NONE;
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static void at803x_link_change_notify(struct phy_device *phydev)
++{
++	/*
++	 * Conduct a hardware reset for AT8030 every time a link loss is
++	 * signalled. This is necessary to circumvent a hardware bug that
++	 * occurs when the cable is unplugged while TX packets are pending
++	 * in the FIFO. In such cases, the FIFO enters an error mode it
++	 * cannot recover from by software.
++	 */
++	if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
++		struct at803x_context context;
++
++		at803x_context_save(phydev, &context);
++
++		phy_device_reset(phydev, 1);
++		usleep_range(1000, 2000);
++		phy_device_reset(phydev, 0);
++		usleep_range(1000, 2000);
++
++		at803x_context_restore(phydev, &context);
++
++		phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
++	}
++}
++
++static int at803x_read_specific_status(struct phy_device *phydev,
++				       struct at803x_ss_mask ss_mask)
++{
++	int ss;
++
++	/* Read the AT8035 PHY-Specific Status register, which indicates the
++	 * speed and duplex that the PHY is actually using, irrespective of
++	 * whether we are in autoneg mode or not.
++	 */
++	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
++	if (ss < 0)
++		return ss;
++
++	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
++		int sfc, speed;
++
++		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
++		if (sfc < 0)
++			return sfc;
++
++		speed = ss & ss_mask.speed_mask;
++		speed >>= ss_mask.speed_shift;
++
++		switch (speed) {
++		case AT803X_SS_SPEED_10:
++			phydev->speed = SPEED_10;
++			break;
++		case AT803X_SS_SPEED_100:
++			phydev->speed = SPEED_100;
++			break;
++		case AT803X_SS_SPEED_1000:
++			phydev->speed = SPEED_1000;
++			break;
++		case QCA808X_SS_SPEED_2500:
++			phydev->speed = SPEED_2500;
++			break;
++		}
++		if (ss & AT803X_SS_DUPLEX)
++			phydev->duplex = DUPLEX_FULL;
++		else
++			phydev->duplex = DUPLEX_HALF;
++
++		if (ss & AT803X_SS_MDIX)
++			phydev->mdix = ETH_TP_MDI_X;
++		else
++			phydev->mdix = ETH_TP_MDI;
++
++		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
++		case AT803X_SFC_MANUAL_MDI:
++			phydev->mdix_ctrl = ETH_TP_MDI;
++			break;
++		case AT803X_SFC_MANUAL_MDIX:
++			phydev->mdix_ctrl = ETH_TP_MDI_X;
++			break;
++		case AT803X_SFC_AUTOMATIC_CROSSOVER:
++			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
++			break;
++		}
++	}
++
++	return 0;
++}
++
++static int at803x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int err, old_link = phydev->link;
++
++	/* Update the link, but return if there was an error */
++	err = genphy_update_link(phydev);
++	if (err)
++		return err;
++
++	/* why bother the PHY if nothing can have changed */
++	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
++		return 0;
++
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	err = genphy_read_lpa(phydev);
++	if (err < 0)
++		return err;
++
++	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
++	err = at803x_read_specific_status(phydev, ss_mask);
++	if (err < 0)
++		return err;
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	return 0;
++}
++
++static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
++{
++	u16 val;
++
++	switch (ctrl) {
++	case ETH_TP_MDI:
++		val = AT803X_SFC_MANUAL_MDI;
++		break;
++	case ETH_TP_MDI_X:
++		val = AT803X_SFC_MANUAL_MDIX;
++		break;
++	case ETH_TP_MDI_AUTO:
++		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
++		break;
++	default:
++		return 0;
++	}
++
++	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
++			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
++			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
++}
++
++static int at803x_prepare_config_aneg(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
++	if (ret < 0)
++		return ret;
++
++	/* Changes of the midx bits are disruptive to the normal operation;
++	 * therefore any changes to these registers must be followed by a
++	 * software reset to take effect.
++	 */
++	if (ret == 1) {
++		ret = genphy_soft_reset(phydev);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int at803x_config_aneg(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int ret;
++
++	ret = at803x_prepare_config_aneg(phydev);
++	if (ret)
++		return ret;
++
++	if (priv->is_1000basex)
++		return genphy_c37_config_aneg(phydev);
++
++	return genphy_config_aneg(phydev);
++}
++
++static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
++{
++	int val;
++
++	val = phy_read(phydev, AT803X_SMART_SPEED);
++	if (val < 0)
++		return val;
++
++	if (val & AT803X_SMART_SPEED_ENABLE)
++		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
++	else
++		*d = DOWNSHIFT_DEV_DISABLE;
++
++	return 0;
++}
++
++static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
++{
++	u16 mask, set;
++	int ret;
++
++	switch (cnt) {
++	case DOWNSHIFT_DEV_DEFAULT_COUNT:
++		cnt = AT803X_DEFAULT_DOWNSHIFT;
++		fallthrough;
++	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
++		set = AT803X_SMART_SPEED_ENABLE |
++		      AT803X_SMART_SPEED_BYPASS_TIMER |
++		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
++		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
++		break;
++	case DOWNSHIFT_DEV_DISABLE:
++		set = 0;
++		mask = AT803X_SMART_SPEED_ENABLE |
++		       AT803X_SMART_SPEED_BYPASS_TIMER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
++
++	/* After changing the smart speed settings, we need to perform a
++	 * software reset, use phy_init_hw() to make sure we set the
++	 * reapply any values which might got lost during software reset.
++	 */
++	if (ret == 1)
++		ret = phy_init_hw(phydev);
++
++	return ret;
++}
++
++static int at803x_get_tunable(struct phy_device *phydev,
++			      struct ethtool_tunable *tuna, void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_get_downshift(phydev, data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static int at803x_set_tunable(struct phy_device *phydev,
++			      struct ethtool_tunable *tuna, const void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_set_downshift(phydev, *(const u8 *)data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++
++static int at803x_cable_test_result_trans(u16 status)
++{
++	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
++	case AT803X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case AT803X_CDT_STATUS_STAT_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case AT803X_CDT_STATUS_STAT_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case AT803X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static bool at803x_cdt_test_failed(u16 status)
++{
++	return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
++		AT803X_CDT_STATUS_STAT_FAIL;
++}
++
++static bool at803x_cdt_fault_length_valid(u16 status)
++{
++	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
++	case AT803X_CDT_STATUS_STAT_OPEN:
++	case AT803X_CDT_STATUS_STAT_SHORT:
++		return true;
++	}
++	return false;
++}
++
++static int at803x_cdt_fault_length(int dt)
++{
++	/* According to the datasheet the distance to the fault is
++	 * DELTA_TIME * 0.824 meters.
++	 *
++	 * The author suspect the correct formula is:
++	 *
++	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
++	 *
++	 * where c is the speed of light, VF is the velocity factor of
++	 * the twisted pair cable, 125MHz the counter frequency and
++	 * we need to divide by 2 because the hardware will measure the
++	 * round trip time to the fault and back to the PHY.
++	 *
++	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
++	 * datasheet.
++	 */
++	return (dt * 824) / 10;
++}
++
++static int at803x_cdt_start(struct phy_device *phydev,
++			    u32 cdt_start)
++{
++	return phy_write(phydev, AT803X_CDT, cdt_start);
++}
++
++static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
++					  u32 cdt_en)
++{
++	int val, ret;
++
++	/* One test run takes about 25ms */
++	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
++				    !(val & cdt_en),
++				    30000, 100000, true);
++
++	return ret < 0 ? ret : 0;
++}
++
++static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
++{
++	static const int ethtool_pair[] = {
++		ETHTOOL_A_CABLE_PAIR_A,
++		ETHTOOL_A_CABLE_PAIR_B,
++		ETHTOOL_A_CABLE_PAIR_C,
++		ETHTOOL_A_CABLE_PAIR_D,
++	};
++	int ret, val;
++
++	val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
++	      AT803X_CDT_ENABLE_TEST;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read(phydev, AT803X_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	if (at803x_cdt_test_failed(val))
++		return 0;
++
++	ethnl_cable_test_result(phydev, ethtool_pair[pair],
++				at803x_cable_test_result_trans(val));
++
++	if (at803x_cdt_fault_length_valid(val)) {
++		val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
++		ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
++					      at803x_cdt_fault_length(val));
++	}
++
++	return 1;
++}
++
++static int at803x_cable_test_get_status(struct phy_device *phydev,
++					bool *finished, unsigned long pair_mask)
++{
++	int retries = 20;
++	int pair, ret;
++
++	*finished = false;
++
++	/* According to the datasheet the CDT can be performed when
++	 * there is no link partner or when the link partner is
++	 * auto-negotiating. Starting the test will restart the AN
++	 * automatically. It seems that doing this repeatedly we will
++	 * get a slot where our link partner won't disturb our
++	 * measurement.
++	 */
++	while (pair_mask && retries--) {
++		for_each_set_bit(pair, &pair_mask, 4) {
++			ret = at803x_cable_test_one_pair(phydev, pair);
++			if (ret < 0)
++				return ret;
++			if (ret)
++				clear_bit(pair, &pair_mask);
++		}
++		if (pair_mask)
++			msleep(250);
++	}
++
++	*finished = true;
++
++	return 0;
++}
++
++static void at803x_cable_test_autoneg(struct phy_device *phydev)
++{
++	/* Enable auto-negotiation, but advertise no capabilities, no link
++	 * will be established. A restart of the auto-negotiation is not
++	 * required, because the cable test will automatically break the link.
++	 */
++	phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
++	phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
++}
++
++static int at803x_cable_test_start(struct phy_device *phydev)
++{
++	at803x_cable_test_autoneg(phydev);
++	/* we do all the (time consuming) work later */
++	return 0;
++}
++
++static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
++					    unsigned int selector)
++{
++	struct phy_device *phydev = rdev_get_drvdata(rdev);
++
++	if (selector)
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     0, AT803X_DEBUG_RGMII_1V8);
++	else
++		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
++					     AT803X_DEBUG_RGMII_1V8, 0);
++}
++
++static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
++{
++	struct phy_device *phydev = rdev_get_drvdata(rdev);
++	int val;
++
++	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
++	if (val < 0)
++		return val;
++
++	return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
++}
++
++static const struct regulator_ops vddio_regulator_ops = {
++	.list_voltage = regulator_list_voltage_table,
++	.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
++	.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
++};
++
++static const unsigned int vddio_voltage_table[] = {
++	1500000,
++	1800000,
++};
++
++static const struct regulator_desc vddio_desc = {
++	.name = "vddio",
++	.of_match = of_match_ptr("vddio-regulator"),
++	.n_voltages = ARRAY_SIZE(vddio_voltage_table),
++	.volt_table = vddio_voltage_table,
++	.ops = &vddio_regulator_ops,
++	.type = REGULATOR_VOLTAGE,
++	.owner = THIS_MODULE,
++};
++
++static const struct regulator_ops vddh_regulator_ops = {
++};
++
++static const struct regulator_desc vddh_desc = {
++	.name = "vddh",
++	.of_match = of_match_ptr("vddh-regulator"),
++	.n_voltages = 1,
++	.fixed_uV = 2500000,
++	.ops = &vddh_regulator_ops,
++	.type = REGULATOR_VOLTAGE,
++	.owner = THIS_MODULE,
++};
++
++static int at8031_register_regulators(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	struct regulator_config config = { };
++
++	config.dev = dev;
++	config.driver_data = phydev;
++
++	priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
++	if (IS_ERR(priv->vddio_rdev)) {
++		phydev_err(phydev, "failed to register VDDIO regulator\n");
++		return PTR_ERR(priv->vddio_rdev);
++	}
++
++	priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
++	if (IS_ERR(priv->vddh_rdev)) {
++		phydev_err(phydev, "failed to register VDDH regulator\n");
++		return PTR_ERR(priv->vddh_rdev);
++	}
++
++	return 0;
++}
++
++static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
++{
++	struct phy_device *phydev = upstream;
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
++	DECLARE_PHY_INTERFACE_MASK(interfaces);
++	phy_interface_t iface;
++
++	linkmode_zero(phy_support);
++	phylink_set(phy_support, 1000baseX_Full);
++	phylink_set(phy_support, 1000baseT_Full);
++	phylink_set(phy_support, Autoneg);
++	phylink_set(phy_support, Pause);
++	phylink_set(phy_support, Asym_Pause);
++
++	linkmode_zero(sfp_support);
++	sfp_parse_support(phydev->sfp_bus, id, sfp_support, interfaces);
++	/* Some modules support 10G modes as well as others we support.
++	 * Mask out non-supported modes so the correct interface is picked.
++	 */
++	linkmode_and(sfp_support, phy_support, sfp_support);
++
++	if (linkmode_empty(sfp_support)) {
++		dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
++		return -EINVAL;
++	}
++
++	iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
++
++	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
++	 * interface for use with SFP modules.
++	 * However, some copper modules detected as having a preferred SGMII
++	 * interface do default to and function in 1000Base-X mode, so just
++	 * print a warning and allow such modules, as they may have some chance
++	 * of working.
++	 */
++	if (iface == PHY_INTERFACE_MODE_SGMII)
++		dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
++	else if (iface != PHY_INTERFACE_MODE_1000BASEX)
++		return -EINVAL;
++
++	return 0;
++}
++
++static const struct sfp_upstream_ops at8031_sfp_ops = {
++	.attach = phy_sfp_attach,
++	.detach = phy_sfp_detach,
++	.module_insert = at8031_sfp_insert,
++};
++
++static int at8031_parse_dt(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct at803x_priv *priv = phydev->priv;
++	int ret;
++
++	if (of_property_read_bool(node, "qca,keep-pll-enabled"))
++		priv->flags |= AT803X_KEEP_PLL_ENABLED;
++
++	ret = at8031_register_regulators(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
++						 "vddio");
++	if (ret) {
++		phydev_err(phydev, "failed to get VDDIO regulator\n");
++		return ret;
++	}
++
++	/* Only AR8031/8033 support 1000Base-X for SFP modules */
++	return phy_sfp_probe(phydev, &at8031_sfp_ops);
++}
++
++static int at8031_probe(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int mode_cfg;
++	int ccr;
++	int ret;
++
++	ret = at803x_probe(phydev);
++	if (ret)
++		return ret;
++
++	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
++	 * options.
++	 */
++	ret = at8031_parse_dt(phydev);
++	if (ret)
++		return ret;
++
++	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
++	if (ccr < 0)
++		return ccr;
++	mode_cfg = ccr & AT803X_MODE_CFG_MASK;
++
++	switch (mode_cfg) {
++	case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
++	case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
++		priv->is_1000basex = true;
++		fallthrough;
++	case AT803X_MODE_CFG_FX100_RGMII_50OHM:
++	case AT803X_MODE_CFG_FX100_RGMII_75OHM:
++		priv->is_fiber = true;
++		break;
++	}
++
++	/* Disable WoL in 1588 register which is enabled
++	 * by default
++	 */
++	return phy_modify_mmd(phydev, MDIO_MMD_PCS,
++			      AT803X_PHY_MMD3_WOL_CTRL,
++			      AT803X_WOL_EN, 0);
++}
++
++static int at8031_config_init(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int ret;
++
++	/* Some bootloaders leave the fiber page selected.
++	 * Switch to the appropriate page (fiber or copper), as otherwise we
++	 * read the PHY capabilities from the wrong page.
++	 */
++	phy_lock_mdio_bus(phydev);
++	ret = at803x_write_page(phydev,
++				priv->is_fiber ? AT803X_PAGE_FIBER :
++						 AT803X_PAGE_COPPER);
++	phy_unlock_mdio_bus(phydev);
++	if (ret)
++		return ret;
++
++	ret = at8031_pll_config(phydev);
++	if (ret < 0)
++		return ret;
++
++	return at803x_config_init(phydev);
++}
++
++static int at8031_set_wol(struct phy_device *phydev,
++			  struct ethtool_wolinfo *wol)
++{
++	int ret;
++
++	/* First setup MAC address and enable WOL interrupt */
++	ret = at803x_set_wol(phydev, wol);
++	if (ret)
++		return ret;
++
++	if (wol->wolopts & WAKE_MAGIC)
++		/* Enable WOL function for 1588 */
++		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
++				     AT803X_PHY_MMD3_WOL_CTRL,
++				     0, AT803X_WOL_EN);
++	else
++		/* Disable WoL function for 1588 */
++		ret = phy_modify_mmd(phydev, MDIO_MMD_PCS,
++				     AT803X_PHY_MMD3_WOL_CTRL,
++				     AT803X_WOL_EN, 0);
++
++	return ret;
++}
++
++static int at8031_config_intr(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++	int err, value = 0;
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
++	    priv->is_fiber) {
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++		if (err)
++			return err;
++
++		value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
++		value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
++
++		err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
++		if (err)
++			return err;
++	}
++
++	return at803x_config_intr(phydev);
++}
++
++/* AR8031 and AR8033 share the same read status logic */
++static int at8031_read_status(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	if (priv->is_1000basex)
++		return genphy_c37_read_status(phydev);
++
++	return at803x_read_status(phydev);
++}
++
++/* AR8031 and AR8035 share the same cable test get status reg */
++static int at8031_cable_test_get_status(struct phy_device *phydev,
++					bool *finished)
++{
++	return at803x_cable_test_get_status(phydev, finished, 0xf);
++}
++
++/* AR8031 and AR8035 share the same cable test start logic */
++static int at8031_cable_test_start(struct phy_device *phydev)
++{
++	at803x_cable_test_autoneg(phydev);
++	phy_write(phydev, MII_CTRL1000, 0);
++	/* we do all the (time consuming) work later */
++	return 0;
++}
++
++/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
++static int at8032_cable_test_get_status(struct phy_device *phydev,
++					bool *finished)
++{
++	return at803x_cable_test_get_status(phydev, finished, 0x3);
++}
++
++static int at8035_parse_dt(struct phy_device *phydev)
++{
++	struct at803x_priv *priv = phydev->priv;
++
++	/* Mask is set by the generic at803x_parse_dt
++	 * if property is set. Assume property is set
++	 * with the mask not zero.
++	 */
++	if (priv->clk_25m_mask) {
++		/* Fixup for the AR8030/AR8035. This chip has another mask and
++		 * doesn't support the DSP reference. Eg. the lowest bit of the
++		 * mask. The upper two bits select the same frequencies. Mask
++		 * the lowest bit here.
++		 *
++		 * Warning:
++		 *   There was no datasheet for the AR8030 available so this is
++		 *   just a guess. But the AR8035 is listed as pin compatible
++		 *   to the AR8030 so there might be a good chance it works on
++		 *   the AR8030 too.
++		 */
++		priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
++		priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
++	}
++
++	return 0;
++}
++
++/* AR8030 and AR8035 shared the same special mask for clk_25m */
++static int at8035_probe(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = at803x_probe(phydev);
++	if (ret)
++		return ret;
++
++	return at8035_parse_dt(phydev);
++}
++
++static int qca83xx_config_init(struct phy_device *phydev)
++{
++	u8 switch_revision;
++
++	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
++
++	switch (switch_revision) {
++	case 1:
++		/* For 100M waveform */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
++		/* Turn on Gigabit clock */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
++		break;
++
++	case 2:
++		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
++		fallthrough;
++	case 4:
++		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
++		break;
++	}
++
++	/* Following original QCA sourcecode set port to prefer master */
++	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
++
++	return 0;
++}
++
++static int qca8327_config_init(struct phy_device *phydev)
++{
++	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
++	 * Disable on init and enable only with 100m speed following
++	 * qca original source code.
++	 */
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++
++	return qca83xx_config_init(phydev);
++}
++
++static void qca83xx_link_change_notify(struct phy_device *phydev)
++{
++	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
++	if (phydev->state == PHY_RUNNING) {
++		if (phydev->speed == SPEED_100)
++			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++					      QCA8327_DEBUG_MANU_CTRL_EN,
++					      QCA8327_DEBUG_MANU_CTRL_EN);
++	} else {
++		/* Reset DAC Amplitude adjustment */
++		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++	}
++}
++
++static int qca83xx_resume(struct phy_device *phydev)
++{
++	int ret, val;
++
++	/* Skip reset if not suspended */
++	if (!phydev->suspended)
++		return 0;
++
++	/* Reinit the port, reset values set by suspend */
++	qca83xx_config_init(phydev);
++
++	/* Reset the port on port resume */
++	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
++
++	/* On resume from suspend the switch execute a reset and
++	 * restart auto-negotiation. Wait for reset to complete.
++	 */
++	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
++				    50000, 600000, true);
++	if (ret)
++		return ret;
++
++	usleep_range(1000, 2000);
++
++	return 0;
++}
++
++static int qca83xx_suspend(struct phy_device *phydev)
++{
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
++			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
++
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
++			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
++			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
++
++	return 0;
++}
++
++static int qca8337_suspend(struct phy_device *phydev)
++{
++	/* Only QCA8337 support actual suspend. */
++	genphy_suspend(phydev);
++
++	return qca83xx_suspend(phydev);
++}
++
++static int qca8327_suspend(struct phy_device *phydev)
++{
++	u16 mask = 0;
++
++	/* QCA8327 cause port unreliability when phy suspend
++	 * is set.
++	 */
++	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
++	phy_modify(phydev, MII_BMCR, mask, 0);
++
++	return qca83xx_suspend(phydev);
++}
++
++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Enable fast retrain */
++	ret = genphy_c45_fast_retrain(phydev, true);
++	if (ret)
++		return ret;
++
++	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
++		      QCA808X_TOP_OPTION1_DATA);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
++		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
++		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
++		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
++		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
++		      QCA808X_MMD3_DEBUG_1_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
++		      QCA808X_MMD3_DEBUG_4_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
++		      QCA808X_MMD3_DEBUG_5_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
++		      QCA808X_MMD3_DEBUG_3_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
++		      QCA808X_MMD3_DEBUG_6_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
++		      QCA808X_MMD3_DEBUG_2_VALUE);
++
++	return 0;
++}
++
++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
++{
++	u16 seed_value;
++
++	if (!enable)
++		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
++
++	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
++			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
++			QCA808X_MASTER_SLAVE_SEED_ENABLE);
++}
++
++static bool qca808x_is_prefer_master(struct phy_device *phydev)
++{
++	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
++		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
++}
++
++static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
++{
++	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++}
++
++static int qca808x_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Active adc&vga on 802.3az for the link 1000M and 100M */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
++			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
++	if (ret)
++		return ret;
++
++	/* Adjust the threshold on 802.3az for the link 1000M */
++	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
++			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
++			    QCA808X_MMD3_AZ_TRAINING_VAL);
++	if (ret)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++		/* Config the fast retrain for the link 2500M */
++		ret = qca808x_phy_fast_retrain_config(phydev);
++		if (ret)
++			return ret;
++
++		ret = genphy_read_master_slave(phydev);
++		if (ret < 0)
++			return ret;
++
++		if (!qca808x_is_prefer_master(phydev)) {
++			/* Enable seed and configure lower ramdom seed to make phy
++			 * linked as slave mode.
++			 */
++			ret = qca808x_phy_ms_seed_enable(phydev, true);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Configure adc threshold as 100mv for the link 10M */
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
++				     QCA808X_ADC_THRESHOLD_MASK,
++				     QCA808X_ADC_THRESHOLD_100MV);
++}
++
++static int qca808x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int ret;
++
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
++	if (ret < 0)
++		return ret;
++
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
++			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
++
++	ret = genphy_read_status(phydev);
++	if (ret)
++		return ret;
++
++	/* qca8081 takes the different bits for speed value from at803x */
++	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
++	ret = at803x_read_specific_status(phydev, ss_mask);
++	if (ret < 0)
++		return ret;
++
++	if (phydev->link) {
++		if (phydev->speed == SPEED_2500)
++			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++		else
++			phydev->interface = PHY_INTERFACE_MODE_SGMII;
++	} else {
++		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
++		 * except for master/slave configuration fault detected or the master mode
++		 * preferred.
++		 *
++		 * the reason for not putting this code into the function link_change_notify is
++		 * the corner case where the link partner is also the qca8081 PHY and the seed
++		 * value is configured as the same value, the link can't be up and no link change
++		 * occurs.
++		 */
++		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
++			    qca808x_is_prefer_master(phydev)) {
++				qca808x_phy_ms_seed_enable(phydev, false);
++			} else {
++				qca808x_phy_ms_seed_enable(phydev, true);
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int qca808x_soft_reset(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_soft_reset(phydev);
++	if (ret < 0)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
++		ret = qca808x_phy_ms_seed_enable(phydev, true);
++
++	return ret;
++}
++
++static bool qca808x_cdt_fault_length_valid(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static int qca808x_cable_test_result_trans(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
++	case QCA808X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
++				    int result)
++{
++	int val;
++	u32 cdt_length_reg = 0;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
++	if (val < 0)
++		return val;
++
++	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
++	else
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
++
++	return at803x_cdt_fault_length(val);
++}
++
++static int qca808x_cable_test_start(struct phy_device *phydev)
++{
++	int ret;
++
++	/* perform CDT with the following configs:
++	 * 1. disable hibernation.
++	 * 2. force PHY working in MDI mode.
++	 * 3. for PHY working in 1000BaseT.
++	 * 4. configure the threshold.
++	 */
++
++	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
++	if (ret < 0)
++		return ret;
++
++	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
++	phydev->duplex = DUPLEX_FULL;
++	phydev->speed = SPEED_1000;
++	ret = genphy_c45_pma_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* configure the thresholds for open, short, pair ok test */
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
++					      u16 status)
++{
++	int length, result;
++	u16 pair_code;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	result = qca808x_cable_test_result_trans(pair_code);
++	ethnl_cable_test_result(phydev, pair, result);
++
++	if (qca808x_cdt_fault_length_valid(pair_code)) {
++		length = qca808x_cdt_fault_length(phydev, pair, result);
++		ethnl_cable_test_fault_length(phydev, pair, length);
++	}
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
++{
++	int ret, val;
++
++	*finished = false;
++
++	val = QCA808X_CDT_ENABLE_TEST |
++	      QCA808X_CDT_LENGTH_UNIT;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
++	if (ret)
++		return ret;
++
++	*finished = true;
++
++	return 0;
++}
++
++static int qca808x_get_features(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_c45_pma_read_abilities(phydev);
++	if (ret)
++		return ret;
++
++	/* The autoneg ability is not existed in bit3 of MMD7.1,
++	 * but it is supported by qca808x PHY, so we add it here
++	 * manually.
++	 */
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
++
++	/* As for the qca8081 1G version chip, the 2500baseT ability is also
++	 * existed in the bit0 of MMD1.21, we need to remove it manually if
++	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
++	 */
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
++	if (ret < 0)
++		return ret;
++
++	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++
++	return 0;
++}
++
++static int qca808x_config_aneg(struct phy_device *phydev)
++{
++	int phy_ctrl = 0;
++	int ret;
++
++	ret = at803x_prepare_config_aneg(phydev);
++	if (ret)
++		return ret;
++
++	/* The reg MII_BMCR also needs to be configured for force mode, the
++	 * genphy_config_aneg is also needed.
++	 */
++	if (phydev->autoneg == AUTONEG_DISABLE)
++		genphy_c45_pma_setup_forced(phydev);
++
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
++		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
++	if (ret < 0)
++		return ret;
++
++	return __genphy_config_aneg(phydev, ret);
++}
++
++static void qca808x_link_change_notify(struct phy_device *phydev)
++{
++	/* Assert interface sgmii fifo on link down, deassert it on link up,
++	 * the interface device address is always phy address added by 1.
++	 */
++	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
++				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
++				   QCA8081_PHY_FIFO_RSTN,
++				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
++}
++
++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	if (test_bit(TRIGGER_NETDEV_TX, &rules))
++		*offload_trigger |= QCA808X_LED_TX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_RX, &rules))
++		*offload_trigger |= QCA808X_LED_RX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED10_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED100_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
++	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	/* Enable BLINK_CHECK_BYPASS by default to make the LED
++	 * blink even with duplex or speed mode not enabled.
++	 */
++	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 2)
++		return -EINVAL;
++
++	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, offload_trigger = 0;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca808x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_PATTERN_MASK,
++			      offload_trigger);
++}
++
++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return false;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca808x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	if (val & QCA808X_LED_TX_BLINK)
++		set_bit(TRIGGER_NETDEV_TX, rules);
++	if (val & QCA808X_LED_RX_BLINK)
++		set_bit(TRIGGER_NETDEV_RX, rules);
++	if (val & QCA808X_LED_SPEED10_ON)
++		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++	if (val & QCA808X_LED_SPEED100_ON)
++		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++	if (val & QCA808X_LED_SPEED1000_ON)
++		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++	if (val & QCA808X_LED_SPEED2500_ON)
++		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
++	if (val & QCA808X_LED_HALF_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++	if (val & QCA808X_LED_FULL_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_PATTERN_MASK);
++}
++
++static int qca808x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	if (!value) {
++		ret = qca808x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF);
++}
++
++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	int ret;
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++
++static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
++				    unsigned long modes)
++{
++	struct at803x_priv *priv = phydev->priv;
++	bool active_low = false;
++	u32 mode;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	/* PHY polarity is global and can't be set per LED.
++	 * To detect this, check if last requested polarity mode
++	 * match the new one.
++	 */
++	if (priv->led_polarity_mode >= 0 &&
++	    priv->led_polarity_mode != active_low) {
++		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
++		return -EINVAL;
++	}
++
++	/* Save the last PHY polarity mode */
++	priv->led_polarity_mode = active_low;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN,
++			      QCA808X_MMD7_LED_POLARITY_CTRL,
++			      QCA808X_LED_ACTIVE_HIGH,
++			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
++}
++
++static struct phy_driver at803x_driver[] = {
++{
++	/* Qualcomm Atheros AR8035 */
++	PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
++	.name			= "Qualcomm Atheros AR8035",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= at8035_probe,
++	.config_aneg		= at803x_config_aneg,
++	.config_init		= at803x_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	/* PHY_GBIT_FEATURES */
++	.read_status		= at803x_read_status,
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.cable_test_start	= at8031_cable_test_start,
++	.cable_test_get_status	= at8031_cable_test_get_status,
++}, {
++	/* Qualcomm Atheros AR8030 */
++	.phy_id			= ATH8030_PHY_ID,
++	.name			= "Qualcomm Atheros AR8030",
++	.phy_id_mask		= AT8030_PHY_ID_MASK,
++	.probe			= at8035_probe,
++	.config_init		= at803x_config_init,
++	.link_change_notify	= at803x_link_change_notify,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++}, {
++	/* Qualcomm Atheros AR8031/AR8033 */
++	PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
++	.name			= "Qualcomm Atheros AR8031/AR8033",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= at8031_probe,
++	.config_init		= at8031_config_init,
++	.config_aneg		= at803x_config_aneg,
++	.soft_reset		= genphy_soft_reset,
++	.set_wol		= at8031_set_wol,
++	.get_wol		= at803x_get_wol,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	.read_page		= at803x_read_page,
++	.write_page		= at803x_write_page,
++	.get_features		= at803x_get_features,
++	.read_status		= at8031_read_status,
++	.config_intr		= at8031_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.cable_test_start	= at8031_cable_test_start,
++	.cable_test_get_status	= at8031_cable_test_get_status,
++}, {
++	/* Qualcomm Atheros AR8032 */
++	PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
++	.name			= "Qualcomm Atheros AR8032",
++	.probe			= at803x_probe,
++	.flags			= PHY_POLL_CABLE_TEST,
++	.config_init		= at803x_config_init,
++	.link_change_notify	= at803x_link_change_notify,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.cable_test_start	= at803x_cable_test_start,
++	.cable_test_get_status	= at8032_cable_test_get_status,
++}, {
++	/* ATHEROS AR9331 */
++	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
++	.name			= "Qualcomm Atheros AR9331 built-in PHY",
++	.probe			= at803x_probe,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	.flags			= PHY_POLL_CABLE_TEST,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.cable_test_start	= at803x_cable_test_start,
++	.cable_test_get_status	= at8032_cable_test_get_status,
++	.read_status		= at803x_read_status,
++	.soft_reset		= genphy_soft_reset,
++	.config_aneg		= at803x_config_aneg,
++}, {
++	/* Qualcomm Atheros QCA9561 */
++	PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
++	.name			= "Qualcomm Atheros QCA9561 built-in PHY",
++	.probe			= at803x_probe,
++	.suspend		= at803x_suspend,
++	.resume			= at803x_resume,
++	.flags			= PHY_POLL_CABLE_TEST,
++	/* PHY_BASIC_FEATURES */
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.cable_test_start	= at803x_cable_test_start,
++	.cable_test_get_status	= at8032_cable_test_get_status,
++	.read_status		= at803x_read_status,
++	.soft_reset		= genphy_soft_reset,
++	.config_aneg		= at803x_config_aneg,
++}, {
++	/* QCA8337 */
++	.phy_id			= QCA8337_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8337 internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.probe			= at803x_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca83xx_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8337_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-A from switch QCA8327-AL1A */
++	.phy_id			= QCA8327_A_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-A internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= at803x_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-B from switch QCA8327-BL1A */
++	.phy_id			= QCA8327_B_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-B internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= at803x_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* Qualcomm QCA8081 */
++	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
++	.name			= "Qualcomm QCA8081",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= at803x_probe,
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.get_features		= qca808x_get_features,
++	.config_aneg		= qca808x_config_aneg,
++	.suspend		= genphy_suspend,
++	.resume			= genphy_resume,
++	.read_status		= qca808x_read_status,
++	.config_init		= qca808x_config_init,
++	.soft_reset		= qca808x_soft_reset,
++	.cable_test_start	= qca808x_cable_test_start,
++	.cable_test_get_status	= qca808x_cable_test_get_status,
++	.link_change_notify	= qca808x_link_change_notify,
++	.led_brightness_set	= qca808x_led_brightness_set,
++	.led_blink_set		= qca808x_led_blink_set,
++	.led_hw_is_supported	= qca808x_led_hw_is_supported,
++	.led_hw_control_set	= qca808x_led_hw_control_set,
++	.led_hw_control_get	= qca808x_led_hw_control_get,
++	.led_polarity_set	= qca808x_led_polarity_set,
++}, };
++
++module_phy_driver(at803x_driver);
++
++static struct mdio_device_id __maybe_unused atheros_tbl[] = {
++	{ ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
++	{ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, atheros_tbl);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch b/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch
new file mode 100644
index 00000000000..7d0e1f4a285
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-02-net-phy-qcom-create-and-move-functions-to-shared-lib.patch
@@ -0,0 +1,243 @@
+From 6fb760972c49490b03f3db2ad64cf30bdd28c54a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:20 +0100
+Subject: [PATCH 2/5] net: phy: qcom: create and move functions to shared
+ library
+
+Create and move functions to shared library in preparation for qca83xx
+PHY Family to be detached from at803x driver.
+
+Only the shared defines are moved to the shared qcom.h header.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-3-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/Kconfig        |  4 ++
+ drivers/net/phy/qcom/Makefile       |  1 +
+ drivers/net/phy/qcom/at803x.c       | 69 +----------------------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 53 ++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         | 34 ++++++++++++++
+ 5 files changed, 94 insertions(+), 67 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/qcom-phy-lib.c
+ create mode 100644 drivers/net/phy/qcom/qcom.h
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -1,6 +1,10 @@
+ # SPDX-License-Identifier: GPL-2.0-only
++config QCOM_NET_PHYLIB
++	tristate
++
+ config AT803X_PHY
+ 	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
++	select QCOM_NET_PHYLIB
+ 	depends on REGULATOR
+ 	help
+ 	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -1,2 +1,3 @@
+ # SPDX-License-Identifier: GPL-2.0
++obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -22,6 +22,8 @@
+ #include <linux/sfp.h>
+ #include <dt-bindings/net/qca-ar803x.h>
+ 
++#include "qcom.h"
++
+ #define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
+ #define AT803X_SFC_ASSERT_CRS			BIT(11)
+ #define AT803X_SFC_FORCE_LINK			BIT(10)
+@@ -84,9 +86,6 @@
+ #define AT803X_REG_CHIP_CONFIG			0x1f
+ #define AT803X_BT_BX_REG_SEL			0x8000
+ 
+-#define AT803X_DEBUG_ADDR			0x1D
+-#define AT803X_DEBUG_DATA			0x1E
+-
+ #define AT803X_MODE_CFG_MASK			0x0F
+ #define AT803X_MODE_CFG_BASET_RGMII		0x00
+ #define AT803X_MODE_CFG_BASET_SGMII		0x01
+@@ -103,19 +102,6 @@
+ #define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
+ #define AT803X_PSSR_MR_AN_COMPLETE		0x0200
+ 
+-#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
+-#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
+-#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
+-#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
+-
+-#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
+-#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
+-
+-#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
+-#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
+-#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
+-#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
+-
+ #define AT803X_DEBUG_REG_3C			0x3C
+ 
+ #define AT803X_DEBUG_REG_GREEN			0x3D
+@@ -393,18 +379,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+-enum stat_access_type {
+-	PHY,
+-	MMD
+-};
+-
+-struct at803x_hw_stat {
+-	const char *string;
+-	u8 reg;
+-	u32 mask;
+-	enum stat_access_type access_type;
+-};
+-
+ static struct at803x_hw_stat qca83xx_hw_stats[] = {
+ 	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
+ 	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
+@@ -439,45 +413,6 @@ struct at803x_context {
+ 	u16 led_control;
+ };
+ 
+-static int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, data);
+-}
+-
+-static int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
+-{
+-	int ret;
+-
+-	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	return phy_read(phydev, AT803X_DEBUG_DATA);
+-}
+-
+-static int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+-				 u16 clear, u16 set)
+-{
+-	u16 val;
+-	int ret;
+-
+-	ret = at803x_debug_reg_read(phydev, reg);
+-	if (ret < 0)
+-		return ret;
+-
+-	val = ret & 0xffff;
+-	val &= ~clear;
+-	val |= set;
+-
+-	return phy_write(phydev, AT803X_DEBUG_DATA, val);
+-}
+-
+ static int at803x_write_page(struct phy_device *phydev, int page)
+ {
+ 	int mask;
+--- /dev/null
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -0,0 +1,53 @@
++// SPDX-License-Identifier: GPL-2.0
++
++#include <linux/phy.h>
++#include <linux/module.h>
++
++#include "qcom.h"
++
++MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL");
++
++int at803x_debug_reg_read(struct phy_device *phydev, u16 reg)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_read(phydev, AT803X_DEBUG_DATA);
++}
++EXPORT_SYMBOL_GPL(at803x_debug_reg_read);
++
++int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
++			  u16 clear, u16 set)
++{
++	u16 val;
++	int ret;
++
++	ret = at803x_debug_reg_read(phydev, reg);
++	if (ret < 0)
++		return ret;
++
++	val = ret & 0xffff;
++	val &= ~clear;
++	val |= set;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, val);
++}
++EXPORT_SYMBOL_GPL(at803x_debug_reg_mask);
++
++int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data)
++{
++	int ret;
++
++	ret = phy_write(phydev, AT803X_DEBUG_ADDR, reg);
++	if (ret < 0)
++		return ret;
++
++	return phy_write(phydev, AT803X_DEBUG_DATA, data);
++}
++EXPORT_SYMBOL_GPL(at803x_debug_reg_write);
+--- /dev/null
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -0,0 +1,34 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++
++#define AT803X_DEBUG_ADDR			0x1D
++#define AT803X_DEBUG_DATA			0x1E
++
++#define AT803X_DEBUG_ANALOG_TEST_CTRL		0x00
++#define QCA8327_DEBUG_MANU_CTRL_EN		BIT(2)
++#define QCA8337_DEBUG_MANU_CTRL_EN		GENMASK(3, 2)
++#define AT803X_DEBUG_RX_CLK_DLY_EN		BIT(15)
++
++#define AT803X_DEBUG_SYSTEM_CTRL_MODE		0x05
++#define AT803X_DEBUG_TX_CLK_DLY_EN		BIT(8)
++
++#define AT803X_DEBUG_REG_HIB_CTRL		0x0b
++#define   AT803X_DEBUG_HIB_CTRL_SEL_RST_80U	BIT(10)
++#define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
++#define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
++
++enum stat_access_type {
++	PHY,
++	MMD
++};
++
++struct at803x_hw_stat {
++	const char *string;
++	u8 reg;
++	u32 mask;
++	enum stat_access_type access_type;
++};
++
++int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
++int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
++			  u16 clear, u16 set);
++int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch b/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch
new file mode 100644
index 00000000000..6ac09dcb9ab
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-03-net-phy-qcom-deatch-qca83xx-PHY-driver-from-at803x.patch
@@ -0,0 +1,638 @@
+From 2e45d404d99d43bb7127b74b5dea8818df64996c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:21 +0100
+Subject: [PATCH 3/5] net: phy: qcom: deatch qca83xx PHY driver from at803x
+
+Deatch qca83xx PHY driver from at803x.
+
+The QCA83xx PHYs implement specific function and doesn't use generic
+at803x so it can be detached from the driver and moved to a dedicated
+one.
+
+Probe function and priv struct is reimplemented to allocate and use
+only the qca83xx specific data. Unused data from at803x PHY driver
+are dropped from at803x priv struct.
+
+This is to make slimmer PHY drivers instead of including lots of bloat
+that would never be used in specific SoC.
+
+A new Kconfig flag QCA83XX_PHY is introduced to compile the new
+introduced PHY driver.
+
+As the Kconfig name starts with Qualcomm the same order is kept.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-4-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/Kconfig   |  11 +-
+ drivers/net/phy/qcom/Makefile  |   1 +
+ drivers/net/phy/qcom/at803x.c  | 235 ----------------------------
+ drivers/net/phy/qcom/qca83xx.c | 275 +++++++++++++++++++++++++++++++++
+ 4 files changed, 284 insertions(+), 238 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/qca83xx.c
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -3,9 +3,14 @@ config QCOM_NET_PHYLIB
+ 	tristate
+ 
+ config AT803X_PHY
+-	tristate "Qualcomm Atheros AR803X PHYs and QCA833x PHYs"
++	tristate "Qualcomm Atheros AR803X PHYs"
+ 	select QCOM_NET_PHYLIB
+ 	depends on REGULATOR
+ 	help
+-	  Currently supports the AR8030, AR8031, AR8033, AR8035 and internal
+-	  QCA8337(Internal qca8k PHY) model
++	  Currently supports the AR8030, AR8031, AR8033, AR8035 model
++
++config QCA83XX_PHY
++	tristate "Qualcomm Atheros QCA833x PHYs"
++	select QCOM_NET_PHYLIB
++	help
++	  Currently supports the internal QCA8337(Internal qca8k PHY) model
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -1,3 +1,4 @@
+ # SPDX-License-Identifier: GPL-2.0
+ obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
++obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -102,17 +102,10 @@
+ #define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
+ #define AT803X_PSSR_MR_AN_COMPLETE		0x0200
+ 
+-#define AT803X_DEBUG_REG_3C			0x3C
+-
+-#define AT803X_DEBUG_REG_GREEN			0x3D
+-#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
+-
+ #define AT803X_DEBUG_REG_1F			0x1F
+ #define AT803X_DEBUG_PLL_ON			BIT(2)
+ #define AT803X_DEBUG_RGMII_1V8			BIT(3)
+ 
+-#define MDIO_AZ_DEBUG				0x800D
+-
+ /* AT803x supports either the XTAL input pad, an internal PLL or the
+  * DSP as clock reference for the clock output pad. The XTAL reference
+  * is only used for 25 MHz output, all other frequencies need the PLL.
+@@ -163,13 +156,7 @@
+ 
+ #define QCA8081_PHY_ID				0x004dd101
+ 
+-#define QCA8327_A_PHY_ID			0x004dd033
+-#define QCA8327_B_PHY_ID			0x004dd034
+-#define QCA8337_PHY_ID				0x004dd036
+ #define QCA9561_PHY_ID				0x004dd042
+-#define QCA8K_PHY_ID_MASK			0xffffffff
+-
+-#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
+ 
+ #define AT803X_PAGE_FIBER			0
+ #define AT803X_PAGE_COPPER			1
+@@ -379,12 +366,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+-static struct at803x_hw_stat qca83xx_hw_stats[] = {
+-	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
+-	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
+-	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
+-};
+-
+ struct at803x_ss_mask {
+ 	u16 speed_mask;
+ 	u8 speed_shift;
+@@ -400,7 +381,6 @@ struct at803x_priv {
+ 	bool is_1000basex;
+ 	struct regulator_dev *vddio_rdev;
+ 	struct regulator_dev *vddh_rdev;
+-	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
+ 	int led_polarity_mode;
+ };
+ 
+@@ -564,53 +544,6 @@ static void at803x_get_wol(struct phy_de
+ 		wol->wolopts |= WAKE_MAGIC;
+ }
+ 
+-static int qca83xx_get_sset_count(struct phy_device *phydev)
+-{
+-	return ARRAY_SIZE(qca83xx_hw_stats);
+-}
+-
+-static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
+-		strscpy(data + i * ETH_GSTRING_LEN,
+-			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
+-	}
+-}
+-
+-static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
+-{
+-	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
+-	struct at803x_priv *priv = phydev->priv;
+-	int val;
+-	u64 ret;
+-
+-	if (stat.access_type == MMD)
+-		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
+-	else
+-		val = phy_read(phydev, stat.reg);
+-
+-	if (val < 0) {
+-		ret = U64_MAX;
+-	} else {
+-		val = val & stat.mask;
+-		priv->stats[i] += val;
+-		ret = priv->stats[i];
+-	}
+-
+-	return ret;
+-}
+-
+-static void qca83xx_get_stats(struct phy_device *phydev,
+-			      struct ethtool_stats *stats, u64 *data)
+-{
+-	int i;
+-
+-	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
+-		data[i] = qca83xx_get_stat(phydev, i);
+-}
+-
+ static int at803x_suspend(struct phy_device *phydev)
+ {
+ 	int value;
+@@ -1707,124 +1640,6 @@ static int at8035_probe(struct phy_devic
+ 	return at8035_parse_dt(phydev);
+ }
+ 
+-static int qca83xx_config_init(struct phy_device *phydev)
+-{
+-	u8 switch_revision;
+-
+-	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
+-
+-	switch (switch_revision) {
+-	case 1:
+-		/* For 100M waveform */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
+-		/* Turn on Gigabit clock */
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
+-		break;
+-
+-	case 2:
+-		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
+-		fallthrough;
+-	case 4:
+-		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
+-		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
+-		break;
+-	}
+-
+-	/* Following original QCA sourcecode set port to prefer master */
+-	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
+-
+-	return 0;
+-}
+-
+-static int qca8327_config_init(struct phy_device *phydev)
+-{
+-	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
+-	 * Disable on init and enable only with 100m speed following
+-	 * qca original source code.
+-	 */
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-
+-	return qca83xx_config_init(phydev);
+-}
+-
+-static void qca83xx_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
+-	if (phydev->state == PHY_RUNNING) {
+-		if (phydev->speed == SPEED_100)
+-			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-					      QCA8327_DEBUG_MANU_CTRL_EN,
+-					      QCA8327_DEBUG_MANU_CTRL_EN);
+-	} else {
+-		/* Reset DAC Amplitude adjustment */
+-		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
+-				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
+-	}
+-}
+-
+-static int qca83xx_resume(struct phy_device *phydev)
+-{
+-	int ret, val;
+-
+-	/* Skip reset if not suspended */
+-	if (!phydev->suspended)
+-		return 0;
+-
+-	/* Reinit the port, reset values set by suspend */
+-	qca83xx_config_init(phydev);
+-
+-	/* Reset the port on port resume */
+-	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
+-
+-	/* On resume from suspend the switch execute a reset and
+-	 * restart auto-negotiation. Wait for reset to complete.
+-	 */
+-	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
+-				    50000, 600000, true);
+-	if (ret)
+-		return ret;
+-
+-	usleep_range(1000, 2000);
+-
+-	return 0;
+-}
+-
+-static int qca83xx_suspend(struct phy_device *phydev)
+-{
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
+-			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
+-
+-	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
+-			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
+-			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
+-
+-	return 0;
+-}
+-
+-static int qca8337_suspend(struct phy_device *phydev)
+-{
+-	/* Only QCA8337 support actual suspend. */
+-	genphy_suspend(phydev);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+-static int qca8327_suspend(struct phy_device *phydev)
+-{
+-	u16 mask = 0;
+-
+-	/* QCA8327 cause port unreliability when phy suspend
+-	 * is set.
+-	 */
+-	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
+-	phy_modify(phydev, MII_BMCR, mask, 0);
+-
+-	return qca83xx_suspend(phydev);
+-}
+-
+ static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -2599,53 +2414,6 @@ static struct phy_driver at803x_driver[]
+ 	.soft_reset		= genphy_soft_reset,
+ 	.config_aneg		= at803x_config_aneg,
+ }, {
+-	/* QCA8337 */
+-	.phy_id			= QCA8337_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8337 internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca83xx_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8337_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-A from switch QCA8327-AL1A */
+-	.phy_id			= QCA8327_A_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-A internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+-	/* QCA8327-B from switch QCA8327-BL1A */
+-	.phy_id			= QCA8327_B_PHY_ID,
+-	.phy_id_mask		= QCA8K_PHY_ID_MASK,
+-	.name			= "Qualcomm Atheros 8327-B internal PHY",
+-	/* PHY_GBIT_FEATURES */
+-	.link_change_notify	= qca83xx_link_change_notify,
+-	.probe			= at803x_probe,
+-	.flags			= PHY_IS_INTERNAL,
+-	.config_init		= qca8327_config_init,
+-	.soft_reset		= genphy_soft_reset,
+-	.get_sset_count		= qca83xx_get_sset_count,
+-	.get_strings		= qca83xx_get_strings,
+-	.get_stats		= qca83xx_get_stats,
+-	.suspend		= qca8327_suspend,
+-	.resume			= qca83xx_resume,
+-}, {
+ 	/* Qualcomm QCA8081 */
+ 	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
+ 	.name			= "Qualcomm QCA8081",
+@@ -2683,9 +2451,6 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+ 	{ }
+--- /dev/null
++++ b/drivers/net/phy/qcom/qca83xx.c
+@@ -0,0 +1,275 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <linux/phy.h>
++#include <linux/module.h>
++
++#include "qcom.h"
++
++#define AT803X_DEBUG_REG_3C			0x3C
++
++#define AT803X_DEBUG_REG_GREEN			0x3D
++#define   AT803X_DEBUG_GATE_CLK_IN1000		BIT(6)
++
++#define MDIO_AZ_DEBUG				0x800D
++
++#define QCA8327_A_PHY_ID			0x004dd033
++#define QCA8327_B_PHY_ID			0x004dd034
++#define QCA8337_PHY_ID				0x004dd036
++#define QCA8K_PHY_ID_MASK			0xffffffff
++
++#define QCA8K_DEVFLAGS_REVISION_MASK		GENMASK(2, 0)
++
++static struct at803x_hw_stat qca83xx_hw_stats[] = {
++	{ "phy_idle_errors", 0xa, GENMASK(7, 0), PHY},
++	{ "phy_receive_errors", 0x15, GENMASK(15, 0), PHY},
++	{ "eee_wake_errors", 0x16, GENMASK(15, 0), MMD},
++};
++
++struct qca83xx_priv {
++	u64 stats[ARRAY_SIZE(qca83xx_hw_stats)];
++};
++
++MODULE_DESCRIPTION("Qualcomm Atheros QCA83XX PHY driver");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_LICENSE("GPL");
++
++static int qca83xx_get_sset_count(struct phy_device *phydev)
++{
++	return ARRAY_SIZE(qca83xx_hw_stats);
++}
++
++static void qca83xx_get_strings(struct phy_device *phydev, u8 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++) {
++		strscpy(data + i * ETH_GSTRING_LEN,
++			qca83xx_hw_stats[i].string, ETH_GSTRING_LEN);
++	}
++}
++
++static u64 qca83xx_get_stat(struct phy_device *phydev, int i)
++{
++	struct at803x_hw_stat stat = qca83xx_hw_stats[i];
++	struct qca83xx_priv *priv = phydev->priv;
++	int val;
++	u64 ret;
++
++	if (stat.access_type == MMD)
++		val = phy_read_mmd(phydev, MDIO_MMD_PCS, stat.reg);
++	else
++		val = phy_read(phydev, stat.reg);
++
++	if (val < 0) {
++		ret = U64_MAX;
++	} else {
++		val = val & stat.mask;
++		priv->stats[i] += val;
++		ret = priv->stats[i];
++	}
++
++	return ret;
++}
++
++static void qca83xx_get_stats(struct phy_device *phydev,
++			      struct ethtool_stats *stats, u64 *data)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(qca83xx_hw_stats); i++)
++		data[i] = qca83xx_get_stat(phydev, i);
++}
++
++static int qca83xx_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct qca83xx_priv *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	phydev->priv = priv;
++
++	return 0;
++}
++
++static int qca83xx_config_init(struct phy_device *phydev)
++{
++	u8 switch_revision;
++
++	switch_revision = phydev->dev_flags & QCA8K_DEVFLAGS_REVISION_MASK;
++
++	switch (switch_revision) {
++	case 1:
++		/* For 100M waveform */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0x02ea);
++		/* Turn on Gigabit clock */
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x68a0);
++		break;
++
++	case 2:
++		phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0x0);
++		fallthrough;
++	case 4:
++		phy_write_mmd(phydev, MDIO_MMD_PCS, MDIO_AZ_DEBUG, 0x803f);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_GREEN, 0x6860);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0x2c46);
++		at803x_debug_reg_write(phydev, AT803X_DEBUG_REG_3C, 0x6000);
++		break;
++	}
++
++	/* Following original QCA sourcecode set port to prefer master */
++	phy_set_bits(phydev, MII_CTRL1000, CTL1000_PREFER_MASTER);
++
++	return 0;
++}
++
++static int qca8327_config_init(struct phy_device *phydev)
++{
++	/* QCA8327 require DAC amplitude adjustment for 100m set to +6%.
++	 * Disable on init and enable only with 100m speed following
++	 * qca original source code.
++	 */
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++			      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++
++	return qca83xx_config_init(phydev);
++}
++
++static void qca83xx_link_change_notify(struct phy_device *phydev)
++{
++	/* Set DAC Amplitude adjustment to +6% for 100m on link running */
++	if (phydev->state == PHY_RUNNING) {
++		if (phydev->speed == SPEED_100)
++			at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++					      QCA8327_DEBUG_MANU_CTRL_EN,
++					      QCA8327_DEBUG_MANU_CTRL_EN);
++	} else {
++		/* Reset DAC Amplitude adjustment */
++		at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
++				      QCA8327_DEBUG_MANU_CTRL_EN, 0);
++	}
++}
++
++static int qca83xx_resume(struct phy_device *phydev)
++{
++	int ret, val;
++
++	/* Skip reset if not suspended */
++	if (!phydev->suspended)
++		return 0;
++
++	/* Reinit the port, reset values set by suspend */
++	qca83xx_config_init(phydev);
++
++	/* Reset the port on port resume */
++	phy_set_bits(phydev, MII_BMCR, BMCR_RESET | BMCR_ANENABLE);
++
++	/* On resume from suspend the switch execute a reset and
++	 * restart auto-negotiation. Wait for reset to complete.
++	 */
++	ret = phy_read_poll_timeout(phydev, MII_BMCR, val, !(val & BMCR_RESET),
++				    50000, 600000, true);
++	if (ret)
++		return ret;
++
++	usleep_range(1000, 2000);
++
++	return 0;
++}
++
++static int qca83xx_suspend(struct phy_device *phydev)
++{
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_GREEN,
++			      AT803X_DEBUG_GATE_CLK_IN1000, 0);
++
++	at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
++			      AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE |
++			      AT803X_DEBUG_HIB_CTRL_SEL_RST_80U, 0);
++
++	return 0;
++}
++
++static int qca8337_suspend(struct phy_device *phydev)
++{
++	/* Only QCA8337 support actual suspend. */
++	genphy_suspend(phydev);
++
++	return qca83xx_suspend(phydev);
++}
++
++static int qca8327_suspend(struct phy_device *phydev)
++{
++	u16 mask = 0;
++
++	/* QCA8327 cause port unreliability when phy suspend
++	 * is set.
++	 */
++	mask |= ~(BMCR_SPEED1000 | BMCR_FULLDPLX);
++	phy_modify(phydev, MII_BMCR, mask, 0);
++
++	return qca83xx_suspend(phydev);
++}
++
++static struct phy_driver qca83xx_driver[] = {
++{
++	/* QCA8337 */
++	.phy_id			= QCA8337_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8337 internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.probe			= qca83xx_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca83xx_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8337_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-A from switch QCA8327-AL1A */
++	.phy_id			= QCA8327_A_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-A internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= qca83xx_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, {
++	/* QCA8327-B from switch QCA8327-BL1A */
++	.phy_id			= QCA8327_B_PHY_ID,
++	.phy_id_mask		= QCA8K_PHY_ID_MASK,
++	.name			= "Qualcomm Atheros 8327-B internal PHY",
++	/* PHY_GBIT_FEATURES */
++	.link_change_notify	= qca83xx_link_change_notify,
++	.probe			= qca83xx_probe,
++	.flags			= PHY_IS_INTERNAL,
++	.config_init		= qca8327_config_init,
++	.soft_reset		= genphy_soft_reset,
++	.get_sset_count		= qca83xx_get_sset_count,
++	.get_strings		= qca83xx_get_strings,
++	.get_stats		= qca83xx_get_stats,
++	.suspend		= qca8327_suspend,
++	.resume			= qca83xx_resume,
++}, };
++
++module_phy_driver(qca83xx_driver);
++
++static struct mdio_device_id __maybe_unused qca83xx_tbl[] = {
++	{ PHY_ID_MATCH_EXACT(QCA8337_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_A_PHY_ID) },
++	{ PHY_ID_MATCH_EXACT(QCA8327_B_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, qca83xx_tbl);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch b/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch
new file mode 100644
index 00000000000..9c43ad13b44
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-04-net-phy-qcom-move-additional-functions-to-shared-lib.patch
@@ -0,0 +1,1014 @@
+From 249d2b80e4db0e38503ed0ec2af6c7401bc099b9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:22 +0100
+Subject: [PATCH 4/5] net: phy: qcom: move additional functions to shared
+ library
+
+Move additional functions to shared library in preparation for qca808x
+PHY Family to be detached from at803x driver.
+
+Only the shared defines are moved to the shared qcom.h header.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-5-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/at803x.c       | 426 +---------------------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 376 ++++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         |  86 ++++++
+ 3 files changed, 463 insertions(+), 425 deletions(-)
+
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -24,65 +24,11 @@
+ 
+ #include "qcom.h"
+ 
+-#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
+-#define AT803X_SFC_ASSERT_CRS			BIT(11)
+-#define AT803X_SFC_FORCE_LINK			BIT(10)
+-#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
+-#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
+-#define AT803X_SFC_MANUAL_MDIX			0x1
+-#define AT803X_SFC_MANUAL_MDI			0x0
+-#define AT803X_SFC_SQE_TEST			BIT(2)
+-#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
+-#define AT803X_SFC_DISABLE_JABBER		BIT(0)
+-
+-#define AT803X_SPECIFIC_STATUS			0x11
+-#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
+-#define AT803X_SS_SPEED_1000			2
+-#define AT803X_SS_SPEED_100			1
+-#define AT803X_SS_SPEED_10			0
+-#define AT803X_SS_DUPLEX			BIT(13)
+-#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
+-#define AT803X_SS_MDIX				BIT(6)
+-
+-#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
+-#define QCA808X_SS_SPEED_2500			4
+-
+-#define AT803X_INTR_ENABLE			0x12
+-#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
+-#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
+-#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
+-#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
+-#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
+-#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
+-#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
+-#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
+-#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
+-#define AT803X_INTR_ENABLE_WOL			BIT(0)
+-
+-#define AT803X_INTR_STATUS			0x13
+-
+-#define AT803X_SMART_SPEED			0x14
+-#define AT803X_SMART_SPEED_ENABLE		BIT(5)
+-#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
+-#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
+-#define AT803X_CDT				0x16
+-#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_ENABLE_TEST			BIT(0)
+-#define AT803X_CDT_STATUS			0x1c
+-#define AT803X_CDT_STATUS_STAT_NORMAL		0
+-#define AT803X_CDT_STATUS_STAT_SHORT		1
+-#define AT803X_CDT_STATUS_STAT_OPEN		2
+-#define AT803X_CDT_STATUS_STAT_FAIL		3
+-#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
+-#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
+ #define AT803X_LED_CONTROL			0x18
+ 
+ #define AT803X_PHY_MMD3_WOL_CTRL		0x8012
+ #define AT803X_WOL_EN				BIT(5)
+-#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+-#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+-#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
++
+ #define AT803X_REG_CHIP_CONFIG			0x1f
+ #define AT803X_BT_BX_REG_SEL			0x8000
+ 
+@@ -138,10 +84,6 @@
+ #define AT803X_CLK_OUT_STRENGTH_HALF		1
+ #define AT803X_CLK_OUT_STRENGTH_QUARTER		2
+ 
+-#define AT803X_DEFAULT_DOWNSHIFT		5
+-#define AT803X_MIN_DOWNSHIFT			2
+-#define AT803X_MAX_DOWNSHIFT			9
+-
+ #define AT803X_MMD3_SMARTEEE_CTL1		0x805b
+ #define AT803X_MMD3_SMARTEEE_CTL2		0x805c
+ #define AT803X_MMD3_SMARTEEE_CTL3		0x805d
+@@ -366,11 +308,6 @@ MODULE_DESCRIPTION("Qualcomm Atheros AR8
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+-struct at803x_ss_mask {
+-	u16 speed_mask;
+-	u8 speed_shift;
+-};
+-
+ struct at803x_priv {
+ 	int flags;
+ 	u16 clk_25m_reg;
+@@ -470,80 +407,6 @@ static void at803x_context_restore(struc
+ 	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
+ }
+ 
+-static int at803x_set_wol(struct phy_device *phydev,
+-			  struct ethtool_wolinfo *wol)
+-{
+-	int ret, irq_enabled;
+-
+-	if (wol->wolopts & WAKE_MAGIC) {
+-		struct net_device *ndev = phydev->attached_dev;
+-		const u8 *mac;
+-		unsigned int i;
+-		static const unsigned int offsets[] = {
+-			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
+-			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
+-			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
+-		};
+-
+-		if (!ndev)
+-			return -ENODEV;
+-
+-		mac = (const u8 *)ndev->dev_addr;
+-
+-		if (!is_valid_ether_addr(mac))
+-			return -EINVAL;
+-
+-		for (i = 0; i < 3; i++)
+-			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
+-				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
+-
+-		/* Enable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
+-		if (ret)
+-			return ret;
+-	} else {
+-		/* Disable WOL interrupt */
+-		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	/* Clear WOL status */
+-	ret = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Check if there are other interrupts except for WOL triggered when PHY is
+-	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
+-	 * be passed up to the interrupt PIN.
+-	 */
+-	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (irq_enabled < 0)
+-		return irq_enabled;
+-
+-	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
+-	if (ret & irq_enabled && !phy_polling_mode(phydev))
+-		phy_trigger_machine(phydev);
+-
+-	return 0;
+-}
+-
+-static void at803x_get_wol(struct phy_device *phydev,
+-			   struct ethtool_wolinfo *wol)
+-{
+-	int value;
+-
+-	wol->supported = WAKE_MAGIC;
+-	wol->wolopts = 0;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (value < 0)
+-		return;
+-
+-	if (value & AT803X_INTR_ENABLE_WOL)
+-		wol->wolopts |= WAKE_MAGIC;
+-}
+-
+ static int at803x_suspend(struct phy_device *phydev)
+ {
+ 	int value;
+@@ -816,73 +679,6 @@ static int at803x_config_init(struct phy
+ 	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
+ }
+ 
+-static int at803x_ack_interrupt(struct phy_device *phydev)
+-{
+-	int err;
+-
+-	err = phy_read(phydev, AT803X_INTR_STATUS);
+-
+-	return (err < 0) ? err : 0;
+-}
+-
+-static int at803x_config_intr(struct phy_device *phydev)
+-{
+-	int err;
+-	int value;
+-
+-	value = phy_read(phydev, AT803X_INTR_ENABLE);
+-
+-	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-		if (err)
+-			return err;
+-
+-		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
+-		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
+-		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
+-		value |= AT803X_INTR_ENABLE_LINK_FAIL;
+-		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
+-
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
+-	} else {
+-		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
+-		if (err)
+-			return err;
+-
+-		/* Clear any pending interrupts */
+-		err = at803x_ack_interrupt(phydev);
+-	}
+-
+-	return err;
+-}
+-
+-static irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
+-{
+-	int irq_status, int_enabled;
+-
+-	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
+-	if (irq_status < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* Read the current enabled interrupts */
+-	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
+-	if (int_enabled < 0) {
+-		phy_error(phydev);
+-		return IRQ_NONE;
+-	}
+-
+-	/* See if this was one of our enabled interrupts */
+-	if (!(irq_status & int_enabled))
+-		return IRQ_NONE;
+-
+-	phy_trigger_machine(phydev);
+-
+-	return IRQ_HANDLED;
+-}
+-
+ static void at803x_link_change_notify(struct phy_device *phydev)
+ {
+ 	/*
+@@ -908,69 +704,6 @@ static void at803x_link_change_notify(st
+ 	}
+ }
+ 
+-static int at803x_read_specific_status(struct phy_device *phydev,
+-				       struct at803x_ss_mask ss_mask)
+-{
+-	int ss;
+-
+-	/* Read the AT8035 PHY-Specific Status register, which indicates the
+-	 * speed and duplex that the PHY is actually using, irrespective of
+-	 * whether we are in autoneg mode or not.
+-	 */
+-	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
+-	if (ss < 0)
+-		return ss;
+-
+-	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
+-		int sfc, speed;
+-
+-		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
+-		if (sfc < 0)
+-			return sfc;
+-
+-		speed = ss & ss_mask.speed_mask;
+-		speed >>= ss_mask.speed_shift;
+-
+-		switch (speed) {
+-		case AT803X_SS_SPEED_10:
+-			phydev->speed = SPEED_10;
+-			break;
+-		case AT803X_SS_SPEED_100:
+-			phydev->speed = SPEED_100;
+-			break;
+-		case AT803X_SS_SPEED_1000:
+-			phydev->speed = SPEED_1000;
+-			break;
+-		case QCA808X_SS_SPEED_2500:
+-			phydev->speed = SPEED_2500;
+-			break;
+-		}
+-		if (ss & AT803X_SS_DUPLEX)
+-			phydev->duplex = DUPLEX_FULL;
+-		else
+-			phydev->duplex = DUPLEX_HALF;
+-
+-		if (ss & AT803X_SS_MDIX)
+-			phydev->mdix = ETH_TP_MDI_X;
+-		else
+-			phydev->mdix = ETH_TP_MDI;
+-
+-		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
+-		case AT803X_SFC_MANUAL_MDI:
+-			phydev->mdix_ctrl = ETH_TP_MDI;
+-			break;
+-		case AT803X_SFC_MANUAL_MDIX:
+-			phydev->mdix_ctrl = ETH_TP_MDI_X;
+-			break;
+-		case AT803X_SFC_AUTOMATIC_CROSSOVER:
+-			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
+-			break;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+ static int at803x_read_status(struct phy_device *phydev)
+ {
+ 	struct at803x_ss_mask ss_mask = { 0 };
+@@ -1006,50 +739,6 @@ static int at803x_read_status(struct phy
+ 	return 0;
+ }
+ 
+-static int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
+-{
+-	u16 val;
+-
+-	switch (ctrl) {
+-	case ETH_TP_MDI:
+-		val = AT803X_SFC_MANUAL_MDI;
+-		break;
+-	case ETH_TP_MDI_X:
+-		val = AT803X_SFC_MANUAL_MDIX;
+-		break;
+-	case ETH_TP_MDI_AUTO:
+-		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
+-		break;
+-	default:
+-		return 0;
+-	}
+-
+-	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
+-			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
+-			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
+-}
+-
+-static int at803x_prepare_config_aneg(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Changes of the midx bits are disruptive to the normal operation;
+-	 * therefore any changes to these registers must be followed by a
+-	 * software reset to take effect.
+-	 */
+-	if (ret == 1) {
+-		ret = genphy_soft_reset(phydev);
+-		if (ret < 0)
+-			return ret;
+-	}
+-
+-	return 0;
+-}
+-
+ static int at803x_config_aneg(struct phy_device *phydev)
+ {
+ 	struct at803x_priv *priv = phydev->priv;
+@@ -1065,80 +754,6 @@ static int at803x_config_aneg(struct phy
+ 	return genphy_config_aneg(phydev);
+ }
+ 
+-static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
+-{
+-	int val;
+-
+-	val = phy_read(phydev, AT803X_SMART_SPEED);
+-	if (val < 0)
+-		return val;
+-
+-	if (val & AT803X_SMART_SPEED_ENABLE)
+-		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
+-	else
+-		*d = DOWNSHIFT_DEV_DISABLE;
+-
+-	return 0;
+-}
+-
+-static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
+-{
+-	u16 mask, set;
+-	int ret;
+-
+-	switch (cnt) {
+-	case DOWNSHIFT_DEV_DEFAULT_COUNT:
+-		cnt = AT803X_DEFAULT_DOWNSHIFT;
+-		fallthrough;
+-	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
+-		set = AT803X_SMART_SPEED_ENABLE |
+-		      AT803X_SMART_SPEED_BYPASS_TIMER |
+-		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
+-		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
+-		break;
+-	case DOWNSHIFT_DEV_DISABLE:
+-		set = 0;
+-		mask = AT803X_SMART_SPEED_ENABLE |
+-		       AT803X_SMART_SPEED_BYPASS_TIMER;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
+-
+-	/* After changing the smart speed settings, we need to perform a
+-	 * software reset, use phy_init_hw() to make sure we set the
+-	 * reapply any values which might got lost during software reset.
+-	 */
+-	if (ret == 1)
+-		ret = phy_init_hw(phydev);
+-
+-	return ret;
+-}
+-
+-static int at803x_get_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_get_downshift(phydev, data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+-static int at803x_set_tunable(struct phy_device *phydev,
+-			      struct ethtool_tunable *tuna, const void *data)
+-{
+-	switch (tuna->id) {
+-	case ETHTOOL_PHY_DOWNSHIFT:
+-		return at803x_set_downshift(phydev, *(const u8 *)data);
+-	default:
+-		return -EOPNOTSUPP;
+-	}
+-}
+-
+ static int at803x_cable_test_result_trans(u16 status)
+ {
+ 	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
+@@ -1170,45 +785,6 @@ static bool at803x_cdt_fault_length_vali
+ 	return false;
+ }
+ 
+-static int at803x_cdt_fault_length(int dt)
+-{
+-	/* According to the datasheet the distance to the fault is
+-	 * DELTA_TIME * 0.824 meters.
+-	 *
+-	 * The author suspect the correct formula is:
+-	 *
+-	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
+-	 *
+-	 * where c is the speed of light, VF is the velocity factor of
+-	 * the twisted pair cable, 125MHz the counter frequency and
+-	 * we need to divide by 2 because the hardware will measure the
+-	 * round trip time to the fault and back to the PHY.
+-	 *
+-	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
+-	 * datasheet.
+-	 */
+-	return (dt * 824) / 10;
+-}
+-
+-static int at803x_cdt_start(struct phy_device *phydev,
+-			    u32 cdt_start)
+-{
+-	return phy_write(phydev, AT803X_CDT, cdt_start);
+-}
+-
+-static int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+-					  u32 cdt_en)
+-{
+-	int val, ret;
+-
+-	/* One test run takes about 25ms */
+-	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
+-				    !(val & cdt_en),
+-				    30000, 100000, true);
+-
+-	return ret < 0 ? ret : 0;
+-}
+-
+ static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
+ {
+ 	static const int ethtool_pair[] = {
+--- a/drivers/net/phy/qcom/qcom-phy-lib.c
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -3,6 +3,9 @@
+ #include <linux/phy.h>
+ #include <linux/module.h>
+ 
++#include <linux/netdevice.h>
++#include <linux/etherdevice.h>
++
+ #include "qcom.h"
+ 
+ MODULE_DESCRIPTION("Qualcomm PHY driver Common Functions");
+@@ -51,3 +54,376 @@ int at803x_debug_reg_write(struct phy_de
+ 	return phy_write(phydev, AT803X_DEBUG_DATA, data);
+ }
+ EXPORT_SYMBOL_GPL(at803x_debug_reg_write);
++
++int at803x_set_wol(struct phy_device *phydev,
++		   struct ethtool_wolinfo *wol)
++{
++	int ret, irq_enabled;
++
++	if (wol->wolopts & WAKE_MAGIC) {
++		struct net_device *ndev = phydev->attached_dev;
++		const u8 *mac;
++		unsigned int i;
++		static const unsigned int offsets[] = {
++			AT803X_LOC_MAC_ADDR_32_47_OFFSET,
++			AT803X_LOC_MAC_ADDR_16_31_OFFSET,
++			AT803X_LOC_MAC_ADDR_0_15_OFFSET,
++		};
++
++		if (!ndev)
++			return -ENODEV;
++
++		mac = (const u8 *)ndev->dev_addr;
++
++		if (!is_valid_ether_addr(mac))
++			return -EINVAL;
++
++		for (i = 0; i < 3; i++)
++			phy_write_mmd(phydev, MDIO_MMD_PCS, offsets[i],
++				      mac[(i * 2) + 1] | (mac[(i * 2)] << 8));
++
++		/* Enable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, 0, AT803X_INTR_ENABLE_WOL);
++		if (ret)
++			return ret;
++	} else {
++		/* Disable WOL interrupt */
++		ret = phy_modify(phydev, AT803X_INTR_ENABLE, AT803X_INTR_ENABLE_WOL, 0);
++		if (ret)
++			return ret;
++	}
++
++	/* Clear WOL status */
++	ret = phy_read(phydev, AT803X_INTR_STATUS);
++	if (ret < 0)
++		return ret;
++
++	/* Check if there are other interrupts except for WOL triggered when PHY is
++	 * in interrupt mode, only the interrupts enabled by AT803X_INTR_ENABLE can
++	 * be passed up to the interrupt PIN.
++	 */
++	irq_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (irq_enabled < 0)
++		return irq_enabled;
++
++	irq_enabled &= ~AT803X_INTR_ENABLE_WOL;
++	if (ret & irq_enabled && !phy_polling_mode(phydev))
++		phy_trigger_machine(phydev);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_set_wol);
++
++void at803x_get_wol(struct phy_device *phydev,
++		    struct ethtool_wolinfo *wol)
++{
++	int value;
++
++	wol->supported = WAKE_MAGIC;
++	wol->wolopts = 0;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (value < 0)
++		return;
++
++	if (value & AT803X_INTR_ENABLE_WOL)
++		wol->wolopts |= WAKE_MAGIC;
++}
++EXPORT_SYMBOL_GPL(at803x_get_wol);
++
++int at803x_ack_interrupt(struct phy_device *phydev)
++{
++	int err;
++
++	err = phy_read(phydev, AT803X_INTR_STATUS);
++
++	return (err < 0) ? err : 0;
++}
++EXPORT_SYMBOL_GPL(at803x_ack_interrupt);
++
++int at803x_config_intr(struct phy_device *phydev)
++{
++	int err;
++	int value;
++
++	value = phy_read(phydev, AT803X_INTR_ENABLE);
++
++	if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++		if (err)
++			return err;
++
++		value |= AT803X_INTR_ENABLE_AUTONEG_ERR;
++		value |= AT803X_INTR_ENABLE_SPEED_CHANGED;
++		value |= AT803X_INTR_ENABLE_DUPLEX_CHANGED;
++		value |= AT803X_INTR_ENABLE_LINK_FAIL;
++		value |= AT803X_INTR_ENABLE_LINK_SUCCESS;
++
++		err = phy_write(phydev, AT803X_INTR_ENABLE, value);
++	} else {
++		err = phy_write(phydev, AT803X_INTR_ENABLE, 0);
++		if (err)
++			return err;
++
++		/* Clear any pending interrupts */
++		err = at803x_ack_interrupt(phydev);
++	}
++
++	return err;
++}
++EXPORT_SYMBOL_GPL(at803x_config_intr);
++
++irqreturn_t at803x_handle_interrupt(struct phy_device *phydev)
++{
++	int irq_status, int_enabled;
++
++	irq_status = phy_read(phydev, AT803X_INTR_STATUS);
++	if (irq_status < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* Read the current enabled interrupts */
++	int_enabled = phy_read(phydev, AT803X_INTR_ENABLE);
++	if (int_enabled < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	/* See if this was one of our enabled interrupts */
++	if (!(irq_status & int_enabled))
++		return IRQ_NONE;
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++EXPORT_SYMBOL_GPL(at803x_handle_interrupt);
++
++int at803x_read_specific_status(struct phy_device *phydev,
++				struct at803x_ss_mask ss_mask)
++{
++	int ss;
++
++	/* Read the AT8035 PHY-Specific Status register, which indicates the
++	 * speed and duplex that the PHY is actually using, irrespective of
++	 * whether we are in autoneg mode or not.
++	 */
++	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
++	if (ss < 0)
++		return ss;
++
++	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
++		int sfc, speed;
++
++		sfc = phy_read(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL);
++		if (sfc < 0)
++			return sfc;
++
++		speed = ss & ss_mask.speed_mask;
++		speed >>= ss_mask.speed_shift;
++
++		switch (speed) {
++		case AT803X_SS_SPEED_10:
++			phydev->speed = SPEED_10;
++			break;
++		case AT803X_SS_SPEED_100:
++			phydev->speed = SPEED_100;
++			break;
++		case AT803X_SS_SPEED_1000:
++			phydev->speed = SPEED_1000;
++			break;
++		case QCA808X_SS_SPEED_2500:
++			phydev->speed = SPEED_2500;
++			break;
++		}
++		if (ss & AT803X_SS_DUPLEX)
++			phydev->duplex = DUPLEX_FULL;
++		else
++			phydev->duplex = DUPLEX_HALF;
++
++		if (ss & AT803X_SS_MDIX)
++			phydev->mdix = ETH_TP_MDI_X;
++		else
++			phydev->mdix = ETH_TP_MDI;
++
++		switch (FIELD_GET(AT803X_SFC_MDI_CROSSOVER_MODE_M, sfc)) {
++		case AT803X_SFC_MANUAL_MDI:
++			phydev->mdix_ctrl = ETH_TP_MDI;
++			break;
++		case AT803X_SFC_MANUAL_MDIX:
++			phydev->mdix_ctrl = ETH_TP_MDI_X;
++			break;
++		case AT803X_SFC_AUTOMATIC_CROSSOVER:
++			phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
++			break;
++		}
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_read_specific_status);
++
++int at803x_config_mdix(struct phy_device *phydev, u8 ctrl)
++{
++	u16 val;
++
++	switch (ctrl) {
++	case ETH_TP_MDI:
++		val = AT803X_SFC_MANUAL_MDI;
++		break;
++	case ETH_TP_MDI_X:
++		val = AT803X_SFC_MANUAL_MDIX;
++		break;
++	case ETH_TP_MDI_AUTO:
++		val = AT803X_SFC_AUTOMATIC_CROSSOVER;
++		break;
++	default:
++		return 0;
++	}
++
++	return phy_modify_changed(phydev, AT803X_SPECIFIC_FUNCTION_CONTROL,
++			  AT803X_SFC_MDI_CROSSOVER_MODE_M,
++			  FIELD_PREP(AT803X_SFC_MDI_CROSSOVER_MODE_M, val));
++}
++EXPORT_SYMBOL_GPL(at803x_config_mdix);
++
++int at803x_prepare_config_aneg(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = at803x_config_mdix(phydev, phydev->mdix_ctrl);
++	if (ret < 0)
++		return ret;
++
++	/* Changes of the midx bits are disruptive to the normal operation;
++	 * therefore any changes to these registers must be followed by a
++	 * software reset to take effect.
++	 */
++	if (ret == 1) {
++		ret = genphy_soft_reset(phydev);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_prepare_config_aneg);
++
++static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
++{
++	int val;
++
++	val = phy_read(phydev, AT803X_SMART_SPEED);
++	if (val < 0)
++		return val;
++
++	if (val & AT803X_SMART_SPEED_ENABLE)
++		*d = FIELD_GET(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, val) + 2;
++	else
++		*d = DOWNSHIFT_DEV_DISABLE;
++
++	return 0;
++}
++
++static int at803x_set_downshift(struct phy_device *phydev, u8 cnt)
++{
++	u16 mask, set;
++	int ret;
++
++	switch (cnt) {
++	case DOWNSHIFT_DEV_DEFAULT_COUNT:
++		cnt = AT803X_DEFAULT_DOWNSHIFT;
++		fallthrough;
++	case AT803X_MIN_DOWNSHIFT ... AT803X_MAX_DOWNSHIFT:
++		set = AT803X_SMART_SPEED_ENABLE |
++		      AT803X_SMART_SPEED_BYPASS_TIMER |
++		      FIELD_PREP(AT803X_SMART_SPEED_RETRY_LIMIT_MASK, cnt - 2);
++		mask = AT803X_SMART_SPEED_RETRY_LIMIT_MASK;
++		break;
++	case DOWNSHIFT_DEV_DISABLE:
++		set = 0;
++		mask = AT803X_SMART_SPEED_ENABLE |
++		       AT803X_SMART_SPEED_BYPASS_TIMER;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	ret = phy_modify_changed(phydev, AT803X_SMART_SPEED, mask, set);
++
++	/* After changing the smart speed settings, we need to perform a
++	 * software reset, use phy_init_hw() to make sure we set the
++	 * reapply any values which might got lost during software reset.
++	 */
++	if (ret == 1)
++		ret = phy_init_hw(phydev);
++
++	return ret;
++}
++
++int at803x_get_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_get_downshift(phydev, data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++EXPORT_SYMBOL_GPL(at803x_get_tunable);
++
++int at803x_set_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, const void *data)
++{
++	switch (tuna->id) {
++	case ETHTOOL_PHY_DOWNSHIFT:
++		return at803x_set_downshift(phydev, *(const u8 *)data);
++	default:
++		return -EOPNOTSUPP;
++	}
++}
++EXPORT_SYMBOL_GPL(at803x_set_tunable);
++
++int at803x_cdt_fault_length(int dt)
++{
++	/* According to the datasheet the distance to the fault is
++	 * DELTA_TIME * 0.824 meters.
++	 *
++	 * The author suspect the correct formula is:
++	 *
++	 *   fault_distance = DELTA_TIME * (c * VF) / 125MHz / 2
++	 *
++	 * where c is the speed of light, VF is the velocity factor of
++	 * the twisted pair cable, 125MHz the counter frequency and
++	 * we need to divide by 2 because the hardware will measure the
++	 * round trip time to the fault and back to the PHY.
++	 *
++	 * With a VF of 0.69 we get the factor 0.824 mentioned in the
++	 * datasheet.
++	 */
++	return (dt * 824) / 10;
++}
++EXPORT_SYMBOL_GPL(at803x_cdt_fault_length);
++
++int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start)
++{
++	return phy_write(phydev, AT803X_CDT, cdt_start);
++}
++EXPORT_SYMBOL_GPL(at803x_cdt_start);
++
++int at803x_cdt_wait_for_completion(struct phy_device *phydev,
++				   u32 cdt_en)
++{
++	int val, ret;
++
++	/* One test run takes about 25ms */
++	ret = phy_read_poll_timeout(phydev, AT803X_CDT, val,
++				    !(val & cdt_en),
++				    30000, 100000, true);
++
++	return ret < 0 ? ret : 0;
++}
++EXPORT_SYMBOL_GPL(at803x_cdt_wait_for_completion);
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -1,5 +1,63 @@
+ /* SPDX-License-Identifier: GPL-2.0 */
+ 
++#define AT803X_SPECIFIC_FUNCTION_CONTROL	0x10
++#define AT803X_SFC_ASSERT_CRS			BIT(11)
++#define AT803X_SFC_FORCE_LINK			BIT(10)
++#define AT803X_SFC_MDI_CROSSOVER_MODE_M		GENMASK(6, 5)
++#define AT803X_SFC_AUTOMATIC_CROSSOVER		0x3
++#define AT803X_SFC_MANUAL_MDIX			0x1
++#define AT803X_SFC_MANUAL_MDI			0x0
++#define AT803X_SFC_SQE_TEST			BIT(2)
++#define AT803X_SFC_POLARITY_REVERSAL		BIT(1)
++#define AT803X_SFC_DISABLE_JABBER		BIT(0)
++
++#define AT803X_SPECIFIC_STATUS			0x11
++#define AT803X_SS_SPEED_MASK			GENMASK(15, 14)
++#define AT803X_SS_SPEED_1000			2
++#define AT803X_SS_SPEED_100			1
++#define AT803X_SS_SPEED_10			0
++#define AT803X_SS_DUPLEX			BIT(13)
++#define AT803X_SS_SPEED_DUPLEX_RESOLVED		BIT(11)
++#define AT803X_SS_MDIX				BIT(6)
++
++#define QCA808X_SS_SPEED_MASK			GENMASK(9, 7)
++#define QCA808X_SS_SPEED_2500			4
++
++#define AT803X_INTR_ENABLE			0x12
++#define AT803X_INTR_ENABLE_AUTONEG_ERR		BIT(15)
++#define AT803X_INTR_ENABLE_SPEED_CHANGED	BIT(14)
++#define AT803X_INTR_ENABLE_DUPLEX_CHANGED	BIT(13)
++#define AT803X_INTR_ENABLE_PAGE_RECEIVED	BIT(12)
++#define AT803X_INTR_ENABLE_LINK_FAIL		BIT(11)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS		BIT(10)
++#define AT803X_INTR_ENABLE_LINK_FAIL_BX		BIT(8)
++#define AT803X_INTR_ENABLE_LINK_SUCCESS_BX	BIT(7)
++#define AT803X_INTR_ENABLE_WIRESPEED_DOWNGRADE	BIT(5)
++#define AT803X_INTR_ENABLE_POLARITY_CHANGED	BIT(1)
++#define AT803X_INTR_ENABLE_WOL			BIT(0)
++
++#define AT803X_INTR_STATUS			0x13
++
++#define AT803X_SMART_SPEED			0x14
++#define AT803X_SMART_SPEED_ENABLE		BIT(5)
++#define AT803X_SMART_SPEED_RETRY_LIMIT_MASK	GENMASK(4, 2)
++#define AT803X_SMART_SPEED_BYPASS_TIMER		BIT(1)
++
++#define AT803X_CDT				0x16
++#define AT803X_CDT_MDI_PAIR_MASK		GENMASK(9, 8)
++#define AT803X_CDT_ENABLE_TEST			BIT(0)
++#define AT803X_CDT_STATUS			0x1c
++#define AT803X_CDT_STATUS_STAT_NORMAL		0
++#define AT803X_CDT_STATUS_STAT_SHORT		1
++#define AT803X_CDT_STATUS_STAT_OPEN		2
++#define AT803X_CDT_STATUS_STAT_FAIL		3
++#define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
++#define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
++
++#define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
++#define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
++#define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
++
+ #define AT803X_DEBUG_ADDR			0x1D
+ #define AT803X_DEBUG_DATA			0x1E
+ 
+@@ -16,6 +74,10 @@
+ #define   AT803X_DEBUG_HIB_CTRL_EN_ANY_CHANGE	BIT(13)
+ #define   AT803X_DEBUG_HIB_CTRL_PS_HIB_EN	BIT(15)
+ 
++#define AT803X_DEFAULT_DOWNSHIFT		5
++#define AT803X_MIN_DOWNSHIFT			2
++#define AT803X_MAX_DOWNSHIFT			9
++
+ enum stat_access_type {
+ 	PHY,
+ 	MMD
+@@ -28,7 +90,31 @@ struct at803x_hw_stat {
+ 	enum stat_access_type access_type;
+ };
+ 
++struct at803x_ss_mask {
++	u16 speed_mask;
++	u8 speed_shift;
++};
++
+ int at803x_debug_reg_read(struct phy_device *phydev, u16 reg);
+ int at803x_debug_reg_mask(struct phy_device *phydev, u16 reg,
+ 			  u16 clear, u16 set);
+ int at803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 data);
++int at803x_set_wol(struct phy_device *phydev,
++		   struct ethtool_wolinfo *wol);
++void at803x_get_wol(struct phy_device *phydev,
++		    struct ethtool_wolinfo *wol);
++int at803x_ack_interrupt(struct phy_device *phydev);
++int at803x_config_intr(struct phy_device *phydev);
++irqreturn_t at803x_handle_interrupt(struct phy_device *phydev);
++int at803x_read_specific_status(struct phy_device *phydev,
++				struct at803x_ss_mask ss_mask);
++int at803x_config_mdix(struct phy_device *phydev, u8 ctrl);
++int at803x_prepare_config_aneg(struct phy_device *phydev);
++int at803x_get_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, void *data);
++int at803x_set_tunable(struct phy_device *phydev,
++		       struct ethtool_tunable *tuna, const void *data);
++int at803x_cdt_fault_length(int dt);
++int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start);
++int at803x_cdt_wait_for_completion(struct phy_device *phydev,
++				   u32 cdt_en);
diff --git a/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch b/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch
new file mode 100644
index 00000000000..597dcea4c06
--- /dev/null
+++ b/target/linux/generic/backport-6.1/713-v6.9-05-net-phy-qcom-detach-qca808x-PHY-driver-from-at803x.patch
@@ -0,0 +1,1936 @@
+From c89414adf2ec7cd9e7080c419aa5847f1db1009c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Mon, 29 Jan 2024 15:15:23 +0100
+Subject: [PATCH 5/5] net: phy: qcom: detach qca808x PHY driver from at803x
+
+Almost all the QCA8081 PHY driver OPs are specific and only some of them
+use the generic at803x.
+
+To make the at803x code slimmer, move all the specific qca808x regs and
+functions to a dedicated PHY driver.
+
+Probe function and priv struct is reworked to allocate and use only the
+qca808x specific data. Unused data from at803x PHY driver are dropped
+from at803x priv struct.
+
+Also a new Kconfig is introduced QCA808X_PHY, to compile the newly
+introduced PHY driver for QCA8081 PHY.
+
+As the Kconfig name starts with Qualcomm the same order is kept.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240129141600.2592-6-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/qcom/Kconfig   |   6 +
+ drivers/net/phy/qcom/Makefile  |   1 +
+ drivers/net/phy/qcom/at803x.c  | 897 +------------------------------
+ drivers/net/phy/qcom/qca808x.c | 934 +++++++++++++++++++++++++++++++++
+ 4 files changed, 942 insertions(+), 896 deletions(-)
+ create mode 100644 drivers/net/phy/qcom/qca808x.c
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -14,3 +14,9 @@ config QCA83XX_PHY
+ 	select QCOM_NET_PHYLIB
+ 	help
+ 	  Currently supports the internal QCA8337(Internal qca8k PHY) model
++
++config QCA808X_PHY
++	tristate "Qualcomm QCA808x PHYs"
++	select QCOM_NET_PHYLIB
++	help
++	  Currently supports the QCA8081 model
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -2,3 +2,4 @@
+ obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-phy-lib.o
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
++obj-$(CONFIG_QCA808X_PHY)	+= qca808x.o
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -96,8 +96,6 @@
+ #define ATH8035_PHY_ID				0x004dd072
+ #define AT8030_PHY_ID_MASK			0xffffffef
+ 
+-#define QCA8081_PHY_ID				0x004dd101
+-
+ #define QCA9561_PHY_ID				0x004dd042
+ 
+ #define AT803X_PAGE_FIBER			0
+@@ -110,201 +108,7 @@
+ /* disable hibernation mode */
+ #define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
+ 
+-/* ADC threshold */
+-#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
+-#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
+-#define QCA808X_ADC_THRESHOLD_80MV		0
+-#define QCA808X_ADC_THRESHOLD_100MV		0xf0
+-#define QCA808X_ADC_THRESHOLD_200MV		0x0f
+-#define QCA808X_ADC_THRESHOLD_300MV		0xff
+-
+-/* CLD control */
+-#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
+-#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
+-#define QCA808X_8023AZ_AFE_EN			0x90
+-
+-/* AZ control */
+-#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
+-#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
+-#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
+-#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
+-#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
+-
+-#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
+-#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
+-
+-#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
+-#define QCA808X_TOP_OPTION1_DATA		0x0
+-
+-#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
+-#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
+-#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
+-#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
+-#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
+-#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
+-#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
+-#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
+-#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
+-#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
+-#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
+-#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
+-
+-/* master/slave seed config */
+-#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
+-#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
+-#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
+-#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
+-
+-/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
+- * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
+- */
+-#define QCA808X_DBG_AN_TEST			0xb
+-#define QCA808X_HIBERNATION_EN			BIT(15)
+-
+-#define QCA808X_CDT_ENABLE_TEST			BIT(15)
+-#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
+-#define QCA808X_CDT_STATUS			BIT(11)
+-#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
+-
+-#define QCA808X_MMD3_CDT_STATUS			0x8064
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
+-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
+-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
+-
+-#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
+-#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
+-#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
+-#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
+-
+-#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
+-#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
+-#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
+-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
+-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
+-
+-#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
+-#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
+-
+-/* NORMAL are MDI with type set to 0 */
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-
+-/* Added for reference of existence but should be handled by wait_for_completion already */
+-#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+-
+-#define QCA808X_MMD7_LED_GLOBAL			0x8073
+-#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+-#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+-/* Values are the same for both BLINK_1 and BLINK_2 */
+-#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
+-#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
+-#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
+-#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
+-#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
+-#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
+-#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
+-#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
+-#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
+-#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
+-#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
+-#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
+-#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
+-#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
+-#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
+-#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
+-#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
+-#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
+-
+-#define QCA808X_MMD7_LED2_CTRL			0x8074
+-#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
+-#define QCA808X_MMD7_LED1_CTRL			0x8076
+-#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
+-#define QCA808X_MMD7_LED0_CTRL			0x8078
+-#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
+-
+-/* LED hw control pattern is the same for every LED */
+-#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
+-#define QCA808X_LED_SPEED2500_ON		BIT(15)
+-#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
+-/* Follow blink trigger even if duplex or speed condition doesn't match */
+-#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
+-#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
+-#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
+-#define QCA808X_LED_TX_BLINK			BIT(10)
+-#define QCA808X_LED_RX_BLINK			BIT(9)
+-#define QCA808X_LED_TX_ON_10MS			BIT(8)
+-#define QCA808X_LED_RX_ON_10MS			BIT(7)
+-#define QCA808X_LED_SPEED1000_ON		BIT(6)
+-#define QCA808X_LED_SPEED100_ON			BIT(5)
+-#define QCA808X_LED_SPEED10_ON			BIT(4)
+-#define QCA808X_LED_COLLISION_BLINK		BIT(3)
+-#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
+-#define QCA808X_LED_SPEED100_BLINK		BIT(1)
+-#define QCA808X_LED_SPEED10_BLINK		BIT(0)
+-
+-#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
+-#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
+-
+-/* LED force ctrl is the same for every LED
+- * No documentation exist for this, not even internal one
+- * with NDA as QCOM gives only info about configuring
+- * hw control pattern rules and doesn't indicate any way
+- * to force the LED to specific mode.
+- * These define comes from reverse and testing and maybe
+- * lack of some info or some info are not entirely correct.
+- * For the basic LED control and hw control these finding
+- * are enough to support LED control in all the required APIs.
+- *
+- * On doing some comparison with implementation with qca807x,
+- * it was found that it's 1:1 equal to it and confirms all the
+- * reverse done. It was also found further specification with the
+- * force mode and the blink modes.
+- */
+-#define QCA808X_LED_FORCE_EN			BIT(15)
+-#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
+-#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
+-#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
+-#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
+-#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
+-
+-#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
+-/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
+- * LED to active high. It's not clear what BIT 3 and BIT 4 does.
+- */
+-#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
+-
+-/* QCA808X 1G chip type */
+-#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
+-#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
+-
+-#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
+-#define QCA8081_PHY_FIFO_RSTN			BIT(11)
+-
+-MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
++MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
+ MODULE_AUTHOR("Matus Ujhelyi");
+ MODULE_LICENSE("GPL");
+ 
+@@ -318,7 +122,6 @@ struct at803x_priv {
+ 	bool is_1000basex;
+ 	struct regulator_dev *vddio_rdev;
+ 	struct regulator_dev *vddh_rdev;
+-	int led_polarity_mode;
+ };
+ 
+ struct at803x_context {
+@@ -519,9 +322,6 @@ static int at803x_probe(struct phy_devic
+ 	if (!priv)
+ 		return -ENOMEM;
+ 
+-	/* Init LED polarity mode to -1 */
+-	priv->led_polarity_mode = -1;
+-
+ 	phydev->priv = priv;
+ 
+ 	ret = at803x_parse_dt(phydev);
+@@ -1216,672 +1016,6 @@ static int at8035_probe(struct phy_devic
+ 	return at8035_parse_dt(phydev);
+ }
+ 
+-static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Enable fast retrain */
+-	ret = genphy_c45_fast_retrain(phydev, true);
+-	if (ret)
+-		return ret;
+-
+-	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
+-		      QCA808X_TOP_OPTION1_DATA);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
+-		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
+-		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
+-		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
+-		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
+-		      QCA808X_MMD3_DEBUG_1_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
+-		      QCA808X_MMD3_DEBUG_4_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
+-		      QCA808X_MMD3_DEBUG_5_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
+-		      QCA808X_MMD3_DEBUG_3_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
+-		      QCA808X_MMD3_DEBUG_6_VALUE);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
+-		      QCA808X_MMD3_DEBUG_2_VALUE);
+-
+-	return 0;
+-}
+-
+-static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
+-{
+-	u16 seed_value;
+-
+-	if (!enable)
+-		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
+-
+-	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
+-			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
+-			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
+-			QCA808X_MASTER_SLAVE_SEED_ENABLE);
+-}
+-
+-static bool qca808x_is_prefer_master(struct phy_device *phydev)
+-{
+-	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
+-		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
+-}
+-
+-static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
+-{
+-	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-}
+-
+-static int qca808x_config_init(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* Active adc&vga on 802.3az for the link 1000M and 100M */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
+-			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
+-	if (ret)
+-		return ret;
+-
+-	/* Adjust the threshold on 802.3az for the link 1000M */
+-	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
+-			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
+-			    QCA808X_MMD3_AZ_TRAINING_VAL);
+-	if (ret)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-		/* Config the fast retrain for the link 2500M */
+-		ret = qca808x_phy_fast_retrain_config(phydev);
+-		if (ret)
+-			return ret;
+-
+-		ret = genphy_read_master_slave(phydev);
+-		if (ret < 0)
+-			return ret;
+-
+-		if (!qca808x_is_prefer_master(phydev)) {
+-			/* Enable seed and configure lower ramdom seed to make phy
+-			 * linked as slave mode.
+-			 */
+-			ret = qca808x_phy_ms_seed_enable(phydev, true);
+-			if (ret)
+-				return ret;
+-		}
+-	}
+-
+-	/* Configure adc threshold as 100mv for the link 10M */
+-	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
+-				     QCA808X_ADC_THRESHOLD_MASK,
+-				     QCA808X_ADC_THRESHOLD_100MV);
+-}
+-
+-static int qca808x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int ret;
+-
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
+-	if (ret < 0)
+-		return ret;
+-
+-	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
+-			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
+-
+-	ret = genphy_read_status(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* qca8081 takes the different bits for speed value from at803x */
+-	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
+-	ret = at803x_read_specific_status(phydev, ss_mask);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (phydev->link) {
+-		if (phydev->speed == SPEED_2500)
+-			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
+-		else
+-			phydev->interface = PHY_INTERFACE_MODE_SGMII;
+-	} else {
+-		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
+-		 * except for master/slave configuration fault detected or the master mode
+-		 * preferred.
+-		 *
+-		 * the reason for not putting this code into the function link_change_notify is
+-		 * the corner case where the link partner is also the qca8081 PHY and the seed
+-		 * value is configured as the same value, the link can't be up and no link change
+-		 * occurs.
+-		 */
+-		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
+-			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
+-			    qca808x_is_prefer_master(phydev)) {
+-				qca808x_phy_ms_seed_enable(phydev, false);
+-			} else {
+-				qca808x_phy_ms_seed_enable(phydev, true);
+-			}
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_soft_reset(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_soft_reset(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
+-		ret = qca808x_phy_ms_seed_enable(phydev, true);
+-
+-	return ret;
+-}
+-
+-static bool qca808x_cdt_fault_length_valid(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return true;
+-	default:
+-		return false;
+-	}
+-}
+-
+-static int qca808x_cable_test_result_trans(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
+-				    int result)
+-{
+-	int val;
+-	u32 cdt_length_reg = 0;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
+-	else
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
+-
+-	return at803x_cdt_fault_length(val);
+-}
+-
+-static int qca808x_cable_test_start(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	/* perform CDT with the following configs:
+-	 * 1. disable hibernation.
+-	 * 2. force PHY working in MDI mode.
+-	 * 3. for PHY working in 1000BaseT.
+-	 * 4. configure the threshold.
+-	 */
+-
+-	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
+-	phydev->duplex = DUPLEX_FULL;
+-	phydev->speed = SPEED_1000;
+-	ret = genphy_c45_pma_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	ret = genphy_setup_forced(phydev);
+-	if (ret < 0)
+-		return ret;
+-
+-	/* configure the thresholds for open, short, pair ok test */
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
+-	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
+-					      u16 status)
+-{
+-	int length, result;
+-	u16 pair_code;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	result = qca808x_cable_test_result_trans(pair_code);
+-	ethnl_cable_test_result(phydev, pair, result);
+-
+-	if (qca808x_cdt_fault_length_valid(pair_code)) {
+-		length = qca808x_cdt_fault_length(phydev, pair, result);
+-		ethnl_cable_test_fault_length(phydev, pair, length);
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
+-{
+-	int ret, val;
+-
+-	*finished = false;
+-
+-	val = QCA808X_CDT_ENABLE_TEST |
+-	      QCA808X_CDT_LENGTH_UNIT;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
+-	if (ret)
+-		return ret;
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+-
+-static int qca808x_get_features(struct phy_device *phydev)
+-{
+-	int ret;
+-
+-	ret = genphy_c45_pma_read_abilities(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The autoneg ability is not existed in bit3 of MMD7.1,
+-	 * but it is supported by qca808x PHY, so we add it here
+-	 * manually.
+-	 */
+-	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
+-
+-	/* As for the qca8081 1G version chip, the 2500baseT ability is also
+-	 * existed in the bit0 of MMD1.21, we need to remove it manually if
+-	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
+-	 */
+-	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
+-	if (ret < 0)
+-		return ret;
+-
+-	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
+-		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
+-
+-	return 0;
+-}
+-
+-static int qca808x_config_aneg(struct phy_device *phydev)
+-{
+-	int phy_ctrl = 0;
+-	int ret;
+-
+-	ret = at803x_prepare_config_aneg(phydev);
+-	if (ret)
+-		return ret;
+-
+-	/* The reg MII_BMCR also needs to be configured for force mode, the
+-	 * genphy_config_aneg is also needed.
+-	 */
+-	if (phydev->autoneg == AUTONEG_DISABLE)
+-		genphy_c45_pma_setup_forced(phydev);
+-
+-	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
+-		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
+-
+-	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
+-				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
+-	if (ret < 0)
+-		return ret;
+-
+-	return __genphy_config_aneg(phydev, ret);
+-}
+-
+-static void qca808x_link_change_notify(struct phy_device *phydev)
+-{
+-	/* Assert interface sgmii fifo on link down, deassert it on link up,
+-	 * the interface device address is always phy address added by 1.
+-	 */
+-	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
+-				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
+-				   QCA8081_PHY_FIFO_RSTN,
+-				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
+-}
+-
+-static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
+-				    u16 *offload_trigger)
+-{
+-	/* Parsing specific to netdev trigger */
+-	if (test_bit(TRIGGER_NETDEV_TX, &rules))
+-		*offload_trigger |= QCA808X_LED_TX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_RX, &rules))
+-		*offload_trigger |= QCA808X_LED_RX_BLINK;
+-	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED10_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED100_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
+-	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
+-		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
+-	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
+-	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
+-		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
+-
+-	if (rules && !*offload_trigger)
+-		return -EOPNOTSUPP;
+-
+-	/* Enable BLINK_CHECK_BYPASS by default to make the LED
+-	 * blink even with duplex or speed mode not enabled.
+-	 */
+-	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+-				       unsigned long rules)
+-{
+-	u16 offload_trigger = 0;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-}
+-
+-static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
+-				      unsigned long rules)
+-{
+-	u16 reg, offload_trigger = 0;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_led_hw_control_enable(phydev, index);
+-	if (ret)
+-		return ret;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_PATTERN_MASK,
+-			      offload_trigger);
+-}
+-
+-static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return false;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-
+-	return !(val & QCA808X_LED_FORCE_EN);
+-}
+-
+-static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
+-				      unsigned long *rules)
+-{
+-	u16 reg;
+-	int val;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	/* Check if we have hw control enabled */
+-	if (qca808x_led_hw_control_status(phydev, index))
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-	if (val & QCA808X_LED_TX_BLINK)
+-		set_bit(TRIGGER_NETDEV_TX, rules);
+-	if (val & QCA808X_LED_RX_BLINK)
+-		set_bit(TRIGGER_NETDEV_RX, rules);
+-	if (val & QCA808X_LED_SPEED10_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_10, rules);
+-	if (val & QCA808X_LED_SPEED100_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_100, rules);
+-	if (val & QCA808X_LED_SPEED1000_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
+-	if (val & QCA808X_LED_SPEED2500_ON)
+-		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
+-	if (val & QCA808X_LED_HALF_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
+-	if (val & QCA808X_LED_FULL_DUPLEX_ON)
+-		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
+-{
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_PATTERN_MASK);
+-}
+-
+-static int qca808x_led_brightness_set(struct phy_device *phydev,
+-				      u8 index, enum led_brightness value)
+-{
+-	u16 reg;
+-	int ret;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	if (!value) {
+-		ret = qca808x_led_hw_control_reset(phydev, index);
+-		if (ret)
+-			return ret;
+-	}
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF);
+-}
+-
+-static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
+-				 unsigned long *delay_on,
+-				 unsigned long *delay_off)
+-{
+-	int ret;
+-	u16 reg;
+-
+-	if (index > 2)
+-		return -EINVAL;
+-
+-	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	/* Set blink to 50% off, 50% on at 4Hz by default */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
+-			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
+-			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
+-	if (ret)
+-		return ret;
+-
+-	/* We use BLINK_1 for normal blinking */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
+-	if (ret)
+-		return ret;
+-
+-	/* We set blink to 4Hz, aka 250ms */
+-	*delay_on = 250 / 2;
+-	*delay_off = 250 / 2;
+-
+-	return 0;
+-}
+-
+-static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
+-				    unsigned long modes)
+-{
+-	struct at803x_priv *priv = phydev->priv;
+-	bool active_low = false;
+-	u32 mode;
+-
+-	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
+-		switch (mode) {
+-		case PHY_LED_ACTIVE_LOW:
+-			active_low = true;
+-			break;
+-		default:
+-			return -EINVAL;
+-		}
+-	}
+-
+-	/* PHY polarity is global and can't be set per LED.
+-	 * To detect this, check if last requested polarity mode
+-	 * match the new one.
+-	 */
+-	if (priv->led_polarity_mode >= 0 &&
+-	    priv->led_polarity_mode != active_low) {
+-		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
+-		return -EINVAL;
+-	}
+-
+-	/* Save the last PHY polarity mode */
+-	priv->led_polarity_mode = active_low;
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN,
+-			      QCA808X_MMD7_LED_POLARITY_CTRL,
+-			      QCA808X_LED_ACTIVE_HIGH,
+-			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
+-}
+-
+ static struct phy_driver at803x_driver[] = {
+ {
+ 	/* Qualcomm Atheros AR8035 */
+@@ -1989,34 +1123,6 @@ static struct phy_driver at803x_driver[]
+ 	.read_status		= at803x_read_status,
+ 	.soft_reset		= genphy_soft_reset,
+ 	.config_aneg		= at803x_config_aneg,
+-}, {
+-	/* Qualcomm QCA8081 */
+-	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
+-	.name			= "Qualcomm QCA8081",
+-	.flags			= PHY_POLL_CABLE_TEST,
+-	.probe			= at803x_probe,
+-	.config_intr		= at803x_config_intr,
+-	.handle_interrupt	= at803x_handle_interrupt,
+-	.get_tunable		= at803x_get_tunable,
+-	.set_tunable		= at803x_set_tunable,
+-	.set_wol		= at803x_set_wol,
+-	.get_wol		= at803x_get_wol,
+-	.get_features		= qca808x_get_features,
+-	.config_aneg		= qca808x_config_aneg,
+-	.suspend		= genphy_suspend,
+-	.resume			= genphy_resume,
+-	.read_status		= qca808x_read_status,
+-	.config_init		= qca808x_config_init,
+-	.soft_reset		= qca808x_soft_reset,
+-	.cable_test_start	= qca808x_cable_test_start,
+-	.cable_test_get_status	= qca808x_cable_test_get_status,
+-	.link_change_notify	= qca808x_link_change_notify,
+-	.led_brightness_set	= qca808x_led_brightness_set,
+-	.led_blink_set		= qca808x_led_blink_set,
+-	.led_hw_is_supported	= qca808x_led_hw_is_supported,
+-	.led_hw_control_set	= qca808x_led_hw_control_set,
+-	.led_hw_control_get	= qca808x_led_hw_control_get,
+-	.led_polarity_set	= qca808x_led_polarity_set,
+ }, };
+ 
+ module_phy_driver(at803x_driver);
+@@ -2028,7 +1134,6 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
+ 	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
+-	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
+ 	{ }
+ };
+ 
+--- /dev/null
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -0,0 +1,934 @@
++// SPDX-License-Identifier: GPL-2.0+
++
++#include <linux/phy.h>
++#include <linux/module.h>
++#include <linux/ethtool_netlink.h>
++
++#include "qcom.h"
++
++/* ADC threshold */
++#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
++#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
++#define QCA808X_ADC_THRESHOLD_80MV		0
++#define QCA808X_ADC_THRESHOLD_100MV		0xf0
++#define QCA808X_ADC_THRESHOLD_200MV		0x0f
++#define QCA808X_ADC_THRESHOLD_300MV		0xff
++
++/* CLD control */
++#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
++#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
++#define QCA808X_8023AZ_AFE_EN			0x90
++
++/* AZ control */
++#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
++#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
++#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
++#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
++#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
++
++#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
++#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
++
++#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
++#define QCA808X_TOP_OPTION1_DATA		0x0
++
++#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
++#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
++#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
++#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
++#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
++#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
++#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
++#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
++#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
++#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
++#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
++#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
++
++/* master/slave seed config */
++#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
++#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
++#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
++#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
++
++/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
++ * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
++ */
++#define QCA808X_DBG_AN_TEST			0xb
++#define QCA808X_HIBERNATION_EN			BIT(15)
++
++#define QCA808X_CDT_ENABLE_TEST			BIT(15)
++#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
++#define QCA808X_CDT_STATUS			BIT(11)
++#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
++
++#define QCA808X_MMD3_CDT_STATUS			0x8064
++#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
++#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
++#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
++#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
++
++#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
++#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
++#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
++#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
++
++#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
++#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
++#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
++
++#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
++#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
++
++/* NORMAL are MDI with type set to 0 */
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++
++/* Added for reference of existence but should be handled by wait_for_completion already */
++#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
++
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++#define QCA808X_MMD7_LED2_CTRL			0x8074
++#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
++#define QCA808X_MMD7_LED1_CTRL			0x8076
++#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
++#define QCA808X_MMD7_LED0_CTRL			0x8078
++#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
++#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
++#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
++/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
++ * LED to active high. It's not clear what BIT 3 and BIT 4 does.
++ */
++#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
++
++/* QCA808X 1G chip type */
++#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
++#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
++
++#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
++#define QCA8081_PHY_FIFO_RSTN			BIT(11)
++
++#define QCA8081_PHY_ID				0x004dd101
++
++MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
++MODULE_AUTHOR("Matus Ujhelyi");
++MODULE_LICENSE("GPL");
++
++struct qca808x_priv {
++	int led_polarity_mode;
++};
++
++static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Enable fast retrain */
++	ret = genphy_c45_fast_retrain(phydev, true);
++	if (ret)
++		return ret;
++
++	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
++		      QCA808X_TOP_OPTION1_DATA);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
++		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
++		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
++		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
++		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
++		      QCA808X_MMD3_DEBUG_1_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
++		      QCA808X_MMD3_DEBUG_4_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
++		      QCA808X_MMD3_DEBUG_5_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
++		      QCA808X_MMD3_DEBUG_3_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
++		      QCA808X_MMD3_DEBUG_6_VALUE);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
++		      QCA808X_MMD3_DEBUG_2_VALUE);
++
++	return 0;
++}
++
++static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
++{
++	u16 seed_value;
++
++	if (!enable)
++		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
++
++	seed_value = prandom_u32_max(QCA808X_MASTER_SLAVE_SEED_RANGE);
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
++			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
++			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
++			QCA808X_MASTER_SLAVE_SEED_ENABLE);
++}
++
++static bool qca808x_is_prefer_master(struct phy_device *phydev)
++{
++	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
++		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
++}
++
++static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
++{
++	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++}
++
++static int qca808x_probe(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct qca808x_priv *priv;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	/* Init LED polarity mode to -1 */
++	priv->led_polarity_mode = -1;
++
++	phydev->priv = priv;
++
++	return 0;
++}
++
++static int qca808x_config_init(struct phy_device *phydev)
++{
++	int ret;
++
++	/* Active adc&vga on 802.3az for the link 1000M and 100M */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
++			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
++	if (ret)
++		return ret;
++
++	/* Adjust the threshold on 802.3az for the link 1000M */
++	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
++			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
++			    QCA808X_MMD3_AZ_TRAINING_VAL);
++	if (ret)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++		/* Config the fast retrain for the link 2500M */
++		ret = qca808x_phy_fast_retrain_config(phydev);
++		if (ret)
++			return ret;
++
++		ret = genphy_read_master_slave(phydev);
++		if (ret < 0)
++			return ret;
++
++		if (!qca808x_is_prefer_master(phydev)) {
++			/* Enable seed and configure lower ramdom seed to make phy
++			 * linked as slave mode.
++			 */
++			ret = qca808x_phy_ms_seed_enable(phydev, true);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Configure adc threshold as 100mv for the link 10M */
++	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
++				     QCA808X_ADC_THRESHOLD_MASK,
++				     QCA808X_ADC_THRESHOLD_100MV);
++}
++
++static int qca808x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int ret;
++
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
++	if (ret < 0)
++		return ret;
++
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
++			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
++
++	ret = genphy_read_status(phydev);
++	if (ret)
++		return ret;
++
++	/* qca8081 takes the different bits for speed value from at803x */
++	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
++	ret = at803x_read_specific_status(phydev, ss_mask);
++	if (ret < 0)
++		return ret;
++
++	if (phydev->link) {
++		if (phydev->speed == SPEED_2500)
++			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
++		else
++			phydev->interface = PHY_INTERFACE_MODE_SGMII;
++	} else {
++		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
++		 * except for master/slave configuration fault detected or the master mode
++		 * preferred.
++		 *
++		 * the reason for not putting this code into the function link_change_notify is
++		 * the corner case where the link partner is also the qca8081 PHY and the seed
++		 * value is configured as the same value, the link can't be up and no link change
++		 * occurs.
++		 */
++		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
++			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
++			    qca808x_is_prefer_master(phydev)) {
++				qca808x_phy_ms_seed_enable(phydev, false);
++			} else {
++				qca808x_phy_ms_seed_enable(phydev, true);
++			}
++		}
++	}
++
++	return 0;
++}
++
++static int qca808x_soft_reset(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_soft_reset(phydev);
++	if (ret < 0)
++		return ret;
++
++	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
++		ret = qca808x_phy_ms_seed_enable(phydev, true);
++
++	return ret;
++}
++
++static bool qca808x_cdt_fault_length_valid(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static int qca808x_cable_test_result_trans(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
++	case QCA808X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
++				    int result)
++{
++	int val;
++	u32 cdt_length_reg = 0;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
++	if (val < 0)
++		return val;
++
++	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
++	else
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
++
++	return at803x_cdt_fault_length(val);
++}
++
++static int qca808x_cable_test_start(struct phy_device *phydev)
++{
++	int ret;
++
++	/* perform CDT with the following configs:
++	 * 1. disable hibernation.
++	 * 2. force PHY working in MDI mode.
++	 * 3. for PHY working in 1000BaseT.
++	 * 4. configure the threshold.
++	 */
++
++	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
++	if (ret < 0)
++		return ret;
++
++	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
++	if (ret < 0)
++		return ret;
++
++	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
++	phydev->duplex = DUPLEX_FULL;
++	phydev->speed = SPEED_1000;
++	ret = genphy_c45_pma_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_setup_forced(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* configure the thresholds for open, short, pair ok test */
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
++	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
++					      u16 status)
++{
++	int length, result;
++	u16 pair_code;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	result = qca808x_cable_test_result_trans(pair_code);
++	ethnl_cable_test_result(phydev, pair, result);
++
++	if (qca808x_cdt_fault_length_valid(pair_code)) {
++		length = qca808x_cdt_fault_length(phydev, pair, result);
++		ethnl_cable_test_fault_length(phydev, pair, length);
++	}
++
++	return 0;
++}
++
++static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
++{
++	int ret, val;
++
++	*finished = false;
++
++	val = QCA808X_CDT_ENABLE_TEST |
++	      QCA808X_CDT_LENGTH_UNIT;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
++	if (ret)
++		return ret;
++
++	*finished = true;
++
++	return 0;
++}
++
++static int qca808x_get_features(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = genphy_c45_pma_read_abilities(phydev);
++	if (ret)
++		return ret;
++
++	/* The autoneg ability is not existed in bit3 of MMD7.1,
++	 * but it is supported by qca808x PHY, so we add it here
++	 * manually.
++	 */
++	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
++
++	/* As for the qca8081 1G version chip, the 2500baseT ability is also
++	 * existed in the bit0 of MMD1.21, we need to remove it manually if
++	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
++	 */
++	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
++	if (ret < 0)
++		return ret;
++
++	if (QCA808X_PHY_CHIP_TYPE_1G & ret)
++		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
++
++	return 0;
++}
++
++static int qca808x_config_aneg(struct phy_device *phydev)
++{
++	int phy_ctrl = 0;
++	int ret;
++
++	ret = at803x_prepare_config_aneg(phydev);
++	if (ret)
++		return ret;
++
++	/* The reg MII_BMCR also needs to be configured for force mode, the
++	 * genphy_config_aneg is also needed.
++	 */
++	if (phydev->autoneg == AUTONEG_DISABLE)
++		genphy_c45_pma_setup_forced(phydev);
++
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
++		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
++
++	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
++	if (ret < 0)
++		return ret;
++
++	return __genphy_config_aneg(phydev, ret);
++}
++
++static void qca808x_link_change_notify(struct phy_device *phydev)
++{
++	/* Assert interface sgmii fifo on link down, deassert it on link up,
++	 * the interface device address is always phy address added by 1.
++	 */
++	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
++				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
++				   QCA8081_PHY_FIFO_RSTN,
++				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
++}
++
++static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	if (test_bit(TRIGGER_NETDEV_TX, &rules))
++		*offload_trigger |= QCA808X_LED_TX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_RX, &rules))
++		*offload_trigger |= QCA808X_LED_RX_BLINK;
++	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED10_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED100_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
++		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
++	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	/* Enable BLINK_CHECK_BYPASS by default to make the LED
++	 * blink even with duplex or speed mode not enabled.
++	 */
++	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 2)
++		return -EINVAL;
++
++	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, offload_trigger = 0;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca808x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_PATTERN_MASK,
++			      offload_trigger);
++}
++
++static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return false;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++
++static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 2)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca808x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	if (val & QCA808X_LED_TX_BLINK)
++		set_bit(TRIGGER_NETDEV_TX, rules);
++	if (val & QCA808X_LED_RX_BLINK)
++		set_bit(TRIGGER_NETDEV_RX, rules);
++	if (val & QCA808X_LED_SPEED10_ON)
++		set_bit(TRIGGER_NETDEV_LINK_10, rules);
++	if (val & QCA808X_LED_SPEED100_ON)
++		set_bit(TRIGGER_NETDEV_LINK_100, rules);
++	if (val & QCA808X_LED_SPEED1000_ON)
++		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++	if (val & QCA808X_LED_SPEED2500_ON)
++		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
++	if (val & QCA808X_LED_HALF_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++	if (val & QCA808X_LED_FULL_DUPLEX_ON)
++		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++
++	return 0;
++}
++
++static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_CTRL(index);
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_PATTERN_MASK);
++}
++
++static int qca808x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 2)
++		return -EINVAL;
++
++	if (!value) {
++		ret = qca808x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF);
++}
++
++static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	int ret;
++	u16 reg;
++
++	if (index > 2)
++		return -EINVAL;
++
++	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++
++static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
++				    unsigned long modes)
++{
++	struct qca808x_priv *priv = phydev->priv;
++	bool active_low = false;
++	u32 mode;
++
++	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
++		switch (mode) {
++		case PHY_LED_ACTIVE_LOW:
++			active_low = true;
++			break;
++		default:
++			return -EINVAL;
++		}
++	}
++
++	/* PHY polarity is global and can't be set per LED.
++	 * To detect this, check if last requested polarity mode
++	 * match the new one.
++	 */
++	if (priv->led_polarity_mode >= 0 &&
++	    priv->led_polarity_mode != active_low) {
++		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
++		return -EINVAL;
++	}
++
++	/* Save the last PHY polarity mode */
++	priv->led_polarity_mode = active_low;
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN,
++			      QCA808X_MMD7_LED_POLARITY_CTRL,
++			      QCA808X_LED_ACTIVE_HIGH,
++			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
++}
++
++static struct phy_driver qca808x_driver[] = {
++{
++	/* Qualcomm QCA8081 */
++	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
++	.name			= "Qualcomm QCA8081",
++	.flags			= PHY_POLL_CABLE_TEST,
++	.probe			= qca808x_probe,
++	.config_intr		= at803x_config_intr,
++	.handle_interrupt	= at803x_handle_interrupt,
++	.get_tunable		= at803x_get_tunable,
++	.set_tunable		= at803x_set_tunable,
++	.set_wol		= at803x_set_wol,
++	.get_wol		= at803x_get_wol,
++	.get_features		= qca808x_get_features,
++	.config_aneg		= qca808x_config_aneg,
++	.suspend		= genphy_suspend,
++	.resume			= genphy_resume,
++	.read_status		= qca808x_read_status,
++	.config_init		= qca808x_config_init,
++	.soft_reset		= qca808x_soft_reset,
++	.cable_test_start	= qca808x_cable_test_start,
++	.cable_test_get_status	= qca808x_cable_test_get_status,
++	.link_change_notify	= qca808x_link_change_notify,
++	.led_brightness_set	= qca808x_led_brightness_set,
++	.led_blink_set		= qca808x_led_blink_set,
++	.led_hw_is_supported	= qca808x_led_hw_is_supported,
++	.led_hw_control_set	= qca808x_led_hw_control_set,
++	.led_hw_control_get	= qca808x_led_hw_control_get,
++	.led_polarity_set	= qca808x_led_polarity_set,
++}, };
++
++module_phy_driver(qca808x_driver);
++
++static struct mdio_device_id __maybe_unused qca808x_tbl[] = {
++	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
++	{ }
++};
++
++MODULE_DEVICE_TABLE(mdio, qca808x_tbl);
diff --git a/target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch b/target/linux/generic/backport-6.1/714-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
similarity index 100%
rename from target/linux/generic/backport-6.1/723-v6.3-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
rename to target/linux/generic/backport-6.1/714-net-pcs-add-driver-for-MediaTek-SGMII-PCS.patch
diff --git a/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch b/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch
new file mode 100644
index 00000000000..6decc3430b0
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-01-net-phy-make-addr-type-u8-in-phy_package_shared-stru.patch
@@ -0,0 +1,28 @@
+From ebb30ccbbdbd6fae5177b676da4f4ac92bb4f635 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:31 +0100
+Subject: [PATCH 1/4] net: phy: make addr type u8 in phy_package_shared struct
+
+Switch addr type in phy_package_shared struct to u8.
+
+The value is already checked to be non negative and to be less than
+PHY_MAX_ADDR, hence u8 is better suited than using int.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ include/linux/phy.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -330,7 +330,7 @@ struct mdio_bus_stats {
+  * phy_package_leave().
+  */
+ struct phy_package_shared {
+-	int addr;
++	u8 addr;
+ 	refcount_t refcnt;
+ 	unsigned long flags;
+ 	size_t priv_size;
diff --git a/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch b/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch
new file mode 100644
index 00000000000..0cf01df3d35
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-02-net-phy-extend-PHY-package-API-to-support-multiple-g.patch
@@ -0,0 +1,341 @@
+From 9eea577eb1155fe4a183bc5e7bf269b0b2e7a6ba Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:32 +0100
+Subject: [PATCH 2/4] net: phy: extend PHY package API to support multiple
+ global address
+
+Current API for PHY package are limited to single address to configure
+global settings for the PHY package.
+
+It was found that some PHY package (for example the qca807x, a PHY
+package that is shipped with a bundle of 5 PHY) requires multiple PHY
+address to configure global settings. An example scenario is a PHY that
+have a dedicated PHY for PSGMII/serdes calibrarion and have a specific
+PHY in the package where the global PHY mode is set and affects every
+other PHY in the package.
+
+Change the API in the following way:
+- Change phy_package_join() to take the base addr of the PHY package
+  instead of the global PHY addr.
+- Make __/phy_package_write/read() require an additional arg that
+  select what global PHY address to use by passing the offset from the
+  base addr passed on phy_package_join().
+
+Each user of this API is updated to follow this new implementation
+following a pattern where an enum is defined to declare the offset of the
+addr.
+
+We also drop the check if shared is defined as any user of the
+phy_package_read/write is expected to use phy_package_join first. Misuse
+of this will correctly trigger a kernel panic for NULL pointer
+exception.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/bcm54140.c       | 16 ++++++--
+ drivers/net/phy/mscc/mscc.h      |  5 +++
+ drivers/net/phy/mscc/mscc_main.c |  4 +-
+ drivers/net/phy/phy_device.c     | 35 +++++++++--------
+ include/linux/phy.h              | 64 +++++++++++++++++++++-----------
+ 5 files changed, 80 insertions(+), 44 deletions(-)
+
+--- a/drivers/net/phy/bcm54140.c
++++ b/drivers/net/phy/bcm54140.c
+@@ -128,6 +128,10 @@
+ #define BCM54140_DEFAULT_DOWNSHIFT 5
+ #define BCM54140_MAX_DOWNSHIFT 9
+ 
++enum bcm54140_global_phy {
++	BCM54140_BASE_ADDR = 0,
++};
++
+ struct bcm54140_priv {
+ 	int port;
+ 	int base_addr;
+@@ -429,11 +433,13 @@ static int bcm54140_base_read_rdb(struct
+ 	int ret;
+ 
+ 	phy_lock_mdio_bus(phydev);
+-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
++	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
++				  MII_BCM54XX_RDB_ADDR, rdb);
+ 	if (ret < 0)
+ 		goto out;
+ 
+-	ret = __phy_package_read(phydev, MII_BCM54XX_RDB_DATA);
++	ret = __phy_package_read(phydev, BCM54140_BASE_ADDR,
++				 MII_BCM54XX_RDB_DATA);
+ 
+ out:
+ 	phy_unlock_mdio_bus(phydev);
+@@ -446,11 +452,13 @@ static int bcm54140_base_write_rdb(struc
+ 	int ret;
+ 
+ 	phy_lock_mdio_bus(phydev);
+-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_ADDR, rdb);
++	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
++				  MII_BCM54XX_RDB_ADDR, rdb);
+ 	if (ret < 0)
+ 		goto out;
+ 
+-	ret = __phy_package_write(phydev, MII_BCM54XX_RDB_DATA, val);
++	ret = __phy_package_write(phydev, BCM54140_BASE_ADDR,
++				  MII_BCM54XX_RDB_DATA, val);
+ 
+ out:
+ 	phy_unlock_mdio_bus(phydev);
+--- a/drivers/net/phy/mscc/mscc.h
++++ b/drivers/net/phy/mscc/mscc.h
+@@ -414,6 +414,11 @@ struct vsc8531_private {
+  * gpio_lock: used for PHC operations. Common for all PHYs as the load/save GPIO
+  * is shared.
+  */
++
++enum vsc85xx_global_phy {
++	VSC88XX_BASE_ADDR = 0,
++};
++
+ struct vsc85xx_shared_private {
+ 	struct mutex gpio_lock;
+ };
+--- a/drivers/net/phy/mscc/mscc_main.c
++++ b/drivers/net/phy/mscc/mscc_main.c
+@@ -700,7 +700,7 @@ int phy_base_write(struct phy_device *ph
+ 		dump_stack();
+ 	}
+ 
+-	return __phy_package_write(phydev, regnum, val);
++	return __phy_package_write(phydev, VSC88XX_BASE_ADDR, regnum, val);
+ }
+ 
+ /* phydev->bus->mdio_lock should be locked when using this function */
+@@ -711,7 +711,7 @@ int phy_base_read(struct phy_device *phy
+ 		dump_stack();
+ 	}
+ 
+-	return __phy_package_read(phydev, regnum);
++	return __phy_package_read(phydev, VSC88XX_BASE_ADDR, regnum);
+ }
+ 
+ u32 vsc85xx_csr_read(struct phy_device *phydev,
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1602,20 +1602,22 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
+ /**
+  * phy_package_join - join a common PHY group
+  * @phydev: target phy_device struct
+- * @addr: cookie and PHY address for global register access
++ * @base_addr: cookie and base PHY address of PHY package for offset
++ *   calculation of global register access
+  * @priv_size: if non-zero allocate this amount of bytes for private data
+  *
+  * This joins a PHY group and provides a shared storage for all phydevs in
+  * this group. This is intended to be used for packages which contain
+  * more than one PHY, for example a quad PHY transceiver.
+  *
+- * The addr parameter serves as a cookie which has to have the same value
+- * for all members of one group and as a PHY address to access generic
+- * registers of a PHY package. Usually, one of the PHY addresses of the
+- * different PHYs in the package provides access to these global registers.
++ * The base_addr parameter serves as cookie which has to have the same values
++ * for all members of one group and as the base PHY address of the PHY package
++ * for offset calculation to access generic registers of a PHY package.
++ * Usually, one of the PHY addresses of the different PHYs in the package
++ * provides access to these global registers.
+  * The address which is given here, will be used in the phy_package_read()
+- * and phy_package_write() convenience functions. If your PHY doesn't have
+- * global registers you can just pick any of the PHY addresses.
++ * and phy_package_write() convenience functions as base and added to the
++ * passed offset in those functions.
+  *
+  * This will set the shared pointer of the phydev to the shared storage.
+  * If this is the first call for a this cookie the shared storage will be
+@@ -1625,17 +1627,17 @@ EXPORT_SYMBOL_GPL(phy_driver_is_genphy_1
+  * Returns < 1 on error, 0 on success. Esp. calling phy_package_join()
+  * with the same cookie but a different priv_size is an error.
+  */
+-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size)
++int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size)
+ {
+ 	struct mii_bus *bus = phydev->mdio.bus;
+ 	struct phy_package_shared *shared;
+ 	int ret;
+ 
+-	if (addr < 0 || addr >= PHY_MAX_ADDR)
++	if (base_addr < 0 || base_addr >= PHY_MAX_ADDR)
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&bus->shared_lock);
+-	shared = bus->shared[addr];
++	shared = bus->shared[base_addr];
+ 	if (!shared) {
+ 		ret = -ENOMEM;
+ 		shared = kzalloc(sizeof(*shared), GFP_KERNEL);
+@@ -1647,9 +1649,9 @@ int phy_package_join(struct phy_device *
+ 				goto err_free;
+ 			shared->priv_size = priv_size;
+ 		}
+-		shared->addr = addr;
++		shared->base_addr = base_addr;
+ 		refcount_set(&shared->refcnt, 1);
+-		bus->shared[addr] = shared;
++		bus->shared[base_addr] = shared;
+ 	} else {
+ 		ret = -EINVAL;
+ 		if (priv_size && priv_size != shared->priv_size)
+@@ -1687,7 +1689,7 @@ void phy_package_leave(struct phy_device
+ 		return;
+ 
+ 	if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+-		bus->shared[shared->addr] = NULL;
++		bus->shared[shared->base_addr] = NULL;
+ 		mutex_unlock(&bus->shared_lock);
+ 		kfree(shared->priv);
+ 		kfree(shared);
+@@ -1706,7 +1708,8 @@ static void devm_phy_package_leave(struc
+  * devm_phy_package_join - resource managed phy_package_join()
+  * @dev: device that is registering this PHY package
+  * @phydev: target phy_device struct
+- * @addr: cookie and PHY address for global register access
++ * @base_addr: cookie and base PHY address of PHY package for offset
++ *   calculation of global register access
+  * @priv_size: if non-zero allocate this amount of bytes for private data
+  *
+  * Managed phy_package_join(). Shared storage fetched by this function,
+@@ -1714,7 +1717,7 @@ static void devm_phy_package_leave(struc
+  * phy_package_join() for more information.
+  */
+ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+-			  int addr, size_t priv_size)
++			  int base_addr, size_t priv_size)
+ {
+ 	struct phy_device **ptr;
+ 	int ret;
+@@ -1724,7 +1727,7 @@ int devm_phy_package_join(struct device
+ 	if (!ptr)
+ 		return -ENOMEM;
+ 
+-	ret = phy_package_join(phydev, addr, priv_size);
++	ret = phy_package_join(phydev, base_addr, priv_size);
+ 
+ 	if (!ret) {
+ 		*ptr = phydev;
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -319,7 +319,8 @@ struct mdio_bus_stats {
+ 
+ /**
+  * struct phy_package_shared - Shared information in PHY packages
+- * @addr: Common PHY address used to combine PHYs in one package
++ * @base_addr: Base PHY address of PHY package used to combine PHYs
++ *   in one package and for offset calculation of phy_package_read/write
+  * @refcnt: Number of PHYs connected to this shared data
+  * @flags: Initialization of PHY package
+  * @priv_size: Size of the shared private data @priv
+@@ -330,7 +331,7 @@ struct mdio_bus_stats {
+  * phy_package_leave().
+  */
+ struct phy_package_shared {
+-	u8 addr;
++	u8 base_addr;
+ 	refcount_t refcnt;
+ 	unsigned long flags;
+ 	size_t priv_size;
+@@ -1763,10 +1764,10 @@ int phy_ethtool_get_link_ksettings(struc
+ int phy_ethtool_set_link_ksettings(struct net_device *ndev,
+ 				   const struct ethtool_link_ksettings *cmd);
+ int phy_ethtool_nway_reset(struct net_device *ndev);
+-int phy_package_join(struct phy_device *phydev, int addr, size_t priv_size);
++int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
+ void phy_package_leave(struct phy_device *phydev);
+ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+-			  int addr, size_t priv_size);
++			  int base_addr, size_t priv_size);
+ 
+ #if IS_ENABLED(CONFIG_PHYLIB)
+ int __init mdio_bus_init(void);
+@@ -1778,46 +1779,65 @@ int phy_ethtool_get_sset_count(struct ph
+ int phy_ethtool_get_stats(struct phy_device *phydev,
+ 			  struct ethtool_stats *stats, u64 *data);
+ 
+-static inline int phy_package_read(struct phy_device *phydev, u32 regnum)
++static inline int phy_package_address(struct phy_device *phydev,
++				      unsigned int addr_offset)
+ {
+ 	struct phy_package_shared *shared = phydev->shared;
++	u8 base_addr = shared->base_addr;
+ 
+-	if (!shared)
++	if (addr_offset >= PHY_MAX_ADDR - base_addr)
+ 		return -EIO;
+ 
+-	return mdiobus_read(phydev->mdio.bus, shared->addr, regnum);
++	/* we know that addr will be in the range 0..31 and thus the
++	 * implicit cast to a signed int is not a problem.
++	 */
++	return base_addr + addr_offset;
+ }
+ 
+-static inline int __phy_package_read(struct phy_device *phydev, u32 regnum)
++static inline int phy_package_read(struct phy_device *phydev,
++				   unsigned int addr_offset, u32 regnum)
+ {
+-	struct phy_package_shared *shared = phydev->shared;
++	int addr = phy_package_address(phydev, addr_offset);
+ 
+-	if (!shared)
+-		return -EIO;
++	if (addr < 0)
++		return addr;
++
++	return mdiobus_read(phydev->mdio.bus, addr, regnum);
++}
++
++static inline int __phy_package_read(struct phy_device *phydev,
++				     unsigned int addr_offset, u32 regnum)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++
++	if (addr < 0)
++		return addr;
+ 
+-	return __mdiobus_read(phydev->mdio.bus, shared->addr, regnum);
++	return __mdiobus_read(phydev->mdio.bus, addr, regnum);
+ }
+ 
+ static inline int phy_package_write(struct phy_device *phydev,
+-				    u32 regnum, u16 val)
++				    unsigned int addr_offset, u32 regnum,
++				    u16 val)
+ {
+-	struct phy_package_shared *shared = phydev->shared;
++	int addr = phy_package_address(phydev, addr_offset);
+ 
+-	if (!shared)
+-		return -EIO;
++	if (addr < 0)
++		return addr;
+ 
+-	return mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
++	return mdiobus_write(phydev->mdio.bus, addr, regnum, val);
+ }
+ 
+ static inline int __phy_package_write(struct phy_device *phydev,
+-				      u32 regnum, u16 val)
++				      unsigned int addr_offset, u32 regnum,
++				      u16 val)
+ {
+-	struct phy_package_shared *shared = phydev->shared;
++	int addr = phy_package_address(phydev, addr_offset);
+ 
+-	if (!shared)
+-		return -EIO;
++	if (addr < 0)
++		return addr;
+ 
+-	return __mdiobus_write(phydev->mdio.bus, shared->addr, regnum, val);
++	return __mdiobus_write(phydev->mdio.bus, addr, regnum, val);
+ }
+ 
+ static inline bool __phy_package_set_once(struct phy_device *phydev,
diff --git a/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch b/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch
new file mode 100644
index 00000000000..4a17d464534
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-03-net-phy-restructure-__phy_write-read_mmd-to-helper-a.patch
@@ -0,0 +1,116 @@
+From 028672bd1d73cf65249a420c1de75e8d2acd2f6a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:33 +0100
+Subject: [PATCH 3/4] net: phy: restructure __phy_write/read_mmd to helper and
+ phydev user
+
+Restructure phy_write_mmd and phy_read_mmd to implement generic helper
+for direct mdiobus access for mmd and use these helper for phydev user.
+
+This is needed in preparation of PHY package API that requires generic
+access to the mdiobus and are deatched from phydev struct but instead
+access them based on PHY package base_addr and offsets.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy-core.c | 64 ++++++++++++++++++--------------------
+ 1 file changed, 30 insertions(+), 34 deletions(-)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -528,6 +528,28 @@ static void mmd_phy_indirect(struct mii_
+ 			devad | MII_MMD_CTRL_NOINCR);
+ }
+ 
++static int mmd_phy_read(struct mii_bus *bus, int phy_addr, bool is_c45,
++			int devad, u32 regnum)
++{
++	if (is_c45)
++		return __mdiobus_c45_read(bus, phy_addr, devad, regnum);
++
++	mmd_phy_indirect(bus, phy_addr, devad, regnum);
++	/* Read the content of the MMD's selected register */
++	return __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
++}
++
++static int mmd_phy_write(struct mii_bus *bus, int phy_addr, bool is_c45,
++			 int devad, u32 regnum, u16 val)
++{
++	if (is_c45)
++		return __mdiobus_c45_write(bus, phy_addr, devad, regnum, val);
++
++	mmd_phy_indirect(bus, phy_addr, devad, regnum);
++	/* Write the data into MMD's selected register */
++	return __mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
++}
++
+ /**
+  * __phy_read_mmd - Convenience function for reading a register
+  * from an MMD on a given PHY.
+@@ -539,26 +561,14 @@ static void mmd_phy_indirect(struct mii_
+  */
+ int __phy_read_mmd(struct phy_device *phydev, int devad, u32 regnum)
+ {
+-	int val;
+-
+ 	if (regnum > (u16)~0 || devad > 32)
+ 		return -EINVAL;
+ 
+-	if (phydev->drv && phydev->drv->read_mmd) {
+-		val = phydev->drv->read_mmd(phydev, devad, regnum);
+-	} else if (phydev->is_c45) {
+-		val = __mdiobus_c45_read(phydev->mdio.bus, phydev->mdio.addr,
+-					 devad, regnum);
+-	} else {
+-		struct mii_bus *bus = phydev->mdio.bus;
+-		int phy_addr = phydev->mdio.addr;
+-
+-		mmd_phy_indirect(bus, phy_addr, devad, regnum);
+-
+-		/* Read the content of the MMD's selected register */
+-		val = __mdiobus_read(bus, phy_addr, MII_MMD_DATA);
+-	}
+-	return val;
++	if (phydev->drv && phydev->drv->read_mmd)
++		return phydev->drv->read_mmd(phydev, devad, regnum);
++
++	return mmd_phy_read(phydev->mdio.bus, phydev->mdio.addr,
++			    phydev->is_c45, devad, regnum);
+ }
+ EXPORT_SYMBOL(__phy_read_mmd);
+ 
+@@ -595,28 +605,14 @@ EXPORT_SYMBOL(phy_read_mmd);
+  */
+ int __phy_write_mmd(struct phy_device *phydev, int devad, u32 regnum, u16 val)
+ {
+-	int ret;
+-
+ 	if (regnum > (u16)~0 || devad > 32)
+ 		return -EINVAL;
+ 
+-	if (phydev->drv && phydev->drv->write_mmd) {
+-		ret = phydev->drv->write_mmd(phydev, devad, regnum, val);
+-	} else if (phydev->is_c45) {
+-		ret = __mdiobus_c45_write(phydev->mdio.bus, phydev->mdio.addr,
+-					  devad, regnum, val);
+-	} else {
+-		struct mii_bus *bus = phydev->mdio.bus;
+-		int phy_addr = phydev->mdio.addr;
++	if (phydev->drv && phydev->drv->write_mmd)
++		return phydev->drv->write_mmd(phydev, devad, regnum, val);
+ 
+-		mmd_phy_indirect(bus, phy_addr, devad, regnum);
+-
+-		/* Write the data into MMD's selected register */
+-		__mdiobus_write(bus, phy_addr, MII_MMD_DATA, val);
+-
+-		ret = 0;
+-	}
+-	return ret;
++	return mmd_phy_write(phydev->mdio.bus, phydev->mdio.addr,
++			     phydev->is_c45, devad, regnum, val);
+ }
+ EXPORT_SYMBOL(__phy_write_mmd);
+ 
diff --git a/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch b/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch
new file mode 100644
index 00000000000..a628a379291
--- /dev/null
+++ b/target/linux/generic/backport-6.1/714-v6.8-04-net-phy-add-support-for-PHY-package-MMD-read-write.patch
@@ -0,0 +1,196 @@
+From d63710fc0f1a501fd75a7025e3070a96ffa1645f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Fri, 15 Dec 2023 14:15:34 +0100
+Subject: [PATCH 4/4] net: phy: add support for PHY package MMD read/write
+
+Some PHY in PHY package may require to read/write MMD regs to correctly
+configure the PHY package.
+
+Add support for these additional required function in both lock and no
+lock variant.
+
+It's assumed that the entire PHY package is either C22 or C45. We use
+C22 or C45 way of writing/reading to mmd regs based on the passed phydev
+whether it's C22 or C45.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy-core.c | 140 +++++++++++++++++++++++++++++++++++++
+ include/linux/phy.h        |  16 +++++
+ 2 files changed, 156 insertions(+)
+
+--- a/drivers/net/phy/phy-core.c
++++ b/drivers/net/phy/phy-core.c
+@@ -639,6 +639,146 @@ int phy_write_mmd(struct phy_device *phy
+ EXPORT_SYMBOL(phy_write_mmd);
+ 
+ /**
++ * __phy_package_read_mmd - read MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to read from
++ * @regnum: The register on the MMD to read
++ *
++ * Convenience helper for reading a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for __phy_read();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int __phy_package_read_mmd(struct phy_device *phydev,
++			   unsigned int addr_offset, int devad,
++			   u32 regnum)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	return mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			    regnum);
++}
++EXPORT_SYMBOL(__phy_package_read_mmd);
++
++/**
++ * phy_package_read_mmd - read MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to read from
++ * @regnum: The register on the MMD to read
++ *
++ * Convenience helper for reading a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for phy_read();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int phy_package_read_mmd(struct phy_device *phydev,
++			 unsigned int addr_offset, int devad,
++			 u32 regnum)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++	int val;
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	phy_lock_mdio_bus(phydev);
++	val = mmd_phy_read(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			   regnum);
++	phy_unlock_mdio_bus(phydev);
++
++	return val;
++}
++EXPORT_SYMBOL(phy_package_read_mmd);
++
++/**
++ * __phy_package_write_mmd - write MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to write to
++ * @regnum: The register on the MMD to write
++ * @val: value to write to @regnum
++ *
++ * Convenience helper for writing a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for __phy_write();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int __phy_package_write_mmd(struct phy_device *phydev,
++			    unsigned int addr_offset, int devad,
++			    u32 regnum, u16 val)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	return mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			     regnum, val);
++}
++EXPORT_SYMBOL(__phy_package_write_mmd);
++
++/**
++ * phy_package_write_mmd - write MMD reg relative to PHY package base addr
++ * @phydev: The phy_device struct
++ * @addr_offset: The offset to be added to PHY package base_addr
++ * @devad: The MMD to write to
++ * @regnum: The register on the MMD to write
++ * @val: value to write to @regnum
++ *
++ * Convenience helper for writing a register of an MMD on a given PHY
++ * using the PHY package base address. The base address is added to
++ * the addr_offset value.
++ *
++ * Same calling rules as for phy_write();
++ *
++ * NOTE: It's assumed that the entire PHY package is either C22 or C45.
++ */
++int phy_package_write_mmd(struct phy_device *phydev,
++			  unsigned int addr_offset, int devad,
++			  u32 regnum, u16 val)
++{
++	int addr = phy_package_address(phydev, addr_offset);
++	int ret;
++
++	if (addr < 0)
++		return addr;
++
++	if (regnum > (u16)~0 || devad > 32)
++		return -EINVAL;
++
++	phy_lock_mdio_bus(phydev);
++	ret = mmd_phy_write(phydev->mdio.bus, addr, phydev->is_c45, devad,
++			    regnum, val);
++	phy_unlock_mdio_bus(phydev);
++
++	return ret;
++}
++EXPORT_SYMBOL(phy_package_write_mmd);
++
++/**
+  * phy_modify_changed - Function for modifying a PHY register
+  * @phydev: the phy_device struct
+  * @regnum: register number to modify
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1840,6 +1840,22 @@ static inline int __phy_package_write(st
+ 	return __mdiobus_write(phydev->mdio.bus, addr, regnum, val);
+ }
+ 
++int __phy_package_read_mmd(struct phy_device *phydev,
++			   unsigned int addr_offset, int devad,
++			   u32 regnum);
++
++int phy_package_read_mmd(struct phy_device *phydev,
++			 unsigned int addr_offset, int devad,
++			 u32 regnum);
++
++int __phy_package_write_mmd(struct phy_device *phydev,
++			    unsigned int addr_offset, int devad,
++			    u32 regnum, u16 val);
++
++int phy_package_write_mmd(struct phy_device *phydev,
++			  unsigned int addr_offset, int devad,
++			  u32 regnum, u16 val);
++
+ static inline bool __phy_package_set_once(struct phy_device *phydev,
+ 					  unsigned int b)
+ {
diff --git a/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch b/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch
new file mode 100644
index 00000000000..2886123f2d8
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-01-v6.2-net-fman-memac-Add-serdes-support.patch
@@ -0,0 +1,103 @@
+From affa013f494486079c3c5ad2d00cebc41a3d7445 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:36 -0400
+Subject: [PATCH 01/21] net: fman: memac: Add serdes support
+
+This adds support for using a serdes which has to be configured. This is
+primarly in preparation for phylink conversion, which will then change the
+serdes mode dynamically.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ .../net/ethernet/freescale/fman/fman_memac.c  | 49 ++++++++++++++++++-
+ 1 file changed, 47 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -13,6 +13,7 @@
+ #include <linux/io.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
++#include <linux/phy/phy.h>
+ #include <linux/of_mdio.h>
+ 
+ /* PCS registers */
+@@ -324,6 +325,7 @@ struct fman_mac {
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
++	struct phy *serdes;
+ 	struct phy_device *pcsphy;
+ 	bool allmulti_enabled;
+ };
+@@ -1203,17 +1205,56 @@ int memac_initialization(struct mac_devi
+ 		}
+ 	}
+ 
++	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
++	err = PTR_ERR(memac->serdes);
++	if (err == -ENODEV || err == -ENOSYS) {
++		dev_dbg(mac_dev->dev, "could not get (optional) serdes\n");
++		memac->serdes = NULL;
++	} else if (IS_ERR(memac->serdes)) {
++		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
++		goto _return_fm_mac_free;
++	} else {
++		err = phy_init(memac->serdes);
++		if (err) {
++			dev_err_probe(mac_dev->dev, err,
++				      "could not initialize serdes\n");
++			goto _return_fm_mac_free;
++		}
++
++		err = phy_power_on(memac->serdes);
++		if (err) {
++			dev_err_probe(mac_dev->dev, err,
++				      "could not power on serdes\n");
++			goto _return_phy_exit;
++		}
++
++		if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
++		    memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
++		    memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
++		    memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
++		    memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
++			err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
++					       memac->phy_if);
++			if (err) {
++				dev_err_probe(mac_dev->dev, err,
++					      "could not set serdes mode to %s\n",
++					      phy_modes(memac->phy_if));
++				goto _return_phy_power_off;
++			}
++		}
++	}
++
+ 	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
+ 		struct phy_device *phy;
+ 
+ 		err = of_phy_register_fixed_link(mac_node);
+ 		if (err)
+-			goto _return_fm_mac_free;
++			goto _return_phy_power_off;
+ 
+ 		fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
+ 		if (!fixed_link) {
+ 			err = -ENOMEM;
+-			goto _return_fm_mac_free;
++			goto _return_phy_power_off;
+ 		}
+ 
+ 		mac_dev->phy_node = of_node_get(mac_node);
+@@ -1242,6 +1283,10 @@ int memac_initialization(struct mac_devi
+ 
+ 	goto _return;
+ 
++_return_phy_power_off:
++	phy_power_off(memac->serdes);
++_return_phy_exit:
++	phy_exit(memac->serdes);
+ _return_fixed_link_free:
+ 	kfree(fixed_link);
+ _return_fm_mac_free:
diff --git a/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch b/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch
new file mode 100644
index 00000000000..873debc0807
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-02-v6.2-net-fman-memac-Use-lynx-pcs-driver.patch
@@ -0,0 +1,384 @@
+From fe60e7154d3a35af975c5e6570d6ec31aab9a731 Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:37 -0400
+Subject: [PATCH 02/21] net: fman: memac: Use lynx pcs driver
+
+Although not stated in the datasheet, as far as I can tell PCS for mEMACs
+is a "Lynx." By reusing the existing driver, we can remove the PCS
+management code from the memac driver. This requires calling some PCS
+functions manually which phylink would usually do for us, but we will let
+it do that soon.
+
+One problem is that we don't actually have a PCS for QSGMII. We pretend
+that each mEMAC's MDIO bus has four QSGMII PCSs, but this is not the case.
+Only the "base" mEMAC's MDIO bus has the four QSGMII PCSs. This is not an
+issue yet, because we never get the PCS state. However, it will be once the
+conversion to phylink is complete, since the links will appear to never
+come up. To get around this, we allow specifying multiple PCSs in pcsphy.
+This breaks backwards compatibility with old device trees, but only for
+QSGMII. IMO this is the only reasonable way to figure out what the actual
+QSGMII PCS is.
+
+Additionally, we now also support a separate XFI PCS. This can allow the
+SerDes driver to set different addresses for the SGMII and XFI PCSs so they
+can be accessed at the same time.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/freescale/fman/Kconfig   |   3 +
+ .../net/ethernet/freescale/fman/fman_memac.c  | 258 +++++++-----------
+ 2 files changed, 105 insertions(+), 156 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/Kconfig
++++ b/drivers/net/ethernet/freescale/fman/Kconfig
+@@ -4,6 +4,9 @@ config FSL_FMAN
+ 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
+ 	select GENERIC_ALLOCATOR
+ 	select PHYLIB
++	select PHYLINK
++	select PCS
++	select PCS_LYNX
+ 	select CRC32
+ 	default n
+ 	help
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -11,43 +11,12 @@
+ 
+ #include <linux/slab.h>
+ #include <linux/io.h>
++#include <linux/pcs-lynx.h>
+ #include <linux/phy.h>
+ #include <linux/phy_fixed.h>
+ #include <linux/phy/phy.h>
+ #include <linux/of_mdio.h>
+ 
+-/* PCS registers */
+-#define MDIO_SGMII_CR			0x00
+-#define MDIO_SGMII_DEV_ABIL_SGMII	0x04
+-#define MDIO_SGMII_LINK_TMR_L		0x12
+-#define MDIO_SGMII_LINK_TMR_H		0x13
+-#define MDIO_SGMII_IF_MODE		0x14
+-
+-/* SGMII Control defines */
+-#define SGMII_CR_AN_EN			0x1000
+-#define SGMII_CR_RESTART_AN		0x0200
+-#define SGMII_CR_FD			0x0100
+-#define SGMII_CR_SPEED_SEL1_1G		0x0040
+-#define SGMII_CR_DEF_VAL		(SGMII_CR_AN_EN | SGMII_CR_FD | \
+-					 SGMII_CR_SPEED_SEL1_1G)
+-
+-/* SGMII Device Ability for SGMII defines */
+-#define MDIO_SGMII_DEV_ABIL_SGMII_MODE	0x4001
+-#define MDIO_SGMII_DEV_ABIL_BASEX_MODE	0x01A0
+-
+-/* Link timer define */
+-#define LINK_TMR_L			0xa120
+-#define LINK_TMR_H			0x0007
+-#define LINK_TMR_L_BASEX		0xaf08
+-#define LINK_TMR_H_BASEX		0x002f
+-
+-/* SGMII IF Mode defines */
+-#define IF_MODE_USE_SGMII_AN		0x0002
+-#define IF_MODE_SGMII_EN		0x0001
+-#define IF_MODE_SGMII_SPEED_100M	0x0004
+-#define IF_MODE_SGMII_SPEED_1G		0x0008
+-#define IF_MODE_SGMII_DUPLEX_HALF	0x0010
+-
+ /* Num of additional exact match MAC adr regs */
+ #define MEMAC_NUM_OF_PADDRS 7
+ 
+@@ -326,7 +295,9 @@ struct fman_mac {
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
+ 	struct phy *serdes;
+-	struct phy_device *pcsphy;
++	struct phylink_pcs *sgmii_pcs;
++	struct phylink_pcs *qsgmii_pcs;
++	struct phylink_pcs *xfi_pcs;
+ 	bool allmulti_enabled;
+ };
+ 
+@@ -487,91 +458,22 @@ static u32 get_mac_addr_hash_code(u64 et
+ 	return xor_val;
+ }
+ 
+-static void setup_sgmii_internal_phy(struct fman_mac *memac,
+-				     struct fixed_phy_status *fixed_link)
+-{
+-	u16 tmp_reg16;
+-
+-	if (WARN_ON(!memac->pcsphy))
+-		return;
+-
+-	/* SGMII mode */
+-	tmp_reg16 = IF_MODE_SGMII_EN;
+-	if (!fixed_link)
+-		/* AN enable */
+-		tmp_reg16 |= IF_MODE_USE_SGMII_AN;
+-	else {
+-		switch (fixed_link->speed) {
+-		case 10:
+-			/* For 10M: IF_MODE[SPEED_10M] = 0 */
+-		break;
+-		case 100:
+-			tmp_reg16 |= IF_MODE_SGMII_SPEED_100M;
+-		break;
+-		case 1000:
+-		default:
+-			tmp_reg16 |= IF_MODE_SGMII_SPEED_1G;
+-		break;
+-		}
+-		if (!fixed_link->duplex)
+-			tmp_reg16 |= IF_MODE_SGMII_DUPLEX_HALF;
+-	}
+-	phy_write(memac->pcsphy, MDIO_SGMII_IF_MODE, tmp_reg16);
+-
+-	/* Device ability according to SGMII specification */
+-	tmp_reg16 = MDIO_SGMII_DEV_ABIL_SGMII_MODE;
+-	phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
+-
+-	/* Adjust link timer for SGMII  -
+-	 * According to Cisco SGMII specification the timer should be 1.6 ms.
+-	 * The link_timer register is configured in units of the clock.
+-	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
+-	 * unit = 1 / (125*10^6 Hz) = 8 ns.
+-	 * 1.6 ms in units of 8 ns = 1.6ms / 8ns = 2*10^5 = 0x30d40
+-	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
+-	 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
+-	 * 1.6 ms in units of 3.2 ns = 1.6ms / 3.2ns = 5*10^5 = 0x7a120.
+-	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
+-	 * we always set up here a value of 2.5 SGMII.
+-	 */
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H);
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L);
+-
+-	if (!fixed_link)
+-		/* Restart AN */
+-		tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
++static void setup_sgmii_internal(struct fman_mac *memac,
++				 struct phylink_pcs *pcs,
++				 struct fixed_phy_status *fixed_link)
++{
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
++	phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
++				PHY_INTERFACE_MODE_SGMII;
++	unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
++
++	linkmode_set_pause(advertising, true, true);
++	pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
++	if (fixed_link)
++		pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
++				      fixed_link->duplex);
+ 	else
+-		/* AN disabled */
+-		tmp_reg16 = SGMII_CR_DEF_VAL & ~SGMII_CR_AN_EN;
+-	phy_write(memac->pcsphy, 0x0, tmp_reg16);
+-}
+-
+-static void setup_sgmii_internal_phy_base_x(struct fman_mac *memac)
+-{
+-	u16 tmp_reg16;
+-
+-	/* AN Device capability  */
+-	tmp_reg16 = MDIO_SGMII_DEV_ABIL_BASEX_MODE;
+-	phy_write(memac->pcsphy, MDIO_SGMII_DEV_ABIL_SGMII, tmp_reg16);
+-
+-	/* Adjust link timer for SGMII  -
+-	 * For Serdes 1000BaseX auto-negotiation the timer should be 10 ms.
+-	 * The link_timer register is configured in units of the clock.
+-	 * - When running as 1G SGMII, Serdes clock is 125 MHz, so
+-	 * unit = 1 / (125*10^6 Hz) = 8 ns.
+-	 * 10 ms in units of 8 ns = 10ms / 8ns = 1250000 = 0x1312d0
+-	 * - When running as 2.5G SGMII, Serdes clock is 312.5 MHz, so
+-	 * unit = 1 / (312.5*10^6 Hz) = 3.2 ns.
+-	 * 10 ms in units of 3.2 ns = 10ms / 3.2ns = 3125000 = 0x2faf08.
+-	 * Since link_timer value of 1G SGMII will be too short for 2.5 SGMII,
+-	 * we always set up here a value of 2.5 SGMII.
+-	 */
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_H, LINK_TMR_H_BASEX);
+-	phy_write(memac->pcsphy, MDIO_SGMII_LINK_TMR_L, LINK_TMR_L_BASEX);
+-
+-	/* Restart AN */
+-	tmp_reg16 = SGMII_CR_DEF_VAL | SGMII_CR_RESTART_AN;
+-	phy_write(memac->pcsphy, 0x0, tmp_reg16);
++		pcs->ops->pcs_an_restart(pcs);
+ }
+ 
+ static int check_init_parameters(struct fman_mac *memac)
+@@ -983,7 +885,6 @@ static int memac_set_exception(struct fm
+ static int memac_init(struct fman_mac *memac)
+ {
+ 	struct memac_cfg *memac_drv_param;
+-	u8 i;
+ 	enet_addr_t eth_addr;
+ 	bool slow_10g_if = false;
+ 	struct fixed_phy_status *fixed_link = NULL;
+@@ -1036,32 +937,10 @@ static int memac_init(struct fman_mac *m
+ 		iowrite32be(reg32, &memac->regs->command_config);
+ 	}
+ 
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII) {
+-		/* Configure internal SGMII PHY */
+-		if (memac->basex_if)
+-			setup_sgmii_internal_phy_base_x(memac);
+-		else
+-			setup_sgmii_internal_phy(memac, fixed_link);
+-	} else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
+-		/* Configure 4 internal SGMII PHYs */
+-		for (i = 0; i < 4; i++) {
+-			u8 qsmgii_phy_addr, phy_addr;
+-			/* QSGMII PHY address occupies 3 upper bits of 5-bit
+-			 * phy_address; the lower 2 bits are used to extend
+-			 * register address space and access each one of 4
+-			 * ports inside QSGMII.
+-			 */
+-			phy_addr = memac->pcsphy->mdio.addr;
+-			qsmgii_phy_addr = (u8)((phy_addr << 2) | i);
+-			memac->pcsphy->mdio.addr = qsmgii_phy_addr;
+-			if (memac->basex_if)
+-				setup_sgmii_internal_phy_base_x(memac);
+-			else
+-				setup_sgmii_internal_phy(memac, fixed_link);
+-
+-			memac->pcsphy->mdio.addr = phy_addr;
+-		}
+-	}
++	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
++		setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
++	else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
++		setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
+ 
+ 	/* Max Frame Length */
+ 	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
+@@ -1097,12 +976,25 @@ static int memac_init(struct fman_mac *m
+ 	return 0;
+ }
+ 
++static void pcs_put(struct phylink_pcs *pcs)
++{
++	struct mdio_device *mdiodev;
++
++	if (IS_ERR_OR_NULL(pcs))
++		return;
++
++	mdiodev = lynx_get_mdio_device(pcs);
++	lynx_pcs_destroy(pcs);
++	mdio_device_free(mdiodev);
++}
++
+ static int memac_free(struct fman_mac *memac)
+ {
+ 	free_init_resources(memac);
+ 
+-	if (memac->pcsphy)
+-		put_device(&memac->pcsphy->mdio.dev);
++	pcs_put(memac->sgmii_pcs);
++	pcs_put(memac->qsgmii_pcs);
++	pcs_put(memac->xfi_pcs);
+ 
+ 	kfree(memac->memac_drv_param);
+ 	kfree(memac);
+@@ -1153,12 +1045,31 @@ static struct fman_mac *memac_config(str
+ 	return memac;
+ }
+ 
++static struct phylink_pcs *memac_pcs_create(struct device_node *mac_node,
++					    int index)
++{
++	struct device_node *node;
++	struct mdio_device *mdiodev = NULL;
++	struct phylink_pcs *pcs;
++
++	node = of_parse_phandle(mac_node, "pcsphy-handle", index);
++	if (node && of_device_is_available(node))
++		mdiodev = of_mdio_find_device(node);
++	of_node_put(node);
++
++	if (!mdiodev)
++		return ERR_PTR(-EPROBE_DEFER);
++
++	pcs = lynx_pcs_create(mdiodev);
++	return pcs;
++}
++
+ int memac_initialization(struct mac_device *mac_dev,
+ 			 struct device_node *mac_node,
+ 			 struct fman_mac_params *params)
+ {
+ 	int			 err;
+-	struct device_node	*phy_node;
++	struct phylink_pcs	*pcs;
+ 	struct fixed_phy_status *fixed_link;
+ 	struct fman_mac		*memac;
+ 
+@@ -1188,23 +1099,58 @@ int memac_initialization(struct mac_devi
+ 	memac = mac_dev->fman_mac;
+ 	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
+ 	memac->memac_drv_param->reset_on_init = true;
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+-	    memac->phy_if == PHY_INTERFACE_MODE_QSGMII) {
+-		phy_node = of_parse_phandle(mac_node, "pcsphy-handle", 0);
+-		if (!phy_node) {
+-			pr_err("PCS PHY node is not available\n");
+-			err = -EINVAL;
++
++	err = of_property_match_string(mac_node, "pcs-handle-names", "xfi");
++	if (err >= 0) {
++		memac->xfi_pcs = memac_pcs_create(mac_node, err);
++		if (IS_ERR(memac->xfi_pcs)) {
++			err = PTR_ERR(memac->xfi_pcs);
++			dev_err_probe(mac_dev->dev, err, "missing xfi pcs\n");
+ 			goto _return_fm_mac_free;
+ 		}
++	} else if (err != -EINVAL && err != -ENODATA) {
++		goto _return_fm_mac_free;
++	}
+ 
+-		memac->pcsphy = of_phy_find_device(phy_node);
+-		if (!memac->pcsphy) {
+-			pr_err("of_phy_find_device (PCS PHY) failed\n");
+-			err = -EINVAL;
++	err = of_property_match_string(mac_node, "pcs-handle-names", "qsgmii");
++	if (err >= 0) {
++		memac->qsgmii_pcs = memac_pcs_create(mac_node, err);
++		if (IS_ERR(memac->qsgmii_pcs)) {
++			err = PTR_ERR(memac->qsgmii_pcs);
++			dev_err_probe(mac_dev->dev, err,
++				      "missing qsgmii pcs\n");
+ 			goto _return_fm_mac_free;
+ 		}
++	} else if (err != -EINVAL && err != -ENODATA) {
++		goto _return_fm_mac_free;
++	}
++
++	/* For compatibility, if pcs-handle-names is missing, we assume this
++	 * phy is the first one in pcsphy-handle
++	 */
++	err = of_property_match_string(mac_node, "pcs-handle-names", "sgmii");
++	if (err == -EINVAL || err == -ENODATA)
++		pcs = memac_pcs_create(mac_node, 0);
++	else if (err < 0)
++		goto _return_fm_mac_free;
++	else
++		pcs = memac_pcs_create(mac_node, err);
++
++	if (!pcs) {
++		dev_err(mac_dev->dev, "missing pcs\n");
++		err = -ENOENT;
++		goto _return_fm_mac_free;
+ 	}
+ 
++	/* If err is set here, it means that pcs-handle-names was missing above
++	 * (and therefore that xfi_pcs cannot be set). If we are defaulting to
++	 * XGMII, assume this is for XFI. Otherwise, assume it is for SGMII.
++	 */
++	if (err && mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		memac->xfi_pcs = pcs;
++	else
++		memac->sgmii_pcs = pcs;
++
+ 	memac->serdes = devm_of_phy_get(mac_dev->dev, mac_node, "serdes");
+ 	err = PTR_ERR(memac->serdes);
+ 	if (err == -ENODEV || err == -ENOSYS) {
diff --git a/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch
new file mode 100644
index 00000000000..63b651bb2dd
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-03-v6.2-net-dpaa-Convert-to-phylink.patch
@@ -0,0 +1,2451 @@
+From 38e50fc3d43882a43115b4f1ca3eb88255163c5b Mon Sep 17 00:00:00 2001
+From: Sean Anderson <sean.anderson@seco.com>
+Date: Mon, 17 Oct 2022 16:22:38 -0400
+Subject: [PATCH 03/21] net: dpaa: Convert to phylink
+
+This converts DPAA to phylink. All macs are converted. This should work
+with no device tree modifications (including those made in this series),
+except for QSGMII (as noted previously).
+
+The mEMAC configuration is one of the tricker areas. I have tried to
+capture all the restrictions across the various models. Most of the time,
+we assume that if the serdes supports a mode or the phy-interface-mode
+specifies it, then we support it. The only place we can't do this is
+(RG)MII, since there's no serdes. In that case, we rely on a (new)
+devicetree property. There are also several cases where half-duplex is
+broken. Unfortunately, only a single compatible is used for the MAC, so we
+have to use the board compatible instead.
+
+The 10GEC conversion is very straightforward, since it only supports XAUI.
+There is generally nothing to configure.
+
+The dTSEC conversion is broadly similar to mEMAC, but is simpler because we
+don't support configuring the SerDes (though this can be easily added) and
+we don't have multiple PCSs. From what I can tell, there's nothing
+different in the driver or documentation between SGMII and 1000BASE-X
+except for the advertising. Similarly, I couldn't find anything about
+2500BASE-X. In both cases, I treat them like SGMII. These modes aren't used
+by any in-tree boards. Similarly, despite being mentioned in the driver, I
+couldn't find any documented SoCs which supported QSGMII.  I have left it
+unimplemented for now.
+
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/ethernet/freescale/dpaa/Kconfig   |   4 +-
+ .../net/ethernet/freescale/dpaa/dpaa_eth.c    |  89 +--
+ .../ethernet/freescale/dpaa/dpaa_ethtool.c    |  90 +--
+ drivers/net/ethernet/freescale/fman/Kconfig   |   1 -
+ .../net/ethernet/freescale/fman/fman_dtsec.c  | 458 +++++++--------
+ .../net/ethernet/freescale/fman/fman_mac.h    |  10 -
+ .../net/ethernet/freescale/fman/fman_memac.c  | 547 +++++++++---------
+ .../net/ethernet/freescale/fman/fman_tgec.c   | 131 ++---
+ drivers/net/ethernet/freescale/fman/mac.c     | 168 +-----
+ drivers/net/ethernet/freescale/fman/mac.h     |  23 +-
+ 10 files changed, 612 insertions(+), 909 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/dpaa/Kconfig
++++ b/drivers/net/ethernet/freescale/dpaa/Kconfig
+@@ -2,8 +2,8 @@
+ menuconfig FSL_DPAA_ETH
+ 	tristate "DPAA Ethernet"
+ 	depends on FSL_DPAA && FSL_FMAN
+-	select PHYLIB
+-	select FIXED_PHY
++	select PHYLINK
++	select PCS_LYNX
+ 	help
+ 	  Data Path Acceleration Architecture Ethernet driver,
+ 	  supporting the Freescale QorIQ chips.
+--- a/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
++++ b/drivers/net/ethernet/freescale/dpaa/dpaa_eth.c
+@@ -264,8 +264,19 @@ static int dpaa_netdev_init(struct net_d
+ 	net_dev->needed_headroom = priv->tx_headroom;
+ 	net_dev->watchdog_timeo = msecs_to_jiffies(tx_timeout);
+ 
+-	mac_dev->net_dev = net_dev;
++	/* The rest of the config is filled in by the mac device already */
++	mac_dev->phylink_config.dev = &net_dev->dev;
++	mac_dev->phylink_config.type = PHYLINK_NETDEV;
+ 	mac_dev->update_speed = dpaa_eth_cgr_set_speed;
++	mac_dev->phylink = phylink_create(&mac_dev->phylink_config,
++					  dev_fwnode(mac_dev->dev),
++					  mac_dev->phy_if,
++					  mac_dev->phylink_ops);
++	if (IS_ERR(mac_dev->phylink)) {
++		err = PTR_ERR(mac_dev->phylink);
++		dev_err_probe(dev, err, "Could not create phylink\n");
++		return err;
++	}
+ 
+ 	/* start without the RUNNING flag, phylib controls it later */
+ 	netif_carrier_off(net_dev);
+@@ -273,6 +284,7 @@ static int dpaa_netdev_init(struct net_d
+ 	err = register_netdev(net_dev);
+ 	if (err < 0) {
+ 		dev_err(dev, "register_netdev() = %d\n", err);
++		phylink_destroy(mac_dev->phylink);
+ 		return err;
+ 	}
+ 
+@@ -295,8 +307,7 @@ static int dpaa_stop(struct net_device *
+ 	 */
+ 	msleep(200);
+ 
+-	if (mac_dev->phy_dev)
+-		phy_stop(mac_dev->phy_dev);
++	phylink_stop(mac_dev->phylink);
+ 	mac_dev->disable(mac_dev->fman_mac);
+ 
+ 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++) {
+@@ -305,8 +316,7 @@ static int dpaa_stop(struct net_device *
+ 			err = error;
+ 	}
+ 
+-	if (net_dev->phydev)
+-		phy_disconnect(net_dev->phydev);
++	phylink_disconnect_phy(mac_dev->phylink);
+ 	net_dev->phydev = NULL;
+ 
+ 	msleep(200);
+@@ -834,10 +844,10 @@ static int dpaa_eth_cgr_init(struct dpaa
+ 
+ 	/* Set different thresholds based on the configured MAC speed.
+ 	 * This may turn suboptimal if the MAC is reconfigured at another
+-	 * speed, so MACs must call dpaa_eth_cgr_set_speed in their adjust_link
++	 * speed, so MACs must call dpaa_eth_cgr_set_speed in their link_up
+ 	 * callback.
+ 	 */
+-	if (priv->mac_dev->if_support & SUPPORTED_10000baseT_Full)
++	if (priv->mac_dev->phylink_config.mac_capabilities & MAC_10000FD)
+ 		cs_th = DPAA_CS_THRESHOLD_10G;
+ 	else
+ 		cs_th = DPAA_CS_THRESHOLD_1G;
+@@ -866,7 +876,7 @@ out_error:
+ 
+ static void dpaa_eth_cgr_set_speed(struct mac_device *mac_dev, int speed)
+ {
+-	struct net_device *net_dev = mac_dev->net_dev;
++	struct net_device *net_dev = to_net_dev(mac_dev->phylink_config.dev);
+ 	struct dpaa_priv *priv = netdev_priv(net_dev);
+ 	struct qm_mcc_initcgr opts = { };
+ 	u32 cs_th;
+@@ -2905,58 +2915,6 @@ static void dpaa_eth_napi_disable(struct
+ 	}
+ }
+ 
+-static void dpaa_adjust_link(struct net_device *net_dev)
+-{
+-	struct mac_device *mac_dev;
+-	struct dpaa_priv *priv;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-	mac_dev->adjust_link(mac_dev);
+-}
+-
+-/* The Aquantia PHYs are capable of performing rate adaptation */
+-#define PHY_VEND_AQUANTIA	0x03a1b400
+-#define PHY_VEND_AQUANTIA2	0x31c31c00
+-
+-static int dpaa_phy_init(struct net_device *net_dev)
+-{
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+-	struct mac_device *mac_dev;
+-	struct phy_device *phy_dev;
+-	struct dpaa_priv *priv;
+-	u32 phy_vendor;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	phy_dev = of_phy_connect(net_dev, mac_dev->phy_node,
+-				 &dpaa_adjust_link, 0,
+-				 mac_dev->phy_if);
+-	if (!phy_dev) {
+-		netif_err(priv, ifup, net_dev, "init_phy() failed\n");
+-		return -ENODEV;
+-	}
+-
+-	phy_vendor = phy_dev->drv->phy_id & GENMASK(31, 10);
+-	/* Unless the PHY is capable of rate adaptation */
+-	if (mac_dev->phy_if != PHY_INTERFACE_MODE_XGMII ||
+-	    (phy_vendor != PHY_VEND_AQUANTIA &&
+-	     phy_vendor != PHY_VEND_AQUANTIA2)) {
+-		/* remove any features not supported by the controller */
+-		ethtool_convert_legacy_u32_to_link_mode(mask,
+-							mac_dev->if_support);
+-		linkmode_and(phy_dev->supported, phy_dev->supported, mask);
+-	}
+-
+-	phy_support_asym_pause(phy_dev);
+-
+-	mac_dev->phy_dev = phy_dev;
+-	net_dev->phydev = phy_dev;
+-
+-	return 0;
+-}
+-
+ static int dpaa_open(struct net_device *net_dev)
+ {
+ 	struct mac_device *mac_dev;
+@@ -2967,7 +2925,8 @@ static int dpaa_open(struct net_device *
+ 	mac_dev = priv->mac_dev;
+ 	dpaa_eth_napi_enable(priv);
+ 
+-	err = dpaa_phy_init(net_dev);
++	err = phylink_of_phy_connect(mac_dev->phylink,
++				     mac_dev->dev->of_node, 0);
+ 	if (err)
+ 		goto phy_init_failed;
+ 
+@@ -2982,7 +2941,7 @@ static int dpaa_open(struct net_device *
+ 		netif_err(priv, ifup, net_dev, "mac_dev->enable() = %d\n", err);
+ 		goto mac_start_failed;
+ 	}
+-	phy_start(priv->mac_dev->phy_dev);
++	phylink_start(mac_dev->phylink);
+ 
+ 	netif_tx_start_all_queues(net_dev);
+ 
+@@ -2991,6 +2950,7 @@ static int dpaa_open(struct net_device *
+ mac_start_failed:
+ 	for (i = 0; i < ARRAY_SIZE(mac_dev->port); i++)
+ 		fman_port_disable(mac_dev->port[i]);
++	phylink_disconnect_phy(mac_dev->phylink);
+ 
+ phy_init_failed:
+ 	dpaa_eth_napi_disable(priv);
+@@ -3146,10 +3106,12 @@ static int dpaa_ts_ioctl(struct net_devi
+ static int dpaa_ioctl(struct net_device *net_dev, struct ifreq *rq, int cmd)
+ {
+ 	int ret = -EINVAL;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
+ 
+ 	if (cmd == SIOCGMIIREG) {
+ 		if (net_dev->phydev)
+-			return phy_mii_ioctl(net_dev->phydev, rq, cmd);
++			return phylink_mii_ioctl(priv->mac_dev->phylink, rq,
++						 cmd);
+ 	}
+ 
+ 	if (cmd == SIOCSHWTSTAMP)
+@@ -3552,6 +3514,7 @@ static int dpaa_remove(struct platform_d
+ 
+ 	dev_set_drvdata(dev, NULL);
+ 	unregister_netdev(net_dev);
++	phylink_destroy(priv->mac_dev->phylink);
+ 
+ 	err = dpaa_fq_free(dev, &priv->dpaa_fq_list);
+ 
+--- a/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
++++ b/drivers/net/ethernet/freescale/dpaa/dpaa_ethtool.c
+@@ -54,27 +54,19 @@ static char dpaa_stats_global[][ETH_GSTR
+ static int dpaa_get_link_ksettings(struct net_device *net_dev,
+ 				   struct ethtool_link_ksettings *cmd)
+ {
+-	if (!net_dev->phydev)
+-		return 0;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	phy_ethtool_ksettings_get(net_dev->phydev, cmd);
+-
+-	return 0;
++	return phylink_ethtool_ksettings_get(mac_dev->phylink, cmd);
+ }
+ 
+ static int dpaa_set_link_ksettings(struct net_device *net_dev,
+ 				   const struct ethtool_link_ksettings *cmd)
+ {
+-	int err;
+-
+-	if (!net_dev->phydev)
+-		return -ENODEV;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	err = phy_ethtool_ksettings_set(net_dev->phydev, cmd);
+-	if (err < 0)
+-		netdev_err(net_dev, "phy_ethtool_ksettings_set() = %d\n", err);
+-
+-	return err;
++	return phylink_ethtool_ksettings_set(mac_dev->phylink, cmd);
+ }
+ 
+ static void dpaa_get_drvinfo(struct net_device *net_dev,
+@@ -99,80 +91,28 @@ static void dpaa_set_msglevel(struct net
+ 
+ static int dpaa_nway_reset(struct net_device *net_dev)
+ {
+-	int err;
+-
+-	if (!net_dev->phydev)
+-		return -ENODEV;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	err = 0;
+-	if (net_dev->phydev->autoneg) {
+-		err = phy_start_aneg(net_dev->phydev);
+-		if (err < 0)
+-			netdev_err(net_dev, "phy_start_aneg() = %d\n",
+-				   err);
+-	}
+-
+-	return err;
++	return phylink_ethtool_nway_reset(mac_dev->phylink);
+ }
+ 
+ static void dpaa_get_pauseparam(struct net_device *net_dev,
+ 				struct ethtool_pauseparam *epause)
+ {
+-	struct mac_device *mac_dev;
+-	struct dpaa_priv *priv;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	if (!net_dev->phydev)
+-		return;
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	epause->autoneg = mac_dev->autoneg_pause;
+-	epause->rx_pause = mac_dev->rx_pause_active;
+-	epause->tx_pause = mac_dev->tx_pause_active;
++	phylink_ethtool_get_pauseparam(mac_dev->phylink, epause);
+ }
+ 
+ static int dpaa_set_pauseparam(struct net_device *net_dev,
+ 			       struct ethtool_pauseparam *epause)
+ {
+-	struct mac_device *mac_dev;
+-	struct phy_device *phydev;
+-	bool rx_pause, tx_pause;
+-	struct dpaa_priv *priv;
+-	int err;
+-
+-	priv = netdev_priv(net_dev);
+-	mac_dev = priv->mac_dev;
+-
+-	phydev = net_dev->phydev;
+-	if (!phydev) {
+-		netdev_err(net_dev, "phy device not initialized\n");
+-		return -ENODEV;
+-	}
+-
+-	if (!phy_validate_pause(phydev, epause))
+-		return -EINVAL;
+-
+-	/* The MAC should know how to handle PAUSE frame autonegotiation before
+-	 * adjust_link is triggered by a forced renegotiation of sym/asym PAUSE
+-	 * settings.
+-	 */
+-	mac_dev->autoneg_pause = !!epause->autoneg;
+-	mac_dev->rx_pause_req = !!epause->rx_pause;
+-	mac_dev->tx_pause_req = !!epause->tx_pause;
+-
+-	/* Determine the sym/asym advertised PAUSE capabilities from the desired
+-	 * rx/tx pause settings.
+-	 */
+-
+-	phy_set_asym_pause(phydev, epause->rx_pause, epause->tx_pause);
+-
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		netdev_err(net_dev, "set_mac_active_pause() = %d\n", err);
++	struct dpaa_priv *priv = netdev_priv(net_dev);
++	struct mac_device *mac_dev = priv->mac_dev;
+ 
+-	return err;
++	return phylink_ethtool_set_pauseparam(mac_dev->phylink, epause);
+ }
+ 
+ static int dpaa_get_sset_count(struct net_device *net_dev, int type)
+--- a/drivers/net/ethernet/freescale/fman/Kconfig
++++ b/drivers/net/ethernet/freescale/fman/Kconfig
+@@ -3,7 +3,6 @@ config FSL_FMAN
+ 	tristate "FMan support"
+ 	depends on FSL_SOC || ARCH_LAYERSCAPE || COMPILE_TEST
+ 	select GENERIC_ALLOCATOR
+-	select PHYLIB
+ 	select PHYLINK
+ 	select PCS
+ 	select PCS_LYNX
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -17,6 +17,7 @@
+ #include <linux/crc32.h>
+ #include <linux/of_mdio.h>
+ #include <linux/mii.h>
++#include <linux/netdevice.h>
+ 
+ /* TBI register addresses */
+ #define MII_TBICON		0x11
+@@ -29,9 +30,6 @@
+ #define TBICON_CLK_SELECT	0x0020	/* Clock select */
+ #define TBICON_MI_MODE		0x0010	/* GMII mode (TBI if not set) */
+ 
+-#define TBIANA_SGMII		0x4001
+-#define TBIANA_1000X		0x01a0
+-
+ /* Interrupt Mask Register (IMASK) */
+ #define DTSEC_IMASK_BREN	0x80000000
+ #define DTSEC_IMASK_RXCEN	0x40000000
+@@ -92,9 +90,10 @@
+ 
+ #define DTSEC_ECNTRL_GMIIM		0x00000040
+ #define DTSEC_ECNTRL_TBIM		0x00000020
+-#define DTSEC_ECNTRL_SGMIIM		0x00000002
+ #define DTSEC_ECNTRL_RPM		0x00000010
+ #define DTSEC_ECNTRL_R100M		0x00000008
++#define DTSEC_ECNTRL_RMM		0x00000004
++#define DTSEC_ECNTRL_SGMIIM		0x00000002
+ #define DTSEC_ECNTRL_QSGMIIM		0x00000001
+ 
+ #define TCTRL_TTSE			0x00000040
+@@ -318,7 +317,8 @@ struct fman_mac {
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+ 	bool basex_if;
+-	struct phy_device *tbiphy;
++	struct mdio_device *tbidev;
++	struct phylink_pcs pcs;
+ };
+ 
+ static void set_dflts(struct dtsec_cfg *cfg)
+@@ -356,56 +356,14 @@ static int init(struct dtsec_regs __iome
+ 		phy_interface_t iface, u16 iface_speed, u64 addr,
+ 		u32 exception_mask, u8 tbi_addr)
+ {
+-	bool is_rgmii, is_sgmii, is_qsgmii;
+ 	enet_addr_t eth_addr;
+-	u32 tmp;
++	u32 tmp = 0;
+ 	int i;
+ 
+ 	/* Soft reset */
+ 	iowrite32be(MACCFG1_SOFT_RESET, &regs->maccfg1);
+ 	iowrite32be(0, &regs->maccfg1);
+ 
+-	/* dtsec_id2 */
+-	tmp = ioread32be(&regs->tsec_id2);
+-
+-	/* check RGMII support */
+-	if (iface == PHY_INTERFACE_MODE_RGMII ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_ID ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+-	    iface == PHY_INTERFACE_MODE_RGMII_TXID ||
+-	    iface == PHY_INTERFACE_MODE_RMII)
+-		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+-			return -EINVAL;
+-
+-	if (iface == PHY_INTERFACE_MODE_SGMII ||
+-	    iface == PHY_INTERFACE_MODE_MII)
+-		if (tmp & DTSEC_ID2_INT_REDUCED_OFF)
+-			return -EINVAL;
+-
+-	is_rgmii = iface == PHY_INTERFACE_MODE_RGMII ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_ID ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_RXID ||
+-		   iface == PHY_INTERFACE_MODE_RGMII_TXID;
+-	is_sgmii = iface == PHY_INTERFACE_MODE_SGMII;
+-	is_qsgmii = iface == PHY_INTERFACE_MODE_QSGMII;
+-
+-	tmp = 0;
+-	if (is_rgmii || iface == PHY_INTERFACE_MODE_GMII)
+-		tmp |= DTSEC_ECNTRL_GMIIM;
+-	if (is_sgmii)
+-		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM);
+-	if (is_qsgmii)
+-		tmp |= (DTSEC_ECNTRL_SGMIIM | DTSEC_ECNTRL_TBIM |
+-			DTSEC_ECNTRL_QSGMIIM);
+-	if (is_rgmii)
+-		tmp |= DTSEC_ECNTRL_RPM;
+-	if (iface_speed == SPEED_100)
+-		tmp |= DTSEC_ECNTRL_R100M;
+-
+-	iowrite32be(tmp, &regs->ecntrl);
+-
+-	tmp = 0;
+-
+ 	if (cfg->tx_pause_time)
+ 		tmp |= cfg->tx_pause_time;
+ 	if (cfg->tx_pause_time_extd)
+@@ -446,17 +404,10 @@ static int init(struct dtsec_regs __iome
+ 
+ 	tmp = 0;
+ 
+-	if (iface_speed < SPEED_1000)
+-		tmp |= MACCFG2_NIBBLE_MODE;
+-	else if (iface_speed == SPEED_1000)
+-		tmp |= MACCFG2_BYTE_MODE;
+-
+ 	tmp |= (cfg->preamble_len << MACCFG2_PREAMBLE_LENGTH_SHIFT) &
+ 		MACCFG2_PREAMBLE_LENGTH_MASK;
+ 	if (cfg->tx_pad_crc)
+ 		tmp |= MACCFG2_PAD_CRC_EN;
+-	/* Full Duplex */
+-	tmp |= MACCFG2_FULL_DUPLEX;
+ 	iowrite32be(tmp, &regs->maccfg2);
+ 
+ 	tmp = (((cfg->non_back_to_back_ipg1 <<
+@@ -525,10 +476,6 @@ static void set_bucket(struct dtsec_regs
+ 
+ static int check_init_parameters(struct fman_mac *dtsec)
+ {
+-	if (dtsec->max_speed >= SPEED_10000) {
+-		pr_err("1G MAC driver supports 1G or lower speeds\n");
+-		return -EINVAL;
+-	}
+ 	if ((dtsec->dtsec_drv_param)->rx_prepend >
+ 	    MAX_PACKET_ALIGNMENT) {
+ 		pr_err("packetAlignmentPadding can't be > than %d\n",
+@@ -630,22 +577,10 @@ static int get_exception_flag(enum fman_
+ 	return bit_mask;
+ }
+ 
+-static bool is_init_done(struct dtsec_cfg *dtsec_drv_params)
+-{
+-	/* Checks if dTSEC driver parameters were initialized */
+-	if (!dtsec_drv_params)
+-		return true;
+-
+-	return false;
+-}
+-
+ static u16 dtsec_get_max_frame_length(struct fman_mac *dtsec)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 
+-	if (is_init_done(dtsec->dtsec_drv_param))
+-		return 0;
+-
+ 	return (u16)ioread32be(&regs->maxfrm);
+ }
+ 
+@@ -682,6 +617,7 @@ static void dtsec_isr(void *handle)
+ 		dtsec->exception_cb(dtsec->dev_id, FM_MAC_EX_1G_COL_RET_LMT);
+ 	if (event & DTSEC_IMASK_XFUNEN) {
+ 		/* FM_TX_LOCKUP_ERRATA_DTSEC6 Errata workaround */
++		/* FIXME: This races with the rest of the driver! */
+ 		if (dtsec->fm_rev_info.major == 2) {
+ 			u32 tpkt1, tmp_reg1, tpkt2, tmp_reg2, i;
+ 			/* a. Write 0x00E0_0C00 to DTSEC_ID
+@@ -814,6 +750,43 @@ static void free_init_resources(struct f
+ 	dtsec->unicast_addr_hash = NULL;
+ }
+ 
++static struct fman_mac *pcs_to_dtsec(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct fman_mac, pcs);
++}
++
++static void dtsec_pcs_get_state(struct phylink_pcs *pcs,
++				struct phylink_link_state *state)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
++}
++
++static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++			    phy_interface_t interface,
++			    const unsigned long *advertising,
++			    bool permit_pause_to_mac)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
++					  advertising);
++}
++
++static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
++{
++	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
++
++	phylink_mii_c22_pcs_an_restart(dtsec->tbidev);
++}
++
++static const struct phylink_pcs_ops dtsec_pcs_ops = {
++	.pcs_get_state = dtsec_pcs_get_state,
++	.pcs_config = dtsec_pcs_config,
++	.pcs_an_restart = dtsec_pcs_an_restart,
++};
++
+ static void graceful_start(struct fman_mac *dtsec)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+@@ -854,36 +827,11 @@ static void graceful_stop(struct fman_ma
+ 
+ static int dtsec_enable(struct fman_mac *dtsec)
+ {
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	/* Enable */
+-	tmp = ioread32be(&regs->maccfg1);
+-	tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
+-	iowrite32be(tmp, &regs->maccfg1);
+-
+-	/* Graceful start - clear the graceful Rx/Tx stop bit */
+-	graceful_start(dtsec);
+-
+ 	return 0;
+ }
+ 
+ static void dtsec_disable(struct fman_mac *dtsec)
+ {
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(dtsec->dtsec_drv_param));
+-
+-	/* Graceful stop - Assert the graceful Rx/Tx stop bit */
+-	graceful_stop(dtsec);
+-
+-	tmp = ioread32be(&regs->maccfg1);
+-	tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
+-	iowrite32be(tmp, &regs->maccfg1);
+ }
+ 
+ static int dtsec_set_tx_pause_frames(struct fman_mac *dtsec,
+@@ -894,11 +842,6 @@ static int dtsec_set_tx_pause_frames(str
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 ptv = 0;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+ 	if (pause_time) {
+ 		/* FM_BAD_TX_TS_IN_B_2_B_ERRATA_DTSEC_A003 Errata workaround */
+ 		if (dtsec->fm_rev_info.major == 2 && pause_time <= 320) {
+@@ -919,8 +862,6 @@ static int dtsec_set_tx_pause_frames(str
+ 		iowrite32be(ioread32be(&regs->maccfg1) & ~MACCFG1_TX_FLOW,
+ 			    &regs->maccfg1);
+ 
+-	graceful_start(dtsec);
+-
+ 	return 0;
+ }
+ 
+@@ -929,11 +870,6 @@ static int dtsec_accept_rx_pause_frames(
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+ 	tmp = ioread32be(&regs->maccfg1);
+ 	if (en)
+ 		tmp |= MACCFG1_RX_FLOW;
+@@ -941,17 +877,125 @@ static int dtsec_accept_rx_pause_frames(
+ 		tmp &= ~MACCFG1_RX_FLOW;
+ 	iowrite32be(tmp, &regs->maccfg1);
+ 
++	return 0;
++}
++
++static struct phylink_pcs *dtsec_select_pcs(struct phylink_config *config,
++					    phy_interface_t iface)
++{
++	struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		return &dtsec->pcs;
++	default:
++		return NULL;
++	}
++}
++
++static void dtsec_mac_config(struct phylink_config *config, unsigned int mode,
++			     const struct phylink_link_state *state)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct dtsec_regs __iomem *regs = mac_dev->fman_mac->regs;
++	u32 tmp;
++
++	switch (state->interface) {
++	case PHY_INTERFACE_MODE_RMII:
++		tmp = DTSEC_ECNTRL_RMM;
++		break;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++		tmp = DTSEC_ECNTRL_GMIIM | DTSEC_ECNTRL_RPM;
++		break;
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		tmp = DTSEC_ECNTRL_TBIM | DTSEC_ECNTRL_SGMIIM;
++		break;
++	default:
++		dev_warn(mac_dev->dev, "cannot configure dTSEC for %s\n",
++			 phy_modes(state->interface));
++		return;
++	}
++
++	iowrite32be(tmp, &regs->ecntrl);
++}
++
++static void dtsec_link_up(struct phylink_config *config, struct phy_device *phy,
++			  unsigned int mode, phy_interface_t interface,
++			  int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *dtsec = mac_dev->fman_mac;
++	struct dtsec_regs __iomem *regs = dtsec->regs;
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++	u32 tmp;
++
++	dtsec_set_tx_pause_frames(dtsec, 0, pause_time, 0);
++	dtsec_accept_rx_pause_frames(dtsec, rx_pause);
++
++	tmp = ioread32be(&regs->ecntrl);
++	if (speed == SPEED_100)
++		tmp |= DTSEC_ECNTRL_R100M;
++	else
++		tmp &= ~DTSEC_ECNTRL_R100M;
++	iowrite32be(tmp, &regs->ecntrl);
++
++	tmp = ioread32be(&regs->maccfg2);
++	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE | MACCFG2_FULL_DUPLEX);
++	if (speed >= SPEED_1000)
++		tmp |= MACCFG2_BYTE_MODE;
++	else
++		tmp |= MACCFG2_NIBBLE_MODE;
++
++	if (duplex == DUPLEX_FULL)
++		tmp |= MACCFG2_FULL_DUPLEX;
++
++	iowrite32be(tmp, &regs->maccfg2);
++
++	mac_dev->update_speed(mac_dev, speed);
++
++	/* Enable */
++	tmp = ioread32be(&regs->maccfg1);
++	tmp |= MACCFG1_RX_EN | MACCFG1_TX_EN;
++	iowrite32be(tmp, &regs->maccfg1);
++
++	/* Graceful start - clear the graceful Rx/Tx stop bit */
+ 	graceful_start(dtsec);
++}
+ 
+-	return 0;
++static void dtsec_link_down(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct fman_mac *dtsec = fman_config_to_mac(config)->fman_mac;
++	struct dtsec_regs __iomem *regs = dtsec->regs;
++	u32 tmp;
++
++	/* Graceful stop - Assert the graceful Rx/Tx stop bit */
++	graceful_stop(dtsec);
++
++	tmp = ioread32be(&regs->maccfg1);
++	tmp &= ~(MACCFG1_RX_EN | MACCFG1_TX_EN);
++	iowrite32be(tmp, &regs->maccfg1);
+ }
+ 
++static const struct phylink_mac_ops dtsec_mac_ops = {
++	.validate = phylink_generic_validate,
++	.mac_select_pcs = dtsec_select_pcs,
++	.mac_config = dtsec_mac_config,
++	.mac_link_up = dtsec_link_up,
++	.mac_link_down = dtsec_link_down,
++};
++
+ static int dtsec_modify_mac_address(struct fman_mac *dtsec,
+ 				    const enet_addr_t *enet_addr)
+ {
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	graceful_stop(dtsec);
+ 
+ 	/* Initialize MAC Station Address registers (1 & 2)
+@@ -975,9 +1019,6 @@ static int dtsec_add_hash_mac_address(st
+ 	u32 crc = 0xFFFFFFFF;
+ 	bool mcast, ghtx;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
+@@ -1037,9 +1078,6 @@ static int dtsec_set_allmulti(struct fma
+ 	u32 tmp;
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->rctrl);
+ 	if (enable)
+ 		tmp |= RCTRL_MPROM;
+@@ -1056,9 +1094,6 @@ static int dtsec_set_tstamp(struct fman_
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 rctrl, tctrl;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	rctrl = ioread32be(&regs->rctrl);
+ 	tctrl = ioread32be(&regs->tctrl);
+ 
+@@ -1087,9 +1122,6 @@ static int dtsec_del_hash_mac_address(st
+ 	u32 crc = 0xFFFFFFFF;
+ 	bool mcast, ghtx;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	ghtx = (bool)((ioread32be(&regs->rctrl) & RCTRL_GHTX) ? true : false);
+@@ -1153,9 +1185,6 @@ static int dtsec_set_promiscuous(struct
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	/* Set unicast promiscuous */
+ 	tmp = ioread32be(&regs->rctrl);
+ 	if (new_val)
+@@ -1177,90 +1206,12 @@ static int dtsec_set_promiscuous(struct
+ 	return 0;
+ }
+ 
+-static int dtsec_adjust_link(struct fman_mac *dtsec, u16 speed)
+-{
+-	struct dtsec_regs __iomem *regs = dtsec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	graceful_stop(dtsec);
+-
+-	tmp = ioread32be(&regs->maccfg2);
+-
+-	/* Full Duplex */
+-	tmp |= MACCFG2_FULL_DUPLEX;
+-
+-	tmp &= ~(MACCFG2_NIBBLE_MODE | MACCFG2_BYTE_MODE);
+-	if (speed < SPEED_1000)
+-		tmp |= MACCFG2_NIBBLE_MODE;
+-	else if (speed == SPEED_1000)
+-		tmp |= MACCFG2_BYTE_MODE;
+-	iowrite32be(tmp, &regs->maccfg2);
+-
+-	tmp = ioread32be(&regs->ecntrl);
+-	if (speed == SPEED_100)
+-		tmp |= DTSEC_ECNTRL_R100M;
+-	else
+-		tmp &= ~DTSEC_ECNTRL_R100M;
+-	iowrite32be(tmp, &regs->ecntrl);
+-
+-	graceful_start(dtsec);
+-
+-	return 0;
+-}
+-
+-static int dtsec_restart_autoneg(struct fman_mac *dtsec)
+-{
+-	u16 tmp_reg16;
+-
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+-	tmp_reg16 = phy_read(dtsec->tbiphy, MII_BMCR);
+-
+-	tmp_reg16 &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
+-	tmp_reg16 |= (BMCR_ANENABLE | BMCR_ANRESTART |
+-		      BMCR_FULLDPLX | BMCR_SPEED1000);
+-
+-	phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-
+-	return 0;
+-}
+-
+-static void adjust_link_dtsec(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	struct fman_mac *fman_mac;
+-	bool rx_pause, tx_pause;
+-	int err;
+-
+-	fman_mac = mac_dev->fman_mac;
+-	if (!phy_dev->link) {
+-		dtsec_restart_autoneg(fman_mac);
+-
+-		return;
+-	}
+-
+-	dtsec_adjust_link(fman_mac, phy_dev->speed);
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
+-			err);
+-}
+-
+ static int dtsec_set_exception(struct fman_mac *dtsec,
+ 			       enum fman_mac_exceptions exception, bool enable)
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	if (exception != FM_MAC_EX_1G_1588_TS_RX_ERR) {
+ 		bit_mask = get_exception_flag(exception);
+ 		if (bit_mask) {
+@@ -1310,12 +1261,9 @@ static int dtsec_init(struct fman_mac *d
+ {
+ 	struct dtsec_regs __iomem *regs = dtsec->regs;
+ 	struct dtsec_cfg *dtsec_drv_param;
+-	u16 max_frm_ln;
++	u16 max_frm_ln, tbicon;
+ 	int err;
+ 
+-	if (is_init_done(dtsec->dtsec_drv_param))
+-		return -EINVAL;
+-
+ 	if (DEFAULT_RESET_ON_INIT &&
+ 	    (fman_reset_mac(dtsec->fm, dtsec->mac_id) != 0)) {
+ 		pr_err("Can't reset MAC!\n");
+@@ -1330,38 +1278,19 @@ static int dtsec_init(struct fman_mac *d
+ 
+ 	err = init(dtsec->regs, dtsec_drv_param, dtsec->phy_if,
+ 		   dtsec->max_speed, dtsec->addr, dtsec->exceptions,
+-		   dtsec->tbiphy->mdio.addr);
++		   dtsec->tbidev->addr);
+ 	if (err) {
+ 		free_init_resources(dtsec);
+ 		pr_err("DTSEC version doesn't support this i/f mode\n");
+ 		return err;
+ 	}
+ 
+-	if (dtsec->phy_if == PHY_INTERFACE_MODE_SGMII) {
+-		u16 tmp_reg16;
+-
+-		/* Configure the TBI PHY Control Register */
+-		tmp_reg16 = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
+-		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
+-
+-		tmp_reg16 = TBICON_CLK_SELECT;
+-		phy_write(dtsec->tbiphy, MII_TBICON, tmp_reg16);
+-
+-		tmp_reg16 = (BMCR_RESET | BMCR_ANENABLE |
+-			     BMCR_FULLDPLX | BMCR_SPEED1000);
+-		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-
+-		if (dtsec->basex_if)
+-			tmp_reg16 = TBIANA_1000X;
+-		else
+-			tmp_reg16 = TBIANA_SGMII;
+-		phy_write(dtsec->tbiphy, MII_ADVERTISE, tmp_reg16);
++	/* Configure the TBI PHY Control Register */
++	tbicon = TBICON_CLK_SELECT | TBICON_SOFT_RESET;
++	mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
+ 
+-		tmp_reg16 = (BMCR_ANENABLE | BMCR_ANRESTART |
+-			     BMCR_FULLDPLX | BMCR_SPEED1000);
+-
+-		phy_write(dtsec->tbiphy, MII_BMCR, tmp_reg16);
+-	}
++	tbicon = TBICON_CLK_SELECT;
++	mdiodev_write(dtsec->tbidev, MII_TBICON, tbicon);
+ 
+ 	/* Max Frame Length */
+ 	max_frm_ln = (u16)ioread32be(&regs->maxfrm);
+@@ -1406,6 +1335,8 @@ static int dtsec_free(struct fman_mac *d
+ 
+ 	kfree(dtsec->dtsec_drv_param);
+ 	dtsec->dtsec_drv_param = NULL;
++	if (!IS_ERR_OR_NULL(dtsec->tbidev))
++		put_device(&dtsec->tbidev->dev);
+ 	kfree(dtsec);
+ 
+ 	return 0;
+@@ -1434,7 +1365,6 @@ static struct fman_mac *dtsec_config(str
+ 
+ 	dtsec->regs = mac_dev->vaddr;
+ 	dtsec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+-	dtsec->max_speed = params->max_speed;
+ 	dtsec->phy_if = mac_dev->phy_if;
+ 	dtsec->mac_id = params->mac_id;
+ 	dtsec->exceptions = (DTSEC_IMASK_BREN	|
+@@ -1457,7 +1387,6 @@ static struct fman_mac *dtsec_config(str
+ 	dtsec->en_tsu_err_exception = dtsec->dtsec_drv_param->ptp_exception_en;
+ 
+ 	dtsec->fm = params->fm;
+-	dtsec->basex_if = params->basex_if;
+ 
+ 	/* Save FMan revision */
+ 	fman_get_revision(dtsec->fm, &dtsec->fm_rev_info);
+@@ -1476,18 +1405,18 @@ int dtsec_initialization(struct mac_devi
+ 	int			err;
+ 	struct fman_mac		*dtsec;
+ 	struct device_node	*phy_node;
++	unsigned long		 capabilities;
++	unsigned long		*supported;
+ 
++	mac_dev->phylink_ops		= &dtsec_mac_ops;
+ 	mac_dev->set_promisc		= dtsec_set_promiscuous;
+ 	mac_dev->change_addr		= dtsec_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= dtsec_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= dtsec_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= dtsec_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= dtsec_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= dtsec_set_exception;
+ 	mac_dev->set_allmulti		= dtsec_set_allmulti;
+ 	mac_dev->set_tstamp		= dtsec_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = adjust_link_dtsec;
+ 	mac_dev->enable			= dtsec_enable;
+ 	mac_dev->disable		= dtsec_disable;
+ 
+@@ -1502,19 +1431,56 @@ int dtsec_initialization(struct mac_devi
+ 	dtsec->dtsec_drv_param->tx_pad_crc = true;
+ 
+ 	phy_node = of_parse_phandle(mac_node, "tbi-handle", 0);
+-	if (!phy_node) {
+-		pr_err("TBI PHY node is not available\n");
++	if (!phy_node || of_device_is_available(phy_node)) {
++		of_node_put(phy_node);
+ 		err = -EINVAL;
++		dev_err_probe(mac_dev->dev, err,
++			      "TBI PCS node is not available\n");
+ 		goto _return_fm_mac_free;
+ 	}
+ 
+-	dtsec->tbiphy = of_phy_find_device(phy_node);
+-	if (!dtsec->tbiphy) {
+-		pr_err("of_phy_find_device (TBI PHY) failed\n");
+-		err = -EINVAL;
++	dtsec->tbidev = of_mdio_find_device(phy_node);
++	of_node_put(phy_node);
++	if (!dtsec->tbidev) {
++		err = -EPROBE_DEFER;
++		dev_err_probe(mac_dev->dev, err,
++			      "could not find mdiodev for PCS\n");
+ 		goto _return_fm_mac_free;
+ 	}
+-	put_device(&dtsec->tbiphy->mdio.dev);
++	dtsec->pcs.ops = &dtsec_pcs_ops;
++	dtsec->pcs.poll = true;
++
++	supported = mac_dev->phylink_config.supported_interfaces;
++
++	/* FIXME: Can we use DTSEC_ID2_INT_FULL_OFF to determine if these are
++	 * supported? If not, we can determine support via the phy if SerDes
++	 * support is added.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII ||
++	    mac_dev->phy_if == PHY_INTERFACE_MODE_1000BASEX) {
++		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
++		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
++	} else if (mac_dev->phy_if == PHY_INTERFACE_MODE_2500BASEX) {
++		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
++	}
++
++	if (!(ioread32be(&dtsec->regs->tsec_id2) & DTSEC_ID2_INT_REDUCED_OFF)) {
++		phy_interface_set_rgmii(supported);
++
++		/* DTSEC_ID2_INT_REDUCED_OFF indicates that the dTSEC supports
++		 * RMII and RGMII. However, the only SoCs which support RMII
++		 * are the P1017 and P1023. Avoid advertising this mode on
++		 * other SoCs. This is a bit of a moot point, since there's no
++		 * in-tree support for ethernet on these platforms...
++		 */
++		if (of_machine_is_compatible("fsl,P1023") ||
++		    of_machine_is_compatible("fsl,P1023RDB"))
++			__set_bit(PHY_INTERFACE_MODE_RMII, supported);
++	}
++
++	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
++	capabilities |= MAC_10 | MAC_100 | MAC_1000FD | MAC_2500FD;
++	mac_dev->phylink_config.mac_capabilities = capabilities;
+ 
+ 	err = dtsec_init(dtsec);
+ 	if (err < 0)
+--- a/drivers/net/ethernet/freescale/fman/fman_mac.h
++++ b/drivers/net/ethernet/freescale/fman/fman_mac.h
+@@ -170,20 +170,10 @@ struct fman_mac_params {
+ 	 * 0 - FM_MAX_NUM_OF_10G_MACS
+ 	 */
+ 	u8 mac_id;
+-	/* Note that the speed should indicate the maximum rate that
+-	 * this MAC should support rather than the actual speed;
+-	 */
+-	u16 max_speed;
+ 	/* A handle to the FM object this port related to */
+ 	void *fm;
+ 	fman_mac_exception_cb *event_cb;    /* MDIO Events Callback Routine */
+ 	fman_mac_exception_cb *exception_cb;/* Exception Callback Routine */
+-	/* SGMII/QSGII interface with 1000BaseX auto-negotiation between MAC
+-	 * and phy or backplane; Note: 1000BaseX auto-negotiation relates only
+-	 * to interface between MAC and phy/backplane, SGMII phy can still
+-	 * synchronize with far-end phy at 10Mbps, 100Mbps or 1000Mbps
+-	*/
+-	bool basex_if;
+ };
+ 
+ struct eth_hash_t {
+--- a/drivers/net/ethernet/freescale/fman/fman_memac.c
++++ b/drivers/net/ethernet/freescale/fman/fman_memac.c
+@@ -278,9 +278,6 @@ struct fman_mac {
+ 	struct memac_regs __iomem *regs;
+ 	/* MAC address of device */
+ 	u64 addr;
+-	/* Ethernet physical interface */
+-	phy_interface_t phy_if;
+-	u16 max_speed;
+ 	struct mac_device *dev_id; /* device cookie used by the exception cbs */
+ 	fman_mac_exception_cb *exception_cb;
+ 	fman_mac_exception_cb *event_cb;
+@@ -293,12 +290,12 @@ struct fman_mac {
+ 	struct memac_cfg *memac_drv_param;
+ 	void *fm;
+ 	struct fman_rev_info fm_rev_info;
+-	bool basex_if;
+ 	struct phy *serdes;
+ 	struct phylink_pcs *sgmii_pcs;
+ 	struct phylink_pcs *qsgmii_pcs;
+ 	struct phylink_pcs *xfi_pcs;
+ 	bool allmulti_enabled;
++	bool rgmii_no_half_duplex;
+ };
+ 
+ static void add_addr_in_paddr(struct memac_regs __iomem *regs, const u8 *adr,
+@@ -356,7 +353,6 @@ static void set_exception(struct memac_r
+ }
+ 
+ static int init(struct memac_regs __iomem *regs, struct memac_cfg *cfg,
+-		phy_interface_t phy_if, u16 speed, bool slow_10g_if,
+ 		u32 exceptions)
+ {
+ 	u32 tmp;
+@@ -384,41 +380,6 @@ static int init(struct memac_regs __iome
+ 	iowrite32be((u32)cfg->pause_quanta, &regs->pause_quanta[0]);
+ 	iowrite32be((u32)0, &regs->pause_thresh[0]);
+ 
+-	/* IF_MODE */
+-	tmp = 0;
+-	switch (phy_if) {
+-	case PHY_INTERFACE_MODE_XGMII:
+-		tmp |= IF_MODE_10G;
+-		break;
+-	case PHY_INTERFACE_MODE_MII:
+-		tmp |= IF_MODE_MII;
+-		break;
+-	default:
+-		tmp |= IF_MODE_GMII;
+-		if (phy_if == PHY_INTERFACE_MODE_RGMII ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_ID ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_RXID ||
+-		    phy_if == PHY_INTERFACE_MODE_RGMII_TXID)
+-			tmp |= IF_MODE_RGMII | IF_MODE_RGMII_AUTO;
+-	}
+-	iowrite32be(tmp, &regs->if_mode);
+-
+-	/* TX_FIFO_SECTIONS */
+-	tmp = 0;
+-	if (phy_if == PHY_INTERFACE_MODE_XGMII) {
+-		if (slow_10g_if) {
+-			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G |
+-				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+-		} else {
+-			tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_10G |
+-				TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G);
+-		}
+-	} else {
+-		tmp |= (TX_FIFO_SECTIONS_TX_AVAIL_1G |
+-			TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G);
+-	}
+-	iowrite32be(tmp, &regs->tx_fifo_sections);
+-
+ 	/* clear all pending events and set-up interrupts */
+ 	iowrite32be(0xffffffff, &regs->ievent);
+ 	set_exception(regs, exceptions, true);
+@@ -458,24 +419,6 @@ static u32 get_mac_addr_hash_code(u64 et
+ 	return xor_val;
+ }
+ 
+-static void setup_sgmii_internal(struct fman_mac *memac,
+-				 struct phylink_pcs *pcs,
+-				 struct fixed_phy_status *fixed_link)
+-{
+-	__ETHTOOL_DECLARE_LINK_MODE_MASK(advertising);
+-	phy_interface_t iface = memac->basex_if ? PHY_INTERFACE_MODE_1000BASEX :
+-				PHY_INTERFACE_MODE_SGMII;
+-	unsigned int mode = fixed_link ? MLO_AN_FIXED : MLO_AN_INBAND;
+-
+-	linkmode_set_pause(advertising, true, true);
+-	pcs->ops->pcs_config(pcs, mode, iface, advertising, true);
+-	if (fixed_link)
+-		pcs->ops->pcs_link_up(pcs, mode, iface, fixed_link->speed,
+-				      fixed_link->duplex);
+-	else
+-		pcs->ops->pcs_an_restart(pcs);
+-}
+-
+ static int check_init_parameters(struct fman_mac *memac)
+ {
+ 	if (!memac->exception_cb) {
+@@ -581,41 +524,31 @@ static void free_init_resources(struct f
+ 	memac->unicast_addr_hash = NULL;
+ }
+ 
+-static bool is_init_done(struct memac_cfg *memac_drv_params)
+-{
+-	/* Checks if mEMAC driver parameters were initialized */
+-	if (!memac_drv_params)
+-		return true;
+-
+-	return false;
+-}
+-
+ static int memac_enable(struct fman_mac *memac)
+ {
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
++	int ret;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
++	ret = phy_init(memac->serdes);
++	if (ret) {
++		dev_err(memac->dev_id->dev,
++			"could not initialize serdes: %pe\n", ERR_PTR(ret));
++		return ret;
++	}
+ 
+-	tmp = ioread32be(&regs->command_config);
+-	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
+-	iowrite32be(tmp, &regs->command_config);
++	ret = phy_power_on(memac->serdes);
++	if (ret) {
++		dev_err(memac->dev_id->dev,
++			"could not power on serdes: %pe\n", ERR_PTR(ret));
++		phy_exit(memac->serdes);
++	}
+ 
+-	return 0;
++	return ret;
+ }
+ 
+ static void memac_disable(struct fman_mac *memac)
+-
+ {
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(memac->memac_drv_param));
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
+-	iowrite32be(tmp, &regs->command_config);
++	phy_power_off(memac->serdes);
++	phy_exit(memac->serdes);
+ }
+ 
+ static int memac_set_promiscuous(struct fman_mac *memac, bool new_val)
+@@ -623,9 +556,6 @@ static int memac_set_promiscuous(struct
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (new_val)
+ 		tmp |= CMD_CFG_PROMIS_EN;
+@@ -637,73 +567,12 @@ static int memac_set_promiscuous(struct
+ 	return 0;
+ }
+ 
+-static int memac_adjust_link(struct fman_mac *memac, u16 speed)
+-{
+-	struct memac_regs __iomem *regs = memac->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+-	tmp = ioread32be(&regs->if_mode);
+-
+-	/* Set full duplex */
+-	tmp &= ~IF_MODE_HD;
+-
+-	if (phy_interface_mode_is_rgmii(memac->phy_if)) {
+-		/* Configure RGMII in manual mode */
+-		tmp &= ~IF_MODE_RGMII_AUTO;
+-		tmp &= ~IF_MODE_RGMII_SP_MASK;
+-		/* Full duplex */
+-		tmp |= IF_MODE_RGMII_FD;
+-
+-		switch (speed) {
+-		case SPEED_1000:
+-			tmp |= IF_MODE_RGMII_1000;
+-			break;
+-		case SPEED_100:
+-			tmp |= IF_MODE_RGMII_100;
+-			break;
+-		case SPEED_10:
+-			tmp |= IF_MODE_RGMII_10;
+-			break;
+-		default:
+-			break;
+-		}
+-	}
+-
+-	iowrite32be(tmp, &regs->if_mode);
+-
+-	return 0;
+-}
+-
+-static void adjust_link_memac(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	struct fman_mac *fman_mac;
+-	bool rx_pause, tx_pause;
+-	int err;
+-
+-	fman_mac = mac_dev->fman_mac;
+-	memac_adjust_link(fman_mac, phy_dev->speed);
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-
+-	fman_get_pause_cfg(mac_dev, &rx_pause, &tx_pause);
+-	err = fman_set_mac_active_pause(mac_dev, rx_pause, tx_pause);
+-	if (err < 0)
+-		dev_err(mac_dev->dev, "fman_set_mac_active_pause() = %d\n",
+-			err);
+-}
+-
+ static int memac_set_tx_pause_frames(struct fman_mac *memac, u8 priority,
+ 				     u16 pause_time, u16 thresh_time)
+ {
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->tx_fifo_sections);
+ 
+ 	GET_TX_EMPTY_DEFAULT_VALUE(tmp);
+@@ -738,9 +607,6 @@ static int memac_accept_rx_pause_frames(
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (en)
+ 		tmp &= ~CMD_CFG_PAUSE_IGNORE;
+@@ -752,12 +618,175 @@ static int memac_accept_rx_pause_frames(
+ 	return 0;
+ }
+ 
++static void memac_validate(struct phylink_config *config,
++			   unsigned long *supported,
++			   struct phylink_link_state *state)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++	unsigned long caps = config->mac_capabilities;
++
++	if (phy_interface_mode_is_rgmii(state->interface) &&
++	    memac->rgmii_no_half_duplex)
++		caps &= ~(MAC_10HD | MAC_100HD);
++
++	phylink_validate_mask_caps(supported, state, caps);
++}
++
++/**
++ * memac_if_mode() - Convert an interface mode into an IF_MODE config
++ * @interface: A phy interface mode
++ *
++ * Return: A configuration word, suitable for programming into the lower bits
++ *         of %IF_MODE.
++ */
++static u32 memac_if_mode(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_MII:
++		return IF_MODE_MII;
++	case PHY_INTERFACE_MODE_RGMII:
++	case PHY_INTERFACE_MODE_RGMII_ID:
++	case PHY_INTERFACE_MODE_RGMII_RXID:
++	case PHY_INTERFACE_MODE_RGMII_TXID:
++		return IF_MODE_GMII | IF_MODE_RGMII;
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_QSGMII:
++		return IF_MODE_GMII;
++	case PHY_INTERFACE_MODE_10GBASER:
++		return IF_MODE_10G;
++	default:
++		WARN_ON_ONCE(1);
++		return 0;
++	}
++}
++
++static struct phylink_pcs *memac_select_pcs(struct phylink_config *config,
++					    phy_interface_t iface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++		return memac->sgmii_pcs;
++	case PHY_INTERFACE_MODE_QSGMII:
++		return memac->qsgmii_pcs;
++	case PHY_INTERFACE_MODE_10GBASER:
++		return memac->xfi_pcs;
++	default:
++		return NULL;
++	}
++}
++
++static int memac_prepare(struct phylink_config *config, unsigned int mode,
++			 phy_interface_t iface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_10GBASER:
++		return phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
++					iface);
++	default:
++		return 0;
++	}
++}
++
++static void memac_mac_config(struct phylink_config *config, unsigned int mode,
++			     const struct phylink_link_state *state)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct memac_regs __iomem *regs = mac_dev->fman_mac->regs;
++	u32 tmp = ioread32be(&regs->if_mode);
++
++	tmp &= ~(IF_MODE_MASK | IF_MODE_RGMII);
++	tmp |= memac_if_mode(state->interface);
++	if (phylink_autoneg_inband(mode))
++		tmp |= IF_MODE_RGMII_AUTO;
++	iowrite32be(tmp, &regs->if_mode);
++}
++
++static void memac_link_up(struct phylink_config *config, struct phy_device *phy,
++			  unsigned int mode, phy_interface_t interface,
++			  int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *memac = mac_dev->fman_mac;
++	struct memac_regs __iomem *regs = memac->regs;
++	u32 tmp = memac_if_mode(interface);
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++
++	memac_set_tx_pause_frames(memac, 0, pause_time, 0);
++	memac_accept_rx_pause_frames(memac, rx_pause);
++
++	if (duplex == DUPLEX_HALF)
++		tmp |= IF_MODE_HD;
++
++	switch (speed) {
++	case SPEED_1000:
++		tmp |= IF_MODE_RGMII_1000;
++		break;
++	case SPEED_100:
++		tmp |= IF_MODE_RGMII_100;
++		break;
++	case SPEED_10:
++		tmp |= IF_MODE_RGMII_10;
++		break;
++	}
++	iowrite32be(tmp, &regs->if_mode);
++
++	/* TODO: EEE? */
++
++	if (speed == SPEED_10000) {
++		if (memac->fm_rev_info.major == 6 &&
++		    memac->fm_rev_info.minor == 4)
++			tmp = TX_FIFO_SECTIONS_TX_AVAIL_SLOW_10G;
++		else
++			tmp = TX_FIFO_SECTIONS_TX_AVAIL_10G;
++		tmp |= TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_10G;
++	} else {
++		tmp = TX_FIFO_SECTIONS_TX_AVAIL_1G |
++		      TX_FIFO_SECTIONS_TX_EMPTY_DEFAULT_1G;
++	}
++	iowrite32be(tmp, &regs->tx_fifo_sections);
++
++	mac_dev->update_speed(mac_dev, speed);
++
++	tmp = ioread32be(&regs->command_config);
++	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static void memac_link_down(struct phylink_config *config, unsigned int mode,
++			    phy_interface_t interface)
++{
++	struct fman_mac *memac = fman_config_to_mac(config)->fman_mac;
++	struct memac_regs __iomem *regs = memac->regs;
++	u32 tmp;
++
++	/* TODO: graceful */
++	tmp = ioread32be(&regs->command_config);
++	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static const struct phylink_mac_ops memac_mac_ops = {
++	.validate = memac_validate,
++	.mac_select_pcs = memac_select_pcs,
++	.mac_prepare = memac_prepare,
++	.mac_config = memac_mac_config,
++	.mac_link_up = memac_link_up,
++	.mac_link_down = memac_link_down,
++};
++
+ static int memac_modify_mac_address(struct fman_mac *memac,
+ 				    const enet_addr_t *enet_addr)
+ {
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	add_addr_in_paddr(memac->regs, (const u8 *)(*enet_addr), 0);
+ 
+ 	return 0;
+@@ -771,9 +800,6 @@ static int memac_add_hash_mac_address(st
+ 	u32 hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	if (!(addr & GROUP_ADDRESS)) {
+@@ -802,9 +828,6 @@ static int memac_set_allmulti(struct fma
+ 	u32 entry;
+ 	struct memac_regs __iomem *regs = memac->regs;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	if (enable) {
+ 		for (entry = 0; entry < HASH_TABLE_SIZE; entry++)
+ 			iowrite32be(entry | HASH_CTRL_MCAST_EN,
+@@ -834,9 +857,6 @@ static int memac_del_hash_mac_address(st
+ 	u32 hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	hash = get_mac_addr_hash_code(addr) & HASH_CTRL_ADDR_MASK;
+@@ -864,9 +884,6 @@ static int memac_set_exception(struct fm
+ {
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	bit_mask = get_exception_flag(exception);
+ 	if (bit_mask) {
+ 		if (enable)
+@@ -886,23 +903,15 @@ static int memac_init(struct fman_mac *m
+ {
+ 	struct memac_cfg *memac_drv_param;
+ 	enet_addr_t eth_addr;
+-	bool slow_10g_if = false;
+-	struct fixed_phy_status *fixed_link = NULL;
+ 	int err;
+ 	u32 reg32 = 0;
+ 
+-	if (is_init_done(memac->memac_drv_param))
+-		return -EINVAL;
+-
+ 	err = check_init_parameters(memac);
+ 	if (err)
+ 		return err;
+ 
+ 	memac_drv_param = memac->memac_drv_param;
+ 
+-	if (memac->fm_rev_info.major == 6 && memac->fm_rev_info.minor == 4)
+-		slow_10g_if = true;
+-
+ 	/* First, reset the MAC if desired. */
+ 	if (memac_drv_param->reset_on_init) {
+ 		err = reset(memac->regs);
+@@ -918,10 +927,7 @@ static int memac_init(struct fman_mac *m
+ 		add_addr_in_paddr(memac->regs, (const u8 *)eth_addr, 0);
+ 	}
+ 
+-	fixed_link = memac_drv_param->fixed_link;
+-
+-	init(memac->regs, memac->memac_drv_param, memac->phy_if,
+-	     memac->max_speed, slow_10g_if, memac->exceptions);
++	init(memac->regs, memac->memac_drv_param, memac->exceptions);
+ 
+ 	/* FM_RX_FIFO_CORRUPT_ERRATA_10GMAC_A006320 errata workaround
+ 	 * Exists only in FMan 6.0 and 6.3.
+@@ -937,11 +943,6 @@ static int memac_init(struct fman_mac *m
+ 		iowrite32be(reg32, &memac->regs->command_config);
+ 	}
+ 
+-	if (memac->phy_if == PHY_INTERFACE_MODE_SGMII)
+-		setup_sgmii_internal(memac, memac->sgmii_pcs, fixed_link);
+-	else if (memac->phy_if == PHY_INTERFACE_MODE_QSGMII)
+-		setup_sgmii_internal(memac, memac->qsgmii_pcs, fixed_link);
+-
+ 	/* Max Frame Length */
+ 	err = fman_set_mac_max_frame(memac->fm, memac->mac_id,
+ 				     memac_drv_param->max_frame_length);
+@@ -970,9 +971,6 @@ static int memac_init(struct fman_mac *m
+ 	fman_register_intr(memac->fm, FMAN_MOD_MAC, memac->mac_id,
+ 			   FMAN_INTR_TYPE_NORMAL, memac_exception, memac);
+ 
+-	kfree(memac_drv_param);
+-	memac->memac_drv_param = NULL;
+-
+ 	return 0;
+ }
+ 
+@@ -995,7 +993,6 @@ static int memac_free(struct fman_mac *m
+ 	pcs_put(memac->sgmii_pcs);
+ 	pcs_put(memac->qsgmii_pcs);
+ 	pcs_put(memac->xfi_pcs);
+-
+ 	kfree(memac->memac_drv_param);
+ 	kfree(memac);
+ 
+@@ -1028,8 +1025,6 @@ static struct fman_mac *memac_config(str
+ 	memac->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+ 
+ 	memac->regs = mac_dev->vaddr;
+-	memac->max_speed = params->max_speed;
+-	memac->phy_if = mac_dev->phy_if;
+ 	memac->mac_id = params->mac_id;
+ 	memac->exceptions = (MEMAC_IMASK_TSECC_ER | MEMAC_IMASK_TECC_ER |
+ 			     MEMAC_IMASK_RECC_ER | MEMAC_IMASK_MGI);
+@@ -1037,7 +1032,6 @@ static struct fman_mac *memac_config(str
+ 	memac->event_cb = params->event_cb;
+ 	memac->dev_id = mac_dev;
+ 	memac->fm = params->fm;
+-	memac->basex_if = params->basex_if;
+ 
+ 	/* Save FMan revision */
+ 	fman_get_revision(memac->fm, &memac->fm_rev_info);
+@@ -1064,37 +1058,44 @@ static struct phylink_pcs *memac_pcs_cre
+ 	return pcs;
+ }
+ 
++static bool memac_supports(struct mac_device *mac_dev, phy_interface_t iface)
++{
++	/* If there's no serdes device, assume that it's been configured for
++	 * whatever the default interface mode is.
++	 */
++	if (!mac_dev->fman_mac->serdes)
++		return mac_dev->phy_if == iface;
++	/* Otherwise, ask the serdes */
++	return !phy_validate(mac_dev->fman_mac->serdes, PHY_MODE_ETHERNET,
++			     iface, NULL);
++}
++
+ int memac_initialization(struct mac_device *mac_dev,
+ 			 struct device_node *mac_node,
+ 			 struct fman_mac_params *params)
+ {
+ 	int			 err;
++	struct device_node      *fixed;
+ 	struct phylink_pcs	*pcs;
+-	struct fixed_phy_status *fixed_link;
+ 	struct fman_mac		*memac;
++	unsigned long		 capabilities;
++	unsigned long		*supported;
+ 
++	mac_dev->phylink_ops		= &memac_mac_ops;
+ 	mac_dev->set_promisc		= memac_set_promiscuous;
+ 	mac_dev->change_addr		= memac_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= memac_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= memac_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= memac_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= memac_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= memac_set_exception;
+ 	mac_dev->set_allmulti		= memac_set_allmulti;
+ 	mac_dev->set_tstamp		= memac_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = adjust_link_memac;
+ 	mac_dev->enable			= memac_enable;
+ 	mac_dev->disable		= memac_disable;
+ 
+-	if (params->max_speed == SPEED_10000)
+-		mac_dev->phy_if = PHY_INTERFACE_MODE_XGMII;
+-
+ 	mac_dev->fman_mac = memac_config(mac_dev, params);
+-	if (!mac_dev->fman_mac) {
+-		err = -EINVAL;
+-		goto _return;
+-	}
++	if (!mac_dev->fman_mac)
++		return -EINVAL;
+ 
+ 	memac = mac_dev->fman_mac;
+ 	memac->memac_drv_param->max_frame_length = fman_get_max_frm();
+@@ -1136,9 +1137,9 @@ int memac_initialization(struct mac_devi
+ 	else
+ 		pcs = memac_pcs_create(mac_node, err);
+ 
+-	if (!pcs) {
+-		dev_err(mac_dev->dev, "missing pcs\n");
+-		err = -ENOENT;
++	if (IS_ERR(pcs)) {
++		err = PTR_ERR(pcs);
++		dev_err_probe(mac_dev->dev, err, "missing pcs\n");
+ 		goto _return_fm_mac_free;
+ 	}
+ 
+@@ -1159,84 +1160,100 @@ int memac_initialization(struct mac_devi
+ 	} else if (IS_ERR(memac->serdes)) {
+ 		dev_err_probe(mac_dev->dev, err, "could not get serdes\n");
+ 		goto _return_fm_mac_free;
+-	} else {
+-		err = phy_init(memac->serdes);
+-		if (err) {
+-			dev_err_probe(mac_dev->dev, err,
+-				      "could not initialize serdes\n");
+-			goto _return_fm_mac_free;
+-		}
+-
+-		err = phy_power_on(memac->serdes);
+-		if (err) {
+-			dev_err_probe(mac_dev->dev, err,
+-				      "could not power on serdes\n");
+-			goto _return_phy_exit;
+-		}
+-
+-		if (memac->phy_if == PHY_INTERFACE_MODE_SGMII ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_1000BASEX ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_2500BASEX ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_QSGMII ||
+-		    memac->phy_if == PHY_INTERFACE_MODE_XGMII) {
+-			err = phy_set_mode_ext(memac->serdes, PHY_MODE_ETHERNET,
+-					       memac->phy_if);
+-			if (err) {
+-				dev_err_probe(mac_dev->dev, err,
+-					      "could not set serdes mode to %s\n",
+-					      phy_modes(memac->phy_if));
+-				goto _return_phy_power_off;
+-			}
+-		}
+ 	}
+ 
+-	if (!mac_dev->phy_node && of_phy_is_fixed_link(mac_node)) {
+-		struct phy_device *phy;
+-
+-		err = of_phy_register_fixed_link(mac_node);
+-		if (err)
+-			goto _return_phy_power_off;
+-
+-		fixed_link = kzalloc(sizeof(*fixed_link), GFP_KERNEL);
+-		if (!fixed_link) {
+-			err = -ENOMEM;
+-			goto _return_phy_power_off;
+-		}
++	/* The internal connection to the serdes is XGMII, but this isn't
++	 * really correct for the phy mode (which is the external connection).
++	 * However, this is how all older device trees say that they want
++	 * 10GBASE-R (aka XFI), so just convert it for them.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		mac_dev->phy_if = PHY_INTERFACE_MODE_10GBASER;
+ 
+-		mac_dev->phy_node = of_node_get(mac_node);
+-		phy = of_phy_find_device(mac_dev->phy_node);
+-		if (!phy) {
+-			err = -EINVAL;
+-			of_node_put(mac_dev->phy_node);
+-			goto _return_fixed_link_free;
+-		}
++	/* TODO: The following interface modes are supported by (some) hardware
++	 * but not by this driver:
++	 * - 1000BASE-KX
++	 * - 10GBASE-KR
++	 * - XAUI/HiGig
++	 */
++	supported = mac_dev->phylink_config.supported_interfaces;
+ 
+-		fixed_link->link = phy->link;
+-		fixed_link->speed = phy->speed;
+-		fixed_link->duplex = phy->duplex;
+-		fixed_link->pause = phy->pause;
+-		fixed_link->asym_pause = phy->asym_pause;
++	/* Note that half duplex is only supported on 10/100M interfaces. */
+ 
+-		put_device(&phy->mdio.dev);
+-		memac->memac_drv_param->fixed_link = fixed_link;
++	if (memac->sgmii_pcs &&
++	    (memac_supports(mac_dev, PHY_INTERFACE_MODE_SGMII) ||
++	     memac_supports(mac_dev, PHY_INTERFACE_MODE_1000BASEX))) {
++		__set_bit(PHY_INTERFACE_MODE_SGMII, supported);
++		__set_bit(PHY_INTERFACE_MODE_1000BASEX, supported);
++	}
++
++	if (memac->sgmii_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_2500BASEX))
++		__set_bit(PHY_INTERFACE_MODE_2500BASEX, supported);
++
++	if (memac->qsgmii_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_QSGMII))
++		__set_bit(PHY_INTERFACE_MODE_QSGMII, supported);
++	else if (mac_dev->phy_if == PHY_INTERFACE_MODE_QSGMII)
++		dev_warn(mac_dev->dev, "no QSGMII pcs specified\n");
++
++	if (memac->xfi_pcs &&
++	    memac_supports(mac_dev, PHY_INTERFACE_MODE_10GBASER)) {
++		__set_bit(PHY_INTERFACE_MODE_10GBASER, supported);
++	} else {
++		/* From what I can tell, no 10g macs support RGMII. */
++		phy_interface_set_rgmii(supported);
++		__set_bit(PHY_INTERFACE_MODE_MII, supported);
+ 	}
+ 
++	capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10 | MAC_100;
++	capabilities |= MAC_1000FD | MAC_2500FD | MAC_10000FD;
++
++	/* These SoCs don't support half duplex at all; there's no different
++	 * FMan version or compatible, so we just have to check the machine
++	 * compatible instead
++	 */
++	if (of_machine_is_compatible("fsl,ls1043a") ||
++	    of_machine_is_compatible("fsl,ls1046a") ||
++	    of_machine_is_compatible("fsl,B4QDS"))
++		capabilities &= ~(MAC_10HD | MAC_100HD);
++
++	mac_dev->phylink_config.mac_capabilities = capabilities;
++
++	/* The T2080 and T4240 don't support half duplex RGMII. There is no
++	 * other way to identify these SoCs, so just use the machine
++	 * compatible.
++	 */
++	if (of_machine_is_compatible("fsl,T2080QDS") ||
++	    of_machine_is_compatible("fsl,T2080RDB") ||
++	    of_machine_is_compatible("fsl,T2081QDS") ||
++	    of_machine_is_compatible("fsl,T4240QDS") ||
++	    of_machine_is_compatible("fsl,T4240RDB"))
++		memac->rgmii_no_half_duplex = true;
++
++	/* Most boards should use MLO_AN_INBAND, but existing boards don't have
++	 * a managed property. Default to MLO_AN_INBAND if nothing else is
++	 * specified. We need to be careful and not enable this if we have a
++	 * fixed link or if we are using MII or RGMII, since those
++	 * configurations modes don't use in-band autonegotiation.
++	 */
++	fixed = of_get_child_by_name(mac_node, "fixed-link");
++	if (!fixed && !of_property_read_bool(mac_node, "fixed-link") &&
++	    !of_property_read_bool(mac_node, "managed") &&
++	    mac_dev->phy_if != PHY_INTERFACE_MODE_MII &&
++	    !phy_interface_mode_is_rgmii(mac_dev->phy_if))
++		mac_dev->phylink_config.ovr_an_inband = true;
++	of_node_put(fixed);
++
+ 	err = memac_init(mac_dev->fman_mac);
+ 	if (err < 0)
+-		goto _return_fixed_link_free;
++		goto _return_fm_mac_free;
+ 
+ 	dev_info(mac_dev->dev, "FMan MEMAC\n");
+ 
+-	goto _return;
++	return 0;
+ 
+-_return_phy_power_off:
+-	phy_power_off(memac->serdes);
+-_return_phy_exit:
+-	phy_exit(memac->serdes);
+-_return_fixed_link_free:
+-	kfree(fixed_link);
+ _return_fm_mac_free:
+ 	memac_free(mac_dev->fman_mac);
+-_return:
+ 	return err;
+ }
+--- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
+@@ -13,6 +13,7 @@
+ #include <linux/bitrev.h>
+ #include <linux/io.h>
+ #include <linux/crc32.h>
++#include <linux/netdevice.h>
+ 
+ /* Transmit Inter-Packet Gap Length Register (TX_IPG_LENGTH) */
+ #define TGEC_TX_IPG_LENGTH_MASK	0x000003ff
+@@ -243,10 +244,6 @@ static int init(struct tgec_regs __iomem
+ 
+ static int check_init_parameters(struct fman_mac *tgec)
+ {
+-	if (tgec->max_speed < SPEED_10000) {
+-		pr_err("10G MAC driver only support 10G speed\n");
+-		return -EINVAL;
+-	}
+ 	if (!tgec->exception_cb) {
+ 		pr_err("uninitialized exception_cb\n");
+ 		return -EINVAL;
+@@ -384,40 +381,13 @@ static void free_init_resources(struct f
+ 	tgec->unicast_addr_hash = NULL;
+ }
+ 
+-static bool is_init_done(struct tgec_cfg *cfg)
+-{
+-	/* Checks if tGEC driver parameters were initialized */
+-	if (!cfg)
+-		return true;
+-
+-	return false;
+-}
+-
+ static int tgec_enable(struct fman_mac *tgec)
+ {
+-	struct tgec_regs __iomem *regs = tgec->regs;
+-	u32 tmp;
+-
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
+-	iowrite32be(tmp, &regs->command_config);
+-
+ 	return 0;
+ }
+ 
+ static void tgec_disable(struct fman_mac *tgec)
+ {
+-	struct tgec_regs __iomem *regs = tgec->regs;
+-	u32 tmp;
+-
+-	WARN_ON_ONCE(!is_init_done(tgec->cfg));
+-
+-	tmp = ioread32be(&regs->command_config);
+-	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
+-	iowrite32be(tmp, &regs->command_config);
+ }
+ 
+ static int tgec_set_promiscuous(struct fman_mac *tgec, bool new_val)
+@@ -425,9 +395,6 @@ static int tgec_set_promiscuous(struct f
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (new_val)
+ 		tmp |= CMD_CFG_PROMIS_EN;
+@@ -444,9 +411,6 @@ static int tgec_set_tx_pause_frames(stru
+ {
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	iowrite32be((u32)pause_time, &regs->pause_quant);
+ 
+ 	return 0;
+@@ -457,9 +421,6 @@ static int tgec_accept_rx_pause_frames(s
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 	if (!en)
+ 		tmp |= CMD_CFG_PAUSE_IGNORE;
+@@ -470,12 +431,53 @@ static int tgec_accept_rx_pause_frames(s
+ 	return 0;
+ }
+ 
++static void tgec_mac_config(struct phylink_config *config, unsigned int mode,
++			    const struct phylink_link_state *state)
++{
++}
++
++static void tgec_link_up(struct phylink_config *config, struct phy_device *phy,
++			 unsigned int mode, phy_interface_t interface,
++			 int speed, int duplex, bool tx_pause, bool rx_pause)
++{
++	struct mac_device *mac_dev = fman_config_to_mac(config);
++	struct fman_mac *tgec = mac_dev->fman_mac;
++	struct tgec_regs __iomem *regs = tgec->regs;
++	u16 pause_time = tx_pause ? FSL_FM_PAUSE_TIME_ENABLE :
++			 FSL_FM_PAUSE_TIME_DISABLE;
++	u32 tmp;
++
++	tgec_set_tx_pause_frames(tgec, 0, pause_time, 0);
++	tgec_accept_rx_pause_frames(tgec, rx_pause);
++	mac_dev->update_speed(mac_dev, speed);
++
++	tmp = ioread32be(&regs->command_config);
++	tmp |= CMD_CFG_RX_EN | CMD_CFG_TX_EN;
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static void tgec_link_down(struct phylink_config *config, unsigned int mode,
++			   phy_interface_t interface)
++{
++	struct fman_mac *tgec = fman_config_to_mac(config)->fman_mac;
++	struct tgec_regs __iomem *regs = tgec->regs;
++	u32 tmp;
++
++	tmp = ioread32be(&regs->command_config);
++	tmp &= ~(CMD_CFG_RX_EN | CMD_CFG_TX_EN);
++	iowrite32be(tmp, &regs->command_config);
++}
++
++static const struct phylink_mac_ops tgec_mac_ops = {
++	.validate = phylink_generic_validate,
++	.mac_config = tgec_mac_config,
++	.mac_link_up = tgec_link_up,
++	.mac_link_down = tgec_link_down,
++};
++
+ static int tgec_modify_mac_address(struct fman_mac *tgec,
+ 				   const enet_addr_t *p_enet_addr)
+ {
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tgec->addr = ENET_ADDR_TO_UINT64(*p_enet_addr);
+ 	set_mac_address(tgec->regs, (const u8 *)(*p_enet_addr));
+ 
+@@ -490,9 +492,6 @@ static int tgec_add_hash_mac_address(str
+ 	u32 crc = 0xFFFFFFFF, hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	addr = ENET_ADDR_TO_UINT64(*eth_addr);
+ 
+ 	if (!(addr & GROUP_ADDRESS)) {
+@@ -525,9 +524,6 @@ static int tgec_set_allmulti(struct fman
+ 	u32 entry;
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	if (enable) {
+ 		for (entry = 0; entry < TGEC_HASH_TABLE_SIZE; entry++)
+ 			iowrite32be(entry | TGEC_HASH_MCAST_EN,
+@@ -548,9 +544,6 @@ static int tgec_set_tstamp(struct fman_m
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 tmp;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	tmp = ioread32be(&regs->command_config);
+ 
+ 	if (enable)
+@@ -572,9 +565,6 @@ static int tgec_del_hash_mac_address(str
+ 	u32 crc = 0xFFFFFFFF, hash;
+ 	u64 addr;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	addr = ((*(u64 *)eth_addr) >> 16);
+ 
+ 	/* CRC calculation */
+@@ -601,22 +591,12 @@ static int tgec_del_hash_mac_address(str
+ 	return 0;
+ }
+ 
+-static void tgec_adjust_link(struct mac_device *mac_dev)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-
+-	mac_dev->update_speed(mac_dev, phy_dev->speed);
+-}
+-
+ static int tgec_set_exception(struct fman_mac *tgec,
+ 			      enum fman_mac_exceptions exception, bool enable)
+ {
+ 	struct tgec_regs __iomem *regs = tgec->regs;
+ 	u32 bit_mask = 0;
+ 
+-	if (!is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	bit_mask = get_exception_flag(exception);
+ 	if (bit_mask) {
+ 		if (enable)
+@@ -641,9 +621,6 @@ static int tgec_init(struct fman_mac *tg
+ 	enet_addr_t eth_addr;
+ 	int err;
+ 
+-	if (is_init_done(tgec->cfg))
+-		return -EINVAL;
+-
+ 	if (DEFAULT_RESET_ON_INIT &&
+ 	    (fman_reset_mac(tgec->fm, tgec->mac_id) != 0)) {
+ 		pr_err("Can't reset MAC!\n");
+@@ -753,7 +730,6 @@ static struct fman_mac *tgec_config(stru
+ 
+ 	tgec->regs = mac_dev->vaddr;
+ 	tgec->addr = ENET_ADDR_TO_UINT64(mac_dev->addr);
+-	tgec->max_speed = params->max_speed;
+ 	tgec->mac_id = params->mac_id;
+ 	tgec->exceptions = (TGEC_IMASK_MDIO_SCAN_EVENT	|
+ 			    TGEC_IMASK_REM_FAULT	|
+@@ -788,17 +764,15 @@ int tgec_initialization(struct mac_devic
+ 	int err;
+ 	struct fman_mac		*tgec;
+ 
++	mac_dev->phylink_ops		= &tgec_mac_ops;
+ 	mac_dev->set_promisc		= tgec_set_promiscuous;
+ 	mac_dev->change_addr		= tgec_modify_mac_address;
+ 	mac_dev->add_hash_mac_addr	= tgec_add_hash_mac_address;
+ 	mac_dev->remove_hash_mac_addr	= tgec_del_hash_mac_address;
+-	mac_dev->set_tx_pause		= tgec_set_tx_pause_frames;
+-	mac_dev->set_rx_pause		= tgec_accept_rx_pause_frames;
+ 	mac_dev->set_exception		= tgec_set_exception;
+ 	mac_dev->set_allmulti		= tgec_set_allmulti;
+ 	mac_dev->set_tstamp		= tgec_set_tstamp;
+ 	mac_dev->set_multi		= fman_set_multi;
+-	mac_dev->adjust_link            = tgec_adjust_link;
+ 	mac_dev->enable			= tgec_enable;
+ 	mac_dev->disable		= tgec_disable;
+ 
+@@ -808,6 +782,19 @@ int tgec_initialization(struct mac_devic
+ 		goto _return;
+ 	}
+ 
++	/* The internal connection to the serdes is XGMII, but this isn't
++	 * really correct for the phy mode (which is the external connection).
++	 * However, this is how all older device trees say that they want
++	 * XAUI, so just convert it for them.
++	 */
++	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
++		mac_dev->phy_if = PHY_INTERFACE_MODE_XAUI;
++
++	__set_bit(PHY_INTERFACE_MODE_XAUI,
++		  mac_dev->phylink_config.supported_interfaces);
++	mac_dev->phylink_config.mac_capabilities =
++		MAC_SYM_PAUSE | MAC_ASYM_PAUSE | MAC_10000FD;
++
+ 	tgec = mac_dev->fman_mac;
+ 	tgec->cfg->max_frame_length = fman_get_max_frm();
+ 	err = tgec_init(tgec);
+--- a/drivers/net/ethernet/freescale/fman/mac.c
++++ b/drivers/net/ethernet/freescale/fman/mac.c
+@@ -15,6 +15,7 @@
+ #include <linux/phy.h>
+ #include <linux/netdevice.h>
+ #include <linux/phy_fixed.h>
++#include <linux/phylink.h>
+ #include <linux/etherdevice.h>
+ #include <linux/libfdt_env.h>
+ 
+@@ -93,130 +94,8 @@ int fman_set_multi(struct net_device *ne
+ 	return 0;
+ }
+ 
+-/**
+- * fman_set_mac_active_pause
+- * @mac_dev:	A pointer to the MAC device
+- * @rx:		Pause frame setting for RX
+- * @tx:		Pause frame setting for TX
+- *
+- * Set the MAC RX/TX PAUSE frames settings
+- *
+- * Avoid redundant calls to FMD, if the MAC driver already contains the desired
+- * active PAUSE settings. Otherwise, the new active settings should be reflected
+- * in FMan.
+- *
+- * Return: 0 on success; Error code otherwise.
+- */
+-int fman_set_mac_active_pause(struct mac_device *mac_dev, bool rx, bool tx)
+-{
+-	struct fman_mac *fman_mac = mac_dev->fman_mac;
+-	int err = 0;
+-
+-	if (rx != mac_dev->rx_pause_active) {
+-		err = mac_dev->set_rx_pause(fman_mac, rx);
+-		if (likely(err == 0))
+-			mac_dev->rx_pause_active = rx;
+-	}
+-
+-	if (tx != mac_dev->tx_pause_active) {
+-		u16 pause_time = (tx ? FSL_FM_PAUSE_TIME_ENABLE :
+-					 FSL_FM_PAUSE_TIME_DISABLE);
+-
+-		err = mac_dev->set_tx_pause(fman_mac, 0, pause_time, 0);
+-
+-		if (likely(err == 0))
+-			mac_dev->tx_pause_active = tx;
+-	}
+-
+-	return err;
+-}
+-EXPORT_SYMBOL(fman_set_mac_active_pause);
+-
+-/**
+- * fman_get_pause_cfg
+- * @mac_dev:	A pointer to the MAC device
+- * @rx_pause:	Return value for RX setting
+- * @tx_pause:	Return value for TX setting
+- *
+- * Determine the MAC RX/TX PAUSE frames settings based on PHY
+- * autonegotiation or values set by eththool.
+- *
+- * Return: Pointer to FMan device.
+- */
+-void fman_get_pause_cfg(struct mac_device *mac_dev, bool *rx_pause,
+-			bool *tx_pause)
+-{
+-	struct phy_device *phy_dev = mac_dev->phy_dev;
+-	u16 lcl_adv, rmt_adv;
+-	u8 flowctrl;
+-
+-	*rx_pause = *tx_pause = false;
+-
+-	if (!phy_dev->duplex)
+-		return;
+-
+-	/* If PAUSE autonegotiation is disabled, the TX/RX PAUSE settings
+-	 * are those set by ethtool.
+-	 */
+-	if (!mac_dev->autoneg_pause) {
+-		*rx_pause = mac_dev->rx_pause_req;
+-		*tx_pause = mac_dev->tx_pause_req;
+-		return;
+-	}
+-
+-	/* Else if PAUSE autonegotiation is enabled, the TX/RX PAUSE
+-	 * settings depend on the result of the link negotiation.
+-	 */
+-
+-	/* get local capabilities */
+-	lcl_adv = linkmode_adv_to_lcl_adv_t(phy_dev->advertising);
+-
+-	/* get link partner capabilities */
+-	rmt_adv = 0;
+-	if (phy_dev->pause)
+-		rmt_adv |= LPA_PAUSE_CAP;
+-	if (phy_dev->asym_pause)
+-		rmt_adv |= LPA_PAUSE_ASYM;
+-
+-	/* Calculate TX/RX settings based on local and peer advertised
+-	 * symmetric/asymmetric PAUSE capabilities.
+-	 */
+-	flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv);
+-	if (flowctrl & FLOW_CTRL_RX)
+-		*rx_pause = true;
+-	if (flowctrl & FLOW_CTRL_TX)
+-		*tx_pause = true;
+-}
+-EXPORT_SYMBOL(fman_get_pause_cfg);
+-
+-#define DTSEC_SUPPORTED \
+-	(SUPPORTED_10baseT_Half \
+-	| SUPPORTED_10baseT_Full \
+-	| SUPPORTED_100baseT_Half \
+-	| SUPPORTED_100baseT_Full \
+-	| SUPPORTED_Autoneg \
+-	| SUPPORTED_Pause \
+-	| SUPPORTED_Asym_Pause \
+-	| SUPPORTED_FIBRE \
+-	| SUPPORTED_MII)
+-
+ static DEFINE_MUTEX(eth_lock);
+ 
+-static const u16 phy2speed[] = {
+-	[PHY_INTERFACE_MODE_MII]		= SPEED_100,
+-	[PHY_INTERFACE_MODE_GMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_SGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_TBI]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RMII]		= SPEED_100,
+-	[PHY_INTERFACE_MODE_RGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_ID]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_RXID]	= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RGMII_TXID]	= SPEED_1000,
+-	[PHY_INTERFACE_MODE_RTBI]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_QSGMII]		= SPEED_1000,
+-	[PHY_INTERFACE_MODE_XGMII]		= SPEED_10000
+-};
+-
+ static struct platform_device *dpaa_eth_add_device(int fman_id,
+ 						   struct mac_device *mac_dev)
+ {
+@@ -263,8 +142,8 @@ no_mem:
+ }
+ 
+ static const struct of_device_id mac_match[] = {
+-	{ .compatible	= "fsl,fman-dtsec", .data = dtsec_initialization },
+-	{ .compatible	= "fsl,fman-xgec", .data = tgec_initialization },
++	{ .compatible   = "fsl,fman-dtsec", .data = dtsec_initialization },
++	{ .compatible   = "fsl,fman-xgec", .data = tgec_initialization },
+ 	{ .compatible	= "fsl,fman-memac", .data = memac_initialization },
+ 	{}
+ };
+@@ -295,6 +174,7 @@ static int mac_probe(struct platform_dev
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
++	platform_set_drvdata(_of_dev, mac_dev);
+ 
+ 	/* Save private information */
+ 	mac_dev->priv = priv;
+@@ -424,57 +304,21 @@ static int mac_probe(struct platform_dev
+ 	}
+ 	mac_dev->phy_if = phy_if;
+ 
+-	priv->speed		= phy2speed[mac_dev->phy_if];
+-	params.max_speed	= priv->speed;
+-	mac_dev->if_support	= DTSEC_SUPPORTED;
+-	/* We don't support half-duplex in SGMII mode */
+-	if (mac_dev->phy_if == PHY_INTERFACE_MODE_SGMII)
+-		mac_dev->if_support &= ~(SUPPORTED_10baseT_Half |
+-					SUPPORTED_100baseT_Half);
+-
+-	/* Gigabit support (no half-duplex) */
+-	if (params.max_speed == 1000)
+-		mac_dev->if_support |= SUPPORTED_1000baseT_Full;
+-
+-	/* The 10G interface only supports one mode */
+-	if (mac_dev->phy_if == PHY_INTERFACE_MODE_XGMII)
+-		mac_dev->if_support = SUPPORTED_10000baseT_Full;
+-
+-	/* Get the rest of the PHY information */
+-	mac_dev->phy_node = of_parse_phandle(mac_node, "phy-handle", 0);
+-
+-	params.basex_if		= false;
+ 	params.mac_id		= priv->cell_index;
+ 	params.fm		= (void *)priv->fman;
+ 	params.exception_cb	= mac_exception;
+ 	params.event_cb		= mac_exception;
+ 
+ 	err = init(mac_dev, mac_node, &params);
+-	if (err < 0) {
+-		dev_err(dev, "mac_dev->init() = %d\n", err);
+-		of_node_put(mac_dev->phy_node);
+-		return err;
+-	}
+-
+-	/* pause frame autonegotiation enabled */
+-	mac_dev->autoneg_pause = true;
+-
+-	/* By intializing the values to false, force FMD to enable PAUSE frames
+-	 * on RX and TX
+-	 */
+-	mac_dev->rx_pause_req = true;
+-	mac_dev->tx_pause_req = true;
+-	mac_dev->rx_pause_active = false;
+-	mac_dev->tx_pause_active = false;
+-	err = fman_set_mac_active_pause(mac_dev, true, true);
+ 	if (err < 0)
+-		dev_err(dev, "fman_set_mac_active_pause() = %d\n", err);
++		return err;
+ 
+ 	if (!is_zero_ether_addr(mac_dev->addr))
+ 		dev_info(dev, "FMan MAC address: %pM\n", mac_dev->addr);
+ 
+ 	priv->eth_dev = dpaa_eth_add_device(fman_id, mac_dev);
+ 	if (IS_ERR(priv->eth_dev)) {
++		err = PTR_ERR(priv->eth_dev);
+ 		dev_err(dev, "failed to add Ethernet platform device for MAC %d\n",
+ 			priv->cell_index);
+ 		priv->eth_dev = NULL;
+--- a/drivers/net/ethernet/freescale/fman/mac.h
++++ b/drivers/net/ethernet/freescale/fman/mac.h
+@@ -9,6 +9,7 @@
+ #include <linux/device.h>
+ #include <linux/if_ether.h>
+ #include <linux/phy.h>
++#include <linux/phylink.h>
+ #include <linux/list.h>
+ 
+ #include "fman_port.h"
+@@ -24,32 +25,22 @@ struct mac_device {
+ 	struct resource		*res;
+ 	u8			 addr[ETH_ALEN];
+ 	struct fman_port	*port[2];
+-	u32			 if_support;
+-	struct phy_device	*phy_dev;
++	struct phylink		*phylink;
++	struct phylink_config	phylink_config;
+ 	phy_interface_t		phy_if;
+-	struct device_node	*phy_node;
+-	struct net_device	*net_dev;
+ 
+-	bool autoneg_pause;
+-	bool rx_pause_req;
+-	bool tx_pause_req;
+-	bool rx_pause_active;
+-	bool tx_pause_active;
+ 	bool promisc;
+ 	bool allmulti;
+ 
++	const struct phylink_mac_ops *phylink_ops;
+ 	int (*enable)(struct fman_mac *mac_dev);
+ 	void (*disable)(struct fman_mac *mac_dev);
+-	void (*adjust_link)(struct mac_device *mac_dev);
+ 	int (*set_promisc)(struct fman_mac *mac_dev, bool enable);
+ 	int (*change_addr)(struct fman_mac *mac_dev, const enet_addr_t *enet_addr);
+ 	int (*set_allmulti)(struct fman_mac *mac_dev, bool enable);
+ 	int (*set_tstamp)(struct fman_mac *mac_dev, bool enable);
+ 	int (*set_multi)(struct net_device *net_dev,
+ 			 struct mac_device *mac_dev);
+-	int (*set_rx_pause)(struct fman_mac *mac_dev, bool en);
+-	int (*set_tx_pause)(struct fman_mac *mac_dev, u8 priority,
+-			    u16 pause_time, u16 thresh_time);
+ 	int (*set_exception)(struct fman_mac *mac_dev,
+ 			     enum fman_mac_exceptions exception, bool enable);
+ 	int (*add_hash_mac_addr)(struct fman_mac *mac_dev,
+@@ -63,6 +54,12 @@ struct mac_device {
+ 	struct mac_priv_s	*priv;
+ };
+ 
++static inline struct mac_device
++*fman_config_to_mac(struct phylink_config *config)
++{
++	return container_of(config, struct mac_device, phylink_config);
++}
++
+ struct dpaa_eth_data {
+ 	struct mac_device *mac_dev;
+ 	int mac_hw_id;
diff --git a/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch b/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch
new file mode 100644
index 00000000000..06c348b1cdf
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-04-v6.2-net-phylink-provide-phylink_validate_mask_caps-helpe.patch
@@ -0,0 +1,93 @@
+From bf4de031052fe7c5309e8956c342d4e5ce79038e Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Mon, 17 Oct 2022 16:22:35 -0400
+Subject: [PATCH 04/21] net: phylink: provide phylink_validate_mask_caps()
+ helper
+
+Provide a helper that restricts the link modes according to the
+phylink capabilities.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+[rebased on net-next/master and added documentation]
+Signed-off-by: Sean Anderson <sean.anderson@seco.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 41 +++++++++++++++++++++++++++------------
+ include/linux/phylink.h   |  3 +++
+ 2 files changed, 32 insertions(+), 12 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -564,31 +564,48 @@ unsigned long phylink_get_capabilities(p
+ EXPORT_SYMBOL_GPL(phylink_get_capabilities);
+ 
+ /**
+- * phylink_generic_validate() - generic validate() callback implementation
+- * @config: a pointer to a &struct phylink_config.
++ * phylink_validate_mask_caps() - Restrict link modes based on caps
+  * @supported: ethtool bitmask for supported link modes.
+- * @state: a pointer to a &struct phylink_link_state.
++ * @state: an (optional) pointer to a &struct phylink_link_state.
++ * @mac_capabilities: bitmask of MAC capabilities
+  *
+- * Generic implementation of the validate() callback that MAC drivers can
+- * use when they pass the range of supported interfaces and MAC capabilities.
+- * This makes use of phylink_get_linkmodes().
++ * Calculate the supported link modes based on @mac_capabilities, and restrict
++ * @supported and @state based on that. Use this function if your capabiliies
++ * aren't constant, such as if they vary depending on the interface.
+  */
+-void phylink_generic_validate(struct phylink_config *config,
+-			      unsigned long *supported,
+-			      struct phylink_link_state *state)
++void phylink_validate_mask_caps(unsigned long *supported,
++				struct phylink_link_state *state,
++				unsigned long mac_capabilities)
+ {
+ 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
+ 	unsigned long caps;
+ 
+ 	phylink_set_port_modes(mask);
+ 	phylink_set(mask, Autoneg);
+-	caps = phylink_get_capabilities(state->interface,
+-					config->mac_capabilities,
++	caps = phylink_get_capabilities(state->interface, mac_capabilities,
+ 					state->rate_matching);
+ 	phylink_caps_to_linkmodes(mask, caps);
+ 
+ 	linkmode_and(supported, supported, mask);
+-	linkmode_and(state->advertising, state->advertising, mask);
++	if (state)
++		linkmode_and(state->advertising, state->advertising, mask);
++}
++EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
++
++/**
++ * phylink_generic_validate() - generic validate() callback implementation
++ * @config: a pointer to a &struct phylink_config.
++ * @supported: ethtool bitmask for supported link modes.
++ * @state: a pointer to a &struct phylink_link_state.
++ *
++ * Generic implementation of the validate() callback that MAC drivers can
++ * use when they pass the range of supported interfaces and MAC capabilities.
++ */
++void phylink_generic_validate(struct phylink_config *config,
++			      unsigned long *supported,
++			      struct phylink_link_state *state)
++{
++	phylink_validate_mask_caps(supported, state, config->mac_capabilities);
+ }
+ EXPORT_SYMBOL_GPL(phylink_generic_validate);
+ 
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -558,6 +558,9 @@ void phylink_caps_to_linkmodes(unsigned
+ unsigned long phylink_get_capabilities(phy_interface_t interface,
+ 				       unsigned long mac_capabilities,
+ 				       int rate_matching);
++void phylink_validate_mask_caps(unsigned long *supported,
++				struct phylink_link_state *state,
++				unsigned long caps);
+ void phylink_generic_validate(struct phylink_config *config,
+ 			      unsigned long *supported,
+ 			      struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch b/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch
new file mode 100644
index 00000000000..e3a1dda688a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-05-v6.2-phylink-require-valid-state-argument-to-phylink_vali.patch
@@ -0,0 +1,39 @@
+From 2bf7e4a68c42eed909f3c29582e1fb85cb157e35 Mon Sep 17 00:00:00 2001
+From: Jakub Kicinski <kuba@kernel.org>
+Date: Tue, 25 Oct 2022 11:51:26 -0700
+Subject: [PATCH 05/21] phylink: require valid state argument to
+ phylink_validate_mask_caps()
+
+state is deferenced earlier in the function, the NULL check
+is pointless. Since we don't have any crash reports presumably
+it's safe to assume state is not NULL.
+
+Fixes: f392a1846489 ("net: phylink: provide phylink_validate_mask_caps() helper")
+Reviewed-by: Sean Anderson <sean.anderson@seco.com>
+Link: https://lore.kernel.org/r/20221025185126.1720553-1-kuba@kernel.org
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -566,7 +566,7 @@ EXPORT_SYMBOL_GPL(phylink_get_capabiliti
+ /**
+  * phylink_validate_mask_caps() - Restrict link modes based on caps
+  * @supported: ethtool bitmask for supported link modes.
+- * @state: an (optional) pointer to a &struct phylink_link_state.
++ * @state: pointer to a &struct phylink_link_state.
+  * @mac_capabilities: bitmask of MAC capabilities
+  *
+  * Calculate the supported link modes based on @mac_capabilities, and restrict
+@@ -587,8 +587,7 @@ void phylink_validate_mask_caps(unsigned
+ 	phylink_caps_to_linkmodes(mask, caps);
+ 
+ 	linkmode_and(supported, supported, mask);
+-	if (state)
+-		linkmode_and(state->advertising, state->advertising, mask);
++	linkmode_and(state->advertising, state->advertising, mask);
+ }
+ EXPORT_SYMBOL_GPL(phylink_validate_mask_caps);
+ 
diff --git a/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch b/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
similarity index 87%
rename from target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
rename to target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
index 81c14a0557b..c217ed87b51 100644
--- a/target/linux/generic/backport-6.1/700-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
+++ b/target/linux/generic/backport-6.1/715-06-v6.2-net-phylink-add-phylink_get_link_timer_ns-helper.patch
@@ -1,7 +1,7 @@
-From 9c5a170677c3c8facc83e931a57f4c99c0511ae0 Mon Sep 17 00:00:00 2001
+From f8fc363bf0c023e4736a0328174b4a24b44ab23a Mon Sep 17 00:00:00 2001
 From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
 Date: Thu, 27 Oct 2022 14:10:37 +0100
-Subject: [PATCH] net: phylink: add phylink_get_link_timer_ns() helper
+Subject: [PATCH 06/21] net: phylink: add phylink_get_link_timer_ns() helper
 
 Add a helper to convert the PHY interface mode to the required link
 timer setting as stated by the appropriate standard. Inappropriate
@@ -15,7 +15,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/include/linux/phylink.h
 +++ b/include/linux/phylink.h
-@@ -614,6 +614,30 @@ int phylink_speed_up(struct phylink *pl)
+@@ -617,6 +617,30 @@ int phylink_speed_up(struct phylink *pl)
  
  void phylink_set_port_modes(unsigned long *bits);
  
diff --git a/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch
new file mode 100644
index 00000000000..28154af920c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-07-v6.2-net-remove-explicit-phylink_generic_validate-referen.patch
@@ -0,0 +1,250 @@
+From b45b773a96b0e9e8d51e5d005485f4e376d6ce9a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 4 Nov 2022 17:13:01 +0000
+Subject: [PATCH 07/21] net: remove explicit phylink_generic_validate()
+ references
+
+Virtually all conventional network drivers are now converted to use
+phylink_generic_validate() - only DSA drivers and fman_memac remain,
+so lets remove the necessity for network drivers to explicitly set
+this member, and default to phylink_generic_validate() when unset.
+This is possible as .validate must currently be set.
+
+Any remaining instances that have not been addressed by this patch can
+be fixed up later.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
+Link: https://lore.kernel.org/r/E1or0FZ-001tRa-DI@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/altera/altera_tse_main.c            | 1 -
+ drivers/net/ethernet/atheros/ag71xx.c                    | 1 -
+ drivers/net/ethernet/cadence/macb_main.c                 | 1 -
+ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c         | 1 -
+ drivers/net/ethernet/freescale/enetc/enetc_pf.c          | 1 -
+ drivers/net/ethernet/freescale/fman/fman_dtsec.c         | 1 -
+ drivers/net/ethernet/freescale/fman/fman_tgec.c          | 1 -
+ drivers/net/ethernet/marvell/mvneta.c                    | 1 -
+ drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c          | 1 -
+ drivers/net/ethernet/marvell/prestera/prestera_main.c    | 1 -
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c              | 1 -
+ drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c | 1 -
+ drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c   | 1 -
+ drivers/net/ethernet/mscc/ocelot_net.c                   | 1 -
+ drivers/net/ethernet/stmicro/stmmac/stmmac_main.c        | 1 -
+ drivers/net/ethernet/ti/am65-cpsw-nuss.c                 | 1 -
+ drivers/net/ethernet/xilinx/xilinx_axienet_main.c        | 1 -
+ drivers/net/phy/phylink.c                                | 5 ++++-
+ drivers/net/usb/asix_devices.c                           | 1 -
+ include/linux/phylink.h                                  | 5 +++++
+ 20 files changed, 9 insertions(+), 19 deletions(-)
+
+--- a/drivers/net/ethernet/altera/altera_tse_main.c
++++ b/drivers/net/ethernet/altera/altera_tse_main.c
+@@ -1096,7 +1096,6 @@ static struct phylink_pcs *alt_tse_selec
+ }
+ 
+ static const struct phylink_mac_ops alt_tse_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_an_restart = alt_tse_mac_an_restart,
+ 	.mac_config = alt_tse_mac_config,
+ 	.mac_link_down = alt_tse_mac_link_down,
+--- a/drivers/net/ethernet/atheros/ag71xx.c
++++ b/drivers/net/ethernet/atheros/ag71xx.c
+@@ -1086,7 +1086,6 @@ static void ag71xx_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops ag71xx_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = ag71xx_mac_config,
+ 	.mac_link_down = ag71xx_mac_link_down,
+ 	.mac_link_up = ag71xx_mac_link_up,
+--- a/drivers/net/ethernet/cadence/macb_main.c
++++ b/drivers/net/ethernet/cadence/macb_main.c
+@@ -752,7 +752,6 @@ static struct phylink_pcs *macb_mac_sele
+ }
+ 
+ static const struct phylink_mac_ops macb_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = macb_mac_select_pcs,
+ 	.mac_config = macb_mac_config,
+ 	.mac_link_down = macb_mac_link_down,
+--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+@@ -235,7 +235,6 @@ static void dpaa2_mac_link_down(struct p
+ }
+ 
+ static const struct phylink_mac_ops dpaa2_mac_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = dpaa2_mac_select_pcs,
+ 	.mac_config = dpaa2_mac_config,
+ 	.mac_link_up = dpaa2_mac_link_up,
+--- a/drivers/net/ethernet/freescale/enetc/enetc_pf.c
++++ b/drivers/net/ethernet/freescale/enetc/enetc_pf.c
+@@ -1111,7 +1111,6 @@ static void enetc_pl_mac_link_down(struc
+ }
+ 
+ static const struct phylink_mac_ops enetc_mac_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = enetc_pl_mac_select_pcs,
+ 	.mac_config = enetc_pl_mac_config,
+ 	.mac_link_up = enetc_pl_mac_link_up,
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -986,7 +986,6 @@ static void dtsec_link_down(struct phyli
+ }
+ 
+ static const struct phylink_mac_ops dtsec_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = dtsec_select_pcs,
+ 	.mac_config = dtsec_mac_config,
+ 	.mac_link_up = dtsec_link_up,
+--- a/drivers/net/ethernet/freescale/fman/fman_tgec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_tgec.c
+@@ -469,7 +469,6 @@ static void tgec_link_down(struct phylin
+ }
+ 
+ static const struct phylink_mac_ops tgec_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = tgec_mac_config,
+ 	.mac_link_up = tgec_link_up,
+ 	.mac_link_down = tgec_link_down,
+--- a/drivers/net/ethernet/marvell/mvneta.c
++++ b/drivers/net/ethernet/marvell/mvneta.c
+@@ -4228,7 +4228,6 @@ static void mvneta_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops mvneta_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mvneta_mac_select_pcs,
+ 	.mac_prepare = mvneta_mac_prepare,
+ 	.mac_config = mvneta_mac_config,
+--- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
++++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c
+@@ -6633,7 +6633,6 @@ static void mvpp2_mac_link_down(struct p
+ }
+ 
+ static const struct phylink_mac_ops mvpp2_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mvpp2_select_pcs,
+ 	.mac_prepare = mvpp2_mac_prepare,
+ 	.mac_config = mvpp2_mac_config,
+--- a/drivers/net/ethernet/marvell/prestera/prestera_main.c
++++ b/drivers/net/ethernet/marvell/prestera/prestera_main.c
+@@ -360,7 +360,6 @@ static void prestera_pcs_an_restart(stru
+ }
+ 
+ static const struct phylink_mac_ops prestera_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = prestera_mac_select_pcs,
+ 	.mac_config = prestera_mac_config,
+ 	.mac_link_down = prestera_mac_link_down,
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -654,7 +654,6 @@ static void mtk_mac_link_up(struct phyli
+ }
+ 
+ static const struct phylink_mac_ops mtk_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = mtk_mac_select_pcs,
+ 	.mac_pcs_get_state = mtk_mac_pcs_get_state,
+ 	.mac_config = mtk_mac_config,
+--- a/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c
++++ b/drivers/net/ethernet/microchip/lan966x/lan966x_phylink.c
+@@ -125,7 +125,6 @@ static void lan966x_pcs_aneg_restart(str
+ }
+ 
+ const struct phylink_mac_ops lan966x_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = lan966x_phylink_mac_select,
+ 	.mac_config = lan966x_phylink_mac_config,
+ 	.mac_prepare = lan966x_phylink_mac_prepare,
+--- a/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
++++ b/drivers/net/ethernet/microchip/sparx5/sparx5_phylink.c
+@@ -138,7 +138,6 @@ const struct phylink_pcs_ops sparx5_phyl
+ };
+ 
+ const struct phylink_mac_ops sparx5_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = sparx5_phylink_mac_select_pcs,
+ 	.mac_config = sparx5_phylink_mac_config,
+ 	.mac_link_down = sparx5_phylink_mac_link_down,
+--- a/drivers/net/ethernet/mscc/ocelot_net.c
++++ b/drivers/net/ethernet/mscc/ocelot_net.c
+@@ -1737,7 +1737,6 @@ static void vsc7514_phylink_mac_link_up(
+ }
+ 
+ static const struct phylink_mac_ops ocelot_phylink_ops = {
+-	.validate		= phylink_generic_validate,
+ 	.mac_config		= vsc7514_phylink_mac_config,
+ 	.mac_link_down		= vsc7514_phylink_mac_link_down,
+ 	.mac_link_up		= vsc7514_phylink_mac_link_up,
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -1090,7 +1090,6 @@ static void stmmac_mac_link_up(struct ph
+ }
+ 
+ static const struct phylink_mac_ops stmmac_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = stmmac_mac_select_pcs,
+ 	.mac_config = stmmac_mac_config,
+ 	.mac_link_down = stmmac_mac_link_down,
+--- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
++++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
+@@ -1493,7 +1493,6 @@ static void am65_cpsw_nuss_mac_link_up(s
+ }
+ 
+ static const struct phylink_mac_ops am65_cpsw_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = am65_cpsw_nuss_mac_config,
+ 	.mac_link_down = am65_cpsw_nuss_mac_link_down,
+ 	.mac_link_up = am65_cpsw_nuss_mac_link_up,
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1736,7 +1736,6 @@ static void axienet_mac_link_up(struct p
+ }
+ 
+ static const struct phylink_mac_ops axienet_phylink_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_select_pcs = axienet_mac_select_pcs,
+ 	.mac_config = axienet_mac_config,
+ 	.mac_link_down = axienet_mac_link_down,
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -651,7 +651,10 @@ static int phylink_validate_mac_and_pcs(
+ 	}
+ 
+ 	/* Then validate the link parameters with the MAC */
+-	pl->mac_ops->validate(pl->config, supported, state);
++	if (pl->mac_ops->validate)
++		pl->mac_ops->validate(pl->config, supported, state);
++	else
++		phylink_generic_validate(pl->config, supported, state);
+ 
+ 	return phylink_is_empty_linkmode(supported) ? -EINVAL : 0;
+ }
+--- a/drivers/net/usb/asix_devices.c
++++ b/drivers/net/usb/asix_devices.c
+@@ -787,7 +787,6 @@ static void ax88772_mac_link_up(struct p
+ }
+ 
+ static const struct phylink_mac_ops ax88772_phylink_mac_ops = {
+-	.validate = phylink_generic_validate,
+ 	.mac_config = ax88772_mac_config,
+ 	.mac_link_down = ax88772_mac_link_down,
+ 	.mac_link_up = ax88772_mac_link_up,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -207,6 +207,11 @@ struct phylink_mac_ops {
+  *
+  * If the @state->interface mode is not supported, then the @supported
+  * mask must be cleared.
++ *
++ * This member is optional; if not set, the generic validator will be
++ * used making use of @config->mac_capabilities and
++ * @config->supported_interfaces to determine which link modes are
++ * supported.
+  */
+ void validate(struct phylink_config *config, unsigned long *supported,
+ 	      struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch b/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch
new file mode 100644
index 00000000000..37d82b2cd7d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-08-net-sfp-make-sfp_bus_find_fwnode-take-a-const-fwnode.patch
@@ -0,0 +1,48 @@
+From a90ac762d345890b40d88a1385a34a2449c2d75e Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Mar 2023 09:23:42 +0000
+Subject: [PATCH] net: sfp: make sfp_bus_find_fwnode() take a const fwnode
+
+sfp_bus_find_fwnode() does not write to the fwnode, so let's make it
+const.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/sfp-bus.c | 2 +-
+ include/linux/sfp.h       | 5 +++--
+ 2 files changed, 4 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -603,7 +603,7 @@ static void sfp_upstream_clear(struct sf
+  *	- %-ENOMEM if we failed to allocate the bus.
+  *	- an error from the upstream's connect_phy() method.
+  */
+-struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
++struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_reference_args ref;
+ 	struct sfp_bus *bus;
+--- a/include/linux/sfp.h
++++ b/include/linux/sfp.h
+@@ -548,7 +548,7 @@ int sfp_get_module_eeprom_by_page(struct
+ void sfp_upstream_start(struct sfp_bus *bus);
+ void sfp_upstream_stop(struct sfp_bus *bus);
+ void sfp_bus_put(struct sfp_bus *bus);
+-struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode);
++struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode);
+ int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
+ 			 const struct sfp_upstream_ops *ops);
+ void sfp_bus_del_upstream(struct sfp_bus *bus);
+@@ -610,7 +610,8 @@ static inline void sfp_bus_put(struct sf
+ {
+ }
+ 
+-static inline struct sfp_bus *sfp_bus_find_fwnode(struct fwnode_handle *fwnode)
++static inline struct sfp_bus *
++sfp_bus_find_fwnode(const struct fwnode_handle *fwnode)
+ {
+ 	return NULL;
+ }
diff --git a/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch b/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch
new file mode 100644
index 00000000000..290cb8d161d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-09-v6.4-net-pcs-lynx-don-t-print-an_enabled-in-pcs_get_state.patch
@@ -0,0 +1,31 @@
+From ecec0ebbc6381a5a375f1cf10c4858f24e91e2ef Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 15 Mar 2023 14:46:49 +0000
+Subject: [PATCH] net: pcs: lynx: don't print an_enabled in pcs_get_state()
+
+an_enabled will be going away, and in any case, pcs_get_state() should
+not be updating this member. Remove the print.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Steen Hegelund <Steen.Hegelund@microchip.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/pcs/pcs-lynx.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -115,11 +115,11 @@ static void lynx_pcs_get_state(struct ph
+ 	}
+ 
+ 	dev_dbg(&lynx->mdio->dev,
+-		"mode=%s/%s/%s link=%u an_enabled=%u an_complete=%u\n",
++		"mode=%s/%s/%s link=%u an_complete=%u\n",
+ 		phy_modes(state->interface),
+ 		phy_speed_to_str(state->speed),
+ 		phy_duplex_to_str(state->duplex),
+-		state->link, state->an_enabled, state->an_complete);
++		state->link, state->an_complete);
+ }
+ 
+ static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
diff --git a/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch b/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch
new file mode 100644
index 00000000000..38ea2654760
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-10-v6.4-net-dpaa2-mac-use-Autoneg-bit-rather-than-an_enabled.patch
@@ -0,0 +1,32 @@
+From 99d0f3a1095f4c938b1665025c29411edafe8a01 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:44 +0000
+Subject: [PATCH] net: dpaa2-mac: use Autoneg bit rather than an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. Thus, we will be removing state->an_enabled.
+
+Use the Autoneg bit in the advertising bitmap to indicate whether
+autonegotiation should be used, rather than using the an_enabled
+member which will be going away. This means we use the same condition
+as phylink_mii_c22_pcs_config().
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
++++ b/drivers/net/ethernet/freescale/dpaa2/dpaa2-mac.c
+@@ -158,7 +158,8 @@ static void dpaa2_mac_config(struct phyl
+ 	struct dpmac_link_state *dpmac_state = &mac->state;
+ 	int err;
+ 
+-	if (state->an_enabled)
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising))
+ 		dpmac_state->options |= DPMAC_LINK_OPT_AUTONEG;
+ 	else
+ 		dpmac_state->options &= ~DPMAC_LINK_OPT_AUTONEG;
diff --git a/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch b/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch
new file mode 100644
index 00000000000..cb9c411cfb0
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-11-v6.4-net-phylink-support-validated-pause-and-autoneg-in-f.patch
@@ -0,0 +1,64 @@
+From 471c40bde606ec0b1ce8c616f7998739c7a783a6 Mon Sep 17 00:00:00 2001
+From: Ivan Bornyakov <i.bornyakov@metrotek.ru>
+Date: Fri, 10 Feb 2023 18:46:27 +0300
+Subject: [PATCH 10/21] net: phylink: support validated pause and autoneg in
+ fixed-link
+
+In fixed-link setup phylink_parse_fixedlink() unconditionally sets
+Pause, Asym_Pause and Autoneg bits to "supported" bitmap, while MAC may
+not support these.
+
+This leads to ethtool reporting:
+
+ > Supported pause frame use: Symmetric Receive-only
+ > Supports auto-negotiation: Yes
+
+regardless of what is actually supported.
+
+Instead of unconditionally set Pause, Asym_Pause and Autoneg it is
+sensible to set them according to validated "supported" bitmap, i.e. the
+result of phylink_validate().
+
+Signed-off-by: Ivan Bornyakov <i.bornyakov@metrotek.ru>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 17 ++++++++++++++---
+ 1 file changed, 14 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -709,6 +709,7 @@ static int phylink_parse_fixedlink(struc
+ 				   struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *fixed_node;
++	bool pause, asym_pause, autoneg;
+ 	const struct phy_setting *s;
+ 	struct gpio_desc *desc;
+ 	u32 speed;
+@@ -781,13 +782,23 @@ static int phylink_parse_fixedlink(struc
+ 	linkmode_copy(pl->link_config.advertising, pl->supported);
+ 	phylink_validate(pl, pl->supported, &pl->link_config);
+ 
++	pause = phylink_test(pl->supported, Pause);
++	asym_pause = phylink_test(pl->supported, Asym_Pause);
++	autoneg = phylink_test(pl->supported, Autoneg);
+ 	s = phy_lookup_setting(pl->link_config.speed, pl->link_config.duplex,
+ 			       pl->supported, true);
+ 	linkmode_zero(pl->supported);
+ 	phylink_set(pl->supported, MII);
+-	phylink_set(pl->supported, Pause);
+-	phylink_set(pl->supported, Asym_Pause);
+-	phylink_set(pl->supported, Autoneg);
++
++	if (pause)
++		phylink_set(pl->supported, Pause);
++
++	if (asym_pause)
++		phylink_set(pl->supported, Asym_Pause);
++
++	if (autoneg)
++		phylink_set(pl->supported, Autoneg);
++
+ 	if (s) {
+ 		__set_bit(s->bit, pl->supported);
+ 		__set_bit(s->bit, pl->link_config.lp_advertising);
diff --git a/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch b/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch
new file mode 100644
index 00000000000..03b4f9d0c4c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-12-v6.4-net-phylink-remove-an_enabled.patch
@@ -0,0 +1,177 @@
+From 7211ffd70941933a7825a56cf480f07ee81c321c Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:54 +0000
+Subject: [PATCH 11/21] net: phylink: remove an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. state->an_enabled is now no longer used by any
+drivers, so lets kill this duplication.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 37 +++++++++++++++++--------------------
+ include/linux/phylink.h   |  2 --
+ 2 files changed, 17 insertions(+), 22 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -841,7 +841,6 @@ static int phylink_parse_mode(struct phy
+ 		phylink_set(pl->supported, Autoneg);
+ 		phylink_set(pl->supported, Asym_Pause);
+ 		phylink_set(pl->supported, Pause);
+-		pl->link_config.an_enabled = true;
+ 		pl->cfg_link_an_mode = MLO_AN_INBAND;
+ 
+ 		switch (pl->link_config.interface) {
+@@ -944,9 +943,6 @@ static int phylink_parse_mode(struct phy
+ 				    "failed to validate link configuration for in-band status\n");
+ 			return -EINVAL;
+ 		}
+-
+-		/* Check if MAC/PCS also supports Autoneg. */
+-		pl->link_config.an_enabled = phylink_test(pl->supported, Autoneg);
+ 	}
+ 
+ 	return 0;
+@@ -956,7 +952,8 @@ static void phylink_apply_manual_flow(st
+ 				      struct phylink_link_state *state)
+ {
+ 	/* If autoneg is disabled, pause AN is also disabled */
+-	if (!state->an_enabled)
++	if (!linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			       state->advertising))
+ 		state->pause &= ~MLO_PAUSE_AN;
+ 
+ 	/* Manual configuration of pause modes */
+@@ -996,21 +993,22 @@ static void phylink_mac_config(struct ph
+ 			       const struct phylink_link_state *state)
+ {
+ 	phylink_dbg(pl,
+-		    "%s: mode=%s/%s/%s/%s/%s adv=%*pb pause=%02x link=%u an=%u\n",
++		    "%s: mode=%s/%s/%s/%s/%s adv=%*pb pause=%02x link=%u\n",
+ 		    __func__, phylink_an_mode_str(pl->cur_link_an_mode),
+ 		    phy_modes(state->interface),
+ 		    phy_speed_to_str(state->speed),
+ 		    phy_duplex_to_str(state->duplex),
+ 		    phy_rate_matching_to_str(state->rate_matching),
+ 		    __ETHTOOL_LINK_MODE_MASK_NBITS, state->advertising,
+-		    state->pause, state->link, state->an_enabled);
++		    state->pause, state->link);
+ 
+ 	pl->mac_ops->mac_config(pl->config, pl->cur_link_an_mode, state);
+ }
+ 
+ static void phylink_mac_pcs_an_restart(struct phylink *pl)
+ {
+-	if (pl->link_config.an_enabled &&
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      pl->link_config.advertising) &&
+ 	    phy_interface_mode_is_8023z(pl->link_config.interface) &&
+ 	    phylink_autoneg_inband(pl->cur_link_an_mode)) {
+ 		if (pl->pcs)
+@@ -1137,9 +1135,9 @@ static void phylink_mac_pcs_get_state(st
+ 	linkmode_copy(state->advertising, pl->link_config.advertising);
+ 	linkmode_zero(state->lp_advertising);
+ 	state->interface = pl->link_config.interface;
+-	state->an_enabled = pl->link_config.an_enabled;
+ 	state->rate_matching = pl->link_config.rate_matching;
+-	if (state->an_enabled) {
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising)) {
+ 		state->speed = SPEED_UNKNOWN;
+ 		state->duplex = DUPLEX_UNKNOWN;
+ 		state->pause = MLO_PAUSE_NONE;
+@@ -1531,7 +1529,6 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.pause = MLO_PAUSE_AN;
+ 	pl->link_config.speed = SPEED_UNKNOWN;
+ 	pl->link_config.duplex = DUPLEX_UNKNOWN;
+-	pl->link_config.an_enabled = true;
+ 	pl->mac_ops = mac_ops;
+ 	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
+ 	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
+@@ -2155,8 +2152,9 @@ static void phylink_get_ksettings(const
+ 		kset->base.speed = state->speed;
+ 		kset->base.duplex = state->duplex;
+ 	}
+-	kset->base.autoneg = state->an_enabled ? AUTONEG_ENABLE :
+-				AUTONEG_DISABLE;
++	kset->base.autoneg = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					       state->advertising) ?
++				AUTONEG_ENABLE : AUTONEG_DISABLE;
+ }
+ 
+ /**
+@@ -2303,9 +2301,8 @@ int phylink_ethtool_ksettings_set(struct
+ 	/* We have ruled out the case with a PHY attached, and the
+ 	 * fixed-link cases.  All that is left are in-band links.
+ 	 */
+-	config.an_enabled = kset->base.autoneg == AUTONEG_ENABLE;
+ 	linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, config.advertising,
+-			 config.an_enabled);
++			 kset->base.autoneg == AUTONEG_ENABLE);
+ 
+ 	/* If this link is with an SFP, ensure that changes to advertised modes
+ 	 * also cause the associated interface to be selected such that the
+@@ -2339,13 +2336,14 @@ int phylink_ethtool_ksettings_set(struct
+ 	}
+ 
+ 	/* If autonegotiation is enabled, we must have an advertisement */
+-	if (config.an_enabled && phylink_is_empty_linkmode(config.advertising))
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      config.advertising) &&
++	    phylink_is_empty_linkmode(config.advertising))
+ 		return -EINVAL;
+ 
+ 	mutex_lock(&pl->state_mutex);
+ 	pl->link_config.speed = config.speed;
+ 	pl->link_config.duplex = config.duplex;
+-	pl->link_config.an_enabled = config.an_enabled;
+ 
+ 	if (pl->link_config.interface != config.interface) {
+ 		/* The interface changed, e.g. 1000base-X <-> 2500base-X */
+@@ -2951,7 +2949,6 @@ static int phylink_sfp_config_phy(struct
+ 	config.speed = SPEED_UNKNOWN;
+ 	config.duplex = DUPLEX_UNKNOWN;
+ 	config.pause = MLO_PAUSE_AN;
+-	config.an_enabled = pl->link_config.an_enabled;
+ 
+ 	/* Ignore errors if we're expecting a PHY to attach later */
+ 	ret = phylink_validate(pl, support, &config);
+@@ -3020,7 +3017,6 @@ static int phylink_sfp_config_optical(st
+ 	config.speed = SPEED_UNKNOWN;
+ 	config.duplex = DUPLEX_UNKNOWN;
+ 	config.pause = MLO_PAUSE_AN;
+-	config.an_enabled = true;
+ 
+ 	/* For all the interfaces that are supported, reduce the sfp_support
+ 	 * mask to only those link modes that can be supported.
+@@ -3354,7 +3350,8 @@ void phylink_mii_c22_pcs_decode_state(st
+ 	/* If there is no link or autonegotiation is disabled, the LP advertisement
+ 	 * data is not meaningful, so don't go any further.
+ 	 */
+-	if (!state->link || !state->an_enabled)
++	if (!state->link || !linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					       state->advertising))
+ 		return;
+ 
+ 	switch (state->interface) {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -93,7 +93,6 @@ static inline bool phylink_autoneg_inban
+  *   the medium link mode (@speed and @duplex) and the speed/duplex of the phy
+  *   interface mode (@interface) are different.
+  * @link: true if the link is up.
+- * @an_enabled: true if autonegotiation is enabled/desired.
+  * @an_complete: true if autonegotiation has completed.
+  */
+ struct phylink_link_state {
+@@ -105,7 +104,6 @@ struct phylink_link_state {
+ 	int pause;
+ 	int rate_matching;
+ 	unsigned int link:1;
+-	unsigned int an_enabled:1;
+ 	unsigned int an_complete:1;
+ };
+ 
diff --git a/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch b/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch
new file mode 100644
index 00000000000..c06a367b8be
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-13-v6.5-net-phylink-constify-fwnode-arguments.patch
@@ -0,0 +1,88 @@
+From a3555d1f5c208f0a63eafee77381f68d304a0512 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 12 May 2023 17:58:37 +0100
+Subject: [PATCH 12/21] net: phylink: constify fwnode arguments
+
+Both phylink_create() and phylink_fwnode_phy_connect() do not modify
+the fwnode argument that they are passed, so lets constify these.
+
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 11 ++++++-----
+ include/linux/phylink.h   |  9 +++++----
+ 2 files changed, 11 insertions(+), 9 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -706,7 +706,7 @@ static int phylink_validate(struct phyli
+ }
+ 
+ static int phylink_parse_fixedlink(struct phylink *pl,
+-				   struct fwnode_handle *fwnode)
++				   const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *fixed_node;
+ 	bool pause, asym_pause, autoneg;
+@@ -817,7 +817,8 @@ static int phylink_parse_fixedlink(struc
+ 	return 0;
+ }
+ 
+-static int phylink_parse_mode(struct phylink *pl, struct fwnode_handle *fwnode)
++static int phylink_parse_mode(struct phylink *pl,
++			      const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *dn;
+ 	const char *managed;
+@@ -1440,7 +1441,7 @@ static void phylink_fixed_poll(struct ti
+ static const struct sfp_upstream_ops sfp_phylink_ops;
+ 
+ static int phylink_register_sfp(struct phylink *pl,
+-				struct fwnode_handle *fwnode)
++				const struct fwnode_handle *fwnode)
+ {
+ 	struct sfp_bus *bus;
+ 	int ret;
+@@ -1479,7 +1480,7 @@ static int phylink_register_sfp(struct p
+  * must use IS_ERR() to check for errors from this function.
+  */
+ struct phylink *phylink_create(struct phylink_config *config,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       phy_interface_t iface,
+ 			       const struct phylink_mac_ops *mac_ops)
+ {
+@@ -1809,7 +1810,7 @@ EXPORT_SYMBOL_GPL(phylink_of_phy_connect
+  * Returns 0 on success or a negative errno.
+  */
+ int phylink_fwnode_phy_connect(struct phylink *pl,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       u32 flags)
+ {
+ 	struct fwnode_handle *phy_fwnode;
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -568,16 +568,17 @@ void phylink_generic_validate(struct phy
+ 			      unsigned long *supported,
+ 			      struct phylink_link_state *state);
+ 
+-struct phylink *phylink_create(struct phylink_config *, struct fwnode_handle *,
+-			       phy_interface_t iface,
+-			       const struct phylink_mac_ops *mac_ops);
++struct phylink *phylink_create(struct phylink_config *,
++			       const struct fwnode_handle *,
++			       phy_interface_t,
++			       const struct phylink_mac_ops *);
+ void phylink_destroy(struct phylink *);
+ bool phylink_expects_phy(struct phylink *pl);
+ 
+ int phylink_connect_phy(struct phylink *, struct phy_device *);
+ int phylink_of_phy_connect(struct phylink *, struct device_node *, u32 flags);
+ int phylink_fwnode_phy_connect(struct phylink *pl,
+-			       struct fwnode_handle *fwnode,
++			       const struct fwnode_handle *fwnode,
+ 			       u32 flags);
+ void phylink_disconnect_phy(struct phylink *);
+ 
diff --git a/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch b/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch
new file mode 100644
index 00000000000..2649634dc7b
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-14-v6.3-net-phy-constify-fwnode_get_phy_node-fwnode-argument.patch
@@ -0,0 +1,38 @@
+From 4a0faa02d419a6728abef0f1d8a32d8c35ef95e6 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 24 Mar 2023 09:23:53 +0000
+Subject: [PATCH] net: phy: constify fwnode_get_phy_node() fwnode argument
+
+fwnode_get_phy_node() does not motify the fwnode structure, so make
+the argument const,
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy_device.c | 2 +-
+ include/linux/phy.h          | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -3003,7 +3003,7 @@ EXPORT_SYMBOL_GPL(device_phy_find_device
+  * and "phy-device" are not supported in ACPI. DT supports all the three
+  * named references to the phy node.
+  */
+-struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode)
++struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode)
+ {
+ 	struct fwnode_handle *phy_node;
+ 
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1473,7 +1473,7 @@ int fwnode_get_phy_id(struct fwnode_hand
+ struct mdio_device *fwnode_mdio_find_device(struct fwnode_handle *fwnode);
+ struct phy_device *fwnode_phy_find_device(struct fwnode_handle *phy_fwnode);
+ struct phy_device *device_phy_find_device(struct device *dev);
+-struct fwnode_handle *fwnode_get_phy_node(struct fwnode_handle *fwnode);
++struct fwnode_handle *fwnode_get_phy_node(const struct fwnode_handle *fwnode);
+ struct phy_device *get_phy_device(struct mii_bus *bus, int addr, bool is_c45);
+ int phy_device_register(struct phy_device *phy);
+ void phy_device_free(struct phy_device *phydev);
diff --git a/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch b/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch
new file mode 100644
index 00000000000..5eba18b0260
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-15-v6.4-net-phylink-fix-ksettings_set-ethtool-call.patch
@@ -0,0 +1,44 @@
+From cc73de0411f7d3cdd157564a78f7a39058420ff8 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 13 May 2023 22:03:45 +0100
+Subject: [PATCH 13/21] net: phylink: fix ksettings_set() ethtool call
+
+While testing a Fiberstore SFP-10G-T module (which uses 10GBASE-R with
+rate adaption) in a Clearfog platform (which can't do that) it was
+found that the PHYs advertisement was not limited according to the
+hosts capabilities when using ethtool to change it.
+
+Fix this by ensuring that we mask the advertisement with the computed
+support mask as the very first thing we do.
+
+Fixes: cbc1bb1e4689 ("net: phylink: simplify phy case for ksettings_set method")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phylink.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -2226,6 +2226,10 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	ASSERT_RTNL();
+ 
++	/* Mask out unsupported advertisements */
++	linkmode_and(config.advertising, kset->link_modes.advertising,
++		     pl->supported);
++
+ 	if (pl->phydev) {
+ 		/* We can rely on phylib for this update; we also do not need
+ 		 * to update the pl->link_config settings:
+@@ -2250,10 +2254,6 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	config = pl->link_config;
+ 
+-	/* Mask out unsupported advertisements */
+-	linkmode_and(config.advertising, kset->link_modes.advertising,
+-		     pl->supported);
+-
+ 	/* FIXME: should we reject autoneg if phy/mac does not support it? */
+ 	switch (kset->base.autoneg) {
+ 	case AUTONEG_DISABLE:
diff --git a/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch b/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch
new file mode 100644
index 00000000000..79de6122b75
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-16-v6.5-net-sfp-add-support-for-setting-signalling-rate.patch
@@ -0,0 +1,149 @@
+From 0100d1c5789018ba77bf2f4fab3bd91ecece7b3b Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Wed, 17 May 2023 11:38:12 +0100
+Subject: [PATCH 14/21] net: sfp: add support for setting signalling rate
+
+Add support to the SFP layer to allow phylink to set the signalling
+rate for a SFP module. The rate given will be in units of kilo-baud
+(1000 baud).
+
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 24 ++++++++++++++++++++++++
+ drivers/net/phy/sfp-bus.c | 20 ++++++++++++++++++++
+ drivers/net/phy/sfp.c     |  5 +++++
+ drivers/net/phy/sfp.h     |  1 +
+ include/linux/sfp.h       |  6 ++++++
+ 5 files changed, 56 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -156,6 +156,23 @@ static const char *phylink_an_mode_str(u
+ 	return mode < ARRAY_SIZE(modestr) ? modestr[mode] : "unknown";
+ }
+ 
++static unsigned int phylink_interface_signal_rate(phy_interface_t interface)
++{
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_1000BASEX: /* 1.25Mbd */
++		return 1250;
++	case PHY_INTERFACE_MODE_2500BASEX: /* 3.125Mbd */
++		return 3125;
++	case PHY_INTERFACE_MODE_5GBASER: /* 5.15625Mbd */
++		return 5156;
++	case PHY_INTERFACE_MODE_10GBASER: /* 10.3125Mbd */
++		return 10313;
++	default:
++		return 0;
++	}
++}
++
+ /**
+  * phylink_interface_max_speed() - get the maximum speed of a phy interface
+  * @interface: phy interface mode defined by &typedef phy_interface_t
+@@ -1024,6 +1041,7 @@ static void phylink_major_config(struct
+ {
+ 	struct phylink_pcs *pcs = NULL;
+ 	bool pcs_changed = false;
++	unsigned int rate_kbd;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+@@ -1083,6 +1101,12 @@ static void phylink_major_config(struct
+ 				    ERR_PTR(err));
+ 	}
+ 
++	if (pl->sfp_bus) {
++		rate_kbd = phylink_interface_signal_rate(state->interface);
++		if (rate_kbd)
++			sfp_upstream_set_signal_rate(pl->sfp_bus, rate_kbd);
++	}
++
+ 	phylink_pcs_poll_start(pl);
+ }
+ 
+--- a/drivers/net/phy/sfp-bus.c
++++ b/drivers/net/phy/sfp-bus.c
+@@ -586,6 +586,26 @@ static void sfp_upstream_clear(struct sf
+ }
+ 
+ /**
++ * sfp_upstream_set_signal_rate() - set data signalling rate
++ * @bus: a pointer to the &struct sfp_bus structure for the sfp module
++ * @rate_kbd: signalling rate in units of 1000 baud
++ *
++ * Configure the rate select settings on the SFP module for the signalling
++ * rate (not the same as the data rate).
++ *
++ * Locks that may be held:
++ *  Phylink's state_mutex
++ *  rtnl lock
++ *  SFP's sm_mutex
++ */
++void sfp_upstream_set_signal_rate(struct sfp_bus *bus, unsigned int rate_kbd)
++{
++	if (bus->registered)
++		bus->socket_ops->set_signal_rate(bus->sfp, rate_kbd);
++}
++EXPORT_SYMBOL_GPL(sfp_upstream_set_signal_rate);
++
++/**
+  * sfp_bus_find_fwnode() - parse and locate the SFP bus from fwnode
+  * @fwnode: firmware node for the parent device (MAC or PHY)
+  *
+--- a/drivers/net/phy/sfp.c
++++ b/drivers/net/phy/sfp.c
+@@ -2474,6 +2474,10 @@ static void sfp_stop(struct sfp *sfp)
+ 	sfp_sm_event(sfp, SFP_E_DEV_DOWN);
+ }
+ 
++static void sfp_set_signal_rate(struct sfp *sfp, unsigned int rate_kbd)
++{
++}
++
+ static int sfp_module_info(struct sfp *sfp, struct ethtool_modinfo *modinfo)
+ {
+ 	/* locking... and check module is present */
+@@ -2552,6 +2556,7 @@ static const struct sfp_socket_ops sfp_m
+ 	.detach = sfp_detach,
+ 	.start = sfp_start,
+ 	.stop = sfp_stop,
++	.set_signal_rate = sfp_set_signal_rate,
+ 	.module_info = sfp_module_info,
+ 	.module_eeprom = sfp_module_eeprom,
+ 	.module_eeprom_by_page = sfp_module_eeprom_by_page,
+--- a/drivers/net/phy/sfp.h
++++ b/drivers/net/phy/sfp.h
+@@ -19,6 +19,7 @@ struct sfp_socket_ops {
+ 	void (*detach)(struct sfp *sfp);
+ 	void (*start)(struct sfp *sfp);
+ 	void (*stop)(struct sfp *sfp);
++	void (*set_signal_rate)(struct sfp *sfp, unsigned int rate_kbd);
+ 	int (*module_info)(struct sfp *sfp, struct ethtool_modinfo *modinfo);
+ 	int (*module_eeprom)(struct sfp *sfp, struct ethtool_eeprom *ee,
+ 			     u8 *data);
+--- a/include/linux/sfp.h
++++ b/include/linux/sfp.h
+@@ -547,6 +547,7 @@ int sfp_get_module_eeprom_by_page(struct
+ 				  struct netlink_ext_ack *extack);
+ void sfp_upstream_start(struct sfp_bus *bus);
+ void sfp_upstream_stop(struct sfp_bus *bus);
++void sfp_upstream_set_signal_rate(struct sfp_bus *bus, unsigned int rate_kbd);
+ void sfp_bus_put(struct sfp_bus *bus);
+ struct sfp_bus *sfp_bus_find_fwnode(const struct fwnode_handle *fwnode);
+ int sfp_bus_add_upstream(struct sfp_bus *bus, void *upstream,
+@@ -606,6 +607,11 @@ static inline void sfp_upstream_stop(str
+ {
+ }
+ 
++static inline void sfp_upstream_set_signal_rate(struct sfp_bus *bus,
++						unsigned int rate_kbd)
++{
++}
++
+ static inline void sfp_bus_put(struct sfp_bus *bus)
+ {
+ }
diff --git a/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch b/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch
new file mode 100644
index 00000000000..8a694c86daf
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-17-v6.5-net-phy-add-helpers-for-comparing-phy-IDs.patch
@@ -0,0 +1,147 @@
+From b84acdb07222a701bfc6403b374249c86f97d18d Mon Sep 17 00:00:00 2001
+From: Russell King <rmk+kernel@armlinux.org.uk>
+Date: Fri, 19 May 2023 14:03:59 +0100
+Subject: [PATCH 15/21] net: phy: add helpers for comparing phy IDs
+
+There are several places which open code comparing PHY IDs. Provide a
+couple of helpers to assist with this, using a slightly simpler test
+than the original:
+
+- phy_id_compare() compares two arbitary PHY IDs and a mask of the
+  significant bits in the ID.
+- phydev_id_compare() compares the bound phydev with the specified
+  PHY ID, using the bound driver's mask.
+
+Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/micrel.c     |  6 +++---
+ drivers/net/phy/phy_device.c | 16 +++++++---------
+ drivers/net/phy/phylink.c    |  4 ++--
+ include/linux/phy.h          | 28 ++++++++++++++++++++++++++++
+ 4 files changed, 40 insertions(+), 14 deletions(-)
+
+--- a/drivers/net/phy/micrel.c
++++ b/drivers/net/phy/micrel.c
+@@ -620,7 +620,7 @@ static int ksz8051_ksz8795_match_phy_dev
+ {
+ 	int ret;
+ 
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
++	if (!phy_id_compare(phydev->phy_id, PHY_ID_KSZ8051, MICREL_PHY_ID_MASK))
+ 		return 0;
+ 
+ 	ret = phy_read(phydev, MII_BMSR);
+@@ -1455,7 +1455,7 @@ static int ksz9x31_cable_test_fault_leng
+ 	 *
+ 	 * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
+ 	 */
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
++	if (phydev_id_compare(phydev, PHY_ID_KSZ9131))
+ 		dt = clamp(dt - 22, 0, 255);
+ 
+ 	return (dt * 400) / 10;
+@@ -1887,7 +1887,7 @@ static __always_inline int ksz886x_cable
+ 	 */
+ 	dt = FIELD_GET(data_mask, status);
+ 
+-	if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_LAN8814)
++	if (phydev_id_compare(phydev, PHY_ID_LAN8814))
+ 		return ((dt - 22) * 800) / 10;
+ 	else
+ 		return (dt * 400) / 10;
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -422,8 +422,7 @@ int phy_unregister_fixup(const char *bus
+ 		fixup = list_entry(pos, struct phy_fixup, list);
+ 
+ 		if ((!strcmp(fixup->bus_id, bus_id)) &&
+-		    ((fixup->phy_uid & phy_uid_mask) ==
+-		     (phy_uid & phy_uid_mask))) {
++		    phy_id_compare(fixup->phy_uid, phy_uid, phy_uid_mask)) {
+ 			list_del(&fixup->list);
+ 			kfree(fixup);
+ 			ret = 0;
+@@ -459,8 +458,8 @@ static int phy_needs_fixup(struct phy_de
+ 		if (strcmp(fixup->bus_id, PHY_ANY_ID) != 0)
+ 			return 0;
+ 
+-	if ((fixup->phy_uid & fixup->phy_uid_mask) !=
+-	    (phydev->phy_id & fixup->phy_uid_mask))
++	if (!phy_id_compare(phydev->phy_id, fixup->phy_uid,
++			    fixup->phy_uid_mask))
+ 		if (fixup->phy_uid != PHY_ANY_UID)
+ 			return 0;
+ 
+@@ -507,15 +506,14 @@ static int phy_bus_match(struct device *
+ 			if (phydev->c45_ids.device_ids[i] == 0xffffffff)
+ 				continue;
+ 
+-			if ((phydrv->phy_id & phydrv->phy_id_mask) ==
+-			    (phydev->c45_ids.device_ids[i] &
+-			     phydrv->phy_id_mask))
++			if (phy_id_compare(phydev->c45_ids.device_ids[i],
++					   phydrv->phy_id, phydrv->phy_id_mask))
+ 				return 1;
+ 		}
+ 		return 0;
+ 	} else {
+-		return (phydrv->phy_id & phydrv->phy_id_mask) ==
+-			(phydev->phy_id & phydrv->phy_id_mask);
++		return phy_id_compare(phydev->phy_id, phydrv->phy_id,
++				      phydrv->phy_id_mask);
+ 	}
+ }
+ 
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3151,8 +3151,8 @@ static void phylink_sfp_link_up(void *up
+  */
+ static bool phylink_phy_no_inband(struct phy_device *phy)
+ {
+-	return phy->is_c45 &&
+-		(phy->c45_ids.device_ids[1] & 0xfffffff0) == 0xae025150;
++	return phy->is_c45 && phy_id_compare(phy->c45_ids.device_ids[1],
++					     0xae025150, 0xfffffff0);
+ }
+ 
+ static int phylink_sfp_connect_phy(void *upstream, struct phy_device *phy)
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -993,6 +993,34 @@ struct phy_driver {
+ #define PHY_ID_MATCH_MODEL(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 4)
+ #define PHY_ID_MATCH_VENDOR(id) .phy_id = (id), .phy_id_mask = GENMASK(31, 10)
+ 
++/**
++ * phy_id_compare - compare @id1 with @id2 taking account of @mask
++ * @id1: first PHY ID
++ * @id2: second PHY ID
++ * @mask: the PHY ID mask, set bits are significant in matching
++ *
++ * Return true if the bits from @id1 and @id2 specified by @mask match.
++ * This uses an equivalent test to (@id & @mask) == (@phy_id & @mask).
++ */
++static inline bool phy_id_compare(u32 id1, u32 id2, u32 mask)
++{
++	return !((id1 ^ id2) & mask);
++}
++
++/**
++ * phydev_id_compare - compare @id with the PHY's Clause 22 ID
++ * @phydev: the PHY device
++ * @id: the PHY ID to be matched
++ *
++ * Compare the @phydev clause 22 ID with the provided @id and return true or
++ * false depending whether it matches, using the bound driver mask. The
++ * @phydev must be bound to a driver.
++ */
++static inline bool phydev_id_compare(struct phy_device *phydev, u32 id)
++{
++	return phy_id_compare(id, phydev->phy_id, phydev->drv->phy_id_mask);
++}
++
+ /* A Structure for boards to register fixups with the PHY Lib */
+ struct phy_fixup {
+ 	struct list_head list;
diff --git a/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch b/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch
new file mode 100644
index 00000000000..5970355a6c2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-18-v6.5-net-phylink-require-supported_interfaces-to-be-fille.patch
@@ -0,0 +1,71 @@
+From 441e1e44301fc5762a06737f8ec04bf1ce3fb039 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Sat, 20 May 2023 11:41:42 +0100
+Subject: [PATCH 16/21] net: phylink: require supported_interfaces to be filled
+
+We have been requiring the supported_interfaces bitmap to be filled in
+by MAC drivers that have a mac_select_pcs() method. Now that all MAC
+drivers fill in the supported_interfaces bitmap, it is time to enforce
+this. We have already required supported_interfaces to be set in order
+for optical SFPs to be configured in commit f81fa96d8a6c ("net: phylink:
+use phy_interface_t bitmaps for optical modules").
+
+Refuse phylink creation if supported_interfaces is empty, and remove
+code to deal with cases where this mask is empty.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/E1q0K1u-006EIP-ET@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 26 +++++++++++---------------
+ 1 file changed, 11 insertions(+), 15 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -710,14 +710,11 @@ static int phylink_validate(struct phyli
+ {
+ 	const unsigned long *interfaces = pl->config->supported_interfaces;
+ 
+-	if (!phy_interface_empty(interfaces)) {
+-		if (state->interface == PHY_INTERFACE_MODE_NA)
+-			return phylink_validate_mask(pl, supported, state,
+-						     interfaces);
++	if (state->interface == PHY_INTERFACE_MODE_NA)
++		return phylink_validate_mask(pl, supported, state, interfaces);
+ 
+-		if (!test_bit(state->interface, interfaces))
+-			return -EINVAL;
+-	}
++	if (!test_bit(state->interface, interfaces))
++		return -EINVAL;
+ 
+ 	return phylink_validate_mac_and_pcs(pl, supported, state);
+ }
+@@ -1512,19 +1509,18 @@ struct phylink *phylink_create(struct ph
+ 	struct phylink *pl;
+ 	int ret;
+ 
+-	if (mac_ops->mac_select_pcs &&
+-	    mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
+-	      ERR_PTR(-EOPNOTSUPP))
+-		using_mac_select_pcs = true;
+-
+ 	/* Validate the supplied configuration */
+-	if (using_mac_select_pcs &&
+-	    phy_interface_empty(config->supported_interfaces)) {
++	if (phy_interface_empty(config->supported_interfaces)) {
+ 		dev_err(config->dev,
+-			"phylink: error: empty supported_interfaces but mac_select_pcs() method present\n");
++			"phylink: error: empty supported_interfaces\n");
+ 		return ERR_PTR(-EINVAL);
+ 	}
+ 
++	if (mac_ops->mac_select_pcs &&
++	    mac_ops->mac_select_pcs(config, PHY_INTERFACE_MODE_NA) !=
++	      ERR_PTR(-EOPNOTSUPP))
++		using_mac_select_pcs = true;
++
+ 	pl = kzalloc(sizeof(*pl), GFP_KERNEL);
+ 	if (!pl)
+ 		return ERR_PTR(-ENOMEM);
diff --git a/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch b/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch
new file mode 100644
index 00000000000..3a26b4b6006
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-19-v6.5-net-phylink-remove-duplicated-linkmode-pause-resolut.patch
@@ -0,0 +1,64 @@
+From 4b624a39f2ab523ca6a6ad9448fab1deb7b101e2 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 11:15:53 +0100
+Subject: [PATCH 17/21] net: phylink: remove duplicated linkmode pause
+ resolution
+
+Phylink had two chunks of code virtually the same for resolving the
+negotiated pause modes. Factor this down to one function.
+
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 15 ++++-----------
+ 1 file changed, 4 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -976,11 +976,10 @@ static void phylink_apply_manual_flow(st
+ 		state->pause = pl->link_config.pause;
+ }
+ 
+-static void phylink_resolve_flow(struct phylink_link_state *state)
++static void phylink_resolve_an_pause(struct phylink_link_state *state)
+ {
+ 	bool tx_pause, rx_pause;
+ 
+-	state->pause = MLO_PAUSE_NONE;
+ 	if (state->duplex == DUPLEX_FULL) {
+ 		linkmode_resolve_pause(state->advertising,
+ 				       state->lp_advertising,
+@@ -1192,7 +1191,8 @@ static void phylink_get_fixed_state(stru
+ 	else if (pl->link_gpio)
+ 		state->link = !!gpiod_get_value_cansleep(pl->link_gpio);
+ 
+-	phylink_resolve_flow(state);
++	state->pause = MLO_PAUSE_NONE;
++	phylink_resolve_an_pause(state);
+ }
+ 
+ static void phylink_mac_initial_config(struct phylink *pl, bool force_restart)
+@@ -3215,7 +3215,6 @@ static const struct sfp_upstream_ops sfp
+ static void phylink_decode_c37_word(struct phylink_link_state *state,
+ 				    uint16_t config_reg, int speed)
+ {
+-	bool tx_pause, rx_pause;
+ 	int fd_bit;
+ 
+ 	if (speed == SPEED_2500)
+@@ -3234,13 +3233,7 @@ static void phylink_decode_c37_word(stru
+ 		state->link = false;
+ 	}
+ 
+-	linkmode_resolve_pause(state->advertising, state->lp_advertising,
+-			       &tx_pause, &rx_pause);
+-
+-	if (tx_pause)
+-		state->pause |= MLO_PAUSE_TX;
+-	if (rx_pause)
+-		state->pause |= MLO_PAUSE_RX;
++	phylink_resolve_an_pause(state);
+ }
+ 
+ static void phylink_decode_sgmii_word(struct phylink_link_state *state,
diff --git a/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch b/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch
new file mode 100644
index 00000000000..2b2634f80c0
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-20-v6.5-net-phylink-add-function-to-resolve-clause-73-negoti.patch
@@ -0,0 +1,76 @@
+From aa8b6bd2b1f235b262bd27f317a0516f196c2c6a Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 11:15:58 +0100
+Subject: [PATCH 18/21] net: phylink: add function to resolve clause 73
+ negotiation
+
+Add a function to resolve clause 73 negotiation according to the
+priority resolution function described in clause 73.3.6.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 39 +++++++++++++++++++++++++++++++++++++++
+ include/linux/phylink.h   |  2 ++
+ 2 files changed, 41 insertions(+)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3212,6 +3212,45 @@ static const struct sfp_upstream_ops sfp
+ 
+ /* Helpers for MAC drivers */
+ 
++static struct {
++	int bit;
++	int speed;
++} phylink_c73_priority_resolution[] = {
++	{ ETHTOOL_LINK_MODE_100000baseCR4_Full_BIT, SPEED_100000 },
++	{ ETHTOOL_LINK_MODE_100000baseKR4_Full_BIT, SPEED_100000 },
++	/* 100GBASE-KP4 and 100GBASE-CR10 not supported */
++	{ ETHTOOL_LINK_MODE_40000baseCR4_Full_BIT, SPEED_40000 },
++	{ ETHTOOL_LINK_MODE_40000baseKR4_Full_BIT, SPEED_40000 },
++	{ ETHTOOL_LINK_MODE_10000baseKR_Full_BIT, SPEED_10000 },
++	{ ETHTOOL_LINK_MODE_10000baseKX4_Full_BIT, SPEED_10000 },
++	/* 5GBASE-KR not supported */
++	{ ETHTOOL_LINK_MODE_2500baseX_Full_BIT, SPEED_2500 },
++	{ ETHTOOL_LINK_MODE_1000baseKX_Full_BIT, SPEED_1000 },
++};
++
++void phylink_resolve_c73(struct phylink_link_state *state)
++{
++	int i;
++
++	for (i = 0; i < ARRAY_SIZE(phylink_c73_priority_resolution); i++) {
++		int bit = phylink_c73_priority_resolution[i].bit;
++		if (linkmode_test_bit(bit, state->advertising) &&
++		    linkmode_test_bit(bit, state->lp_advertising))
++			break;
++	}
++
++	if (i < ARRAY_SIZE(phylink_c73_priority_resolution)) {
++		state->speed = phylink_c73_priority_resolution[i].speed;
++		state->duplex = DUPLEX_FULL;
++	} else {
++		/* negotiation failure */
++		state->link = false;
++	}
++
++	phylink_resolve_an_pause(state);
++}
++EXPORT_SYMBOL_GPL(phylink_resolve_c73);
++
+ static void phylink_decode_c37_word(struct phylink_link_state *state,
+ 				    uint16_t config_reg, int speed)
+ {
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -656,6 +656,8 @@ int phylink_mii_c22_pcs_config(struct md
+ 			       const unsigned long *advertising);
+ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
+ 
++void phylink_resolve_c73(struct phylink_link_state *state);
++
+ void phylink_mii_c45_pcs_get_state(struct mdio_device *pcs,
+ 				   struct phylink_link_state *state);
+ 
diff --git a/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch b/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch
new file mode 100644
index 00000000000..eea99a5d782
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-21-v6.5-net-phylink-provide-phylink_pcs_config-and-phylink_p.patch
@@ -0,0 +1,100 @@
+From 796d709363135a6bd6a8ccc07b509c939e5b855f Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 23 May 2023 16:31:50 +0100
+Subject: [PATCH 19/21] net: phylink: provide phylink_pcs_config() and
+ phylink_pcs_link_up()
+
+Add two helper functions for calling PCS methods. phylink_pcs_config()
+allows us to handle PCS configuration specifics in one location, rather
+than the two call sites. phylink_pcs_link_up() gives us consistency.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1q1TzK-007Exd-Rs@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 53 ++++++++++++++++++++++++---------------
+ 1 file changed, 33 insertions(+), 20 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -991,6 +991,25 @@ static void phylink_resolve_an_pause(str
+ 	}
+ }
+ 
++static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++			      const struct phylink_link_state *state,
++			      bool permit_pause_to_mac)
++{
++	if (!pcs)
++		return 0;
++
++	return pcs->ops->pcs_config(pcs, mode, state->interface,
++				    state->advertising, permit_pause_to_mac);
++}
++
++static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++				phy_interface_t interface, int speed,
++				int duplex)
++{
++	if (pcs && pcs->ops->pcs_link_up)
++		pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
++}
++
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+ {
+ 	if (pl->cfg_link_an_mode == MLO_AN_INBAND)
+@@ -1074,18 +1093,15 @@ static void phylink_major_config(struct
+ 
+ 	phylink_mac_config(pl, state);
+ 
+-	if (pl->pcs) {
+-		err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+-					       state->interface,
+-					       state->advertising,
+-					       !!(pl->link_config.pause &
+-						  MLO_PAUSE_AN));
+-		if (err < 0)
+-			phylink_err(pl, "pcs_config failed: %pe\n",
+-				    ERR_PTR(err));
+-		if (err > 0)
+-			restart = true;
+-	}
++	err = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode, state,
++				 !!(pl->link_config.pause &
++				    MLO_PAUSE_AN));
++	if (err < 0)
++		phylink_err(pl, "pcs_config failed: %pe\n",
++			    ERR_PTR(err));
++	else if (err > 0)
++		restart = true;
++
+ 	if (restart)
+ 		phylink_mac_pcs_an_restart(pl);
+ 
+@@ -1136,11 +1152,9 @@ static int phylink_change_inband_advert(
+ 	 * restart negotiation if the pcs_config() helper indicates that
+ 	 * the programmed advertisement has changed.
+ 	 */
+-	ret = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
+-				       pl->link_config.interface,
+-				       pl->link_config.advertising,
+-				       !!(pl->link_config.pause &
+-					  MLO_PAUSE_AN));
++	ret = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode,
++				 &pl->link_config,
++				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1272,9 +1286,8 @@ static void phylink_link_up(struct phyli
+ 
+ 	pl->cur_interface = link_state.interface;
+ 
+-	if (pl->pcs && pl->pcs->ops->pcs_link_up)
+-		pl->pcs->ops->pcs_link_up(pl->pcs, pl->cur_link_an_mode,
+-					  pl->cur_interface, speed, duplex);
++	phylink_pcs_link_up(pl->pcs, pl->cur_link_an_mode, pl->cur_interface,
++			    speed, duplex);
+ 
+ 	pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
+ 				 pl->cur_interface, speed, duplex,
diff --git a/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch b/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch
new file mode 100644
index 00000000000..2f7f7a5737f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-23-v6.4-net-phylink-actually-fix-ksettings_set-ethtool-call.patch
@@ -0,0 +1,55 @@
+From 11933aa76865621d8e82553c8f3bc07796a5aaa2 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Thu, 1 Jun 2023 10:12:06 +0100
+Subject: [PATCH 20/21] net: phylink: actually fix ksettings_set() ethtool call
+
+Raju Lakkaraju reported that the below commit caused a regression
+with Lan743x drivers and a 2.5G SFP. Sadly, this is because the commit
+was utterly wrong. Let's fix this properly by not moving the
+linkmode_and(), but instead copying the link ksettings and then
+modifying the advertising mask before passing the modified link
+ksettings to phylib.
+
+Fixes: df0acdc59b09 ("net: phylink: fix ksettings_set() ethtool call")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1q4eLm-00Ayxk-GZ@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 15 ++++++++++-----
+ 1 file changed, 10 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -2259,11 +2259,13 @@ int phylink_ethtool_ksettings_set(struct
+ 
+ 	ASSERT_RTNL();
+ 
+-	/* Mask out unsupported advertisements */
+-	linkmode_and(config.advertising, kset->link_modes.advertising,
+-		     pl->supported);
+-
+ 	if (pl->phydev) {
++		struct ethtool_link_ksettings phy_kset = *kset;
++
++		linkmode_and(phy_kset.link_modes.advertising,
++			     phy_kset.link_modes.advertising,
++			     pl->supported);
++
+ 		/* We can rely on phylib for this update; we also do not need
+ 		 * to update the pl->link_config settings:
+ 		 * - the configuration returned via ksettings_get() will come
+@@ -2282,10 +2284,13 @@ int phylink_ethtool_ksettings_set(struct
+ 		 *   the presence of a PHY, this should not be changed as that
+ 		 *   should be determined from the media side advertisement.
+ 		 */
+-		return phy_ethtool_ksettings_set(pl->phydev, kset);
++		return phy_ethtool_ksettings_set(pl->phydev, &phy_kset);
+ 	}
+ 
+ 	config = pl->link_config;
++	/* Mask out unsupported advertisements */
++	linkmode_and(config.advertising, kset->link_modes.advertising,
++		     pl->supported);
+ 
+ 	/* FIXME: should we reject autoneg if phy/mac does not support it? */
+ 	switch (kset->base.autoneg) {
diff --git a/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch b/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch
new file mode 100644
index 00000000000..e1a8539aae4
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-24-v6.5-net-phylink-add-PCS-negotiation-mode.patch
@@ -0,0 +1,324 @@
+From 79b07c3e9c4a2272927be8848c26b372516e1958 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:22 +0100
+Subject: [PATCH 21/21] net: phylink: add PCS negotiation mode
+
+PCS have to work out whether they should enable PCS negotiation by
+looking at the "mode" and "interface" arguments, and the Autoneg bit
+in the advertising mask.
+
+This leads to some complex logic, so lets pull that out into phylink
+and instead pass a "neg_mode" argument to the PCS configuration and
+link up methods, instead of the "mode" argument.
+
+In order to transition drivers, add a "neg_mode" flag to the phylink
+PCS structure to PCS can indicate whether they want to be passed the
+neg_mode or the old mode argument.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8De-00EaFA-Ht@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c |  45 +++++++++++++----
+ include/linux/phylink.h   | 104 +++++++++++++++++++++++++++++++++++---
+ 2 files changed, 132 insertions(+), 17 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -71,6 +71,7 @@ struct phylink {
+ 	struct mutex state_mutex;
+ 	struct phylink_link_state phy_state;
+ 	struct work_struct resolve;
++	unsigned int pcs_neg_mode;
+ 
+ 	bool mac_link_dropped;
+ 	bool using_mac_select_pcs;
+@@ -991,23 +992,23 @@ static void phylink_resolve_an_pause(str
+ 	}
+ }
+ 
+-static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      const struct phylink_link_state *state,
+ 			      bool permit_pause_to_mac)
+ {
+ 	if (!pcs)
+ 		return 0;
+ 
+-	return pcs->ops->pcs_config(pcs, mode, state->interface,
++	return pcs->ops->pcs_config(pcs, neg_mode, state->interface,
+ 				    state->advertising, permit_pause_to_mac);
+ }
+ 
+-static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++static void phylink_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface, int speed,
+ 				int duplex)
+ {
+ 	if (pcs && pcs->ops->pcs_link_up)
+-		pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex);
++		pcs->ops->pcs_link_up(pcs, neg_mode, interface, speed, duplex);
+ }
+ 
+ static void phylink_pcs_poll_stop(struct phylink *pl)
+@@ -1057,10 +1058,15 @@ static void phylink_major_config(struct
+ 	struct phylink_pcs *pcs = NULL;
+ 	bool pcs_changed = false;
+ 	unsigned int rate_kbd;
++	unsigned int neg_mode;
+ 	int err;
+ 
+ 	phylink_dbg(pl, "major config %s\n", phy_modes(state->interface));
+ 
++	pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
++						state->interface,
++						state->advertising);
++
+ 	if (pl->using_mac_select_pcs) {
+ 		pcs = pl->mac_ops->mac_select_pcs(pl->config, state->interface);
+ 		if (IS_ERR(pcs)) {
+@@ -1093,9 +1099,12 @@ static void phylink_major_config(struct
+ 
+ 	phylink_mac_config(pl, state);
+ 
+-	err = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode, state,
+-				 !!(pl->link_config.pause &
+-				    MLO_PAUSE_AN));
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs && pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
++	err = phylink_pcs_config(pl->pcs, neg_mode, state,
++				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (err < 0)
+ 		phylink_err(pl, "pcs_config failed: %pe\n",
+ 			    ERR_PTR(err));
+@@ -1130,6 +1139,7 @@ static void phylink_major_config(struct
+  */
+ static int phylink_change_inband_advert(struct phylink *pl)
+ {
++	unsigned int neg_mode;
+ 	int ret;
+ 
+ 	if (test_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state))
+@@ -1148,12 +1158,20 @@ static int phylink_change_inband_advert(
+ 		    __ETHTOOL_LINK_MODE_MASK_NBITS, pl->link_config.advertising,
+ 		    pl->link_config.pause);
+ 
++	/* Recompute the PCS neg mode */
++	pl->pcs_neg_mode = phylink_pcs_neg_mode(pl->cur_link_an_mode,
++					pl->link_config.interface,
++					pl->link_config.advertising);
++
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
+ 	/* Modern PCS-based method; update the advert at the PCS, and
+ 	 * restart negotiation if the pcs_config() helper indicates that
+ 	 * the programmed advertisement has changed.
+ 	 */
+-	ret = phylink_pcs_config(pl->pcs, pl->cur_link_an_mode,
+-				 &pl->link_config,
++	ret = phylink_pcs_config(pl->pcs, neg_mode, &pl->link_config,
+ 				 !!(pl->link_config.pause & MLO_PAUSE_AN));
+ 	if (ret < 0)
+ 		return ret;
+@@ -1256,6 +1274,7 @@ static void phylink_link_up(struct phyli
+ 			    struct phylink_link_state link_state)
+ {
+ 	struct net_device *ndev = pl->netdev;
++	unsigned int neg_mode;
+ 	int speed, duplex;
+ 	bool rx_pause;
+ 
+@@ -1286,8 +1305,12 @@ static void phylink_link_up(struct phyli
+ 
+ 	pl->cur_interface = link_state.interface;
+ 
+-	phylink_pcs_link_up(pl->pcs, pl->cur_link_an_mode, pl->cur_interface,
+-			    speed, duplex);
++	neg_mode = pl->cur_link_an_mode;
++	if (pl->pcs && pl->pcs->neg_mode)
++		neg_mode = pl->pcs_neg_mode;
++
++	phylink_pcs_link_up(pl->pcs, neg_mode, pl->cur_interface, speed,
++			    duplex);
+ 
+ 	pl->mac_ops->mac_link_up(pl->config, pl->phydev, pl->cur_link_an_mode,
+ 				 pl->cur_interface, speed, duplex,
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -21,6 +21,24 @@ enum {
+ 	MLO_AN_FIXED,	/* Fixed-link mode */
+ 	MLO_AN_INBAND,	/* In-band protocol */
+ 
++	/* PCS "negotiation" mode.
++	 *  PHYLINK_PCS_NEG_NONE - protocol has no inband capability
++	 *  PHYLINK_PCS_NEG_OUTBAND - some out of band or fixed link setting
++	 *  PHYLINK_PCS_NEG_INBAND_DISABLED - inband mode disabled, e.g.
++	 *				      1000base-X with autoneg off
++	 *  PHYLINK_PCS_NEG_INBAND_ENABLED - inband mode enabled
++	 * Additionally, this can be tested using bitmasks:
++	 *  PHYLINK_PCS_NEG_INBAND - inband mode selected
++	 *  PHYLINK_PCS_NEG_ENABLED - negotiation mode enabled
++	 */
++	PHYLINK_PCS_NEG_NONE = 0,
++	PHYLINK_PCS_NEG_ENABLED = BIT(4),
++	PHYLINK_PCS_NEG_OUTBAND = BIT(5),
++	PHYLINK_PCS_NEG_INBAND = BIT(6),
++	PHYLINK_PCS_NEG_INBAND_DISABLED = PHYLINK_PCS_NEG_INBAND,
++	PHYLINK_PCS_NEG_INBAND_ENABLED = PHYLINK_PCS_NEG_INBAND |
++					 PHYLINK_PCS_NEG_ENABLED,
++
+ 	/* MAC_SYM_PAUSE and MAC_ASYM_PAUSE are used when configuring our
+ 	 * autonegotiation advertisement. They correspond to the PAUSE and
+ 	 * ASM_DIR bits defined by 802.3, respectively.
+@@ -80,6 +98,70 @@ static inline bool phylink_autoneg_inban
+ }
+ 
+ /**
++ * phylink_pcs_neg_mode() - helper to determine PCS inband mode
++ * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @interface: interface mode to be used
++ * @advertising: adertisement ethtool link mode mask
++ *
++ * Determines the negotiation mode to be used by the PCS, and returns
++ * one of:
++ * %PHYLINK_PCS_NEG_NONE: interface mode does not support inband
++ * %PHYLINK_PCS_NEG_OUTBAND: an out of band mode (e.g. reading the PHY)
++ *   will be used.
++ * %PHYLINK_PCS_NEG_INBAND_DISABLED: inband mode selected but autoneg disabled
++ * %PHYLINK_PCS_NEG_INBAND_ENABLED: inband mode selected and autoneg enabled
++ *
++ * Note: this is for cases where the PCS itself is involved in negotiation
++ * (e.g. Clause 37, SGMII and similar) not Clause 73.
++ */
++static inline unsigned int phylink_pcs_neg_mode(unsigned int mode,
++						phy_interface_t interface,
++						const unsigned long *advertising)
++{
++	unsigned int neg_mode;
++
++	switch (interface) {
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_QSGMII:
++	case PHY_INTERFACE_MODE_QUSGMII:
++	case PHY_INTERFACE_MODE_USXGMII:
++		/* These protocols are designed for use with a PHY which
++		 * communicates its negotiation result back to the MAC via
++		 * inband communication. Note: there exist PHYs that run
++		 * with SGMII but do not send the inband data.
++		 */
++		if (!phylink_autoneg_inband(mode))
++			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++		else
++			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++		break;
++
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++		/* 1000base-X is designed for use media-side for Fibre
++		 * connections, and thus the Autoneg bit needs to be
++		 * taken into account. We also do this for 2500base-X
++		 * as well, but drivers may not support this, so may
++		 * need to override this.
++		 */
++		if (!phylink_autoneg_inband(mode))
++			neg_mode = PHYLINK_PCS_NEG_OUTBAND;
++		else if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++					   advertising))
++			neg_mode = PHYLINK_PCS_NEG_INBAND_ENABLED;
++		else
++			neg_mode = PHYLINK_PCS_NEG_INBAND_DISABLED;
++		break;
++
++	default:
++		neg_mode = PHYLINK_PCS_NEG_NONE;
++		break;
++	}
++
++	return neg_mode;
++}
++
++/**
+  * struct phylink_link_state - link state structure
+  * @advertising: ethtool bitmask containing advertised link modes
+  * @lp_advertising: ethtool bitmask containing link partner advertised link
+@@ -436,6 +518,7 @@ struct phylink_pcs_ops;
+ /**
+  * struct phylink_pcs - PHYLINK PCS instance
+  * @ops: a pointer to the &struct phylink_pcs_ops structure
++ * @neg_mode: provide PCS neg mode via "mode" argument
+  * @poll: poll the PCS for link changes
+  *
+  * This structure is designed to be embedded within the PCS private data,
+@@ -443,6 +526,7 @@ struct phylink_pcs_ops;
+  */
+ struct phylink_pcs {
+ 	const struct phylink_pcs_ops *ops;
++	bool neg_mode;
+ 	bool poll;
+ };
+ 
+@@ -460,12 +544,12 @@ struct phylink_pcs_ops {
+ 			    const struct phylink_link_state *state);
+ 	void (*pcs_get_state)(struct phylink_pcs *pcs,
+ 			      struct phylink_link_state *state);
+-	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
++	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			  phy_interface_t interface,
+ 			  const unsigned long *advertising,
+ 			  bool permit_pause_to_mac);
+ 	void (*pcs_an_restart)(struct phylink_pcs *pcs);
+-	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int mode,
++	void (*pcs_link_up)(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			    phy_interface_t interface, int speed, int duplex);
+ };
+ 
+@@ -508,7 +592,7 @@ void pcs_get_state(struct phylink_pcs *p
+ /**
+  * pcs_config() - Configure the PCS mode and advertisement
+  * @pcs: a pointer to a &struct phylink_pcs.
+- * @mode: one of %MLO_AN_FIXED, %MLO_AN_PHY, %MLO_AN_INBAND.
++ * @neg_mode: link negotiation mode (see below)
+  * @interface: interface mode to be used
+  * @advertising: adertisement ethtool link mode mask
+  * @permit_pause_to_mac: permit forwarding pause resolution to MAC
+@@ -526,8 +610,12 @@ void pcs_get_state(struct phylink_pcs *p
+  * For 1000BASE-X, the advertisement should be programmed into the PCS.
+  *
+  * For most 10GBASE-R, there is no advertisement.
++ *
++ * The %neg_mode argument should be tested via the phylink_mode_*() family of
++ * functions, or for PCS that set pcs->neg_mode true, should be tested
++ * against the %PHYLINK_PCS_NEG_* definitions.
+  */
+-int pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++int pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 	       phy_interface_t interface, const unsigned long *advertising,
+ 	       bool permit_pause_to_mac);
+ 
+@@ -543,7 +631,7 @@ void pcs_an_restart(struct phylink_pcs *
+ /**
+  * pcs_link_up() - program the PCS for the resolved link configuration
+  * @pcs: a pointer to a &struct phylink_pcs.
+- * @mode: link autonegotiation mode
++ * @neg_mode: link negotiation mode (see below)
+  * @interface: link &typedef phy_interface_t mode
+  * @speed: link speed
+  * @duplex: link duplex
+@@ -552,8 +640,12 @@ void pcs_an_restart(struct phylink_pcs *
+  * the resolved link parameters. For example, a PCS operating in SGMII
+  * mode without in-band AN needs to be manually configured for the link
+  * and duplex setting. Otherwise, this should be a no-op.
++ *
++ * The %mode argument should be tested via the phylink_mode_*() family of
++ * functions, or for PCS that set pcs->neg_mode true, should be tested
++ * against the %PHYLINK_PCS_NEG_* definitions.
+  */
+-void pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
++void pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 		 phy_interface_t interface, int speed, int duplex);
+ #endif
+ 
diff --git a/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch b/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch
new file mode 100644
index 00000000000..473e9d5836d
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-25-v6.5-net-phylink-convert-phylink_mii_c22_pcs_config-to-ne.patch
@@ -0,0 +1,45 @@
+From cdb08aa0473730315dbc088d5394e59622314034 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:27 +0100
+Subject: [PATCH 1/2] net: phylink: convert phylink_mii_c22_pcs_config() to
+ neg_mode
+
+Use phylink_pcs_neg_mode() for phylink_mii_c22_pcs_config(). This
+results in no functional change.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Dj-00EaFG-Mt@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phylink.c | 9 ++++-----
+ 1 file changed, 4 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3558,6 +3558,7 @@ int phylink_mii_c22_pcs_config(struct md
+ 			       phy_interface_t interface,
+ 			       const unsigned long *advertising)
+ {
++	unsigned int neg_mode;
+ 	bool changed = 0;
+ 	u16 bmcr;
+ 	int ret, adv;
+@@ -3571,15 +3572,13 @@ int phylink_mii_c22_pcs_config(struct md
+ 		changed = ret;
+ 	}
+ 
+-	/* Ensure ISOLATE bit is disabled */
+-	if (mode == MLO_AN_INBAND &&
+-	    (interface == PHY_INTERFACE_MODE_SGMII ||
+-	     interface == PHY_INTERFACE_MODE_QSGMII ||
+-	     linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, advertising)))
++	neg_mode = phylink_pcs_neg_mode(mode, interface, advertising);
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ 		bmcr = BMCR_ANENABLE;
+ 	else
+ 		bmcr = 0;
+ 
++	/* Configure the inband state. Ensure ISOLATE bit is disabled */
+ 	ret = mdiodev_modify(pcs, MII_BMCR, BMCR_ANENABLE | BMCR_ISOLATE, bmcr);
+ 	if (ret < 0)
+ 		return ret;
diff --git a/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch
new file mode 100644
index 00000000000..5572850e95a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-26-v6.5-net-phylink-pass-neg_mode-into-phylink_mii_c22_pcs_c.patch
@@ -0,0 +1,187 @@
+From febf2aaf05641f3258cc30e072aff65cffc7c82c Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:32 +0100
+Subject: [PATCH 2/2] net: phylink: pass neg_mode into
+ phylink_mii_c22_pcs_config()
+
+Convert fman_dtsec, xilinx_axienet and pcs-lynx to pass the neg_mode
+into phylink_mii_c22_pcs_config(). Where appropriate, drivers are
+updated to have neg_mode passed into their pcs_config() and
+pcs_link_up() functions. For other drivers, we just hoist the call
+to phylink_pcs_neg_mode() to their pcs_config() method out of
+phylink_mii_c22_pcs_config().
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Do-00EaFM-Ra@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ .../net/ethernet/freescale/fman/fman_dtsec.c   |  7 ++++---
+ .../net/ethernet/xilinx/xilinx_axienet_main.c  |  6 ++++--
+ drivers/net/pcs/pcs-lynx.c                     | 18 ++++++++++++------
+ drivers/net/phy/phylink.c                      |  9 ++++-----
+ include/linux/phylink.h                        |  5 +++--
+ 5 files changed, 27 insertions(+), 18 deletions(-)
+
+--- a/drivers/net/ethernet/freescale/fman/fman_dtsec.c
++++ b/drivers/net/ethernet/freescale/fman/fman_dtsec.c
+@@ -763,15 +763,15 @@ static void dtsec_pcs_get_state(struct p
+ 	phylink_mii_c22_pcs_get_state(dtsec->tbidev, state);
+ }
+ 
+-static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int dtsec_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			    phy_interface_t interface,
+ 			    const unsigned long *advertising,
+ 			    bool permit_pause_to_mac)
+ {
+ 	struct fman_mac *dtsec = pcs_to_dtsec(pcs);
+ 
+-	return phylink_mii_c22_pcs_config(dtsec->tbidev, mode, interface,
+-					  advertising);
++	return phylink_mii_c22_pcs_config(dtsec->tbidev, interface,
++					  advertising, neg_mode);
+ }
+ 
+ static void dtsec_pcs_an_restart(struct phylink_pcs *pcs)
+@@ -1447,6 +1447,7 @@ int dtsec_initialization(struct mac_devi
+ 		goto _return_fm_mac_free;
+ 	}
+ 	dtsec->pcs.ops = &dtsec_pcs_ops;
++	dtsec->pcs.neg_mode = true;
+ 	dtsec->pcs.poll = true;
+ 
+ 	supported = mac_dev->phylink_config.supported_interfaces;
+--- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
++++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
+@@ -1631,7 +1631,7 @@ static void axienet_pcs_an_restart(struc
+ 	phylink_mii_c22_pcs_an_restart(pcs_phy);
+ }
+ 
+-static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
++static int axienet_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      phy_interface_t interface,
+ 			      const unsigned long *advertising,
+ 			      bool permit_pause_to_mac)
+@@ -1653,7 +1653,8 @@ static int axienet_pcs_config(struct phy
+ 		}
+ 	}
+ 
+-	ret = phylink_mii_c22_pcs_config(pcs_phy, mode, interface, advertising);
++	ret = phylink_mii_c22_pcs_config(pcs_phy, interface, advertising,
++					 neg_mode);
+ 	if (ret < 0)
+ 		netdev_warn(ndev, "Failed to configure PCS: %d\n", ret);
+ 
+@@ -2129,6 +2130,7 @@ static int axienet_probe(struct platform
+ 		}
+ 		of_node_put(np);
+ 		lp->pcs.ops = &axienet_pcs_ops;
++		lp->pcs.neg_mode = true;
+ 		lp->pcs.poll = true;
+ 	}
+ 
+--- a/drivers/net/pcs/pcs-lynx.c
++++ b/drivers/net/pcs/pcs-lynx.c
+@@ -122,9 +122,10 @@ static void lynx_pcs_get_state(struct ph
+ 		state->link, state->an_complete);
+ }
+ 
+-static int lynx_pcs_config_giga(struct mdio_device *pcs, unsigned int mode,
++static int lynx_pcs_config_giga(struct mdio_device *pcs,
+ 				phy_interface_t interface,
+-				const unsigned long *advertising)
++				const unsigned long *advertising,
++				unsigned int neg_mode)
+ {
+ 	u32 link_timer;
+ 	u16 if_mode;
+@@ -137,8 +138,9 @@ static int lynx_pcs_config_giga(struct m
+ 
+ 		if_mode = 0;
+ 	} else {
++		/* SGMII and QSGMII */
+ 		if_mode = IF_MODE_SGMII_EN;
+-		if (mode == MLO_AN_INBAND) {
++		if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ 			if_mode |= IF_MODE_USE_SGMII_AN;
+ 
+ 			/* Adjust link timer for SGMII */
+@@ -154,7 +156,8 @@ static int lynx_pcs_config_giga(struct m
+ 	if (err)
+ 		return err;
+ 
+-	return phylink_mii_c22_pcs_config(pcs, mode, interface, advertising);
++	return phylink_mii_c22_pcs_config(pcs, interface, advertising,
++					  neg_mode);
+ }
+ 
+ static int lynx_pcs_config_usxgmii(struct mdio_device *pcs, unsigned int mode,
+@@ -181,13 +184,16 @@ static int lynx_pcs_config(struct phylin
+ 			   bool permit)
+ {
+ 	struct lynx_pcs *lynx = phylink_pcs_to_lynx(pcs);
++	unsigned int neg_mode;
++
++	neg_mode = phylink_pcs_neg_mode(mode, ifmode, advertising);
+ 
+ 	switch (ifmode) {
+ 	case PHY_INTERFACE_MODE_1000BASEX:
+ 	case PHY_INTERFACE_MODE_SGMII:
+ 	case PHY_INTERFACE_MODE_QSGMII:
+-		return lynx_pcs_config_giga(lynx->mdio, mode, ifmode,
+-					    advertising);
++		return lynx_pcs_config_giga(lynx->mdio, ifmode, advertising,
++					    neg_mode);
+ 	case PHY_INTERFACE_MODE_2500BASEX:
+ 		if (phylink_autoneg_inband(mode)) {
+ 			dev_err(&lynx->mdio->dev,
+--- a/drivers/net/phy/phylink.c
++++ b/drivers/net/phy/phylink.c
+@@ -3545,20 +3545,20 @@ EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_en
+ /**
+  * phylink_mii_c22_pcs_config() - configure clause 22 PCS
+  * @pcs: a pointer to a &struct mdio_device.
+- * @mode: link autonegotiation mode
+  * @interface: the PHY interface mode being configured
+  * @advertising: the ethtool advertisement mask
++ * @neg_mode: PCS negotiation mode
+  *
+  * Configure a Clause 22 PCS PHY with the appropriate negotiation
+  * parameters for the @mode, @interface and @advertising parameters.
+  * Returns negative error number on failure, zero if the advertisement
+  * has not changed, or positive if there is a change.
+  */
+-int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
++int phylink_mii_c22_pcs_config(struct mdio_device *pcs,
+ 			       phy_interface_t interface,
+-			       const unsigned long *advertising)
++			       const unsigned long *advertising,
++			       unsigned int neg_mode)
+ {
+-	unsigned int neg_mode;
+ 	bool changed = 0;
+ 	u16 bmcr;
+ 	int ret, adv;
+@@ -3572,7 +3572,6 @@ int phylink_mii_c22_pcs_config(struct md
+ 		changed = ret;
+ 	}
+ 
+-	neg_mode = phylink_pcs_neg_mode(mode, interface, advertising);
+ 	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED)
+ 		bmcr = BMCR_ANENABLE;
+ 	else
+--- a/include/linux/phylink.h
++++ b/include/linux/phylink.h
+@@ -743,9 +743,10 @@ void phylink_mii_c22_pcs_get_state(struc
+ 				   struct phylink_link_state *state);
+ int phylink_mii_c22_pcs_encode_advertisement(phy_interface_t interface,
+ 					     const unsigned long *advertising);
+-int phylink_mii_c22_pcs_config(struct mdio_device *pcs, unsigned int mode,
++int phylink_mii_c22_pcs_config(struct mdio_device *pcs,
+ 			       phy_interface_t interface,
+-			       const unsigned long *advertising);
++			       const unsigned long *advertising,
++			       unsigned int neg_mode);
+ void phylink_mii_c22_pcs_an_restart(struct mdio_device *pcs);
+ 
+ void phylink_resolve_c73(struct phylink_link_state *state);
diff --git a/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch b/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch
new file mode 100644
index 00000000000..5e0128766ca
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-27-v6.5-net-pcs-lynxi-update-PCS-driver-to-use-neg_mode.patch
@@ -0,0 +1,101 @@
+From 3b2de56a146f34e3f70a84cc3a1897064e445d16 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Fri, 16 Jun 2023 13:06:43 +0100
+Subject: [PATCH] net: pcs: lynxi: update PCS driver to use neg_mode
+
+Update the Lynxi PCS driver to use neg_mode rather than the mode
+argument. This ensures that the link_up() method will always program
+the speed and duplex when negotiation is disabled.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Link: https://lore.kernel.org/r/E1qA8Dz-00EaFY-5A@rmk-PC.armlinux.org.uk
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c | 39 ++++++++++++++-------------------
+ 1 file changed, 16 insertions(+), 23 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -102,13 +102,13 @@ static void mtk_pcs_lynxi_get_state(stru
+ 					 FIELD_GET(SGMII_LPA, adv));
+ }
+ 
+-static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int mode,
++static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface,
+ 				const unsigned long *advertising,
+ 				bool permit_pause_to_mac)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+-	bool mode_changed = false, changed, use_an;
++	bool mode_changed = false, changed;
+ 	unsigned int rgc3, sgm_mode, bmcr;
+ 	int advertise, link_timer;
+ 
+@@ -121,30 +121,22 @@ static int mtk_pcs_lynxi_config(struct p
+ 	 * we assume that fixes it's speed at bitrate = line rate (in
+ 	 * other words, 1000Mbps or 2500Mbps).
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_SGMII) {
++	if (interface == PHY_INTERFACE_MODE_SGMII)
+ 		sgm_mode = SGMII_IF_MODE_SGMII;
+-		if (phylink_autoneg_inband(mode)) {
+-			sgm_mode |= SGMII_REMOTE_FAULT_DIS |
+-				    SGMII_SPEED_DUPLEX_AN;
+-			use_an = true;
+-		} else {
+-			use_an = false;
+-		}
+-	} else if (phylink_autoneg_inband(mode)) {
+-		/* 1000base-X or 2500base-X autoneg */
+-		sgm_mode = SGMII_REMOTE_FAULT_DIS;
+-		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
+-					   advertising);
+-	} else {
++	else
+ 		/* 1000base-X or 2500base-X without autoneg */
+ 		sgm_mode = 0;
+-		use_an = false;
+-	}
+ 
+-	if (use_an)
++	if (neg_mode & PHYLINK_PCS_NEG_INBAND)
++		sgm_mode |= SGMII_REMOTE_FAULT_DIS;
++
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
++		if (interface == PHY_INTERFACE_MODE_SGMII)
++			sgm_mode |= SGMII_SPEED_DUPLEX_AN;
+ 		bmcr = BMCR_ANENABLE;
+-	else
++	} else {
+ 		bmcr = 0;
++	}
+ 
+ 	if (mpcs->interface != interface) {
+ 		link_timer = phylink_get_link_timer_ns(interface);
+@@ -216,14 +208,15 @@ static void mtk_pcs_lynxi_restart_an(str
+ 	regmap_set_bits(mpcs->regmap, SGMSYS_PCS_CONTROL_1, BMCR_ANRESTART);
+ }
+ 
+-static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs, unsigned int mode,
++static void mtk_pcs_lynxi_link_up(struct phylink_pcs *pcs,
++				  unsigned int neg_mode,
+ 				  phy_interface_t interface, int speed,
+ 				  int duplex)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ 	unsigned int sgm_mode;
+ 
+-	if (!phylink_autoneg_inband(mode)) {
++	if (neg_mode != PHYLINK_PCS_NEG_INBAND_ENABLED) {
+ 		/* Force the speed and duplex setting */
+ 		if (speed == SPEED_10)
+ 			sgm_mode = SGMII_SPEED_10;
+@@ -286,6 +279,7 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 	mpcs->regmap = regmap;
+ 	mpcs->flags = flags;
+ 	mpcs->pcs.ops = &mtk_pcs_lynxi_ops;
++	mpcs->pcs.neg_mode = true;
+ 	mpcs->pcs.poll = true;
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ 
diff --git a/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch b/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch
new file mode 100644
index 00000000000..3dd22d29160
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-28-v6.4-net-pcs-xpcs-use-Autoneg-bit-rather-than-an_enabled.patch
@@ -0,0 +1,55 @@
+From 459fd2f11204c962e3153020f4f56748e0e10afb Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 21 Mar 2023 15:58:49 +0000
+Subject: [PATCH] net: pcs: xpcs: use Autoneg bit rather than an_enabled
+
+The Autoneg bit in the advertising bitmap and state->an_enabled are
+always identical. Thus, we will be removing state->an_enabled.
+
+Use the Autoneg bit in the advertising bitmap to indicate whether
+autonegotiation should be used, rather than using the an_enabled
+member which will be going away.
+
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Simon Horman <simon.horman@corigine.com>
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/pcs/pcs-xpcs.c | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -931,6 +931,7 @@ static int xpcs_get_state_c73(struct dw_
+ 			      struct phylink_link_state *state,
+ 			      const struct xpcs_compat *compat)
+ {
++	bool an_enabled;
+ 	int ret;
+ 
+ 	/* Link needs to be read first ... */
+@@ -948,11 +949,13 @@ static int xpcs_get_state_c73(struct dw_
+ 		return xpcs_do_config(xpcs, state->interface, MLO_AN_INBAND, NULL);
+ 	}
+ 
+-	if (state->an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
++	an_enabled = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++				       state->advertising);
++	if (an_enabled && xpcs_aneg_done_c73(xpcs, state, compat)) {
+ 		state->an_complete = true;
+ 		xpcs_read_lpa_c73(xpcs, state);
+ 		xpcs_resolve_lpa_c73(xpcs, state);
+-	} else if (state->an_enabled) {
++	} else if (an_enabled) {
+ 		state->link = 0;
+ 	} else if (state->link) {
+ 		xpcs_resolve_pma(xpcs, state);
+@@ -1007,7 +1010,8 @@ static int xpcs_get_state_c37_1000basex(
+ {
+ 	int lpa, bmsr;
+ 
+-	if (state->an_enabled) {
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
++			      state->advertising)) {
+ 		/* Reset link state */
+ 		state->link = false;
+ 
diff --git a/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch b/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch
new file mode 100644
index 00000000000..7cae8515fa1
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-29-v6.4-net-pcs-xpcs-fix-incorrect-number-of-interfaces.patch
@@ -0,0 +1,30 @@
+From 43fb622d91a9f408322735d2f736495c1009f575 Mon Sep 17 00:00:00 2001
+From: "Russell King (Oracle)" <rmk+kernel@armlinux.org.uk>
+Date: Tue, 9 May 2023 12:50:04 +0100
+Subject: [PATCH] net: pcs: xpcs: fix incorrect number of interfaces
+
+In synopsys_xpcs_compat[], the DW_XPCS_2500BASEX entry was setting
+the number of interfaces using the xpcs_2500basex_features array
+rather than xpcs_2500basex_interfaces. This causes us to overflow
+the array of interfaces. Fix this.
+
+Fixes: f27abde3042a ("net: pcs: add 2500BASEX support for Intel mGbE controller")
+Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Reviewed-by: Leon Romanovsky <leonro@nvidia.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/pcs/pcs-xpcs.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/pcs/pcs-xpcs.c
++++ b/drivers/net/pcs/pcs-xpcs.c
+@@ -1211,7 +1211,7 @@ static const struct xpcs_compat synopsys
+ 	[DW_XPCS_2500BASEX] = {
+ 		.supported = xpcs_2500basex_features,
+ 		.interface = xpcs_2500basex_interfaces,
+-		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_features),
++		.num_interfaces = ARRAY_SIZE(xpcs_2500basex_interfaces),
+ 		.an_mode = DW_2500BASEX,
+ 	},
+ };
diff --git a/target/linux/generic/backport-6.1/715-v6.9-01-net-phy-qcom-qca808x-fix-logic-error-in-LED-brightne.patch b/target/linux/generic/backport-6.1/715-v6.9-01-net-phy-qcom-qca808x-fix-logic-error-in-LED-brightne.patch
new file mode 100644
index 00000000000..0a7b5358f13
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-v6.9-01-net-phy-qcom-qca808x-fix-logic-error-in-LED-brightne.patch
@@ -0,0 +1,36 @@
+From f2ec98566775dd4341ec1dcf93aa5859c60de826 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 1 Feb 2024 14:46:00 +0100
+Subject: [PATCH 1/2] net: phy: qcom: qca808x: fix logic error in LED
+ brightness set
+
+In switching to using phy_modify_mmd and a more short version of the
+LED ON/OFF condition in later revision, it was made a logic error where
+
+value ? QCA808X_LED_FORCE_ON : QCA808X_LED_FORCE_OFF is always true as
+value is always OR with QCA808X_LED_FORCE_EN due to missing ()
+resulting in the testing condition being QCA808X_LED_FORCE_EN | value.
+
+Add the () to apply the correct condition and restore correct
+functionality of the brightness ON/OFF.
+
+Fixes: 7196062b64ee ("net: phy: at803x: add LED support for qca808x")
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -820,8 +820,8 @@ static int qca808x_led_brightness_set(st
+ 
+ 	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+ 			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF);
++			      QCA808X_LED_FORCE_EN | (value ? QCA808X_LED_FORCE_ON :
++							     QCA808X_LED_FORCE_OFF));
+ }
+ 
+ static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
diff --git a/target/linux/generic/backport-6.1/715-v6.9-02-net-phy-qcom-qca808x-default-to-LED-active-High-if-n.patch b/target/linux/generic/backport-6.1/715-v6.9-02-net-phy-qcom-qca808x-default-to-LED-active-High-if-n.patch
new file mode 100644
index 00000000000..e32ed7f7772
--- /dev/null
+++ b/target/linux/generic/backport-6.1/715-v6.9-02-net-phy-qcom-qca808x-default-to-LED-active-High-if-n.patch
@@ -0,0 +1,41 @@
+From f203c8c77c7616c099647636f4c67d59a45fe8a2 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 1 Feb 2024 14:46:01 +0100
+Subject: [PATCH 2/2] net: phy: qcom: qca808x: default to LED active High if
+ not set
+
+qca808x PHY provide support for the led_polarity_set OP to configure
+and apply the active-low property but on PHY reset, the Active High bit
+is not set resulting in the LED driven as active-low.
+
+To fix this, check if active-low is not set in DT and enable Active High
+polarity by default to restore correct funcionality of the LED.
+
+Fixes: 7196062b64ee ("net: phy: at803x: add LED support for qca808x")
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -290,8 +290,18 @@ static int qca808x_probe(struct phy_devi
+ 
+ static int qca808x_config_init(struct phy_device *phydev)
+ {
++	struct qca808x_priv *priv = phydev->priv;
+ 	int ret;
+ 
++	/* Default to LED Active High if active-low not in DT */
++	if (priv->led_polarity_mode == -1) {
++		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
++				       QCA808X_MMD7_LED_POLARITY_CTRL,
++				       QCA808X_LED_ACTIVE_HIGH);
++		if (ret)
++			return ret;
++	}
++
+ 	/* Active adc&vga on 802.3az for the link 1000M and 100M */
+ 	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
+ 			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-02-net-phy-add-support-for-scanning-PHY-in-PHY-packages.patch b/target/linux/generic/backport-6.1/716-v6.9-02-net-phy-add-support-for-scanning-PHY-in-PHY-packages.patch
new file mode 100644
index 00000000000..b355031aa5e
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-02-net-phy-add-support-for-scanning-PHY-in-PHY-packages.patch
@@ -0,0 +1,211 @@
+From 385ef48f468696d6d172eb367656a3466fa0408d Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:05 +0100
+Subject: [PATCH 02/10] net: phy: add support for scanning PHY in PHY packages
+ nodes
+
+Add support for scanning PHY in PHY package nodes. PHY packages nodes
+are just container for actual PHY on the MDIO bus.
+
+Their PHY address defined in the PHY package node are absolute and
+reflect the address on the MDIO bus.
+
+mdio_bus.c and of_mdio.c is updated to now support and parse also
+PHY package subnode by checking if the node name match
+"ethernet-phy-package".
+
+As PHY package reg is mandatory and each PHY in the PHY package must
+have a reg, every invalid PHY Package node is ignored and will be
+skipped by the autoscan fallback.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/mdio/of_mdio.c | 79 +++++++++++++++++++++++++++-----------
+ drivers/net/phy/mdio_bus.c | 44 +++++++++++++++++----
+ 2 files changed, 92 insertions(+), 31 deletions(-)
+
+--- a/drivers/net/mdio/of_mdio.c
++++ b/drivers/net/mdio/of_mdio.c
+@@ -138,6 +138,53 @@ bool of_mdiobus_child_is_phy(struct devi
+ }
+ EXPORT_SYMBOL(of_mdiobus_child_is_phy);
+ 
++static int __of_mdiobus_parse_phys(struct mii_bus *mdio, struct device_node *np,
++				   bool *scanphys)
++{
++	struct device_node *child;
++	int addr, rc = 0;
++
++	/* Loop over the child nodes and register a phy_device for each phy */
++	for_each_available_child_of_node(np, child) {
++		if (of_node_name_eq(child, "ethernet-phy-package")) {
++			/* Ignore invalid ethernet-phy-package node */
++			if (!of_find_property(child, "reg", NULL))
++				continue;
++
++			rc = __of_mdiobus_parse_phys(mdio, child, NULL);
++			if (rc && rc != -ENODEV)
++				goto exit;
++
++			continue;
++		}
++
++		addr = of_mdio_parse_addr(&mdio->dev, child);
++		if (addr < 0) {
++			/* Skip scanning for invalid ethernet-phy-package node */
++			if (scanphys)
++				*scanphys = true;
++			continue;
++		}
++
++		if (of_mdiobus_child_is_phy(child))
++			rc = of_mdiobus_register_phy(mdio, child, addr);
++		else
++			rc = of_mdiobus_register_device(mdio, child, addr);
++
++		if (rc == -ENODEV)
++			dev_err(&mdio->dev,
++				"MDIO device at address %d is missing.\n",
++				addr);
++		else if (rc)
++			goto exit;
++	}
++
++	return 0;
++exit:
++	of_node_put(child);
++	return rc;
++}
++
+ /**
+  * __of_mdiobus_register - Register mii_bus and create PHYs from the device tree
+  * @mdio: pointer to mii_bus structure
+@@ -179,33 +226,18 @@ int __of_mdiobus_register(struct mii_bus
+ 		return rc;
+ 
+ 	/* Loop over the child nodes and register a phy_device for each phy */
+-	for_each_available_child_of_node(np, child) {
+-		addr = of_mdio_parse_addr(&mdio->dev, child);
+-		if (addr < 0) {
+-			scanphys = true;
+-			continue;
+-		}
+-
+-		if (of_mdiobus_child_is_phy(child))
+-			rc = of_mdiobus_register_phy(mdio, child, addr);
+-		else
+-			rc = of_mdiobus_register_device(mdio, child, addr);
+-
+-		if (rc == -ENODEV)
+-			dev_err(&mdio->dev,
+-				"MDIO device at address %d is missing.\n",
+-				addr);
+-		else if (rc)
+-			goto unregister;
+-	}
++	rc = __of_mdiobus_parse_phys(mdio, np, &scanphys);
++	if (rc)
++		goto unregister;
+ 
+ 	if (!scanphys)
+ 		return 0;
+ 
+ 	/* auto scan for PHYs with empty reg property */
+ 	for_each_available_child_of_node(np, child) {
+-		/* Skip PHYs with reg property set */
+-		if (of_find_property(child, "reg", NULL))
++		/* Skip PHYs with reg property set or ethernet-phy-package node */
++		if (of_find_property(child, "reg", NULL) ||
++		    of_node_name_eq(child, "ethernet-phy-package"))
+ 			continue;
+ 
+ 		for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
+@@ -226,15 +258,16 @@ int __of_mdiobus_register(struct mii_bus
+ 				if (!rc)
+ 					break;
+ 				if (rc != -ENODEV)
+-					goto unregister;
++					goto put_unregister;
+ 			}
+ 		}
+ 	}
+ 
+ 	return 0;
+ 
+-unregister:
++put_unregister:
+ 	of_node_put(child);
++unregister:
+ 	mdiobus_unregister(mdio);
+ 	return rc;
+ }
+--- a/drivers/net/phy/mdio_bus.c
++++ b/drivers/net/phy/mdio_bus.c
+@@ -448,19 +448,34 @@ EXPORT_SYMBOL(of_mdio_find_bus);
+  * found, set the of_node pointer for the mdio device. This allows
+  * auto-probed phy devices to be supplied with information passed in
+  * via DT.
++ * If a PHY package is found, PHY is searched also there.
+  */
+-static void of_mdiobus_link_mdiodev(struct mii_bus *bus,
+-				    struct mdio_device *mdiodev)
++static int of_mdiobus_find_phy(struct device *dev, struct mdio_device *mdiodev,
++			       struct device_node *np)
+ {
+-	struct device *dev = &mdiodev->dev;
+ 	struct device_node *child;
+ 
+-	if (dev->of_node || !bus->dev.of_node)
+-		return;
+-
+-	for_each_available_child_of_node(bus->dev.of_node, child) {
++	for_each_available_child_of_node(np, child) {
+ 		int addr;
+ 
++		if (of_node_name_eq(child, "ethernet-phy-package")) {
++			/* Validate PHY package reg presence */
++			if (!of_find_property(child, "reg", NULL)) {
++				of_node_put(child);
++				return -EINVAL;
++			}
++
++			if (!of_mdiobus_find_phy(dev, mdiodev, child)) {
++				/* The refcount for the PHY package will be
++				 * incremented later when PHY join the Package.
++				 */
++				of_node_put(child);
++				return 0;
++			}
++
++			continue;
++		}
++
+ 		addr = of_mdio_parse_addr(dev, child);
+ 		if (addr < 0)
+ 			continue;
+@@ -470,9 +485,22 @@ static void of_mdiobus_link_mdiodev(stru
+ 			/* The refcount on "child" is passed to the mdio
+ 			 * device. Do _not_ use of_node_put(child) here.
+ 			 */
+-			return;
++			return 0;
+ 		}
+ 	}
++
++	return -ENODEV;
++}
++
++static void of_mdiobus_link_mdiodev(struct mii_bus *bus,
++				    struct mdio_device *mdiodev)
++{
++	struct device *dev = &mdiodev->dev;
++
++	if (dev->of_node || !bus->dev.of_node)
++		return;
++
++	of_mdiobus_find_phy(dev, mdiodev, bus->dev.of_node);
+ }
+ #else /* !IS_ENABLED(CONFIG_OF_MDIO) */
+ static inline void of_mdiobus_link_mdiodev(struct mii_bus *mdio,
diff --git a/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch b/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
new file mode 100644
index 00000000000..3c7bf6c132f
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-03-net-phy-add-devm-of_phy_package_join-helper.patch
@@ -0,0 +1,185 @@
+From 471e8fd3afcef5a9f9089f0bd21965ad9ba35c91 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:06 +0100
+Subject: [PATCH 03/10] net: phy: add devm/of_phy_package_join helper
+
+Add devm/of_phy_package_join helper to join PHYs in a PHY package. These
+are variant of the manual phy_package_join with the difference that
+these will use DT nodes to derive the base_addr instead of manually
+passing an hardcoded value.
+
+An additional value is added in phy_package_shared, "np" to reference
+the PHY package node pointer in specific PHY driver probe_once and
+config_init_once functions to make use of additional specific properties
+defined in the PHY package node in DT.
+
+The np value is filled only with of_phy_package_join if a valid PHY
+package node is found. A valid PHY package node must have the node name
+set to "ethernet-phy-package".
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/phy_device.c | 96 ++++++++++++++++++++++++++++++++++++
+ include/linux/phy.h          |  6 +++
+ 2 files changed, 102 insertions(+)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -1648,6 +1648,7 @@ int phy_package_join(struct phy_device *
+ 			shared->priv_size = priv_size;
+ 		}
+ 		shared->base_addr = base_addr;
++		shared->np = NULL;
+ 		refcount_set(&shared->refcnt, 1);
+ 		bus->shared[base_addr] = shared;
+ 	} else {
+@@ -1671,6 +1672,63 @@ err_unlock:
+ EXPORT_SYMBOL_GPL(phy_package_join);
+ 
+ /**
++ * of_phy_package_join - join a common PHY group in PHY package
++ * @phydev: target phy_device struct
++ * @priv_size: if non-zero allocate this amount of bytes for private data
++ *
++ * This is a variant of phy_package_join for PHY package defined in DT.
++ *
++ * The parent node of the @phydev is checked as a valid PHY package node
++ * structure (by matching the node name "ethernet-phy-package") and the
++ * base_addr for the PHY package is passed to phy_package_join.
++ *
++ * With this configuration the shared struct will also have the np value
++ * filled to use additional DT defined properties in PHY specific
++ * probe_once and config_init_once PHY package OPs.
++ *
++ * Returns < 0 on error, 0 on success. Esp. calling phy_package_join()
++ * with the same cookie but a different priv_size is an error. Or a parent
++ * node is not detected or is not valid or doesn't match the expected node
++ * name for PHY package.
++ */
++int of_phy_package_join(struct phy_device *phydev, size_t priv_size)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct device_node *package_node;
++	u32 base_addr;
++	int ret;
++
++	if (!node)
++		return -EINVAL;
++
++	package_node = of_get_parent(node);
++	if (!package_node)
++		return -EINVAL;
++
++	if (!of_node_name_eq(package_node, "ethernet-phy-package")) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	if (of_property_read_u32(package_node, "reg", &base_addr)) {
++		ret = -EINVAL;
++		goto exit;
++	}
++
++	ret = phy_package_join(phydev, base_addr, priv_size);
++	if (ret)
++		goto exit;
++
++	phydev->shared->np = package_node;
++
++	return 0;
++exit:
++	of_node_put(package_node);
++	return ret;
++}
++EXPORT_SYMBOL_GPL(of_phy_package_join);
++
++/**
+  * phy_package_leave - leave a common PHY group
+  * @phydev: target phy_device struct
+  *
+@@ -1686,6 +1744,10 @@ void phy_package_leave(struct phy_device
+ 	if (!shared)
+ 		return;
+ 
++	/* Decrease the node refcount on leave if present */
++	if (shared->np)
++		of_node_put(shared->np);
++
+ 	if (refcount_dec_and_mutex_lock(&shared->refcnt, &bus->shared_lock)) {
+ 		bus->shared[shared->base_addr] = NULL;
+ 		mutex_unlock(&bus->shared_lock);
+@@ -1739,6 +1801,40 @@ int devm_phy_package_join(struct device
+ EXPORT_SYMBOL_GPL(devm_phy_package_join);
+ 
+ /**
++ * devm_of_phy_package_join - resource managed of_phy_package_join()
++ * @dev: device that is registering this PHY package
++ * @phydev: target phy_device struct
++ * @priv_size: if non-zero allocate this amount of bytes for private data
++ *
++ * Managed of_phy_package_join(). Shared storage fetched by this function,
++ * phy_package_leave() is automatically called on driver detach. See
++ * of_phy_package_join() for more information.
++ */
++int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev,
++			     size_t priv_size)
++{
++	struct phy_device **ptr;
++	int ret;
++
++	ptr = devres_alloc(devm_phy_package_leave, sizeof(*ptr),
++			   GFP_KERNEL);
++	if (!ptr)
++		return -ENOMEM;
++
++	ret = of_phy_package_join(phydev, priv_size);
++
++	if (!ret) {
++		*ptr = phydev;
++		devres_add(dev, ptr);
++	} else {
++		devres_free(ptr);
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(devm_of_phy_package_join);
++
++/**
+  * phy_detach - detach a PHY device from its network device
+  * @phydev: target phy_device struct
+  *
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -321,6 +321,7 @@ struct mdio_bus_stats {
+  * struct phy_package_shared - Shared information in PHY packages
+  * @base_addr: Base PHY address of PHY package used to combine PHYs
+  *   in one package and for offset calculation of phy_package_read/write
++ * @np: Pointer to the Device Node if PHY package defined in DT
+  * @refcnt: Number of PHYs connected to this shared data
+  * @flags: Initialization of PHY package
+  * @priv_size: Size of the shared private data @priv
+@@ -332,6 +333,8 @@ struct mdio_bus_stats {
+  */
+ struct phy_package_shared {
+ 	u8 base_addr;
++	/* With PHY package defined in DT this points to the PHY package node */
++	struct device_node *np;
+ 	refcount_t refcnt;
+ 	unsigned long flags;
+ 	size_t priv_size;
+@@ -1793,9 +1796,12 @@ int phy_ethtool_set_link_ksettings(struc
+ 				   const struct ethtool_link_ksettings *cmd);
+ int phy_ethtool_nway_reset(struct net_device *ndev);
+ int phy_package_join(struct phy_device *phydev, int base_addr, size_t priv_size);
++int of_phy_package_join(struct phy_device *phydev, size_t priv_size);
+ void phy_package_leave(struct phy_device *phydev);
+ int devm_phy_package_join(struct device *dev, struct phy_device *phydev,
+ 			  int base_addr, size_t priv_size);
++int devm_of_phy_package_join(struct device *dev, struct phy_device *phydev,
++			     size_t priv_size);
+ 
+ #if IS_ENABLED(CONFIG_PHYLIB)
+ int __init mdio_bus_init(void);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-04-net-phy-qcom-move-more-function-to-shared-library.patch b/target/linux/generic/backport-6.1/716-v6.9-04-net-phy-qcom-move-more-function-to-shared-library.patch
new file mode 100644
index 00000000000..e935725630c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-04-net-phy-qcom-move-more-function-to-shared-library.patch
@@ -0,0 +1,583 @@
+From 737eb75a815f9c08dcbb6631db57f4f4b0540a5b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:07 +0100
+Subject: [PATCH 04/10] net: phy: qcom: move more function to shared library
+
+Move more function to shared library in preparation for introduction of
+new PHY Family qca807x that will make use of both functions from at803x
+and qca808x as it's a transition PHY with some implementation of at803x
+and some from the new qca808x.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/at803x.c       |  35 -----
+ drivers/net/phy/qcom/qca808x.c      | 205 ----------------------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 193 ++++++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         |  51 +++++++
+ 4 files changed, 244 insertions(+), 240 deletions(-)
+
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -504,41 +504,6 @@ static void at803x_link_change_notify(st
+ 	}
+ }
+ 
+-static int at803x_read_status(struct phy_device *phydev)
+-{
+-	struct at803x_ss_mask ss_mask = { 0 };
+-	int err, old_link = phydev->link;
+-
+-	/* Update the link, but return if there was an error */
+-	err = genphy_update_link(phydev);
+-	if (err)
+-		return err;
+-
+-	/* why bother the PHY if nothing can have changed */
+-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
+-		return 0;
+-
+-	phydev->speed = SPEED_UNKNOWN;
+-	phydev->duplex = DUPLEX_UNKNOWN;
+-	phydev->pause = 0;
+-	phydev->asym_pause = 0;
+-
+-	err = genphy_read_lpa(phydev);
+-	if (err < 0)
+-		return err;
+-
+-	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
+-	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
+-	err = at803x_read_specific_status(phydev, ss_mask);
+-	if (err < 0)
+-		return err;
+-
+-	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
+-		phy_resolve_aneg_pause(phydev);
+-
+-	return 0;
+-}
+-
+ static int at803x_config_aneg(struct phy_device *phydev)
+ {
+ 	struct at803x_priv *priv = phydev->priv;
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -2,7 +2,6 @@
+ 
+ #include <linux/phy.h>
+ #include <linux/module.h>
+-#include <linux/ethtool_netlink.h>
+ 
+ #include "qcom.h"
+ 
+@@ -63,55 +62,6 @@
+ #define QCA808X_DBG_AN_TEST			0xb
+ #define QCA808X_HIBERNATION_EN			BIT(15)
+ 
+-#define QCA808X_CDT_ENABLE_TEST			BIT(15)
+-#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
+-#define QCA808X_CDT_STATUS			BIT(11)
+-#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
+-
+-#define QCA808X_MMD3_CDT_STATUS			0x8064
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
+-#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
+-#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
+-#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
+-
+-#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
+-#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
+-#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
+-#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
+-
+-#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
+-#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
+-#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
+-#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
+-#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
+-
+-#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
+-#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
+-#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
+-
+-/* NORMAL are MDI with type set to 0 */
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI1)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI2)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
+-									 QCA808X_CDT_STATUS_STAT_MDI3)
+-
+-/* Added for reference of existence but should be handled by wait_for_completion already */
+-#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+-
+ #define QCA808X_MMD7_LED_GLOBAL			0x8073
+ #define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+ #define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+@@ -406,86 +356,6 @@ static int qca808x_soft_reset(struct phy
+ 	return ret;
+ }
+ 
+-static bool qca808x_cdt_fault_length_valid(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return true;
+-	default:
+-		return false;
+-	}
+-}
+-
+-static int qca808x_cable_test_result_trans(int cdt_code)
+-{
+-	switch (cdt_code) {
+-	case QCA808X_CDT_STATUS_STAT_NORMAL:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
+-	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
+-	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
+-	case QCA808X_CDT_STATUS_STAT_FAIL:
+-	default:
+-		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
+-	}
+-}
+-
+-static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
+-				    int result)
+-{
+-	int val;
+-	u32 cdt_length_reg = 0;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
+-	if (val < 0)
+-		return val;
+-
+-	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
+-	else
+-		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
+-
+-	return at803x_cdt_fault_length(val);
+-}
+-
+ static int qca808x_cable_test_start(struct phy_device *phydev)
+ {
+ 	int ret;
+@@ -526,81 +396,6 @@ static int qca808x_cable_test_start(stru
+ 
+ 	return 0;
+ }
+-
+-static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
+-					      u16 status)
+-{
+-	int length, result;
+-	u16 pair_code;
+-
+-	switch (pair) {
+-	case ETHTOOL_A_CABLE_PAIR_A:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_B:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_C:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
+-		break;
+-	case ETHTOOL_A_CABLE_PAIR_D:
+-		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
+-		break;
+-	default:
+-		return -EINVAL;
+-	}
+-
+-	result = qca808x_cable_test_result_trans(pair_code);
+-	ethnl_cable_test_result(phydev, pair, result);
+-
+-	if (qca808x_cdt_fault_length_valid(pair_code)) {
+-		length = qca808x_cdt_fault_length(phydev, pair, result);
+-		ethnl_cable_test_fault_length(phydev, pair, length);
+-	}
+-
+-	return 0;
+-}
+-
+-static int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
+-{
+-	int ret, val;
+-
+-	*finished = false;
+-
+-	val = QCA808X_CDT_ENABLE_TEST |
+-	      QCA808X_CDT_LENGTH_UNIT;
+-	ret = at803x_cdt_start(phydev, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
+-	if (ret)
+-		return ret;
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
+-	if (val < 0)
+-		return val;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
+-	if (ret)
+-		return ret;
+-
+-	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
+-	if (ret)
+-		return ret;
+-
+-	*finished = true;
+-
+-	return 0;
+-}
+ 
+ static int qca808x_get_features(struct phy_device *phydev)
+ {
+--- a/drivers/net/phy/qcom/qcom-phy-lib.c
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -5,6 +5,7 @@
+ 
+ #include <linux/netdevice.h>
+ #include <linux/etherdevice.h>
++#include <linux/ethtool_netlink.h>
+ 
+ #include "qcom.h"
+ 
+@@ -311,6 +312,42 @@ int at803x_prepare_config_aneg(struct ph
+ }
+ EXPORT_SYMBOL_GPL(at803x_prepare_config_aneg);
+ 
++int at803x_read_status(struct phy_device *phydev)
++{
++	struct at803x_ss_mask ss_mask = { 0 };
++	int err, old_link = phydev->link;
++
++	/* Update the link, but return if there was an error */
++	err = genphy_update_link(phydev);
++	if (err)
++		return err;
++
++	/* why bother the PHY if nothing can have changed */
++	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
++		return 0;
++
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	err = genphy_read_lpa(phydev);
++	if (err < 0)
++		return err;
++
++	ss_mask.speed_mask = AT803X_SS_SPEED_MASK;
++	ss_mask.speed_shift = __bf_shf(AT803X_SS_SPEED_MASK);
++	err = at803x_read_specific_status(phydev, ss_mask);
++	if (err < 0)
++		return err;
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(at803x_read_status);
++
+ static int at803x_get_downshift(struct phy_device *phydev, u8 *d)
+ {
+ 	int val;
+@@ -427,3 +464,159 @@ int at803x_cdt_wait_for_completion(struc
+ 	return ret < 0 ? ret : 0;
+ }
+ EXPORT_SYMBOL_GPL(at803x_cdt_wait_for_completion);
++
++static bool qca808x_cdt_fault_length_valid(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return true;
++	default:
++		return false;
++	}
++}
++
++static int qca808x_cable_test_result_trans(int cdt_code)
++{
++	switch (cdt_code) {
++	case QCA808X_CDT_STATUS_STAT_NORMAL:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
++	case QCA808X_CDT_STATUS_STAT_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
++	case QCA808X_CDT_STATUS_STAT_SAME_OPEN:
++		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN:
++	case QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT:
++		return ETHTOOL_A_CABLE_RESULT_CODE_CROSS_SHORT;
++	case QCA808X_CDT_STATUS_STAT_FAIL:
++	default:
++		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
++	}
++}
++
++static int qca808x_cdt_fault_length(struct phy_device *phydev, int pair,
++				    int result)
++{
++	int val;
++	u32 cdt_length_reg = 0;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_A;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_B;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_C;
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		cdt_length_reg = QCA808X_MMD3_CDT_DIAG_PAIR_D;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, cdt_length_reg);
++	if (val < 0)
++		return val;
++
++	if (result == ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT)
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_SAME_SHORT, val);
++	else
++		val = FIELD_GET(QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT, val);
++
++	return at803x_cdt_fault_length(val);
++}
++
++static int qca808x_cable_test_get_pair_status(struct phy_device *phydev, u8 pair,
++					      u16 status)
++{
++	int length, result;
++	u16 pair_code;
++
++	switch (pair) {
++	case ETHTOOL_A_CABLE_PAIR_A:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_A, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_B:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_B, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_C:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_C, status);
++		break;
++	case ETHTOOL_A_CABLE_PAIR_D:
++		pair_code = FIELD_GET(QCA808X_CDT_CODE_PAIR_D, status);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	result = qca808x_cable_test_result_trans(pair_code);
++	ethnl_cable_test_result(phydev, pair, result);
++
++	if (qca808x_cdt_fault_length_valid(pair_code)) {
++		length = qca808x_cdt_fault_length(phydev, pair, result);
++		ethnl_cable_test_fault_length(phydev, pair, length);
++	}
++
++	return 0;
++}
++
++int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished)
++{
++	int ret, val;
++
++	*finished = false;
++
++	val = QCA808X_CDT_ENABLE_TEST |
++	      QCA808X_CDT_LENGTH_UNIT;
++	ret = at803x_cdt_start(phydev, val);
++	if (ret)
++		return ret;
++
++	ret = at803x_cdt_wait_for_completion(phydev, QCA808X_CDT_ENABLE_TEST);
++	if (ret)
++		return ret;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_PCS, QCA808X_MMD3_CDT_STATUS);
++	if (val < 0)
++		return val;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_A, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_B, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_C, val);
++	if (ret)
++		return ret;
++
++	ret = qca808x_cable_test_get_pair_status(phydev, ETHTOOL_A_CABLE_PAIR_D, val);
++	if (ret)
++		return ret;
++
++	*finished = true;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(qca808x_cable_test_get_status);
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -54,6 +54,55 @@
+ #define AT803X_CDT_STATUS_STAT_MASK		GENMASK(9, 8)
+ #define AT803X_CDT_STATUS_DELTA_TIME_MASK	GENMASK(7, 0)
+ 
++#define QCA808X_CDT_ENABLE_TEST			BIT(15)
++#define QCA808X_CDT_INTER_CHECK_DIS		BIT(13)
++#define QCA808X_CDT_STATUS			BIT(11)
++#define QCA808X_CDT_LENGTH_UNIT			BIT(10)
++
++#define QCA808X_MMD3_CDT_STATUS			0x8064
++#define QCA808X_MMD3_CDT_DIAG_PAIR_A		0x8065
++#define QCA808X_MMD3_CDT_DIAG_PAIR_B		0x8066
++#define QCA808X_MMD3_CDT_DIAG_PAIR_C		0x8067
++#define QCA808X_MMD3_CDT_DIAG_PAIR_D		0x8068
++#define QCA808X_CDT_DIAG_LENGTH_SAME_SHORT	GENMASK(15, 8)
++#define QCA808X_CDT_DIAG_LENGTH_CROSS_SHORT	GENMASK(7, 0)
++
++#define QCA808X_CDT_CODE_PAIR_A			GENMASK(15, 12)
++#define QCA808X_CDT_CODE_PAIR_B			GENMASK(11, 8)
++#define QCA808X_CDT_CODE_PAIR_C			GENMASK(7, 4)
++#define QCA808X_CDT_CODE_PAIR_D			GENMASK(3, 0)
++
++#define QCA808X_CDT_STATUS_STAT_TYPE		GENMASK(1, 0)
++#define QCA808X_CDT_STATUS_STAT_FAIL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 0)
++#define QCA808X_CDT_STATUS_STAT_NORMAL		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 1)
++#define QCA808X_CDT_STATUS_STAT_SAME_OPEN	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 2)
++#define QCA808X_CDT_STATUS_STAT_SAME_SHORT	FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_TYPE, 3)
++
++#define QCA808X_CDT_STATUS_STAT_MDI		GENMASK(3, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI1		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 1)
++#define QCA808X_CDT_STATUS_STAT_MDI2		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 2)
++#define QCA808X_CDT_STATUS_STAT_MDI3		FIELD_PREP_CONST(QCA808X_CDT_STATUS_STAT_MDI, 3)
++
++/* NORMAL are MDI with type set to 0 */
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI1
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI1_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI1)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI2
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI2_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI2)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_NORMAL	QCA808X_CDT_STATUS_STAT_MDI3
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_OPEN		(QCA808X_CDT_STATUS_STAT_SAME_OPEN |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++#define QCA808X_CDT_STATUS_STAT_CROSS_SHORT_WITH_MDI3_SAME_SHORT	(QCA808X_CDT_STATUS_STAT_SAME_SHORT |\
++									 QCA808X_CDT_STATUS_STAT_MDI3)
++
++/* Added for reference of existence but should be handled by wait_for_completion already */
++#define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
++
+ #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+ #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+ #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
+@@ -110,6 +159,7 @@ int at803x_read_specific_status(struct p
+ 				struct at803x_ss_mask ss_mask);
+ int at803x_config_mdix(struct phy_device *phydev, u8 ctrl);
+ int at803x_prepare_config_aneg(struct phy_device *phydev);
++int at803x_read_status(struct phy_device *phydev);
+ int at803x_get_tunable(struct phy_device *phydev,
+ 		       struct ethtool_tunable *tuna, void *data);
+ int at803x_set_tunable(struct phy_device *phydev,
+@@ -118,3 +168,4 @@ int at803x_cdt_fault_length(int dt);
+ int at803x_cdt_start(struct phy_device *phydev, u32 cdt_start);
+ int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+ 				   u32 cdt_en);
++int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch b/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
new file mode 100644
index 00000000000..acaa4a644ee
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-06-net-phy-provide-whether-link-has-changed-in-c37_read.patch
@@ -0,0 +1,100 @@
+From 9b1d5e055508393561e26bd1720f4c2639b03b1a Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:09 +0100
+Subject: [PATCH 06/10] net: phy: provide whether link has changed in
+ c37_read_status
+
+Some PHY driver might require additional regs call after
+genphy_c37_read_status() is called.
+
+Expand genphy_c37_read_status to provide a bool wheather the link has
+changed or not to permit PHY driver to skip additional regs call if
+nothing has changed.
+
+Every user of genphy_c37_read_status() is updated with the new
+additional bool.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/broadcom.c    |  3 ++-
+ drivers/net/phy/phy_device.c  | 11 +++++++++--
+ drivers/net/phy/qcom/at803x.c |  3 ++-
+ include/linux/phy.h           |  2 +-
+ 4 files changed, 14 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/broadcom.c
++++ b/drivers/net/phy/broadcom.c
+@@ -609,10 +609,11 @@ static int bcm54616s_config_aneg(struct
+ static int bcm54616s_read_status(struct phy_device *phydev)
+ {
+ 	struct bcm54616s_phy_priv *priv = phydev->priv;
++	bool changed;
+ 	int err;
+ 
+ 	if (priv->mode_1000bx_en)
+-		err = genphy_c37_read_status(phydev);
++		err = genphy_c37_read_status(phydev, &changed);
+ 	else
+ 		err = genphy_read_status(phydev);
+ 
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -2549,12 +2549,15 @@ EXPORT_SYMBOL(genphy_read_status);
+ /**
+  * genphy_c37_read_status - check the link status and update current link state
+  * @phydev: target phy_device struct
++ * @changed: pointer where to store if link changed
+  *
+  * Description: Check the link, then figure out the current state
+  *   by comparing what we advertise with what the link partner
+  *   advertises. This function is for Clause 37 1000Base-X mode.
++ *
++ *   If link has changed, @changed is set to true, false otherwise.
+  */
+-int genphy_c37_read_status(struct phy_device *phydev)
++int genphy_c37_read_status(struct phy_device *phydev, bool *changed)
+ {
+ 	int lpa, err, old_link = phydev->link;
+ 
+@@ -2564,9 +2567,13 @@ int genphy_c37_read_status(struct phy_de
+ 		return err;
+ 
+ 	/* why bother the PHY if nothing can have changed */
+-	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link)
++	if (phydev->autoneg == AUTONEG_ENABLE && old_link && phydev->link) {
++		*changed = false;
+ 		return 0;
++	}
+ 
++	/* Signal link has changed */
++	*changed = true;
+ 	phydev->duplex = DUPLEX_UNKNOWN;
+ 	phydev->pause = 0;
+ 	phydev->asym_pause = 0;
+--- a/drivers/net/phy/qcom/at803x.c
++++ b/drivers/net/phy/qcom/at803x.c
+@@ -912,9 +912,10 @@ static int at8031_config_intr(struct phy
+ static int at8031_read_status(struct phy_device *phydev)
+ {
+ 	struct at803x_priv *priv = phydev->priv;
++	bool changed;
+ 
+ 	if (priv->is_1000basex)
+-		return genphy_c37_read_status(phydev);
++		return genphy_c37_read_status(phydev, &changed);
+ 
+ 	return at803x_read_status(phydev);
+ }
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -1688,7 +1688,7 @@ int genphy_write_mmd_unsupported(struct
+ 
+ /* Clause 37 */
+ int genphy_c37_config_aneg(struct phy_device *phydev);
+-int genphy_c37_read_status(struct phy_device *phydev);
++int genphy_c37_read_status(struct phy_device *phydev, bool *changed);
+ 
+ /* Clause 45 PHY */
+ int genphy_c45_restart_aneg(struct phy_device *phydev);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch b/target/linux/generic/backport-6.1/716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch
new file mode 100644
index 00000000000..bbf0f76d68c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-07-net-phy-qcom-add-support-for-QCA807x-PHY-Family.patch
@@ -0,0 +1,668 @@
+From d1cb613efbd3cd7d0c000167816beb3f248f5eb8 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robert.marko@sartura.hr>
+Date: Tue, 6 Feb 2024 18:31:10 +0100
+Subject: [PATCH 07/10] net: phy: qcom: add support for QCA807x PHY Family
+
+This adds driver for the Qualcomm QCA8072 and QCA8075 PHY-s.
+
+They are 2 or 5 port IEEE 802.3 clause 22 compliant 10BASE-Te,
+100BASE-TX and 1000BASE-T PHY-s.
+
+They feature 2 SerDes, one for PSGMII or QSGMII connection with
+MAC, while second one is SGMII for connection to MAC or fiber.
+
+Both models have a combo port that supports 1000BASE-X and
+100BASE-FX fiber.
+
+PHY package can be configured in 3 mode following this table:
+
+              First Serdes mode       Second Serdes mode
+Option 1      PSGMII for copper       Disabled
+              ports 0-4
+Option 2      PSGMII for copper       1000BASE-X / 100BASE-FX
+              ports 0-4
+Option 3      QSGMII for copper       SGMII for
+              ports 0-3               copper port 4
+
+Each PHY inside of QCA807x series has 4 digitally controlled
+output only pins that natively drive LED-s.
+But some vendors used these to driver generic LED-s controlled
+by userspace, so lets enable registering each PHY as GPIO
+controller and add driver for it.
+
+These are commonly used in Qualcomm IPQ40xx, IPQ60xx and IPQ807x
+boards.
+
+Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Robert Marko <robert.marko@sartura.hr>
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/Kconfig   |   8 +
+ drivers/net/phy/qcom/Makefile  |   1 +
+ drivers/net/phy/qcom/qca807x.c | 597 +++++++++++++++++++++++++++++++++
+ 3 files changed, 606 insertions(+)
+ create mode 100644 drivers/net/phy/qcom/qca807x.c
+
+--- a/drivers/net/phy/qcom/Kconfig
++++ b/drivers/net/phy/qcom/Kconfig
+@@ -20,3 +20,11 @@ config QCA808X_PHY
+ 	select QCOM_NET_PHYLIB
+ 	help
+ 	  Currently supports the QCA8081 model
++
++config QCA807X_PHY
++	tristate "Qualcomm QCA807x PHYs"
++	select QCOM_NET_PHYLIB
++	depends on OF_MDIO
++	help
++	  Currently supports the Qualcomm QCA8072, QCA8075 and the PSGMII
++	  control PHY.
+--- a/drivers/net/phy/qcom/Makefile
++++ b/drivers/net/phy/qcom/Makefile
+@@ -3,3 +3,4 @@ obj-$(CONFIG_QCOM_NET_PHYLIB)	+= qcom-ph
+ obj-$(CONFIG_AT803X_PHY)	+= at803x.o
+ obj-$(CONFIG_QCA83XX_PHY)	+= qca83xx.o
+ obj-$(CONFIG_QCA808X_PHY)	+= qca808x.o
++obj-$(CONFIG_QCA807X_PHY)	+= qca807x.o
+--- /dev/null
++++ b/drivers/net/phy/qcom/qca807x.c
+@@ -0,0 +1,597 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2023 Sartura Ltd.
++ *
++ * Author: Robert Marko <robert.marko@sartura.hr>
++ *         Christian Marangi <ansuelsmth@gmail.com>
++ *
++ * Qualcomm QCA8072 and QCA8075 PHY driver
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/phy.h>
++#include <linux/bitfield.h>
++#include <linux/gpio/driver.h>
++#include <linux/sfp.h>
++
++#include "qcom.h"
++
++#define QCA807X_CHIP_CONFIGURATION				0x1f
++#define QCA807X_BT_BX_REG_SEL					BIT(15)
++#define QCA807X_BT_BX_REG_SEL_FIBER				0
++#define QCA807X_BT_BX_REG_SEL_COPPER				1
++#define QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK		GENMASK(3, 0)
++#define QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII		4
++#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER		3
++#define QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER	0
++
++#define QCA807X_MEDIA_SELECT_STATUS				0x1a
++#define QCA807X_MEDIA_DETECTED_COPPER				BIT(5)
++#define QCA807X_MEDIA_DETECTED_1000_BASE_X			BIT(4)
++#define QCA807X_MEDIA_DETECTED_100_BASE_FX			BIT(3)
++
++#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION			0x807e
++#define QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN		BIT(0)
++
++#define QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH	0x801a
++#define QCA807X_CONTROL_DAC_MASK				GENMASK(2, 0)
++/* List of tweaks enabled by this bit:
++ * - With both FULL amplitude and FULL bias current: bias current
++ *   is set to half.
++ * - With only DSP amplitude: bias current is set to half and
++ *   is set to 1/4 with cable < 10m.
++ * - With DSP bias current (included both DSP amplitude and
++ *   DSP bias current): bias current is half the detected current
++ *   with cable < 10m.
++ */
++#define QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK			BIT(2)
++#define QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT			BIT(1)
++#define QCA807X_CONTROL_DAC_DSP_AMPLITUDE			BIT(0)
++
++#define QCA807X_MMD7_LED_100N_1				0x8074
++#define QCA807X_MMD7_LED_100N_2				0x8075
++#define QCA807X_MMD7_LED_1000N_1			0x8076
++#define QCA807X_MMD7_LED_1000N_2			0x8077
++
++#define QCA807X_MMD7_LED_CTRL(x)			(0x8074 + ((x) * 2))
++#define QCA807X_MMD7_LED_FORCE_CTRL(x)			(0x8075 + ((x) * 2))
++
++#define QCA807X_GPIO_FORCE_EN				BIT(15)
++#define QCA807X_GPIO_FORCE_MODE_MASK			GENMASK(14, 13)
++
++#define QCA807X_FUNCTION_CONTROL			0x10
++#define QCA807X_FC_MDI_CROSSOVER_MODE_MASK		GENMASK(6, 5)
++#define QCA807X_FC_MDI_CROSSOVER_AUTO			3
++#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDIX		1
++#define QCA807X_FC_MDI_CROSSOVER_MANUAL_MDI		0
++
++/* PQSGMII Analog PHY specific */
++#define PQSGMII_CTRL_REG				0x0
++#define PQSGMII_ANALOG_SW_RESET				BIT(6)
++#define PQSGMII_DRIVE_CONTROL_1				0xb
++#define PQSGMII_TX_DRIVER_MASK				GENMASK(7, 4)
++#define PQSGMII_TX_DRIVER_140MV				0x0
++#define PQSGMII_TX_DRIVER_160MV				0x1
++#define PQSGMII_TX_DRIVER_180MV				0x2
++#define PQSGMII_TX_DRIVER_200MV				0x3
++#define PQSGMII_TX_DRIVER_220MV				0x4
++#define PQSGMII_TX_DRIVER_240MV				0x5
++#define PQSGMII_TX_DRIVER_260MV				0x6
++#define PQSGMII_TX_DRIVER_280MV				0x7
++#define PQSGMII_TX_DRIVER_300MV				0x8
++#define PQSGMII_TX_DRIVER_320MV				0x9
++#define PQSGMII_TX_DRIVER_400MV				0xa
++#define PQSGMII_TX_DRIVER_500MV				0xb
++#define PQSGMII_TX_DRIVER_600MV				0xc
++#define PQSGMII_MODE_CTRL				0x6d
++#define PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK		BIT(0)
++#define PQSGMII_MMD3_SERDES_CONTROL			0x805a
++
++#define PHY_ID_QCA8072		0x004dd0b2
++#define PHY_ID_QCA8075		0x004dd0b1
++
++#define QCA807X_COMBO_ADDR_OFFSET			4
++#define QCA807X_PQSGMII_ADDR_OFFSET			5
++#define SERDES_RESET_SLEEP				100
++
++enum qca807x_global_phy {
++	QCA807X_COMBO_ADDR = 4,
++	QCA807X_PQSGMII_ADDR = 5,
++};
++
++struct qca807x_shared_priv {
++	unsigned int package_mode;
++	u32 tx_drive_strength;
++};
++
++struct qca807x_gpio_priv {
++	struct phy_device *phy;
++};
++
++struct qca807x_priv {
++	bool dac_full_amplitude;
++	bool dac_full_bias_current;
++	bool dac_disable_bias_current_tweak;
++};
++
++static int qca807x_cable_test_start(struct phy_device *phydev)
++{
++	/* we do all the (time consuming) work later */
++	return 0;
++}
++
++#ifdef CONFIG_GPIOLIB
++static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
++{
++	return GPIO_LINE_DIRECTION_OUT;
++}
++
++static int qca807x_gpio_get(struct gpio_chip *gc, unsigned int offset)
++{
++	struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
++	u16 reg;
++	int val;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(offset);
++	val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
++
++	return FIELD_GET(QCA807X_GPIO_FORCE_MODE_MASK, val);
++}
++
++static void qca807x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)
++{
++	struct qca807x_gpio_priv *priv = gpiochip_get_data(gc);
++	u16 reg;
++	int val;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(offset);
++
++	val = phy_read_mmd(priv->phy, MDIO_MMD_AN, reg);
++	val &= ~QCA807X_GPIO_FORCE_MODE_MASK;
++	val |= QCA807X_GPIO_FORCE_EN;
++	val |= FIELD_PREP(QCA807X_GPIO_FORCE_MODE_MASK, value);
++
++	phy_write_mmd(priv->phy, MDIO_MMD_AN, reg, val);
++}
++
++static int qca807x_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int value)
++{
++	qca807x_gpio_set(gc, offset, value);
++
++	return 0;
++}
++
++static int qca807x_gpio(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	struct qca807x_gpio_priv *priv;
++	struct gpio_chip *gc;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->phy = phydev;
++
++	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
++	if (!gc)
++		return -ENOMEM;
++
++	gc->label = dev_name(dev);
++	gc->base = -1;
++	gc->ngpio = 2;
++	gc->parent = dev;
++	gc->owner = THIS_MODULE;
++	gc->can_sleep = true;
++	gc->get_direction = qca807x_gpio_get_direction;
++	gc->direction_output = qca807x_gpio_dir_out;
++	gc->get = qca807x_gpio_get;
++	gc->set = qca807x_gpio_set;
++
++	return devm_gpiochip_add_data(dev, gc, priv);
++}
++#endif
++
++static int qca807x_read_fiber_status(struct phy_device *phydev)
++{
++	bool changed;
++	int ss, err;
++
++	err = genphy_c37_read_status(phydev, &changed);
++	if (err || !changed)
++		return err;
++
++	/* Read the QCA807x PHY-Specific Status register fiber page,
++	 * which indicates the speed and duplex that the PHY is actually
++	 * using, irrespective of whether we are in autoneg mode or not.
++	 */
++	ss = phy_read(phydev, AT803X_SPECIFIC_STATUS);
++	if (ss < 0)
++		return ss;
++
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	if (ss & AT803X_SS_SPEED_DUPLEX_RESOLVED) {
++		switch (FIELD_GET(AT803X_SS_SPEED_MASK, ss)) {
++		case AT803X_SS_SPEED_100:
++			phydev->speed = SPEED_100;
++			break;
++		case AT803X_SS_SPEED_1000:
++			phydev->speed = SPEED_1000;
++			break;
++		}
++
++		if (ss & AT803X_SS_DUPLEX)
++			phydev->duplex = DUPLEX_FULL;
++		else
++			phydev->duplex = DUPLEX_HALF;
++	}
++
++	return 0;
++}
++
++static int qca807x_read_status(struct phy_device *phydev)
++{
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported)) {
++		switch (phydev->port) {
++		case PORT_FIBRE:
++			return qca807x_read_fiber_status(phydev);
++		case PORT_TP:
++			return at803x_read_status(phydev);
++		default:
++			return -EINVAL;
++		}
++	}
++
++	return at803x_read_status(phydev);
++}
++
++static int qca807x_phy_package_probe_once(struct phy_device *phydev)
++{
++	struct phy_package_shared *shared = phydev->shared;
++	struct qca807x_shared_priv *priv = shared->priv;
++	unsigned int tx_drive_strength;
++	const char *package_mode_name;
++
++	/* Default to 600mw if not defined */
++	if (of_property_read_u32(shared->np, "qcom,tx-drive-strength-milliwatt",
++				 &tx_drive_strength))
++		tx_drive_strength = 600;
++
++	switch (tx_drive_strength) {
++	case 140:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_140MV;
++		break;
++	case 160:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_160MV;
++		break;
++	case 180:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_180MV;
++		break;
++	case 200:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_200MV;
++		break;
++	case 220:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_220MV;
++		break;
++	case 240:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_240MV;
++		break;
++	case 260:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_260MV;
++		break;
++	case 280:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_280MV;
++		break;
++	case 300:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_300MV;
++		break;
++	case 320:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_320MV;
++		break;
++	case 400:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_400MV;
++		break;
++	case 500:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_500MV;
++		break;
++	case 600:
++		priv->tx_drive_strength = PQSGMII_TX_DRIVER_600MV;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	priv->package_mode = PHY_INTERFACE_MODE_NA;
++	if (!of_property_read_string(shared->np, "qcom,package-mode",
++				     &package_mode_name)) {
++		if (!strcasecmp(package_mode_name,
++				phy_modes(PHY_INTERFACE_MODE_PSGMII)))
++			priv->package_mode = PHY_INTERFACE_MODE_PSGMII;
++		else if (!strcasecmp(package_mode_name,
++				     phy_modes(PHY_INTERFACE_MODE_QSGMII)))
++			priv->package_mode = PHY_INTERFACE_MODE_QSGMII;
++		else
++			return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int qca807x_phy_package_config_init_once(struct phy_device *phydev)
++{
++	struct phy_package_shared *shared = phydev->shared;
++	struct qca807x_shared_priv *priv = shared->priv;
++	int val, ret;
++
++	phy_lock_mdio_bus(phydev);
++
++	/* Set correct PHY package mode */
++	val = __phy_package_read(phydev, QCA807X_COMBO_ADDR,
++				 QCA807X_CHIP_CONFIGURATION);
++	val &= ~QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK;
++	/* package_mode can be QSGMII or PSGMII and we validate
++	 * this in probe_once.
++	 * With package_mode to NA, we default to PSGMII.
++	 */
++	switch (priv->package_mode) {
++	case PHY_INTERFACE_MODE_QSGMII:
++		val |= QCA807X_CHIP_CONFIGURATION_MODE_QSGMII_SGMII;
++		break;
++	case PHY_INTERFACE_MODE_PSGMII:
++	default:
++		val |= QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_ALL_COPPER;
++	}
++	ret = __phy_package_write(phydev, QCA807X_COMBO_ADDR,
++				  QCA807X_CHIP_CONFIGURATION, val);
++	if (ret)
++		goto exit;
++
++	/* After mode change Serdes reset is required */
++	val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
++				 PQSGMII_CTRL_REG);
++	val &= ~PQSGMII_ANALOG_SW_RESET;
++	ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
++				  PQSGMII_CTRL_REG, val);
++	if (ret)
++		goto exit;
++
++	msleep(SERDES_RESET_SLEEP);
++
++	val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
++				 PQSGMII_CTRL_REG);
++	val |= PQSGMII_ANALOG_SW_RESET;
++	ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
++				  PQSGMII_CTRL_REG, val);
++	if (ret)
++		goto exit;
++
++	/* Workaround to enable AZ transmitting ability */
++	val = __phy_package_read_mmd(phydev, QCA807X_PQSGMII_ADDR,
++				     MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL);
++	val &= ~PQSGMII_MODE_CTRL_AZ_WORKAROUND_MASK;
++	ret = __phy_package_write_mmd(phydev, QCA807X_PQSGMII_ADDR,
++				      MDIO_MMD_PMAPMD, PQSGMII_MODE_CTRL, val);
++	if (ret)
++		goto exit;
++
++	/* Set PQSGMII TX AMP strength */
++	val = __phy_package_read(phydev, QCA807X_PQSGMII_ADDR,
++				 PQSGMII_DRIVE_CONTROL_1);
++	val &= ~PQSGMII_TX_DRIVER_MASK;
++	val |= FIELD_PREP(PQSGMII_TX_DRIVER_MASK, priv->tx_drive_strength);
++	ret = __phy_package_write(phydev, QCA807X_PQSGMII_ADDR,
++				  PQSGMII_DRIVE_CONTROL_1, val);
++	if (ret)
++		goto exit;
++
++	/* Prevent PSGMII going into hibernation via PSGMII self test */
++	val = __phy_package_read_mmd(phydev, QCA807X_COMBO_ADDR,
++				     MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL);
++	val &= ~BIT(1);
++	ret = __phy_package_write_mmd(phydev, QCA807X_COMBO_ADDR,
++				      MDIO_MMD_PCS, PQSGMII_MMD3_SERDES_CONTROL, val);
++
++exit:
++	phy_unlock_mdio_bus(phydev);
++
++	return ret;
++}
++
++static int qca807x_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
++{
++	struct phy_device *phydev = upstream;
++	__ETHTOOL_DECLARE_LINK_MODE_MASK(support) = { 0, };
++	phy_interface_t iface;
++	int ret;
++	DECLARE_PHY_INTERFACE_MASK(interfaces);
++
++	sfp_parse_support(phydev->sfp_bus, id, support, interfaces);
++	iface = sfp_select_interface(phydev->sfp_bus, support);
++
++	dev_info(&phydev->mdio.dev, "%s SFP module inserted\n", phy_modes(iface));
++
++	switch (iface) {
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_100BASEX:
++		/* Set PHY mode to PSGMII combo (1/4 copper + combo ports) mode */
++		ret = phy_modify(phydev,
++				 QCA807X_CHIP_CONFIGURATION,
++				 QCA807X_CHIP_CONFIGURATION_MODE_CFG_MASK,
++				 QCA807X_CHIP_CONFIGURATION_MODE_PSGMII_FIBER);
++		/* Enable fiber mode autodection (1000Base-X or 100Base-FX) */
++		ret = phy_set_bits_mmd(phydev,
++				       MDIO_MMD_AN,
++				       QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION,
++				       QCA807X_MMD7_FIBER_MODE_AUTO_DETECTION_EN);
++		/* Select fiber page */
++		ret = phy_clear_bits(phydev,
++				     QCA807X_CHIP_CONFIGURATION,
++				     QCA807X_BT_BX_REG_SEL);
++
++		phydev->port = PORT_FIBRE;
++		break;
++	default:
++		dev_err(&phydev->mdio.dev, "Incompatible SFP module inserted\n");
++		return -EINVAL;
++	}
++
++	return ret;
++}
++
++static void qca807x_sfp_remove(void *upstream)
++{
++	struct phy_device *phydev = upstream;
++
++	/* Select copper page */
++	phy_set_bits(phydev,
++		     QCA807X_CHIP_CONFIGURATION,
++		     QCA807X_BT_BX_REG_SEL);
++
++	phydev->port = PORT_TP;
++}
++
++static const struct sfp_upstream_ops qca807x_sfp_ops = {
++	.attach = phy_sfp_attach,
++	.detach = phy_sfp_detach,
++	.module_insert = qca807x_sfp_insert,
++	.module_remove = qca807x_sfp_remove,
++};
++
++static int qca807x_probe(struct phy_device *phydev)
++{
++	struct device_node *node = phydev->mdio.dev.of_node;
++	struct qca807x_shared_priv *shared_priv;
++	struct device *dev = &phydev->mdio.dev;
++	struct phy_package_shared *shared;
++	struct qca807x_priv *priv;
++	int ret;
++
++	ret = devm_of_phy_package_join(dev, phydev, sizeof(*shared_priv));
++	if (ret)
++		return ret;
++
++	if (phy_package_probe_once(phydev)) {
++		ret = qca807x_phy_package_probe_once(phydev);
++		if (ret)
++			return ret;
++	}
++
++	shared = phydev->shared;
++	shared_priv = shared->priv;
++
++	/* Make sure PHY follow PHY package mode if enforced */
++	if (shared_priv->package_mode != PHY_INTERFACE_MODE_NA &&
++	    phydev->interface != shared_priv->package_mode)
++		return -EINVAL;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->dac_full_amplitude = of_property_read_bool(node, "qcom,dac-full-amplitude");
++	priv->dac_full_bias_current = of_property_read_bool(node, "qcom,dac-full-bias-current");
++	priv->dac_disable_bias_current_tweak = of_property_read_bool(node,
++								     "qcom,dac-disable-bias-current-tweak");
++
++	if (IS_ENABLED(CONFIG_GPIOLIB)) {
++		/* Do not register a GPIO controller unless flagged for it */
++		if (of_property_read_bool(node, "gpio-controller")) {
++			ret = qca807x_gpio(phydev);
++			if (ret)
++				return ret;
++		}
++	}
++
++	/* Attach SFP bus on combo port*/
++	if (phy_read(phydev, QCA807X_CHIP_CONFIGURATION)) {
++		ret = phy_sfp_probe(phydev, &qca807x_sfp_ops);
++		if (ret)
++			return ret;
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->supported);
++		linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, phydev->advertising);
++	}
++
++	phydev->priv = priv;
++
++	return 0;
++}
++
++static int qca807x_config_init(struct phy_device *phydev)
++{
++	struct qca807x_priv *priv = phydev->priv;
++	u16 control_dac;
++	int ret;
++
++	if (phy_package_init_once(phydev)) {
++		ret = qca807x_phy_package_config_init_once(phydev);
++		if (ret)
++			return ret;
++	}
++
++	control_dac = phy_read_mmd(phydev, MDIO_MMD_AN,
++				   QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH);
++	control_dac &= ~QCA807X_CONTROL_DAC_MASK;
++	if (!priv->dac_full_amplitude)
++		control_dac |= QCA807X_CONTROL_DAC_DSP_AMPLITUDE;
++	if (!priv->dac_full_amplitude)
++		control_dac |= QCA807X_CONTROL_DAC_DSP_BIAS_CURRENT;
++	if (!priv->dac_disable_bias_current_tweak)
++		control_dac |= QCA807X_CONTROL_DAC_BIAS_CURRENT_TWEAK;
++	return phy_write_mmd(phydev, MDIO_MMD_AN,
++			     QCA807X_MMD7_1000BASE_T_POWER_SAVE_PER_CABLE_LENGTH,
++			     control_dac);
++}
++
++static struct phy_driver qca807x_drivers[] = {
++	{
++		PHY_ID_MATCH_EXACT(PHY_ID_QCA8072),
++		.name           = "Qualcomm QCA8072",
++		.flags		= PHY_POLL_CABLE_TEST,
++		/* PHY_GBIT_FEATURES */
++		.probe		= qca807x_probe,
++		.config_init	= qca807x_config_init,
++		.read_status	= qca807x_read_status,
++		.config_intr	= at803x_config_intr,
++		.handle_interrupt = at803x_handle_interrupt,
++		.soft_reset	= genphy_soft_reset,
++		.get_tunable	= at803x_get_tunable,
++		.set_tunable	= at803x_set_tunable,
++		.resume		= genphy_resume,
++		.suspend	= genphy_suspend,
++		.cable_test_start	= qca807x_cable_test_start,
++		.cable_test_get_status	= qca808x_cable_test_get_status,
++	},
++	{
++		PHY_ID_MATCH_EXACT(PHY_ID_QCA8075),
++		.name           = "Qualcomm QCA8075",
++		.flags		= PHY_POLL_CABLE_TEST,
++		/* PHY_GBIT_FEATURES */
++		.probe		= qca807x_probe,
++		.config_init	= qca807x_config_init,
++		.read_status	= qca807x_read_status,
++		.config_intr	= at803x_config_intr,
++		.handle_interrupt = at803x_handle_interrupt,
++		.soft_reset	= genphy_soft_reset,
++		.get_tunable	= at803x_get_tunable,
++		.set_tunable	= at803x_set_tunable,
++		.resume		= genphy_resume,
++		.suspend	= genphy_suspend,
++		.cable_test_start	= qca807x_cable_test_start,
++		.cable_test_get_status	= qca808x_cable_test_get_status,
++	},
++};
++module_phy_driver(qca807x_drivers);
++
++static struct mdio_device_id __maybe_unused qca807x_tbl[] = {
++	{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8072) },
++	{ PHY_ID_MATCH_EXACT(PHY_ID_QCA8075) },
++	{ }
++};
++
++MODULE_AUTHOR("Robert Marko <robert.marko@sartura.hr>");
++MODULE_AUTHOR("Christian Marangi <ansuelsmth@gmail.com>");
++MODULE_DESCRIPTION("Qualcomm QCA807x PHY driver");
++MODULE_DEVICE_TABLE(mdio, qca807x_tbl);
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/backport-6.1/716-v6.9-08-net-phy-qcom-move-common-qca808x-LED-define-to-share.patch b/target/linux/generic/backport-6.1/716-v6.9-08-net-phy-qcom-move-common-qca808x-LED-define-to-share.patch
new file mode 100644
index 00000000000..cf4d74e8c52
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-08-net-phy-qcom-move-common-qca808x-LED-define-to-share.patch
@@ -0,0 +1,179 @@
+From ee9d9807bee0e6af8ca2a4db6f0d1dc0e5b41f44 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:11 +0100
+Subject: [PATCH 08/10] net: phy: qcom: move common qca808x LED define to
+ shared header
+
+The LED implementation of qca808x and qca807x is the same but qca807x
+supports also Fiber port and have different hw control bits for Fiber
+port.
+
+In preparation for qca807x introduction, move all the common define to
+shared header.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c | 65 ----------------------------------
+ drivers/net/phy/qcom/qcom.h    | 65 ++++++++++++++++++++++++++++++++++
+ 2 files changed, 65 insertions(+), 65 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -62,29 +62,6 @@
+ #define QCA808X_DBG_AN_TEST			0xb
+ #define QCA808X_HIBERNATION_EN			BIT(15)
+ 
+-#define QCA808X_MMD7_LED_GLOBAL			0x8073
+-#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
+-#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
+-/* Values are the same for both BLINK_1 and BLINK_2 */
+-#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
+-#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
+-#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
+-#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
+-#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
+-#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
+-#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
+-#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
+-#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
+-#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
+-#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
+-#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
+-#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
+-#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
+-#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
+-#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
+-#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
+-#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
+-
+ #define QCA808X_MMD7_LED2_CTRL			0x8074
+ #define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
+ #define QCA808X_MMD7_LED1_CTRL			0x8076
+@@ -92,51 +69,9 @@
+ #define QCA808X_MMD7_LED0_CTRL			0x8078
+ #define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
+ 
+-/* LED hw control pattern is the same for every LED */
+-#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
+-#define QCA808X_LED_SPEED2500_ON		BIT(15)
+-#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
+-/* Follow blink trigger even if duplex or speed condition doesn't match */
+-#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
+-#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
+-#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
+-#define QCA808X_LED_TX_BLINK			BIT(10)
+-#define QCA808X_LED_RX_BLINK			BIT(9)
+-#define QCA808X_LED_TX_ON_10MS			BIT(8)
+-#define QCA808X_LED_RX_ON_10MS			BIT(7)
+-#define QCA808X_LED_SPEED1000_ON		BIT(6)
+-#define QCA808X_LED_SPEED100_ON			BIT(5)
+-#define QCA808X_LED_SPEED10_ON			BIT(4)
+-#define QCA808X_LED_COLLISION_BLINK		BIT(3)
+-#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
+-#define QCA808X_LED_SPEED100_BLINK		BIT(1)
+-#define QCA808X_LED_SPEED10_BLINK		BIT(0)
+-
+ #define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
+ #define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
+ 
+-/* LED force ctrl is the same for every LED
+- * No documentation exist for this, not even internal one
+- * with NDA as QCOM gives only info about configuring
+- * hw control pattern rules and doesn't indicate any way
+- * to force the LED to specific mode.
+- * These define comes from reverse and testing and maybe
+- * lack of some info or some info are not entirely correct.
+- * For the basic LED control and hw control these finding
+- * are enough to support LED control in all the required APIs.
+- *
+- * On doing some comparison with implementation with qca807x,
+- * it was found that it's 1:1 equal to it and confirms all the
+- * reverse done. It was also found further specification with the
+- * force mode and the blink modes.
+- */
+-#define QCA808X_LED_FORCE_EN			BIT(15)
+-#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
+-#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
+-#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
+-#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
+-#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
+-
+ #define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
+ /* QSDK sets by default 0x46 to this reg that sets BIT 6 for
+  * LED to active high. It's not clear what BIT 3 and BIT 4 does.
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -103,6 +103,71 @@
+ /* Added for reference of existence but should be handled by wait_for_completion already */
+ #define QCA808X_CDT_STATUS_STAT_BUSY		(BIT(1) | BIT(3))
+ 
++#define QCA808X_MMD7_LED_GLOBAL			0x8073
++#define QCA808X_LED_BLINK_1			GENMASK(11, 6)
++#define QCA808X_LED_BLINK_2			GENMASK(5, 0)
++/* Values are the same for both BLINK_1 and BLINK_2 */
++#define QCA808X_LED_BLINK_FREQ_MASK		GENMASK(5, 3)
++#define QCA808X_LED_BLINK_FREQ_2HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x0)
++#define QCA808X_LED_BLINK_FREQ_4HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x1)
++#define QCA808X_LED_BLINK_FREQ_8HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x2)
++#define QCA808X_LED_BLINK_FREQ_16HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x3)
++#define QCA808X_LED_BLINK_FREQ_32HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x4)
++#define QCA808X_LED_BLINK_FREQ_64HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x5)
++#define QCA808X_LED_BLINK_FREQ_128HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x6)
++#define QCA808X_LED_BLINK_FREQ_256HZ		FIELD_PREP(QCA808X_LED_BLINK_FREQ_MASK, 0x7)
++#define QCA808X_LED_BLINK_DUTY_MASK		GENMASK(2, 0)
++#define QCA808X_LED_BLINK_DUTY_50_50		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x0)
++#define QCA808X_LED_BLINK_DUTY_75_25		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x1)
++#define QCA808X_LED_BLINK_DUTY_25_75		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x2)
++#define QCA808X_LED_BLINK_DUTY_33_67		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x3)
++#define QCA808X_LED_BLINK_DUTY_67_33		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x4)
++#define QCA808X_LED_BLINK_DUTY_17_83		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x5)
++#define QCA808X_LED_BLINK_DUTY_83_17		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x6)
++#define QCA808X_LED_BLINK_DUTY_8_92		FIELD_PREP(QCA808X_LED_BLINK_DUTY_MASK, 0x7)
++
++/* LED hw control pattern is the same for every LED */
++#define QCA808X_LED_PATTERN_MASK		GENMASK(15, 0)
++#define QCA808X_LED_SPEED2500_ON		BIT(15)
++#define QCA808X_LED_SPEED2500_BLINK		BIT(14)
++/* Follow blink trigger even if duplex or speed condition doesn't match */
++#define QCA808X_LED_BLINK_CHECK_BYPASS		BIT(13)
++#define QCA808X_LED_FULL_DUPLEX_ON		BIT(12)
++#define QCA808X_LED_HALF_DUPLEX_ON		BIT(11)
++#define QCA808X_LED_TX_BLINK			BIT(10)
++#define QCA808X_LED_RX_BLINK			BIT(9)
++#define QCA808X_LED_TX_ON_10MS			BIT(8)
++#define QCA808X_LED_RX_ON_10MS			BIT(7)
++#define QCA808X_LED_SPEED1000_ON		BIT(6)
++#define QCA808X_LED_SPEED100_ON			BIT(5)
++#define QCA808X_LED_SPEED10_ON			BIT(4)
++#define QCA808X_LED_COLLISION_BLINK		BIT(3)
++#define QCA808X_LED_SPEED1000_BLINK		BIT(2)
++#define QCA808X_LED_SPEED100_BLINK		BIT(1)
++#define QCA808X_LED_SPEED10_BLINK		BIT(0)
++
++/* LED force ctrl is the same for every LED
++ * No documentation exist for this, not even internal one
++ * with NDA as QCOM gives only info about configuring
++ * hw control pattern rules and doesn't indicate any way
++ * to force the LED to specific mode.
++ * These define comes from reverse and testing and maybe
++ * lack of some info or some info are not entirely correct.
++ * For the basic LED control and hw control these finding
++ * are enough to support LED control in all the required APIs.
++ *
++ * On doing some comparison with implementation with qca807x,
++ * it was found that it's 1:1 equal to it and confirms all the
++ * reverse done. It was also found further specification with the
++ * force mode and the blink modes.
++ */
++#define QCA808X_LED_FORCE_EN			BIT(15)
++#define QCA808X_LED_FORCE_MODE_MASK		GENMASK(14, 13)
++#define QCA808X_LED_FORCE_BLINK_1		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x3)
++#define QCA808X_LED_FORCE_BLINK_2		FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x2)
++#define QCA808X_LED_FORCE_ON			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x1)
++#define QCA808X_LED_FORCE_OFF			FIELD_PREP(QCA808X_LED_FORCE_MODE_MASK, 0x0)
++
+ #define AT803X_LOC_MAC_ADDR_0_15_OFFSET		0x804C
+ #define AT803X_LOC_MAC_ADDR_16_31_OFFSET	0x804B
+ #define AT803X_LOC_MAC_ADDR_32_47_OFFSET	0x804A
diff --git a/target/linux/generic/backport-6.1/716-v6.9-09-net-phy-qcom-generalize-some-qca808x-LED-functions.patch b/target/linux/generic/backport-6.1/716-v6.9-09-net-phy-qcom-generalize-some-qca808x-LED-functions.patch
new file mode 100644
index 00000000000..da73c1d3b89
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-09-net-phy-qcom-generalize-some-qca808x-LED-functions.patch
@@ -0,0 +1,172 @@
+From 47b930d0dd437af927145dba50a2e2ea1ba97c67 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:12 +0100
+Subject: [PATCH 09/10] net: phy: qcom: generalize some qca808x LED functions
+
+Generalize some qca808x LED functions in preparation for qca807x LED
+support.
+
+The LED implementation of qca808x and qca807x is the same but qca807x
+supports also Fiber port and have different hw control bits for Fiber
+port. To limit code duplication introduce micro functions that takes reg
+instead of LED index to tweak all the supported LED modes.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca808x.c      | 38 +++-----------------
+ drivers/net/phy/qcom/qcom-phy-lib.c | 54 +++++++++++++++++++++++++++++
+ drivers/net/phy/qcom/qcom.h         |  7 ++++
+ 3 files changed, 65 insertions(+), 34 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca808x.c
++++ b/drivers/net/phy/qcom/qca808x.c
+@@ -437,9 +437,7 @@ static int qca808x_led_hw_control_enable
+ 		return -EINVAL;
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
+-				  QCA808X_LED_FORCE_EN);
++	return qca808x_led_reg_hw_control_enable(phydev, reg);
+ }
+ 
+ static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
+@@ -480,16 +478,12 @@ static int qca808x_led_hw_control_set(st
+ static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
+ {
+ 	u16 reg;
+-	int val;
+ 
+ 	if (index > 2)
+ 		return false;
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
+-
+-	return !(val & QCA808X_LED_FORCE_EN);
++	return qca808x_led_reg_hw_control_status(phydev, reg);
+ }
+ 
+ static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
+@@ -557,44 +551,20 @@ static int qca808x_led_brightness_set(st
+ 	}
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			      QCA808X_LED_FORCE_EN | (value ? QCA808X_LED_FORCE_ON :
+-							     QCA808X_LED_FORCE_OFF));
++	return qca808x_led_reg_brightness_set(phydev, reg, value);
+ }
+ 
+ static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
+ 				 unsigned long *delay_on,
+ 				 unsigned long *delay_off)
+ {
+-	int ret;
+ 	u16 reg;
+ 
+ 	if (index > 2)
+ 		return -EINVAL;
+ 
+ 	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
+-
+-	/* Set blink to 50% off, 50% on at 4Hz by default */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
+-			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
+-			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
+-	if (ret)
+-		return ret;
+-
+-	/* We use BLINK_1 for normal blinking */
+-	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
+-			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
+-	if (ret)
+-		return ret;
+-
+-	/* We set blink to 4Hz, aka 250ms */
+-	*delay_on = 250 / 2;
+-	*delay_off = 250 / 2;
+-
+-	return 0;
++	return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
+ }
+ 
+ static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
+--- a/drivers/net/phy/qcom/qcom-phy-lib.c
++++ b/drivers/net/phy/qcom/qcom-phy-lib.c
+@@ -620,3 +620,57 @@ int qca808x_cable_test_get_status(struct
+ 	return 0;
+ }
+ EXPORT_SYMBOL_GPL(qca808x_cable_test_get_status);
++
++int qca808x_led_reg_hw_control_enable(struct phy_device *phydev, u16 reg)
++{
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
++				  QCA808X_LED_FORCE_EN);
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_hw_control_enable);
++
++bool qca808x_led_reg_hw_control_status(struct phy_device *phydev, u16 reg)
++{
++	int val;
++
++	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++	return !(val & QCA808X_LED_FORCE_EN);
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_hw_control_status);
++
++int qca808x_led_reg_brightness_set(struct phy_device *phydev,
++				   u16 reg, enum led_brightness value)
++{
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			      QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			      QCA808X_LED_FORCE_EN | (value ? QCA808X_LED_FORCE_ON :
++							      QCA808X_LED_FORCE_OFF));
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_brightness_set);
++
++int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg,
++			      unsigned long *delay_on,
++			      unsigned long *delay_off)
++{
++	int ret;
++
++	/* Set blink to 50% off, 50% on at 4Hz by default */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, QCA808X_MMD7_LED_GLOBAL,
++			     QCA808X_LED_BLINK_FREQ_MASK | QCA808X_LED_BLINK_DUTY_MASK,
++			     QCA808X_LED_BLINK_FREQ_4HZ | QCA808X_LED_BLINK_DUTY_50_50);
++	if (ret)
++		return ret;
++
++	/* We use BLINK_1 for normal blinking */
++	ret = phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_MODE_MASK,
++			     QCA808X_LED_FORCE_EN | QCA808X_LED_FORCE_BLINK_1);
++	if (ret)
++		return ret;
++
++	/* We set blink to 4Hz, aka 250ms */
++	*delay_on = 250 / 2;
++	*delay_off = 250 / 2;
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(qca808x_led_reg_blink_set);
+--- a/drivers/net/phy/qcom/qcom.h
++++ b/drivers/net/phy/qcom/qcom.h
+@@ -234,3 +234,10 @@ int at803x_cdt_start(struct phy_device *
+ int at803x_cdt_wait_for_completion(struct phy_device *phydev,
+ 				   u32 cdt_en);
+ int qca808x_cable_test_get_status(struct phy_device *phydev, bool *finished);
++int qca808x_led_reg_hw_control_enable(struct phy_device *phydev, u16 reg);
++bool qca808x_led_reg_hw_control_status(struct phy_device *phydev, u16 reg);
++int qca808x_led_reg_brightness_set(struct phy_device *phydev,
++				   u16 reg, enum led_brightness value);
++int qca808x_led_reg_blink_set(struct phy_device *phydev, u16 reg,
++			      unsigned long *delay_on,
++			      unsigned long *delay_off);
diff --git a/target/linux/generic/backport-6.1/716-v6.9-10-net-phy-qca807x-add-support-for-configurable-LED.patch b/target/linux/generic/backport-6.1/716-v6.9-10-net-phy-qca807x-add-support-for-configurable-LED.patch
new file mode 100644
index 00000000000..3bd36f6ffe2
--- /dev/null
+++ b/target/linux/generic/backport-6.1/716-v6.9-10-net-phy-qca807x-add-support-for-configurable-LED.patch
@@ -0,0 +1,326 @@
+From f508a226b517a6a8afd78a317de46bc83e3e3d51 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 6 Feb 2024 18:31:13 +0100
+Subject: [PATCH 10/10] net: phy: qca807x: add support for configurable LED
+
+QCA8072/5 have up to 2 LEDs attached for PHY.
+
+LEDs can be configured to be ON/hw blink or be set to HW control.
+
+Hw blink mode is set to blink at 4Hz or 250ms.
+
+PHY can support both copper (TP) or fiber (FIBRE) kind and supports
+different HW control modes based on the port type.
+
+HW control modes supported for netdev trigger for copper ports are:
+- LINK_10
+- LINK_100
+- LINK_1000
+- TX
+- RX
+- FULL_DUPLEX
+- HALF_DUPLEX
+
+HW control modes supported for netdev trigger for fiber ports are:
+- LINK_100
+- LINK_1000
+- TX
+- RX
+- FULL_DUPLEX
+- HALF_DUPLEX
+
+LED support conflicts with GPIO controller feature and must be disabled
+if gpio-controller is used for the PHY.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/phy/qcom/qca807x.c | 256 ++++++++++++++++++++++++++++++++-
+ 1 file changed, 254 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca807x.c
++++ b/drivers/net/phy/qcom/qca807x.c
+@@ -57,8 +57,18 @@
+ #define QCA807X_MMD7_LED_CTRL(x)			(0x8074 + ((x) * 2))
+ #define QCA807X_MMD7_LED_FORCE_CTRL(x)			(0x8075 + ((x) * 2))
+ 
+-#define QCA807X_GPIO_FORCE_EN				BIT(15)
+-#define QCA807X_GPIO_FORCE_MODE_MASK			GENMASK(14, 13)
++/* LED hw control pattern for fiber port */
++#define QCA807X_LED_FIBER_PATTERN_MASK			GENMASK(11, 1)
++#define QCA807X_LED_FIBER_TXACT_BLK_EN			BIT(10)
++#define QCA807X_LED_FIBER_RXACT_BLK_EN			BIT(9)
++#define QCA807X_LED_FIBER_FDX_ON_EN			BIT(6)
++#define QCA807X_LED_FIBER_HDX_ON_EN			BIT(5)
++#define QCA807X_LED_FIBER_1000BX_ON_EN			BIT(2)
++#define QCA807X_LED_FIBER_100FX_ON_EN			BIT(1)
++
++/* Some device repurpose the LED as GPIO out */
++#define QCA807X_GPIO_FORCE_EN				QCA808X_LED_FORCE_EN
++#define QCA807X_GPIO_FORCE_MODE_MASK			QCA808X_LED_FORCE_MODE_MASK
+ 
+ #define QCA807X_FUNCTION_CONTROL			0x10
+ #define QCA807X_FC_MDI_CROSSOVER_MODE_MASK		GENMASK(6, 5)
+@@ -121,6 +131,233 @@ static int qca807x_cable_test_start(stru
+ 	return 0;
+ }
+ 
++static int qca807x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
++				    u16 *offload_trigger)
++{
++	/* Parsing specific to netdev trigger */
++	switch (phydev->port) {
++	case PORT_TP:
++		if (test_bit(TRIGGER_NETDEV_TX, &rules))
++			*offload_trigger |= QCA808X_LED_TX_BLINK;
++		if (test_bit(TRIGGER_NETDEV_RX, &rules))
++			*offload_trigger |= QCA808X_LED_RX_BLINK;
++		if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
++			*offload_trigger |= QCA808X_LED_SPEED10_ON;
++		if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++			*offload_trigger |= QCA808X_LED_SPEED100_ON;
++		if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++			*offload_trigger |= QCA808X_LED_SPEED1000_ON;
++		if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++			*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
++		if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++			*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
++		break;
++	case PORT_FIBRE:
++		if (test_bit(TRIGGER_NETDEV_TX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_TXACT_BLK_EN;
++		if (test_bit(TRIGGER_NETDEV_RX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_RXACT_BLK_EN;
++		if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_100FX_ON_EN;
++		if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_1000BX_ON_EN;
++		if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_HDX_ON_EN;
++		if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
++			*offload_trigger |= QCA807X_LED_FIBER_FDX_ON_EN;
++		break;
++	default:
++		return -EOPNOTSUPP;
++	}
++
++	if (rules && !*offload_trigger)
++		return -EOPNOTSUPP;
++
++	return 0;
++}
++
++static int qca807x_led_hw_control_enable(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 1)
++		return -EINVAL;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_hw_control_enable(phydev, reg);
++}
++
++static int qca807x_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	u16 offload_trigger = 0;
++
++	if (index > 1)
++		return -EINVAL;
++
++	return qca807x_led_parse_netdev(phydev, rules, &offload_trigger);
++}
++
++static int qca807x_led_hw_control_set(struct phy_device *phydev, u8 index,
++				      unsigned long rules)
++{
++	u16 reg, mask, offload_trigger = 0;
++	int ret;
++
++	if (index > 1)
++		return -EINVAL;
++
++	ret = qca807x_led_parse_netdev(phydev, rules, &offload_trigger);
++	if (ret)
++		return ret;
++
++	ret = qca807x_led_hw_control_enable(phydev, index);
++	if (ret)
++		return ret;
++
++	switch (phydev->port) {
++	case PORT_TP:
++		reg = QCA807X_MMD7_LED_CTRL(index);
++		mask = QCA808X_LED_PATTERN_MASK;
++		break;
++	case PORT_FIBRE:
++		/* HW control pattern bits are in LED FORCE reg */
++		reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++		mask = QCA807X_LED_FIBER_PATTERN_MASK;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg, mask,
++			      offload_trigger);
++}
++
++static bool qca807x_led_hw_control_status(struct phy_device *phydev, u8 index)
++{
++	u16 reg;
++
++	if (index > 1)
++		return false;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_hw_control_status(phydev, reg);
++}
++
++static int qca807x_led_hw_control_get(struct phy_device *phydev, u8 index,
++				      unsigned long *rules)
++{
++	u16 reg;
++	int val;
++
++	if (index > 1)
++		return -EINVAL;
++
++	/* Check if we have hw control enabled */
++	if (qca807x_led_hw_control_status(phydev, index))
++		return -EINVAL;
++
++	/* Parsing specific to netdev trigger */
++	switch (phydev->port) {
++	case PORT_TP:
++		reg = QCA807X_MMD7_LED_CTRL(index);
++		val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++		if (val & QCA808X_LED_TX_BLINK)
++			set_bit(TRIGGER_NETDEV_TX, rules);
++		if (val & QCA808X_LED_RX_BLINK)
++			set_bit(TRIGGER_NETDEV_RX, rules);
++		if (val & QCA808X_LED_SPEED10_ON)
++			set_bit(TRIGGER_NETDEV_LINK_10, rules);
++		if (val & QCA808X_LED_SPEED100_ON)
++			set_bit(TRIGGER_NETDEV_LINK_100, rules);
++		if (val & QCA808X_LED_SPEED1000_ON)
++			set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++		if (val & QCA808X_LED_HALF_DUPLEX_ON)
++			set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++		if (val & QCA808X_LED_FULL_DUPLEX_ON)
++			set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++		break;
++	case PORT_FIBRE:
++		/* HW control pattern bits are in LED FORCE reg */
++		reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++		val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
++		if (val & QCA807X_LED_FIBER_TXACT_BLK_EN)
++			set_bit(TRIGGER_NETDEV_TX, rules);
++		if (val & QCA807X_LED_FIBER_RXACT_BLK_EN)
++			set_bit(TRIGGER_NETDEV_RX, rules);
++		if (val & QCA807X_LED_FIBER_100FX_ON_EN)
++			set_bit(TRIGGER_NETDEV_LINK_100, rules);
++		if (val & QCA807X_LED_FIBER_1000BX_ON_EN)
++			set_bit(TRIGGER_NETDEV_LINK_1000, rules);
++		if (val & QCA807X_LED_FIBER_HDX_ON_EN)
++			set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
++		if (val & QCA807X_LED_FIBER_FDX_ON_EN)
++			set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int qca807x_led_hw_control_reset(struct phy_device *phydev, u8 index)
++{
++	u16 reg, mask;
++
++	if (index > 1)
++		return -EINVAL;
++
++	switch (phydev->port) {
++	case PORT_TP:
++		reg = QCA807X_MMD7_LED_CTRL(index);
++		mask = QCA808X_LED_PATTERN_MASK;
++		break;
++	case PORT_FIBRE:
++		/* HW control pattern bits are in LED FORCE reg */
++		reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++		mask = QCA807X_LED_FIBER_PATTERN_MASK;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg, mask);
++}
++
++static int qca807x_led_brightness_set(struct phy_device *phydev,
++				      u8 index, enum led_brightness value)
++{
++	u16 reg;
++	int ret;
++
++	if (index > 1)
++		return -EINVAL;
++
++	/* If we are setting off the LED reset any hw control rule */
++	if (!value) {
++		ret = qca807x_led_hw_control_reset(phydev, index);
++		if (ret)
++			return ret;
++	}
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_brightness_set(phydev, reg, value);
++}
++
++static int qca807x_led_blink_set(struct phy_device *phydev, u8 index,
++				 unsigned long *delay_on,
++				 unsigned long *delay_off)
++{
++	u16 reg;
++
++	if (index > 1)
++		return -EINVAL;
++
++	reg = QCA807X_MMD7_LED_FORCE_CTRL(index);
++	return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
++}
++
+ #ifdef CONFIG_GPIOLIB
+ static int qca807x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)
+ {
+@@ -496,6 +733,16 @@ static int qca807x_probe(struct phy_devi
+ 								     "qcom,dac-disable-bias-current-tweak");
+ 
+ 	if (IS_ENABLED(CONFIG_GPIOLIB)) {
++		/* Make sure we don't have mixed leds node and gpio-controller
++		 * to prevent registering leds and having gpio-controller usage
++		 * conflicting with them.
++		 */
++		if (of_find_property(node, "leds", NULL) &&
++		    of_find_property(node, "gpio-controller", NULL)) {
++			phydev_err(phydev, "Invalid property detected. LEDs and gpio-controller are mutually exclusive.");
++			return -EINVAL;
++		}
++
+ 		/* Do not register a GPIO controller unless flagged for it */
+ 		if (of_property_read_bool(node, "gpio-controller")) {
+ 			ret = qca807x_gpio(phydev);
+@@ -580,6 +827,11 @@ static struct phy_driver qca807x_drivers
+ 		.suspend	= genphy_suspend,
+ 		.cable_test_start	= qca807x_cable_test_start,
+ 		.cable_test_get_status	= qca808x_cable_test_get_status,
++		.led_brightness_set = qca807x_led_brightness_set,
++		.led_blink_set = qca807x_led_blink_set,
++		.led_hw_is_supported = qca807x_led_hw_is_supported,
++		.led_hw_control_set = qca807x_led_hw_control_set,
++		.led_hw_control_get = qca807x_led_hw_control_get,
+ 	},
+ };
+ module_phy_driver(qca807x_drivers);
diff --git a/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch b/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
new file mode 100644
index 00000000000..53652c38fc0
--- /dev/null
+++ b/target/linux/generic/backport-6.1/717-v6.9-net-phy-qca807x-move-interface-mode-check-to-.config.patch
@@ -0,0 +1,51 @@
+From 3be0d950b62852a693182cb678948f481de02825 Mon Sep 17 00:00:00 2001
+From: Robert Marko <robimarko@gmail.com>
+Date: Mon, 12 Feb 2024 12:49:34 +0100
+Subject: [PATCH] net: phy: qca807x: move interface mode check to
+ .config_init_once
+
+Currently, we are checking whether the PHY package mode matches the
+individual PHY interface modes at PHY package probe time, but at that time
+we only know the PHY package mode and not the individual PHY interface
+modes as of_get_phy_mode() that populates it will only get called once the
+netdev to which PHY-s are attached to is being probed and thus this check
+will always fail and return -EINVAL.
+
+So, lets move this check to .config_init_once as at that point individual
+PHY interface modes should be populated.
+
+Fixes: d1cb613efbd3 ("net: phy: qcom: add support for QCA807x PHY Family")
+Signed-off-by: Robert Marko <robimarko@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240212115043.1725918-1-robimarko@gmail.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/qcom/qca807x.c | 10 +++++-----
+ 1 file changed, 5 insertions(+), 5 deletions(-)
+
+--- a/drivers/net/phy/qcom/qca807x.c
++++ b/drivers/net/phy/qcom/qca807x.c
+@@ -562,6 +562,11 @@ static int qca807x_phy_package_config_in
+ 	struct qca807x_shared_priv *priv = shared->priv;
+ 	int val, ret;
+ 
++	/* Make sure PHY follow PHY package mode if enforced */
++	if (priv->package_mode != PHY_INTERFACE_MODE_NA &&
++	    phydev->interface != priv->package_mode)
++		return -EINVAL;
++
+ 	phy_lock_mdio_bus(phydev);
+ 
+ 	/* Set correct PHY package mode */
+@@ -718,11 +723,6 @@ static int qca807x_probe(struct phy_devi
+ 	shared = phydev->shared;
+ 	shared_priv = shared->priv;
+ 
+-	/* Make sure PHY follow PHY package mode if enforced */
+-	if (shared_priv->package_mode != PHY_INTERFACE_MODE_NA &&
+-	    phydev->interface != shared_priv->package_mode)
+-		return -EINVAL;
+-
+ 	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ 	if (!priv)
+ 		return -ENOMEM;
diff --git a/target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch b/target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
new file mode 100644
index 00000000000..e6a240dbdae
--- /dev/null
+++ b/target/linux/generic/backport-6.1/720-v6.9-net-mdio-ipq4019-add-support-for-clock-frequency-pro.patch
@@ -0,0 +1,205 @@
+From bdce82e960d1205d118662f575cec39379984e34 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 31 Jan 2024 03:26:04 +0100
+Subject: [PATCH] net: mdio: ipq4019: add support for clock-frequency property
+
+The IPQ4019 MDIO internally divide the clock feed by AHB based on the
+MDIO_MODE reg. On reset or power up, the default value for the
+divider is 0xff that reflect the divider set to /256.
+
+This makes the MDC run at a very low rate, that is, considering AHB is
+always fixed to 100Mhz, a value of 390KHz.
+
+This hasn't have been a problem as MDIO wasn't used for time sensitive
+operation, it is now that on IPQ807x is usually mounted with PHY that
+requires MDIO to load their firmware (example Aquantia PHY).
+
+To handle this problem and permit to set the correct designed MDC
+frequency for the SoC add support for the standard "clock-frequency"
+property for the MDIO node.
+
+The divider supports value from /1 to /256 and the common value are to
+set it to /16 to reflect 6.25Mhz or to /8 on newer platform to reflect
+12.5Mhz.
+
+To scan if the requested rate is supported by the divider, loop with
+each supported divider and stop when the requested rate match the final
+rate with the current divider. An error is returned if the rate doesn't
+match any value.
+
+On MDIO reset, the divider is restored to the requested value to prevent
+any kind of downclocking caused by the divider reverting to a default
+value.
+
+To follow 802.3 spec of 2.5MHz of default value, if divider is set at
+/256 and "clock-frequency" is not set in DT, assume nobody set the
+divider and try to find the closest MDC rate to 2.5MHz. (in the case of
+AHB set to 100MHz, it's 1.5625MHz)
+
+While at is also document other bits of the MDIO_MODE reg to have a
+clear idea of what is actually applied there.
+
+Documentation of some BITs is skipped as they are marked as reserved and
+their usage is not clear (RES 11:9 GENPHY 16:13 RES1 19:17)
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Signed-off-by: David S. Miller <davem@davemloft.net>
+---
+ drivers/net/mdio/mdio-ipq4019.c | 109 ++++++++++++++++++++++++++++++--
+ 1 file changed, 103 insertions(+), 6 deletions(-)
+
+--- a/drivers/net/mdio/mdio-ipq4019.c
++++ b/drivers/net/mdio/mdio-ipq4019.c
+@@ -14,6 +14,20 @@
+ #include <linux/clk.h>
+ 
+ #define MDIO_MODE_REG				0x40
++#define   MDIO_MODE_MDC_MODE			BIT(12)
++/* 0 = Clause 22, 1 = Clause 45 */
++#define   MDIO_MODE_C45				BIT(8)
++#define   MDIO_MODE_DIV_MASK			GENMASK(7, 0)
++#define     MDIO_MODE_DIV(x)			FIELD_PREP(MDIO_MODE_DIV_MASK, (x) - 1)
++#define     MDIO_MODE_DIV_1			0x0
++#define     MDIO_MODE_DIV_2			0x1
++#define     MDIO_MODE_DIV_4			0x3
++#define     MDIO_MODE_DIV_8			0x7
++#define     MDIO_MODE_DIV_16			0xf
++#define     MDIO_MODE_DIV_32			0x1f
++#define     MDIO_MODE_DIV_64			0x3f
++#define     MDIO_MODE_DIV_128			0x7f
++#define     MDIO_MODE_DIV_256			0xff
+ #define MDIO_ADDR_REG				0x44
+ #define MDIO_DATA_WRITE_REG			0x48
+ #define MDIO_DATA_READ_REG			0x4c
+@@ -26,9 +40,6 @@
+ #define MDIO_CMD_ACCESS_CODE_C45_WRITE	1
+ #define MDIO_CMD_ACCESS_CODE_C45_READ	2
+ 
+-/* 0 = Clause 22, 1 = Clause 45 */
+-#define MDIO_MODE_C45				BIT(8)
+-
+ #define IPQ4019_MDIO_TIMEOUT	10000
+ #define IPQ4019_MDIO_SLEEP		10
+ 
+@@ -41,6 +52,7 @@ struct ipq4019_mdio_data {
+ 	void __iomem	*membase;
+ 	void __iomem *eth_ldo_rdy;
+ 	struct clk *mdio_clk;
++	unsigned int mdc_rate;
+ };
+ 
+ static int ipq4019_mdio_wait_busy(struct mii_bus *bus)
+@@ -179,6 +191,38 @@ static int ipq4019_mdio_write(struct mii
+ 	return 0;
+ }
+ 
++static int ipq4019_mdio_set_div(struct ipq4019_mdio_data *priv)
++{
++	unsigned long ahb_rate;
++	int div;
++	u32 val;
++
++	/* If we don't have a clock for AHB use the fixed value */
++	ahb_rate = IPQ_MDIO_CLK_RATE;
++	if (priv->mdio_clk)
++		ahb_rate = clk_get_rate(priv->mdio_clk);
++
++	/* MDC rate is ahb_rate/(MDIO_MODE_DIV + 1)
++	 * While supported, internal documentation doesn't
++	 * assure correct functionality of the MDIO bus
++	 * with divider of 1, 2 or 4.
++	 */
++	for (div = 8; div <= 256; div *= 2) {
++		/* The requested rate is supported by the div */
++		if (priv->mdc_rate == DIV_ROUND_UP(ahb_rate, div)) {
++			val = readl(priv->membase + MDIO_MODE_REG);
++			val &= ~MDIO_MODE_DIV_MASK;
++			val |= MDIO_MODE_DIV(div);
++			writel(val, priv->membase + MDIO_MODE_REG);
++
++			return 0;
++		}
++	}
++
++	/* The requested rate is not supported */
++	return -EINVAL;
++}
++
+ static int ipq_mdio_reset(struct mii_bus *bus)
+ {
+ 	struct ipq4019_mdio_data *priv = bus->priv;
+@@ -201,10 +245,58 @@ static int ipq_mdio_reset(struct mii_bus
+ 		return ret;
+ 
+ 	ret = clk_prepare_enable(priv->mdio_clk);
+-	if (ret == 0)
+-		mdelay(10);
++	if (ret)
++		return ret;
++
++	mdelay(10);
+ 
+-	return ret;
++	/* Restore MDC rate */
++	return ipq4019_mdio_set_div(priv);
++}
++
++static void ipq4019_mdio_select_mdc_rate(struct platform_device *pdev,
++					 struct ipq4019_mdio_data *priv)
++{
++	unsigned long ahb_rate;
++	int div;
++	u32 val;
++
++	/* MDC rate defined in DT, we don't have to decide a default value */
++	if (!of_property_read_u32(pdev->dev.of_node, "clock-frequency",
++				  &priv->mdc_rate))
++		return;
++
++	/* If we don't have a clock for AHB use the fixed value */
++	ahb_rate = IPQ_MDIO_CLK_RATE;
++	if (priv->mdio_clk)
++		ahb_rate = clk_get_rate(priv->mdio_clk);
++
++	/* Check what is the current div set */
++	val = readl(priv->membase + MDIO_MODE_REG);
++	div = FIELD_GET(MDIO_MODE_DIV_MASK, val);
++
++	/* div is not set to the default value of /256
++	 * Probably someone changed that (bootloader, other drivers)
++	 * Keep this and don't overwrite it.
++	 */
++	if (div != MDIO_MODE_DIV_256) {
++		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div + 1);
++		return;
++	}
++
++	/* If div is /256 assume nobody have set this value and
++	 * try to find one MDC rate that is close the 802.3 spec of
++	 * 2.5MHz
++	 */
++	for (div = 256; div >= 8; div /= 2) {
++		/* Stop as soon as we found a divider that
++		 * reached the closest value to 2.5MHz
++		 */
++		if (DIV_ROUND_UP(ahb_rate, div) > 2500000)
++			break;
++
++		priv->mdc_rate = DIV_ROUND_UP(ahb_rate, div);
++	}
+ }
+ 
+ static int ipq4019_mdio_probe(struct platform_device *pdev)
+@@ -228,6 +320,11 @@ static int ipq4019_mdio_probe(struct pla
+ 	if (IS_ERR(priv->mdio_clk))
+ 		return PTR_ERR(priv->mdio_clk);
+ 
++	ipq4019_mdio_select_mdc_rate(pdev, priv);
++	ret = ipq4019_mdio_set_div(priv);
++	if (ret)
++		return ret;
++
+ 	/* The platform resource is provided on the chipset IPQ5018 */
+ 	/* This resource is optional */
+ 	res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
diff --git a/target/linux/generic/backport-6.1/721-v6.7-net-phy-aquantia-drop-wrong-endianness-conversion-fo.patch b/target/linux/generic/backport-6.1/721-v6.7-net-phy-aquantia-drop-wrong-endianness-conversion-fo.patch
new file mode 100644
index 00000000000..d32a7edf93c
--- /dev/null
+++ b/target/linux/generic/backport-6.1/721-v6.7-net-phy-aquantia-drop-wrong-endianness-conversion-fo.patch
@@ -0,0 +1,92 @@
+From 7edce370d87a23e8ed46af5b76a9fef1e341b67b Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Tue, 28 Nov 2023 14:59:28 +0100
+Subject: [PATCH] net: phy: aquantia: drop wrong endianness conversion for addr
+ and CRC
+
+On further testing on BE target with kernel test robot, it was notice
+that the endianness conversion for addr and CRC in fw_load_memory was
+wrong.
+
+Drop the cpu_to_le32 conversion for addr load as it's not needed.
+
+Use get_unaligned_le32 instead of get_unaligned for FW data word load to
+correctly convert data in the correct order to follow system endian.
+
+Also drop the cpu_to_be32 for CRC calculation as it's wrong and would
+cause different CRC on BE system.
+The loaded word is swapped internally and MAILBOX calculates the CRC on
+the swapped word. To correctly calculate the CRC to be later matched
+with the one from MAILBOX, use an u8 struct and swap the word there to
+keep the same order on both LE and BE for crc_ccitt_false function.
+Also add additional comments on how the CRC verification for the loaded
+section works.
+
+CRC is calculated as we load the section and verified with the MAILBOX
+only after the entire section is loaded to skip additional slowdown by
+loop the section data again.
+
+Reported-by: kernel test robot <lkp@intel.com>
+Closes: https://lore.kernel.org/oe-kbuild-all/202311210414.sEJZjlcD-lkp@intel.com/
+Fixes: e93984ebc1c8 ("net: phy: aquantia: add firmware load support")
+Tested-by: Robert Marko <robimarko@gmail.com> # ipq8072 LE device
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Link: https://lore.kernel.org/r/20231128135928.9841-1-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/aquantia/aquantia_firmware.c | 24 ++++++++++++--------
+ 1 file changed, 14 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/phy/aquantia/aquantia_firmware.c
++++ b/drivers/net/phy/aquantia/aquantia_firmware.c
+@@ -93,9 +93,6 @@ static int aqr_fw_load_memory(struct phy
+ 	u16 crc = 0, up_crc;
+ 	size_t pos;
+ 
+-	/* PHY expect addr in LE */
+-	addr = (__force u32)cpu_to_le32(addr);
+-
+ 	phy_write_mmd(phydev, MDIO_MMD_VEND1,
+ 		      VEND1_GLOBAL_MAILBOX_INTERFACE1,
+ 		      VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
+@@ -110,10 +107,11 @@ static int aqr_fw_load_memory(struct phy
+ 	 * If a firmware that is not word aligned is found, please report upstream.
+ 	 */
+ 	for (pos = 0; pos < len; pos += sizeof(u32)) {
++		u8 crc_data[4];
+ 		u32 word;
+ 
+ 		/* FW data is always stored in little-endian */
+-		word = get_unaligned((const u32 *)(data + pos));
++		word = get_unaligned_le32((const u32 *)(data + pos));
+ 
+ 		phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
+ 			      VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
+@@ -124,15 +122,21 @@ static int aqr_fw_load_memory(struct phy
+ 			      VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
+ 			      VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
+ 
+-		/* calculate CRC as we load data to the mailbox.
+-		 * We convert word to big-endian as PHY is BE and mailbox will
+-		 * return a BE CRC.
++		/* Word is swapped internally and MAILBOX CRC is calculated
++		 * using big-endian order. Mimic what the PHY does to have a
++		 * matching CRC...
+ 		 */
+-		word = (__force u32)cpu_to_be32(word);
+-		crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
+-	}
++		crc_data[0] = word >> 24;
++		crc_data[1] = word >> 16;
++		crc_data[2] = word >> 8;
++		crc_data[3] = word;
+ 
++		/* ...calculate CRC as we load data... */
++		crc = crc_ccitt_false(crc, crc_data, sizeof(crc_data));
++	}
++	/* ...gets CRC from MAILBOX after we have loaded the entire section... */
+ 	up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
++	/* ...and make sure it does match our calculated CRC */
+ 	if (crc != up_crc) {
+ 		phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
+ 			   crc, up_crc);
diff --git a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
index 55267916242..816aa67787d 100644
--- a/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
+++ b/target/linux/generic/backport-6.1/724-v6.2-net-ethernet-mtk_eth_soc-enable-flow-offloading-supp.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4334,6 +4334,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4333,6 +4333,7 @@ static const struct mtk_soc_data mt7986_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7986_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch b/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
index 95a21e1c9a3..cefe1eefff2 100644
--- a/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
+++ b/target/linux/generic/backport-6.1/729-07-v6.1-net-ethernet-mtk_eth_soc-remove-cpu_relax-in-mtk_pen.patch
@@ -12,7 +12,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3481,11 +3481,8 @@ static void mtk_pending_work(struct work
+@@ -3480,11 +3480,8 @@ static void mtk_pending_work(struct work
  	rtnl_lock();
  
  	dev_dbg(eth->dev, "[%s][%d] reset\n", __func__, __LINE__);
@@ -25,7 +25,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!eth->netdev[i])
-@@ -3519,7 +3516,7 @@ static void mtk_pending_work(struct work
+@@ -3518,7 +3515,7 @@ static void mtk_pending_work(struct work
  
  	dev_dbg(eth->dev, "[%s][%d] reset done\n", __func__, __LINE__);
  
diff --git a/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch b/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
index 8bdbfc29279..c91861a8f11 100644
--- a/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
+++ b/target/linux/generic/backport-6.1/729-18-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_reset-util.patch
@@ -16,7 +16,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3257,6 +3257,27 @@ static void mtk_set_mcr_max_rx(struct mt
+@@ -3256,6 +3256,27 @@ static void mtk_set_mcr_max_rx(struct mt
  		mtk_w32(mac->hw, mcr_new, MTK_MAC_MCR(mac->id));
  }
  
@@ -44,7 +44,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int mtk_hw_init(struct mtk_eth *eth)
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3296,22 +3317,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3295,22 +3316,9 @@ static int mtk_hw_init(struct mtk_eth *e
  		return 0;
  	}
  
diff --git a/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch b/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
index 712b6a2d3af..6597eb5b746 100644
--- a/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
+++ b/target/linux/generic/backport-6.1/729-19-v6.3-net-ethernet-mtk_eth_soc-introduce-mtk_hw_warm_reset.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3278,7 +3278,54 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3277,7 +3277,54 @@ static void mtk_hw_reset(struct mtk_eth
  			     0x3ffffff);
  }
  
@@ -73,7 +73,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
  		       ETHSYS_DMA_AG_MAP_PPE;
-@@ -3317,7 +3364,12 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3316,7 +3363,12 @@ static int mtk_hw_init(struct mtk_eth *e
  		return 0;
  	}
  
@@ -87,7 +87,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		/* Set FE to PDMAv2 if necessary */
-@@ -3508,7 +3560,7 @@ static void mtk_pending_work(struct work
+@@ -3507,7 +3559,7 @@ static void mtk_pending_work(struct work
  	if (eth->dev->pins)
  		pinctrl_select_state(eth->dev->pins->p,
  				     eth->dev->pins->default_state);
@@ -96,7 +96,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* restart DMA and enable IRQs */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -4110,7 +4162,7 @@ static int mtk_probe(struct platform_dev
+@@ -4109,7 +4161,7 @@ static int mtk_probe(struct platform_dev
  	eth->msg_enable = netif_msg_init(mtk_msg_level, MTK_DEFAULT_MSG_ENABLE);
  	INIT_WORK(&eth->pending_work, mtk_pending_work);
  
diff --git a/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch b/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
index 9da16ec56cc..55ab19f4c8d 100644
--- a/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
+++ b/target/linux/generic/backport-6.1/729-20-v6.3-net-ethernet-mtk_eth_soc-align-reset-procedure-to-ve.patch
@@ -16,7 +16,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -2845,14 +2845,29 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2844,14 +2844,29 @@ static void mtk_dma_free(struct mtk_eth
  	kfree(eth->scratch_head);
  }
  
@@ -48,7 +48,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	schedule_work(&eth->pending_work);
  }
  
-@@ -3332,15 +3347,17 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3331,15 +3346,17 @@ static int mtk_hw_init(struct mtk_eth *e
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	int i, val, ret;
  
@@ -72,7 +72,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (eth->ethsys)
  		regmap_update_bits(eth->ethsys, ETHSYS_DMA_AG_MAP, dma_mask,
-@@ -3469,8 +3486,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3468,8 +3485,10 @@ static int mtk_hw_init(struct mtk_eth *e
  	return 0;
  
  err_disable_pm:
@@ -85,7 +85,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return ret;
  }
-@@ -3532,30 +3551,53 @@ static int mtk_do_ioctl(struct net_devic
+@@ -3531,30 +3550,53 @@ static int mtk_do_ioctl(struct net_devic
  	return -EOPNOTSUPP;
  }
  
@@ -148,7 +148,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (eth->dev->pins)
  		pinctrl_select_state(eth->dev->pins->p,
-@@ -3566,15 +3608,19 @@ static void mtk_pending_work(struct work
+@@ -3565,15 +3607,19 @@ static void mtk_pending_work(struct work
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!test_bit(i, &restart))
  			continue;
diff --git a/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch b/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
index 96ebc874814..d5a7c0eba2a 100644
--- a/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
+++ b/target/linux/generic/backport-6.1/729-21-v6.3-net-ethernet-mtk_eth_soc-add-dma-checks-to-mtk_hw_re.patch
@@ -49,7 +49,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  };
  
  /* strings used by ethtool */
-@@ -3340,6 +3346,102 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3339,6 +3345,102 @@ static void mtk_hw_warm_reset(struct mtk
  			val, rst_mask);
  }
  
@@ -152,7 +152,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int mtk_hw_init(struct mtk_eth *eth, bool reset)
  {
  	u32 dma_mask = ETHSYS_DMA_AG_MAP_PDMA | ETHSYS_DMA_AG_MAP_QDMA |
-@@ -3658,6 +3760,7 @@ static int mtk_cleanup(struct mtk_eth *e
+@@ -3657,6 +3759,7 @@ static int mtk_cleanup(struct mtk_eth *e
  	mtk_unreg_dev(eth);
  	mtk_free_dev(eth);
  	cancel_work_sync(&eth->pending_work);
@@ -160,7 +160,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	return 0;
  }
-@@ -4095,6 +4198,7 @@ static int mtk_probe(struct platform_dev
+@@ -4094,6 +4197,7 @@ static int mtk_probe(struct platform_dev
  
  	eth->rx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  	INIT_WORK(&eth->rx_dim.work, mtk_dim_rx);
@@ -168,7 +168,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	eth->tx_dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;
  	INIT_WORK(&eth->tx_dim.work, mtk_dim_tx);
-@@ -4297,6 +4401,8 @@ static int mtk_probe(struct platform_dev
+@@ -4296,6 +4400,8 @@ static int mtk_probe(struct platform_dev
  	netif_napi_add(&eth->dummy_dev, &eth->rx_napi, mtk_napi_rx);
  
  	platform_set_drvdata(pdev, eth);
diff --git a/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch b/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
index da1ce24b8ff..c21d094ae84 100644
--- a/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
+++ b/target/linux/generic/backport-6.1/729-22-v6.3-net-ethernet-mtk_wed-add-reset-reset_complete-callba.patch
@@ -14,7 +14,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3689,6 +3689,11 @@ static void mtk_pending_work(struct work
+@@ -3688,6 +3688,11 @@ static void mtk_pending_work(struct work
  	set_bit(MTK_RESETTING, &eth->state);
  
  	mtk_prepare_for_reset(eth);
@@ -26,7 +26,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	/* stop all devices to make sure that dma is properly shut down */
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
-@@ -3726,6 +3731,8 @@ static void mtk_pending_work(struct work
+@@ -3725,6 +3730,8 @@ static void mtk_pending_work(struct work
  
  	clear_bit(MTK_RESETTING, &eth->state);
  
diff --git a/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch b/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
index c3b8af0b2b7..046a5812247 100644
--- a/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
+++ b/target/linux/generic/backport-6.1/730-02-v6.3-net-ethernet-mtk_eth_soc-increase-tx-ring-side-for-Q.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -945,7 +945,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -944,7 +944,7 @@ static int mtk_init_fq_dma(struct mtk_et
  {
  	const struct mtk_soc_data *soc = eth->soc;
  	dma_addr_t phy_ring_tail;
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	dma_addr_t dma_addr;
  	int i;
  
-@@ -2209,19 +2209,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2208,19 +2208,25 @@ static int mtk_tx_alloc(struct mtk_eth *
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	int i, sz = soc->txrx.txd_size;
  	struct mtk_tx_dma_v2 *txd;
@@ -51,7 +51,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		u32 next_ptr = ring->phys + next * sz;
  
  		txd = ring->dma + i * sz;
-@@ -2241,22 +2247,22 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2240,22 +2246,22 @@ static int mtk_tx_alloc(struct mtk_eth *
  	 * descriptors in ring->dma_pdma.
  	 */
  	if (!MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ring->thresh = MAX_SKB_FRAGS;
  
  	/* make sure that all changes to the dma ring are flushed before we
-@@ -2268,14 +2274,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2267,14 +2273,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  		mtk_w32(eth, ring->phys, soc->reg_map->qdma.ctx_ptr);
  		mtk_w32(eth, ring->phys, soc->reg_map->qdma.dtx_ptr);
  		mtk_w32(eth,
@@ -96,7 +96,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		mtk_w32(eth, 0, MT7628_TX_CTX_IDX0);
  		mtk_w32(eth, MT7628_PST_DTX_IDX0, soc->reg_map->pdma.rst_idx);
  	}
-@@ -2293,7 +2299,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2292,7 +2298,7 @@ static void mtk_tx_clean(struct mtk_eth
  	int i;
  
  	if (ring->buf) {
@@ -105,7 +105,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			mtk_tx_unmap(eth, &ring->buf[i], NULL, false);
  		kfree(ring->buf);
  		ring->buf = NULL;
-@@ -2301,14 +2307,14 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2300,14 +2306,14 @@ static void mtk_tx_clean(struct mtk_eth
  
  	if (ring->dma) {
  		dma_free_coherent(eth->dma_dev,
@@ -122,7 +122,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  				  ring->dma_pdma, ring->phys_pdma);
  		ring->dma_pdma = NULL;
  	}
-@@ -2833,7 +2839,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2832,7 +2838,7 @@ static void mtk_dma_free(struct mtk_eth
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
  		dma_free_coherent(eth->dma_dev,
diff --git a/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch b/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
index bc794a5c8a0..7e879ca1d5a 100644
--- a/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
+++ b/target/linux/generic/backport-6.1/730-03-v6.3-net-ethernet-mtk_eth_soc-avoid-port_mg-assignment-on.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4480,7 +4480,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4479,7 +4479,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -21,7 +21,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	.hash_offset = 2,
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
-@@ -4519,7 +4519,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4518,7 +4518,7 @@ static const struct mtk_soc_data mt7623_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
diff --git a/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch b/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
index 48d9b31fef4..8ceba7831e0 100644
--- a/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
+++ b/target/linux/generic/backport-6.1/730-04-v6.3-net-ethernet-mtk_eth_soc-implement-multi-queue-suppo.patch
@@ -139,7 +139,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* Configure duplex */
  	if (duplex == DUPLEX_FULL)
  		mcr |= MAC_MCR_FORCE_DPX;
-@@ -1106,7 +1181,8 @@ static void mtk_tx_set_dma_desc_v1(struc
+@@ -1105,7 +1180,8 @@ static void mtk_tx_set_dma_desc_v1(struc
  
  	WRITE_ONCE(desc->txd1, info->addr);
  
@@ -149,7 +149,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (info->last)
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
-@@ -1140,9 +1216,6 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1139,9 +1215,6 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -159,7 +159,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	data = (mac->id + 1) << TX_DMA_FPORT_SHIFT_V2; /* forward port */
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
-@@ -1186,11 +1259,12 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1185,11 +1258,12 @@ static int mtk_tx_map(struct sk_buff *sk
  		.gso = gso,
  		.csum = skb->ip_summed == CHECKSUM_PARTIAL,
  		.vlan = skb_vlan_tag_present(skb),
@@ -173,7 +173,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct mtk_mac *mac = netdev_priv(dev);
  	struct mtk_eth *eth = mac->hw;
  	const struct mtk_soc_data *soc = eth->soc;
-@@ -1198,8 +1272,10 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1197,8 +1271,10 @@ static int mtk_tx_map(struct sk_buff *sk
  	struct mtk_tx_dma *itxd_pdma, *txd_pdma;
  	struct mtk_tx_buf *itx_buf, *tx_buf;
  	int i, n_desc = 1;
@@ -184,7 +184,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	itxd = ring->next_free;
  	itxd_pdma = qdma_to_pdma(ring, itxd);
  	if (itxd == ring->last_free)
-@@ -1248,7 +1324,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1247,7 +1323,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  			txd_info.size = min_t(unsigned int, frag_size,
  					      soc->txrx.dma_max_len);
@@ -193,7 +193,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			txd_info.last = i == skb_shinfo(skb)->nr_frags - 1 &&
  					!(frag_size - txd_info.size);
  			txd_info.addr = skb_frag_dma_map(eth->dma_dev, frag,
-@@ -1287,7 +1363,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1286,7 +1362,7 @@ static int mtk_tx_map(struct sk_buff *sk
  			txd_pdma->txd2 |= TX_DMA_LS1;
  	}
  
@@ -202,7 +202,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	skb_tx_timestamp(skb);
  
  	ring->next_free = mtk_qdma_phys_to_virt(ring, txd->txd2);
-@@ -1299,8 +1375,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1298,8 +1374,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	wmb();
  
  	if (MTK_HAS_CAPS(soc->caps, MTK_QDMA)) {
@@ -212,7 +212,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			mtk_w32(eth, txd->txd2, soc->reg_map->qdma.ctx_ptr);
  	} else {
  		int next_idx;
-@@ -1369,7 +1444,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1368,7 +1443,7 @@ static void mtk_wake_queue(struct mtk_et
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
  		if (!eth->netdev[i])
  			continue;
@@ -221,7 +221,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  }
  
-@@ -1393,7 +1468,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1392,7 +1467,7 @@ static netdev_tx_t mtk_start_xmit(struct
  
  	tx_num = mtk_cal_txd_req(eth, skb);
  	if (unlikely(atomic_read(&ring->free_count) <= tx_num)) {
@@ -230,7 +230,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		netif_err(eth, tx_queued, dev,
  			  "Tx Ring full when queue awake!\n");
  		spin_unlock(&eth->page_lock);
-@@ -1419,7 +1494,7 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1418,7 +1493,7 @@ static netdev_tx_t mtk_start_xmit(struct
  		goto drop;
  
  	if (unlikely(atomic_read(&ring->free_count) <= ring->thresh))
@@ -239,7 +239,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	spin_unlock(&eth->page_lock);
  
-@@ -1586,10 +1661,12 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1585,10 +1660,12 @@ static int mtk_xdp_submit_frame(struct m
  	struct skb_shared_info *sinfo = xdp_get_shared_info_from_frame(xdpf);
  	const struct mtk_soc_data *soc = eth->soc;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
@@ -252,7 +252,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	};
  	int err, index = 0, n_desc = 1, nr_frags;
  	struct mtk_tx_buf *htx_buf, *tx_buf;
-@@ -1639,6 +1716,7 @@ static int mtk_xdp_submit_frame(struct m
+@@ -1638,6 +1715,7 @@ static int mtk_xdp_submit_frame(struct m
  		memset(&txd_info, 0, sizeof(struct mtk_tx_dma_desc_info));
  		txd_info.size = skb_frag_size(&sinfo->frags[index]);
  		txd_info.last = index + 1 == nr_frags;
@@ -260,7 +260,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		data = skb_frag_address(&sinfo->frags[index]);
  
  		index++;
-@@ -1993,8 +2071,46 @@ rx_done:
+@@ -1992,8 +2070,46 @@ rx_done:
  	return done;
  }
  
@@ -308,7 +308,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	struct mtk_tx_ring *ring = &eth->tx_ring;
-@@ -2026,12 +2142,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2025,12 +2141,9 @@ static int mtk_poll_tx_qdma(struct mtk_e
  			break;
  
  		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
@@ -323,7 +323,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			budget--;
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2050,7 +2163,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2049,7 +2162,7 @@ static int mtk_poll_tx_qdma(struct mtk_e
  }
  
  static int mtk_poll_tx_pdma(struct mtk_eth *eth, int budget,
@@ -332,7 +332,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  {
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct mtk_tx_buf *tx_buf;
-@@ -2068,12 +2181,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
+@@ -2067,12 +2180,8 @@ static int mtk_poll_tx_pdma(struct mtk_e
  			break;
  
  		if (tx_buf->data != (void *)MTK_DMA_DUMMY_DESC) {
@@ -347,7 +347,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			budget--;
  		}
  		mtk_tx_unmap(eth, tx_buf, &bq, true);
-@@ -2095,26 +2204,15 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2094,26 +2203,15 @@ static int mtk_poll_tx(struct mtk_eth *e
  {
  	struct mtk_tx_ring *ring = &eth->tx_ring;
  	struct dim_sample dim_sample = {};
@@ -379,7 +379,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	dim_update_sample(eth->tx_events, eth->tx_packets, eth->tx_bytes,
  			  &dim_sample);
-@@ -2124,7 +2222,7 @@ static int mtk_poll_tx(struct mtk_eth *e
+@@ -2123,7 +2221,7 @@ static int mtk_poll_tx(struct mtk_eth *e
  	    (atomic_read(&ring->free_count) > ring->thresh))
  		mtk_wake_queue(eth);
  
@@ -388,7 +388,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static void mtk_handle_status_irq(struct mtk_eth *eth)
-@@ -2210,6 +2308,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2209,6 +2307,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  	int i, sz = soc->txrx.txd_size;
  	struct mtk_tx_dma_v2 *txd;
  	int ring_size;
@@ -396,7 +396,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (MTK_HAS_CAPS(soc->caps, MTK_QDMA))
  		ring_size = MTK_QDMA_RING_SIZE;
-@@ -2277,8 +2376,25 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2276,8 +2375,25 @@ static int mtk_tx_alloc(struct mtk_eth *
  			ring->phys + ((ring_size - 1) * sz),
  			soc->reg_map->qdma.crx_ptr);
  		mtk_w32(eth, ring->last_free_ptr, soc->reg_map->qdma.drx_ptr);
@@ -424,7 +424,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	} else {
  		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
  		mtk_w32(eth, ring_size, MT7628_TX_MAX_CNT0);
-@@ -2963,7 +3079,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -2962,7 +3078,7 @@ static int mtk_start_dma(struct mtk_eth
  		if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2))
  			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
  			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
@@ -433,7 +433,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		else
  			val |= MTK_RX_BT_32DWORDS;
  		mtk_w32(eth, val, reg_map->qdma.glo_cfg);
-@@ -3009,6 +3125,45 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3008,6 +3124,45 @@ static void mtk_gdm_config(struct mtk_et
  	mtk_w32(eth, 0, MTK_RST_GL);
  }
  
@@ -479,7 +479,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int mtk_open(struct net_device *dev)
  {
  	struct mtk_mac *mac = netdev_priv(dev);
-@@ -3051,7 +3206,8 @@ static int mtk_open(struct net_device *d
+@@ -3050,7 +3205,8 @@ static int mtk_open(struct net_device *d
  		refcount_inc(&eth->dma_refcnt);
  
  	phylink_start(mac->phylink);
@@ -489,7 +489,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3760,8 +3916,12 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3759,8 +3915,12 @@ static int mtk_unreg_dev(struct mtk_eth
  	int i;
  
  	for (i = 0; i < MTK_MAC_COUNT; i++) {
@@ -502,7 +502,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		unregister_netdev(eth->netdev[i]);
  	}
  
-@@ -3978,6 +4138,23 @@ static int mtk_set_rxnfc(struct net_devi
+@@ -3977,6 +4137,23 @@ static int mtk_set_rxnfc(struct net_devi
  	return ret;
  }
  
@@ -526,7 +526,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static const struct ethtool_ops mtk_ethtool_ops = {
  	.get_link_ksettings	= mtk_get_link_ksettings,
  	.set_link_ksettings	= mtk_set_link_ksettings,
-@@ -4012,6 +4189,7 @@ static const struct net_device_ops mtk_n
+@@ -4011,6 +4188,7 @@ static const struct net_device_ops mtk_n
  	.ndo_setup_tc		= mtk_eth_setup_tc,
  	.ndo_bpf		= mtk_xdp,
  	.ndo_xdp_xmit		= mtk_xdp_xmit,
@@ -534,7 +534,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  };
  
  static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
-@@ -4021,6 +4199,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4020,6 +4198,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	struct phylink *phylink;
  	struct mtk_mac *mac;
  	int id, err;
@@ -542,7 +542,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	if (!_id) {
  		dev_err(eth->dev, "missing mac id\n");
-@@ -4038,7 +4217,10 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4037,7 +4216,10 @@ static int mtk_add_mac(struct mtk_eth *e
  		return -EINVAL;
  	}
  
@@ -554,7 +554,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (!eth->netdev[id]) {
  		dev_err(eth->dev, "alloc_etherdev failed\n");
  		return -ENOMEM;
-@@ -4146,6 +4328,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4145,6 +4327,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	else
  		eth->netdev[id]->max_mtu = MTK_MAX_RX_LENGTH_2K - MTK_RX_ETH_HLEN;
  
diff --git a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
index b45a33c4cb5..b8e3452f300 100644
--- a/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
+++ b/target/linux/generic/backport-6.1/730-09-v6.3-net-ethernet-mtk_eth_soc-fix-VLAN-rx-hardware-accele.patch
@@ -22,7 +22,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  #include "mtk_eth_soc.h"
  #include "mtk_wed.h"
-@@ -2022,16 +2023,22 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2021,16 +2022,22 @@ static int mtk_poll_rx(struct napi_struc
  						htons(RX_DMA_VPID(trxd.rxd4)),
  						RX_DMA_VID(trxd.rxd4));
  			} else if (trxd.rxd2 & RX_DMA_VTAG) {
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		}
  
  		skb_record_rx_queue(skb, 0);
-@@ -2859,15 +2866,30 @@ static netdev_features_t mtk_fix_feature
+@@ -2858,15 +2865,30 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -88,7 +88,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  /* wait for DMA to finish whatever it is doing before we start using it again */
-@@ -3164,11 +3186,45 @@ found:
+@@ -3163,11 +3185,45 @@ found:
  	return NOTIFY_DONE;
  }
  
@@ -135,7 +135,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
-@@ -3689,6 +3745,10 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3688,6 +3744,10 @@ static int mtk_hw_init(struct mtk_eth *e
  	 */
  	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
  	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
@@ -146,7 +146,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* Enable RX VLan Offloading */
  	mtk_w32(eth, 1, MTK_CDMP_EG_CTRL);
-@@ -3908,6 +3968,12 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3907,6 +3967,12 @@ static int mtk_free_dev(struct mtk_eth *
  		free_netdev(eth->netdev[i]);
  	}
  
diff --git a/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch b/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
index 42c745d02fa..a88df2b8e3a 100644
--- a/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
+++ b/target/linux/generic/backport-6.1/730-12-v6.3-net-ethernet-mtk_eth_soc-disable-hardware-DSA-untagg.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3202,7 +3202,8 @@ static int mtk_open(struct net_device *d
+@@ -3201,7 +3201,8 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
  			struct metadata_dst *md_dst = eth->dsa_meta[i];
  
-@@ -3219,7 +3220,8 @@ static int mtk_open(struct net_device *d
+@@ -3218,7 +3219,8 @@ static int mtk_open(struct net_device *d
  		}
  	} else {
  		/* Hardware special tag parsing needs to be disabled if at least
diff --git a/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch b/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
index 39874c9d1c0..8da728b9e9d 100644
--- a/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
+++ b/target/linux/generic/backport-6.1/730-13-v6.3-net-ethernet-mtk_eth_soc-enable-special-tag-when-any.patch
@@ -23,7 +23,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3137,7 +3137,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3136,7 +3136,7 @@ static void mtk_gdm_config(struct mtk_et
  
  		val |= config;
  
@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			val |= MTK_GDMA_SPECIAL_TAG;
  
  		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3202,8 +3202,7 @@ static int mtk_open(struct net_device *d
+@@ -3201,8 +3201,7 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -42,7 +42,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		for (i = 0; i < ARRAY_SIZE(eth->dsa_meta); i++) {
  			struct metadata_dst *md_dst = eth->dsa_meta[i];
  
-@@ -3220,8 +3219,7 @@ static int mtk_open(struct net_device *d
+@@ -3219,8 +3218,7 @@ static int mtk_open(struct net_device *d
  		}
  	} else {
  		/* Hardware special tag parsing needs to be disabled if at least
diff --git a/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch b/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
index a9879ebfa9d..51cd572ab24 100644
--- a/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
+++ b/target/linux/generic/backport-6.1/730-14-v6.3-net-ethernet-mtk_eth_soc-fix-DSA-TX-tag-hwaccel-for-.patch
@@ -77,7 +77,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1878,7 +1878,9 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1877,7 +1877,9 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -87,7 +87,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -2018,27 +2020,29 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2017,27 +2019,29 @@ static int mtk_poll_rx(struct napi_struc
  
  		if (netdev->features & NETIF_F_HW_VLAN_CTAG_RX) {
  			if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
diff --git a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
index 089f25545d6..a1247218b09 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-18-net-ethernet-mtk_eth_soc-add-support-for-MT7981.patch
@@ -57,7 +57,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		mtk_eth_path_name(path), __func__, updated);
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4804,6 +4804,26 @@ static const struct mtk_soc_data mt7629_
+@@ -4803,6 +4803,26 @@ static const struct mtk_soc_data mt7629_
  	},
  };
  
@@ -84,7 +84,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static const struct mtk_soc_data mt7986_data = {
  	.reg_map = &mt7986_reg_map,
  	.ana_rgc3 = 0x128,
-@@ -4846,6 +4866,7 @@ const struct of_device_id of_mtk_match[]
+@@ -4845,6 +4865,7 @@ const struct of_device_id of_mtk_match[]
  	{ .compatible = "mediatek,mt7622-eth", .data = &mt7622_data},
  	{ .compatible = "mediatek,mt7623-eth", .data = &mt7623_data},
  	{ .compatible = "mediatek,mt7629-eth", .data = &mt7629_data},
diff --git a/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch b/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
index ea20bd87f73..1cb1f405385 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-19-net-ethernet-mtk_eth_soc-set-MDIO-bus-clock-frequenc.patch
@@ -21,7 +21,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -745,8 +745,10 @@ static const struct phylink_mac_ops mtk_
+@@ -744,8 +744,10 @@ static const struct phylink_mac_ops mtk_
  
  static int mtk_mdio_init(struct mtk_eth *eth)
  {
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	mii_np = of_get_child_by_name(eth->dev->of_node, "mdio-bus");
  	if (!mii_np) {
-@@ -773,6 +775,25 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -772,6 +774,25 @@ static int mtk_mdio_init(struct mtk_eth
  	eth->mii_bus->parent = eth->dev;
  
  	snprintf(eth->mii_bus->id, MII_BUS_ID_SIZE, "%pOFn", mii_np);
diff --git a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
index 15295959c11..110944658de 100644
--- a/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
+++ b/target/linux/generic/backport-6.1/733-v6.3-20-net-ethernet-mtk_eth_soc-switch-to-external-PCS-driv.patch
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	return NULL;
-@@ -4017,8 +4018,17 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -4016,8 +4017,17 @@ static int mtk_unreg_dev(struct mtk_eth
  	return 0;
  }
  
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	mtk_unreg_dev(eth);
  	mtk_free_dev(eth);
  	cancel_work_sync(&eth->pending_work);
-@@ -4458,6 +4468,36 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4457,6 +4467,36 @@ void mtk_eth_set_dma_device(struct mtk_e
  	rtnl_unlock();
  }
  
@@ -115,7 +115,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static int mtk_probe(struct platform_device *pdev)
  {
  	struct resource *res = NULL;
-@@ -4521,13 +4561,7 @@ static int mtk_probe(struct platform_dev
+@@ -4520,13 +4560,7 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
@@ -130,7 +130,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (err)
  			return err;
-@@ -4538,14 +4572,17 @@ static int mtk_probe(struct platform_dev
+@@ -4537,14 +4571,17 @@ static int mtk_probe(struct platform_dev
  							    "mediatek,pctl");
  		if (IS_ERR(eth->pctl)) {
  			dev_err(&pdev->dev, "no pctl regmap found\n");
@@ -151,7 +151,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	if (eth->soc->offload_version) {
-@@ -4704,6 +4741,8 @@ err_deinit_hw:
+@@ -4703,6 +4740,8 @@ err_deinit_hw:
  	mtk_hw_deinit(eth);
  err_wed_exit:
  	mtk_wed_exit();
diff --git a/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
index df8d6427943..93eaffa19e7 100644
--- a/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
+++ b/target/linux/generic/backport-6.1/733-v6.4-23-net-ethernet-mtk_eth_soc-ppe-add-support-for-flow-ac.patch
@@ -27,7 +27,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4692,8 +4692,8 @@ static int mtk_probe(struct platform_dev
+@@ -4691,8 +4691,8 @@ static int mtk_probe(struct platform_dev
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			if (!eth->ppe[i]) {
  				err = -ENOMEM;
  				goto err_deinit_ppe;
-@@ -4817,6 +4817,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4816,6 +4816,7 @@ static const struct mtk_soc_data mt7622_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 2,
@@ -46,7 +46,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.foe_entry_size = sizeof(struct mtk_foe_entry) - 16,
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
-@@ -4854,6 +4855,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4853,6 +4854,7 @@ static const struct mtk_soc_data mt7629_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
@@ -54,7 +54,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4874,6 +4876,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4873,6 +4875,7 @@ static const struct mtk_soc_data mt7981_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4894,6 +4897,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4893,6 +4896,7 @@ static const struct mtk_soc_data mt7986_
  	.offload_version = 2,
  	.hash_offset = 4,
  	.foe_entry_size = sizeof(struct mtk_foe_entry),
diff --git a/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
index d6309964c38..217e517c3af 100644
--- a/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
+++ b/target/linux/generic/backport-6.1/733-v6.4-25-net-ethernet-mtk_eth_soc-drop-generic-vlan-rx-offloa.patch
@@ -17,7 +17,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1898,9 +1898,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1897,9 +1897,7 @@ static int mtk_poll_rx(struct napi_struc
  
  	while (done < budget) {
  		unsigned int pktlen, *rxdcsum;
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		dma_addr_t dma_addr;
  		u32 hash, reason;
  		int mac = 0;
-@@ -2035,36 +2033,21 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2034,36 +2032,21 @@ static int mtk_poll_rx(struct napi_struc
  			skb_checksum_none_assert(skb);
  		skb->protocol = eth_type_trans(skb, netdev);
  
@@ -70,7 +70,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		skb_record_rx_queue(skb, 0);
  		napi_gro_receive(napi, skb);
  
-@@ -2890,29 +2873,11 @@ static netdev_features_t mtk_fix_feature
+@@ -2889,29 +2872,11 @@ static netdev_features_t mtk_fix_feature
  
  static int mtk_set_features(struct net_device *dev, netdev_features_t features)
  {
@@ -100,7 +100,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3226,30 +3191,6 @@ static int mtk_open(struct net_device *d
+@@ -3225,30 +3190,6 @@ static int mtk_open(struct net_device *d
  	struct mtk_eth *eth = mac->hw;
  	int i, err;
  
@@ -131,7 +131,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
  	if (err) {
  		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
-@@ -3288,6 +3229,35 @@ static int mtk_open(struct net_device *d
+@@ -3287,6 +3228,35 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	return 0;
  }
  
-@@ -3772,10 +3742,9 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3771,10 +3741,9 @@ static int mtk_hw_init(struct mtk_eth *e
  	if (!MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
@@ -180,7 +180,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  	/* set interrupt delays based on current Net DIM sample */
  	mtk_dim_rx(&eth->rx_dim.work);
-@@ -4415,7 +4384,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4414,7 +4383,7 @@ static int mtk_add_mac(struct mtk_eth *e
  		eth->netdev[id]->hw_features |= NETIF_F_LRO;
  
  	eth->netdev[id]->vlan_features = eth->soc->hw_features &
diff --git a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
index a0b9b6a299b..d7d1c08fce0 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-01-net-ethernet-mtk_ppe-add-MTK_FOE_ENTRY_V-1-2-_SIZE-m.patch
@@ -17,7 +17,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4766,7 +4766,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4765,7 +4765,7 @@ static const struct mtk_soc_data mt7621_
  	.required_pctl = false,
  	.offload_version = 1,
  	.hash_offset = 2,
@@ -26,7 +26,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4787,7 +4787,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4786,7 +4786,7 @@ static const struct mtk_soc_data mt7622_
  	.offload_version = 2,
  	.hash_offset = 2,
  	.has_accounting = true,
@@ -35,7 +35,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4806,7 +4806,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4805,7 +4805,7 @@ static const struct mtk_soc_data mt7623_
  	.required_pctl = true,
  	.offload_version = 1,
  	.hash_offset = 2,
@@ -44,7 +44,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4844,8 +4844,8 @@ static const struct mtk_soc_data mt7981_
+@@ -4843,8 +4843,8 @@ static const struct mtk_soc_data mt7981_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 4,
@@ -54,7 +54,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma_v2),
  		.rxd_size = sizeof(struct mtk_rx_dma_v2),
-@@ -4865,8 +4865,8 @@ static const struct mtk_soc_data mt7986_
+@@ -4864,8 +4864,8 @@ static const struct mtk_soc_data mt7986_
  	.required_pctl = false,
  	.offload_version = 2,
  	.hash_offset = 4,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
index 8914e8da96d..fb54f404b21 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-02-net-ethernet-mtk_eth_soc-remove-incorrect-PLL-config.patch
@@ -95,7 +95,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  				/* mt7623_pad_clk_setup */
  				for (i = 0 ; i < NUM_TRGMII_CTRL; i++)
-@@ -4343,13 +4315,19 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4342,13 +4314,19 @@ static int mtk_add_mac(struct mtk_eth *e
  	mac->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE |
  		MAC_10 | MAC_100 | MAC_1000 | MAC_2500FD;
  
@@ -121,7 +121,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  
  	if (MTK_HAS_CAPS(mac->hw->soc->caps, MTK_TRGMII) && !mac->id)
  		__set_bit(PHY_INTERFACE_MODE_TRGMII,
-@@ -4807,6 +4785,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4806,6 +4784,7 @@ static const struct mtk_soc_data mt7623_
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
index 351568f187c..293066fa9a0 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-03-net-ethernet-mtk_eth_soc-remove-mac_pcs_get_state-an.patch
@@ -62,15 +62,15 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static void mtk_mac_link_down(struct phylink_config *config, unsigned int mode,
  			      phy_interface_t interface)
  {
-@@ -709,7 +677,6 @@ static void mtk_mac_link_up(struct phyli
+@@ -708,7 +676,6 @@ static void mtk_mac_link_up(struct phyli
+ 
  static const struct phylink_mac_ops mtk_phylink_ops = {
- 	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
 -	.mac_pcs_get_state = mtk_mac_pcs_get_state,
  	.mac_config = mtk_mac_config,
  	.mac_finish = mtk_mac_finish,
  	.mac_link_down = mtk_mac_link_down,
-@@ -4310,8 +4277,6 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4309,8 +4276,6 @@ static int mtk_add_mac(struct mtk_eth *e
  
  	mac->phylink_config.dev = &eth->netdev[id]->dev;
  	mac->phylink_config.type = PHYLINK_NETDEV;
diff --git a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
index f4795223394..25c87b0415e 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-05-net-ethernet-mtk_eth_soc-add-version-in-mtk_soc_data.patch
@@ -32,7 +32,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		val |= MTK_QTX_SCH_LEAKY_BUCKET_EN;
  
  	if (IS_ENABLED(CONFIG_SOC_MT7621)) {
-@@ -956,7 +956,7 @@ static bool mtk_rx_get_desc(struct mtk_e
+@@ -955,7 +955,7 @@ static bool mtk_rx_get_desc(struct mtk_e
  	rxd->rxd1 = READ_ONCE(dma_rxd->rxd1);
  	rxd->rxd3 = READ_ONCE(dma_rxd->rxd3);
  	rxd->rxd4 = READ_ONCE(dma_rxd->rxd4);
@@ -41,7 +41,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rxd->rxd5 = READ_ONCE(dma_rxd->rxd5);
  		rxd->rxd6 = READ_ONCE(dma_rxd->rxd6);
  	}
-@@ -1014,7 +1014,7 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1013,7 +1013,7 @@ static int mtk_init_fq_dma(struct mtk_et
  
  		txd->txd3 = TX_DMA_PLEN0(MTK_QDMA_PAGE_SIZE);
  		txd->txd4 = 0;
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			txd->txd5 = 0;
  			txd->txd6 = 0;
  			txd->txd7 = 0;
-@@ -1205,7 +1205,7 @@ static void mtk_tx_set_dma_desc(struct n
+@@ -1204,7 +1204,7 @@ static void mtk_tx_set_dma_desc(struct n
  	struct mtk_mac *mac = netdev_priv(dev);
  	struct mtk_eth *eth = mac->hw;
  
@@ -59,7 +59,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		mtk_tx_set_dma_desc_v2(dev, txd, info);
  	else
  		mtk_tx_set_dma_desc_v1(dev, txd, info);
-@@ -1512,7 +1512,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1511,7 +1511,7 @@ static void mtk_update_rx_cpu_idx(struct
  
  static bool mtk_page_pool_enabled(struct mtk_eth *eth)
  {
@@ -68,7 +68,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  }
  
  static struct page_pool *mtk_create_page_pool(struct mtk_eth *eth,
-@@ -1854,7 +1854,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1853,7 +1853,7 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -77,7 +77,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			mac = RX_DMA_GET_SPORT_V2(trxd.rxd5) - 1;
  		else if (!MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628) &&
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
-@@ -1950,7 +1950,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1949,7 +1949,7 @@ static int mtk_poll_rx(struct napi_struc
  		skb->dev = netdev;
  		bytes += skb->len;
  
@@ -86,7 +86,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			reason = FIELD_GET(MTK_RXD5_PPE_CPU_REASON, trxd.rxd5);
  			hash = trxd.rxd5 & MTK_RXD5_FOE_ENTRY;
  			if (hash != MTK_RXD5_FOE_ENTRY)
-@@ -1975,8 +1975,8 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1974,8 +1974,8 @@ static int mtk_poll_rx(struct napi_struc
  		/* When using VLAN untagging in combination with DSA, the
  		 * hardware treats the MTK special tag as a VLAN and untags it.
  		 */
@@ -97,7 +97,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			unsigned int port = RX_DMA_VPID(trxd.rxd3) & GENMASK(2, 0);
  
  			if (port < ARRAY_SIZE(eth->dsa_meta) &&
-@@ -2286,7 +2286,7 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2285,7 +2285,7 @@ static int mtk_tx_alloc(struct mtk_eth *
  		txd->txd2 = next_ptr;
  		txd->txd3 = TX_DMA_LS0 | TX_DMA_OWNER_CPU;
  		txd->txd4 = 0;
@@ -106,7 +106,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			txd->txd5 = 0;
  			txd->txd6 = 0;
  			txd->txd7 = 0;
-@@ -2339,14 +2339,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2338,14 +2338,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_MAN, 1) |
  			      FIELD_PREP(MTK_QTX_SCH_MIN_RATE_EXP, 4) |
  			      MTK_QTX_SCH_LEAKY_BUCKET_SIZE;
@@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			mtk_w32(eth, val, soc->reg_map->qdma.tx_sch_rate + 4);
  	} else {
  		mtk_w32(eth, ring->phys_pdma, MT7628_TX_BASE_PTR0);
-@@ -2475,7 +2475,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2474,7 +2474,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
@@ -132,7 +132,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			rxd->rxd5 = 0;
  			rxd->rxd6 = 0;
  			rxd->rxd7 = 0;
-@@ -3026,7 +3026,7 @@ static int mtk_start_dma(struct mtk_eth
+@@ -3025,7 +3025,7 @@ static int mtk_start_dma(struct mtk_eth
  		       MTK_TX_BT_32DWORDS | MTK_NDP_CO_PRO |
  		       MTK_RX_2B_OFFSET | MTK_TX_WB_DDONE;
  
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			val |= MTK_MUTLI_CNT | MTK_RESV_BUF |
  			       MTK_WCOMP_EN | MTK_DMAD_WR_WDONE |
  			       MTK_CHK_DDONE_EN | MTK_LEAKY_BUCKET_EN;
-@@ -3168,7 +3168,7 @@ static int mtk_open(struct net_device *d
+@@ -3167,7 +3167,7 @@ static int mtk_open(struct net_device *d
  	phylink_start(mac->phylink);
  	netif_tx_start_all_queues(dev);
  
@@ -150,7 +150,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		return 0;
  
  	if (mtk_uses_dsa(dev) && !eth->prog) {
-@@ -3433,7 +3433,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3432,7 +3432,7 @@ static void mtk_hw_reset(struct mtk_eth
  {
  	u32 val;
  
@@ -159,7 +159,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN, 0);
  		val = RSTCTRL_PPE0_V2;
  	} else {
-@@ -3445,7 +3445,7 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3444,7 +3444,7 @@ static void mtk_hw_reset(struct mtk_eth
  
  	ethsys_reset(eth, RSTCTRL_ETH | RSTCTRL_FE | val);
  
@@ -168,7 +168,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  			     0x3ffffff);
  }
-@@ -3471,7 +3471,7 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3470,7 +3470,7 @@ static void mtk_hw_warm_reset(struct mtk
  		return;
  	}
  
@@ -177,7 +177,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0_V2;
  	else
  		rst_mask = RSTCTRL_ETH | RSTCTRL_PPE0;
-@@ -3641,7 +3641,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3640,7 +3640,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	else
  		mtk_hw_reset(eth);
  
@@ -186,7 +186,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* Set FE to PDMAv2 if necessary */
  		val = mtk_r32(eth, MTK_FE_GLO_MISC);
  		mtk_w32(eth,  val | BIT(4), MTK_FE_GLO_MISC);
-@@ -3678,7 +3678,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3677,7 +3677,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	 */
  	val = mtk_r32(eth, MTK_CDMQ_IG_CTRL);
  	mtk_w32(eth, val | MTK_CDMQ_STAG_EN, MTK_CDMQ_IG_CTRL);
@@ -195,7 +195,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		val = mtk_r32(eth, MTK_CDMP_IG_CTRL);
  		mtk_w32(eth, val | MTK_CDMP_STAG_EN, MTK_CDMP_IG_CTRL);
  
-@@ -3700,7 +3700,7 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3699,7 +3699,7 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
@@ -204,7 +204,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4489,7 +4489,7 @@ static int mtk_probe(struct platform_dev
+@@ -4488,7 +4488,7 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
@@ -213,7 +213,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  		if (!res) {
  			err = -EINVAL;
-@@ -4597,9 +4597,8 @@ static int mtk_probe(struct platform_dev
+@@ -4596,9 +4596,8 @@ static int mtk_probe(struct platform_dev
  	}
  
  	if (eth->soc->offload_version) {
@@ -224,7 +224,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		num_ppe = min_t(u32, ARRAY_SIZE(eth->ppe), num_ppe);
  		for (i = 0; i < num_ppe; i++) {
  			u32 ppe_addr = eth->soc->reg_map->ppe_base + i * 0x400;
-@@ -4691,6 +4690,7 @@ static const struct mtk_soc_data mt2701_
+@@ -4690,6 +4689,7 @@ static const struct mtk_soc_data mt2701_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
@@ -232,7 +232,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4707,6 +4707,7 @@ static const struct mtk_soc_data mt7621_
+@@ -4706,6 +4706,7 @@ static const struct mtk_soc_data mt7621_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7621_CLKS_BITMAP,
  	.required_pctl = false,
@@ -240,7 +240,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4727,6 +4728,7 @@ static const struct mtk_soc_data mt7622_
+@@ -4726,6 +4727,7 @@ static const struct mtk_soc_data mt7622_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7622_CLKS_BITMAP,
  	.required_pctl = false,
@@ -248,7 +248,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 2,
  	.has_accounting = true,
-@@ -4747,6 +4749,7 @@ static const struct mtk_soc_data mt7623_
+@@ -4746,6 +4748,7 @@ static const struct mtk_soc_data mt7623_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7623_CLKS_BITMAP,
  	.required_pctl = true,
@@ -256,7 +256,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 1,
  	.hash_offset = 2,
  	.foe_entry_size = MTK_FOE_ENTRY_V1_SIZE,
-@@ -4769,6 +4772,7 @@ static const struct mtk_soc_data mt7629_
+@@ -4768,6 +4771,7 @@ static const struct mtk_soc_data mt7629_
  	.required_clks = MT7629_CLKS_BITMAP,
  	.required_pctl = false,
  	.has_accounting = true,
@@ -264,7 +264,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.txrx = {
  		.txd_size = sizeof(struct mtk_tx_dma),
  		.rxd_size = sizeof(struct mtk_rx_dma),
-@@ -4786,6 +4790,7 @@ static const struct mtk_soc_data mt7981_
+@@ -4785,6 +4789,7 @@ static const struct mtk_soc_data mt7981_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7981_CLKS_BITMAP,
  	.required_pctl = false,
@@ -272,7 +272,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 4,
  	.has_accounting = true,
-@@ -4807,6 +4812,7 @@ static const struct mtk_soc_data mt7986_
+@@ -4806,6 +4811,7 @@ static const struct mtk_soc_data mt7986_
  	.hw_features = MTK_HW_FEATURES,
  	.required_clks = MT7986_CLKS_BITMAP,
  	.required_pctl = false,
@@ -280,7 +280,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	.offload_version = 2,
  	.hash_offset = 4,
  	.has_accounting = true,
-@@ -4827,6 +4833,7 @@ static const struct mtk_soc_data rt5350_
+@@ -4826,6 +4832,7 @@ static const struct mtk_soc_data rt5350_
  	.hw_features = MTK_HW_FEATURES_MT7628,
  	.required_clks = MT7628_CLKS_BITMAP,
  	.required_pctl = false,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
index 5ac9d61ab42..80716583134 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-07-net-ethernet-mtk_eth_soc-rely-on-MTK_MAX_DEVS-and-re.patch
@@ -17,7 +17,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -882,7 +882,7 @@ static void mtk_stats_update(struct mtk_
+@@ -881,7 +881,7 @@ static void mtk_stats_update(struct mtk_
  {
  	int i;
  
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->mac[i] || !eth->mac[i]->hw_stats)
  			continue;
  		if (spin_trylock(&eth->mac[i]->hw_stats->stats_lock)) {
-@@ -1387,7 +1387,7 @@ static int mtk_queue_stopped(struct mtk_
+@@ -1386,7 +1386,7 @@ static int mtk_queue_stopped(struct mtk_
  {
  	int i;
  
@@ -35,7 +35,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		if (netif_queue_stopped(eth->netdev[i]))
-@@ -1401,7 +1401,7 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1400,7 +1400,7 @@ static void mtk_wake_queue(struct mtk_et
  {
  	int i;
  
@@ -44,7 +44,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		netif_tx_wake_all_queues(eth->netdev[i]);
-@@ -1860,7 +1860,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1859,7 +1859,7 @@ static int mtk_poll_rx(struct napi_struc
  			 !(trxd.rxd4 & RX_DMA_SPECIAL_TAG))
  			mac = RX_DMA_GET_SPORT(trxd.rxd4) - 1;
  
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			     !eth->netdev[mac]))
  			goto release_desc;
  
-@@ -2900,7 +2900,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -2899,7 +2899,7 @@ static void mtk_dma_free(struct mtk_eth
  	const struct mtk_soc_data *soc = eth->soc;
  	int i;
  
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
  	if (eth->scratch_ring) {
-@@ -3054,8 +3054,13 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3053,8 +3053,13 @@ static void mtk_gdm_config(struct mtk_et
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		return;
  
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		/* default setup the forward port to send frame to PDMA */
  		val &= ~0xffff;
-@@ -3065,7 +3070,7 @@ static void mtk_gdm_config(struct mtk_et
+@@ -3064,7 +3069,7 @@ static void mtk_gdm_config(struct mtk_et
  
  		val |= config;
  
@@ -87,7 +87,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			val |= MTK_GDMA_SPECIAL_TAG;
  
  		mtk_w32(eth, val, MTK_GDMA_FWD_CFG(i));
-@@ -3662,15 +3667,15 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3661,15 +3666,15 @@ static int mtk_hw_init(struct mtk_eth *e
  	 * up with the more appropriate value when mtk_mac_config call is being
  	 * invoked.
  	 */
@@ -109,7 +109,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	/* Indicates CDM to parse the MTK special tag from CPU
-@@ -3850,7 +3855,7 @@ static void mtk_pending_work(struct work
+@@ -3849,7 +3854,7 @@ static void mtk_pending_work(struct work
  	mtk_prepare_for_reset(eth);
  
  	/* stop all devices to make sure that dma is properly shut down */
@@ -118,7 +118,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i] || !netif_running(eth->netdev[i]))
  			continue;
  
-@@ -3866,8 +3871,8 @@ static void mtk_pending_work(struct work
+@@ -3865,8 +3870,8 @@ static void mtk_pending_work(struct work
  	mtk_hw_init(eth, true);
  
  	/* restart DMA and enable IRQs */
@@ -129,7 +129,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  			continue;
  
  		if (mtk_open(eth->netdev[i])) {
-@@ -3894,7 +3899,7 @@ static int mtk_free_dev(struct mtk_eth *
+@@ -3893,7 +3898,7 @@ static int mtk_free_dev(struct mtk_eth *
  {
  	int i;
  
@@ -138,7 +138,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		if (!eth->netdev[i])
  			continue;
  		free_netdev(eth->netdev[i]);
-@@ -3913,7 +3918,7 @@ static int mtk_unreg_dev(struct mtk_eth
+@@ -3912,7 +3917,7 @@ static int mtk_unreg_dev(struct mtk_eth
  {
  	int i;
  
@@ -147,7 +147,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		struct mtk_mac *mac;
  		if (!eth->netdev[i])
  			continue;
-@@ -4214,7 +4219,7 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4213,7 +4218,7 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  
  	id = be32_to_cpup(_id);
@@ -156,7 +156,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev_err(eth->dev, "%d is not a valid mac id\n", id);
  		return -EINVAL;
  	}
-@@ -4359,7 +4364,7 @@ void mtk_eth_set_dma_device(struct mtk_e
+@@ -4358,7 +4363,7 @@ void mtk_eth_set_dma_device(struct mtk_e
  
  	rtnl_lock();
  
@@ -165,7 +165,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dev = eth->netdev[i];
  
  		if (!dev || !(dev->flags & IFF_UP))
-@@ -4665,7 +4670,7 @@ static int mtk_remove(struct platform_de
+@@ -4664,7 +4669,7 @@ static int mtk_remove(struct platform_de
  	int i;
  
  	/* stop all devices to make sure that dma is properly shut down */
diff --git a/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
index bf6ef4c1370..1a9b31f526b 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-08-net-ethernet-mtk_eth_soc-add-NETSYS_V3-version-suppo.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -862,17 +862,32 @@ void mtk_stats_update_mac(struct mtk_mac
+@@ -861,17 +861,32 @@ void mtk_stats_update_mac(struct mtk_mac
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x20 + offs);
  		hw_stats->rx_flow_control_packets +=
  			mtk_r32(mac->hw, reg_map->gdm1_cnt + 0x24 + offs);
@@ -62,7 +62,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	u64_stats_update_end(&hw_stats->syncp);
-@@ -1176,7 +1191,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1175,7 +1190,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -74,7 +74,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -1187,6 +1205,8 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1186,6 +1204,8 @@ static void mtk_tx_set_dma_desc_v2(struc
  		/* tx checksum offload */
  		if (info->csum)
  			data |= TX_DMA_CHKSUM_V2;
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  	WRITE_ONCE(desc->txd5, data);
  
-@@ -1252,8 +1272,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1251,8 +1271,7 @@ static int mtk_tx_map(struct sk_buff *sk
  	mtk_tx_set_dma_desc(dev, itxd, &txd_info);
  
  	itx_buf->flags |= MTK_TX_FLAGS_SINGLE0;
@@ -93,7 +93,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	setup_tx_buf(eth, itx_buf, itxd_pdma, txd_info.addr, txd_info.size,
  		     k++);
  
-@@ -1301,8 +1320,7 @@ static int mtk_tx_map(struct sk_buff *sk
+@@ -1300,8 +1319,7 @@ static int mtk_tx_map(struct sk_buff *sk
  				memset(tx_buf, 0, sizeof(*tx_buf));
  			tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  			tx_buf->flags |= MTK_TX_FLAGS_PAGE0;
@@ -103,7 +103,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			setup_tx_buf(eth, tx_buf, txd_pdma, txd_info.addr,
  				     txd_info.size, k++);
-@@ -1604,7 +1622,7 @@ static int mtk_xdp_frame_map(struct mtk_
+@@ -1603,7 +1621,7 @@ static int mtk_xdp_frame_map(struct mtk_
  	}
  	mtk_tx_set_dma_desc(dev, txd, txd_info);
  
@@ -112,7 +112,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tx_buf->type = dma_map ? MTK_TYPE_XDP_NDO : MTK_TYPE_XDP_TX;
  	tx_buf->data = (void *)MTK_DMA_DUMMY_DESC;
  
-@@ -1854,11 +1872,24 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1853,11 +1871,24 @@ static int mtk_poll_rx(struct napi_struc
  			break;
  
  		/* find out which mac the packet come from. values start at 1 */
@@ -141,7 +141,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		if (unlikely(mac < 0 || mac >= MTK_MAX_DEVS ||
  			     !eth->netdev[mac]))
-@@ -2080,7 +2111,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2079,7 +2110,6 @@ static int mtk_poll_tx_qdma(struct mtk_e
  
  	while ((cpu != dma) && budget) {
  		u32 next_cpu = desc->txd2;
@@ -149,7 +149,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  		desc = mtk_qdma_phys_to_virt(ring, desc->txd2);
  		if ((desc->txd3 & TX_DMA_OWNER_CPU) == 0)
-@@ -2088,15 +2118,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
+@@ -2087,15 +2117,13 @@ static int mtk_poll_tx_qdma(struct mtk_e
  
  		tx_buf = mtk_desc_to_tx_buf(ring, desc,
  					    eth->soc->txrx.txd_size);
@@ -167,7 +167,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  			budget--;
  		}
-@@ -3705,7 +3733,24 @@ static int mtk_hw_init(struct mtk_eth *e
+@@ -3704,7 +3732,24 @@ static int mtk_hw_init(struct mtk_eth *e
  	mtk_w32(eth, eth->soc->txrx.rx_irq_done_mask, reg_map->qdma.int_grp + 4);
  	mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
  
@@ -193,7 +193,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		/* PSE should not drop port8 and port9 packets from WDMA Tx */
  		mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
  
-@@ -4267,7 +4312,11 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4266,7 +4311,11 @@ static int mtk_add_mac(struct mtk_eth *e
  	}
  	spin_lock_init(&mac->hw_stats->stats_lock);
  	u64_stats_init(&mac->hw_stats->syncp);
diff --git a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
index 97a2992cfed..8c24321dd43 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-11-net-ethernet-mtk_eth_soc-add-basic-support-for-MT798.patch
@@ -219,7 +219,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	return;
  
  err_phy:
-@@ -726,11 +842,15 @@ static int mtk_mdio_init(struct mtk_eth
+@@ -725,11 +841,15 @@ static int mtk_mdio_init(struct mtk_eth
  	}
  	divider = min_t(unsigned int, DIV_ROUND_UP(MDC_MAX_FREQ, max_clk), 63);
  
@@ -239,7 +239,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	dev_dbg(eth->dev, "MDC is running on %d Hz\n", MDC_MAX_FREQ / divider);
  
-@@ -1191,10 +1311,19 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1190,10 +1310,19 @@ static void mtk_tx_set_dma_desc_v2(struc
  		data |= TX_DMA_LS0;
  	WRITE_ONCE(desc->txd3, data);
  
@@ -263,7 +263,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	data |= TX_DMA_SWC_V2 | QID_BITS_V2(info->qid);
  	WRITE_ONCE(desc->txd4, data);
  
-@@ -4361,6 +4490,17 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4360,6 +4489,17 @@ static int mtk_add_mac(struct mtk_eth *e
  			  mac->phylink_config.supported_interfaces);
  	}
  
@@ -281,7 +281,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4881,6 +5021,24 @@ static const struct mtk_soc_data mt7986_
+@@ -4880,6 +5020,24 @@ static const struct mtk_soc_data mt7986_
  	},
  };
  
@@ -306,7 +306,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static const struct mtk_soc_data rt5350_data = {
  	.reg_map = &mt7628_reg_map,
  	.caps = MT7628_CAPS,
-@@ -4899,14 +5057,15 @@ static const struct mtk_soc_data rt5350_
+@@ -4898,14 +5056,15 @@ static const struct mtk_soc_data rt5350_
  };
  
  const struct of_device_id of_mtk_match[] = {
diff --git a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
index 62c38c7137f..3dc4662d1a5 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-12-net-ethernet-mtk_eth_soc-enable-page_pool-support-fo.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1659,7 +1659,7 @@ static void mtk_update_rx_cpu_idx(struct
+@@ -1658,7 +1658,7 @@ static void mtk_update_rx_cpu_idx(struct
  
  static bool mtk_page_pool_enabled(struct mtk_eth *eth)
  {
diff --git a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
index b175aedf0c4..32f26d7d27d 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-13-net-ethernet-mtk_eth_soc-enable-nft-hw-flowtable_off.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5029,6 +5029,9 @@ static const struct mtk_soc_data mt7988_
+@@ -5028,6 +5028,9 @@ static const struct mtk_soc_data mt7988_
  	.required_clks = MT7988_CLKS_BITMAP,
  	.required_pctl = false,
  	.version = 3,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
index bf0a39b9d3f..876bdd5dd31 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-14-net-ethernet-mtk_eth_soc-support-per-flow-accounting.patch
@@ -20,7 +20,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -5031,6 +5031,7 @@ static const struct mtk_soc_data mt7988_
+@@ -5030,6 +5030,7 @@ static const struct mtk_soc_data mt7988_
  	.version = 3,
  	.offload_version = 2,
  	.hash_offset = 4,
diff --git a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
index a4ff5a292e7..05a18364d67 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-17-net-ethernet-mtk_eth_soc-add-reset-bits-for-MT7988.patch
@@ -16,7 +16,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3595,19 +3595,34 @@ static void mtk_hw_reset(struct mtk_eth
+@@ -3594,19 +3594,34 @@ static void mtk_hw_reset(struct mtk_eth
  {
  	u32 val;
  
@@ -56,7 +56,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		regmap_write(eth->ethsys, ETHSYS_FE_RST_CHK_IDLE_EN,
  			     0x3ffffff);
  }
-@@ -3633,13 +3648,21 @@ static void mtk_hw_warm_reset(struct mtk
+@@ -3632,13 +3647,21 @@ static void mtk_hw_warm_reset(struct mtk
  		return;
  	}
  
@@ -83,7 +83,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	regmap_update_bits(eth->ethsys, ETHSYS_RSTCTRL, rst_mask, rst_mask);
  
-@@ -3991,11 +4014,17 @@ static void mtk_prepare_for_reset(struct
+@@ -3990,11 +4013,17 @@ static void mtk_prepare_for_reset(struct
  	u32 val;
  	int i;
  
@@ -106,7 +106,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  
  	/* adjust PPE configurations to prepare for reset */
  	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
-@@ -4056,11 +4085,18 @@ static void mtk_pending_work(struct work
+@@ -4055,11 +4084,18 @@ static void mtk_pending_work(struct work
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
index 872262b0f82..74ac8dc8981 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-18-net-ethernet-mtk_eth_soc-add-support-for-in-SoC-SRAM.patch
@@ -20,7 +20,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1119,10 +1119,13 @@ static int mtk_init_fq_dma(struct mtk_et
+@@ -1118,10 +1118,13 @@ static int mtk_init_fq_dma(struct mtk_et
  	dma_addr_t dma_addr;
  	int i;
  
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (unlikely(!eth->scratch_ring))
  		return -ENOMEM;
  
-@@ -2430,8 +2433,14 @@ static int mtk_tx_alloc(struct mtk_eth *
+@@ -2429,8 +2432,14 @@ static int mtk_tx_alloc(struct mtk_eth *
  	if (!ring->buf)
  		goto no_tx_mem;
  
@@ -55,7 +55,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!ring->dma)
  		goto no_tx_mem;
  
-@@ -2530,8 +2539,7 @@ static void mtk_tx_clean(struct mtk_eth
+@@ -2529,8 +2538,7 @@ static void mtk_tx_clean(struct mtk_eth
  		kfree(ring->buf);
  		ring->buf = NULL;
  	}
@@ -65,7 +65,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  ring->dma_size * soc->txrx.txd_size,
  				  ring->dma, ring->phys);
-@@ -2550,9 +2558,14 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2549,9 +2557,14 @@ static int mtk_rx_alloc(struct mtk_eth *
  {
  	const struct mtk_reg_map *reg_map = eth->soc->reg_map;
  	struct mtk_rx_ring *ring;
@@ -81,7 +81,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (rx_flag == MTK_RX_FLAGS_QDMA) {
  		if (ring_no)
  			return -EINVAL;
-@@ -2587,9 +2600,20 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2586,9 +2599,20 @@ static int mtk_rx_alloc(struct mtk_eth *
  		ring->page_pool = pp;
  	}
  
@@ -105,7 +105,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	if (!ring->dma)
  		return -ENOMEM;
  
-@@ -2674,7 +2698,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2673,7 +2697,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  	return 0;
  }
  
@@ -114,7 +114,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  {
  	int i;
  
-@@ -2697,7 +2721,7 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2696,7 +2720,7 @@ static void mtk_rx_clean(struct mtk_eth
  		ring->data = NULL;
  	}
  
@@ -123,7 +123,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  ring->dma_size * eth->soc->txrx.rxd_size,
  				  ring->dma, ring->phys);
-@@ -3060,7 +3084,7 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3059,7 +3083,7 @@ static void mtk_dma_free(struct mtk_eth
  	for (i = 0; i < MTK_MAX_DEVS; i++)
  		if (eth->netdev[i])
  			netdev_reset_queue(eth->netdev[i]);
@@ -132,7 +132,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		dma_free_coherent(eth->dma_dev,
  				  MTK_QDMA_RING_SIZE * soc->txrx.txd_size,
  				  eth->scratch_ring, eth->phy_scratch_ring);
-@@ -3068,13 +3092,13 @@ static void mtk_dma_free(struct mtk_eth
+@@ -3067,13 +3091,13 @@ static void mtk_dma_free(struct mtk_eth
  		eth->phy_scratch_ring = 0;
  	}
  	mtk_tx_clean(eth);
@@ -149,7 +149,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	}
  
  	kfree(eth->scratch_head);
-@@ -4642,7 +4666,7 @@ static int mtk_sgmii_init(struct mtk_eth
+@@ -4641,7 +4665,7 @@ static int mtk_sgmii_init(struct mtk_eth
  
  static int mtk_probe(struct platform_device *pdev)
  {
@@ -158,7 +158,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	struct device_node *mac_np;
  	struct mtk_eth *eth;
  	int err, i;
-@@ -4662,6 +4686,20 @@ static int mtk_probe(struct platform_dev
+@@ -4661,6 +4685,20 @@ static int mtk_probe(struct platform_dev
  	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SOC_MT7628))
  		eth->ip_align = NET_IP_ALIGN;
  
@@ -179,7 +179,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	spin_lock_init(&eth->page_lock);
  	spin_lock_init(&eth->tx_irq_lock);
  	spin_lock_init(&eth->rx_irq_lock);
-@@ -4725,6 +4763,18 @@ static int mtk_probe(struct platform_dev
+@@ -4724,6 +4762,18 @@ static int mtk_probe(struct platform_dev
  			err = -EINVAL;
  			goto err_destroy_sgmii;
  		}
diff --git a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
index 9266c33f825..1584dfd07c6 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-19-net-ethernet-mtk_eth_soc-support-36-bit-DMA-addressi.patch
@@ -19,7 +19,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1312,6 +1312,10 @@ static void mtk_tx_set_dma_desc_v2(struc
+@@ -1311,6 +1311,10 @@ static void mtk_tx_set_dma_desc_v2(struc
  	data = TX_DMA_PLEN0(info->size);
  	if (info->last)
  		data |= TX_DMA_LS0;
@@ -30,7 +30,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	WRITE_ONCE(desc->txd3, data);
  
  	 /* set forward port */
-@@ -1981,6 +1985,7 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1980,6 +1984,7 @@ static int mtk_poll_rx(struct napi_struc
  	bool xdp_flush = false;
  	int idx;
  	struct sk_buff *skb;
@@ -38,7 +38,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	u8 *data, *new_data;
  	struct mtk_rx_dma_v2 *rxd, trxd;
  	int done = 0, bytes = 0;
-@@ -2096,7 +2101,10 @@ static int mtk_poll_rx(struct napi_struc
+@@ -2095,7 +2100,10 @@ static int mtk_poll_rx(struct napi_struc
  				goto release_desc;
  			}
  
@@ -50,7 +50,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					 ring->buf_size, DMA_FROM_DEVICE);
  
  			skb = build_skb(data, ring->frag_size);
-@@ -2162,6 +2170,9 @@ release_desc:
+@@ -2161,6 +2169,9 @@ release_desc:
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
@@ -60,7 +60,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		ring->calc_idx = idx;
  		done++;
  	}
-@@ -2654,6 +2665,9 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2653,6 +2664,9 @@ static int mtk_rx_alloc(struct mtk_eth *
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
@@ -70,7 +70,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  		rxd->rxd3 = 0;
  		rxd->rxd4 = 0;
  		if (mtk_is_netsys_v2_or_greater(eth)) {
-@@ -2700,6 +2714,7 @@ static int mtk_rx_alloc(struct mtk_eth *
+@@ -2699,6 +2713,7 @@ static int mtk_rx_alloc(struct mtk_eth *
  
  static void mtk_rx_clean(struct mtk_eth *eth, struct mtk_rx_ring *ring, bool in_sram)
  {
@@ -78,7 +78,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int i;
  
  	if (ring->data && ring->dma) {
-@@ -2713,7 +2728,10 @@ static void mtk_rx_clean(struct mtk_eth
+@@ -2712,7 +2727,10 @@ static void mtk_rx_clean(struct mtk_eth
  			if (!rxd->rxd1)
  				continue;
  
@@ -90,7 +90,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  					 ring->buf_size, DMA_FROM_DEVICE);
  			mtk_rx_put_buff(ring, ring->data[i], false);
  		}
-@@ -4700,6 +4718,14 @@ static int mtk_probe(struct platform_dev
+@@ -4699,6 +4717,14 @@ static int mtk_probe(struct platform_dev
  		}
  	}
  
diff --git a/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch b/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
index 697c2db1451..5b27458eb8e 100644
--- a/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
+++ b/target/linux/generic/backport-6.1/750-v6.5-20-net-ethernet-mtk_eth_soc-fix-uninitialized-variable.patch
@@ -19,7 +19,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1989,11 +1989,11 @@ static int mtk_poll_rx(struct napi_struc
+@@ -1988,11 +1988,11 @@ static int mtk_poll_rx(struct napi_struc
  	u8 *data, *new_data;
  	struct mtk_rx_dma_v2 *rxd, trxd;
  	int done = 0, bytes = 0;
@@ -32,7 +32,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  		u32 hash, reason;
  		int mac = 0;
  
-@@ -2170,7 +2170,8 @@ release_desc:
+@@ -2169,7 +2169,8 @@ release_desc:
  		else
  			rxd->rxd2 = RX_DMA_PREP_PLEN0(ring->buf_size);
  
diff --git a/target/linux/generic/backport-6.1/770-net-introduce-napi_is_scheduled-helper.patch b/target/linux/generic/backport-6.1/770-net-introduce-napi_is_scheduled-helper.patch
new file mode 100644
index 00000000000..789b93e9f93
--- /dev/null
+++ b/target/linux/generic/backport-6.1/770-net-introduce-napi_is_scheduled-helper.patch
@@ -0,0 +1,96 @@
+From 7f3eb2174512fe6c9c0f062e96eccb0d3cc6d5cd Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Oct 2023 14:35:47 +0200
+Subject: [PATCH] net: introduce napi_is_scheduled helper
+
+We currently have napi_if_scheduled_mark_missed that can be used to
+check if napi is scheduled but that does more thing than simply checking
+it and return a bool. Some driver already implement custom function to
+check if napi is scheduled.
+
+Drop these custom function and introduce napi_is_scheduled that simply
+check if napi is scheduled atomically.
+
+Update any driver and code that implement a similar check and instead
+use this new helper.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/chelsio/cxgb3/sge.c  |  8 --------
+ drivers/net/wireless/realtek/rtw89/core.c |  2 +-
+ include/linux/netdevice.h                 | 23 +++++++++++++++++++++++
+ net/core/dev.c                            |  2 +-
+ 4 files changed, 25 insertions(+), 10 deletions(-)
+
+--- a/drivers/net/ethernet/chelsio/cxgb3/sge.c
++++ b/drivers/net/ethernet/chelsio/cxgb3/sge.c
+@@ -2507,14 +2507,6 @@ static int napi_rx_handler(struct napi_s
+ 	return work_done;
+ }
+ 
+-/*
+- * Returns true if the device is already scheduled for polling.
+- */
+-static inline int napi_is_scheduled(struct napi_struct *napi)
+-{
+-	return test_bit(NAPI_STATE_SCHED, &napi->state);
+-}
+-
+ /**
+  *	process_pure_responses - process pure responses from a response queue
+  *	@adap: the adapter
+--- a/drivers/net/wireless/realtek/rtw89/core.c
++++ b/drivers/net/wireless/realtek/rtw89/core.c
+@@ -1479,7 +1479,7 @@ static void rtw89_core_rx_to_mac80211(st
+ 	struct napi_struct *napi = &rtwdev->napi;
+ 
+ 	/* In low power mode, napi isn't scheduled. Receive it to netif. */
+-	if (unlikely(!test_bit(NAPI_STATE_SCHED, &napi->state)))
++	if (unlikely(!napi_is_scheduled(napi)))
+ 		napi = NULL;
+ 
+ 	rtw89_core_hw_to_sband_rate(rx_status);
+--- a/include/linux/netdevice.h
++++ b/include/linux/netdevice.h
+@@ -468,6 +468,29 @@ static inline bool napi_prefer_busy_poll
+ 	return test_bit(NAPI_STATE_PREFER_BUSY_POLL, &n->state);
+ }
+ 
++/**
++ * napi_is_scheduled - test if NAPI is scheduled
++ * @n: NAPI context
++ *
++ * This check is "best-effort". With no locking implemented,
++ * a NAPI can be scheduled or terminate right after this check
++ * and produce not precise results.
++ *
++ * NAPI_STATE_SCHED is an internal state, napi_is_scheduled
++ * should not be used normally and napi_schedule should be
++ * used instead.
++ *
++ * Use only if the driver really needs to check if a NAPI
++ * is scheduled for example in the context of delayed timer
++ * that can be skipped if a NAPI is already scheduled.
++ *
++ * Return True if NAPI is scheduled, False otherwise.
++ */
++static inline bool napi_is_scheduled(struct napi_struct *n)
++{
++	return test_bit(NAPI_STATE_SCHED, &n->state);
++}
++
+ bool napi_schedule_prep(struct napi_struct *n);
+ 
+ /**
+--- a/net/core/dev.c
++++ b/net/core/dev.c
+@@ -6533,7 +6533,7 @@ static int __napi_poll(struct napi_struc
+ 	 * accidentally calling ->poll() when NAPI is not scheduled.
+ 	 */
+ 	work = 0;
+-	if (test_bit(NAPI_STATE_SCHED, &n->state)) {
++	if (napi_is_scheduled(n)) {
+ 		work = n->poll(n, weight);
+ 		trace_napi_poll(n, work, weight);
+ 	}
diff --git a/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch b/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
new file mode 100644
index 00000000000..aa0d730bc8a
--- /dev/null
+++ b/target/linux/generic/backport-6.1/771-v6.7-01-net-stmmac-improve-TX-timer-arm-logic.patch
@@ -0,0 +1,77 @@
+From 2d1a42cf7f77cda54dbbee18d00b1200e7bc22aa Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Oct 2023 14:35:48 +0200
+Subject: [PATCH 1/3] net: stmmac: improve TX timer arm logic
+
+There is currently a problem with the TX timer getting armed multiple
+unnecessary times causing big performance regression on some device that
+suffer from heavy handling of hrtimer rearm.
+
+The use of the TX timer is an old implementation that predates the napi
+implementation and the interrupt enable/disable handling.
+
+Due to stmmac being a very old code, the TX timer was never evaluated
+again with this new implementation and was kept there causing
+performance regression. The performance regression started to appear
+with kernel version 4.19 with 8fce33317023 ("net: stmmac: Rework coalesce
+timer and fix multi-queue races") where the timer was reduced to 1ms
+causing it to be armed 40 times more than before.
+
+Decreasing the timer made the problem more present and caused the
+regression in the other of 600-700mbps on some device (regression where
+this was notice is ipq806x).
+
+The problem is in the fact that handling the hrtimer on some target is
+expensive and recent kernel made the timer armed much more times.
+A solution that was proposed was reverting the hrtimer change and use
+mod_timer but such solution would still hide the real problem in the
+current implementation.
+
+To fix the regression, apply some additional logic and skip arming the
+timer when not needed.
+
+Arm the timer ONLY if a napi is not already scheduled. Running the timer
+is redundant since the same function (stmmac_tx_clean) will run in the
+napi TX poll. Also try to cancel any timer if a napi is scheduled to
+prevent redundant run of TX call.
+
+With the following new logic the original performance are restored while
+keeping using the hrtimer.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ .../net/ethernet/stmicro/stmmac/stmmac_main.c  | 18 +++++++++++++++---
+ 1 file changed, 15 insertions(+), 3 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -2974,13 +2974,25 @@ static void stmmac_tx_timer_arm(struct s
+ {
+ 	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
+ 	u32 tx_coal_timer = priv->tx_coal_timer[queue];
++	struct stmmac_channel *ch;
++	struct napi_struct *napi;
+ 
+ 	if (!tx_coal_timer)
+ 		return;
+ 
+-	hrtimer_start(&tx_q->txtimer,
+-		      STMMAC_COAL_TIMER(tx_coal_timer),
+-		      HRTIMER_MODE_REL);
++	ch = &priv->channel[tx_q->queue_index];
++	napi = tx_q->xsk_pool ? &ch->rxtx_napi : &ch->tx_napi;
++
++	/* Arm timer only if napi is not already scheduled.
++	 * Try to cancel any timer if napi is scheduled, timer will be armed
++	 * again in the next scheduled napi.
++	 */
++	if (unlikely(!napi_is_scheduled(napi)))
++		hrtimer_start(&tx_q->txtimer,
++			      STMMAC_COAL_TIMER(tx_coal_timer),
++			      HRTIMER_MODE_REL);
++	else
++		hrtimer_try_to_cancel(&tx_q->txtimer);
+ }
+ 
+ /**
diff --git a/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
new file mode 100644
index 00000000000..4e9e951598b
--- /dev/null
+++ b/target/linux/generic/backport-6.1/771-v6.7-02-net-stmmac-move-TX-timer-arm-after-DMA-enable.patch
@@ -0,0 +1,96 @@
+From a594166387fe08e6f5a32130c400249a35b298f9 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Oct 2023 14:35:49 +0200
+Subject: [PATCH 2/3] net: stmmac: move TX timer arm after DMA enable
+
+Move TX timer arm call after DMA interrupt is enabled again.
+
+The TX timer arm function changed logic and now is skipped if a napi is
+already scheduled. By moving the TX timer arm call after DMA is enabled,
+we permit to correctly skip if a DMA interrupt has been fired and a napi
+has been scheduled again.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ .../net/ethernet/stmicro/stmmac/stmmac_main.c | 22 +++++++++++++++----
+ 1 file changed, 18 insertions(+), 4 deletions(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
++++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+@@ -2527,9 +2527,13 @@ static void stmmac_bump_dma_threshold(st
+  * @priv: driver private structure
+  * @budget: napi budget limiting this functions packet handling
+  * @queue: TX queue index
++ * @pending_packets: signal to arm the TX coal timer
+  * Description: it reclaims the transmit resources after transmission completes.
++ * If some packets still needs to be handled, due to TX coalesce, set
++ * pending_packets to true to make NAPI arm the TX coal timer.
+  */
+-static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue)
++static int stmmac_tx_clean(struct stmmac_priv *priv, int budget, u32 queue,
++			   bool *pending_packets)
+ {
+ 	struct stmmac_tx_queue *tx_q = &priv->dma_conf.tx_queue[queue];
+ 	unsigned int bytes_compl = 0, pkts_compl = 0;
+@@ -2692,7 +2696,7 @@ static int stmmac_tx_clean(struct stmmac
+ 
+ 	/* We still have pending packets, let's call for a new scheduling */
+ 	if (tx_q->dirty_tx != tx_q->cur_tx)
+-		stmmac_tx_timer_arm(priv, queue);
++		*pending_packets = true;
+ 
+ 	__netif_tx_unlock_bh(netdev_get_tx_queue(priv->dev, queue));
+ 
+@@ -5485,12 +5489,13 @@ static int stmmac_napi_poll_tx(struct na
+ 	struct stmmac_channel *ch =
+ 		container_of(napi, struct stmmac_channel, tx_napi);
+ 	struct stmmac_priv *priv = ch->priv_data;
++	bool pending_packets = false;
+ 	u32 chan = ch->index;
+ 	int work_done;
+ 
+ 	priv->xstats.napi_poll++;
+ 
+-	work_done = stmmac_tx_clean(priv, budget, chan);
++	work_done = stmmac_tx_clean(priv, budget, chan, &pending_packets);
+ 	work_done = min(work_done, budget);
+ 
+ 	if (work_done < budget && napi_complete_done(napi, work_done)) {
+@@ -5501,6 +5506,10 @@ static int stmmac_napi_poll_tx(struct na
+ 		spin_unlock_irqrestore(&ch->lock, flags);
+ 	}
+ 
++	/* TX still have packet to handle, check if we need to arm tx timer */
++	if (pending_packets)
++		stmmac_tx_timer_arm(priv, chan);
++
+ 	return work_done;
+ }
+ 
+@@ -5509,12 +5518,13 @@ static int stmmac_napi_poll_rxtx(struct
+ 	struct stmmac_channel *ch =
+ 		container_of(napi, struct stmmac_channel, rxtx_napi);
+ 	struct stmmac_priv *priv = ch->priv_data;
++	bool tx_pending_packets = false;
+ 	int rx_done, tx_done, rxtx_done;
+ 	u32 chan = ch->index;
+ 
+ 	priv->xstats.napi_poll++;
+ 
+-	tx_done = stmmac_tx_clean(priv, budget, chan);
++	tx_done = stmmac_tx_clean(priv, budget, chan, &tx_pending_packets);
+ 	tx_done = min(tx_done, budget);
+ 
+ 	rx_done = stmmac_rx_zc(priv, budget, chan);
+@@ -5539,6 +5549,10 @@ static int stmmac_napi_poll_rxtx(struct
+ 		spin_unlock_irqrestore(&ch->lock, flags);
+ 	}
+ 
++	/* TX still have packet to handle, check if we need to arm tx timer */
++	if (tx_pending_packets)
++		stmmac_tx_timer_arm(priv, chan);
++
+ 	return min(rxtx_done, budget - 1);
+ }
+ 
diff --git a/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch b/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
new file mode 100644
index 00000000000..bce54eba4f0
--- /dev/null
+++ b/target/linux/generic/backport-6.1/771-v6.7-03-net-stmmac-increase-TX-coalesce-timer-to-5ms.patch
@@ -0,0 +1,38 @@
+From 039550960a2235cfe2dfaa773df9f98f8da31a0c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 18 Oct 2023 14:35:50 +0200
+Subject: [PATCH 3/3] net: stmmac: increase TX coalesce timer to 5ms
+
+Commit 8fce33317023 ("net: stmmac: Rework coalesce timer and fix
+multi-queue races") decreased the TX coalesce timer from 40ms to 1ms.
+
+This caused some performance regression on some target (regression was
+reported at least on ipq806x) in the order of 600mbps dropping from
+gigabit handling to only 200mbps.
+
+The problem was identified in the TX timer getting armed too much time.
+While this was fixed and improved in another commit, performance can be
+improved even further by increasing the timer delay a bit moving from
+1ms to 5ms.
+
+The value is a good balance between battery saving by prevending too
+much interrupt to be generated and permitting good performance for
+internet oriented devices.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/ethernet/stmicro/stmmac/common.h | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/stmicro/stmmac/common.h
++++ b/drivers/net/ethernet/stmicro/stmmac/common.h
+@@ -287,7 +287,7 @@ struct stmmac_safety_stats {
+ #define MIN_DMA_RIWT		0x10
+ #define DEF_DMA_RIWT		0xa0
+ /* Tx coalesce parameters */
+-#define STMMAC_COAL_TX_TIMER	1000
++#define STMMAC_COAL_TX_TIMER	5000
+ #define STMMAC_MAX_COAL_TX_TICK	100000
+ #define STMMAC_TX_MAX_FRAMES	256
+ #define STMMAC_TX_FRAMES	25
diff --git a/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch b/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch
index 0a631a09c1d..b8f8071b0a1 100644
--- a/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch
+++ b/target/linux/generic/backport-6.1/778-v6.3-02-net-dsa-qca8k-convert-to-regmap-read-write-API.patch
@@ -168,7 +168,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  static int
-@@ -2102,8 +2158,6 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
+@@ -2112,8 +2168,6 @@ static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
  
  static const struct qca8k_info_ops qca8xxx_ops = {
  	.autocast_mib = qca8k_get_ethtool_stats_eth,
diff --git a/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch b/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch
index 6e93491a127..d31789370e8 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-01-net-dsa-qca8k-make-learning-configurable-and-keep-of.patch
@@ -32,7 +32,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1894,9 +1894,8 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1905,9 +1905,8 @@ qca8k_setup(struct dsa_switch *ds)
  			if (ret)
  				return ret;
  
@@ -44,7 +44,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  			if (ret)
  				return ret;
  
-@@ -2002,6 +2001,8 @@ static const struct dsa_switch_ops qca8k
+@@ -2013,6 +2012,8 @@ static const struct dsa_switch_ops qca8k
  	.port_change_mtu	= qca8k_port_change_mtu,
  	.port_max_mtu		= qca8k_port_max_mtu,
  	.port_stp_state_set	= qca8k_port_stp_state_set,
diff --git a/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch b/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch
index fdb3a8cdb94..4b457f67de8 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-02-net-dsa-qca8k-limit-user-ports-access-to-the-first-C.patch
@@ -26,7 +26,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1874,18 +1874,16 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1885,18 +1885,16 @@ qca8k_setup(struct dsa_switch *ds)
  	if (ret)
  		return ret;
  
diff --git a/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch b/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch
index c789fdf05ee..f556628b5b5 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-03-net-dsa-qca8k-move-qca8xxx-hol-fixup-to-separate-fun.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1784,6 +1784,46 @@ static int qca8k_connect_tag_protocol(st
+@@ -1795,6 +1795,46 @@ static int qca8k_connect_tag_protocol(st
  	return 0;
  }
  
@@ -64,7 +64,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  static int
  qca8k_setup(struct dsa_switch *ds)
  {
-@@ -1919,42 +1959,8 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1930,42 +1970,8 @@ qca8k_setup(struct dsa_switch *ds)
  		 * missing settings to improve switch stability under load condition.
  		 * This problem is limited to qca8337 and other qca8k switch are not affected.
  		 */
diff --git a/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch b/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch
index 4f9581235db..faa0142ca99 100644
--- a/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch
+++ b/target/linux/generic/backport-6.1/780-v6.6-04-net-dsa-qca8k-use-dsa_for_each-macro-instead-of-for-.patch
@@ -17,7 +17,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1828,7 +1828,8 @@ static int
+@@ -1839,7 +1839,8 @@ static int
  qca8k_setup(struct dsa_switch *ds)
  {
  	struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
@@ -27,7 +27,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	u32 mask;
  
  	cpu_port = qca8k_find_cpu_port(ds);
-@@ -1879,27 +1880,27 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1890,27 +1891,27 @@ qca8k_setup(struct dsa_switch *ds)
  		dev_warn(priv->dev, "mib init failed");
  
  	/* Initial setup of all ports */
@@ -70,7 +70,7 @@ Signed-off-by: Paolo Abeni <pabeni@redhat.com>
  	}
  
  	/* Forward all unknown frames to CPU port for Linux processing
-@@ -1921,48 +1922,48 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1932,48 +1933,48 @@ qca8k_setup(struct dsa_switch *ds)
  		return ret;
  
  	/* Setup connection between CPU port & user ports
diff --git a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
index 893a81246d8..f82c8fc622b 100644
--- a/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
+++ b/target/linux/generic/backport-6.1/792-v6.6-net-phylink-add-pcs_enable-pcs_disable-methods.patch
@@ -27,15 +27,15 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  };
  
  /**
-@@ -71,6 +75,7 @@ struct phylink {
- 	struct mutex state_mutex;
+@@ -72,6 +76,7 @@ struct phylink {
  	struct phylink_link_state phy_state;
  	struct work_struct resolve;
+ 	unsigned int pcs_neg_mode;
 +	unsigned int pcs_state;
  
  	bool mac_link_dropped;
  	bool using_mac_select_pcs;
-@@ -990,6 +995,22 @@ static void phylink_mac_pcs_an_restart(s
+@@ -992,6 +997,22 @@ static void phylink_resolve_an_pause(str
  	}
  }
  
@@ -55,16 +55,17 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	return err;
 +}
 +
- static void phylink_major_config(struct phylink *pl, bool restart,
- 				  const struct phylink_link_state *state)
- {
-@@ -1026,11 +1047,16 @@ static void phylink_major_config(struct
+ static int phylink_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 			      const struct phylink_link_state *state,
+ 			      bool permit_pause_to_mac)
+@@ -1094,11 +1115,17 @@ static void phylink_major_config(struct
  	/* If we have a new PCS, switch to the new PCS after preparing the MAC
  	 * for the change.
  	 */
 -	if (pcs_changed)
 +	if (pcs_changed) {
 +		phylink_pcs_disable(pl->pcs);
++
  		pl->pcs = pcs;
 +	}
  
@@ -73,18 +74,18 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	if (pl->pcs_state == PCS_STATE_STARTING || pcs_changed)
 +		phylink_pcs_enable(pl->pcs);
 +
- 	if (pl->pcs) {
- 		err = pl->pcs->ops->pcs_config(pl->pcs, pl->cur_link_an_mode,
- 					       state->interface,
-@@ -1502,6 +1528,7 @@ struct phylink *phylink_create(struct ph
+ 	neg_mode = pl->cur_link_an_mode;
+ 	if (pl->pcs && pl->pcs->neg_mode)
+ 		neg_mode = pl->pcs_neg_mode;
+@@ -1586,6 +1613,7 @@ struct phylink *phylink_create(struct ph
+ 	pl->link_config.pause = MLO_PAUSE_AN;
  	pl->link_config.speed = SPEED_UNKNOWN;
  	pl->link_config.duplex = DUPLEX_UNKNOWN;
- 	pl->link_config.an_enabled = true;
 +	pl->pcs_state = PCS_STATE_DOWN;
  	pl->mac_ops = mac_ops;
  	__set_bit(PHYLINK_DISABLE_STOPPED, &pl->phylink_disable_state);
  	timer_setup(&pl->link_poll, phylink_fixed_poll, 0);
-@@ -1903,6 +1930,8 @@ void phylink_start(struct phylink *pl)
+@@ -1987,6 +2015,8 @@ void phylink_start(struct phylink *pl)
  	if (pl->netdev)
  		netif_carrier_off(pl->netdev);
  
@@ -93,7 +94,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	/* Apply the link configuration to the MAC when starting. This allows
  	 * a fixed-link to start with the correct parameters, and also
  	 * ensures that we set the appropriate advertisement for Serdes links.
-@@ -1913,6 +1942,8 @@ void phylink_start(struct phylink *pl)
+@@ -1997,6 +2027,8 @@ void phylink_start(struct phylink *pl)
  	 */
  	phylink_mac_initial_config(pl, true);
  
@@ -102,7 +103,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	phylink_enable_and_run_resolve(pl, PHYLINK_DISABLE_STOPPED);
  
  	if (pl->cfg_link_an_mode == MLO_AN_FIXED && pl->link_gpio) {
-@@ -1931,15 +1962,9 @@ void phylink_start(struct phylink *pl)
+@@ -2015,15 +2047,9 @@ void phylink_start(struct phylink *pl)
  			poll = true;
  	}
  
@@ -120,7 +121,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (poll)
  		mod_timer(&pl->link_poll, jiffies + HZ);
  	if (pl->phydev)
-@@ -1976,6 +2001,10 @@ void phylink_stop(struct phylink *pl)
+@@ -2060,6 +2086,10 @@ void phylink_stop(struct phylink *pl)
  	}
  
  	phylink_run_resolve_and_disable(pl, PHYLINK_DISABLE_STOPPED);
@@ -133,7 +134,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
 --- a/include/linux/phylink.h
 +++ b/include/linux/phylink.h
-@@ -446,6 +446,8 @@ struct phylink_pcs {
+@@ -533,6 +533,8 @@ struct phylink_pcs {
  /**
   * struct phylink_pcs_ops - MAC PCS operations structure.
   * @pcs_validate: validate the link configuration.
@@ -142,7 +143,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @pcs_get_state: read the current MAC PCS link state from the hardware.
   * @pcs_config: configure the MAC PCS for the selected mode and state.
   * @pcs_an_restart: restart 802.3z BaseX autonegotiation.
-@@ -455,6 +457,8 @@ struct phylink_pcs {
+@@ -542,6 +544,8 @@ struct phylink_pcs {
  struct phylink_pcs_ops {
  	int (*pcs_validate)(struct phylink_pcs *pcs, unsigned long *supported,
  			    const struct phylink_link_state *state);
@@ -150,8 +151,8 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 +	void (*pcs_disable)(struct phylink_pcs *pcs);
  	void (*pcs_get_state)(struct phylink_pcs *pcs,
  			      struct phylink_link_state *state);
- 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int mode,
-@@ -485,6 +489,18 @@ int pcs_validate(struct phylink_pcs *pcs
+ 	int (*pcs_config)(struct phylink_pcs *pcs, unsigned int neg_mode,
+@@ -572,6 +576,18 @@ int pcs_validate(struct phylink_pcs *pcs
  		 const struct phylink_link_state *state);
  
  /**
diff --git a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
index eb9b4b7c09e..6b6369761a1 100644
--- a/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
+++ b/target/linux/generic/backport-6.1/793-v6.6-net-pcs-lynxi-implement-pcs_disable-op.patch
@@ -22,7 +22,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -241,11 +241,19 @@ static void mtk_pcs_lynxi_link_up(struct
+@@ -234,11 +234,19 @@ static void mtk_pcs_lynxi_link_up(struct
  	}
  }
  
diff --git a/target/linux/generic/backport-6.1/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch b/target/linux/generic/backport-6.1/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch
index a9e3c71d542..c4141eee933 100644
--- a/target/linux/generic/backport-6.1/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch
+++ b/target/linux/generic/backport-6.1/794-v6.2-net-core-Allow-live-renaming-when-an-interface-is-up.patch
@@ -46,7 +46,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -1668,7 +1668,6 @@ struct net_device_ops {
+@@ -1691,7 +1691,6 @@ struct net_device_ops {
   * @IFF_FAILOVER: device is a failover master device
   * @IFF_FAILOVER_SLAVE: device is lower dev of a failover master device
   * @IFF_L3MDEV_RX_HANDLER: only invoke the rx handler of L3 master device
@@ -54,7 +54,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @IFF_TX_SKB_NO_LINEAR: device/driver is capable of xmitting frames with
   *	skb_headlen(skb) == 0 (data starts from frag0)
   * @IFF_CHANGE_PROTO_DOWN: device supports setting carrier via IFLA_PROTO_DOWN
-@@ -1704,7 +1703,7 @@ enum netdev_priv_flags {
+@@ -1727,7 +1726,7 @@ enum netdev_priv_flags {
  	IFF_FAILOVER			= 1<<27,
  	IFF_FAILOVER_SLAVE		= 1<<28,
  	IFF_L3MDEV_RX_HANDLER		= 1<<29,
@@ -63,7 +63,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	IFF_TX_SKB_NO_LINEAR		= BIT_ULL(31),
  	IFF_CHANGE_PROTO_DOWN		= BIT_ULL(32),
  };
-@@ -1739,7 +1738,6 @@ enum netdev_priv_flags {
+@@ -1762,7 +1761,6 @@ enum netdev_priv_flags {
  #define IFF_FAILOVER			IFF_FAILOVER
  #define IFF_FAILOVER_SLAVE		IFF_FAILOVER_SLAVE
  #define IFF_L3MDEV_RX_HANDLER		IFF_L3MDEV_RX_HANDLER
diff --git a/target/linux/generic/backport-6.1/795-v6.8-19-r8152-Choose-our-USB-config-with-choose_configuratio.patch b/target/linux/generic/backport-6.1/795-v6.8-19-r8152-Choose-our-USB-config-with-choose_configuratio.patch
deleted file mode 100644
index 05fb69bc21e..00000000000
--- a/target/linux/generic/backport-6.1/795-v6.8-19-r8152-Choose-our-USB-config-with-choose_configuratio.patch
+++ /dev/null
@@ -1,70 +0,0 @@
-From aa4f2b3e418e8673e55145de8b8016a7a9920306 Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Fri, 1 Dec 2023 10:29:52 -0800
-Subject: [PATCH] r8152: Choose our USB config with choose_configuration()
- rather than probe()
-
-If you deauthorize the r8152 device (by writing 0 to the "authorized"
-field in sysfs) and then reauthorize it (by writing a 1) then it no
-longer works. This is because when you do the above we lose the
-special configuration that we set in rtl8152_cfgselector_probe().
-Deauthorizing causes the config to be set to -1 and then reauthorizing
-runs the default logic for choosing the best config.
-
-I made an attempt to fix it so that the config is kept across
-deauthorizing / reauthorizing [1] but it was a bit ugly.
-
-Let's instead use the new USB core feature to override
-choose_configuration().
-
-This patch relies upon the patches ("usb: core: Don't force USB
-generic_subclass drivers to define probe()") and ("usb: core: Allow
-subclassed USB drivers to override usb_choose_configuration()")
-
-[1] https://lore.kernel.org/r/20231130154337.1.Ie00e07f07f87149c9ce0b27ae4e26991d307e14b@changeid
-
-Fixes: ec51fbd1b8a2 ("r8152: add USB device driver for config selection")
-Suggested-by: Alan Stern <stern@rowland.harvard.edu>
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Grant Grundler <grundler@chromium.org>
-Link: https://lore.kernel.org/r/20231201102946.v2.3.Ie00e07f07f87149c9ce0b27ae4e26991d307e14b@changeid
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/net/usb/r8152.c | 16 +++++-----------
- 1 file changed, 5 insertions(+), 11 deletions(-)
-
---- a/drivers/net/usb/r8152.c
-+++ b/drivers/net/usb/r8152.c
-@@ -10068,7 +10068,7 @@ static struct usb_driver rtl8152_driver
- 	.disable_hub_initiated_lpm = 1,
- };
- 
--static int rtl8152_cfgselector_probe(struct usb_device *udev)
-+static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev)
- {
- 	struct usb_host_config *c;
- 	int i, num_configs;
-@@ -10095,19 +10095,13 @@ static int rtl8152_cfgselector_probe(str
- 	if (i == num_configs)
- 		return -ENODEV;
- 
--	if (usb_set_configuration(udev, c->desc.bConfigurationValue)) {
--		dev_err(&udev->dev, "Failed to set configuration %d\n",
--			c->desc.bConfigurationValue);
--		return -ENODEV;
--	}
--
--	return 0;
-+	return c->desc.bConfigurationValue;
- }
- 
- static struct usb_device_driver rtl8152_cfgselector_driver = {
--	.name =		MODULENAME "-cfgselector",
--	.probe =	rtl8152_cfgselector_probe,
--	.id_table =	rtl8152_table,
-+	.name =	MODULENAME "-cfgselector",
-+	.choose_configuration = rtl8152_cfgselector_choose_configuration,
-+	.id_table = rtl8152_table,
- 	.generic_subclass = 1,
- 	.supports_autosuspend = 1,
- };
diff --git a/target/linux/generic/backport-6.1/795-v6.8-21-usb-core-Allow-subclassed-USB-drivers-to-override-us.patch b/target/linux/generic/backport-6.1/795-v6.8-21-usb-core-Allow-subclassed-USB-drivers-to-override-us.patch
deleted file mode 100644
index 46db091a100..00000000000
--- a/target/linux/generic/backport-6.1/795-v6.8-21-usb-core-Allow-subclassed-USB-drivers-to-override-us.patch
+++ /dev/null
@@ -1,76 +0,0 @@
-From a87b8e3be926af0fc3b9b1af42b1127bd1ff077c Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Fri, 1 Dec 2023 10:29:51 -0800
-Subject: [PATCH] usb: core: Allow subclassed USB drivers to override
- usb_choose_configuration()
-
-For some USB devices we might want to do something different for
-usb_choose_configuration(). One example here is the r8152 driver where
-we want to end up using the vendor driver with the preferred
-interface.
-
-The r8152 driver tried to make things work by implementing a USB
-generic_subclass driver and then overriding the normal config
-selection after it happened. This is less than ideal and also caused
-breakage if someone deauthorized and re-authorized the USB device
-because the USB core ended up going back to it's default logic for
-choosing the best config. I made an attempt to fix this [1] but it was
-a bit ugly.
-
-Let's do this better and allow USB generic_subclass drivers to
-override usb_choose_configuration().
-
-[1] https://lore.kernel.org/r/20231130154337.1.Ie00e07f07f87149c9ce0b27ae4e26991d307e14b@changeid
-
-Suggested-by: Alan Stern <stern@rowland.harvard.edu>
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Reviewed-by: Alan Stern <stern@rowland.harvard.edu>
-Link: https://lore.kernel.org/r/20231201102946.v2.2.Iade5fa31997f1a0ca3e1dec0591633b02471df12@changeid
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/core/generic.c | 7 +++++++
- include/linux/usb.h        | 6 ++++++
- 2 files changed, 13 insertions(+)
-
---- a/drivers/usb/core/generic.c
-+++ b/drivers/usb/core/generic.c
-@@ -59,10 +59,17 @@ int usb_choose_configuration(struct usb_
- 	int num_configs;
- 	int insufficient_power = 0;
- 	struct usb_host_config *c, *best;
-+	struct usb_device_driver *udriver = to_usb_device_driver(udev->dev.driver);
- 
- 	if (usb_device_is_owned(udev))
- 		return 0;
- 
-+	if (udriver->choose_configuration) {
-+		i = udriver->choose_configuration(udev);
-+		if (i >= 0)
-+			return i;
-+	}
-+
- 	best = NULL;
- 	c = udev->config;
- 	num_configs = udev->descriptor.bNumConfigurations;
---- a/include/linux/usb.h
-+++ b/include/linux/usb.h
-@@ -1234,6 +1234,9 @@ struct usb_driver {
-  *	module is being unloaded.
-  * @suspend: Called when the device is going to be suspended by the system.
-  * @resume: Called when the device is being resumed by the system.
-+ * @choose_configuration: If non-NULL, called instead of the default
-+ *	usb_choose_configuration(). If this returns an error then we'll go
-+ *	on to call the normal usb_choose_configuration().
-  * @dev_groups: Attributes attached to the device that will be created once it
-  *	is bound to the driver.
-  * @drvwrap: Driver-model core structure wrapper.
-@@ -1257,6 +1260,9 @@ struct usb_device_driver {
- 
- 	int (*suspend) (struct usb_device *udev, pm_message_t message);
- 	int (*resume) (struct usb_device *udev, pm_message_t message);
-+
-+	int (*choose_configuration) (struct usb_device *udev);
-+
- 	const struct attribute_group **dev_groups;
- 	struct usbdrv_wrap drvwrap;
- 	const struct usb_device_id *id_table;
diff --git a/target/linux/generic/backport-6.1/795-v6.8-22-usb-core-Fix-crash-w-usb_choose_configuration-if-no-.patch b/target/linux/generic/backport-6.1/795-v6.8-22-usb-core-Fix-crash-w-usb_choose_configuration-if-no-.patch
deleted file mode 100644
index abfdcef37e1..00000000000
--- a/target/linux/generic/backport-6.1/795-v6.8-22-usb-core-Fix-crash-w-usb_choose_configuration-if-no-.patch
+++ /dev/null
@@ -1,55 +0,0 @@
-From 44995e6f07028f798efd0c3c11a1efc78330f600 Mon Sep 17 00:00:00 2001
-From: Douglas Anderson <dianders@chromium.org>
-Date: Mon, 11 Dec 2023 07:32:41 -0800
-Subject: [PATCH] usb: core: Fix crash w/ usb_choose_configuration() if no
- driver
-
-It's possible that usb_choose_configuration() can get called when a
-USB device has no driver. In this case the recent commit a87b8e3be926
-("usb: core: Allow subclassed USB drivers to override
-usb_choose_configuration()") can cause a crash since it dereferenced
-the driver structure without checking for NULL. Let's add a check.
-
-A USB device with no driver is an anomaly, so make
-usb_choose_configuration() return immediately if there is no driver.
-
-This was seen in the real world when usbguard got ahold of a r8152
-device at the wrong time. It can also be simulated via this on a
-computer with one r8152-based USB Ethernet adapter:
-  cd /sys/bus/usb/drivers/r8152-cfgselector
-  to_unbind="$(ls -d *-*)"
-  real_dir="$(readlink -f "${to_unbind}")"
-  echo "${to_unbind}" > unbind
-  cd "${real_dir}"
-  echo 0 > authorized
-  echo 1 > authorized
-
-Fixes: a87b8e3be926 ("usb: core: Allow subclassed USB drivers to override usb_choose_configuration()")
-Reviewed-by: Alan Stern <stern@rowland.harvard.edu>
-Signed-off-by: Douglas Anderson <dianders@chromium.org>
-Link: https://lore.kernel.org/r/20231211073237.v3.1.If27eb3bf7812f91ab83810f232292f032f4203e0@changeid
-Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
----
- drivers/usb/core/generic.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
---- a/drivers/usb/core/generic.c
-+++ b/drivers/usb/core/generic.c
-@@ -59,7 +59,16 @@ int usb_choose_configuration(struct usb_
- 	int num_configs;
- 	int insufficient_power = 0;
- 	struct usb_host_config *c, *best;
--	struct usb_device_driver *udriver = to_usb_device_driver(udev->dev.driver);
-+	struct usb_device_driver *udriver;
-+
-+	/*
-+	 * If a USB device (not an interface) doesn't have a driver then the
-+	 * kernel has no business trying to select or install a configuration
-+	 * for it.
-+	 */
-+	if (!udev->dev.driver)
-+		return -1;
-+	udriver = to_usb_device_driver(udev->dev.driver);
- 
- 	if (usb_device_is_owned(udev))
- 		return 0;
diff --git a/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch b/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch
index 4bd84223ef3..409fe9c7a19 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-02-net-dsa-qca8k-add-LEDs-basic-support.patch
@@ -71,7 +71,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  static void
  qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
-@@ -1840,6 +1841,10 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1851,6 +1852,10 @@ qca8k_setup(struct dsa_switch *ds)
  	if (ret)
  		return ret;
  
diff --git a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
index d33fc72dd1e..0d2c0bcd83f 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-05-net-phy-Add-a-binding-for-PHY-LEDs.patch
@@ -48,7 +48,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #include <linux/netdevice.h>
  #include <linux/phy.h>
  #include <linux/phy_led_triggers.h>
-@@ -644,6 +646,7 @@ struct phy_device *phy_device_create(str
+@@ -642,6 +644,7 @@ struct phy_device *phy_device_create(str
  	device_initialize(&mdiodev->dev);
  
  	dev->state = PHY_DOWN;
@@ -56,7 +56,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	mutex_init(&dev->lock);
  	INIT_DELAYED_WORK(&dev->state_queue, phy_state_machine);
-@@ -2931,6 +2934,74 @@ static bool phy_drv_supports_irq(struct
+@@ -3035,6 +3038,74 @@ static bool phy_drv_supports_irq(struct
  	return phydrv->config_intr && phydrv->handle_interrupt;
  }
  
@@ -131,7 +131,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /**
   * fwnode_mdio_find_device - Given a fwnode, find the mdio_device
   * @fwnode: pointer to the mdio_device's fwnode
-@@ -3109,6 +3180,11 @@ static int phy_probe(struct device *dev)
+@@ -3213,6 +3284,11 @@ static int phy_probe(struct device *dev)
  	/* Set the state to READY by default */
  	phydev->state = PHY_READY;
  
@@ -153,7 +153,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  #include <linux/linkmode.h>
  #include <linux/netlink.h>
  #include <linux/mdio.h>
-@@ -602,6 +603,7 @@ struct macsec_ops;
+@@ -606,6 +607,7 @@ struct macsec_ops;
   * @phy_num_led_triggers: Number of triggers in @phy_led_triggers
   * @led_link_trigger: LED trigger for link up/down
   * @last_triggered: last LED trigger for link speed
@@ -161,7 +161,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
   * @master_slave_set: User requested master/slave configuration
   * @master_slave_get: Current master/slave advertisement
   * @master_slave_state: Current master/slave configuration
-@@ -694,6 +696,7 @@ struct phy_device {
+@@ -698,6 +700,7 @@ struct phy_device {
  
  	struct phy_led_trigger *led_link_trigger;
  #endif
@@ -169,7 +169,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  
  	/*
  	 * Interrupt number for this PHY
-@@ -768,6 +771,19 @@ struct phy_tdr_config {
+@@ -772,6 +775,19 @@ struct phy_tdr_config {
  #define PHY_PAIR_ALL -1
  
  /**
diff --git a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index c1678ce2ea3..4873c40a776 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-06-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -20,7 +20,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2934,11 +2934,18 @@ static bool phy_drv_supports_irq(struct
+@@ -3038,11 +3038,18 @@ static bool phy_drv_supports_irq(struct
  	return phydrv->config_intr && phydrv->handle_interrupt;
  }
  
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  }
  
  static int of_phy_led(struct phy_device *phydev,
-@@ -2955,12 +2962,14 @@ static int of_phy_led(struct phy_device
+@@ -3059,12 +3066,14 @@ static int of_phy_led(struct phy_device
  		return -ENOMEM;
  
  	cdev = &phyled->led_cdev;
@@ -59,7 +59,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -774,15 +774,19 @@ struct phy_tdr_config {
+@@ -778,15 +778,19 @@ struct phy_tdr_config {
   * struct phy_led: An LED driven by the PHY
   *
   * @list: List of LEDs
@@ -79,7 +79,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  /**
   * struct phy_driver - Driver structure for a particular PHY type
   *
-@@ -997,6 +1001,15 @@ struct phy_driver {
+@@ -1001,6 +1005,15 @@ struct phy_driver {
  	int (*get_sqi)(struct phy_device *dev);
  	/** @get_sqi_max: Get the maximum signal quality indication */
  	int (*get_sqi_max)(struct phy_device *dev);
diff --git a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index f234b2bff13..00bdcc54689 100644
--- a/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/801-v6.4-08-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -18,7 +18,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2948,6 +2948,22 @@ static int phy_led_set_brightness(struct
+@@ -3052,6 +3052,22 @@ static int phy_led_set_brightness(struct
  	return err;
  }
  
@@ -41,7 +41,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int of_phy_led(struct phy_device *phydev,
  		      struct device_node *led)
  {
-@@ -2970,6 +2986,8 @@ static int of_phy_led(struct phy_device
+@@ -3074,6 +3090,8 @@ static int of_phy_led(struct phy_device
  
  	if (phydev->drv->led_brightness_set)
  		cdev->brightness_set_blocking = phy_led_set_brightness;
@@ -52,7 +52,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -1010,6 +1010,18 @@ struct phy_driver {
+@@ -1014,6 +1014,18 @@ struct phy_driver {
  	 */
  	int (*led_brightness_set)(struct phy_device *dev,
  				  u8 index, enum led_brightness value);
diff --git a/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch b/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
index f64bbc77827..00773ab0f63 100644
--- a/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
+++ b/target/linux/generic/backport-6.1/815-v6.7-3-leds-turris-omnia-Support-HW-controlled-mode-via-pri.patch
@@ -49,7 +49,7 @@ Signed-off-by: Lee Jones <lee@kernel.org>
 
 --- a/drivers/leds/Kconfig
 +++ b/drivers/leds/Kconfig
-@@ -163,6 +163,7 @@ config LEDS_TURRIS_OMNIA
+@@ -164,6 +164,7 @@ config LEDS_TURRIS_OMNIA
  	depends on I2C
  	depends on MACH_ARMADA_38X || COMPILE_TEST
  	depends on OF
diff --git a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
index 1de086417b6..3b68403690c 100644
--- a/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
+++ b/target/linux/generic/backport-6.1/820-v6.4-net-phy-fix-circular-LEDS_CLASS-dependencies.patch
@@ -53,7 +53,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	tristate "MDIO Bus/PHY emulation with fixed speed/link PHYs"
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -3210,7 +3210,8 @@ static int phy_probe(struct device *dev)
+@@ -3314,7 +3314,8 @@ static int phy_probe(struct device *dev)
  	/* Get the LEDs from the device tree, and instantiate standard
  	 * LEDs for them.
  	 */
diff --git a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
index d6081d0e637..622bb9e94a9 100644
--- a/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
+++ b/target/linux/generic/backport-6.1/821-v6.4-net-phy-Fix-reading-LED-reg-property.patch
@@ -18,7 +18,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2971,6 +2971,7 @@ static int of_phy_led(struct phy_device
+@@ -3075,6 +3075,7 @@ static int of_phy_led(struct phy_device
  	struct led_init_data init_data = {};
  	struct led_classdev *cdev;
  	struct phy_led *phyled;
@@ -26,7 +26,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	int err;
  
  	phyled = devm_kzalloc(dev, sizeof(*phyled), GFP_KERNEL);
-@@ -2980,10 +2981,13 @@ static int of_phy_led(struct phy_device
+@@ -3084,10 +3085,13 @@ static int of_phy_led(struct phy_device
  	cdev = &phyled->led_cdev;
  	phyled->phydev = phydev;
  
diff --git a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
index 8f076be640c..80197e963b8 100644
--- a/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
+++ b/target/linux/generic/backport-6.1/822-v6.4-net-phy-Manual-remove-LEDs-to-ensure-correct-orderin.patch
@@ -22,7 +22,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2964,6 +2964,15 @@ static int phy_led_blink_set(struct led_
+@@ -3068,6 +3068,15 @@ static int phy_led_blink_set(struct led_
  	return err;
  }
  
@@ -38,7 +38,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  static int of_phy_led(struct phy_device *phydev,
  		      struct device_node *led)
  {
-@@ -2997,7 +3006,7 @@ static int of_phy_led(struct phy_device
+@@ -3101,7 +3110,7 @@ static int of_phy_led(struct phy_device
  	init_data.fwnode = of_fwnode_handle(led);
  	init_data.devname_mandatory = true;
  
@@ -47,7 +47,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  	if (err)
  		return err;
  
-@@ -3026,6 +3035,7 @@ static int of_phy_leds(struct phy_device
+@@ -3130,6 +3139,7 @@ static int of_phy_leds(struct phy_device
  		err = of_phy_led(phydev, led);
  		if (err) {
  			of_node_put(led);
@@ -55,7 +55,7 @@ Signed-off-by: David S. Miller <davem@davemloft.net>
  			return err;
  		}
  	}
-@@ -3231,6 +3241,9 @@ static int phy_remove(struct device *dev
+@@ -3335,6 +3345,9 @@ static int phy_remove(struct device *dev
  
  	cancel_delayed_work_sync(&phydev->state_queue);
  
diff --git a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
index daa970884e6..505513a53fe 100644
--- a/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
+++ b/target/linux/generic/backport-6.1/826-v6.6-02-net-phy-phy_device-Call-into-the-PHY-driver-to-set-L.patch
@@ -23,7 +23,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -2964,6 +2964,61 @@ static int phy_led_blink_set(struct led_
+@@ -3068,6 +3068,61 @@ static int phy_led_blink_set(struct led_
  	return err;
  }
  
@@ -85,7 +85,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  static void phy_leds_unregister(struct phy_device *phydev)
  {
  	struct phy_led *phyled;
-@@ -3001,6 +3056,19 @@ static int of_phy_led(struct phy_device
+@@ -3105,6 +3160,19 @@ static int of_phy_led(struct phy_device
  		cdev->brightness_set_blocking = phy_led_set_brightness;
  	if (phydev->drv->led_blink_set)
  		cdev->blink_set = phy_led_blink_set;
@@ -107,7 +107,7 @@ Signed-off-by: Jakub Kicinski <kuba@kernel.org>
  	init_data.fwnode = of_fwnode_handle(led);
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -1022,6 +1022,39 @@ struct phy_driver {
+@@ -1026,6 +1026,39 @@ struct phy_driver {
  	int (*led_blink_set)(struct phy_device *dev, u8 index,
  			     unsigned long *delay_on,
  			     unsigned long *delay_off);
diff --git a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
index 15af039a16f..671556fbaa8 100644
--- a/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
+++ b/target/linux/generic/backport-6.1/828-v6.4-0003-of-Rename-of_modalias_node.patch
@@ -148,7 +148,7 @@ Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
   * of_find_node_by_phandle - Find a node given a phandle
 --- a/drivers/spi/spi.c
 +++ b/drivers/spi/spi.c
-@@ -2326,8 +2326,8 @@ of_register_spi_device(struct spi_contro
+@@ -2330,8 +2330,8 @@ of_register_spi_device(struct spi_contro
  	}
  
  	/* Select device driver */
diff --git a/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch b/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch
new file mode 100644
index 00000000000..1c8e014a1ae
--- /dev/null
+++ b/target/linux/generic/backport-6.1/834-v6.8-leds-trigger-netdev-Extend-speeds-up-to-10G.patch
@@ -0,0 +1,111 @@
+From bc8e1da69a68d9871773b657d18400a7941cbdef Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 28 Nov 2023 04:00:10 +0000
+Subject: [PATCH] leds: trigger: netdev: Extend speeds up to 10G
+
+Add 2.5G, 5G and 10G as available speeds to the netdev LED trigger.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/99e7d3304c6bba7f4863a4a80764a869855f2085.1701143925.git.daniel@makrotopia.org
+Signed-off-by: Lee Jones <lee@kernel.org>
+---
+ drivers/leds/trigger/ledtrig-netdev.c | 32 ++++++++++++++++++++++++++-
+ include/linux/leds.h                  |  3 +++
+ 2 files changed, 34 insertions(+), 1 deletion(-)
+
+--- a/drivers/leds/trigger/ledtrig-netdev.c
++++ b/drivers/leds/trigger/ledtrig-netdev.c
+@@ -99,6 +99,18 @@ static void set_baseline_state(struct le
+ 		    trigger_data->link_speed == SPEED_1000)
+ 			blink_on = true;
+ 
++		if (test_bit(TRIGGER_NETDEV_LINK_2500, &trigger_data->mode) &&
++		    trigger_data->link_speed == SPEED_2500)
++			blink_on = true;
++
++		if (test_bit(TRIGGER_NETDEV_LINK_5000, &trigger_data->mode) &&
++		    trigger_data->link_speed == SPEED_5000)
++			blink_on = true;
++
++		if (test_bit(TRIGGER_NETDEV_LINK_10000, &trigger_data->mode) &&
++		    trigger_data->link_speed == SPEED_10000)
++			blink_on = true;
++
+ 		if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &trigger_data->mode) &&
+ 		    trigger_data->duplex == DUPLEX_HALF)
+ 			blink_on = true;
+@@ -286,6 +298,9 @@ static ssize_t netdev_led_attr_show(stru
+ 	case TRIGGER_NETDEV_LINK_10:
+ 	case TRIGGER_NETDEV_LINK_100:
+ 	case TRIGGER_NETDEV_LINK_1000:
++	case TRIGGER_NETDEV_LINK_2500:
++	case TRIGGER_NETDEV_LINK_5000:
++	case TRIGGER_NETDEV_LINK_10000:
+ 	case TRIGGER_NETDEV_HALF_DUPLEX:
+ 	case TRIGGER_NETDEV_FULL_DUPLEX:
+ 	case TRIGGER_NETDEV_TX:
+@@ -316,6 +331,9 @@ static ssize_t netdev_led_attr_store(str
+ 	case TRIGGER_NETDEV_LINK_10:
+ 	case TRIGGER_NETDEV_LINK_100:
+ 	case TRIGGER_NETDEV_LINK_1000:
++	case TRIGGER_NETDEV_LINK_2500:
++	case TRIGGER_NETDEV_LINK_5000:
++	case TRIGGER_NETDEV_LINK_10000:
+ 	case TRIGGER_NETDEV_HALF_DUPLEX:
+ 	case TRIGGER_NETDEV_FULL_DUPLEX:
+ 	case TRIGGER_NETDEV_TX:
+@@ -334,7 +352,10 @@ static ssize_t netdev_led_attr_store(str
+ 	if (test_bit(TRIGGER_NETDEV_LINK, &mode) &&
+ 	    (test_bit(TRIGGER_NETDEV_LINK_10, &mode) ||
+ 	     test_bit(TRIGGER_NETDEV_LINK_100, &mode) ||
+-	     test_bit(TRIGGER_NETDEV_LINK_1000, &mode)))
++	     test_bit(TRIGGER_NETDEV_LINK_1000, &mode) ||
++	     test_bit(TRIGGER_NETDEV_LINK_2500, &mode) ||
++	     test_bit(TRIGGER_NETDEV_LINK_5000, &mode) ||
++	     test_bit(TRIGGER_NETDEV_LINK_10000, &mode)))
+ 		return -EINVAL;
+ 
+ 	cancel_delayed_work_sync(&trigger_data->work);
+@@ -364,6 +385,9 @@ DEFINE_NETDEV_TRIGGER(link, TRIGGER_NETD
+ DEFINE_NETDEV_TRIGGER(link_10, TRIGGER_NETDEV_LINK_10);
+ DEFINE_NETDEV_TRIGGER(link_100, TRIGGER_NETDEV_LINK_100);
+ DEFINE_NETDEV_TRIGGER(link_1000, TRIGGER_NETDEV_LINK_1000);
++DEFINE_NETDEV_TRIGGER(link_2500, TRIGGER_NETDEV_LINK_2500);
++DEFINE_NETDEV_TRIGGER(link_5000, TRIGGER_NETDEV_LINK_5000);
++DEFINE_NETDEV_TRIGGER(link_10000, TRIGGER_NETDEV_LINK_10000);
+ DEFINE_NETDEV_TRIGGER(half_duplex, TRIGGER_NETDEV_HALF_DUPLEX);
+ DEFINE_NETDEV_TRIGGER(full_duplex, TRIGGER_NETDEV_FULL_DUPLEX);
+ DEFINE_NETDEV_TRIGGER(tx, TRIGGER_NETDEV_TX);
+@@ -422,6 +446,9 @@ static struct attribute *netdev_trig_att
+ 	&dev_attr_link_10.attr,
+ 	&dev_attr_link_100.attr,
+ 	&dev_attr_link_1000.attr,
++	&dev_attr_link_2500.attr,
++	&dev_attr_link_5000.attr,
++	&dev_attr_link_10000.attr,
+ 	&dev_attr_full_duplex.attr,
+ 	&dev_attr_half_duplex.attr,
+ 	&dev_attr_rx.attr,
+@@ -519,6 +546,9 @@ static void netdev_trig_work(struct work
+ 			 test_bit(TRIGGER_NETDEV_LINK_10, &trigger_data->mode) ||
+ 			 test_bit(TRIGGER_NETDEV_LINK_100, &trigger_data->mode) ||
+ 			 test_bit(TRIGGER_NETDEV_LINK_1000, &trigger_data->mode) ||
++			 test_bit(TRIGGER_NETDEV_LINK_2500, &trigger_data->mode) ||
++			 test_bit(TRIGGER_NETDEV_LINK_5000, &trigger_data->mode) ||
++			 test_bit(TRIGGER_NETDEV_LINK_10000, &trigger_data->mode) ||
+ 			 test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &trigger_data->mode) ||
+ 			 test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &trigger_data->mode);
+ 		interval = jiffies_to_msecs(
+--- a/include/linux/leds.h
++++ b/include/linux/leds.h
+@@ -533,6 +533,9 @@ enum led_trigger_netdev_modes {
+ 	TRIGGER_NETDEV_LINK_10,
+ 	TRIGGER_NETDEV_LINK_100,
+ 	TRIGGER_NETDEV_LINK_1000,
++	TRIGGER_NETDEV_LINK_2500,
++	TRIGGER_NETDEV_LINK_5000,
++	TRIGGER_NETDEV_LINK_10000,
+ 	TRIGGER_NETDEV_HALF_DUPLEX,
+ 	TRIGGER_NETDEV_FULL_DUPLEX,
+ 	TRIGGER_NETDEV_TX,
diff --git a/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
new file mode 100644
index 00000000000..0182e6d1a20
--- /dev/null
+++ b/target/linux/generic/backport-6.1/835-v6.9-net-phy-add-support-for-PHY-LEDs-polarity-modes.patch
@@ -0,0 +1,98 @@
+From 7ae215ee7bb855f13c80565470fc7f67db4ba82f Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Thu, 25 Jan 2024 21:36:59 +0100
+Subject: [PATCH 3/5] net: phy: add support for PHY LEDs polarity modes
+
+Add support for PHY LEDs polarity modes. Some PHY require LED to be set
+to active low to be turned ON. Adds support for this by declaring
+active-low property in DT.
+
+PHY driver needs to declare .led_polarity_set() to configure LED
+polarity modes. Function will pass the index with the LED index and a
+bitmap with all the required modes to set.
+
+Current supported modes are:
+- active-low with the flag PHY_LED_ACTIVE_LOW. LED is set to active-low
+  to turn it ON.
+- inactive-high-impedance with the flag PHY_LED_INACTIVE_HIGH_IMPEDANCE.
+  LED is set to high impedance to turn it OFF.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240125203702.4552-4-ansuelsmth@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/net/phy/phy_device.c | 16 ++++++++++++++++
+ include/linux/phy.h          | 22 ++++++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+
+--- a/drivers/net/phy/phy_device.c
++++ b/drivers/net/phy/phy_device.c
+@@ -3138,6 +3138,7 @@ static int of_phy_led(struct phy_device
+ 	struct device *dev = &phydev->mdio.dev;
+ 	struct led_init_data init_data = {};
+ 	struct led_classdev *cdev;
++	unsigned long modes = 0;
+ 	struct phy_led *phyled;
+ 	u32 index;
+ 	int err;
+@@ -3155,6 +3156,21 @@ static int of_phy_led(struct phy_device
+ 	if (index > U8_MAX)
+ 		return -EINVAL;
+ 
++	if (of_property_read_bool(led, "active-low"))
++		set_bit(PHY_LED_ACTIVE_LOW, &modes);
++	if (of_property_read_bool(led, "inactive-high-impedance"))
++		set_bit(PHY_LED_INACTIVE_HIGH_IMPEDANCE, &modes);
++
++	if (modes) {
++		/* Return error if asked to set polarity modes but not supported */
++		if (!phydev->drv->led_polarity_set)
++			return -EINVAL;
++
++		err = phydev->drv->led_polarity_set(phydev, index, modes);
++		if (err)
++			return err;
++	}
++
+ 	phyled->index = index;
+ 	if (phydev->drv->led_brightness_set)
+ 		cdev->brightness_set_blocking = phy_led_set_brightness;
+--- a/include/linux/phy.h
++++ b/include/linux/phy.h
+@@ -791,6 +791,15 @@ struct phy_led {
+ 
+ #define to_phy_led(d) container_of(d, struct phy_led, led_cdev)
+ 
++/* Modes for PHY LED configuration */
++enum phy_led_modes {
++	PHY_LED_ACTIVE_LOW = 0,
++	PHY_LED_INACTIVE_HIGH_IMPEDANCE = 1,
++
++	/* keep it last */
++	__PHY_LED_MODES_NUM,
++};
++
+ /**
+  * struct phy_driver - Driver structure for a particular PHY type
+  *
+@@ -1059,6 +1068,19 @@ struct phy_driver {
+ 	int (*led_hw_control_get)(struct phy_device *dev, u8 index,
+ 				  unsigned long *rules);
+ 
++	/**
++	 * @led_polarity_set: Set the LED polarity modes
++	 * @dev: PHY device which has the LED
++	 * @index: Which LED of the PHY device
++	 * @modes: bitmap of LED polarity modes
++	 *
++	 * Configure LED with all the required polarity modes in @modes
++	 * to make it correctly turn ON or OFF.
++	 *
++	 * Returns 0, or an error code.
++	 */
++	int (*led_polarity_set)(struct phy_device *dev, int index,
++				unsigned long modes);
+ };
+ #define to_phy_driver(d) container_of(to_mdio_common_driver(d),		\
+ 				      struct phy_driver, mdiodrv)
diff --git a/target/linux/generic/backport-6.1/836-v6.7-leds-trigger-netdev-fix-RTNL-handling-to-prevent-pot.patch b/target/linux/generic/backport-6.1/836-v6.7-leds-trigger-netdev-fix-RTNL-handling-to-prevent-pot.patch
new file mode 100644
index 00000000000..cbb91720323
--- /dev/null
+++ b/target/linux/generic/backport-6.1/836-v6.7-leds-trigger-netdev-fix-RTNL-handling-to-prevent-pot.patch
@@ -0,0 +1,170 @@
+From fe2b1226656afae56702d1d84c6900f6b67df297 Mon Sep 17 00:00:00 2001
+From: Heiner Kallweit <hkallweit1@gmail.com>
+Date: Fri, 1 Dec 2023 11:23:22 +0100
+Subject: [PATCH] leds: trigger: netdev: fix RTNL handling to prevent potential
+ deadlock
+
+When working on LED support for r8169 I got the following lockdep
+warning. Easiest way to prevent this scenario seems to be to take
+the RTNL lock before the trigger_data lock in set_device_name().
+
+======================================================
+WARNING: possible circular locking dependency detected
+6.7.0-rc2-next-20231124+ #2 Not tainted
+------------------------------------------------------
+bash/383 is trying to acquire lock:
+ffff888103aa1c68 (&trigger_data->lock){+.+.}-{3:3}, at: netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+
+but task is already holding lock:
+ffffffff8cddf808 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x12/0x20
+
+which lock already depends on the new lock.
+
+the existing dependency chain (in reverse order) is:
+
+-> #1 (rtnl_mutex){+.+.}-{3:3}:
+       __mutex_lock+0x9b/0xb50
+       mutex_lock_nested+0x16/0x20
+       rtnl_lock+0x12/0x20
+       set_device_name+0xa9/0x120 [ledtrig_netdev]
+       netdev_trig_activate+0x1a1/0x230 [ledtrig_netdev]
+       led_trigger_set+0x172/0x2c0
+       led_trigger_write+0xf1/0x140
+       sysfs_kf_bin_write+0x5d/0x80
+       kernfs_fop_write_iter+0x15d/0x210
+       vfs_write+0x1f0/0x510
+       ksys_write+0x6c/0xf0
+       __x64_sys_write+0x14/0x20
+       do_syscall_64+0x3f/0xf0
+       entry_SYSCALL_64_after_hwframe+0x6c/0x74
+
+-> #0 (&trigger_data->lock){+.+.}-{3:3}:
+       __lock_acquire+0x1459/0x25a0
+       lock_acquire+0xc8/0x2d0
+       __mutex_lock+0x9b/0xb50
+       mutex_lock_nested+0x16/0x20
+       netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+       call_netdevice_register_net_notifiers+0x5a/0x100
+       register_netdevice_notifier+0x85/0x120
+       netdev_trig_activate+0x1d4/0x230 [ledtrig_netdev]
+       led_trigger_set+0x172/0x2c0
+       led_trigger_write+0xf1/0x140
+       sysfs_kf_bin_write+0x5d/0x80
+       kernfs_fop_write_iter+0x15d/0x210
+       vfs_write+0x1f0/0x510
+       ksys_write+0x6c/0xf0
+       __x64_sys_write+0x14/0x20
+       do_syscall_64+0x3f/0xf0
+       entry_SYSCALL_64_after_hwframe+0x6c/0x74
+
+other info that might help us debug this:
+
+ Possible unsafe locking scenario:
+
+       CPU0                    CPU1
+       ----                    ----
+  lock(rtnl_mutex);
+                               lock(&trigger_data->lock);
+                               lock(rtnl_mutex);
+  lock(&trigger_data->lock);
+
+ *** DEADLOCK ***
+
+8 locks held by bash/383:
+ #0: ffff888103ff33f0 (sb_writers#3){.+.+}-{0:0}, at: ksys_write+0x6c/0xf0
+ #1: ffff888103aa1e88 (&of->mutex){+.+.}-{3:3}, at: kernfs_fop_write_iter+0x114/0x210
+ #2: ffff8881036f1890 (kn->active#82){.+.+}-{0:0}, at: kernfs_fop_write_iter+0x11d/0x210
+ #3: ffff888108e2c358 (&led_cdev->led_access){+.+.}-{3:3}, at: led_trigger_write+0x30/0x140
+ #4: ffffffff8cdd9e10 (triggers_list_lock){++++}-{3:3}, at: led_trigger_write+0x75/0x140
+ #5: ffff888108e2c270 (&led_cdev->trigger_lock){++++}-{3:3}, at: led_trigger_write+0xe3/0x140
+ #6: ffffffff8cdde3d0 (pernet_ops_rwsem){++++}-{3:3}, at: register_netdevice_notifier+0x1c/0x120
+ #7: ffffffff8cddf808 (rtnl_mutex){+.+.}-{3:3}, at: rtnl_lock+0x12/0x20
+
+stack backtrace:
+CPU: 0 PID: 383 Comm: bash Not tainted 6.7.0-rc2-next-20231124+ #2
+Hardware name: Default string Default string/Default string, BIOS ADLN.M6.SODIMM.ZB.CY.015 08/08/2023
+Call Trace:
+ <TASK>
+ dump_stack_lvl+0x5c/0xd0
+ dump_stack+0x10/0x20
+ print_circular_bug+0x2dd/0x410
+ check_noncircular+0x131/0x150
+ __lock_acquire+0x1459/0x25a0
+ lock_acquire+0xc8/0x2d0
+ ? netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ __mutex_lock+0x9b/0xb50
+ ? netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ ? __this_cpu_preempt_check+0x13/0x20
+ ? netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ ? __cancel_work_timer+0x11c/0x1b0
+ ? __mutex_lock+0x123/0xb50
+ mutex_lock_nested+0x16/0x20
+ ? mutex_lock_nested+0x16/0x20
+ netdev_trig_notify+0xec/0x190 [ledtrig_netdev]
+ call_netdevice_register_net_notifiers+0x5a/0x100
+ register_netdevice_notifier+0x85/0x120
+ netdev_trig_activate+0x1d4/0x230 [ledtrig_netdev]
+ led_trigger_set+0x172/0x2c0
+ ? preempt_count_add+0x49/0xc0
+ led_trigger_write+0xf1/0x140
+ sysfs_kf_bin_write+0x5d/0x80
+ kernfs_fop_write_iter+0x15d/0x210
+ vfs_write+0x1f0/0x510
+ ksys_write+0x6c/0xf0
+ __x64_sys_write+0x14/0x20
+ do_syscall_64+0x3f/0xf0
+ entry_SYSCALL_64_after_hwframe+0x6c/0x74
+RIP: 0033:0x7f269055d034
+Code: c7 00 16 00 00 00 b8 ff ff ff ff c3 66 2e 0f 1f 84 00 00 00 00 00 f3 0f 1e fa 80 3d 35 c3 0d 00 00 74 13 b8 01 00 00 00 0f 05 <48> 3d 00 f0 ff ff 77 54 c3 0f 1f 00 48 83 ec 28 48 89 54 24 18 48
+RSP: 002b:00007ffddb7ef748 EFLAGS: 00000202 ORIG_RAX: 0000000000000001
+RAX: ffffffffffffffda RBX: 0000000000000007 RCX: 00007f269055d034
+RDX: 0000000000000007 RSI: 000055bf5f4af3c0 RDI: 0000000000000001
+RBP: 000055bf5f4af3c0 R08: 0000000000000073 R09: 0000000000000001
+R10: 0000000000000000 R11: 0000000000000202 R12: 0000000000000007
+R13: 00007f26906325c0 R14: 00007f269062ff20 R15: 0000000000000000
+ </TASK>
+
+Fixes: d5e01266e7f5 ("leds: trigger: netdev: add additional specific link speed mode")
+Cc: stable@vger.kernel.org
+Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Acked-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/fb5c8294-2a10-4bf5-8f10-3d2b77d2757e@gmail.com
+Signed-off-by: Jakub Kicinski <kuba@kernel.org>
+---
+ drivers/leds/trigger/ledtrig-netdev.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/leds/trigger/ledtrig-netdev.c
++++ b/drivers/leds/trigger/ledtrig-netdev.c
+@@ -235,6 +235,11 @@ static int set_device_name(struct led_ne
+ {
+ 	cancel_delayed_work_sync(&trigger_data->work);
+ 
++	/*
++	 * Take RTNL lock before trigger_data lock to prevent potential
++	 * deadlock with netdev notifier registration.
++	 */
++	rtnl_lock();
+ 	mutex_lock(&trigger_data->lock);
+ 
+ 	if (trigger_data->net_dev) {
+@@ -254,16 +259,14 @@ static int set_device_name(struct led_ne
+ 	trigger_data->carrier_link_up = false;
+ 	trigger_data->link_speed = SPEED_UNKNOWN;
+ 	trigger_data->duplex = DUPLEX_UNKNOWN;
+-	if (trigger_data->net_dev != NULL) {
+-		rtnl_lock();
++	if (trigger_data->net_dev)
+ 		get_device_state(trigger_data);
+-		rtnl_unlock();
+-	}
+ 
+ 	trigger_data->last_activity = 0;
+ 
+ 	set_baseline_state(trigger_data);
+ 	mutex_unlock(&trigger_data->lock);
++	rtnl_unlock();
+ 
+ 	return 0;
+ }
diff --git a/target/linux/generic/backport-6.1/837-v6.4-net-phy-hide-the-PHYLIB_LEDS-knob.patch b/target/linux/generic/backport-6.1/837-v6.4-net-phy-hide-the-PHYLIB_LEDS-knob.patch
new file mode 100644
index 00000000000..51b4bbbfcb1
--- /dev/null
+++ b/target/linux/generic/backport-6.1/837-v6.4-net-phy-hide-the-PHYLIB_LEDS-knob.patch
@@ -0,0 +1,43 @@
+From 9b78d919632b7149d311aaad5a977e4b48b10321 Mon Sep 17 00:00:00 2001
+From: Paolo Abeni <pabeni@redhat.com>
+Date: Wed, 26 Apr 2023 10:15:31 +0200
+Subject: [PATCH] net: phy: hide the PHYLIB_LEDS knob
+
+commit 4bb7aac70b5d ("net: phy: fix circular LEDS_CLASS dependencies")
+solved a build failure, but introduces a new config knob with a default
+'y' value: PHYLIB_LEDS.
+
+The latter is against the current new config policy. The exception
+was raised to allow the user to catch bad configurations without led
+support.
+
+Anyway the current definition of PHYLIB_LEDS does not fit the above
+goal: if LEDS_CLASS is disabled, the new config will be available
+only with PHYLIB disabled, too.
+
+Hide the mentioned config, to preserve the randconfig testing done so
+far, while respecting the mentioned policy.
+
+Suggested-by: Andrew Lunn <andrew@lunn.ch>
+Suggested-by: Arnd Bergmann <arnd@arndb.de>
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+Link: https://lore.kernel.org/r/d82489be8ed911c383c3447e9abf469995ccf39a.1682496488.git.pabeni@redhat.com
+Signed-off-by: Paolo Abeni <pabeni@redhat.com>
+---
+ drivers/net/phy/Kconfig | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -45,10 +45,8 @@ config LED_TRIGGER_PHY
+ 		for any speed known to the PHY.
+ 
+ config PHYLIB_LEDS
+-	bool "Support probing LEDs from device tree"
++	def_bool OF
+ 	depends on LEDS_CLASS=y || LEDS_CLASS=PHYLIB
+-	depends on OF
+-	default y
+ 	help
+ 	  When LED class support is enabled, phylib can automatically
+ 	  probe LED setting from device tree.
diff --git a/target/linux/generic/backport-6.1/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch b/target/linux/generic/backport-6.1/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch
new file mode 100644
index 00000000000..8d391678ffb
--- /dev/null
+++ b/target/linux/generic/backport-6.1/838-v6.9-leds-trigger-netdev-Fix-kernel-panic-on-interface-re.patch
@@ -0,0 +1,55 @@
+From 12ce20e02e532f101b725d71c52a36c5cc8ad1e6 Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Sun, 4 Feb 2024 00:54:01 +0100
+Subject: [PATCH] leds: trigger: netdev: Fix kernel panic on interface rename
+ trig notify
+
+Commit d5e01266e7f5 ("leds: trigger: netdev: add additional specific link
+speed mode") in the various changes, reworked the way to set the LINKUP
+mode in commit cee4bd16c319 ("leds: trigger: netdev: Recheck
+NETDEV_LED_MODE_LINKUP on dev rename") and moved it to a generic function.
+
+This changed the logic where, in the previous implementation the dev
+from the trigger event was used to check if the carrier was ok, but in
+the new implementation with the generic function, the dev in
+trigger_data is used instead.
+
+This is problematic and cause a possible kernel panic due to the fact
+that the dev in the trigger_data still reference the old one as the
+new one (passed from the trigger event) still has to be hold and saved
+in the trigger_data struct (done in the NETDEV_REGISTER case).
+
+On calling of get_device_state(), an invalid net_dev is used and this
+cause a kernel panic.
+
+To handle this correctly, move the call to get_device_state() after the
+new net_dev is correctly set in trigger_data (in the NETDEV_REGISTER
+case) and correctly parse the new dev.
+
+Fixes: d5e01266e7f5 ("leds: trigger: netdev: add additional specific link speed mode")
+Cc: stable@vger.kernel.org
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+Reviewed-by: Andrew Lunn <andrew@lunn.ch>
+Link: https://lore.kernel.org/r/20240203235413.1146-1-ansuelsmth@gmail.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+---
+ drivers/leds/trigger/ledtrig-netdev.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/leds/trigger/ledtrig-netdev.c
++++ b/drivers/leds/trigger/ledtrig-netdev.c
+@@ -489,12 +489,12 @@ static int netdev_trig_notify(struct not
+ 	trigger_data->duplex = DUPLEX_UNKNOWN;
+ 	switch (evt) {
+ 	case NETDEV_CHANGENAME:
+-		get_device_state(trigger_data);
+-		fallthrough;
+ 	case NETDEV_REGISTER:
+ 		dev_put(trigger_data->net_dev);
+ 		dev_hold(dev);
+ 		trigger_data->net_dev = dev;
++		if (evt == NETDEV_CHANGENAME)
++			get_device_state(trigger_data);
+ 		break;
+ 	case NETDEV_UNREGISTER:
+ 		dev_put(trigger_data->net_dev);
diff --git a/target/linux/generic/config-5.15 b/target/linux/generic/config-5.15
index bc2509ff478..5f82f0937d4 100644
--- a/target/linux/generic/config-5.15
+++ b/target/linux/generic/config-5.15
@@ -2071,7 +2071,6 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
-# CONFIG_FIT_PARTITION is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
diff --git a/target/linux/generic/config-6.1 b/target/linux/generic/config-6.1
index d11c946dbca..18ce637c805 100644
--- a/target/linux/generic/config-6.1
+++ b/target/linux/generic/config-6.1
@@ -605,6 +605,7 @@ CONFIG_BASE_SMALL=0
 # CONFIG_BAYCOM_SER_FDX is not set
 # CONFIG_BAYCOM_SER_HDX is not set
 # CONFIG_BCACHE is not set
+# CONFIG_BCM2712_MIP is not set
 # CONFIG_BCM47XX is not set
 # CONFIG_BCM54140_PHY is not set
 # CONFIG_BCM63XX is not set
@@ -729,6 +730,7 @@ CONFIG_BLK_DEV_LOOP_MIN_COUNT=8
 # CONFIG_BLK_DEV_VIA82CXXX is not set
 # CONFIG_BLK_DEV_ZONED is not set
 # CONFIG_BLK_INLINE_ENCRYPTION is not set
+# CONFIG_BLK_NVMEM is not set
 # CONFIG_BLK_SED_OPAL is not set
 # CONFIG_BLK_WBT is not set
 CONFIG_BLOCK=y
@@ -1036,6 +1038,8 @@ CONFIG_CMDLINE=""
 # CONFIG_COMMON_CLK_PWM is not set
 # CONFIG_COMMON_CLK_PXA is not set
 # CONFIG_COMMON_CLK_QCOM is not set
+# CONFIG_COMMON_CLK_RP1 is not set
+# CONFIG_COMMON_CLK_RP1_SDIO  is not set
 # CONFIG_COMMON_CLK_RS9_PCIE is not set
 # CONFIG_COMMON_CLK_SI514 is not set
 # CONFIG_COMMON_CLK_SI5341 is not set
@@ -1725,6 +1729,9 @@ CONFIG_DQL=y
 # CONFIG_DRM_RCAR_USE_LVDS is not set
 # CONFIG_DRM_RCAR_USE_MIPI_DSI is not set
 # CONFIG_DRM_ROCKCHIP is not set
+# CONFIG_DRM_RP1_DPI is not set
+# CONFIG_DRM_RP1_DSI is not set
+# CONFIG_DRM_RP1_VEC is not set
 # CONFIG_DRM_SII902X is not set
 # CONFIG_DRM_SII9234 is not set
 # CONFIG_DRM_SIL_SII8620 is not set
@@ -1750,6 +1757,7 @@ CONFIG_DQL=y
 # CONFIG_DRM_TOSHIBA_TC358775 is not set
 # CONFIG_DRM_TVE200 is not set
 # CONFIG_DRM_UDL is not set
+# CONFIG_DRM_V3D is not set
 # CONFIG_DRM_VBOXVIDEO is not set
 # CONFIG_DRM_VC4_HDMI_CEC is not set
 # CONFIG_DRM_VGEM is not set
@@ -2083,6 +2091,7 @@ CONFIG_FB_NOTIFY=y
 # CONFIG_FB_PXA is not set
 # CONFIG_FB_RADEON is not set
 # CONFIG_FB_RIVA is not set
+# CONFIG_FB_RPISENSE is not set
 # CONFIG_FB_S1D13XXX is not set
 # CONFIG_FB_S3 is not set
 # CONFIG_FB_SAVAGE is not set
@@ -2159,7 +2168,6 @@ CONFIG_FILE_LOCKING=y
 # CONFIG_FIRMWARE_EDID is not set
 # CONFIG_FIRMWARE_IN_KERNEL is not set
 # CONFIG_FIRMWARE_MEMMAP is not set
-# CONFIG_FIT_PARTITION is not set
 # CONFIG_FIXED_PHY is not set
 CONFIG_FLATMEM=y
 CONFIG_FLATMEM_MANUAL=y
@@ -2283,6 +2291,7 @@ CONFIG_GPIOLIB_FASTPATH_LIMIT=512
 # CONFIG_GPIO_AMDPT is not set
 # CONFIG_GPIO_AMD_FCH is not set
 # CONFIG_GPIO_BCM_KONA is not set
+# CONFIG_GPIO_BRCMSTB is not set
 # CONFIG_GPIO_BT8XX is not set
 # CONFIG_GPIO_CADENCE is not set
 # CONFIG_GPIO_CASCADE is not set
@@ -2853,6 +2862,7 @@ CONFIG_INPUT_MISC=y
 # CONFIG_INPUT_POWERMATE is not set
 # CONFIG_INPUT_PWM_BEEPER is not set
 # CONFIG_INPUT_PWM_VIBRA is not set
+# CONFIG_INPUT_RASPBERRYPI_BUTTON is not set
 # CONFIG_INPUT_REGULATOR_HAPTIC is not set
 # CONFIG_INPUT_SOC_BUTTON_ARRAY is not set
 # CONFIG_INPUT_SPARSEKMAP is not set
@@ -3609,6 +3619,7 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_PM8921_CORE is not set
 # CONFIG_MFD_PM8XXX is not set
 # CONFIG_MFD_QCOM_PM8008 is not set
+# CONFIG_MFD_RASPBERRYPI_POE_HAT is not set
 # CONFIG_MFD_RC5T583 is not set
 # CONFIG_MFD_RDC321X is not set
 # CONFIG_MFD_RETU is not set
@@ -3618,6 +3629,8 @@ CONFIG_MESSAGE_LOGLEVEL_DEFAULT=4
 # CONFIG_MFD_ROHM_BD71828 is not set
 # CONFIG_MFD_ROHM_BD718XX is not set
 # CONFIG_MFD_ROHM_BD957XMUF is not set
+# CONFIG_MFD_RP1 is not set
+# CONFIG_MFD_RPISENSE_CORE is not set
 # CONFIG_MFD_RSMU_I2C is not set
 # CONFIG_MFD_RSMU_SPI is not set
 # CONFIG_MFD_RT4831 is not set
@@ -4025,6 +4038,7 @@ CONFIG_MTD_SPLIT_SUPPORT=y
 # CONFIG_MTD_UBI is not set
 # CONFIG_MTD_UBI_FASTMAP is not set
 # CONFIG_MTD_UBI_GLUEBI is not set
+# CONFIG_MTD_UBI_NVMEM is not set
 # CONFIG_MTD_UIMAGE_SPLIT is not set
 # CONFIG_MTD_VIRT_CONCAT is not set
 # CONFIG_MTK_DEVAPC is not set
@@ -4824,6 +4838,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PCNET32 is not set
 # CONFIG_PCPU_DEV_REFCNT is not set
 # CONFIG_PCSPKR_PLATFORM is not set
+# CONFIG_PCS_MTK_USXGMII is not set
 # CONFIG_PCS_XPCS is not set
 # CONFIG_PD6729 is not set
 # CONFIG_PDA_POWER is not set
@@ -4839,6 +4854,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PHYLIB is not set
 # CONFIG_PHYLIB_LEDS is not set
 # CONFIG_PHYS_ADDR_T_64BIT is not set
+# CONFIG_PHY_BRCM_USB is not set
 # CONFIG_PHY_CADENCE_DP is not set
 # CONFIG_PHY_CADENCE_DPHY is not set
 # CONFIG_PHY_CADENCE_DPHY_RX is not set
@@ -4857,6 +4873,7 @@ CONFIG_PCI_SYSCALL=y
 # CONFIG_PHY_MIXEL_MIPI_DPHY is not set
 # CONFIG_PHY_MTK_HDMI is not set
 # CONFIG_PHY_MTK_MIPI_DSI is not set
+# CONFIG_PHY_MTK_XFI_TPHY is not set
 # CONFIG_PHY_MVEBU_CP110_UTMI is not set
 # CONFIG_PHY_OCELOT_SERDES is not set
 # CONFIG_PHY_PISTACHIO_USB is not set
@@ -4875,6 +4892,7 @@ CONFIG_PINCONF=y
 # CONFIG_PINCTRL is not set
 # CONFIG_PINCTRL_AMD is not set
 # CONFIG_PINCTRL_AXP209 is not set
+# CONFIG_PINCTRL_BCM2712 is not set
 # CONFIG_PINCTRL_CEDARFORK is not set
 # CONFIG_PINCTRL_CY8C95X0 is not set
 # CONFIG_PINCTRL_EXYNOS is not set
@@ -4895,6 +4913,7 @@ CONFIG_PINCONF=y
 # CONFIG_PINCTRL_MTK_V2 is not set
 # CONFIG_PINCTRL_OCELOT is not set
 # CONFIG_PINCTRL_PISTACHIO is not set
+# CONFIG_PINCTRL_RP1 is not set
 # CONFIG_PINCTRL_SC7280 is not set
 # CONFIG_PINCTRL_SC8180X is not set
 # CONFIG_PINCTRL_SDX55 is not set
@@ -5053,6 +5072,7 @@ CONFIG_PSTORE_DEFAULT_KMSG_BYTES=10240
 # CONFIG_PWM_MEDIATEK is not set
 # CONFIG_PWM_PCA9685 is not set
 # CONFIG_PWM_RASPBERRYPI_POE is not set
+# CONFIG_PWM_RP1 is not set
 # CONFIG_PWM_XILINX is not set
 CONFIG_PWRSEQ_EMMC=y
 # CONFIG_PWRSEQ_SD8787 is not set
@@ -5060,6 +5080,9 @@ CONFIG_PWRSEQ_SIMPLE=y
 # CONFIG_QCA7000 is not set
 # CONFIG_QCA7000_SPI is not set
 # CONFIG_QCA7000_UART is not set
+# CONFIG_QCA83XX_PHY is not set
+# CONFIG_QCA807X_PHY is not set
+# CONFIG_QCA808X_PHY is not set
 # CONFIG_QCOM_A7PLL is not set
 # CONFIG_QCOM_BAM_DMUX is not set
 # CONFIG_QCOM_EMAC is not set
@@ -5127,6 +5150,7 @@ CONFIG_RANDOM_TRUST_CPU=y
 # CONFIG_RANDSTRUCT_NONE is not set
 # CONFIG_RAPIDIO is not set
 # CONFIG_RAS is not set
+# CONFIG_RASPBERRYPI_GPIOMEM is not set
 # CONFIG_RBTREE_TEST is not set
 # CONFIG_RCU_BOOST is not set
 CONFIG_RCU_CPU_STALL_TIMEOUT=60
@@ -5251,6 +5275,7 @@ CONFIG_REISERFS_FS_XATTR=y
 # CONFIG_RENESAS_PHY is not set
 # CONFIG_RESET_ATH79 is not set
 # CONFIG_RESET_BERLIN is not set
+# CONFIG_RESET_BRCMSTB is not set
 # CONFIG_RESET_BRCMSTB_RESCAL is not set
 # CONFIG_RESET_CONTROLLER is not set
 # CONFIG_RESET_IMX7 is not set
@@ -5779,6 +5804,7 @@ CONFIG_SELECT_MEMORY_MODEL=y
 # CONFIG_SENSORS_Q54SJ108A2 is not set
 # CONFIG_SENSORS_RM3100_I2C is not set
 # CONFIG_SENSORS_RM3100_SPI is not set
+# CONFIG_SENSORS_RP1_ADC is not set
 # CONFIG_SENSORS_SBRMI is not set
 # CONFIG_SENSORS_SBTSI is not set
 # CONFIG_SENSORS_SCH5627 is not set
@@ -6020,6 +6046,7 @@ CONFIG_SLUB_CPU_PARTIAL=y
 # CONFIG_SND_AZT2320 is not set
 # CONFIG_SND_AZT3328 is not set
 # CONFIG_SND_BCD2000 is not set
+# CONFIG_SND_BCM2835 is not set
 # CONFIG_SND_BCM63XX_I2S_WHISTLER is not set
 # CONFIG_SND_BT87X is not set
 # CONFIG_SND_CA0106 is not set
@@ -6593,6 +6620,7 @@ CONFIG_STDBINUTILS=y
 # CONFIG_STMMAC_PCI is not set
 # CONFIG_STMMAC_PLATFORM is not set
 # CONFIG_STMMAC_SELFTESTS is not set
+# CONFIG_STMPE_ADC is not set
 # CONFIG_STM_DUMMY is not set
 # CONFIG_STM_SOURCE_CONSOLE is not set
 CONFIG_STP=y
@@ -7047,6 +7075,7 @@ CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
 # CONFIG_UHID is not set
 CONFIG_UID16=y
 # CONFIG_UIO is not set
+# CONFIG_UIMAGE_FIT_BLK is not set
 # CONFIG_ULTRA is not set
 # CONFIG_ULTRIX_PARTITION is not set
 # CONFIG_UNICODE is not set
@@ -7502,14 +7531,19 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_AK881X is not set
 # CONFIG_VIDEO_AM437X_VPFE is not set
 # CONFIG_VIDEO_AR0521 is not set
+# CONFIG_VIDEO_ARDUCAM_64MP is not set
+# CONFIG_VIDEO_ARDUCAM_PIVARIETY is not set
 # CONFIG_VIDEO_ASPEED is not set
 # CONFIG_VIDEO_ATMEL_ISC is not set
 # CONFIG_VIDEO_ATMEL_ISI is not set
 # CONFIG_VIDEO_AU0828 is not set
+# CONFIG_VIDEO_BCM2835 is not set
+# CONFIG_VIDEO_BCM2835_UNICAM is not set
 # CONFIG_VIDEO_BT819 is not set
 # CONFIG_VIDEO_BT848 is not set
 # CONFIG_VIDEO_BT856 is not set
 # CONFIG_VIDEO_BT866 is not set
+# CONFIG_VIDEO_BU64754 is not set
 # CONFIG_VIDEO_CADENCE is not set
 # CONFIG_VIDEO_CADENCE_CSI2RX is not set
 # CONFIG_VIDEO_CADENCE_CSI2TX is not set
@@ -7518,6 +7552,7 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_CCS is not set
 # CONFIG_VIDEO_COBALT is not set
 # CONFIG_VIDEO_CODA is not set
+# CONFIG_VIDEO_CODEC_BCM2835 is not set
 # CONFIG_VIDEO_CS3308 is not set
 # CONFIG_VIDEO_CS5345 is not set
 # CONFIG_VIDEO_CS53L32A is not set
@@ -7550,17 +7585,22 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_IMX258 is not set
 # CONFIG_VIDEO_IMX274 is not set
 # CONFIG_VIDEO_IMX290 is not set
+# CONFIG_VIDEO_IMX296 is not set
 # CONFIG_VIDEO_IMX319 is not set
 # CONFIG_VIDEO_IMX334 is not set
 # CONFIG_VIDEO_IMX335 is not set
 # CONFIG_VIDEO_IMX355 is not set
 # CONFIG_VIDEO_IMX412 is not set
 # CONFIG_VIDEO_IMX477 is not set
+# CONFIG_VIDEO_IMX519 is not set
+# CONFIG_VIDEO_IMX708 is not set
 # CONFIG_VIDEO_IMX8_JPEG is not set
+# CONFIG_VIDEO_IMX_MIPI_CSIS is not set
 # CONFIG_VIDEO_IMX_PXP is not set
 # CONFIG_VIDEO_IRS1125 is not set
 # CONFIG_VIDEO_IR_I2C is not set
 # CONFIG_VIDEO_ISL7998X is not set
+# CONFIG_VIDEO_ISP_BCM2835 is not set
 # CONFIG_VIDEO_IVTV is not set
 # CONFIG_VIDEO_KS0127 is not set
 # CONFIG_VIDEO_LM3560 is not set
@@ -7603,6 +7643,7 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_OV5675 is not set
 # CONFIG_VIDEO_OV5693 is not set
 # CONFIG_VIDEO_OV5695 is not set
+# CONFIG_VIDEO_OV64A40 is not set
 # CONFIG_VIDEO_OV6650 is not set
 # CONFIG_VIDEO_OV7251 is not set
 # CONFIG_VIDEO_OV7640 is not set
@@ -7617,9 +7658,15 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_OV9650 is not set
 # CONFIG_VIDEO_OV9734 is not set
 # CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_RASPBERRYPI_PISP_BE is not set
+# CONFIG_VIDEO_RCAR_CSI2 is not set
+# CONFIG_VIDEO_RCAR_ISP is not set
+# CONFIG_VIDEO_RCAR_VIN is not set
 # CONFIG_VIDEO_RDACM20 is not set
 # CONFIG_VIDEO_RDACM21 is not set
 # CONFIG_VIDEO_RJ54N1 is not set
+# CONFIG_VIDEO_ROCKCHIP_ISP1 is not set
+# CONFIG_VIDEO_RP1_CFE is not set
 # CONFIG_VIDEO_S5C73M3 is not set
 # CONFIG_VIDEO_S5K4ECGX is not set
 # CONFIG_VIDEO_S5K5BAF is not set
@@ -7638,6 +7685,9 @@ CONFIG_VHOST_MENU=y
 # CONFIG_VIDEO_SMIAPP is not set
 # CONFIG_VIDEO_SOLO6X10 is not set
 # CONFIG_VIDEO_SONY_BTF_MPX is not set
+# CONFIG_VIDEO_SUN4I_CSI is not set
+# CONFIG_VIDEO_SUN6I_CSI is not set
+# CONFIG_VIDEO_SUN8I_A83T_MIPI_CSI2 is not set
 # CONFIG_VIDEO_SR030PC30 is not set
 # CONFIG_VIDEO_STK1160_COMMON is not set
 # CONFIG_VIDEO_ST_MIPID02 is not set
diff --git a/target/linux/generic/files/block/partitions/fit.c b/target/linux/generic/files/block/partitions/fit.c
deleted file mode 100644
index 91b25e0581e..00000000000
--- a/target/linux/generic/files/block/partitions/fit.c
+++ /dev/null
@@ -1,303 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-or-later
-/*
- *  fs/partitions/fit.c
- *  Copyright (C) 2021  Daniel Golle
- *
- *  headers extracted from U-Boot mkimage sources
- *  (C) Copyright 2008 Semihalf
- *  (C) Copyright 2000-2005
- *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- *  based on existing partition parsers
- *  Copyright (C) 1991-1998  Linus Torvalds
- *  Re-organised Feb 1998 Russell King
- */
-
-#define pr_fmt(fmt) fmt
-
-#include <linux/types.h>
-#include <linux/of.h>
-#include <linux/of_device.h>
-#include <linux/of_fdt.h>
-#include <linux/libfdt.h>
-#include <linux/version.h>
-
-#include "check.h"
-
-#define FIT_IMAGES_PATH		"/images"
-#define FIT_CONFS_PATH		"/configurations"
-
-/* hash/signature/key node */
-#define FIT_HASH_NODENAME	"hash"
-#define FIT_ALGO_PROP		"algo"
-#define FIT_VALUE_PROP		"value"
-#define FIT_IGNORE_PROP		"uboot-ignore"
-#define FIT_SIG_NODENAME	"signature"
-#define FIT_KEY_REQUIRED	"required"
-#define FIT_KEY_HINT		"key-name-hint"
-
-/* cipher node */
-#define FIT_CIPHER_NODENAME	"cipher"
-#define FIT_ALGO_PROP		"algo"
-
-/* image node */
-#define FIT_DATA_PROP		"data"
-#define FIT_DATA_POSITION_PROP	"data-position"
-#define FIT_DATA_OFFSET_PROP	"data-offset"
-#define FIT_DATA_SIZE_PROP	"data-size"
-#define FIT_TIMESTAMP_PROP	"timestamp"
-#define FIT_DESC_PROP		"description"
-#define FIT_ARCH_PROP		"arch"
-#define FIT_TYPE_PROP		"type"
-#define FIT_OS_PROP		"os"
-#define FIT_COMP_PROP		"compression"
-#define FIT_ENTRY_PROP		"entry"
-#define FIT_LOAD_PROP		"load"
-
-/* configuration node */
-#define FIT_KERNEL_PROP		"kernel"
-#define FIT_FILESYSTEM_PROP	"filesystem"
-#define FIT_RAMDISK_PROP	"ramdisk"
-#define FIT_FDT_PROP		"fdt"
-#define FIT_LOADABLE_PROP	"loadables"
-#define FIT_DEFAULT_PROP	"default"
-#define FIT_SETUP_PROP		"setup"
-#define FIT_FPGA_PROP		"fpga"
-#define FIT_FIRMWARE_PROP	"firmware"
-#define FIT_STANDALONE_PROP	"standalone"
-
-#define FIT_MAX_HASH_LEN	HASH_MAX_DIGEST_SIZE
-
-#define MIN_FREE_SECT		16
-#define REMAIN_VOLNAME		"rootfs_data"
-
-int parse_fit_partitions(struct parsed_partitions *state, u64 fit_start_sector, u64 sectors, int *slot, int add_remain)
-{
-	struct block_device *bdev = state->disk->part0;
-	struct address_space *mapping = bdev->bd_inode->i_mapping;
-	struct page *page;
-	void *fit, *init_fit;
-	struct partition_meta_info *info;
-	char tmp[sizeof(info->volname)];
-	u64 dsize, dsectors, imgmaxsect = 0;
-	u32 size, image_pos, image_len;
-	const u32 *image_offset_be, *image_len_be, *image_pos_be;
-	int ret = 1, node, images, config;
-	const char *image_name, *image_type, *image_description, *config_default,
-		*config_description, *config_loadables, *bootconf_c;
-	int image_name_len, image_type_len, image_description_len, config_default_len,
-		config_description_len, config_loadables_len, bootconf_len;
-	sector_t start_sect, nr_sects;
-	size_t label_min;
-	struct device_node *np = NULL;
-	char *bootconf = NULL, *bootconf_term;
-	const char *loadable;
-	const char *select_rootfs = NULL;
-	bool found;
-	int loadables_rem_len, loadable_len;
-
-	if (fit_start_sector % (1<<(PAGE_SHIFT - SECTOR_SHIFT)))
-		return -ERANGE;
-
-	page = read_mapping_page(mapping, fit_start_sector >> (PAGE_SHIFT - SECTOR_SHIFT), NULL);
-	if (IS_ERR(page))
-		return -EFAULT;
-
-	if (PageError(page))
-		return -EFAULT;
-
-	init_fit = page_address(page);
-
-	if (!init_fit) {
-		put_page(page);
-		return -EFAULT;
-	}
-
-	if (fdt_check_header(init_fit)) {
-		put_page(page);
-		return 0;
-	}
-
-	dsectors = get_capacity(bdev->bd_disk);
-	if (sectors)
-		dsectors = (dsectors>sectors)?sectors:dsectors;
-
-	dsize = dsectors << SECTOR_SHIFT;
-	size = fdt_totalsize(init_fit);
-
-	/* silently skip non-external-data legacy FIT images */
-	if (size > PAGE_SIZE) {
-		put_page(page);
-		return 0;
-	}
-
-	if (size >= dsize) {
-		state->access_beyond_eod = 1;
-		put_page(page);
-		return -EFBIG;
-	}
-
-	fit = kmemdup(init_fit, size, GFP_KERNEL);
-	put_page(page);
-	if (!fit)
-		return -ENOMEM;
-
-	np = of_find_node_by_path("/chosen");
-	if (np) {
-		bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
-		if (bootconf_c && bootconf_len)
-			bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
-	}
-
-	if (bootconf) {
-		bootconf_term = strchr(bootconf, '#');
-		if (bootconf_term)
-			*bootconf_term = '\0';
-	}
-
-	config = fdt_path_offset(fit, FIT_CONFS_PATH);
-	if (config < 0) {
-		printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_CONFS_PATH, images);
-		ret = -ENOENT;
-		goto ret_out;
-	}
-
-	config_default = fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);
-
-	if (!config_default && !bootconf) {
-		printk(KERN_ERR "FIT: Cannot find default configuration\n");
-		ret = -ENOENT;
-		goto ret_out;
-	}
-
-	node = fdt_subnode_offset(fit, config, bootconf?:config_default);
-	if (node < 0) {
-		printk(KERN_ERR "FIT: Cannot find %s node: %d\n", bootconf?:config_default, node);
-		ret = -ENOENT;
-		goto ret_out;
-	}
-
-	config_description = fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);
-	config_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP, &config_loadables_len);
-
-	printk(KERN_DEBUG "FIT: %s configuration: \"%s\"%s%s%s\n",
-		bootconf?"Selected":"Default", bootconf?:config_default,
-		config_description?" (":"", config_description?:"", config_description?")":"");
-
-	if (!config_loadables || !config_loadables_len) {
-		printk(KERN_ERR "FIT: No loadables configured in \"%s\"\n", bootconf?:config_default);
-		ret = -ENOENT;
-		goto ret_out;
-	}
-
-	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
-	if (images < 0) {
-		printk(KERN_ERR "FIT: Cannot find %s node: %d\n", FIT_IMAGES_PATH, images);
-		ret = -EINVAL;
-		goto ret_out;
-	}
-
-	fdt_for_each_subnode(node, fit, images) {
-		image_name = fdt_get_name(fit, node, &image_name_len);
-		image_type = fdt_getprop(fit, node, FIT_TYPE_PROP, &image_type_len);
-		image_offset_be = fdt_getprop(fit, node, FIT_DATA_OFFSET_PROP, NULL);
-		image_pos_be = fdt_getprop(fit, node, FIT_DATA_POSITION_PROP, NULL);
-		image_len_be = fdt_getprop(fit, node, FIT_DATA_SIZE_PROP, NULL);
-		if (!image_name || !image_type || !image_len_be)
-			continue;
-
-		image_len = be32_to_cpu(*image_len_be);
-		if (!image_len)
-			continue;
-
-		if (image_offset_be)
-			image_pos = be32_to_cpu(*image_offset_be) + size;
-		else if (image_pos_be)
-			image_pos = be32_to_cpu(*image_pos_be);
-		else
-			continue;
-
-		image_description = fdt_getprop(fit, node, FIT_DESC_PROP, &image_description_len);
-
-		printk(KERN_DEBUG "FIT: %16s sub-image 0x%08x..0x%08x \"%s\" %s%s%s\n",
-			image_type, image_pos, image_pos + image_len - 1, image_name,
-			image_description?"(":"", image_description?:"", image_description?") ":"");
-
-		if (strcmp(image_type, FIT_FILESYSTEM_PROP))
-			continue;
-
-		/* check if sub-image is part of configured loadables */
-		found = false;
-		loadable = config_loadables;
-		loadables_rem_len = config_loadables_len;
-		while (loadables_rem_len > 1) {
-			loadable_len = strnlen(loadable, loadables_rem_len - 1) + 1;
-			loadables_rem_len -= loadable_len;
-			if (!strncmp(image_name, loadable, loadable_len)) {
-				found = true;
-				break;
-			}
-			loadable += loadable_len;
-		}
-		if (!found)
-			continue;
-
-		if (image_pos & ((1 << PAGE_SHIFT)-1)) {
-			printk(KERN_ERR "FIT: image %s start not aligned to page boundaries, skipping\n", image_name);
-			continue;
-		}
-
-		if (image_len & ((1 << PAGE_SHIFT)-1)) {
-			printk(KERN_ERR "FIT: sub-image %s end not aligned to page boundaries, skipping\n", image_name);
-			continue;
-		}
-
-		start_sect = image_pos >> SECTOR_SHIFT;
-		nr_sects = image_len >> SECTOR_SHIFT;
-		imgmaxsect = (imgmaxsect < (start_sect + nr_sects))?(start_sect + nr_sects):imgmaxsect;
-
-		if (start_sect + nr_sects > dsectors) {
-			state->access_beyond_eod = 1;
-			continue;
-		}
-
-		put_partition(state, ++(*slot), fit_start_sector + start_sect, nr_sects);
-		state->parts[*slot].flags = ADDPART_FLAG_READONLY;
-		state->parts[*slot].has_info = true;
-		info = &state->parts[*slot].info;
-
-		label_min = min_t(int, sizeof(info->volname) - 1, image_name_len);
-		strncpy(info->volname, image_name, label_min);
-		info->volname[label_min] = '\0';
-
-		snprintf(tmp, sizeof(tmp), "(%s)", info->volname);
-		strlcat(state->pp_buf, tmp, PAGE_SIZE);
-
-		/* Mark first loadable listed to be mounted as rootfs */
-		if (!strcmp(image_name, config_loadables)) {
-			select_rootfs = image_name;
-			state->parts[*slot].flags |= ADDPART_FLAG_ROOTDEV;
-		}
-	}
-
-	if (select_rootfs)
-		printk(KERN_DEBUG "FIT: selecting configured loadable \"%s\" to be root filesystem\n", select_rootfs);
-
-	if (add_remain && (imgmaxsect + MIN_FREE_SECT) < dsectors) {
-		put_partition(state, ++(*slot), fit_start_sector + imgmaxsect, dsectors - imgmaxsect);
-		state->parts[*slot].flags = 0;
-		info = &state->parts[*slot].info;
-		strcpy(info->volname, REMAIN_VOLNAME);
-		snprintf(tmp, sizeof(tmp), "(%s)", REMAIN_VOLNAME);
-		strlcat(state->pp_buf, tmp, PAGE_SIZE);
-	}
-ret_out:
-	kfree(bootconf);
-	kfree(fit);
-	return ret;
-}
-
-int fit_partition(struct parsed_partitions *state) {
-	int slot = 0;
-	return parse_fit_partitions(state, 0, 0, &slot, 0);
-}
diff --git a/target/linux/generic/hack-5.15/251-kconfig.patch b/target/linux/generic/hack-5.15/251-kconfig.patch
index 9350e366d86..00c23db955e 100644
--- a/target/linux/generic/hack-5.15/251-kconfig.patch
+++ b/target/linux/generic/hack-5.15/251-kconfig.patch
@@ -124,59 +124,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
  
  config NETFILTER_FAMILY_BRIDGE
  	bool
---- a/net/wireless/Kconfig
-+++ b/net/wireless/Kconfig
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- config WIRELESS_EXT
--	bool
-+	bool "Wireless extensions"
- 
- config WEXT_CORE
- 	def_bool y
-@@ -12,10 +12,10 @@ config WEXT_PROC
- 	depends on WEXT_CORE
- 
- config WEXT_SPY
--	bool
-+	bool "WEXT_SPY"
- 
- config WEXT_PRIV
--	bool
-+	bool "WEXT_PRIV"
- 
- config CFG80211
- 	tristate "cfg80211 - wireless configuration API"
-@@ -204,7 +204,7 @@ config CFG80211_WEXT_EXPORT
- endif # CFG80211
- 
- config LIB80211
--	tristate
-+	tristate "LIB80211"
- 	default n
- 	help
- 	  This options enables a library of common routines used
-@@ -213,17 +213,17 @@ config LIB80211
- 	  Drivers should select this themselves if needed.
- 
- config LIB80211_CRYPT_WEP
--	tristate
-+	tristate "LIB80211_CRYPT_WEP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_CRYPT_CCMP
--	tristate
-+	tristate "LIB80211_CRYPT_CCMP"
- 	select CRYPTO
- 	select CRYPTO_AES
- 	select CRYPTO_CCM
- 
- config LIB80211_CRYPT_TKIP
--	tristate
-+	tristate "LIB80211_CRYPT_TKIP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_DEBUG
 --- a/sound/core/Kconfig
 +++ b/sound/core/Kconfig
 @@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM
diff --git a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch
deleted file mode 100644
index f1942e20375..00000000000
--- a/target/linux/generic/hack-5.15/321-powerpc_crtsavres_prereq.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
-From: "Alexandros C. Couloumbis" <alex@ozo.com>
-Date: Fri, 7 Jul 2017 17:14:51 +0200
-Subject: hack: arch: powerpc: drop register save/restore library from modules
-
-Upstream GCC uses a libgcc function for saving/restoring registers. This
-makes the code bigger, and upstream kernels need to carry that function
-for every single kernel module. Our GCC is patched to avoid those
-references, so we can drop the extra bloat for modules.
-
-lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
-Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
----
- arch/powerpc/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -44,19 +44,6 @@ machine-$(CONFIG_PPC64) += 64
- machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
- UTS_MACHINE := $(subst $(space),,$(machine-y))
- 
--# XXX This needs to be before we override LD below
--ifdef CONFIG_PPC32
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--else
--ifeq ($(call ld-ifversion, -ge, 22500, y),y)
--# Have the linker provide sfpr if possible.
--# There is a corresponding test in arch/powerpc/lib/Makefile
--KBUILD_LDFLAGS_MODULE += --save-restore-funcs
--else
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--endif
--endif
--
- ifdef CONFIG_CPU_LITTLE_ENDIAN
- KBUILD_CFLAGS	+= -mlittle-endian
- KBUILD_LDFLAGS	+= -EL
diff --git a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch b/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch
deleted file mode 100644
index 13a16b6fa08..00000000000
--- a/target/linux/generic/hack-5.15/410-block-fit-partition-parser.patch
+++ /dev/null
@@ -1,214 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -354,6 +354,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -101,6 +101,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -58,6 +58,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -68,3 +69,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -12,6 +12,10 @@
- #include <linux/vmalloc.h>
- #include <linux/blktrace_api.h>
- #include <linux/raid/detect.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-+
- #include "check.h"
- 
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -48,6 +52,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -408,6 +415,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -595,6 +607,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -52,6 +52,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -345,6 +345,8 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	gd->first_minor = (new->devnum) << tr->part_bits;
- 	gd->minors = 1 << tr->part_bits;
- 	gd->fops = &mtd_block_ops;
-+	if (IS_ENABLED(CONFIG_FIT_PARTITION) && !mtd_type_is_nand(new->mtd))
-+		gd->flags |= GENHD_FL_EXT_DEVT;
- 
- 	if (tr->part_bits)
- 		if (new->devnum < 26)
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -428,6 +428,9 @@ int ubiblock_create(struct ubi_volume_in
- 		goto out_cleanup_disk;
- 	}
- 	gd->private_data = dev;
-+#ifdef CONFIG_FIT_PARTITION
-+	gd->flags |= GENHD_FL_EXT_DEVT;
-+#endif
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
- 	dev->gd = gd;
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 
diff --git a/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch b/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch
deleted file mode 100644
index 55866c31350..00000000000
--- a/target/linux/generic/hack-5.15/601-of_net-add-mac-address-ascii-support.patch
+++ /dev/null
@@ -1,116 +0,0 @@
-From: Yousong Zhou <yszhou4tech@gmail.com>
-Subject: [PATCH] of: net: add nvmem cell mac-address-ascii support
-
-This is needed for devices with mac address stored in ascii format,
-e.g. HiWiFi HC6361 to be ported in the following patch.
-
-Submitted-by: Yousong Zhou <yszhou4tech@gmail.com>
----
- net/core/of_net.c | 83 ++++++++++++------
- 1 files changed, 72 insertions(+), 11 deletions(-)
-
---- a/net/core/of_net.c
-+++ b/net/core/of_net.c
-@@ -57,13 +57,70 @@ static int of_get_mac_addr(struct device
- 	return -ENODEV;
- }
- 
-+static void *nvmem_cell_get_mac_address(struct nvmem_cell *cell)
-+{
-+	size_t len;
-+	void *mac;
-+
-+	mac = nvmem_cell_read(cell, &len);
-+	if (IS_ERR(mac))
-+		return mac;
-+	if (len != ETH_ALEN) {
-+		kfree(mac);
-+		return ERR_PTR(-EINVAL);
-+	}
-+	return mac;
-+}
-+
-+static void *nvmem_cell_get_mac_address_ascii(struct nvmem_cell *cell)
-+{
-+	size_t len;
-+	int ret;
-+	void *mac_ascii;
-+	u8 *mac;
-+
-+	mac_ascii = nvmem_cell_read(cell, &len);
-+	if (IS_ERR(mac_ascii))
-+		return mac_ascii;
-+	if (len != ETH_ALEN*2+5) {
-+		kfree(mac_ascii);
-+		return ERR_PTR(-EINVAL);
-+	}
-+	mac = kmalloc(ETH_ALEN, GFP_KERNEL);
-+	if (!mac) {
-+		kfree(mac_ascii);
-+		return ERR_PTR(-ENOMEM);
-+	}
-+	ret = sscanf(mac_ascii, "%2hhx:%2hhx:%2hhx:%2hhx:%2hhx:%2hhx",
-+				&mac[0], &mac[1], &mac[2],
-+				&mac[3], &mac[4], &mac[5]);
-+	kfree(mac_ascii);
-+	if (ret == ETH_ALEN)
-+		return mac;
-+	kfree(mac);
-+	return ERR_PTR(-EINVAL);
-+}
-+
-+static struct nvmem_cell_mac_address_property {
-+	char *name;
-+	void *(*read)(struct nvmem_cell *);
-+} nvmem_cell_mac_address_properties[] = {
-+	{
-+		.name = "mac-address",
-+		.read = nvmem_cell_get_mac_address,
-+	}, {
-+		.name = "mac-address-ascii",
-+		.read = nvmem_cell_get_mac_address_ascii,
-+	},
-+};
-+
- static int of_get_mac_addr_nvmem(struct device_node *np, u8 *addr)
- {
- 	struct platform_device *pdev = of_find_device_by_node(np);
-+	struct nvmem_cell_mac_address_property *property;
- 	struct nvmem_cell *cell;
- 	const void *mac;
--	size_t len;
--	int ret;
-+	int ret, i;
- 
- 	/* Try lookup by device first, there might be a nvmem_cell_lookup
- 	 * associated with a given device.
-@@ -74,17 +131,26 @@ static int of_get_mac_addr_nvmem(struct
- 		return ret;
- 	}
- 
--	cell = of_nvmem_cell_get(np, "mac-address");
-+	for (i = 0; i < ARRAY_SIZE(nvmem_cell_mac_address_properties); i++) {
-+		property = &nvmem_cell_mac_address_properties[i];
-+		cell = of_nvmem_cell_get(np, property->name);
-+		/* For -EPROBE_DEFER don't try other properties.
-+		 * We'll get back to this one.
-+		 */
-+		if (!IS_ERR(cell) || PTR_ERR(cell) == -EPROBE_DEFER)
-+			break;
-+	}
-+
- 	if (IS_ERR(cell))
- 		return PTR_ERR(cell);
- 
--	mac = nvmem_cell_read(cell, &len);
-+	mac = property->read(cell);
- 	nvmem_cell_put(cell);
- 
- 	if (IS_ERR(mac))
- 		return PTR_ERR(mac);
- 
--	if (len != ETH_ALEN || !is_valid_ether_addr(mac)) {
-+	if (!is_valid_ether_addr(mac)) {
- 		kfree(mac);
- 		return -EINVAL;
- 	}
diff --git a/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch b/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
index 29050d38ea2..c4a915956e9 100644
--- a/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
+++ b/target/linux/generic/hack-5.15/720-net-phy-add-aqr-phys.patch
@@ -7,20 +7,17 @@ PHYs AQR113C and AQR813.
 
 Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
 
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -20,8 +20,10 @@
- #define PHY_ID_AQR105	0x03a1b4a2
- #define PHY_ID_AQR106	0x03a1b4d0
- #define PHY_ID_AQR107	0x03a1b4e0
-+#define PHY_ID_AQR113C	0x31c31c12
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -23,6 +23,7 @@
  #define PHY_ID_AQCS109	0x03a1b5c2
  #define PHY_ID_AQR405	0x03a1b4b0
+ #define PHY_ID_AQR113C	0x31c31c12
 +#define PHY_ID_AQR813	0x31c31cb2
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
  #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
-@@ -381,6 +383,49 @@ static int aqr107_read_rate(struct phy_d
+@@ -360,6 +361,49 @@ static int aqr107_read_rate(struct phy_d
  	return 0;
  }
  
@@ -70,7 +67,7 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
  static int aqr107_read_status(struct phy_device *phydev)
  {
  	int val, ret;
-@@ -511,7 +556,7 @@ static void aqr107_chip_info(struct phy_
+@@ -499,7 +543,7 @@ static void aqr107_chip_info(struct phy_
  	build_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_FW_BUILD_ID, val);
  	prov_id = FIELD_GET(VEND1_GLOBAL_RSVD_STAT1_PROV_ID, val);
  
@@ -79,35 +76,19 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
  		   fw_major, fw_minor, build_id, prov_id);
  }
  
-@@ -719,6 +764,24 @@ static struct phy_driver aqr_driver[] =
+@@ -762,7 +806,7 @@ static struct phy_driver aqr_driver[] =
+ 	.config_aneg    = aqr_config_aneg,
+ 	.config_intr    = aqr_config_intr,
+ 	.handle_interrupt       = aqr_handle_interrupt,
+-	.read_status    = aqr107_read_status,
++	.read_status    = aqr113c_read_status,
+ 	.get_tunable    = aqr107_get_tunable,
+ 	.set_tunable    = aqr107_set_tunable,
+ 	.suspend        = aqr107_suspend,
+@@ -772,6 +816,24 @@ static struct phy_driver aqr_driver[] =
+ 	.get_stats      = aqr107_get_stats,
  	.link_change_notify = aqr107_link_change_notify,
  },
- {
-+	PHY_ID_MATCH_MODEL(PHY_ID_AQR113C),
-+	.name		= "Aquantia AQR113C",
-+	.probe		= aqr107_probe,
-+	.config_init	= aqr107_config_init,
-+	.config_aneg    = aqr_config_aneg,
-+	.config_intr	= aqr_config_intr,
-+	.handle_interrupt = aqr_handle_interrupt,
-+	.read_status	= aqr113c_read_status,
-+	.get_tunable    = aqr107_get_tunable,
-+	.set_tunable    = aqr107_set_tunable,
-+	.suspend	= aqr107_suspend,
-+	.resume		= aqr107_resume,
-+	.get_sset_count	= aqr107_get_sset_count,
-+	.get_strings	= aqr107_get_strings,
-+	.get_stats	= aqr107_get_stats,
-+	.link_change_notify = aqr107_link_change_notify,
-+},
-+{
- 	PHY_ID_MATCH_MODEL(PHY_ID_AQCS109),
- 	.name		= "Aquantia AQCS109",
- 	.probe		= aqr107_probe,
-@@ -744,6 +807,24 @@ static struct phy_driver aqr_driver[] =
- 	.handle_interrupt = aqr_handle_interrupt,
- 	.read_status	= aqr_read_status,
- },
 +{
 +	PHY_ID_MATCH_MODEL(PHY_ID_AQR813),
 +	.name		= "Aquantia AQR813",
@@ -129,13 +110,10 @@ Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
  };
  
  module_phy_driver(aqr_driver);
-@@ -754,8 +835,10 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+@@ -785,6 +847,7 @@ static struct mdio_device_id __maybe_unu
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
  	{ }
  };
diff --git a/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
index ac9a161b5f5..b03b4a674fc 100644
--- a/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-5.15/721-net-add-packet-mangeling.patch
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -1681,6 +1681,10 @@ enum netdev_priv_flags {
+@@ -1682,6 +1682,10 @@ enum netdev_priv_flags {
  	IFF_TX_SKB_NO_LINEAR		= BIT_ULL(31),
  };
  
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #define IFF_802_1Q_VLAN			IFF_802_1Q_VLAN
  #define IFF_EBRIDGE			IFF_EBRIDGE
  #define IFF_BONDING			IFF_BONDING
-@@ -1712,6 +1716,7 @@ enum netdev_priv_flags {
+@@ -1713,6 +1717,7 @@ enum netdev_priv_flags {
  #define IFF_FAILOVER_SLAVE		IFF_FAILOVER_SLAVE
  #define IFF_L3MDEV_RX_HANDLER		IFF_L3MDEV_RX_HANDLER
  #define IFF_TX_SKB_NO_LINEAR		IFF_TX_SKB_NO_LINEAR
@@ -38,7 +38,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  /* Specifies the type of the struct net_device::ml_priv pointer */
  enum netdev_ml_priv_type {
-@@ -2012,6 +2017,7 @@ struct net_device {
+@@ -2013,6 +2018,7 @@ struct net_device {
  	/* Read-mostly cache-line for fast-path access */
  	unsigned int		flags;
  	unsigned int		priv_flags;
@@ -46,7 +46,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	const struct net_device_ops *netdev_ops;
  	int			ifindex;
  	unsigned short		gflags;
-@@ -2072,6 +2078,11 @@ struct net_device {
+@@ -2073,6 +2079,11 @@ struct net_device {
  	const struct tlsdev_ops *tlsdev_ops;
  #endif
  
@@ -58,7 +58,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	const struct header_ops *header_ops;
  
  	unsigned char		operstate;
-@@ -2143,6 +2154,10 @@ struct net_device {
+@@ -2144,6 +2155,10 @@ struct net_device {
  	struct mctp_dev __rcu	*mctp_ptr;
  #endif
  
@@ -116,7 +116,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	help
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -3597,6 +3597,11 @@ static int xmit_one(struct sk_buff *skb,
+@@ -3600,6 +3600,11 @@ static int xmit_one(struct sk_buff *skb,
  	if (dev_nit_active(dev))
  		dev_queue_xmit_nit(skb, dev);
  
diff --git a/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch b/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
index 211696c5688..6ec0db2526d 100644
--- a/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
+++ b/target/linux/generic/hack-5.15/722-net-phy-aquantia-enable-AQR112-and-AQR412.patch
@@ -10,24 +10,21 @@ different firmware on the PHY.
 
 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 ---
- drivers/net/phy/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 88 +++++++++++++++++++++++++++++++++++++++++
  1 file changed, 88 insertions(+)
 
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -20,9 +20,11 @@
- #define PHY_ID_AQR105	0x03a1b4a2
- #define PHY_ID_AQR106	0x03a1b4d0
- #define PHY_ID_AQR107	0x03a1b4e0
-+#define PHY_ID_AQR112	0x03a1b662
- #define PHY_ID_AQR113C	0x31c31c12
- #define PHY_ID_AQCS109	0x03a1b5c2
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -24,6 +24,8 @@
  #define PHY_ID_AQR405	0x03a1b4b0
-+#define PHY_ID_AQR412	0x03a1b712
+ #define PHY_ID_AQR113C	0x31c31c12
  #define PHY_ID_AQR813	0x31c31cb2
++#define PHY_ID_AQR112	0x03a1b662
++#define PHY_ID_AQR412	0x03a1b712
  
  #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
-@@ -135,6 +137,29 @@
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+@@ -96,6 +98,29 @@
  #define AQR107_OP_IN_PROG_SLEEP		1000
  #define AQR107_OP_IN_PROG_TIMEOUT	100000
  
@@ -57,7 +54,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  struct aqr107_hw_stat {
  	const char *name;
  	int reg;
-@@ -266,6 +291,51 @@ static int aqr_config_aneg(struct phy_de
+@@ -227,6 +252,51 @@ static int aqr_config_aneg(struct phy_de
  	return genphy_c45_check_and_restart_aneg(phydev, changed);
  }
  
@@ -109,7 +106,7 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  static int aqr_config_intr(struct phy_device *phydev)
  {
  	bool en = phydev->interrupts == PHY_INTERRUPT_ENABLED;
-@@ -825,6 +895,30 @@ static struct phy_driver aqr_driver[] =
+@@ -834,6 +904,30 @@ static struct phy_driver aqr_driver[] =
  	.get_stats	= aqr107_get_stats,
  	.link_change_notify = aqr107_link_change_notify,
  },
@@ -140,15 +137,12 @@ Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
  };
  
  module_phy_driver(aqr_driver);
-@@ -835,9 +929,11 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+@@ -848,6 +942,8 @@ static struct mdio_device_id __maybe_unu
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
-+	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
++	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
  	{ }
  };
+ 
diff --git a/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch b/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
index 7d16c8aa289..33b182eab92 100644
--- a/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
+++ b/target/linux/generic/hack-5.15/723-net-phy-aquantia-fix-system-side-protocol-mi.patch
@@ -9,12 +9,12 @@ these protocols leads to link issues on system side.
 
 Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
 ---
- drivers/net/phy/aquantia_main.c | 8 +++++++-
+ drivers/net/phy/aquantia/aquantia_main.c | 8 +++++++-
  1 file changed, 7 insertions(+), 1 deletion(-)
 
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -324,10 +324,16 @@ static int aqr_config_aneg_set_prot(stru
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -285,10 +285,16 @@ static int aqr_config_aneg_set_prot(stru
  	phy_write_mmd(phydev, MDIO_MMD_VEND1, AQUANTIA_VND1_GSTART_RATE,
  		      aquantia_syscfg[if_type].start_rate);
  
diff --git a/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch b/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
index d03c3430fae..a31b327f9e9 100644
--- a/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
+++ b/target/linux/generic/hack-5.15/724-net-phy-aquantia-Add-AQR113-driver-support.patch
@@ -5,20 +5,20 @@ Subject: [PATCH] PONRTSYS-8842: aquantia: Add AQR113 driver support
 
 Add a new entry for AQR113 PHY_ID
 ---
- drivers/net/phy/aquantia_main.c | 10 ++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
  1 file changed, 10 insertions(+)
 
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -21,6 +21,7 @@
- #define PHY_ID_AQR106	0x03a1b4d0
- #define PHY_ID_AQR107	0x03a1b4e0
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -26,6 +26,7 @@
+ #define PHY_ID_AQR813	0x31c31cb2
  #define PHY_ID_AQR112	0x03a1b662
+ #define PHY_ID_AQR412	0x03a1b712
 +#define PHY_ID_AQR113	0x31c31c40
- #define PHY_ID_AQR113C	0x31c31c12
- #define PHY_ID_AQCS109	0x03a1b5c2
- #define PHY_ID_AQR405	0x03a1b4b0
-@@ -914,6 +915,14 @@ static struct phy_driver aqr_driver[] =
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+@@ -923,6 +924,14 @@ static struct phy_driver aqr_driver[] =
  	.get_stats	= aqr107_get_stats,
  },
  {
@@ -33,11 +33,11 @@ Add a new entry for AQR113 PHY_ID
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR412),
  	.name		= "Aquantia AQR412",
  	.probe		= aqr107_probe,
-@@ -936,6 +945,7 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+@@ -950,6 +959,7 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ 	{ }
+ };
+ 
diff --git a/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch b/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
index 9821c0c86ee..b2f79f4d586 100644
--- a/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
+++ b/target/linux/generic/hack-5.15/725-net-phy-aquantia-add-PHY_IDs-for-AQR112-variants.patch
@@ -7,21 +7,21 @@ As advised by Ian Chang this PHY is used in Puzzle devices.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 ---
- drivers/net/phy/aquantia_main.c | 10 ++++++++++
+ drivers/net/phy/aquantia/aquantia_main.c | 10 ++++++++++
  1 file changed, 10 insertions(+)
 
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -21,6 +21,8 @@
- #define PHY_ID_AQR106	0x03a1b4d0
- #define PHY_ID_AQR107	0x03a1b4e0
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -27,6 +27,8 @@
  #define PHY_ID_AQR112	0x03a1b662
+ #define PHY_ID_AQR412	0x03a1b712
+ #define PHY_ID_AQR113	0x31c31c40
 +#define PHY_ID_AQR112C	0x03a1b790
 +#define PHY_ID_AQR112R	0x31c31d12
- #define PHY_ID_AQR113	0x31c31c40
- #define PHY_ID_AQR113C	0x31c31c12
- #define PHY_ID_AQCS109	0x03a1b5c2
-@@ -915,6 +917,30 @@ static struct phy_driver aqr_driver[] =
+ 
+ #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
+ #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_MASK	GENMASK(7, 3)
+@@ -924,6 +926,30 @@ static struct phy_driver aqr_driver[] =
  	.get_stats	= aqr107_get_stats,
  },
  {
@@ -52,12 +52,12 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR113),
  	.name		= "Aquantia AQR113",
  	.config_aneg	= aqr_config_aneg,
-@@ -945,6 +971,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+@@ -960,6 +986,8 @@ static struct mdio_device_id __maybe_unu
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQCS109) },
+ 	{ }
+ };
+ 
diff --git a/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch b/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
index e14a5f17477..3d2c86169b6 100644
--- a/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
+++ b/target/linux/generic/hack-5.15/726-net-phy-aquantia-enable-AQR111-and-AQR111B0.patch
@@ -10,18 +10,18 @@ This is a 5GbE chip but it reports support for 10G. Implement config_init()
 to set max speed to 5G.
 
 Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
---- a/drivers/net/phy/aquantia_main.c
-+++ b/drivers/net/phy/aquantia_main.c
-@@ -20,6 +20,8 @@
- #define PHY_ID_AQR105	0x03a1b4a2
- #define PHY_ID_AQR106	0x03a1b4d0
- #define PHY_ID_AQR107	0x03a1b4e0
+--- a/drivers/net/phy/aquantia/aquantia_main.c
++++ b/drivers/net/phy/aquantia/aquantia_main.c
+@@ -24,6 +24,8 @@
+ #define PHY_ID_AQR405	0x03a1b4b0
+ #define PHY_ID_AQR113C	0x31c31c12
+ #define PHY_ID_AQR813	0x31c31cb2
 +#define PHY_ID_AQR111	0x03a1b610
 +#define PHY_ID_AQR111B0	0x03a1b612
  #define PHY_ID_AQR112	0x03a1b662
- #define PHY_ID_AQR112C	0x03a1b790
- #define PHY_ID_AQR112R	0x31c31d12
-@@ -686,6 +688,33 @@ static int aqcs109_config_init(struct ph
+ #define PHY_ID_AQR412	0x03a1b712
+ #define PHY_ID_AQR113	0x31c31c40
+@@ -676,6 +678,33 @@ static int aqcs109_config_init(struct ph
  	return aqr107_set_downshift(phydev, MDIO_AN_VEND_PROV_DOWNSHIFT_DFLT);
  }
  
@@ -55,7 +55,7 @@ Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
  static void aqr107_link_change_notify(struct phy_device *phydev)
  {
  	u8 fw_major, fw_minor;
-@@ -905,6 +934,42 @@ static struct phy_driver aqr_driver[] =
+@@ -914,6 +943,42 @@ static struct phy_driver aqr_driver[] =
  	.link_change_notify = aqr107_link_change_notify,
  },
  {
@@ -98,12 +98,12 @@ Signed-off-by: Thomas Kupper <thomas.kupper@gmail.com>
  	PHY_ID_MATCH_MODEL(PHY_ID_AQR112),
  	.name		= "Aquantia AQR112",
  	.probe		= aqr107_probe,
-@@ -970,6 +1035,8 @@ static struct mdio_device_id __maybe_unu
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR105) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR106) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR107) },
+@@ -983,6 +1048,8 @@ static struct mdio_device_id __maybe_unu
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR405) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113C) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR813) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111) },
 +	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR111B0) },
  	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112C) },
- 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR112R) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR412) },
+ 	{ PHY_ID_MATCH_MODEL(PHY_ID_AQR113) },
diff --git a/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch b/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch
index 26c5af8510e..5c5bd99b450 100644
--- a/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch
+++ b/target/linux/generic/hack-5.15/760-net-usb-r8152-add-LED-configuration-from-OF.patch
@@ -22,7 +22,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  #include <linux/crc32.h>
  #include <linux/if_vlan.h>
  #include <linux/uaccess.h>
-@@ -6980,6 +6981,22 @@ static void rtl_tally_reset(struct r8152
+@@ -6994,6 +6995,22 @@ static void rtl_tally_reset(struct r8152
  	ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data);
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  static void r8152b_init(struct r8152 *tp)
  {
  	u32 ocp_data;
-@@ -7021,6 +7038,8 @@ static void r8152b_init(struct r8152 *tp
+@@ -7035,6 +7052,8 @@ static void r8152b_init(struct r8152 *tp
  	ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
  	ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
  	ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
@@ -54,7 +54,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  }
  
  static void r8153_init(struct r8152 *tp)
-@@ -7161,6 +7180,8 @@ static void r8153_init(struct r8152 *tp)
+@@ -7175,6 +7194,8 @@ static void r8153_init(struct r8152 *tp)
  		tp->coalesce = COALESCE_SLOW;
  		break;
  	}
@@ -63,7 +63,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  }
  
  static void r8153b_init(struct r8152 *tp)
-@@ -7243,6 +7264,8 @@ static void r8153b_init(struct r8152 *tp
+@@ -7257,6 +7278,8 @@ static void r8153b_init(struct r8152 *tp
  	rtl_tally_reset(tp);
  
  	tp->coalesce = 15000;	/* 15 us */
diff --git a/target/linux/generic/hack-5.15/765-mxl-gpy-control-LED-reg-from-DT.patch b/target/linux/generic/hack-5.15/765-mxl-gpy-control-LED-reg-from-DT.patch
index 8de3668def2..95e9749d912 100644
--- a/target/linux/generic/hack-5.15/765-mxl-gpy-control-LED-reg-from-DT.patch
+++ b/target/linux/generic/hack-5.15/765-mxl-gpy-control-LED-reg-from-DT.patch
@@ -55,7 +55,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  /* SGMII */
  #define VSPEC1_SGMII_CTRL	0x08
  #define VSPEC1_SGMII_CTRL_ANEN	BIT(12)		/* Aneg enable */
-@@ -80,6 +87,31 @@ static const struct {
+@@ -80,6 +87,35 @@ static const struct {
  	{9, 0x73},
  };
  
@@ -64,6 +64,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 +	struct device_node *node = phydev->mdio.dev.of_node;
 +	u32 led_regs[PHY_LED_NUM_LEDS];
 +	int i, ret;
++	u16 val = 0xff00;
 +
 +	if (!IS_ENABLED(CONFIG_OF_MDIO))
 +		return 0;
@@ -71,8 +72,11 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
 +	if (of_property_read_u32_array(node, "mxl,led-config", led_regs, PHY_LED_NUM_LEDS))
 +		return 0;
 +
++	if (of_property_read_bool(node, "mxl,led-drive-vdd"))
++		val &= 0x0fff;
++
 +	/* Enable LED function handling on all ports*/
-+	phy_write(phydev, PHY_LED, 0xFF00);
++	phy_write(phydev, PHY_LED, val);
 +
 +	/* Write LED register values */
 +	for (i = 0; i < PHY_LED_NUM_LEDS; i++) {
@@ -87,7 +91,7 @@ Signed-off-by: David Bauer <mail@david-bauer.net>
  static int gpy_config_init(struct phy_device *phydev)
  {
  	int ret;
-@@ -91,7 +123,10 @@ static int gpy_config_init(struct phy_de
+@@ -91,7 +127,10 @@ static int gpy_config_init(struct phy_de
  
  	/* Clear all pending interrupts */
  	ret = phy_read(phydev, PHY_ISTAT);
diff --git a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
index 304f5480a3f..0060fbbd2ad 100644
--- a/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
+++ b/target/linux/generic/hack-5.15/780-usb-net-MeigLink_modem_support.patch
@@ -43,7 +43,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  
  #define QUECTEL_VENDOR_ID			0x2c7c
  /* These Quectel products use Quectel's vendor ID */
-@@ -1144,6 +1149,11 @@ static const struct usb_device_id option
+@@ -1147,6 +1152,11 @@ static const struct usb_device_id option
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x0023)}, /* ONYX 3G device */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000), /* SIMCom SIM5218 */
  	  .driver_info = NCTRL(0) | NCTRL(1) | NCTRL(2) | NCTRL(3) | RSVD(4) },
@@ -55,7 +55,7 @@ Subject: [PATCH] net/usb/qmi_wwan: add MeigLink modem support
  	/* Quectel products using Qualcomm vendor ID */
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC15)},
  	{ USB_DEVICE(QUALCOMM_VENDOR_ID, QUECTEL_PRODUCT_UC20),
-@@ -1185,6 +1195,11 @@ static const struct usb_device_id option
+@@ -1188,6 +1198,11 @@ static const struct usb_device_id option
  	  .driver_info = ZLP },
  	{ USB_DEVICE(QUECTEL_VENDOR_ID, QUECTEL_PRODUCT_BG96),
  	  .driver_info = RSVD(4) },
diff --git a/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch b/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch
index a463bf7c4eb..f93d84c6a43 100644
--- a/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch
+++ b/target/linux/generic/hack-5.15/795-backport-phylink_pcs-helpers.patch
@@ -57,7 +57,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  					  const unsigned long *advertising);
 --- a/drivers/net/phy/phylink.c
 +++ b/drivers/net/phy/phylink.c
-@@ -931,7 +931,6 @@ static int phylink_change_inband_advert(
+@@ -934,7 +934,6 @@ static int phylink_change_inband_advert(
  
  	return 0;
  }
@@ -65,7 +65,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  static void phylink_mac_pcs_get_state(struct phylink *pl,
  				      struct phylink_link_state *state)
  {
-@@ -3015,6 +3014,52 @@ void phylink_mii_c22_pcs_get_state(struc
+@@ -3019,6 +3018,52 @@ void phylink_mii_c22_pcs_get_state(struc
  EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_get_state);
  
  /**
@@ -118,7 +118,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
   * phylink_mii_c22_pcs_set_advertisement() - configure the clause 37 PCS
   *	advertisement
   * @pcs: a pointer to a &struct mdio_device.
-@@ -3086,6 +3131,46 @@ int phylink_mii_c22_pcs_set_advertisemen
+@@ -3090,6 +3135,46 @@ int phylink_mii_c22_pcs_set_advertisemen
  EXPORT_SYMBOL_GPL(phylink_mii_c22_pcs_set_advertisement);
  
  /**
diff --git a/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch b/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch
index f27b7ef9de5..258a5fb33c3 100644
--- a/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch
+++ b/target/linux/generic/hack-5.15/800-GPIO-add-named-gpio-exports.patch
@@ -157,7 +157,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  {
 --- a/drivers/gpio/gpiolib-sysfs.c
 +++ b/drivers/gpio/gpiolib-sysfs.c
-@@ -561,7 +561,7 @@ static struct class gpio_class = {
+@@ -564,7 +564,7 @@ static struct class gpio_class = {
   *
   * Returns zero on success, else an error.
   */
@@ -166,7 +166,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  {
  	struct gpio_chip	*chip;
  	struct gpio_device	*gdev;
-@@ -623,6 +623,8 @@ int gpiod_export(struct gpio_desc *desc,
+@@ -626,6 +626,8 @@ int gpiod_export(struct gpio_desc *desc,
  	offset = gpio_chip_hwgpio(desc);
  	if (chip->names && chip->names[offset])
  		ioname = chip->names[offset];
@@ -175,7 +175,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
  
  	dev = device_create_with_groups(&gpio_class, &gdev->dev,
  					MKDEV(0, 0), data, gpio_groups,
-@@ -644,6 +646,12 @@ err_unlock:
+@@ -647,6 +649,12 @@ err_unlock:
  	gpiod_dbg(desc, "%s: status %d\n", __func__, status);
  	return status;
  }
diff --git a/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch b/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch
index 11f4f556e86..ab4d636956e 100644
--- a/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-5.15/901-debloat_sock_diag.patch
@@ -77,7 +77,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -1987,9 +2001,11 @@ static void __sk_free(struct sock *sk)
+@@ -1994,9 +2008,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-5.15/902-debloat_proc.patch b/target/linux/generic/hack-5.15/902-debloat_proc.patch
index 768d3e1f0cf..dcdad4ca695 100644
--- a/target/linux/generic/hack-5.15/902-debloat_proc.patch
+++ b/target/linux/generic/hack-5.15/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -3881,6 +3881,8 @@ static __net_initdata struct pernet_oper
+@@ -3889,6 +3889,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/hack-6.1/251-kconfig.patch b/target/linux/generic/hack-6.1/251-kconfig.patch
index e1ecbca6fe3..fcf4eaf6e8d 100644
--- a/target/linux/generic/hack-6.1/251-kconfig.patch
+++ b/target/linux/generic/hack-6.1/251-kconfig.patch
@@ -124,59 +124,6 @@ Signed-off-by: John Crispin <john@phrozen.org>
  
  config NETFILTER_FAMILY_BRIDGE
  	bool
---- a/net/wireless/Kconfig
-+++ b/net/wireless/Kconfig
-@@ -1,6 +1,6 @@
- # SPDX-License-Identifier: GPL-2.0-only
- config WIRELESS_EXT
--	bool
-+	bool "Wireless extensions"
- 
- config WEXT_CORE
- 	def_bool y
-@@ -12,10 +12,10 @@ config WEXT_PROC
- 	depends on WEXT_CORE
- 
- config WEXT_SPY
--	bool
-+	bool "WEXT_SPY"
- 
- config WEXT_PRIV
--	bool
-+	bool "WEXT_PRIV"
- 
- config CFG80211
- 	tristate "cfg80211 - wireless configuration API"
-@@ -208,7 +208,7 @@ config CFG80211_WEXT_EXPORT
- endif # CFG80211
- 
- config LIB80211
--	tristate
-+	tristate "LIB80211"
- 	default n
- 	help
- 	  This options enables a library of common routines used
-@@ -217,17 +217,17 @@ config LIB80211
- 	  Drivers should select this themselves if needed.
- 
- config LIB80211_CRYPT_WEP
--	tristate
-+	tristate "LIB80211_CRYPT_WEP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_CRYPT_CCMP
--	tristate
-+	tristate "LIB80211_CRYPT_CCMP"
- 	select CRYPTO
- 	select CRYPTO_AES
- 	select CRYPTO_CCM
- 
- config LIB80211_CRYPT_TKIP
--	tristate
-+	tristate "LIB80211_CRYPT_TKIP"
- 	select CRYPTO_LIB_ARC4
- 
- config LIB80211_DEBUG
 --- a/sound/core/Kconfig
 +++ b/sound/core/Kconfig
 @@ -17,7 +17,7 @@ config SND_DMAENGINE_PCM
diff --git a/target/linux/generic/hack-6.1/301-arm64-cpuinfo-Add-model-name-in-proc-cpuinfo-for-64bit-ta.patch b/target/linux/generic/hack-6.1/301-arm64-cpuinfo-Add-model-name-in-proc-cpuinfo-for-64bit-ta.patch
new file mode 100644
index 00000000000..e5733d5cf0c
--- /dev/null
+++ b/target/linux/generic/hack-6.1/301-arm64-cpuinfo-Add-model-name-in-proc-cpuinfo-for-64bit-ta.patch
@@ -0,0 +1,38 @@
+From: Sumit Gupta <sumitg@nvidia.com>
+To: <catalin.marinas@arm.com>, <linux-arm-kernel@lists.infradead.org>,
+	<linux-kernel@vger.kernel.org>
+Cc: <will.deacon@arm.com>, <suzuki.poulose@arm.com>,
+	<james.morse@arm.com>, <mark.rutland@arm.com>,
+	<yang.shi@linaro.org>, <julien.grall@arm.com>,
+	<steve.capper@linaro.org>, <bbasu@nvidia.com>,
+	<linux-tegra@vger.kernel.org>, Sumit Gupta <sumitg@nvidia.com>
+Subject: [PATCH] arm64: cpuinfo: Add "model name" in /proc/cpuinfo for 64bit tasks also
+Date: Mon, 29 Aug 2016 14:32:25 +0530
+Message-ID: <1472461345-28219-1-git-send-email-sumitg@nvidia.com> (raw)
+
+Removed restriction of displaying model name for 32 bit tasks only.
+Because of this Processor details were not displayed in
+"System setting -> Details" in Ubuntu model name display is generic
+and can be printed for 64 bit also.
+
+model name : ARMv8 Processor rev X (v8l)
+
+Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
+---
+ arch/arm64/kernel/cpuinfo.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/arch/arm64/kernel/cpuinfo.c
++++ b/arch/arm64/kernel/cpuinfo.c
+@@ -170,9 +170,8 @@ static int c_show(struct seq_file *m, vo
+ 		 * "processor".  Give glibc what it expects.
+ 		 */
+ 		seq_printf(m, "processor\t: %d\n", i);
+-		if (compat)
+-			seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
+-				   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
++		seq_printf(m, "model name\t: ARMv8 Processor rev %d (%s)\n",
++			   MIDR_REVISION(midr), COMPAT_ELF_PLATFORM);
+ 
+ 		seq_printf(m, "BogoMIPS\t: %lu.%02lu\n",
+ 			   loops_per_jiffy / (500000UL/HZ),
diff --git a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch b/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
deleted file mode 100644
index 17eba0b354e..00000000000
--- a/target/linux/generic/hack-6.1/321-powerpc_crtsavres_prereq.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 107c0964cb8db7ca28ac5199426414fdab3c274d Mon Sep 17 00:00:00 2001
-From: "Alexandros C. Couloumbis" <alex@ozo.com>
-Date: Fri, 7 Jul 2017 17:14:51 +0200
-Subject: hack: arch: powerpc: drop register save/restore library from modules
-
-Upstream GCC uses a libgcc function for saving/restoring registers. This
-makes the code bigger, and upstream kernels need to carry that function
-for every single kernel module. Our GCC is patched to avoid those
-references, so we can drop the extra bloat for modules.
-
-lede-commit: e8e1084654f50904e6bf77b70b2de3f137d7b3ec
-Signed-off-by: Alexandros C. Couloumbis <alex@ozo.com>
----
- arch/powerpc/Makefile | 1 -
- 1 file changed, 1 deletion(-)
-
---- a/arch/powerpc/Makefile
-+++ b/arch/powerpc/Makefile
-@@ -42,19 +42,6 @@ machine-$(CONFIG_PPC64) += 64
- machine-$(CONFIG_CPU_LITTLE_ENDIAN) += le
- UTS_MACHINE := $(subst $(space),,$(machine-y))
- 
--# XXX This needs to be before we override LD below
--ifdef CONFIG_PPC32
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--else
--ifeq ($(call ld-ifversion, -ge, 22500, y),y)
--# Have the linker provide sfpr if possible.
--# There is a corresponding test in arch/powerpc/lib/Makefile
--KBUILD_LDFLAGS_MODULE += --save-restore-funcs
--else
--KBUILD_LDFLAGS_MODULE += arch/powerpc/lib/crtsavres.o
--endif
--endif
--
- ifdef CONFIG_CPU_LITTLE_ENDIAN
- KBUILD_CFLAGS	+= -mlittle-endian
- KBUILD_LDFLAGS	+= -EL
diff --git a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch b/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
deleted file mode 100644
index 1258f64722a..00000000000
--- a/target/linux/generic/hack-6.1/410-block-fit-partition-parser.patch
+++ /dev/null
@@ -1,217 +0,0 @@
-From 69357074558daf6ff24c9f58714935e9e095a865 Mon Sep 17 00:00:00 2001
-From: OpenWrt community <openwrt-devel@lists.openwrt.org>
-Date: Wed, 13 Jul 2022 13:37:33 +0200
-Subject: [PATCH] kernel: add block fit partition parser
-
----
- block/blk.h                     |  2 ++
- block/partitions/Kconfig        |  7 +++++++
- block/partitions/Makefile       |  1 +
- block/partitions/check.h        |  3 +++
- block/partitions/core.c         | 17 +++++++++++++++++
- block/partitions/efi.c          |  8 ++++++++
- block/partitions/efi.h          |  3 +++
- block/partitions/msdos.c        | 10 ++++++++++
- drivers/mtd/mtd_blkdevs.c       |  2 ++
- drivers/mtd/ubi/block.c         |  3 +++
- include/linux/msdos_partition.h |  1 +
- 11 files changed, 57 insertions(+)
-
---- a/block/blk.h
-+++ b/block/blk.h
-@@ -414,6 +414,8 @@ void blk_free_ext_minor(unsigned int min
- #define ADDPART_FLAG_NONE	0
- #define ADDPART_FLAG_RAID	1
- #define ADDPART_FLAG_WHOLEDISK	2
-+#define ADDPART_FLAG_READONLY	4
-+#define ADDPART_FLAG_ROOTDEV	8
- int bdev_add_partition(struct gendisk *disk, int partno, sector_t start,
- 		sector_t length);
- int bdev_del_partition(struct gendisk *disk, int partno);
---- a/block/partitions/Kconfig
-+++ b/block/partitions/Kconfig
-@@ -103,6 +103,13 @@ config ATARI_PARTITION
- 	  Say Y here if you would like to use hard disks under Linux which
- 	  were partitioned under the Atari OS.
- 
-+config FIT_PARTITION
-+	bool "Flattened-Image-Tree (FIT) partition support" if PARTITION_ADVANCED
-+	default n
-+	help
-+	  Say Y here if your system needs to mount the filesystem part of
-+	  a Flattened-Image-Tree (FIT) image commonly used with Das U-Boot.
-+
- config IBM_PARTITION
- 	bool "IBM disk label and partition support"
- 	depends on PARTITION_ADVANCED && S390
---- a/block/partitions/Makefile
-+++ b/block/partitions/Makefile
-@@ -8,6 +8,7 @@ obj-$(CONFIG_ACORN_PARTITION) += acorn.o
- obj-$(CONFIG_AMIGA_PARTITION) += amiga.o
- obj-$(CONFIG_ATARI_PARTITION) += atari.o
- obj-$(CONFIG_AIX_PARTITION) += aix.o
-+obj-$(CONFIG_FIT_PARTITION) += fit.o
- obj-$(CONFIG_CMDLINE_PARTITION) += cmdline.o
- obj-$(CONFIG_MAC_PARTITION) += mac.o
- obj-$(CONFIG_LDM_PARTITION) += ldm.o
---- a/block/partitions/check.h
-+++ b/block/partitions/check.h
-@@ -57,6 +57,7 @@ int amiga_partition(struct parsed_partit
- int atari_partition(struct parsed_partitions *state);
- int cmdline_partition(struct parsed_partitions *state);
- int efi_partition(struct parsed_partitions *state);
-+int fit_partition(struct parsed_partitions *state);
- int ibm_partition(struct parsed_partitions *);
- int karma_partition(struct parsed_partitions *state);
- int ldm_partition(struct parsed_partitions *state);
-@@ -67,3 +68,5 @@ int sgi_partition(struct parsed_partitio
- int sun_partition(struct parsed_partitions *state);
- int sysv68_partition(struct parsed_partitions *state);
- int ultrix_partition(struct parsed_partitions *state);
-+
-+int parse_fit_partitions(struct parsed_partitions *state, u64 start_sector, u64 nr_sectors, int *slot, int add_remain);
---- a/block/partitions/core.c
-+++ b/block/partitions/core.c
-@@ -10,6 +10,10 @@
- #include <linux/ctype.h>
- #include <linux/vmalloc.h>
- #include <linux/raid/detect.h>
-+#ifdef CONFIG_FIT_PARTITION
-+#include <linux/root_dev.h>
-+#endif
-+
- #include "check.h"
- 
- static int (*check_part[])(struct parsed_partitions *) = {
-@@ -46,6 +50,9 @@ static int (*check_part[])(struct parsed
- #ifdef CONFIG_EFI_PARTITION
- 	efi_partition,		/* this must come before msdos */
- #endif
-+#ifdef CONFIG_FIT_PARTITION
-+	fit_partition,
-+#endif
- #ifdef CONFIG_SGI_PARTITION
- 	sgi_partition,
- #endif
-@@ -398,6 +405,11 @@ static struct block_device *add_partitio
- 			goto out_del;
- 	}
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if (flags & ADDPART_FLAG_READONLY)
-+		bdev->bd_read_only = true;
-+#endif
-+
- 	/* everything is up and running, commence */
- 	err = xa_insert(&disk->part_tbl, partno, bdev, GFP_KERNEL);
- 	if (err)
-@@ -585,6 +597,11 @@ static bool blk_add_partition(struct gen
- 	    (state->parts[p].flags & ADDPART_FLAG_RAID))
- 		md_autodetect_dev(part->bd_dev);
- 
-+#ifdef CONFIG_FIT_PARTITION
-+	if ((state->parts[p].flags & ADDPART_FLAG_ROOTDEV) && ROOT_DEV == 0)
-+		ROOT_DEV = part->bd_dev;
-+#endif
-+
- 	return true;
- }
- 
---- a/block/partitions/efi.c
-+++ b/block/partitions/efi.c
-@@ -716,6 +716,9 @@ int efi_partition(struct parsed_partitio
- 	gpt_entry *ptes = NULL;
- 	u32 i;
- 	unsigned ssz = queue_logical_block_size(state->disk->queue) / 512;
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+#endif
- 
- 	if (!find_valid_gpt(state, &gpt, &ptes) || !gpt || !ptes) {
- 		kfree(gpt);
-@@ -749,6 +752,11 @@ int efi_partition(struct parsed_partitio
- 				ARRAY_SIZE(ptes[i].partition_name));
- 		utf16_le_to_7bit(ptes[i].partition_name, label_max, info->volname);
- 		state->parts[i + 1].has_info = true;
-+#ifdef CONFIG_FIT_PARTITION
-+		/* If this is a U-Boot FIT volume it may have subpartitions */
-+		if (!efi_guidcmp(ptes[i].partition_type_guid, PARTITION_LINUX_FIT_GUID))
-+			(void) parse_fit_partitions(state, start * ssz, size * ssz, &extra_slot, 1);
-+#endif
- 	}
- 	kfree(ptes);
- 	kfree(gpt);
---- a/block/partitions/efi.h
-+++ b/block/partitions/efi.h
-@@ -51,6 +51,9 @@
- #define PARTITION_LINUX_LVM_GUID \
-     EFI_GUID( 0xe6d6d379, 0xf507, 0x44c2, \
-               0xa2, 0x3c, 0x23, 0x8f, 0x2a, 0x3d, 0xf9, 0x28)
-+#define PARTITION_LINUX_FIT_GUID \
-+    EFI_GUID( 0xcae9be83, 0xb15f, 0x49cc, \
-+              0x86, 0x3f, 0x08, 0x1b, 0x74, 0x4a, 0x2d, 0x93)
- 
- typedef struct _gpt_header {
- 	__le64 signature;
---- a/block/partitions/msdos.c
-+++ b/block/partitions/msdos.c
-@@ -564,6 +564,15 @@ static void parse_minix(struct parsed_pa
- #endif /* CONFIG_MINIX_SUBPARTITION */
- }
- 
-+static void parse_fit_mbr(struct parsed_partitions *state,
-+			  sector_t offset, sector_t size, int origin)
-+{
-+#ifdef CONFIG_FIT_PARTITION
-+	u32 extra_slot = 64;
-+	(void) parse_fit_partitions(state, offset, size, &extra_slot, 1);
-+#endif /* CONFIG_FIT_PARTITION */
-+}
-+
- static struct {
- 	unsigned char id;
- 	void (*parse)(struct parsed_partitions *, sector_t, sector_t, int);
-@@ -575,6 +584,7 @@ static struct {
- 	{UNIXWARE_PARTITION, parse_unixware},
- 	{SOLARIS_X86_PARTITION, parse_solaris_x86},
- 	{NEW_SOLARIS_X86_PARTITION, parse_solaris_x86},
-+	{FIT_PARTITION, parse_fit_mbr},
- 	{0, NULL},
- };
- 
---- a/drivers/mtd/mtd_blkdevs.c
-+++ b/drivers/mtd/mtd_blkdevs.c
-@@ -359,7 +359,9 @@ int add_mtd_blktrans_dev(struct mtd_blkt
- 	} else {
- 		snprintf(gd->disk_name, sizeof(gd->disk_name),
- 			 "%s%d", tr->name, new->devnum);
--		gd->flags |= GENHD_FL_NO_PART;
-+
-+		if (!IS_ENABLED(CONFIG_FIT_PARTITION) || mtd_type_is_nand(new->mtd))
-+			gd->flags |= GENHD_FL_NO_PART;
- 	}
- 
- 	set_capacity(gd, ((u64)new->size * tr->blksize) >> 9);
---- a/drivers/mtd/ubi/block.c
-+++ b/drivers/mtd/ubi/block.c
-@@ -431,7 +431,9 @@ int ubiblock_create(struct ubi_volume_in
- 		ret = -ENODEV;
- 		goto out_cleanup_disk;
- 	}
--	gd->flags |= GENHD_FL_NO_PART;
-+	if (!IS_ENABLED(CONFIG_FIT_PARTITION))
-+		gd->flags |= GENHD_FL_NO_PART;
-+
- 	gd->private_data = dev;
- 	sprintf(gd->disk_name, "ubiblock%d_%d", dev->ubi_num, dev->vol_id);
- 	set_capacity(gd, disk_capacity);
---- a/include/linux/msdos_partition.h
-+++ b/include/linux/msdos_partition.h
-@@ -31,6 +31,7 @@ enum msdos_sys_ind {
- 	LINUX_LVM_PARTITION = 0x8e,
- 	LINUX_RAID_PARTITION = 0xfd,	/* autodetect RAID partition */
- 
-+	FIT_PARTITION = 0x2e,		/* U-Boot uImage.FIT */
- 	SOLARIS_X86_PARTITION =	0x82,	/* also Linux swap partitions */
- 	NEW_SOLARIS_X86_PARTITION = 0xbf,
- 
diff --git a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
index 9ff45a414ee..f753b590e70 100644
--- a/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
+++ b/target/linux/generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch
@@ -36,7 +36,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_NETFILTER_XT_TARGET_LED) += xt_LED.o
 --- /dev/null
 +++ b/net/netfilter/xt_FLOWOFFLOAD.c
-@@ -0,0 +1,698 @@
+@@ -0,0 +1,699 @@
 +/*
 + * Copyright (C) 2018-2021 Felix Fietkau <nbd@nbd.name>
 + *
@@ -574,6 +574,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +	if (!net)
 +		write_pnet(&table->ft.net, xt_net(par));
 +
++	__set_bit(NF_FLOW_HW_BIDIRECTIONAL, &flow->flags);
 +	if (flow_offload_add(&table->ft, flow) < 0)
 +		goto err_flow_add;
 +
diff --git a/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch b/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
index 5f49678a34b..673082d8408 100644
--- a/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
+++ b/target/linux/generic/hack-6.1/700-swconfig_switch_drivers.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -69,6 +69,80 @@ config SFP
+@@ -67,6 +67,80 @@ config SFP
  	depends on HWMON || HWMON=n
  	select MDIO_I2C
  
@@ -92,7 +92,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 +
  comment "MII PHY device drivers"
  
- config AMD_PHY
+ config AIR_EN8811H_PHY
 --- a/drivers/net/phy/Makefile
 +++ b/drivers/net/phy/Makefile
 @@ -24,6 +24,21 @@ libphy-$(CONFIG_LED_TRIGGER_PHY)	+= phy_
diff --git a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
index 40aeb5da6ff..b0be9dfdcbe 100644
--- a/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
+++ b/target/linux/generic/hack-6.1/721-net-add-packet-mangeling.patch
@@ -19,7 +19,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -1707,6 +1707,7 @@ enum netdev_priv_flags {
+@@ -1730,6 +1730,7 @@ enum netdev_priv_flags {
  	/* was IFF_LIVE_RENAME_OK */
  	IFF_TX_SKB_NO_LINEAR		= BIT_ULL(31),
  	IFF_CHANGE_PROTO_DOWN		= BIT_ULL(32),
@@ -27,7 +27,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  };
  
  #define IFF_802_1Q_VLAN			IFF_802_1Q_VLAN
-@@ -1740,6 +1741,7 @@ enum netdev_priv_flags {
+@@ -1763,6 +1764,7 @@ enum netdev_priv_flags {
  #define IFF_FAILOVER_SLAVE		IFF_FAILOVER_SLAVE
  #define IFF_L3MDEV_RX_HANDLER		IFF_L3MDEV_RX_HANDLER
  #define IFF_TX_SKB_NO_LINEAR		IFF_TX_SKB_NO_LINEAR
@@ -35,7 +35,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  /* Specifies the type of the struct net_device::ml_priv pointer */
  enum netdev_ml_priv_type {
-@@ -2108,6 +2110,11 @@ struct net_device {
+@@ -2131,6 +2133,11 @@ struct net_device {
  	const struct tlsdev_ops *tlsdev_ops;
  #endif
  
@@ -47,7 +47,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	const struct header_ops *header_ops;
  
  	unsigned char		operstate;
-@@ -2183,6 +2190,10 @@ struct net_device {
+@@ -2206,6 +2213,10 @@ struct net_device {
  	struct mctp_dev __rcu	*mctp_ptr;
  #endif
  
diff --git a/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch b/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
index 8b7f2f09557..a2bd3a3dbbc 100644
--- a/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
+++ b/target/linux/generic/hack-6.1/750-net-pcs-mtk-lynxi-workaround-2500BaseX-no-an.patch
@@ -13,7 +13,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/net/pcs/pcs-mtk-lynxi.c
 +++ b/drivers/net/pcs/pcs-mtk-lynxi.c
-@@ -92,14 +92,23 @@ static void mtk_pcs_lynxi_get_state(stru
+@@ -114,14 +114,23 @@ static void mtk_pcs_lynxi_get_state(stru
  				    struct phylink_link_state *state)
  {
  	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
@@ -40,14 +40,14 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	phylink_mii_c22_pcs_decode_state(state, bmsr, FIELD_GET(SGMII_LPA, adv));
  }
  
- static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int mode,
-@@ -134,7 +143,8 @@ static int mtk_pcs_lynxi_config(struct p
- 		/* 1000base-X or 2500base-X autoneg */
- 		sgm_mode = SGMII_REMOTE_FAULT_DIS;
- 		use_an = linkmode_test_bit(ETHTOOL_LINK_MODE_Autoneg_BIT,
--					   advertising);
-+					   advertising) &&
-+			 !(interface == PHY_INTERFACE_MODE_2500BASEX);
- 	} else {
- 		/* 1000base-X or 2500base-X without autoneg */
- 		sgm_mode = 0;
+ static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
+@@ -163,7 +172,8 @@ static int mtk_pcs_lynxi_config(struct p
+ 	if (neg_mode & PHYLINK_PCS_NEG_INBAND)
+ 		sgm_mode |= SGMII_REMOTE_FAULT_DIS;
+ 
+-	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED) {
++	if (neg_mode == PHYLINK_PCS_NEG_INBAND_ENABLED &&
++	    interface != PHY_INTERFACE_MODE_2500BASEX) {
+ 		if (interface == PHY_INTERFACE_MODE_SGMII)
+ 			sgm_mode |= SGMII_SPEED_DUPLEX_AN;
+ 		bmcr = BMCR_ANENABLE;
diff --git a/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch b/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
index 27c87d5b656..bb21bb39d39 100644
--- a/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
+++ b/target/linux/generic/hack-6.1/790-SFP-GE-T-ignore-TX_FAULT.patch
@@ -46,7 +46,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  		} else if (event == SFP_E_TIMEOUT || event == SFP_E_TX_CLEAR) {
  	init_done:
  			/* Create mdiobus and start trying for PHY */
-@@ -2573,10 +2577,12 @@ static void sfp_check_state(struct sfp *
+@@ -2578,10 +2582,12 @@ static void sfp_check_state(struct sfp *
  	mutex_lock(&sfp->st_mutex);
  	state = sfp_get_state(sfp);
  	changed = state ^ sfp->state;
diff --git a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
index ffa6e8ac60d..ec71f9af4be 100644
--- a/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
+++ b/target/linux/generic/hack-6.1/901-debloat_sock_diag.patch
@@ -44,7 +44,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  obj-$(CONFIG_PROC_FS) += net-procfs.o
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -114,6 +114,7 @@
+@@ -115,6 +115,7 @@
  #include <linux/memcontrol.h>
  #include <linux/prefetch.h>
  #include <linux/compat.h>
@@ -52,7 +52,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  #include <linux/uaccess.h>
  
-@@ -145,6 +146,7 @@
+@@ -146,6 +147,7 @@
  
  static DEFINE_MUTEX(proto_list_mutex);
  static LIST_HEAD(proto_list);
@@ -60,7 +60,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  static void sock_def_write_space_wfree(struct sock *sk);
  static void sock_def_write_space(struct sock *sk);
-@@ -584,6 +586,18 @@ discard_and_relse:
+@@ -585,6 +587,18 @@ discard_and_relse:
  }
  EXPORT_SYMBOL(__sk_receive_skb);
  
@@ -79,7 +79,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ip6_dst_check(struct dst_entry *,
  							  u32));
  INDIRECT_CALLABLE_DECLARE(struct dst_entry *ipv4_dst_check(struct dst_entry *,
-@@ -2187,9 +2201,11 @@ static void __sk_free(struct sock *sk)
+@@ -2188,9 +2202,11 @@ static void __sk_free(struct sock *sk)
  	if (likely(sk->sk_net_refcnt))
  		sock_inuse_add(sock_net(sk), -1);
  
diff --git a/target/linux/generic/hack-6.1/902-debloat_proc.patch b/target/linux/generic/hack-6.1/902-debloat_proc.patch
index 0d844994aae..a90169efc9c 100644
--- a/target/linux/generic/hack-6.1/902-debloat_proc.patch
+++ b/target/linux/generic/hack-6.1/902-debloat_proc.patch
@@ -330,7 +330,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
 --- a/net/core/sock.c
 +++ b/net/core/sock.c
-@@ -4113,6 +4113,8 @@ static __net_initdata struct pernet_oper
+@@ -4114,6 +4114,8 @@ static __net_initdata struct pernet_oper
  
  static int __init proto_init(void)
  {
diff --git a/target/linux/generic/pending-5.15/151-net-bridge-do-not-send-arp-replies-if-src-and-target.patch b/target/linux/generic/pending-5.15/151-net-bridge-do-not-send-arp-replies-if-src-and-target.patch
new file mode 100644
index 00000000000..f420d210c27
--- /dev/null
+++ b/target/linux/generic/pending-5.15/151-net-bridge-do-not-send-arp-replies-if-src-and-target.patch
@@ -0,0 +1,37 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Thu, 4 Jan 2024 15:21:21 +0100
+Subject: [PATCH] net: bridge: do not send arp replies if src and target hw
+ addr is the same
+
+There are broken devices in the wild that handle duplicate IP address
+detection by sending out ARP requests for the IP that they received from a
+DHCP server and refuse the address if they get a reply.
+When proxyarp is enabled, they would go into a loop of requesting an address
+and then NAKing it again.
+
+Link: https://github.com/openwrt/openwrt/issues/14309
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/bridge/br_arp_nd_proxy.c
++++ b/net/bridge/br_arp_nd_proxy.c
+@@ -204,7 +204,10 @@ void br_do_proxy_suppress_arp(struct sk_
+ 			if ((p && (p->flags & BR_PROXYARP)) ||
+ 			    (f->dst && (f->dst->flags & (BR_PROXYARP_WIFI |
+ 							 BR_NEIGH_SUPPRESS)))) {
+-				if (!vid)
++				replied = true;
++				if (!memcmp(n->ha, sha, dev->addr_len))
++					replied = false;
++				else if (!vid)
+ 					br_arp_send(br, p, skb->dev, sip, tip,
+ 						    sha, n->ha, sha, 0, 0);
+ 				else
+@@ -212,7 +215,6 @@ void br_do_proxy_suppress_arp(struct sk_
+ 						    sha, n->ha, sha,
+ 						    skb->vlan_proto,
+ 						    skb_vlan_tag_get(skb));
+-				replied = true;
+ 			}
+ 
+ 			/* If we have replied or as long as we know the
diff --git a/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch b/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch
index 0fcd415966e..be4dacf0945 100644
--- a/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch
+++ b/target/linux/generic/pending-5.15/300-mips_expose_boot_raw.patch
@@ -9,7 +9,7 @@ Acked-by: Rob Landley <rob@landley.net>
 ---
 --- a/arch/mips/Kconfig
 +++ b/arch/mips/Kconfig
-@@ -1102,9 +1102,6 @@ config FW_ARC
+@@ -1103,9 +1103,6 @@ config FW_ARC
  config ARCH_MAY_HAVE_PC_FDC
  	bool
  
@@ -19,7 +19,7 @@ Acked-by: Rob Landley <rob@landley.net>
  config CEVT_BCM1480
  	bool
  
-@@ -3184,6 +3181,18 @@ choice
+@@ -3186,6 +3183,18 @@ choice
  		bool "Extend builtin kernel arguments with bootloader arguments"
  endchoice
  
diff --git a/target/linux/generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch b/target/linux/generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch
new file mode 100644
index 00000000000..1bc0e724188
--- /dev/null
+++ b/target/linux/generic/pending-5.15/540-ksmbd-only-v2-leases-handle-the-directory.patch
@@ -0,0 +1,32 @@
+From cb1d41b99e4afa062f904339666fae2578559718 Mon Sep 17 00:00:00 2001
+From: Namjae Jeon <linkinjeon@kernel.org>
+Date: Mon, 15 Jan 2024 10:24:54 +0900
+Subject: [PATCH] ksmbd: only v2 leases handle the directory
+
+When smb2 leases is disable, ksmbd can send oplock break notification
+and cause wait oplock break ack timeout. It may appear like hang when
+accessing a directory. This patch make only v2 leases handle the
+directory.
+
+Cc: stable@vger.kernel.org
+Signed-off-by: Namjae Jeon <linkinjeon@kernel.org>
+Signed-off-by: Steve French <stfrench@microsoft.com>
+---
+ fs/ksmbd/oplock.c | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/fs/ksmbd/oplock.c
++++ b/fs/ksmbd/oplock.c
+@@ -1191,6 +1191,12 @@ int smb_grant_oplock(struct ksmbd_work *
+ 	bool prev_op_has_lease;
+ 	__le32 prev_op_state = 0;
+ 
++	/* Only v2 leases handle the directory */
++	if (S_ISDIR(file_inode(fp->filp)->i_mode)) {
++		if (!lctx || lctx->version != 2)
++			return 0;
++	}
++
+ 	opinfo = alloc_opinfo(work, pid, tid);
+ 	if (!opinfo)
+ 		return -ENOMEM;
diff --git a/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch b/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
index 7aaac965318..071a2ed3e5e 100644
--- a/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
+++ b/target/linux/generic/pending-5.15/670-ipv6-allow-rejecting-with-source-address-failed-policy.patch
@@ -157,7 +157,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	case RTN_THROW:
  	case RTN_UNREACHABLE:
  	default:
-@@ -4560,6 +4579,17 @@ static int ip6_pkt_prohibit_out(struct n
+@@ -4557,6 +4576,17 @@ static int ip6_pkt_prohibit_out(struct n
  	return ip6_pkt_drop(skb, ICMPV6_ADM_PROHIBITED, IPSTATS_MIB_OUTNOROUTES);
  }
  
@@ -175,7 +175,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  /*
   *	Allocate a dst for local (unicast / anycast) address.
   */
-@@ -5047,7 +5077,8 @@ static int rtm_to_fib6_config(struct sk_
+@@ -5044,7 +5074,8 @@ static int rtm_to_fib6_config(struct sk_
  	if (rtm->rtm_type == RTN_UNREACHABLE ||
  	    rtm->rtm_type == RTN_BLACKHOLE ||
  	    rtm->rtm_type == RTN_PROHIBIT ||
@@ -185,7 +185,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		cfg->fc_flags |= RTF_REJECT;
  
  	if (rtm->rtm_type == RTN_LOCAL)
-@@ -6301,6 +6332,8 @@ static int ip6_route_dev_notify(struct n
+@@ -6298,6 +6329,8 @@ static int ip6_route_dev_notify(struct n
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		net->ipv6.ip6_prohibit_entry->dst.dev = dev;
  		net->ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(dev);
@@ -194,7 +194,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		net->ipv6.ip6_blk_hole_entry->dst.dev = dev;
  		net->ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(dev);
  #endif
-@@ -6312,6 +6345,7 @@ static int ip6_route_dev_notify(struct n
+@@ -6309,6 +6342,7 @@ static int ip6_route_dev_notify(struct n
  		in6_dev_put_clear(&net->ipv6.ip6_null_entry->rt6i_idev);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  		in6_dev_put_clear(&net->ipv6.ip6_prohibit_entry->rt6i_idev);
@@ -202,7 +202,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  		in6_dev_put_clear(&net->ipv6.ip6_blk_hole_entry->rt6i_idev);
  #endif
  	}
-@@ -6503,6 +6537,8 @@ static int __net_init ip6_route_net_init
+@@ -6500,6 +6534,8 @@ static int __net_init ip6_route_net_init
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	net->ipv6.fib6_has_custom_rules = false;
@@ -211,7 +211,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_prohibit_entry = kmemdup(&ip6_prohibit_entry_template,
  					       sizeof(*net->ipv6.ip6_prohibit_entry),
  					       GFP_KERNEL);
-@@ -6513,11 +6549,21 @@ static int __net_init ip6_route_net_init
+@@ -6510,11 +6546,21 @@ static int __net_init ip6_route_net_init
  			 ip6_template_metrics, true);
  	INIT_LIST_HEAD(&net->ipv6.ip6_prohibit_entry->rt6i_uncached);
  
@@ -234,7 +234,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	net->ipv6.ip6_blk_hole_entry->dst.ops = &net->ipv6.ip6_dst_ops;
  	dst_init_metrics(&net->ipv6.ip6_blk_hole_entry->dst,
  			 ip6_template_metrics, true);
-@@ -6544,6 +6590,8 @@ out:
+@@ -6541,6 +6587,8 @@ out:
  	return ret;
  
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
@@ -243,7 +243,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  out_ip6_prohibit_entry:
  	kfree(net->ipv6.ip6_prohibit_entry);
  out_ip6_null_entry:
-@@ -6563,6 +6611,7 @@ static void __net_exit ip6_route_net_exi
+@@ -6560,6 +6608,7 @@ static void __net_exit ip6_route_net_exi
  	kfree(net->ipv6.ip6_null_entry);
  #ifdef CONFIG_IPV6_MULTIPLE_TABLES
  	kfree(net->ipv6.ip6_prohibit_entry);
@@ -251,7 +251,7 @@ Signed-off-by: Jonas Gorski <jogo@openwrt.org>
  	kfree(net->ipv6.ip6_blk_hole_entry);
  #endif
  	dst_entries_destroy(&net->ipv6.ip6_dst_ops);
-@@ -6646,6 +6695,9 @@ void __init ip6_route_init_special_entri
+@@ -6643,6 +6692,9 @@ void __init ip6_route_init_special_entri
  	init_net.ipv6.ip6_prohibit_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
  	init_net.ipv6.ip6_blk_hole_entry->dst.dev = init_net.loopback_dev;
  	init_net.ipv6.ip6_blk_hole_entry->rt6i_idev = in6_dev_get(init_net.loopback_dev);
diff --git a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 46856e1552f..c6a6c6e7978 100644
--- a/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-5.15/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -2098,6 +2098,8 @@ struct net_device {
+@@ -2099,6 +2099,8 @@ struct net_device {
  	struct netdev_hw_addr_list	mc;
  	struct netdev_hw_addr_list	dev_addrs;
  
@@ -32,7 +32,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	__u8			inner_protocol_type:1;
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -6074,6 +6074,9 @@ static enum gro_result dev_gro_receive(s
+@@ -6077,6 +6077,9 @@ static enum gro_result dev_gro_receive(s
  	int same_flow;
  	int grow;
  
@@ -42,7 +42,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	if (netif_elide_gro(skb->dev))
  		goto normal;
  
-@@ -8088,6 +8091,48 @@ static void __netdev_adjacent_dev_unlink
+@@ -8091,6 +8094,48 @@ static void __netdev_adjacent_dev_unlink
  					   &upper_dev->adj_list.lower);
  }
  
@@ -91,7 +91,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  static int __netdev_upper_dev_link(struct net_device *dev,
  				   struct net_device *upper_dev, bool master,
  				   void *upper_priv, void *upper_info,
-@@ -8139,6 +8184,7 @@ static int __netdev_upper_dev_link(struc
+@@ -8142,6 +8187,7 @@ static int __netdev_upper_dev_link(struc
  	if (ret)
  		return ret;
  
@@ -99,7 +99,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	ret = call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  					    &changeupper_info.info);
  	ret = notifier_to_errno(ret);
-@@ -8235,6 +8281,7 @@ static void __netdev_upper_dev_unlink(st
+@@ -8238,6 +8284,7 @@ static void __netdev_upper_dev_unlink(st
  
  	__netdev_adjacent_dev_unlink_neighbour(dev, upper_dev);
  
@@ -107,7 +107,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	call_netdevice_notifiers_info(NETDEV_CHANGEUPPER,
  				      &changeupper_info.info);
  
-@@ -9054,6 +9101,7 @@ int dev_set_mac_address(struct net_devic
+@@ -9057,6 +9104,7 @@ int dev_set_mac_address(struct net_devic
  	if (err)
  		return err;
  	dev->addr_assign_type = NET_ADDR_SET;
diff --git a/target/linux/generic/pending-5.15/682-of_net-add-mac-address-increment-support.patch b/target/linux/generic/pending-5.15/682-of_net-add-mac-address-increment-support.patch
deleted file mode 100644
index 73eabf4f376..00000000000
--- a/target/linux/generic/pending-5.15/682-of_net-add-mac-address-increment-support.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 844c273286f328acf0dab5fbd5d864366b4904dc Mon Sep 17 00:00:00 2001
-From: Ansuel Smith <ansuelsmth@gmail.com>
-Date: Tue, 30 Mar 2021 18:21:14 +0200
-Subject: [PATCH] of_net: add mac-address-increment support
-
-Lots of embedded devices use the mac-address of other interface
-extracted from nvmem cells and increments it by one or two. Add two
-bindings to integrate this and directly use the right mac-address for
-the interface. Some example are some routers that use the gmac
-mac-address stored in the art partition and increments it by one for the
-wifi. mac-address-increment-byte bindings is used to tell what byte of
-the mac-address has to be increased (if not defined the last byte is
-increased) and mac-address-increment tells how much the byte decided
-early has to be increased.
-
-Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
----
- net/core/of_net.c | 43 +++++++++++++++++++++++++++++++++++++++----
- 1 file changed, 39 insertions(+), 4 deletions(-)
-
---- a/net/core/of_net.c
-+++ b/net/core/of_net.c
-@@ -119,10 +119,19 @@ static int of_get_mac_addr_nvmem(struct
-  * this case, the real MAC is in 'local-mac-address', and 'mac-address' exists
-  * but is all zeros.
-  *
-+ * DT can tell the system to increment the mac-address after is extracted by
-+ * using:
-+ * - mac-address-increment to decide how much to increase. The value WILL
-+ *   overflow to other bytes if the increment is over 255 or the total
-+ *   increment will exceed 255 of the current byte.
-+ *   (example 00:01:02:03:04:ff + 1 == 00:01:02:03:05:00)
-+ *   (example 00:01:02:03:04:fe + 5 == 00:01:02:03:05:03)
-+ *
-  * Return: 0 on success and errno in case of error.
- */
- int of_get_mac_address(struct device_node *np, u8 *addr)
- {
-+	u32 mac_inc, mac_val;
- 	int ret;
- 
- 	if (!np)
-@@ -130,17 +139,33 @@ int of_get_mac_address(struct device_nod
- 
- 	ret = of_get_mac_addr(np, "mac-address", addr);
- 	if (!ret)
--		return 0;
-+		goto found;
- 
- 	ret = of_get_mac_addr(np, "local-mac-address", addr);
- 	if (!ret)
--		return 0;
-+		goto found;
- 
- 	ret = of_get_mac_addr(np, "address", addr);
- 	if (!ret)
--		return 0;
-+		goto found;
-+
-+	ret = of_get_mac_addr_nvmem(np, addr);
-+	if (ret)
-+		return ret;
-+
-+found:
-+	if (!of_property_read_u32(np, "mac-address-increment", &mac_inc)) {
-+		/* Convert to a contiguous value */
-+		mac_val = (addr[3] << 16) + (addr[4] << 8) + addr[5];
-+		mac_val += mac_inc;
-+
-+		/* Apply the incremented value handling overflow case */
-+		addr[3] = (mac_val >> 16) & 0xff;
-+		addr[4] = (mac_val >> 8) & 0xff;
-+		addr[5] = (mac_val >> 0) & 0xff;
-+	}
- 
--	return of_get_mac_addr_nvmem(np, addr);
-+	return ret;
- }
- EXPORT_SYMBOL(of_get_mac_address);
- 
diff --git a/target/linux/generic/pending-5.15/683-of_net-add-mac-address-to-of-tree.patch b/target/linux/generic/pending-5.15/683-of_net-add-mac-address-to-of-tree.patch
index 29144ce8b40..03ee537fb8f 100644
--- a/target/linux/generic/pending-5.15/683-of_net-add-mac-address-to-of-tree.patch
+++ b/target/linux/generic/pending-5.15/683-of_net-add-mac-address-to-of-tree.patch
@@ -45,11 +45,31 @@ property. This way, the MAC address can be accessed using procfs.
  /**
   * of_get_mac_address()
   * @np:		Caller's Device Node
-@@ -165,6 +186,7 @@ found:
- 		addr[5] = (mac_val >> 0) & 0xff;
- 	}
+@@ -130,17 +151,23 @@ int of_get_mac_address(struct device_nod
  
-+	of_add_mac_address(np, addr);
- 	return ret;
+ 	ret = of_get_mac_addr(np, "mac-address", addr);
+ 	if (!ret)
+-		return 0;
++		goto found;
+ 
+ 	ret = of_get_mac_addr(np, "local-mac-address", addr);
+ 	if (!ret)
+-		return 0;
++		goto found;
+ 
+ 	ret = of_get_mac_addr(np, "address", addr);
+ 	if (!ret)
+-		return 0;
++		goto found;
+ 
+-	return of_get_mac_addr_nvmem(np, addr);
++	ret = of_get_mac_addr_nvmem(np, addr);
++	if (ret)
++		return ret;
++
++found:
++	ret = of_add_mac_address(np, addr);
++	return ret;
  }
  EXPORT_SYMBOL(of_get_mac_address);
+ 
diff --git a/target/linux/generic/pending-5.15/684-of_net-do-mac-address-increment-only-once.patch b/target/linux/generic/pending-5.15/684-of_net-do-mac-address-increment-only-once.patch
deleted file mode 100644
index c37c4519899..00000000000
--- a/target/linux/generic/pending-5.15/684-of_net-do-mac-address-increment-only-once.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From dd07dd394d8bfdb5d527fab18ca54f20815ec4e4 Mon Sep 17 00:00:00 2001
-From: Will Moss <willormos@gmail.com>
-Date: Wed, 3 Aug 2022 13:48:55 +0000
-Subject: [PATCH] of_net: do mac-address-increment only once
-
-Remove mac-address-increment and mac-address-increment-byte
-DT property after incrementing process to make sure MAC address
-would not get incremented more if this function is stared again.
-It could happen if device initialization is deferred after
-unsuccessful attempt.
-
-Signed-off-by: Will Moss <willormos@gmail.com>
----
- drivers/of/of_net.c | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/net/core/of_net.c
-+++ b/net/core/of_net.c
-@@ -184,6 +184,11 @@ found:
- 		addr[3] = (mac_val >> 16) & 0xff;
- 		addr[4] = (mac_val >> 8) & 0xff;
- 		addr[5] = (mac_val >> 0) & 0xff;
-+
-+		/* Remove mac-address-increment DT property to make sure MAC
-+		 * address would not get incremented more if this function is
-+		 * stared again. */
-+		of_remove_property(np, of_find_property(np, "mac-address-increment", NULL));
- 	}
- 
- 	of_add_mac_address(np, addr);
diff --git a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index 8743d7f3671..892887c4236 100644
--- a/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-5.15/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -7708,7 +7708,7 @@ static int nft_register_flowtable_net_ho
+@@ -7752,7 +7752,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
index 67cff4d22ba..ca42728784e 100644
--- a/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
+++ b/target/linux/generic/pending-5.15/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -3099,8 +3099,8 @@ static irqreturn_t mtk_handle_irq_rx(int
+@@ -3100,8 +3100,8 @@ static irqreturn_t mtk_handle_irq_rx(int
  
  	eth->rx_events++;
  	if (likely(napi_schedule_prep(&eth->rx_napi))) {
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  
  	return IRQ_HANDLED;
-@@ -3112,8 +3112,8 @@ static irqreturn_t mtk_handle_irq_tx(int
+@@ -3113,8 +3113,8 @@ static irqreturn_t mtk_handle_irq_tx(int
  
  	eth->tx_events++;
  	if (likely(napi_schedule_prep(&eth->tx_napi))) {
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	}
  
  	return IRQ_HANDLED;
-@@ -4887,6 +4887,8 @@ static int mtk_probe(struct platform_dev
+@@ -4888,6 +4888,8 @@ static int mtk_probe(struct platform_dev
  	 * for NAPI to work
  	 */
  	init_dummy_netdev(&eth->dummy_dev);
diff --git a/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch
index 83587b5c931..f93dca68141 100644
--- a/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch
+++ b/target/linux/generic/pending-5.15/703-phy-add-detach-callback-to-struct-phy_driver.patch
@@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  			sysfs_remove_link(&dev->dev.kobj, "phydev");
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -843,6 +843,12 @@ struct phy_driver {
+@@ -868,6 +868,12 @@ struct phy_driver {
  	/** @handle_interrupt: Override default interrupt handling */
  	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
  
diff --git a/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
index 56edb632345..c9c9d13c955 100644
--- a/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
+++ b/target/linux/generic/pending-5.15/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1516,12 +1516,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1517,12 +1517,28 @@ static void mtk_wake_queue(struct mtk_et
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	bool gso = false;
  	int tx_num;
  
-@@ -1543,6 +1559,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1544,6 +1560,18 @@ static netdev_tx_t mtk_start_xmit(struct
  		return NETDEV_TX_BUSY;
  	}
  
@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* TSO: fill MSS info in tcp checksum field */
  	if (skb_is_gso(skb)) {
  		if (skb_cow_head(skb, 0)) {
-@@ -1558,8 +1586,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1559,8 +1587,14 @@ static netdev_tx_t mtk_start_xmit(struct
  		}
  	}
  
diff --git a/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch b/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
index cc6c9e91bf7..82a76b569ea 100644
--- a/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
+++ b/target/linux/generic/pending-5.15/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
@@ -22,7 +22,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -723,6 +723,7 @@ static void mtk_mac_link_up(struct phyli
+@@ -724,6 +724,7 @@ static void mtk_mac_link_up(struct phyli
  		 MAC_MCR_FORCE_RX_FC);
  
  	/* Configure speed */
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	switch (speed) {
  	case SPEED_2500:
  	case SPEED_1000:
-@@ -3292,6 +3293,9 @@ found:
+@@ -3293,6 +3294,9 @@ found:
  	if (dp->index >= MTK_QDMA_NUM_QUEUES)
  		return NOTIFY_DONE;
  
diff --git a/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch b/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch
index 104ce00b7eb..ed0a5442281 100644
--- a/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch
+++ b/target/linux/generic/pending-5.15/734-net-ethernet-mtk_eth_soc-ppe-fix-L2-offloading-with-.patch
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #include <net/dsa.h>
  #include "mtk_eth_soc.h"
  #include "mtk_ppe.h"
-@@ -781,7 +782,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe
+@@ -835,7 +836,9 @@ void __mtk_ppe_check_skb(struct mtk_ppe
  		    skb->dev->dsa_ptr->tag_ops->proto != DSA_TAG_PROTO_MTK)
  			goto out;
  
diff --git a/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
index b85b1364e18..29f565d312b 100644
--- a/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
+++ b/target/linux/generic/pending-5.15/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
@@ -249,7 +249,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 -
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -431,6 +431,30 @@ static void mtk_setup_bridge_switch(stru
+@@ -432,6 +432,30 @@ static void mtk_setup_bridge_switch(stru
  		MTK_GSW_CFG);
  }
  
@@ -280,7 +280,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
  					      phy_interface_t interface)
  {
-@@ -439,12 +463,20 @@ static struct phylink_pcs *mtk_mac_selec
+@@ -440,12 +464,20 @@ static struct phylink_pcs *mtk_mac_selec
  	struct mtk_eth *eth = mac->hw;
  	unsigned int sid;
  
@@ -307,7 +307,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	return NULL;
-@@ -500,7 +532,22 @@ static void mtk_mac_config(struct phylin
+@@ -501,7 +533,22 @@ static void mtk_mac_config(struct phylin
  					goto init_err;
  			}
  			break;
@@ -330,7 +330,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			break;
  		default:
  			goto err_phy;
-@@ -555,8 +602,6 @@ static void mtk_mac_config(struct phylin
+@@ -556,8 +603,6 @@ static void mtk_mac_config(struct phylin
  		val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
  		val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
  		regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
@@ -339,7 +339,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	/* SGMII */
-@@ -573,21 +618,40 @@ static void mtk_mac_config(struct phylin
+@@ -574,21 +619,40 @@ static void mtk_mac_config(struct phylin
  
  		/* Save the syscfg0 value for mac_finish */
  		mac->syscfg0 = val;
@@ -387,7 +387,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	return;
  
  err_phy:
-@@ -633,10 +697,13 @@ static void mtk_mac_link_down(struct phy
+@@ -634,10 +698,13 @@ static void mtk_mac_link_down(struct phy
  {
  	struct mtk_mac *mac = container_of(config, struct mtk_mac,
  					   phylink_config);
@@ -404,7 +404,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  }
  
  static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
-@@ -708,13 +775,11 @@ static void mtk_set_queue_speed(struct m
+@@ -709,13 +776,11 @@ static void mtk_set_queue_speed(struct m
  	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
  }
  
@@ -422,7 +422,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	u32 mcr;
  
  	mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
-@@ -748,6 +813,55 @@ static void mtk_mac_link_up(struct phyli
+@@ -749,6 +814,55 @@ static void mtk_mac_link_up(struct phyli
  	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
  }
  
@@ -478,7 +478,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  static const struct phylink_mac_ops mtk_phylink_ops = {
  	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
-@@ -4562,8 +4676,21 @@ static int mtk_add_mac(struct mtk_eth *e
+@@ -4563,8 +4677,21 @@ static int mtk_add_mac(struct mtk_eth *e
  		phy_interface_zero(mac->phylink_config.supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  mac->phylink_config.supported_interfaces);
@@ -500,7 +500,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4756,6 +4883,13 @@ static int mtk_probe(struct platform_dev
+@@ -4757,6 +4884,13 @@ static int mtk_probe(struct platform_dev
  
  		if (err)
  			return err;
diff --git a/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
new file mode 100644
index 00000000000..dda864ab4df
--- /dev/null
+++ b/target/linux/generic/pending-5.15/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
@@ -0,0 +1,46 @@
+From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
+Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 03:19:49 +0000
+Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
+ working
+To: Felix Fietkau <nbd@nbd.name>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Mark Lee <Mark-MC.Lee@mediatek.com>,
+    Lorenzo Bianconi <lorenzo@kernel.org>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Set DMA coherent mask to 32-bit which makes PPE offloading engine start
+working on BPi-R4 which got 4 GiB of RAM.
+
+Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
+Suggested-by: Elad Yifee <eladwf@users.github.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4832,7 +4832,10 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
+-		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
++		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
++		if (!err)
++			err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++
+ 		if (err) {
+ 			dev_err(&pdev->dev, "Wrong DMA config\n");
+ 			return -EINVAL;
diff --git a/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch
index 62daef91b15..c8d0bc69f93 100644
--- a/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-5.15/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  /**
   *	napi_disable - prevent NAPI from scheduling
-@@ -3363,6 +3364,7 @@ struct softnet_data {
+@@ -3364,6 +3365,7 @@ struct softnet_data {
  	unsigned int		processed;
  	unsigned int		time_squeeze;
  	unsigned int		received_rps;
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #endif
 --- a/net/core/dev.c
 +++ b/net/core/dev.c
-@@ -4583,7 +4583,7 @@ static int rps_ipi_queued(struct softnet
+@@ -4586,7 +4586,7 @@ static int rps_ipi_queued(struct softnet
  #ifdef CONFIG_RPS
  	struct softnet_data *mysd = this_cpu_ptr(&softnet_data);
  
@@ -39,7 +39,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		sd->rps_ipi_next = mysd->rps_ipi_list;
  		mysd->rps_ipi_list = sd;
  
-@@ -5764,6 +5764,8 @@ static DEFINE_PER_CPU(struct work_struct
+@@ -5767,6 +5767,8 @@ static DEFINE_PER_CPU(struct work_struct
  /* Network device is going away, flush any packets still pending */
  static void flush_backlog(struct work_struct *work)
  {
@@ -48,7 +48,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	struct sk_buff *skb, *tmp;
  	struct softnet_data *sd;
  
-@@ -5779,9 +5781,18 @@ static void flush_backlog(struct work_st
+@@ -5782,9 +5784,18 @@ static void flush_backlog(struct work_st
  			input_queue_head_incr(sd);
  		}
  	}
@@ -67,7 +67,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	skb_queue_walk_safe(&sd->process_queue, skb, tmp) {
  		if (skb->dev->reg_state == NETREG_UNREGISTERING) {
  			__skb_unlink(skb, &sd->process_queue);
-@@ -5789,7 +5800,18 @@ static void flush_backlog(struct work_st
+@@ -5792,7 +5803,18 @@ static void flush_backlog(struct work_st
  			input_queue_head_incr(sd);
  		}
  	}
@@ -86,7 +86,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  }
  
  static bool flush_required(int cpu)
-@@ -6472,6 +6494,7 @@ static int process_backlog(struct napi_s
+@@ -6475,6 +6497,7 @@ static int process_backlog(struct napi_s
  
  		local_irq_disable();
  		rps_lock(sd);
@@ -94,7 +94,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  		if (skb_queue_empty(&sd->input_pkt_queue)) {
  			/*
  			 * Inline a custom version of __napi_complete().
-@@ -6481,7 +6504,8 @@ static int process_backlog(struct napi_s
+@@ -6484,7 +6507,8 @@ static int process_backlog(struct napi_s
  			 * We can use a plain write instead of clear_bit(),
  			 * and we dont need an smp_mb() memory barrier.
  			 */
@@ -104,7 +104,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  			again = false;
  		} else {
  			skb_queue_splice_tail_init(&sd->input_pkt_queue,
-@@ -6898,6 +6922,57 @@ int dev_set_threaded(struct net_device *
+@@ -6901,6 +6925,57 @@ int dev_set_threaded(struct net_device *
  }
  EXPORT_SYMBOL(dev_set_threaded);
  
@@ -162,7 +162,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  void netif_napi_add(struct net_device *dev, struct napi_struct *napi,
  		    int (*poll)(struct napi_struct *, int), int weight)
  {
-@@ -11378,6 +11453,9 @@ static int dev_cpu_dead(unsigned int old
+@@ -11381,6 +11456,9 @@ static int dev_cpu_dead(unsigned int old
  	raise_softirq_irqoff(NET_TX_SOFTIRQ);
  	local_irq_enable();
  
@@ -172,7 +172,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11717,6 +11795,7 @@ static int __init net_dev_init(void)
+@@ -11720,6 +11798,7 @@ static int __init net_dev_init(void)
  		sd->cpu = i;
  #endif
  
diff --git a/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
new file mode 100644
index 00000000000..f2e91d3fe5f
--- /dev/null
+++ b/target/linux/generic/pending-5.15/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -0,0 +1,45 @@
+From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
+Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 04:17:11 +0000
+Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
+To: Arınç ÜNAL <arinc.unal@arinc9.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    DENG Qingfang <dqfext@gmail.com>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Florian Fainelli <f.fainelli@gmail.com>,
+    Vladimir Oltean <olteanv@gmail.com>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Setup PMCR port register for actual speed and duplex on internally
+connected PHYs of the MT7988 built-in switch. This fixes links with
+speeds other than 1000M.
+
+Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2832,8 +2832,7 @@ static void mt753x_phylink_mac_link_up(s
+ 	/* MT753x MAC works in 1G full duplex mode for all up-clocked
+ 	 * variants.
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_INTERNAL ||
+-	    interface == PHY_INTERFACE_MODE_TRGMII ||
++	if (interface == PHY_INTERFACE_MODE_TRGMII ||
+ 	    (phy_interface_mode_is_8023z(interface))) {
+ 		speed = SPEED_1000;
+ 		duplex = DUPLEX_FULL;
diff --git a/target/linux/generic/pending-5.15/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch b/target/linux/generic/pending-5.15/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch
index 9b111050eef..d07447bcba8 100644
--- a/target/linux/generic/pending-5.15/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch
+++ b/target/linux/generic/pending-5.15/802-nvmem-u-boot-env-align-endianness-of-crc32-values.patch
@@ -36,9 +36,9 @@ Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
 
 --- a/drivers/nvmem/u-boot-env.c
 +++ b/drivers/nvmem/u-boot-env.c
-@@ -182,7 +182,7 @@ static int u_boot_env_parse(struct u_boo
- 	crc32_data_len = priv->mtd->size - crc32_data_offset;
- 	data_len = priv->mtd->size - data_offset;
+@@ -181,7 +181,7 @@ static int u_boot_env_parse(struct u_boo
+ 	crc32_data_len = dev_size - crc32_data_offset;
+ 	data_len = dev_size - data_offset;
  
 -	calc = crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L;
 +	calc = le32_to_cpu((__le32)crc32(~0, buf + crc32_data_offset, crc32_data_len) ^ ~0L);
diff --git a/target/linux/generic/pending-5.15/803-nvmem-core-fix-support-for-fixed-cells-NVMEM-layout.patch b/target/linux/generic/pending-5.15/803-nvmem-core-fix-support-for-fixed-cells-NVMEM-layout.patch
deleted file mode 100644
index f403bbec9b1..00000000000
--- a/target/linux/generic/pending-5.15/803-nvmem-core-fix-support-for-fixed-cells-NVMEM-layout.patch
+++ /dev/null
@@ -1,40 +0,0 @@
-From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
-Date: Thu, 13 Jul 2023 17:30:59 +0200
-Subject: [PATCH] nvmem: core: fix support for fixed cells NVMEM layout
-MIME-Version: 1.0
-Content-Type: text/plain; charset=UTF-8
-Content-Transfer-Encoding: 8bit
-
-Returning -EPROBE_DEFER for "fixed-layout" makes nvmem_register() always
-fail (that layout is supported internally with no external module). That
-makes callers (e.g. mtd_nvmem_add()) fail as well and prevents booting
-on devices with "fixed-layout" in DT.
-
-Add a quick workaround for it.
-
-Fixes: 6468a6f45148 ("nvmem: core: handle the absence of expected layouts")
-Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
----
-
---- a/drivers/nvmem/core.c
-+++ b/drivers/nvmem/core.c
-@@ -798,6 +798,19 @@ static struct nvmem_layout *nvmem_layout
- 		return NULL;
- 
- 	/*
-+	 * We should return -EPROBE_DEFER only when layout driver is expected to
-+	 * become available later. Otherwise NVMEM will never probe successfully
-+	 * for unsupported layouts. There is no known solution for that right
-+	 * now.
-+	 *
-+	 * This problem also affects "fixed-layout". It's supported in NVMEM
-+	 * core code so there never will be layout for it. We shouldn't return
-+	 * -EPROBE_DEFER in such case. Add a quick workaround for that.
-+	 */
-+	if (of_device_is_compatible(layout_np, "fixed-layout"))
-+		return NULL;
-+
-+	/*
- 	 * In case the nvmem device was built-in while the layout was built as a
- 	 * module, we shall manually request the layout driver loading otherwise
- 	 * we'll never have any match.
diff --git a/target/linux/generic/pending-5.15/804-nvmem-core-support-mac-base-fixed-layout-cells.patch b/target/linux/generic/pending-5.15/804-nvmem-core-support-mac-base-fixed-layout-cells.patch
index 95f29b1865d..9bb94a28b54 100644
--- a/target/linux/generic/pending-5.15/804-nvmem-core-support-mac-base-fixed-layout-cells.patch
+++ b/target/linux/generic/pending-5.15/804-nvmem-core-support-mac-base-fixed-layout-cells.patch
@@ -15,9 +15,9 @@ string.
  menuconfig NVMEM
  	bool "NVMEM Support"
 +	select GENERIC_NET_UTILS
+ 	imply NVMEM_LAYOUTS
  	help
  	  Support for NVMEM(Non Volatile Memory) devices like EEPROM, EFUSES...
- 
 --- a/drivers/nvmem/core.c
 +++ b/drivers/nvmem/core.c
 @@ -7,9 +7,12 @@
@@ -33,7 +33,7 @@ string.
  #include <linux/init.h>
  #include <linux/kref.h>
  #include <linux/module.h>
-@@ -696,6 +699,62 @@ static int nvmem_validate_keepouts(struc
+@@ -780,6 +783,62 @@ static int nvmem_validate_keepouts(struc
  	return 0;
  }
  
@@ -95,10 +95,10 @@ string.
 +
  static int nvmem_add_cells_from_dt(struct nvmem_device *nvmem, struct device_node *np)
  {
- 	struct nvmem_layout *layout = nvmem->layout;
-@@ -731,6 +790,25 @@ static int nvmem_add_cells_from_dt(struc
- 		if (layout && layout->fixup_cell_info)
- 			layout->fixup_cell_info(nvmem, layout, &info);
+ 	struct device *dev = &nvmem->dev;
+@@ -814,6 +873,25 @@ static int nvmem_add_cells_from_dt(struc
+ 		if (nvmem->fixup_dt_cell_info)
+ 			nvmem->fixup_dt_cell_info(nvmem, &info);
  
 +		if (of_device_is_compatible(np, "fixed-layout")) {
 +			if (of_device_is_compatible(child, "mac-base")) {
diff --git a/target/linux/generic/pending-5.15/870-ARM-dts-nxp-imx7d-pico-add-cpu-supply-nodes.patch b/target/linux/generic/pending-5.15/870-ARM-dts-nxp-imx7d-pico-add-cpu-supply-nodes.patch
new file mode 100644
index 00000000000..186b052d40c
--- /dev/null
+++ b/target/linux/generic/pending-5.15/870-ARM-dts-nxp-imx7d-pico-add-cpu-supply-nodes.patch
@@ -0,0 +1,43 @@
+From 89a74fc5d367441bf4912e9158f0640ea3494b9e Mon Sep 17 00:00:00 2001
+From: Lech Perczak <lech.perczak@gmail.com>
+Date: Fri, 17 Nov 2023 21:33:04 +0100
+Subject: [PATCH] ARM: dts: nxp: imx7d-pico: add cpu-supply nodes
+
+The PICO-IMX7D SoM has the usual power supply configuration using
+output sw1a of PF3000 PMIC, which was defined in downstream derivative
+of linux-imx (see link) in the sources for "Android Things" devkit.
+It is required to support CPU frequency scaling.
+
+Map the respective "cpu-supply" nodes of each core to sw1a of the PMIC.
+
+Enabling them causes cpufreq-dt, and imx-thermal drivers to probe
+successfully, and CPU frequency scaling to function.
+
+Link: https://android.googlesource.com/platform/hardware/bsp/kernel/nxp/imx-v4.1/+/o-iot-preview-5/arch/arm/boot/dts/imx7d-pico.dtsi#849
+
+Cc: Fabio Estevam <festevam@gmail.com>
+Cc: Shawn Guo <shawnguo@kernel.org>
+Cc: Sascha Hauer <s.hauer@pengutronix.de>
+
+Signed-off-by: Lech Perczak <lech.perczak@gmail.com>
+---
+ arch/arm/boot/dts/imx7d-pico.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm/boot/dts/imx7d-pico.dtsi
++++ b/arch/arm/boot/dts/imx7d-pico.dtsi
+@@ -108,6 +108,14 @@
+ 	assigned-clock-rates = <0>, <32768>;
+ };
+ 
++&cpu0 {
++	cpu-supply = <&sw1a_reg>;
++};
++
++&cpu1 {
++	cpu-supply = <&sw1a_reg>;
++};
++
+ &ecspi3 {
+ 	cs-gpios = <&gpio4 11 GPIO_ACTIVE_LOW>;
+ 	pinctrl-names = "default";
diff --git a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch
index 7e1f26d243f..5f2bb8c37f4 100644
--- a/target/linux/generic/pending-5.15/920-mangle_bootargs.patch
+++ b/target/linux/generic/pending-5.15/920-mangle_bootargs.patch
@@ -31,7 +31,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  	help
 --- a/init/main.c
 +++ b/init/main.c
-@@ -614,6 +614,29 @@ static inline void setup_nr_cpu_ids(void
+@@ -618,6 +618,29 @@ static inline void setup_nr_cpu_ids(void
  static inline void smp_prepare_cpus(unsigned int maxcpus) { }
  #endif
  
@@ -61,7 +61,7 @@ Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
  /*
   * We need to store the untouched command line for future reference.
   * We also need to store the touched command line since the parameter
-@@ -953,6 +976,7 @@ asmlinkage __visible void __init __no_sa
+@@ -957,6 +980,7 @@ asmlinkage __visible void __init __no_sa
  	pr_notice("%s", linux_banner);
  	early_security_init();
  	setup_arch(&command_line);
diff --git a/target/linux/generic/pending-5.15/980-tools-thermal-tmon-Fix-compilation-warning-for-wrong.patch b/target/linux/generic/pending-5.15/980-tools-thermal-tmon-Fix-compilation-warning-for-wrong.patch
new file mode 100644
index 00000000000..6a0a19987fa
--- /dev/null
+++ b/target/linux/generic/pending-5.15/980-tools-thermal-tmon-Fix-compilation-warning-for-wrong.patch
@@ -0,0 +1,51 @@
+From a7a94ca21ac0f347f683d33c72b4aab57ce5eec3 Mon Sep 17 00:00:00 2001
+From: Florian Eckert <fe@dev.tdt.de>
+Date: Mon, 20 Nov 2023 11:13:20 +0100
+Subject: [PATCH] tools/thermal/tmon: Fix compilation warning for wrong format
+
+The following warnings are shown during compilation:
+
+tui.c: In function 'show_cooling_device':
+ tui.c:216:40: warning: format '%d' expects argument of type 'int', but
+argument 7 has type 'long unsigned int' [-Wformat=]
+   216 |                         "%02d %12.12s%6d %6d",
+       |                                      ~~^
+       |                                        |
+       |                                        int
+       |                                      %6ld
+ ......
+   219 |                         ptdata.cdi[j].cur_state,
+       |                         ~~~~~~~~~~~~~~~~~~~~~~~
+       |                                      |
+       |                                      long unsigned int
+ tui.c:216:44: warning: format '%d' expects argument of type 'int', but
+argument 8 has type 'long unsigned int' [-Wformat=]
+   216 |                         "%02d %12.12s%6d %6d",
+       |                                          ~~^
+       |                                            |
+       |                                            int
+       |                                          %6ld
+ ......
+   220 |                         ptdata.cdi[j].max_state);
+       |                         ~~~~~~~~~~~~~~~~~~~~~~~
+       |                                      |
+       |                                      long unsigned int
+
+To fix this, the correct string format must be used for printing.
+
+Signed-off-by: Florian Eckert <fe@dev.tdt.de>
+---
+ tools/thermal/tmon/tui.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/tools/thermal/tmon/tui.c
++++ b/tools/thermal/tmon/tui.c
+@@ -213,7 +213,7 @@ void show_cooling_device(void)
+ 		 * cooling device instances. skip unused idr.
+ 		 */
+ 		mvwprintw(cooling_device_window, j + 2, 1,
+-			"%02d %12.12s%6d %6d",
++			"%02d %12.12s%6lu %6lu",
+ 			ptdata.cdi[j].instance,
+ 			ptdata.cdi[j].type,
+ 			ptdata.cdi[j].cur_state,
diff --git a/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch b/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch
new file mode 100644
index 00000000000..063d3fa79c9
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-01-dt-bindings-mtd-add-basic-bindings-for-UBI.patch
@@ -0,0 +1,121 @@
+From ffbbe7d66872ff8957dad2136133e28a1fd5d437 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 22:51:05 +0100
+Subject: [PATCH 01/15] dt-bindings: mtd: add basic bindings for UBI
+
+Add basic bindings for UBI devices and volumes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/mtd/partitions/linux,ubi.yaml    | 65 +++++++++++++++++++
+ .../bindings/mtd/partitions/ubi-volume.yaml   | 35 ++++++++++
+ 2 files changed, 100 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+ create mode 100644 Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+@@ -0,0 +1,65 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/partitions/linux,ubi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Unsorted Block Images
++
++description: |
++  UBI ("Unsorted Block Images") is a volume management system for raw
++  flash devices which manages multiple logical volumes on a single
++  physical flash device and spreads the I/O load (i.e wear-leveling)
++  across the whole flash chip.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++allOf:
++  - $ref: partition.yaml#
++
++properties:
++  compatible:
++    const: linux,ubi
++
++  volumes:
++    type: object
++    description: UBI Volumes
++
++    patternProperties:
++      "^ubi-volume-.*$":
++        $ref: /schemas/mtd/partitions/ubi-volume.yaml#
++
++    unevaluatedProperties: false
++
++required:
++  - compatible
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    partitions {
++        compatible = "fixed-partitions";
++        #address-cells = <1>;
++        #size-cells = <1>;
++
++        partition@0 {
++            reg = <0x0 0x100000>;
++            label = "bootloader";
++            read-only;
++        };
++
++        partition@100000 {
++            reg = <0x100000 0x1ff00000>;
++            label = "ubi";
++            compatible = "linux,ubi";
++
++            volumes {
++                ubi-volume-caldata {
++                    volid = <2>;
++                    volname = "rf";
++                };
++            };
++        };
++    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+@@ -0,0 +1,35 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mtd/partitions/ubi-volume.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: UBI volume
++
++description: |
++  This binding describes a single UBI volume. Volumes can be matches either
++  by their ID or their name, or both.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  volid:
++    $ref: "/schemas/types.yaml#/definitions/uint32"
++    description:
++      Match UBI volume ID
++
++  volname:
++    $ref: "/schemas/types.yaml#/definitions/string"
++    description:
++      Match UBI volume ID
++
++anyOf:
++  - required:
++    - volid
++
++  - required:
++    - volname
++
++# This is a generic file other binding inherit from and extend
++additionalProperties: true
diff --git a/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch b/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch
new file mode 100644
index 00000000000..823c8e83b71
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-02-dt-bindings-mtd-ubi-volume-allow-UBI-volumes-to-prov.patch
@@ -0,0 +1,48 @@
+From e4dad3aa5c3ab9c553555dd23c0b85f725f2eb51 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 22:53:01 +0100
+Subject: [PATCH 02/15] dt-bindings: mtd: ubi-volume: allow UBI volumes to
+ provide NVMEM
+
+UBI volumes may be used to contain NVMEM bits, typically device MAC
+addresses or wireless radio calibration data.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../devicetree/bindings/mtd/partitions/linux,ubi.yaml  | 10 ++++++++++
+ .../devicetree/bindings/mtd/partitions/ubi-volume.yaml |  5 +++++
+ 2 files changed, 15 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
++++ b/Documentation/devicetree/bindings/mtd/partitions/linux,ubi.yaml
+@@ -59,6 +59,16 @@ examples:
+                 ubi-volume-caldata {
+                     volid = <2>;
+                     volname = "rf";
++
++                    nvmem-layout {
++                        compatible = "fixed-layout";
++                        #address-cells = <1>;
++                        #size-cells = <1>;
++
++                        eeprom@0 {
++                            reg = <0x0 0x1000>;
++                        };
++                    };
+                 };
+             };
+         };
+--- a/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
++++ b/Documentation/devicetree/bindings/mtd/partitions/ubi-volume.yaml
+@@ -24,6 +24,11 @@ properties:
+     description:
+       Match UBI volume ID
+ 
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++    description:
++      This container may reference an NVMEM layout parser.
++
+ anyOf:
+   - required:
+     - volid
diff --git a/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch b/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch
new file mode 100644
index 00000000000..eda3b108da3
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-03-mtd-ubi-block-use-notifier-to-create-ubiblock-from-p.patch
@@ -0,0 +1,225 @@
+From e5cf19bd8204925f3bd2067df9e867313eac388b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 1 May 2023 11:57:51 +0100
+Subject: [PATCH 03/15] mtd: ubi: block: use notifier to create ubiblock from
+ parameter
+
+Use UBI_VOLUME_ADDED notification to create ubiblock device specified
+on kernel cmdline or module parameter.
+This makes thing more simple and has the advantage that ubiblock devices
+on volumes which are not present at the time the ubi module is probed
+will still be created.
+
+Suggested-by: Zhihao Cheng <chengzhihao1@huawei.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 154 ++++++++++++++++++++++------------------
+ 1 file changed, 85 insertions(+), 69 deletions(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -33,6 +33,7 @@
+ #include <linux/kernel.h>
+ #include <linux/list.h>
+ #include <linux/mutex.h>
++#include <linux/namei.h>
+ #include <linux/slab.h>
+ #include <linux/mtd/ubi.h>
+ #include <linux/workqueue.h>
+@@ -67,10 +68,10 @@ struct ubiblock_pdu {
+ };
+ 
+ /* Numbers of elements set in the @ubiblock_param array */
+-static int ubiblock_devs __initdata;
++static int ubiblock_devs;
+ 
+ /* MTD devices specification parameters */
+-static struct ubiblock_param ubiblock_param[UBIBLOCK_MAX_DEVICES] __initdata;
++static struct ubiblock_param ubiblock_param[UBIBLOCK_MAX_DEVICES];
+ 
+ struct ubiblock {
+ 	struct ubi_volume_desc *desc;
+@@ -504,7 +505,7 @@ int ubiblock_remove(struct ubi_volume_in
+ 	}
+ 
+ 	/* Found a device, let's lock it so we can check if it's busy */
+-	mutex_lock(&dev->dev_mutex);
++	mutex_lock_nested(&dev->dev_mutex, SINGLE_DEPTH_NESTING);
+ 	if (dev->refcnt > 0) {
+ 		ret = -EBUSY;
+ 		goto out_unlock_dev;
+@@ -567,6 +568,85 @@ static int ubiblock_resize(struct ubi_vo
+ 	return 0;
+ }
+ 
++static bool
++match_volume_desc(struct ubi_volume_info *vi, const char *name, int ubi_num, int vol_id)
++{
++	int err, len;
++	struct path path;
++	struct kstat stat;
++
++	if (ubi_num == -1) {
++		/* No ubi num, name must be a vol device path */
++		err = kern_path(name, LOOKUP_FOLLOW, &path);
++		if (err)
++			return false;
++
++		err = vfs_getattr(&path, &stat, STATX_TYPE, AT_STATX_SYNC_AS_STAT);
++		path_put(&path);
++		if (err)
++			return false;
++
++		if (!S_ISCHR(stat.mode))
++			return false;
++
++		if (vi->ubi_num != ubi_major2num(MAJOR(stat.rdev)))
++			return false;
++
++		if (vi->vol_id != MINOR(stat.rdev) - 1)
++			return false;
++
++		return true;
++	}
++
++	if (vol_id == -1) {
++		if (vi->ubi_num != ubi_num)
++			return false;
++
++		len = strnlen(name, UBI_VOL_NAME_MAX + 1);
++		if (len < 1 || vi->name_len != len)
++			return false;
++
++		if (strcmp(name, vi->name))
++			return false;
++
++		return true;
++	}
++
++	if (vi->ubi_num != ubi_num)
++		return false;
++
++	if (vi->vol_id != vol_id)
++		return false;
++
++	return true;
++}
++
++static void
++ubiblock_create_from_param(struct ubi_volume_info *vi)
++{
++	int i, ret = 0;
++	struct ubiblock_param *p;
++
++	/*
++	 * Iterate over ubiblock cmdline parameters. If a parameter matches the
++	 * newly added volume create the ubiblock device for it.
++	 */
++	for (i = 0; i < ubiblock_devs; i++) {
++		p = &ubiblock_param[i];
++
++		if (!match_volume_desc(vi, p->name, p->ubi_num, p->vol_id))
++			continue;
++
++		ret = ubiblock_create(vi);
++		if (ret) {
++			pr_err(
++			       "UBI: block: can't add '%s' volume on ubi%d_%d, err=%d\n",
++			       vi->name, p->ubi_num, p->vol_id, ret);
++		}
++		break;
++	}
++}
++
+ static int ubiblock_notify(struct notifier_block *nb,
+ 			 unsigned long notification_type, void *ns_ptr)
+ {
+@@ -574,10 +654,7 @@ static int ubiblock_notify(struct notifi
+ 
+ 	switch (notification_type) {
+ 	case UBI_VOLUME_ADDED:
+-		/*
+-		 * We want to enforce explicit block device creation for
+-		 * volumes, so when a volume is added we do nothing.
+-		 */
++		ubiblock_create_from_param(&nt->vi);
+ 		break;
+ 	case UBI_VOLUME_REMOVED:
+ 		ubiblock_remove(&nt->vi);
+@@ -603,56 +680,6 @@ static struct notifier_block ubiblock_no
+ 	.notifier_call = ubiblock_notify,
+ };
+ 
+-static struct ubi_volume_desc * __init
+-open_volume_desc(const char *name, int ubi_num, int vol_id)
+-{
+-	if (ubi_num == -1)
+-		/* No ubi num, name must be a vol device path */
+-		return ubi_open_volume_path(name, UBI_READONLY);
+-	else if (vol_id == -1)
+-		/* No vol_id, must be vol_name */
+-		return ubi_open_volume_nm(ubi_num, name, UBI_READONLY);
+-	else
+-		return ubi_open_volume(ubi_num, vol_id, UBI_READONLY);
+-}
+-
+-static void __init ubiblock_create_from_param(void)
+-{
+-	int i, ret = 0;
+-	struct ubiblock_param *p;
+-	struct ubi_volume_desc *desc;
+-	struct ubi_volume_info vi;
+-
+-	/*
+-	 * If there is an error creating one of the ubiblocks, continue on to
+-	 * create the following ubiblocks. This helps in a circumstance where
+-	 * the kernel command-line specifies multiple block devices and some
+-	 * may be broken, but we still want the working ones to come up.
+-	 */
+-	for (i = 0; i < ubiblock_devs; i++) {
+-		p = &ubiblock_param[i];
+-
+-		desc = open_volume_desc(p->name, p->ubi_num, p->vol_id);
+-		if (IS_ERR(desc)) {
+-			pr_err(
+-			       "UBI: block: can't open volume on ubi%d_%d, err=%ld\n",
+-			       p->ubi_num, p->vol_id, PTR_ERR(desc));
+-			continue;
+-		}
+-
+-		ubi_get_volume_info(desc, &vi);
+-		ubi_close_volume(desc);
+-
+-		ret = ubiblock_create(&vi);
+-		if (ret) {
+-			pr_err(
+-			       "UBI: block: can't add '%s' volume on ubi%d_%d, err=%d\n",
+-			       vi.name, p->ubi_num, p->vol_id, ret);
+-			continue;
+-		}
+-	}
+-}
+-
+ static void ubiblock_remove_all(void)
+ {
+ 	struct ubiblock *next;
+@@ -678,18 +705,7 @@ int __init ubiblock_init(void)
+ 	if (ubiblock_major < 0)
+ 		return ubiblock_major;
+ 
+-	/*
+-	 * Attach block devices from 'block=' module param.
+-	 * Even if one block device in the param list fails to come up,
+-	 * still allow the module to load and leave any others up.
+-	 */
+-	ubiblock_create_from_param();
+-
+-	/*
+-	 * Block devices are only created upon user requests, so we ignore
+-	 * existing volumes.
+-	 */
+-	ret = ubi_register_volume_notifier(&ubiblock_notifier, 1);
++	ret = ubi_register_volume_notifier(&ubiblock_notifier, 0);
+ 	if (ret)
+ 		goto err_unreg;
+ 	return 0;
diff --git a/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch b/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch
new file mode 100644
index 00000000000..6e10e5ebed4
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-04-mtd-ubi-attach-from-device-tree.patch
@@ -0,0 +1,264 @@
+From 471a17d8d1b838092d1a76e48cdce8b5b67ff809 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 27 Nov 2023 01:54:28 +0000
+Subject: [PATCH 04/15] mtd: ubi: attach from device tree
+
+Introduce device tree compatible 'linux,ubi' and attach compatible MTD
+devices using the MTD add notifier. This is needed for a UBI device to
+be available early at boot (and not only after late_initcall), so
+volumes on them can be used eg. as NVMEM providers for other drivers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/build.c | 146 ++++++++++++++++++++++++++++------------
+ drivers/mtd/ubi/cdev.c  |   2 +-
+ drivers/mtd/ubi/ubi.h   |   2 +-
+ 3 files changed, 106 insertions(+), 44 deletions(-)
+
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -27,6 +27,7 @@
+ #include <linux/log2.h>
+ #include <linux/kthread.h>
+ #include <linux/kernel.h>
++#include <linux/of.h>
+ #include <linux/slab.h>
+ #include <linux/major.h>
+ #include "ubi.h"
+@@ -1071,6 +1072,7 @@ out_free:
+  * ubi_detach_mtd_dev - detach an MTD device.
+  * @ubi_num: UBI device number to detach from
+  * @anyway: detach MTD even if device reference count is not zero
++ * @have_lock: called by MTD notifier holding mtd_table_mutex
+  *
+  * This function destroys an UBI device number @ubi_num and detaches the
+  * underlying MTD device. Returns zero in case of success and %-EBUSY if the
+@@ -1080,7 +1082,7 @@ out_free:
+  * Note, the invocations of this function has to be serialized by the
+  * @ubi_devices_mutex.
+  */
+-int ubi_detach_mtd_dev(int ubi_num, int anyway)
++int ubi_detach_mtd_dev(int ubi_num, int anyway, bool have_lock)
+ {
+ 	struct ubi_device *ubi;
+ 
+@@ -1136,7 +1138,11 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 	vfree(ubi->peb_buf);
+ 	vfree(ubi->fm_buf);
+ 	ubi_msg(ubi, "mtd%d is detached", ubi->mtd->index);
+-	put_mtd_device(ubi->mtd);
++	if (have_lock)
++		__put_mtd_device(ubi->mtd);
++	else
++		put_mtd_device(ubi->mtd);
++
+ 	put_device(&ubi->dev);
+ 	return 0;
+ }
+@@ -1213,43 +1219,43 @@ static struct mtd_info * __init open_mtd
+ 	return mtd;
+ }
+ 
+-static int __init ubi_init(void)
++static void ubi_notify_add(struct mtd_info *mtd)
+ {
+-	int err, i, k;
++	struct device_node *np = mtd_get_of_node(mtd);
++	int err;
+ 
+-	/* Ensure that EC and VID headers have correct size */
+-	BUILD_BUG_ON(sizeof(struct ubi_ec_hdr) != 64);
+-	BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64);
++	if (!of_device_is_compatible(np, "linux,ubi"))
++		return;
+ 
+-	if (mtd_devs > UBI_MAX_DEVICES) {
+-		pr_err("UBI error: too many MTD devices, maximum is %d\n",
+-		       UBI_MAX_DEVICES);
+-		return -EINVAL;
+-	}
++	/*
++	 * we are already holding &mtd_table_mutex, but still need
++	 * to bump refcount
++	 */
++	err = __get_mtd_device(mtd);
++	if (err)
++		return;
+ 
+-	/* Create base sysfs directory and sysfs files */
+-	err = class_register(&ubi_class);
++	/* called while holding mtd_table_mutex */
++	mutex_lock_nested(&ubi_devices_mutex, SINGLE_DEPTH_NESTING);
++	err = ubi_attach_mtd_dev(mtd, UBI_DEV_NUM_AUTO, 0, 0, false);
++	mutex_unlock(&ubi_devices_mutex);
+ 	if (err < 0)
+-		return err;
+-
+-	err = misc_register(&ubi_ctrl_cdev);
+-	if (err) {
+-		pr_err("UBI error: cannot register device\n");
+-		goto out;
+-	}
++		__put_mtd_device(mtd);
++}
+ 
+-	ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab",
+-					      sizeof(struct ubi_wl_entry),
+-					      0, 0, NULL);
+-	if (!ubi_wl_entry_slab) {
+-		err = -ENOMEM;
+-		goto out_dev_unreg;
+-	}
++static void ubi_notify_remove(struct mtd_info *mtd)
++{
++	WARN(1, "mtd%d removed despite UBI still being attached", mtd->index);
++}
+ 
+-	err = ubi_debugfs_init();
+-	if (err)
+-		goto out_slab;
++static struct mtd_notifier ubi_mtd_notifier = {
++	.add = ubi_notify_add,
++	.remove = ubi_notify_remove,
++};
+ 
++static int __init ubi_init_attach(void)
++{
++	int err, i, k;
+ 
+ 	/* Attach MTD devices */
+ 	for (i = 0; i < mtd_devs; i++) {
+@@ -1297,25 +1303,79 @@ static int __init ubi_init(void)
+ 		}
+ 	}
+ 
++	return 0;
++
++out_detach:
++	for (k = 0; k < i; k++)
++		if (ubi_devices[k]) {
++			mutex_lock(&ubi_devices_mutex);
++			ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1, false);
++			mutex_unlock(&ubi_devices_mutex);
++		}
++	return err;
++}
++#ifndef CONFIG_MTD_UBI_MODULE
++late_initcall(ubi_init_attach);
++#endif
++
++static int __init ubi_init(void)
++{
++	int err;
++
++	/* Ensure that EC and VID headers have correct size */
++	BUILD_BUG_ON(sizeof(struct ubi_ec_hdr) != 64);
++	BUILD_BUG_ON(sizeof(struct ubi_vid_hdr) != 64);
++
++	if (mtd_devs > UBI_MAX_DEVICES) {
++		pr_err("UBI error: too many MTD devices, maximum is %d\n",
++		       UBI_MAX_DEVICES);
++		return -EINVAL;
++	}
++
++	/* Create base sysfs directory and sysfs files */
++	err = class_register(&ubi_class);
++	if (err < 0)
++		return err;
++
++	err = misc_register(&ubi_ctrl_cdev);
++	if (err) {
++		pr_err("UBI error: cannot register device\n");
++		goto out;
++	}
++
++	ubi_wl_entry_slab = kmem_cache_create("ubi_wl_entry_slab",
++					      sizeof(struct ubi_wl_entry),
++					      0, 0, NULL);
++	if (!ubi_wl_entry_slab) {
++		err = -ENOMEM;
++		goto out_dev_unreg;
++	}
++
++	err = ubi_debugfs_init();
++	if (err)
++		goto out_slab;
++
+ 	err = ubiblock_init();
+ 	if (err) {
+ 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
+ 
+ 		/* See comment above re-ubi_is_module(). */
+ 		if (ubi_is_module())
+-			goto out_detach;
++			goto out_slab;
++	}
++
++	register_mtd_user(&ubi_mtd_notifier);
++
++	if (ubi_is_module()) {
++		err = ubi_init_attach();
++		if (err)
++			goto out_mtd_notifier;
+ 	}
+ 
+ 	return 0;
+ 
+-out_detach:
+-	for (k = 0; k < i; k++)
+-		if (ubi_devices[k]) {
+-			mutex_lock(&ubi_devices_mutex);
+-			ubi_detach_mtd_dev(ubi_devices[k]->ubi_num, 1);
+-			mutex_unlock(&ubi_devices_mutex);
+-		}
+-	ubi_debugfs_exit();
++out_mtd_notifier:
++	unregister_mtd_user(&ubi_mtd_notifier);
+ out_slab:
+ 	kmem_cache_destroy(ubi_wl_entry_slab);
+ out_dev_unreg:
+@@ -1325,18 +1385,20 @@ out:
+ 	pr_err("UBI error: cannot initialize UBI, error %d\n", err);
+ 	return err;
+ }
+-late_initcall(ubi_init);
++device_initcall(ubi_init);
++
+ 
+ static void __exit ubi_exit(void)
+ {
+ 	int i;
+ 
+ 	ubiblock_exit();
++	unregister_mtd_user(&ubi_mtd_notifier);
+ 
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++)
+ 		if (ubi_devices[i]) {
+ 			mutex_lock(&ubi_devices_mutex);
+-			ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1);
++			ubi_detach_mtd_dev(ubi_devices[i]->ubi_num, 1, false);
+ 			mutex_unlock(&ubi_devices_mutex);
+ 		}
+ 	ubi_debugfs_exit();
+--- a/drivers/mtd/ubi/cdev.c
++++ b/drivers/mtd/ubi/cdev.c
+@@ -1065,7 +1065,7 @@ static long ctrl_cdev_ioctl(struct file
+ 		}
+ 
+ 		mutex_lock(&ubi_devices_mutex);
+-		err = ubi_detach_mtd_dev(ubi_num, 0);
++		err = ubi_detach_mtd_dev(ubi_num, 0, false);
+ 		mutex_unlock(&ubi_devices_mutex);
+ 		break;
+ 	}
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -939,7 +939,7 @@ int ubi_io_write_vid_hdr(struct ubi_devi
+ int ubi_attach_mtd_dev(struct mtd_info *mtd, int ubi_num,
+ 		       int vid_hdr_offset, int max_beb_per1024,
+ 		       bool disable_fm);
+-int ubi_detach_mtd_dev(int ubi_num, int anyway);
++int ubi_detach_mtd_dev(int ubi_num, int anyway, bool have_lock);
+ struct ubi_device *ubi_get_device(int ubi_num);
+ void ubi_put_device(struct ubi_device *ubi);
+ struct ubi_device *ubi_get_by_major(int major);
diff --git a/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch b/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch
new file mode 100644
index 00000000000..d5da37b8562
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-05-mtd-ubi-introduce-pre-removal-notification-for-UBI-v.patch
@@ -0,0 +1,226 @@
+From 2d664266cfdd114cc7a1fa28dd64275e99222455 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 8 Jun 2023 17:18:09 +0100
+Subject: [PATCH 05/15] mtd: ubi: introduce pre-removal notification for UBI
+ volumes
+
+Introduce a new notification type UBI_VOLUME_SHUTDOWN to inform users
+that a volume is just about to be removed.
+This is needed because users (such as the NVMEM subsystem) expect that
+at the time their removal function is called, the parenting device is
+still available (for removal of sysfs nodes, for example, in case of
+NVMEM which otherwise WARNs on volume removal).
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/block.c | 26 ++++++++++++++++++++++++++
+ drivers/mtd/ubi/build.c | 20 +++++++++++++++-----
+ drivers/mtd/ubi/kapi.c  |  2 +-
+ drivers/mtd/ubi/ubi.h   |  2 ++
+ drivers/mtd/ubi/vmt.c   | 17 +++++++++++++++--
+ include/linux/mtd/ubi.h |  2 ++
+ 6 files changed, 61 insertions(+), 8 deletions(-)
+
+--- a/drivers/mtd/ubi/block.c
++++ b/drivers/mtd/ubi/block.c
+@@ -568,6 +568,29 @@ static int ubiblock_resize(struct ubi_vo
+ 	return 0;
+ }
+ 
++static int ubiblock_shutdown(struct ubi_volume_info *vi)
++{
++	struct ubiblock *dev;
++	struct gendisk *disk;
++	int ret = 0;
++
++	mutex_lock(&devices_mutex);
++	dev = find_dev_nolock(vi->ubi_num, vi->vol_id);
++	if (!dev) {
++		ret = -ENODEV;
++		goto out_unlock;
++	}
++	disk = dev->gd;
++
++out_unlock:
++	mutex_unlock(&devices_mutex);
++
++	if (!ret)
++		blk_mark_disk_dead(disk);
++
++	return ret;
++};
++
+ static bool
+ match_volume_desc(struct ubi_volume_info *vi, const char *name, int ubi_num, int vol_id)
+ {
+@@ -659,6 +682,9 @@ static int ubiblock_notify(struct notifi
+ 	case UBI_VOLUME_REMOVED:
+ 		ubiblock_remove(&nt->vi);
+ 		break;
++	case UBI_VOLUME_SHUTDOWN:
++		ubiblock_shutdown(&nt->vi);
++		break;
+ 	case UBI_VOLUME_RESIZED:
+ 		ubiblock_resize(&nt->vi);
+ 		break;
+--- a/drivers/mtd/ubi/build.c
++++ b/drivers/mtd/ubi/build.c
+@@ -89,7 +89,7 @@ static struct ubi_device *ubi_devices[UB
+ /* Serializes UBI devices creations and removals */
+ DEFINE_MUTEX(ubi_devices_mutex);
+ 
+-/* Protects @ubi_devices and @ubi->ref_count */
++/* Protects @ubi_devices, @ubi->ref_count and @ubi->is_dead */
+ static DEFINE_SPINLOCK(ubi_devices_lock);
+ 
+ /* "Show" method for files in '/<sysfs>/class/ubi/' */
+@@ -258,6 +258,9 @@ struct ubi_device *ubi_get_device(int ub
+ 
+ 	spin_lock(&ubi_devices_lock);
+ 	ubi = ubi_devices[ubi_num];
++	if (ubi && ubi->is_dead)
++		ubi = NULL;
++
+ 	if (ubi) {
+ 		ubi_assert(ubi->ref_count >= 0);
+ 		ubi->ref_count += 1;
+@@ -295,7 +298,7 @@ struct ubi_device *ubi_get_by_major(int
+ 	spin_lock(&ubi_devices_lock);
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++) {
+ 		ubi = ubi_devices[i];
+-		if (ubi && MAJOR(ubi->cdev.dev) == major) {
++		if (ubi && !ubi->is_dead && MAJOR(ubi->cdev.dev) == major) {
+ 			ubi_assert(ubi->ref_count >= 0);
+ 			ubi->ref_count += 1;
+ 			get_device(&ubi->dev);
+@@ -324,7 +327,7 @@ int ubi_major2num(int major)
+ 	for (i = 0; i < UBI_MAX_DEVICES; i++) {
+ 		struct ubi_device *ubi = ubi_devices[i];
+ 
+-		if (ubi && MAJOR(ubi->cdev.dev) == major) {
++		if (ubi && !ubi->is_dead && MAJOR(ubi->cdev.dev) == major) {
+ 			ubi_num = ubi->ubi_num;
+ 			break;
+ 		}
+@@ -511,7 +514,7 @@ static void ubi_free_volumes_from(struct
+ 	int i;
+ 
+ 	for (i = from; i < ubi->vtbl_slots + UBI_INT_VOL_COUNT; i++) {
+-		if (!ubi->volumes[i])
++		if (!ubi->volumes[i] || ubi->volumes[i]->is_dead)
+ 			continue;
+ 		ubi_eba_replace_table(ubi->volumes[i], NULL);
+ 		ubi_fastmap_destroy_checkmap(ubi->volumes[i]);
+@@ -1094,10 +1097,10 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 		return -EINVAL;
+ 
+ 	spin_lock(&ubi_devices_lock);
+-	put_device(&ubi->dev);
+ 	ubi->ref_count -= 1;
+ 	if (ubi->ref_count) {
+ 		if (!anyway) {
++			ubi->ref_count += 1;
+ 			spin_unlock(&ubi_devices_lock);
+ 			return -EBUSY;
+ 		}
+@@ -1105,6 +1108,13 @@ int ubi_detach_mtd_dev(int ubi_num, int
+ 		ubi_err(ubi, "%s reference count %d, destroy anyway",
+ 			ubi->ubi_name, ubi->ref_count);
+ 	}
++	ubi->is_dead = true;
++	spin_unlock(&ubi_devices_lock);
++
++	ubi_notify_all(ubi, UBI_VOLUME_SHUTDOWN, NULL);
++
++	spin_lock(&ubi_devices_lock);
++	put_device(&ubi->dev);
+ 	ubi_devices[ubi_num] = NULL;
+ 	spin_unlock(&ubi_devices_lock);
+ 
+--- a/drivers/mtd/ubi/kapi.c
++++ b/drivers/mtd/ubi/kapi.c
+@@ -152,7 +152,7 @@ struct ubi_volume_desc *ubi_open_volume(
+ 
+ 	spin_lock(&ubi->volumes_lock);
+ 	vol = ubi->volumes[vol_id];
+-	if (!vol)
++	if (!vol || vol->is_dead)
+ 		goto out_unlock;
+ 
+ 	err = -EBUSY;
+--- a/drivers/mtd/ubi/ubi.h
++++ b/drivers/mtd/ubi/ubi.h
+@@ -345,6 +345,7 @@ struct ubi_volume {
+ 	int writers;
+ 	int exclusive;
+ 	int metaonly;
++	bool is_dead;
+ 
+ 	int reserved_pebs;
+ 	int vol_type;
+@@ -564,6 +565,7 @@ struct ubi_device {
+ 	spinlock_t volumes_lock;
+ 	int ref_count;
+ 	int image_seq;
++	bool is_dead;
+ 
+ 	int rsvd_pebs;
+ 	int avail_pebs;
+--- a/drivers/mtd/ubi/vmt.c
++++ b/drivers/mtd/ubi/vmt.c
+@@ -59,7 +59,7 @@ static ssize_t vol_attribute_show(struct
+ 	struct ubi_device *ubi = vol->ubi;
+ 
+ 	spin_lock(&ubi->volumes_lock);
+-	if (!ubi->volumes[vol->vol_id]) {
++	if (!ubi->volumes[vol->vol_id] || ubi->volumes[vol->vol_id]->is_dead) {
+ 		spin_unlock(&ubi->volumes_lock);
+ 		return -ENODEV;
+ 	}
+@@ -189,7 +189,7 @@ int ubi_create_volume(struct ubi_device
+ 
+ 	/* Ensure that the name is unique */
+ 	for (i = 0; i < ubi->vtbl_slots; i++)
+-		if (ubi->volumes[i] &&
++		if (ubi->volumes[i] && !ubi->volumes[i]->is_dead &&
+ 		    ubi->volumes[i]->name_len == req->name_len &&
+ 		    !strcmp(ubi->volumes[i]->name, req->name)) {
+ 			ubi_err(ubi, "volume \"%s\" exists (ID %d)",
+@@ -352,6 +352,19 @@ int ubi_remove_volume(struct ubi_volume_
+ 		err = -EBUSY;
+ 		goto out_unlock;
+ 	}
++
++	/*
++	 * Mark volume as dead at this point to prevent that anyone
++	 * can take a reference to the volume from now on.
++	 * This is necessary as we have to release the spinlock before
++	 * calling ubi_volume_notify.
++	 */
++	vol->is_dead = true;
++	spin_unlock(&ubi->volumes_lock);
++
++	ubi_volume_notify(ubi, vol, UBI_VOLUME_SHUTDOWN);
++
++	spin_lock(&ubi->volumes_lock);
+ 	ubi->volumes[vol_id] = NULL;
+ 	spin_unlock(&ubi->volumes_lock);
+ 
+--- a/include/linux/mtd/ubi.h
++++ b/include/linux/mtd/ubi.h
+@@ -192,6 +192,7 @@ struct ubi_device_info {
+  *			or a volume was removed)
+  * @UBI_VOLUME_RESIZED: a volume has been re-sized
+  * @UBI_VOLUME_RENAMED: a volume has been re-named
++ * @UBI_VOLUME_SHUTDOWN: a volume is going to removed, shutdown users
+  * @UBI_VOLUME_UPDATED: data has been written to a volume
+  *
+  * These constants define which type of event has happened when a volume
+@@ -202,6 +203,7 @@ enum {
+ 	UBI_VOLUME_REMOVED,
+ 	UBI_VOLUME_RESIZED,
+ 	UBI_VOLUME_RENAMED,
++	UBI_VOLUME_SHUTDOWN,
+ 	UBI_VOLUME_UPDATED,
+ };
+ 
diff --git a/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch b/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch
new file mode 100644
index 00000000000..13227669654
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-06-mtd-ubi-populate-ubi-volume-fwnode.patch
@@ -0,0 +1,65 @@
+From 3a041ee543cdf2e707a1dd72946cd6a583509b28 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Jul 2023 19:26:37 +0100
+Subject: [PATCH 06/15] mtd: ubi: populate ubi volume fwnode
+
+Look for the 'volumes' subnode of an MTD partition attached to a UBI
+device and attach matching child nodes to UBI volumes.
+This allows UBI volumes to be referenced in device tree, e.g. for use
+as NVMEM providers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/vmt.c | 27 +++++++++++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/drivers/mtd/ubi/vmt.c
++++ b/drivers/mtd/ubi/vmt.c
+@@ -124,6 +124,31 @@ static void vol_release(struct device *d
+ 	kfree(vol);
+ }
+ 
++static struct fwnode_handle *find_volume_fwnode(struct ubi_volume *vol)
++{
++	struct fwnode_handle *fw_vols, *fw_vol;
++	const char *volname;
++	u32 volid;
++
++	fw_vols = device_get_named_child_node(vol->dev.parent->parent, "volumes");
++	if (!fw_vols)
++		return NULL;
++
++	fwnode_for_each_child_node(fw_vols, fw_vol) {
++		if (!fwnode_property_read_string(fw_vol, "volname", &volname) &&
++		    strncmp(volname, vol->name, vol->name_len))
++			continue;
++
++		if (!fwnode_property_read_u32(fw_vol, "volid", &volid) &&
++		    vol->vol_id != volid)
++			continue;
++
++		return fw_vol;
++	}
++
++	return NULL;
++}
++
+ /**
+  * ubi_create_volume - create volume.
+  * @ubi: UBI device description object
+@@ -223,6 +248,7 @@ int ubi_create_volume(struct ubi_device
+ 	vol->name_len  = req->name_len;
+ 	memcpy(vol->name, req->name, vol->name_len);
+ 	vol->ubi = ubi;
++	device_set_node(&vol->dev, find_volume_fwnode(vol));
+ 
+ 	/*
+ 	 * Finish all pending erases because there may be some LEBs belonging
+@@ -605,6 +631,7 @@ int ubi_add_volume(struct ubi_device *ub
+ 	vol->dev.class = &ubi_class;
+ 	vol->dev.groups = volume_dev_groups;
+ 	dev_set_name(&vol->dev, "%s_%d", ubi->ubi_name, vol->vol_id);
++	device_set_node(&vol->dev, find_volume_fwnode(vol));
+ 	err = device_register(&vol->dev);
+ 	if (err) {
+ 		cdev_del(&vol->cdev);
diff --git a/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch b/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch
new file mode 100644
index 00000000000..9e6fbea38cf
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-07-mtd-ubi-provide-NVMEM-layer-over-UBI-volumes.patch
@@ -0,0 +1,243 @@
+From 7eb6666348f3f2d1f7308c712fa5903cbe189401 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 8 Jun 2023 17:22:04 +0100
+Subject: [PATCH 07/15] mtd: ubi: provide NVMEM layer over UBI volumes
+
+In an ideal world we would like UBI to be used where ever possible on a
+NAND chip. And with UBI support in ARM Trusted Firmware and U-Boot it
+is possible to achieve an (almost-)all-UBI flash layout. Hence the need
+for a way to also use UBI volumes to store board-level constants, such
+as MAC addresses and calibration data of wireless interfaces.
+
+Add UBI volume NVMEM driver module exposing UBI volumes as NVMEM
+providers. Allow UBI devices to have a "volumes" firmware subnode with
+volumes which may be compatible with "nvmem-cells".
+Access to UBI volumes via the NVMEM interface at this point is
+read-only, and it is slow, opening and closing the UBI volume for each
+access due to limitations of the NVMEM provider API.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mtd/ubi/Kconfig  |  12 +++
+ drivers/mtd/ubi/Makefile |   1 +
+ drivers/mtd/ubi/nvmem.c  | 188 +++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 201 insertions(+)
+ create mode 100644 drivers/mtd/ubi/nvmem.c
+
+--- a/drivers/mtd/ubi/Kconfig
++++ b/drivers/mtd/ubi/Kconfig
+@@ -104,4 +104,16 @@ config MTD_UBI_BLOCK
+ 
+ 	   If in doubt, say "N".
+ 
++config MTD_UBI_NVMEM
++	tristate "UBI virtual NVMEM"
++	default n
++	depends on NVMEM
++	help
++	   This option enabled an additional driver exposing UBI volumes as NVMEM
++	   providers, intended for platforms where UBI is part of the firmware
++	   specification and used to store also e.g. MAC addresses or board-
++	   specific Wi-Fi calibration data.
++
++	   If in doubt, say "N".
++
+ endif # MTD_UBI
+--- a/drivers/mtd/ubi/Makefile
++++ b/drivers/mtd/ubi/Makefile
+@@ -7,3 +7,4 @@ ubi-$(CONFIG_MTD_UBI_FASTMAP) += fastmap
+ ubi-$(CONFIG_MTD_UBI_BLOCK) += block.o
+ 
+ obj-$(CONFIG_MTD_UBI_GLUEBI) += gluebi.o
++obj-$(CONFIG_MTD_UBI_NVMEM) += nvmem.o
+--- /dev/null
++++ b/drivers/mtd/ubi/nvmem.c
+@@ -0,0 +1,188 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ */
++
++/* UBI NVMEM provider */
++#include "ubi.h"
++#include <linux/nvmem-provider.h>
++#include <asm/div64.h>
++
++/* List of all NVMEM devices */
++static LIST_HEAD(nvmem_devices);
++static DEFINE_MUTEX(devices_mutex);
++
++struct ubi_nvmem {
++	struct nvmem_device *nvmem;
++	int ubi_num;
++	int vol_id;
++	int usable_leb_size;
++	struct list_head list;
++};
++
++static int ubi_nvmem_reg_read(void *priv, unsigned int from,
++			      void *val, size_t bytes)
++{
++	int err = 0, lnum = from, offs, bytes_left = bytes, to_read;
++	struct ubi_nvmem *unv = priv;
++	struct ubi_volume_desc *desc;
++
++	desc = ubi_open_volume(unv->ubi_num, unv->vol_id, UBI_READONLY);
++	if (IS_ERR(desc))
++		return PTR_ERR(desc);
++
++	offs = do_div(lnum, unv->usable_leb_size);
++	while (bytes_left) {
++		to_read = unv->usable_leb_size - offs;
++
++		if (to_read > bytes_left)
++			to_read = bytes_left;
++
++		err = ubi_read(desc, lnum, val, offs, to_read);
++		if (err)
++			break;
++
++		lnum += 1;
++		offs = 0;
++		bytes_left -= to_read;
++		val += to_read;
++	}
++	ubi_close_volume(desc);
++
++	if (err)
++		return err;
++
++	return bytes_left == 0 ? 0 : -EIO;
++}
++
++static int ubi_nvmem_add(struct ubi_volume_info *vi)
++{
++	struct device_node *np = dev_of_node(vi->dev);
++	struct nvmem_config config = {};
++	struct ubi_nvmem *unv;
++	int ret;
++
++	if (!np)
++		return 0;
++
++	if (!of_get_child_by_name(np, "nvmem-layout"))
++		return 0;
++
++	if (WARN_ON_ONCE(vi->usable_leb_size <= 0) ||
++	    WARN_ON_ONCE(vi->size <= 0))
++		return -EINVAL;
++
++	unv = kzalloc(sizeof(struct ubi_nvmem), GFP_KERNEL);
++	if (!unv)
++		return -ENOMEM;
++
++	config.id = NVMEM_DEVID_NONE;
++	config.dev = vi->dev;
++	config.name = dev_name(vi->dev);
++	config.owner = THIS_MODULE;
++	config.priv = unv;
++	config.reg_read = ubi_nvmem_reg_read;
++	config.size = vi->usable_leb_size * vi->size;
++	config.word_size = 1;
++	config.stride = 1;
++	config.read_only = true;
++	config.root_only = true;
++	config.ignore_wp = true;
++	config.of_node = np;
++
++	unv->ubi_num = vi->ubi_num;
++	unv->vol_id = vi->vol_id;
++	unv->usable_leb_size = vi->usable_leb_size;
++	unv->nvmem = nvmem_register(&config);
++	if (IS_ERR(unv->nvmem)) {
++		ret = dev_err_probe(vi->dev, PTR_ERR(unv->nvmem),
++				    "Failed to register NVMEM device\n");
++		kfree(unv);
++		return ret;
++	}
++
++	mutex_lock(&devices_mutex);
++	list_add_tail(&unv->list, &nvmem_devices);
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++}
++
++static void ubi_nvmem_remove(struct ubi_volume_info *vi)
++{
++	struct ubi_nvmem *unv_c, *unv = NULL;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry(unv_c, &nvmem_devices, list)
++		if (unv_c->ubi_num == vi->ubi_num && unv_c->vol_id == vi->vol_id) {
++			unv = unv_c;
++			break;
++		}
++
++	if (!unv) {
++		mutex_unlock(&devices_mutex);
++		return;
++	}
++
++	list_del(&unv->list);
++	mutex_unlock(&devices_mutex);
++	nvmem_unregister(unv->nvmem);
++	kfree(unv);
++}
++
++/**
++ * nvmem_notify - UBI notification handler.
++ * @nb: registered notifier block
++ * @l: notification type
++ * @ns_ptr: pointer to the &struct ubi_notification object
++ */
++static int nvmem_notify(struct notifier_block *nb, unsigned long l,
++			 void *ns_ptr)
++{
++	struct ubi_notification *nt = ns_ptr;
++
++	switch (l) {
++	case UBI_VOLUME_RESIZED:
++		ubi_nvmem_remove(&nt->vi);
++		fallthrough;
++	case UBI_VOLUME_ADDED:
++		ubi_nvmem_add(&nt->vi);
++		break;
++	case UBI_VOLUME_SHUTDOWN:
++		ubi_nvmem_remove(&nt->vi);
++		break;
++	default:
++		break;
++	}
++	return NOTIFY_OK;
++}
++
++static struct notifier_block nvmem_notifier = {
++	.notifier_call = nvmem_notify,
++};
++
++static int __init ubi_nvmem_init(void)
++{
++	return ubi_register_volume_notifier(&nvmem_notifier, 0);
++}
++
++static void __exit ubi_nvmem_exit(void)
++{
++	struct ubi_nvmem *unv, *tmp;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry_safe(unv, tmp, &nvmem_devices, list) {
++		nvmem_unregister(unv->nvmem);
++		list_del(&unv->list);
++		kfree(unv);
++	}
++	mutex_unlock(&devices_mutex);
++
++	ubi_unregister_volume_notifier(&nvmem_notifier);
++}
++
++module_init(ubi_nvmem_init);
++module_exit(ubi_nvmem_exit);
++MODULE_DESCRIPTION("NVMEM layer over UBI volumes");
++MODULE_AUTHOR("Daniel Golle");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch b/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch
new file mode 100644
index 00000000000..d0727faf3dc
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-08-dt-bindings-block-add-basic-bindings-for-block-devic.patch
@@ -0,0 +1,120 @@
+From 9ffc1d7d73609a89eb264d6066340f8b7b3b0ebe Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 21:19:45 +0100
+Subject: [PATCH 08/15] dt-bindings: block: add basic bindings for block
+ devices
+
+Add bindings for block devices which are used to allow referencing
+nvmem bits on them.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/block/block-device.yaml          | 22 ++++++++
+ .../devicetree/bindings/block/partition.yaml  | 50 +++++++++++++++++++
+ .../devicetree/bindings/block/partitions.yaml | 20 ++++++++
+ 3 files changed, 92 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/block/block-device.yaml
+ create mode 100644 Documentation/devicetree/bindings/block/partition.yaml
+ create mode 100644 Documentation/devicetree/bindings/block/partitions.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/block-device.yaml
+@@ -0,0 +1,22 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/block-device.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: block storage device
++
++description: |
++  This binding is generic and describes a block-oriented storage device.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  partitions:
++    $ref: /schemas/block/partitions.yaml
++
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++
++unevaluatedProperties: false
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/partition.yaml
+@@ -0,0 +1,50 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/partition.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Partition on a block device
++
++description: |
++  This binding describes a partition on a block device.
++  Partitions may be matched by a combination of partition number, name,
++  and UUID.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++properties:
++  $nodename:
++    pattern: '^block-partition-.+$'
++
++  partnum:
++    description:
++      Matches partition by number if present.
++
++  partname:
++    "$ref": "/schemas/types.yaml#/definitions/string"
++    description:
++      Matches partition by PARTNAME if present.
++
++  uuid:
++    "$ref": "/schemas/types.yaml#/definitions/string"
++    description:
++      Matches partition by PARTUUID if present.
++
++  nvmem-layout:
++    $ref: /schemas/nvmem/layouts/nvmem-layout.yaml#
++    description:
++      This container may reference an NVMEM layout parser.
++
++anyOf:
++  - required:
++    - partnum
++
++  - required:
++    - partname
++
++  - required:
++    - uuid
++
++unevaluatedProperties: false
+--- /dev/null
++++ b/Documentation/devicetree/bindings/block/partitions.yaml
+@@ -0,0 +1,20 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/block/partitions.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Partitions on block devices
++
++description: |
++  This binding is generic and describes the content of the partitions container
++  node.
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++patternProperties:
++  "^block-partition-.+$":
++    $ref: partition.yaml
++
++unevaluatedProperties: false
diff --git a/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch b/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch
new file mode 100644
index 00000000000..8aa5cba6788
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-09-block-partitions-populate-fwnode.patch
@@ -0,0 +1,77 @@
+From 614f4f6fdda09e30ecf7ef6c8091579db15018cb Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Fri, 21 Jul 2023 17:51:03 +0100
+Subject: [PATCH 09/15] block: partitions: populate fwnode
+
+Let block partitions to be represented by a firmware node and hence
+allow them to being referenced e.g. for use with blk-nvmem.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/partitions/core.c | 41 +++++++++++++++++++++++++++++++++++++++++
+ 1 file changed, 41 insertions(+)
+
+--- a/block/partitions/core.c
++++ b/block/partitions/core.c
+@@ -10,6 +10,8 @@
+ #include <linux/ctype.h>
+ #include <linux/vmalloc.h>
+ #include <linux/raid/detect.h>
++#include <linux/property.h>
++
+ #include "check.h"
+ 
+ static int (*check_part[])(struct parsed_partitions *) = {
+@@ -298,6 +300,43 @@ static ssize_t whole_disk_show(struct de
+ }
+ static DEVICE_ATTR(whole_disk, 0444, whole_disk_show, NULL);
+ 
++static struct fwnode_handle *find_partition_fwnode(struct block_device *bdev)
++{
++	struct fwnode_handle *fw_parts, *fw_part;
++	struct device *ddev = disk_to_dev(bdev->bd_disk);
++	const char *partname, *uuid;
++	u32 partno;
++
++	fw_parts = device_get_named_child_node(ddev, "partitions");
++	if (!fw_parts)
++		fw_parts = device_get_named_child_node(ddev->parent, "partitions");
++
++	if (!fw_parts)
++		return NULL;
++
++	fwnode_for_each_child_node(fw_parts, fw_part) {
++		if (!fwnode_property_read_string(fw_part, "uuid", &uuid) &&
++		    (!bdev->bd_meta_info || strncmp(uuid,
++						    bdev->bd_meta_info->uuid,
++						    PARTITION_META_INFO_UUIDLTH)))
++			continue;
++
++		if (!fwnode_property_read_string(fw_part, "partname", &partname) &&
++		    (!bdev->bd_meta_info || strncmp(partname,
++						    bdev->bd_meta_info->volname,
++						    PARTITION_META_INFO_VOLNAMELTH)))
++			continue;
++
++		if (!fwnode_property_read_u32(fw_part, "partno", &partno) &&
++		    bdev->bd_partno != partno)
++			continue;
++
++		return fw_part;
++	}
++
++	return NULL;
++}
++
+ /*
+  * Must be called either with open_mutex held, before a disk can be opened or
+  * after all disk users are gone.
+@@ -380,6 +419,8 @@ static struct block_device *add_partitio
+ 			goto out_put;
+ 	}
+ 
++	device_set_node(pdev, find_partition_fwnode(bdev));
++
+ 	/* delay uevent until 'holders' subdir is created */
+ 	dev_set_uevent_suppress(pdev, 1);
+ 	err = device_add(pdev);
diff --git a/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch b/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch
new file mode 100644
index 00000000000..4cbec14f5c9
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-10-block-add-new-genhd-flag-GENHD_FL_NVMEM.patch
@@ -0,0 +1,29 @@
+From 65f3ff9672ccd5ee78937047e7a2fc696eee1c8f Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:07:16 +0100
+Subject: [PATCH 10/15] block: add new genhd flag GENHD_FL_NVMEM
+
+Add new flag to destinguish block devices which may act as an NVMEM
+provider.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ include/linux/blkdev.h | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/include/linux/blkdev.h
++++ b/include/linux/blkdev.h
+@@ -87,11 +87,13 @@ struct partition_meta_info {
+  * ``GENHD_FL_NO_PART``: partition support is disabled.  The kernel will not
+  * scan for partitions from add_disk, and users can't add partitions manually.
+  *
++ * ``GENHD_FL_NVMEM``: the block device should be considered as NVMEM provider.
+  */
+ enum {
+ 	GENHD_FL_REMOVABLE			= 1 << 0,
+ 	GENHD_FL_HIDDEN				= 1 << 1,
+ 	GENHD_FL_NO_PART			= 1 << 2,
++	GENHD_FL_NVMEM				= 1 << 3,
+ };
+ 
+ enum {
diff --git a/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch b/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch
new file mode 100644
index 00000000000..e18b0c3a5c7
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-11-block-implement-NVMEM-provider.patch
@@ -0,0 +1,235 @@
+From b9936aa8a3775c2027f655d91a206d0e6e1c7ec0 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 11 Jul 2023 00:17:31 +0100
+Subject: [PATCH 11/15] block: implement NVMEM provider
+
+On embedded devices using an eMMC it is common that one or more partitions
+on the eMMC are used to store MAC addresses and Wi-Fi calibration EEPROM
+data. Allow referencing the partition in device tree for the kernel and
+Wi-Fi drivers accessing it via the NVMEM layer.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ block/Kconfig     |   9 +++
+ block/Makefile    |   1 +
+ block/blk-nvmem.c | 186 ++++++++++++++++++++++++++++++++++++++++++++++
+ 3 files changed, 196 insertions(+)
+ create mode 100644 block/blk-nvmem.c
+
+--- a/block/Kconfig
++++ b/block/Kconfig
+@@ -203,6 +203,15 @@ config BLK_INLINE_ENCRYPTION_FALLBACK
+ 	  by falling back to the kernel crypto API when inline
+ 	  encryption hardware is not present.
+ 
++config BLK_NVMEM
++	bool "Block device NVMEM provider"
++	depends on OF
++	depends on NVMEM
++	help
++	  Allow block devices (or partitions) to act as NVMEM prodivers,
++	  typically used with eMMC to store MAC addresses or Wi-Fi
++	  calibration data on embedded devices.
++
+ source "block/partitions/Kconfig"
+ 
+ config BLOCK_COMPAT
+--- a/block/Makefile
++++ b/block/Makefile
+@@ -35,6 +35,7 @@ obj-$(CONFIG_BLK_DEV_ZONED)	+= blk-zoned
+ obj-$(CONFIG_BLK_WBT)		+= blk-wbt.o
+ obj-$(CONFIG_BLK_DEBUG_FS)	+= blk-mq-debugfs.o
+ obj-$(CONFIG_BLK_DEBUG_FS_ZONED)+= blk-mq-debugfs-zoned.o
++obj-$(CONFIG_BLK_NVMEM)		+= blk-nvmem.o
+ obj-$(CONFIG_BLK_SED_OPAL)	+= sed-opal.o
+ obj-$(CONFIG_BLK_PM)		+= blk-pm.o
+ obj-$(CONFIG_BLK_INLINE_ENCRYPTION)	+= blk-crypto.o blk-crypto-profile.o \
+--- /dev/null
++++ b/block/blk-nvmem.c
+@@ -0,0 +1,186 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * block device NVMEM provider
++ *
++ * Copyright (c) 2023 Daniel Golle <daniel@makrotopia.org>
++ *
++ * Useful on devices using a partition on an eMMC for MAC addresses or
++ * Wi-Fi calibration EEPROM data.
++ */
++
++#include "blk.h"
++#include <linux/nvmem-provider.h>
++#include <linux/of.h>
++#include <linux/pagemap.h>
++#include <linux/property.h>
++
++/* List of all NVMEM devices */
++static LIST_HEAD(nvmem_devices);
++static DEFINE_MUTEX(devices_mutex);
++
++struct blk_nvmem {
++	struct nvmem_device *nvmem;
++	struct block_device *bdev;
++	struct list_head list;
++};
++
++static int blk_nvmem_reg_read(void *priv, unsigned int from,
++			      void *val, size_t bytes)
++{
++	unsigned long offs = from & ~PAGE_MASK, to_read;
++	pgoff_t f_index = from >> PAGE_SHIFT;
++	struct address_space *mapping;
++	struct blk_nvmem *bnv = priv;
++	size_t bytes_left = bytes;
++	struct folio *folio;
++	void *p;
++	int ret;
++
++	if (!bnv->bdev)
++		return -ENODEV;
++
++	if (!bnv->bdev->bd_disk)
++		return -EINVAL;
++
++	if (!bnv->bdev->bd_disk->fops)
++		return -EIO;
++
++	if (!bnv->bdev->bd_disk->fops->open)
++		return -EIO;
++
++	ret = bnv->bdev->bd_disk->fops->open(bnv->bdev, FMODE_READ);
++	if (ret)
++		return ret;
++
++	mapping = bnv->bdev->bd_inode->i_mapping;
++
++	while (bytes_left) {
++		folio = read_mapping_folio(mapping, f_index++, NULL);
++		if (IS_ERR(folio)) {
++			ret = PTR_ERR(folio);
++			goto err_release_bdev;
++		}
++		to_read = min_t(unsigned long, bytes_left, PAGE_SIZE - offs);
++		p = folio_address(folio) + offset_in_folio(folio, offs);
++		memcpy(val, p, to_read);
++		offs = 0;
++		bytes_left -= to_read;
++		val += to_read;
++		folio_put(folio);
++	}
++
++err_release_bdev:
++	bnv->bdev->bd_disk->fops->release(bnv->bdev->bd_disk, FMODE_READ);
++
++	return ret;
++}
++
++static int blk_nvmem_register(struct device *dev, struct class_interface *iface)
++{
++	struct device_node *np = dev_of_node(dev);
++	struct block_device *bdev = dev_to_bdev(dev);
++	struct nvmem_config config = {};
++	struct blk_nvmem *bnv;
++
++	/* skip devices which do not have a device tree node */
++	if (!np)
++		return 0;
++
++	/* skip devices without an nvmem layout defined */
++	if (!of_get_child_by_name(np, "nvmem-layout"))
++		return 0;
++
++	/*
++	 * skip devices which don't have GENHD_FL_NVMEM set
++	 *
++	 * This flag is used for mtdblock and ubiblock devices because
++	 * both, MTD and UBI already implement their own NVMEM provider.
++	 * To avoid registering multiple NVMEM providers for the same
++	 * device node, don't register the block NVMEM provider for them.
++	 */
++	if (!(bdev->bd_disk->flags & GENHD_FL_NVMEM))
++		return 0;
++
++	/*
++	 * skip block device too large to be represented as NVMEM devices
++	 * which are using an 'int' as address
++	 */
++	if (bdev_nr_bytes(bdev) > INT_MAX)
++		return -EFBIG;
++
++	bnv = kzalloc(sizeof(struct blk_nvmem), GFP_KERNEL);
++	if (!bnv)
++		return -ENOMEM;
++
++	config.id = NVMEM_DEVID_NONE;
++	config.dev = &bdev->bd_device;
++	config.name = dev_name(&bdev->bd_device);
++	config.owner = THIS_MODULE;
++	config.priv = bnv;
++	config.reg_read = blk_nvmem_reg_read;
++	config.size = bdev_nr_bytes(bdev);
++	config.word_size = 1;
++	config.stride = 1;
++	config.read_only = true;
++	config.root_only = true;
++	config.ignore_wp = true;
++	config.of_node = to_of_node(dev->fwnode);
++
++	bnv->bdev = bdev;
++	bnv->nvmem = nvmem_register(&config);
++	if (IS_ERR(bnv->nvmem)) {
++		dev_err_probe(&bdev->bd_device, PTR_ERR(bnv->nvmem),
++			      "Failed to register NVMEM device\n");
++
++		kfree(bnv);
++		return PTR_ERR(bnv->nvmem);
++	}
++
++	mutex_lock(&devices_mutex);
++	list_add_tail(&bnv->list, &nvmem_devices);
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++}
++
++static void blk_nvmem_unregister(struct device *dev, struct class_interface *iface)
++{
++	struct block_device *bdev = dev_to_bdev(dev);
++	struct blk_nvmem *bnv_c, *bnv = NULL;
++
++	mutex_lock(&devices_mutex);
++	list_for_each_entry(bnv_c, &nvmem_devices, list) {
++		if (bnv_c->bdev == bdev) {
++			bnv = bnv_c;
++			break;
++		}
++	}
++
++	if (!bnv) {
++		mutex_unlock(&devices_mutex);
++		return;
++	}
++
++	list_del(&bnv->list);
++	mutex_unlock(&devices_mutex);
++	nvmem_unregister(bnv->nvmem);
++	kfree(bnv);
++}
++
++static struct class_interface blk_nvmem_bus_interface __refdata = {
++	.class = &block_class,
++	.add_dev = &blk_nvmem_register,
++	.remove_dev = &blk_nvmem_unregister,
++};
++
++static int __init blk_nvmem_init(void)
++{
++	int ret;
++
++	ret = class_interface_register(&blk_nvmem_bus_interface);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++device_initcall(blk_nvmem_init);
diff --git a/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch b/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch
new file mode 100644
index 00000000000..77c9bf91a54
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-12-dt-bindings-mmc-mmc-card-add-block-device-nodes.patch
@@ -0,0 +1,74 @@
+From 86864bf8f40e84dc881c197ef470a88668329dbf Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 7 Aug 2023 21:21:45 +0100
+Subject: [PATCH 12/15] dt-bindings: mmc: mmc-card: add block device nodes
+
+Add nodes representing the block devices exposed by an MMC device
+including an example involving nvmem-cells.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../devicetree/bindings/mmc/mmc-card.yaml     | 45 +++++++++++++++++++
+ 1 file changed, 45 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mmc/mmc-card.yaml
++++ b/Documentation/devicetree/bindings/mmc/mmc-card.yaml
+@@ -26,6 +26,18 @@ properties:
+       Use this to indicate that the mmc-card has a broken hpi
+       implementation, and that hpi should not be used.
+ 
++  block:
++    $ref: /schemas/block/block-device.yaml#
++    description:
++      Represents the block storage provided by an SD card or the
++      main hardware partition of an eMMC.
++
++patternProperties:
++  '^boot[0-9]+':
++    $ref: /schemas/block/block-device.yaml#
++    description:
++      Represents a boot hardware partition on an eMMC.
++
+ required:
+   - compatible
+   - reg
+@@ -42,6 +54,39 @@ examples:
+             compatible = "mmc-card";
+             reg = <0>;
+             broken-hpi;
++
++            block {
++                partitions {
++                    cal_data: block-partition-rf {
++                        partnum = <3>;
++                        partname = "rf";
++
++                        nvmem-layout {
++                            compatible = "fixed-layout";
++                            #address-cells = <1>;
++                            #size-cells = <1>;
++
++                            eeprom@0 {
++                                reg = <0x0 0x1000>;
++                            };
++                        };
++                    };
++                };
++            };
++
++            boot1 {
++                nvmem-layout {
++                    compatible = "fixed-layout";
++                    #address-cells = <1>;
++                    #size-cells = <1>;
++
++                    macaddr: macaddr@a {
++                        compatible = "mac-base";
++                        reg = <0xa 0x6>;
++                        #nvmem-cell-cells = <1>;
++                    };
++                };
++            };
+         };
+     };
+ 
diff --git a/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch b/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch
new file mode 100644
index 00000000000..fada2804379
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-13-mmc-core-set-card-fwnode_handle.patch
@@ -0,0 +1,23 @@
+From 644942a31719de674e2aa68f83d66bd8ae7e4fb7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:12:21 +0100
+Subject: [PATCH 13/15] mmc: core: set card fwnode_handle
+
+Set fwnode in case it isn't set yet and of_node is present.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/bus.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/mmc/core/bus.c
++++ b/drivers/mmc/core/bus.c
+@@ -363,6 +363,8 @@ int mmc_add_card(struct mmc_card *card)
+ 	mmc_add_card_debugfs(card);
+ #endif
+ 	card->dev.of_node = mmc_of_find_child_device(card->host, 0);
++	if (card->dev.of_node && !card->dev.fwnode)
++		card->dev.fwnode = &card->dev.of_node->fwnode;
+ 
+ 	device_enable_async_suspend(&card->dev);
+ 
diff --git a/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch b/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch
new file mode 100644
index 00000000000..d033abb70de
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-14-mmc-block-set-fwnode-of-disk-devices.patch
@@ -0,0 +1,38 @@
+From d9143f86330dd038fc48878558dd287ceee5d3d4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 13 Jul 2023 04:13:04 +0100
+Subject: [PATCH 14/15] mmc: block: set fwnode of disk devices
+
+Set fwnode of disk devices to 'block', 'boot0' and 'boot1' subnodes of
+the mmc-card. This is done in preparation for having the eMMC act as
+NVMEM provider.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/block.c | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -2484,6 +2484,8 @@ static struct mmc_blk_data *mmc_blk_allo
+ 					      int area_type,
+ 					      unsigned int part_type)
+ {
++	struct fwnode_handle *fwnode;
++	struct device *ddev;
+ 	struct mmc_blk_data *md;
+ 	int devidx, ret;
+ 	char cap_str[10];
+@@ -2580,6 +2582,12 @@ static struct mmc_blk_data *mmc_blk_allo
+ 
+ 	blk_queue_write_cache(md->queue.queue, cache_enabled, fua_enabled);
+ 
++	ddev = disk_to_dev(md->disk);
++	fwnode = device_get_named_child_node(subname ? md->parent->parent :
++						       md->parent,
++					     subname ? subname : "block");
++	ddev->fwnode = fwnode;
++
+ 	string_get_size((u64)size, 512, STRING_UNITS_2,
+ 			cap_str, sizeof(cap_str));
+ 	pr_info("%s: %s %s %s %s\n",
diff --git a/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch b/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch
new file mode 100644
index 00000000000..d76e7b2fe59
--- /dev/null
+++ b/target/linux/generic/pending-6.1/450-15-mmc-block-set-GENHD_FL_NVMEM.patch
@@ -0,0 +1,22 @@
+From 322035ab2b0113d98b6c0ea788d971e0df2952a4 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Thu, 20 Jul 2023 17:36:44 +0100
+Subject: [PATCH 15/15] mmc: block: set GENHD_FL_NVMEM
+
+Set flag to consider MMC block devices as NVMEM providers.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/mmc/core/block.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/core/block.c
++++ b/drivers/mmc/core/block.c
+@@ -2538,6 +2538,7 @@ static struct mmc_blk_data *mmc_blk_allo
+ 	md->disk->major	= MMC_BLOCK_MAJOR;
+ 	md->disk->minors = perdev_minors;
+ 	md->disk->first_minor = devidx * perdev_minors;
++	md->disk->flags = GENHD_FL_NVMEM;
+ 	md->disk->fops = &mmc_bdops;
+ 	md->disk->private_data = md;
+ 	md->parent = parent;
diff --git a/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch b/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
index 765eecd9d71..2eccb9d3bbb 100644
--- a/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
+++ b/target/linux/generic/pending-6.1/490-ubi-auto-attach-mtd-device-named-ubi-or-data-on-boot.patch
@@ -8,10 +8,11 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/build.c
 +++ b/drivers/mtd/ubi/build.c
-@@ -1212,6 +1212,73 @@ static struct mtd_info * __init open_mtd
- 	return mtd;
- }
+@@ -1263,6 +1263,74 @@ static struct mtd_notifier ubi_mtd_notif
+ 	.remove = ubi_notify_remove,
+ };
  
++
 +/*
 + * This function tries attaching mtd partitions named either "ubi" or "data"
 + * during boot.
@@ -79,10 +80,10 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	put_mtd_device(mtd);
 +}
 +
- static int __init ubi_init(void)
+ static int __init ubi_init_attach(void)
  {
  	int err, i, k;
-@@ -1296,6 +1363,12 @@ static int __init ubi_init(void)
+@@ -1313,6 +1381,12 @@ static int __init ubi_init_attach(void)
  		}
  	}
  
@@ -92,6 +93,6 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	    !ubi_is_module() && !mtd_devs)
 +		ubi_auto_attach();
 +
- 	err = ubiblock_init();
- 	if (err) {
- 		pr_err("UBI error: block: cannot initialize, error %d\n", err);
+ 	return 0;
+ 
+ out_detach:
diff --git a/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch b/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
index 17e8d8bedb6..a43da2a5725 100644
--- a/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
+++ b/target/linux/generic/pending-6.1/491-ubi-auto-create-ubiblock-device-for-rootfs.patch
@@ -8,8 +8,8 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -653,6 +653,47 @@ static void __init ubiblock_create_from_
- 	}
+@@ -644,10 +644,47 @@ match_volume_desc(struct ubi_volume_info
+ 	return true;
  }
  
 +#define UBIFS_NODE_MAGIC  0x06101831
@@ -24,46 +24,54 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	return magic == UBIFS_NODE_MAGIC;
 +}
 +
-+static void __init ubiblock_create_auto_rootfs(void)
++static void __init ubiblock_create_auto_rootfs(struct ubi_volume_info *vi)
 +{
-+	int ubi_num, ret, is_ubifs;
++	int ret, is_ubifs;
 +	struct ubi_volume_desc *desc;
-+	struct ubi_volume_info vi;
 +
-+	for (ubi_num = 0; ubi_num < UBI_MAX_DEVICES; ubi_num++) {
-+		desc = ubi_open_volume_nm(ubi_num, "rootfs", UBI_READONLY);
-+		if (IS_ERR(desc))
-+			desc = ubi_open_volume_nm(ubi_num, "fit", UBI_READONLY);;
++	if (strcmp(vi->name, "rootfs") &&
++	    strcmp(vi->name, "fit"))
++		return;
 +
-+		if (IS_ERR(desc))
-+			continue;
++	desc = ubi_open_volume(vi->ubi_num, vi->vol_id, UBI_READONLY);
++	if (IS_ERR(desc))
++		return;
 +
-+		ubi_get_volume_info(desc, &vi);
-+		is_ubifs = ubi_vol_is_ubifs(desc);
-+		ubi_close_volume(desc);
-+		if (is_ubifs)
-+			break;
++	is_ubifs = ubi_vol_is_ubifs(desc);
++	ubi_close_volume(desc);
++	if (is_ubifs)
++		return;
 +
-+		ret = ubiblock_create(&vi);
-+		if (ret)
-+			pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
-+				vi.name, ret);
-+		/* always break if we get here */
-+		break;
-+	}
++	ret = ubiblock_create(vi);
++	if (ret)
++		pr_err("UBI error: block: can't add '%s' volume, err=%d\n",
++			vi->name, ret);
 +}
 +
- static void ubiblock_remove_all(void)
+ static void
+ ubiblock_create_from_param(struct ubi_volume_info *vi)
  {
- 	struct ubiblock *next;
-@@ -685,6 +726,10 @@ int __init ubiblock_init(void)
- 	 */
- 	ubiblock_create_from_param();
+ 	int i, ret = 0;
++	bool got_param = false;
+ 	struct ubiblock_param *p;
  
-+	/* auto-attach "rootfs" volume if existing and non-ubifs */
-+	if (IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
-+		ubiblock_create_auto_rootfs();
-+
  	/*
- 	 * Block devices are only created upon user requests, so we ignore
- 	 * existing volumes.
+@@ -660,6 +697,7 @@ ubiblock_create_from_param(struct ubi_vo
+ 		if (!match_volume_desc(vi, p->name, p->ubi_num, p->vol_id))
+ 			continue;
+ 
++		got_param = true;
+ 		ret = ubiblock_create(vi);
+ 		if (ret) {
+ 			pr_err(
+@@ -668,6 +706,10 @@ ubiblock_create_from_param(struct ubi_vo
+ 		}
+ 		break;
+ 	}
++
++	/* auto-attach "rootfs" volume if existing and non-ubifs */
++	if (!got_param && IS_ENABLED(CONFIG_MTD_ROOTFS_ROOT_DEV))
++		ubiblock_create_auto_rootfs(vi);
+ }
+ 
+ static int ubiblock_notify(struct notifier_block *nb,
diff --git a/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch b/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
index e3493ef19ef..5357c7e15d7 100644
--- a/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
+++ b/target/linux/generic/pending-6.1/493-ubi-set-ROOT_DEV-to-ubiblock-rootfs-if-unset.patch
@@ -8,7 +8,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 
 --- a/drivers/mtd/ubi/block.c
 +++ b/drivers/mtd/ubi/block.c
-@@ -42,6 +42,7 @@
+@@ -43,6 +43,7 @@
  #include <linux/scatterlist.h>
  #include <linux/idr.h>
  #include <asm/div64.h>
@@ -16,7 +16,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #include "ubi-media.h"
  #include "ubi.h"
-@@ -459,6 +460,15 @@ int ubiblock_create(struct ubi_volume_in
+@@ -460,6 +461,15 @@ int ubiblock_create(struct ubi_volume_in
  	dev_info(disk_to_dev(dev->gd), "created from ubi%d:%d(%s)",
  		 dev->ubi_num, dev->vol_id, vi->name);
  	mutex_unlock(&devices_mutex);
diff --git a/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch b/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
index 413431755f1..fc481462212 100644
--- a/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
+++ b/target/linux/generic/pending-6.1/494-mtd-ubi-add-EOF-marker-support.patch
@@ -50,7 +50,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  		break;
 --- a/drivers/mtd/ubi/ubi.h
 +++ b/drivers/mtd/ubi/ubi.h
-@@ -778,6 +778,7 @@ struct ubi_attach_info {
+@@ -780,6 +780,7 @@ struct ubi_attach_info {
  	int mean_ec;
  	uint64_t ec_sum;
  	int ec_count;
diff --git a/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch b/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch
new file mode 100644
index 00000000000..7ee66b318c4
--- /dev/null
+++ b/target/linux/generic/pending-6.1/510-block-add-uImage.FIT-subimage-block-driver.patch
@@ -0,0 +1,732 @@
+From 6173a065cb395d4a9528c4e49810af127db68141 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 16 Nov 2022 12:49:52 +0000
+Subject: [PATCH 1/2] block: add uImage.FIT subimage block driver
+
+Add a small block driver which exposes filesystem sub-images contained
+in U-Boot uImage.FIT images as block devices.
+
+The uImage.FIT image has to be stored directly on a block device or
+partition, MTD device or partition, or UBI volume.
+
+The driver is intended for systems using the U-Boot bootloader and
+uses the root device hint left by the bootloader (or the user) in
+the 'chosen' section of the device-tree.
+
+Example:
+/dts-v1/;
+/ {
+        chosen {
+                rootdisk = <&mmc0_part3>;
+        };
+};
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                 |   6 +
+ drivers/block/Kconfig       |  12 +
+ drivers/block/Makefile      |   2 +
+ drivers/block/fitblk.c      | 658 ++++++++++++++++++++++++++++++++++++
+ drivers/block/open          |   4 +
+ include/uapi/linux/fitblk.h |  10 +
+ 6 files changed, 692 insertions(+)
+ create mode 100644 drivers/block/fitblk.c
+ create mode 100644 drivers/block/open
+ create mode 100644 include/uapi/linux/fitblk.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -21052,6 +21052,12 @@ F:	Documentation/filesystems/ubifs-authe
+ F:	Documentation/filesystems/ubifs.rst
+ F:	fs/ubifs/
+ 
++U-BOOT UIMAGE.FIT PARSER
++M:	Daniel Golle <daniel@makrotopia.org>
++L:	linux-block@vger.kernel.org
++S:	Maintained
++F:	drivers/block/fitblk.c
++
+ UBLK USERSPACE BLOCK DRIVER
+ M:	Ming Lei <ming.lei@redhat.com>
+ L:	linux-block@vger.kernel.org
+--- a/drivers/block/Kconfig
++++ b/drivers/block/Kconfig
+@@ -383,6 +383,18 @@ config VIRTIO_BLK
+ 	  This is the virtual block driver for virtio.  It can be used with
+           QEMU based VMMs (like KVM or Xen).  Say Y or M.
+ 
++config UIMAGE_FIT_BLK
++	bool "uImage.FIT block driver"
++	help
++	  This driver allows using filesystems contained in uImage.FIT images
++	  by mapping them as block devices.
++
++	  It can currently not be built as a module due to libfdt symbols not
++	  being exported.
++
++	  Say Y if you want to mount filesystems sub-images of a uImage.FIT
++	  stored in a block device partition, mtdblock or ubiblock device.
++
+ config BLK_DEV_RBD
+ 	tristate "Rados block device (RBD)"
+ 	depends on INET && BLOCK
+--- a/drivers/block/Makefile
++++ b/drivers/block/Makefile
+@@ -39,4 +39,6 @@ obj-$(CONFIG_BLK_DEV_NULL_BLK)	+= null_b
+ 
+ obj-$(CONFIG_BLK_DEV_UBLK)			+= ublk_drv.o
+ 
++obj-$(CONFIG_UIMAGE_FIT_BLK)	+= fitblk.o
++
+ swim_mod-y	:= swim.o swim_asm.o
+--- /dev/null
++++ b/drivers/block/fitblk.c
+@@ -0,0 +1,635 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * uImage.FIT virtual block device driver.
++ *
++ * Copyright (C) 2023 Daniel Golle
++ * Copyright (C) 2007 Nick Piggin
++ * Copyright (C) 2007 Novell Inc.
++ *
++ * Initially derived from drivers/block/brd.c which is in parts derived from
++ * drivers/block/rd.c, and drivers/block/loop.c, copyright of their respective
++ * owners.
++ *
++ * uImage.FIT headers extracted from Das U-Boot
++ *  (C) Copyright 2008 Semihalf
++ *  (C) Copyright 2000-2005
++ *  Wolfgang Denk, DENX Software Engineering, wd@denx.de.
++ */
++
++#include <linux/init.h>
++#include <linux/initrd.h>
++#include <linux/module.h>
++#include <linux/moduleparam.h>
++#include <linux/major.h>
++#include <linux/blkdev.h>
++#include <linux/blkpg.h>
++#include <linux/blk-mq.h>
++#include <linux/ctype.h>
++#include <linux/hdreg.h>
++#include <linux/list.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_device.h>
++#include <linux/of_fdt.h>
++#include <linux/pagemap.h>
++#include <linux/platform_device.h>
++#include <linux/property.h>
++#include <linux/refcount.h>
++#include <linux/task_work.h>
++#include <linux/types.h>
++#include <linux/libfdt.h>
++#include <linux/mtd/mtd.h>
++#include <linux/root_dev.h>
++#include <uapi/linux/fitblk.h>
++
++#define FIT_DEVICE_PREFIX	"fit"
++
++/* maximum number of pages used for the uImage.FIT index structure */
++#define FIT_MAX_PAGES		1024
++
++/* minimum free sectors to map as read-write "remainder" volume */
++#define MIN_FREE_SECT		16
++
++/* maximum number of mapped loadables */
++#define MAX_FIT_LOADABLES	16
++
++/* constants for uImage.FIT structrure traversal */
++#define FIT_IMAGES_PATH		"/images"
++#define FIT_CONFS_PATH		"/configurations"
++
++/* hash/signature/key node */
++#define FIT_HASH_NODENAME	"hash"
++#define FIT_ALGO_PROP		"algo"
++#define FIT_VALUE_PROP		"value"
++#define FIT_IGNORE_PROP		"uboot-ignore"
++#define FIT_SIG_NODENAME	"signature"
++#define FIT_KEY_REQUIRED	"required"
++#define FIT_KEY_HINT		"key-name-hint"
++
++/* cipher node */
++#define FIT_CIPHER_NODENAME	"cipher"
++#define FIT_ALGO_PROP		"algo"
++
++/* image node */
++#define FIT_DATA_PROP		"data"
++#define FIT_DATA_POSITION_PROP	"data-position"
++#define FIT_DATA_OFFSET_PROP	"data-offset"
++#define FIT_DATA_SIZE_PROP	"data-size"
++#define FIT_TIMESTAMP_PROP	"timestamp"
++#define FIT_DESC_PROP		"description"
++#define FIT_ARCH_PROP		"arch"
++#define FIT_TYPE_PROP		"type"
++#define FIT_OS_PROP		"os"
++#define FIT_COMP_PROP		"compression"
++#define FIT_ENTRY_PROP		"entry"
++#define FIT_LOAD_PROP		"load"
++
++/* configuration node */
++#define FIT_KERNEL_PROP		"kernel"
++#define FIT_FILESYSTEM_PROP	"filesystem"
++#define FIT_RAMDISK_PROP	"ramdisk"
++#define FIT_FDT_PROP		"fdt"
++#define FIT_LOADABLE_PROP	"loadables"
++#define FIT_DEFAULT_PROP	"default"
++#define FIT_SETUP_PROP		"setup"
++#define FIT_FPGA_PROP		"fpga"
++#define FIT_FIRMWARE_PROP	"firmware"
++#define FIT_STANDALONE_PROP	"standalone"
++
++/* fitblk driver data */
++static const char *_fitblk_claim_ptr = "I belong to fitblk";
++static const char *ubootver;
++struct device_node *rootdisk;
++static struct platform_device *pdev;
++static LIST_HEAD(fitblk_devices);
++static DEFINE_MUTEX(devices_mutex);
++refcount_t num_devs;
++
++struct fitblk {
++	struct platform_device	*pdev;
++	struct block_device	*lower_bdev;
++	sector_t		start_sect;
++	struct gendisk		*disk;
++	struct work_struct	remove_work;
++	struct list_head	list;
++	bool			dead;
++};
++
++static int fitblk_open(struct block_device *bdev, fmode_t mode)
++{
++	struct fitblk *fitblk = bdev->bd_disk->private_data;
++
++	if (fitblk->dead)
++		return -ENOENT;
++
++	return 0;
++}
++
++static void fitblk_release(struct gendisk *disk, fmode_t mode)
++{
++	return;
++}
++
++static void fitblk_submit_bio(struct bio *orig_bio)
++{
++	struct bio *bio = orig_bio;
++	struct fitblk *fitblk = bio->bi_bdev->bd_disk->private_data;
++
++	if (fitblk->dead)
++		return;
++
++	/* mangle bio and re-submit */
++	while (bio) {
++		bio->bi_iter.bi_sector += fitblk->start_sect;
++		bio->bi_bdev = fitblk->lower_bdev;
++		bio = bio->bi_next;
++	}
++	submit_bio(orig_bio);
++}
++
++static void fitblk_remove(struct fitblk *fitblk)
++{
++	blk_mark_disk_dead(fitblk->disk);
++	mutex_lock(&devices_mutex);
++	fitblk->dead = true;
++	list_del(&fitblk->list);
++	mutex_unlock(&devices_mutex);
++
++	schedule_work(&fitblk->remove_work);
++}
++
++static int fitblk_ioctl(struct block_device *bdev, fmode_t mode,
++			unsigned int cmd, unsigned long arg)
++{
++	struct fitblk *fitblk = bdev->bd_disk->private_data;
++
++	if (!capable(CAP_SYS_ADMIN))
++		return -EACCES;
++
++	if (fitblk->dead)
++		return -ENOENT;
++
++	switch (cmd) {
++	case FITBLK_RELEASE:
++		fitblk_remove(fitblk);
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static const struct block_device_operations fitblk_fops = {
++	.owner		= THIS_MODULE,
++	.ioctl		= fitblk_ioctl,
++	.open		= fitblk_open,
++	.release	= fitblk_release,
++	.submit_bio	= fitblk_submit_bio,
++};
++
++static void fitblk_purge(struct work_struct *work)
++{
++	struct fitblk *fitblk = container_of(work, struct fitblk, remove_work);
++
++	//del_gendisk(fitblk->disk); // causes crash, not doing it doesn't matter
++	refcount_dec(&num_devs);
++	platform_device_del(fitblk->pdev);
++	platform_device_put(fitblk->pdev);
++
++	if (refcount_dec_if_one(&num_devs)) {
++		sysfs_remove_link(&pdev->dev.kobj, "lower_dev");
++		blkdev_put(fitblk->lower_bdev, FMODE_READ | FMODE_EXCL);
++	}
++
++	kfree(fitblk);
++}
++
++static int add_fit_subimage_device(struct block_device *lower_bdev,
++				   unsigned int slot, sector_t start_sect,
++				   sector_t nr_sect, bool readonly)
++{
++	struct fitblk *fitblk;
++	struct gendisk *disk;
++	int err;
++
++	mutex_lock(&devices_mutex);
++	if (!refcount_inc_not_zero(&num_devs))
++		return -EBADF;
++
++	fitblk = kzalloc(sizeof(struct fitblk), GFP_KERNEL);
++	if (!fitblk) {
++		err = -ENOMEM;
++		goto out_unlock;
++	}
++
++	fitblk->lower_bdev = lower_bdev;
++	fitblk->start_sect = start_sect;
++	INIT_WORK(&fitblk->remove_work, fitblk_purge);
++
++	disk = blk_alloc_disk(NUMA_NO_NODE);
++	if (!disk) {
++		err = -ENOMEM;
++		goto out_free_fitblk;
++	}
++
++	disk->first_minor = 0;
++	disk->flags = lower_bdev->bd_disk->flags | GENHD_FL_NO_PART;
++	disk->fops = &fitblk_fops;
++	disk->private_data = fitblk;
++	if (readonly) {
++		set_disk_ro(disk, 1);
++		snprintf(disk->disk_name, sizeof(disk->disk_name), FIT_DEVICE_PREFIX "%u", slot);
++	} else {
++		strcpy(disk->disk_name, FIT_DEVICE_PREFIX "rw");
++	}
++
++	set_capacity(disk, nr_sect);
++
++	disk->queue->queue_flags = lower_bdev->bd_disk->queue->queue_flags;
++	memcpy(&disk->queue->limits, &lower_bdev->bd_disk->queue->limits,
++	       sizeof(struct queue_limits));
++
++	fitblk->disk = disk;
++	fitblk->pdev = platform_device_alloc(disk->disk_name, PLATFORM_DEVID_NONE);
++	if (!fitblk->pdev) {
++		err = -ENOMEM;
++		goto out_cleanup_disk;
++	}
++
++	fitblk->pdev->dev.parent = &pdev->dev;
++	err = platform_device_add(fitblk->pdev);
++	if (err)
++		goto out_put_pdev;
++
++	err = device_add_disk(&fitblk->pdev->dev, disk, NULL);
++	if (err)
++		goto out_del_pdev;
++
++	if (!ROOT_DEV)
++		ROOT_DEV = disk->part0->bd_dev;
++
++	list_add_tail(&fitblk->list, &fitblk_devices);
++
++	mutex_unlock(&devices_mutex);
++
++	return 0;
++
++out_del_pdev:
++	platform_device_del(fitblk->pdev);
++out_put_pdev:
++	platform_device_put(fitblk->pdev);
++out_cleanup_disk:
++	put_disk(disk);
++out_free_fitblk:
++	kfree(fitblk);
++out_unlock:
++	refcount_dec(&num_devs);
++	mutex_unlock(&devices_mutex);
++	return err;
++}
++
++static int parse_fit_on_dev(struct device *dev)
++{
++	struct block_device *bdev;
++	struct address_space *mapping;
++	struct folio *folio;
++	pgoff_t f_index = 0;
++	size_t bytes_left, bytes_to_copy;
++	void *pre_fit, *fit, *fit_c;
++	u64 dsize, dsectors, imgmaxsect = 0;
++	u32 size, image_pos, image_len;
++	const __be32 *image_offset_be, *image_len_be, *image_pos_be;
++	int ret = 0, node, images, config;
++	const char *image_name, *image_type, *image_description,
++		*config_default, *config_description, *config_loadables;
++	u32 image_name_len, image_type_len, image_description_len,
++		bootconf_len, config_default_len, config_description_len,
++		config_loadables_len;
++	sector_t start_sect, nr_sects;
++	struct device_node *np = NULL;
++	const char *bootconf_c;
++	const char *loadable;
++	char *bootconf = NULL, *bootconf_term;
++	bool found;
++	int loadables_rem_len, loadable_len;
++	u16 loadcnt;
++	unsigned int slot = 0;
++
++	/* Exclusive open the block device to receive holder notifications */
++	bdev = blkdev_get_by_dev(dev->devt, FMODE_READ | FMODE_EXCL, &_fitblk_claim_ptr);
++	if (!bdev)
++		return -ENODEV;
++
++	if (IS_ERR(bdev))
++		return PTR_ERR(bdev);
++
++	mapping = bdev->bd_inode->i_mapping;
++
++	/* map first page */
++	folio = read_mapping_folio(mapping, f_index++, NULL);
++	if (IS_ERR(folio)) {
++		ret = PTR_ERR(folio);
++		goto out_blkdev;
++	}
++	pre_fit = folio_address(folio) + offset_in_folio(folio, 0);
++
++	/* uImage.FIT is based on flattened device tree structure */
++	if (fdt_check_header(pre_fit)) {
++		ret = -EINVAL;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	size = fdt_totalsize(pre_fit);
++
++	if (size > PAGE_SIZE * FIT_MAX_PAGES) {
++		ret = -EOPNOTSUPP;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	/* acquire disk size */
++	dsectors = bdev_nr_sectors(bdev);
++	dsize = dsectors << SECTOR_SHIFT;
++
++	/* abort if FIT structure is larger than disk or partition size */
++	if (size >= dsize) {
++		ret = -EFBIG;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	fit = kmalloc(size, GFP_KERNEL);
++	if (!fit) {
++		ret = -ENOMEM;
++		folio_put(folio);
++		goto out_blkdev;
++	}
++
++	bytes_left = size;
++	fit_c = fit;
++	while (bytes_left > 0) {
++		bytes_to_copy = min(bytes_left, folio_size(folio) - offset_in_folio(folio, 0));
++		memcpy(fit_c, pre_fit, bytes_to_copy);
++		fit_c += bytes_to_copy;
++		bytes_left -= bytes_to_copy;
++		if (bytes_left) {
++			folio_put(folio);
++			folio = read_mapping_folio(mapping, f_index++, NULL);
++			if (IS_ERR(folio)) {
++				ret = PTR_ERR(folio);
++				goto out_blkdev;
++			};
++			pre_fit = folio_address(folio) + offset_in_folio(folio, 0);
++		}
++	}
++	folio_put(folio);
++
++	/* set boot config node name U-Boot may have added to the device tree */
++	np = of_find_node_by_path("/chosen");
++	if (np) {
++		bootconf_c = of_get_property(np, "u-boot,bootconf", &bootconf_len);
++		if (bootconf_c && bootconf_len)
++			bootconf = kmemdup_nul(bootconf_c, bootconf_len, GFP_KERNEL);
++	}
++
++	if (bootconf) {
++		bootconf_term = strchr(bootconf, '#');
++		if (bootconf_term)
++			*bootconf_term = '\0';
++	}
++
++	/* find configuration path in uImage.FIT */
++	config = fdt_path_offset(fit, FIT_CONFS_PATH);
++	if (config < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n",
++			FIT_CONFS_PATH, config);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* get default configuration node name */
++	config_default =
++		fdt_getprop(fit, config, FIT_DEFAULT_PROP, &config_default_len);
++
++	/* make sure we got either default or selected boot config node name */
++	if (!config_default && !bootconf) {
++		pr_err("FIT: Cannot find default configuration\n");
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* find selected boot config node, fallback on default config node */
++	node = fdt_subnode_offset(fit, config, bootconf ?: config_default);
++	if (node < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n",
++			bootconf ?: config_default, node);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	pr_info("FIT: Detected U-Boot %s\n", ubootver);
++
++	/* get selected configuration data */
++	config_description =
++		fdt_getprop(fit, node, FIT_DESC_PROP, &config_description_len);
++	config_loadables = fdt_getprop(fit, node, FIT_LOADABLE_PROP,
++				       &config_loadables_len);
++
++	pr_info("FIT: %s configuration: \"%.*s\"%s%.*s%s\n",
++		bootconf ? "Selected" : "Default",
++		bootconf ? bootconf_len : config_default_len,
++		bootconf ?: config_default,
++		config_description ? " (" : "",
++		config_description ? config_description_len : 0,
++		config_description ?: "",
++		config_description ? ")" : "");
++
++	if (!config_loadables || !config_loadables_len) {
++		pr_err("FIT: No loadables configured in \"%s\"\n",
++			bootconf ?: config_default);
++		ret = -ENOENT;
++		goto out_bootconf;
++	}
++
++	/* get images path in uImage.FIT */
++	images = fdt_path_offset(fit, FIT_IMAGES_PATH);
++	if (images < 0) {
++		pr_err("FIT: Cannot find %s node: %d\n", FIT_IMAGES_PATH, images);
++		ret = -EINVAL;
++		goto out_bootconf;
++	}
++
++	/* iterate over images in uImage.FIT */
++	fdt_for_each_subnode(node, fit, images) {
++		image_name = fdt_get_name(fit, node, &image_name_len);
++		image_type = fdt_getprop(fit, node, FIT_TYPE_PROP, &image_type_len);
++		image_offset_be = fdt_getprop(fit, node, FIT_DATA_OFFSET_PROP, NULL);
++		image_pos_be = fdt_getprop(fit, node, FIT_DATA_POSITION_PROP, NULL);
++		image_len_be = fdt_getprop(fit, node, FIT_DATA_SIZE_PROP, NULL);
++
++		if (!image_name || !image_type || !image_len_be ||
++		    !image_name_len || !image_type_len)
++			continue;
++
++		image_len = be32_to_cpu(*image_len_be);
++		if (!image_len)
++			continue;
++
++		if (image_offset_be)
++			image_pos = be32_to_cpu(*image_offset_be) + size;
++		else if (image_pos_be)
++			image_pos = be32_to_cpu(*image_pos_be);
++		else
++			continue;
++
++		image_description = fdt_getprop(fit, node, FIT_DESC_PROP,
++						&image_description_len);
++
++		pr_info("FIT: %16s sub-image 0x%08x..0x%08x \"%.*s\"%s%.*s%s\n",
++			image_type, image_pos, image_pos + image_len - 1,
++			image_name_len, image_name, image_description ? " (" : "",
++			image_description ? image_description_len : 0,
++			image_description ?: "", image_description ? ") " : "");
++
++		/* only 'filesystem' images should be mapped as partitions */
++		if (strncmp(image_type, FIT_FILESYSTEM_PROP, image_type_len))
++			continue;
++
++		/* check if sub-image is part of configured loadables */
++		found = false;
++		loadable = config_loadables;
++		loadables_rem_len = config_loadables_len;
++		for (loadcnt = 0; loadables_rem_len > 1 &&
++				  loadcnt < MAX_FIT_LOADABLES; ++loadcnt) {
++			loadable_len =
++				strnlen(loadable, loadables_rem_len - 1) + 1;
++			loadables_rem_len -= loadable_len;
++			if (!strncmp(image_name, loadable, loadable_len)) {
++				found = true;
++				break;
++			}
++			loadable += loadable_len;
++		}
++		if (!found)
++			continue;
++
++		if (image_pos % (1 << PAGE_SHIFT)) {
++			dev_err(dev, "FIT: image %.*s start not aligned to page boundaries, skipping\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		if (image_len % (1 << PAGE_SHIFT)) {
++			dev_err(dev, "FIT: sub-image %.*s end not aligned to page boundaries, skipping\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		start_sect = image_pos >> SECTOR_SHIFT;
++		nr_sects = image_len >> SECTOR_SHIFT;
++		imgmaxsect = max_t(sector_t, imgmaxsect, start_sect + nr_sects);
++
++		if (start_sect + nr_sects > dsectors) {
++			dev_err(dev, "FIT: sub-image %.*s disk access beyond EOD\n",
++				image_name_len, image_name);
++			continue;
++		}
++
++		if (!slot) {
++			ret = sysfs_create_link_nowarn(&pdev->dev.kobj, bdev_kobj(bdev), "lower_dev");
++			if (ret && ret != -EEXIST)
++				goto out_bootconf;
++
++			ret = 0;
++		}
++
++		add_fit_subimage_device(bdev, slot++, start_sect, nr_sects, true);
++	}
++
++	if (!found || !slot)
++		goto out_bootconf;
++
++	dev_info(dev, "mapped %u uImage.FIT filesystem sub-image%s as /dev/fit%s%u%s\n",
++		 slot, (slot > 1)?"s":"", (slot > 1)?"[0...":"", slot - 1,
++		 (slot > 1)?"]":"");
++
++	/* in case uImage.FIT is stored in a partition, map the remaining space */
++	if (!bdev->bd_read_only && bdev_is_partition(bdev) &&
++	    (imgmaxsect + MIN_FREE_SECT) < dsectors) {
++		add_fit_subimage_device(bdev, slot++, imgmaxsect,
++					dsectors - imgmaxsect, false);
++		dev_info(dev, "mapped remaing space as /dev/fitrw\n");
++	}
++
++out_bootconf:
++	kfree(bootconf);
++	kfree(fit);
++out_blkdev:
++	if (!found || ret)
++		blkdev_put(bdev, FMODE_READ | FMODE_EXCL);
++
++	return ret;
++}
++
++static int fitblk_match_of_node(struct device *dev, const void *np)
++{
++	int ret;
++
++	ret = device_match_of_node(dev, np);
++	if (ret)
++		return ret;
++
++	/*
++	 * To match ubiblock and mtdblock devices by their parent ubi
++	 * or mtd device, also consider block device parent
++	 */
++	if (!dev->parent)
++		return 0;
++
++	return device_match_of_node(dev->parent, np);
++}
++
++static int fitblk_probe(struct platform_device *pdev)
++{
++	struct device *dev;
++
++	dev = class_find_device(&block_class, NULL, rootdisk, fitblk_match_of_node);
++	if (!dev)
++		return -EPROBE_DEFER;
++
++	return parse_fit_on_dev(dev);
++}
++
++static struct platform_driver fitblk_driver = {
++	.probe		= fitblk_probe,
++	.driver		= {
++		.name   = "fitblk",
++		.owner   = THIS_MODULE,
++	},
++};
++
++static int __init fitblk_init(void)
++{
++	/* detect U-Boot firmware */
++	ubootver = of_get_property(of_chosen, "u-boot,version", NULL);
++	if (!ubootver)
++		return 0;
++
++	/* parse 'rootdisk' property phandle */
++	rootdisk = of_parse_phandle(of_chosen, "rootdisk", 0);
++	if (!rootdisk)
++		return 0;
++
++	if (platform_driver_register(&fitblk_driver))
++		return -ENODEV;
++
++	refcount_set(&num_devs, 1);
++	pdev = platform_device_register_simple("fitblk", -1, NULL, 0);
++	if (IS_ERR(pdev))
++		return PTR_ERR(pdev);
++
++	return 0;
++}
++device_initcall(fitblk_init);
+--- /dev/null
++++ b/include/uapi/linux/fitblk.h
+@@ -0,0 +1,10 @@
++/* SPDX-License-Identifier: GPL-2.0+ WITH Linux-syscall-note */
++#ifndef _UAPI_LINUX_FITBLK_H
++#define _UAPI_LINUX_FITBLK_H
++
++/*
++ * IOCTL commands --- we will commandeer 0x46 ('F')
++ */
++#define FITBLK_RELEASE             0x4600
++
++#endif /* _UAPI_LINUX_FITBLK_H */
diff --git a/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch b/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch
new file mode 100644
index 00000000000..685a5f9da51
--- /dev/null
+++ b/target/linux/generic/pending-6.1/511-init-bypass-device-lookup-for-dev-fit-rootfs.patch
@@ -0,0 +1,25 @@
+From 5ede3f8aed9a1a579bf7304142600d1f3500add9 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Mon, 12 Jun 2023 03:58:42 +0100
+Subject: [PATCH 2/2] init: bypass device lookup for /dev/fit* rootfs
+
+Allow 'rootwait' as /dev/fit* can show up late if the underlaying
+device is probed late.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ init/do_mounts.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/init/do_mounts.c
++++ b/init/do_mounts.c
+@@ -645,7 +645,8 @@ void __init prepare_namespace(void)
+ 
+ 	if (saved_root_name[0]) {
+ 		root_device_name = saved_root_name;
+-		if (!strncmp(root_device_name, "mtd", 3) ||
++		if (!strncmp(root_device_name, "fit", 3) ||
++		    !strncmp(root_device_name, "mtd", 3) ||
+ 		    !strncmp(root_device_name, "ubi", 3)) {
+ 			mount_block_root(root_device_name, root_mountflags);
+ 			goto out;
diff --git a/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch b/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
index 2bc25eb4fa6..b799c6fc9cb 100644
--- a/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
+++ b/target/linux/generic/pending-6.1/666-Add-support-for-MAP-E-FMRs-mesh-mode.patch
@@ -275,8 +275,8 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  static int __ip6_tnl_rcv(struct ip6_tnl *tunnel, struct sk_buff *skb,
  			 const struct tnl_ptk_info *tpi,
  			 struct metadata_dst *tun_dst,
-@@ -840,6 +966,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
- 	skb_reset_network_header(skb);
+@@ -855,6 +981,27 @@ static int __ip6_tnl_rcv(struct ip6_tnl
+ 
  	memset(skb->cb, 0, sizeof(struct inet6_skb_parm));
  
 +	if (tpi->proto == htons(ETH_P_IP) && tunnel->parms.fmrs &&
@@ -303,7 +303,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	__skb_tunnel_rx(skb, tunnel->dev, tunnel->net);
  
  	err = dscp_ecn_decapsulate(tunnel, ipv6h, skb);
-@@ -987,6 +1134,7 @@ static void init_tel_txopt(struct ipv6_t
+@@ -1002,6 +1149,7 @@ static void init_tel_txopt(struct ipv6_t
  	opt->ops.opt_nflen = 8;
  }
  
@@ -311,7 +311,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  /**
   * ip6_tnl_addr_conflict - compare packet addresses to tunnel's own
   *   @t: the outgoing tunnel device
-@@ -1278,6 +1426,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
+@@ -1293,6 +1441,7 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
  		u8 protocol)
  {
  	struct ip6_tnl *t = netdev_priv(dev);
@@ -319,7 +319,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	struct ipv6hdr *ipv6h;
  	const struct iphdr  *iph;
  	int encap_limit = -1;
-@@ -1377,6 +1526,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
+@@ -1392,6 +1541,18 @@ ipxip6_tnl_xmit(struct sk_buff *skb, str
  	fl6.flowi6_uid = sock_net_uid(dev_net(dev), NULL);
  	dsfield = INET_ECN_encapsulate(dsfield, orig_dsfield);
  
@@ -338,7 +338,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	if (iptunnel_handle_offloads(skb, SKB_GSO_IPXIP6))
  		return -1;
  
-@@ -1530,6 +1691,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
+@@ -1545,6 +1706,14 @@ ip6_tnl_change(struct ip6_tnl *t, const
  	t->parms.link = p->link;
  	t->parms.proto = p->proto;
  	t->parms.fwmark = p->fwmark;
@@ -353,7 +353,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	dst_cache_reset(&t->dst_cache);
  	ip6_tnl_link_config(t);
  }
-@@ -1564,6 +1733,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
+@@ -1579,6 +1748,7 @@ ip6_tnl_parm_from_user(struct __ip6_tnl_
  	p->flowinfo = u->flowinfo;
  	p->link = u->link;
  	p->proto = u->proto;
@@ -361,7 +361,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	memcpy(p->name, u->name, sizeof(u->name));
  }
  
-@@ -1950,6 +2120,15 @@ static int ip6_tnl_validate(struct nlatt
+@@ -1965,6 +2135,15 @@ static int ip6_tnl_validate(struct nlatt
  	return 0;
  }
  
@@ -377,7 +377,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  static void ip6_tnl_netlink_parms(struct nlattr *data[],
  				  struct __ip6_tnl_parm *parms)
  {
-@@ -1987,6 +2166,46 @@ static void ip6_tnl_netlink_parms(struct
+@@ -2002,6 +2181,46 @@ static void ip6_tnl_netlink_parms(struct
  
  	if (data[IFLA_IPTUN_FWMARK])
  		parms->fwmark = nla_get_u32(data[IFLA_IPTUN_FWMARK]);
@@ -424,7 +424,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  }
  
  static int ip6_tnl_newlink(struct net *src_net, struct net_device *dev,
-@@ -2070,6 +2289,12 @@ static void ip6_tnl_dellink(struct net_d
+@@ -2085,6 +2304,12 @@ static void ip6_tnl_dellink(struct net_d
  
  static size_t ip6_tnl_get_size(const struct net_device *dev)
  {
@@ -437,7 +437,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	return
  		/* IFLA_IPTUN_LINK */
  		nla_total_size(4) +
-@@ -2099,6 +2324,24 @@ static size_t ip6_tnl_get_size(const str
+@@ -2114,6 +2339,24 @@ static size_t ip6_tnl_get_size(const str
  		nla_total_size(0) +
  		/* IFLA_IPTUN_FWMARK */
  		nla_total_size(4) +
@@ -462,7 +462,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  		0;
  }
  
-@@ -2106,6 +2349,9 @@ static int ip6_tnl_fill_info(struct sk_b
+@@ -2121,6 +2364,9 @@ static int ip6_tnl_fill_info(struct sk_b
  {
  	struct ip6_tnl *tunnel = netdev_priv(dev);
  	struct __ip6_tnl_parm *parm = &tunnel->parms;
@@ -472,7 +472,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  
  	if (nla_put_u32(skb, IFLA_IPTUN_LINK, parm->link) ||
  	    nla_put_in6_addr(skb, IFLA_IPTUN_LOCAL, &parm->laddr) ||
-@@ -2115,9 +2361,27 @@ static int ip6_tnl_fill_info(struct sk_b
+@@ -2130,9 +2376,27 @@ static int ip6_tnl_fill_info(struct sk_b
  	    nla_put_be32(skb, IFLA_IPTUN_FLOWINFO, parm->flowinfo) ||
  	    nla_put_u32(skb, IFLA_IPTUN_FLAGS, parm->flags) ||
  	    nla_put_u8(skb, IFLA_IPTUN_PROTO, parm->proto) ||
@@ -501,7 +501,7 @@ Signed-off-by: Steven Barth <cyrus@openwrt.org>
  	if (nla_put_u16(skb, IFLA_IPTUN_ENCAP_TYPE, tunnel->encap.type) ||
  	    nla_put_be16(skb, IFLA_IPTUN_ENCAP_SPORT, tunnel->encap.sport) ||
  	    nla_put_be16(skb, IFLA_IPTUN_ENCAP_DPORT, tunnel->encap.dport) ||
-@@ -2157,6 +2421,7 @@ static const struct nla_policy ip6_tnl_p
+@@ -2172,6 +2436,7 @@ static const struct nla_policy ip6_tnl_p
  	[IFLA_IPTUN_ENCAP_DPORT]	= { .type = NLA_U16 },
  	[IFLA_IPTUN_COLLECT_METADATA]	= { .type = NLA_FLAG },
  	[IFLA_IPTUN_FWMARK]		= { .type = NLA_U32 },
diff --git a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
index 8763b92c02a..11850c04186 100644
--- a/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
+++ b/target/linux/generic/pending-6.1/680-NET-skip-GRO-for-foreign-MAC-addresses.patch
@@ -11,7 +11,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -2134,6 +2134,8 @@ struct net_device {
+@@ -2157,6 +2157,8 @@ struct net_device {
  	struct netdev_hw_addr_list	mc;
  	struct netdev_hw_addr_list	dev_addrs;
  
diff --git a/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch b/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
index 47c742cff06..a3897a9fd10 100644
--- a/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
+++ b/target/linux/generic/pending-6.1/700-netfilter-nft_flow_offload-handle-netdevice-events-f.patch
@@ -59,7 +59,7 @@ Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
  }
 --- a/net/netfilter/nft_flow_offload.c
 +++ b/net/netfilter/nft_flow_offload.c
-@@ -470,47 +470,14 @@ static struct nft_expr_type nft_flow_off
+@@ -475,47 +475,14 @@ static struct nft_expr_type nft_flow_off
  	.owner		= THIS_MODULE,
  };
  
diff --git a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
index 307ddce761f..db95e28af3b 100644
--- a/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
+++ b/target/linux/generic/pending-6.1/701-netfilter-nf_tables-ignore-EOPNOTSUPP-on-flowtable-d.patch
@@ -18,7 +18,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/net/netfilter/nf_tables_api.c
 +++ b/net/netfilter/nf_tables_api.c
-@@ -7884,7 +7884,7 @@ static int nft_register_flowtable_net_ho
+@@ -7908,7 +7908,7 @@ static int nft_register_flowtable_net_ho
  		err = flowtable->data.type->setup(&flowtable->data,
  						  hook->ops.dev,
  						  FLOW_BLOCK_BIND);
diff --git a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
index be28fdc8036..842fef3a9c5 100644
--- a/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
+++ b/target/linux/generic/pending-6.1/702-net-ethernet-mtk_eth_soc-enable-threaded-NAPI.patch
@@ -10,7 +10,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -4942,6 +4942,8 @@ static int mtk_probe(struct platform_dev
+@@ -4941,6 +4941,8 @@ static int mtk_probe(struct platform_dev
  	 * for NAPI to work
  	 */
  	init_dummy_netdev(&eth->dummy_dev);
diff --git a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
index 425f82376bb..e4937a1df1b 100644
--- a/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
+++ b/target/linux/generic/pending-6.1/703-phy-add-detach-callback-to-struct-phy_driver.patch
@@ -11,7 +11,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
 
 --- a/drivers/net/phy/phy_device.c
 +++ b/drivers/net/phy/phy_device.c
-@@ -1753,6 +1753,9 @@ void phy_detach(struct phy_device *phyde
+@@ -1850,6 +1850,9 @@ void phy_detach(struct phy_device *phyde
  	struct module *ndev_owner = NULL;
  	struct mii_bus *bus;
  
@@ -23,7 +23,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  			sysfs_remove_link(&dev->dev.kobj, "phydev");
 --- a/include/linux/phy.h
 +++ b/include/linux/phy.h
-@@ -887,6 +887,12 @@ struct phy_driver {
+@@ -900,6 +900,12 @@ struct phy_driver {
  	/** @handle_interrupt: Override default interrupt handling */
  	irqreturn_t (*handle_interrupt)(struct phy_device *phydev);
  
diff --git a/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch b/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch
new file mode 100644
index 00000000000..70724cb3a2d
--- /dev/null
+++ b/target/linux/generic/pending-6.1/704-netfilter-nf_tables-fix-bidirectional-offload-regres.patch
@@ -0,0 +1,24 @@
+From: Felix Fietkau <nbd@nbd.name>
+Date: Wed, 14 Feb 2024 15:24:41 +0100
+Subject: [PATCH] netfilter: nf_tables: fix bidirectional offload regression
+
+Commit 8f84780b84d6 ("netfilter: flowtable: allow unidirectional rules")
+made unidirectional flow offload possible, while completely ignoring (and
+breaking) bidirectional flow offload for nftables.
+Add the missing flag that was left out as an exercise for the reader :)
+
+Cc: Vlad Buslov <vladbu@nvidia.com>
+Fixes: 8f84780b84d6 ("netfilter: flowtable: allow unidirectional rules")
+Signed-off-by: Felix Fietkau <nbd@nbd.name>
+---
+
+--- a/net/netfilter/nft_flow_offload.c
++++ b/net/netfilter/nft_flow_offload.c
+@@ -357,6 +357,7 @@ static void nft_flow_offload_eval(const
+ 		ct->proto.tcp.seen[1].flags |= IP_CT_TCP_FLAG_BE_LIBERAL;
+ 	}
+ 
++	__set_bit(NF_FLOW_HW_BIDIRECTIONAL, &flow->flags);
+ 	ret = flow_offload_add(flowtable, flow);
+ 	if (ret < 0)
+ 		goto err_flow_add;
diff --git a/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch b/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch
index b03bb622d32..629b141572d 100644
--- a/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch
+++ b/target/linux/generic/pending-6.1/711-01-net-dsa-qca8k-implement-lag_fdb_add-del-ops.patch
@@ -16,7 +16,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -2004,6 +2004,8 @@ static const struct dsa_switch_ops qca8k
+@@ -2015,6 +2015,8 @@ static const struct dsa_switch_ops qca8k
  	.port_fdb_add		= qca8k_port_fdb_add,
  	.port_fdb_del		= qca8k_port_fdb_del,
  	.port_fdb_dump		= qca8k_port_fdb_dump,
diff --git a/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch b/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch
index 8ba89ccfa59..24243468a8f 100644
--- a/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch
+++ b/target/linux/generic/pending-6.1/711-02-net-dsa-qca8k-enable-flooding-to-both-CPU-port.patch
@@ -14,7 +14,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1893,15 +1893,12 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -1904,15 +1904,12 @@ qca8k_setup(struct dsa_switch *ds)
  		}
  	}
  
diff --git a/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch b/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch
index bf1415b939f..8a58e0f76e0 100644
--- a/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch
+++ b/target/linux/generic/pending-6.1/711-03-net-dsa-qca8k-add-support-for-port_change_master.patch
@@ -26,7 +26,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -1730,6 +1730,117 @@ qca8k_get_tag_protocol(struct dsa_switch
+@@ -1741,6 +1741,117 @@ qca8k_get_tag_protocol(struct dsa_switch
  	return DSA_TAG_PROTO_QCA;
  }
  
@@ -144,7 +144,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  static void
  qca8k_master_change(struct dsa_switch *ds, const struct net_device *master,
  		    bool operational)
-@@ -2016,8 +2127,9 @@ static const struct dsa_switch_ops qca8k
+@@ -2027,8 +2138,9 @@ static const struct dsa_switch_ops qca8k
  	.phylink_mac_link_down	= qca8k_phylink_mac_link_down,
  	.phylink_mac_link_up	= qca8k_phylink_mac_link_up,
  	.get_phy_flags		= qca8k_get_phy_flags,
diff --git a/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch b/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch
index 4d0b363c379..23816fe3660 100644
--- a/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch
+++ b/target/linux/generic/pending-6.1/712-net-dsa-qca8k-enable-assisted-learning-on-CPU-port.patch
@@ -20,7 +20,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/drivers/net/dsa/qca/qca8k-8xxx.c
 +++ b/drivers/net/dsa/qca/qca8k-8xxx.c
-@@ -2002,6 +2002,12 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -2013,6 +2013,12 @@ qca8k_setup(struct dsa_switch *ds)
  			dev_err(priv->dev, "failed enabling QCA header mode on port %d", dp->index);
  			return ret;
  		}
@@ -33,7 +33,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  	}
  
  	/* Forward all unknown frames to CPU port for Linux processing */
-@@ -2031,11 +2037,6 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -2042,11 +2048,6 @@ qca8k_setup(struct dsa_switch *ds)
  		if (ret)
  			return ret;
  
@@ -45,7 +45,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
  		/* For port based vlans to work we need to set the
  		 * default egress vid
  		 */
-@@ -2087,6 +2088,9 @@ qca8k_setup(struct dsa_switch *ds)
+@@ -2098,6 +2099,9 @@ qca8k_setup(struct dsa_switch *ds)
  	/* Set max number of LAGs supported */
  	ds->num_lag_ids = QCA8K_NUM_LAGS;
  
diff --git a/target/linux/generic/pending-6.1/713-03-arm64-dts-qcom-ipq8074-add-clock-frequency-to-MDIO-n.patch b/target/linux/generic/pending-6.1/713-03-arm64-dts-qcom-ipq8074-add-clock-frequency-to-MDIO-n.patch
new file mode 100644
index 00000000000..55f116ec5f2
--- /dev/null
+++ b/target/linux/generic/pending-6.1/713-03-arm64-dts-qcom-ipq8074-add-clock-frequency-to-MDIO-n.patch
@@ -0,0 +1,25 @@
+From 3b5a603bf66236b956287909556fd7ad4904450c Mon Sep 17 00:00:00 2001
+From: Christian Marangi <ansuelsmth@gmail.com>
+Date: Wed, 24 Jan 2024 19:38:01 +0100
+Subject: [PATCH 3/3] arm64: dts: qcom: ipq8074: add clock-frequency to MDIO
+ node
+
+Add clock-frequency to MDIO node to set the MDC rate to 6.25Mhz instead
+of using the default value of 390KHz from MDIO default divider.
+
+Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
+---
+ arch/arm64/boot/dts/qcom/ipq8074.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
+@@ -263,6 +263,8 @@
+ 			clocks = <&gcc GCC_MDIO_AHB_CLK>;
+ 			clock-names = "gcc_mdio_ahb_clk";
+ 
++			clock-frequency = <6250000>;
++
+ 			status = "disabled";
+ 		};
+ 
diff --git a/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch b/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
index df422e3a08b..a7a4bafbb69 100644
--- a/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
+++ b/target/linux/generic/pending-6.1/731-net-permit-ieee80211_ptr-even-with-no-CFG82111-suppo.patch
@@ -17,7 +17,7 @@ Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -2169,7 +2169,7 @@ struct net_device {
+@@ -2192,7 +2192,7 @@ struct net_device {
  #if IS_ENABLED(CONFIG_AX25)
  	void			*ax25_ptr;
  #endif
diff --git a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
index fe8841dd3e6..a1cc109050e 100644
--- a/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
+++ b/target/linux/generic/pending-6.1/732-01-net-ethernet-mtk_eth_soc-work-around-issue-with-send.patch
@@ -16,7 +16,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -1563,12 +1563,28 @@ static void mtk_wake_queue(struct mtk_et
+@@ -1562,12 +1562,28 @@ static void mtk_wake_queue(struct mtk_et
  	}
  }
  
@@ -45,7 +45,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	bool gso = false;
  	int tx_num;
  
-@@ -1590,6 +1606,18 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1589,6 +1605,18 @@ static netdev_tx_t mtk_start_xmit(struct
  		return NETDEV_TX_BUSY;
  	}
  
@@ -64,7 +64,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	/* TSO: fill MSS info in tcp checksum field */
  	if (skb_is_gso(skb)) {
  		if (skb_cow_head(skb, 0)) {
-@@ -1605,8 +1633,14 @@ static netdev_tx_t mtk_start_xmit(struct
+@@ -1604,8 +1632,14 @@ static netdev_tx_t mtk_start_xmit(struct
  		}
  	}
  
diff --git a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
index 757d2edb2c5..0a49c75b00d 100644
--- a/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
+++ b/target/linux/generic/pending-6.1/732-03-net-ethernet-mtk_eth_soc-fix-remaining-throughput-re.patch
@@ -30,7 +30,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  	switch (speed) {
  	case SPEED_2500:
  	case SPEED_1000:
-@@ -3349,6 +3350,9 @@ found:
+@@ -3348,6 +3349,9 @@ found:
  	if (dp->index >= MTK_QDMA_NUM_QUEUES)
  		return NOTIFY_DONE;
  
diff --git a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
index 23daa299989..afe561ab31f 100644
--- a/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
+++ b/target/linux/generic/pending-6.1/737-net-ethernet-mtk_eth_soc-add-paths-and-SerDes-modes-.patch
@@ -1,8 +1,8 @@
-From 1e25ca1147579bda8b941be1b9851f5911d44eb0 Mon Sep 17 00:00:00 2001
+From 91bda2f441f9e37273922028ffc48ce8e91bf5bd Mon Sep 17 00:00:00 2001
 From: Daniel Golle <daniel@makrotopia.org>
-Date: Tue, 22 Aug 2023 19:04:42 +0100
-Subject: [PATCH 098/125] net: ethernet: mtk_eth_soc: add paths and SerDes
- modes for MT7988
+Date: Tue, 12 Dec 2023 03:51:14 +0000
+Subject: [PATCH] net: ethernet: mtk_eth_soc: add paths and SerDes modes for
+ MT7988
 
 MT7988 comes with a built-in 2.5G PHY as well as SerDes lanes to
 connect external PHYs or transceivers in USXGMII, 10GBase-R, 5GBase-R,
@@ -18,50 +18,11 @@ modes.
 
 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 ---
- drivers/net/ethernet/mediatek/Kconfig        |  16 +
- drivers/net/ethernet/mediatek/Makefile       |   1 +
- drivers/net/ethernet/mediatek/mtk_eth_path.c | 123 +++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 182 ++++-
- drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 232 ++++++-
- drivers/net/ethernet/mediatek/mtk_usxgmii.c  | 692 +++++++++++++++++++
- 6 files changed, 1215 insertions(+), 31 deletions(-)
- create mode 100644 drivers/net/ethernet/mediatek/mtk_usxgmii.c
+ drivers/net/ethernet/mediatek/mtk_eth_path.c | 122 +++++++-
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c  | 291 +++++++++++++++++--
+ drivers/net/ethernet/mediatek/mtk_eth_soc.h  | 107 ++++++-
+ 3 files changed, 469 insertions(+), 51 deletions(-)
 
---- a/drivers/net/ethernet/mediatek/Kconfig
-+++ b/drivers/net/ethernet/mediatek/Kconfig
-@@ -25,6 +25,22 @@ config NET_MEDIATEK_SOC
- 	  This driver supports the gigabit ethernet MACs in the
- 	  MediaTek SoC family.
- 
-+config NET_MEDIATEK_SOC_USXGMII
-+	bool "Support USXGMII SerDes on MT7988"
-+	depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST
-+	def_bool NET_MEDIATEK_SOC != n
-+	help
-+	  Include support for 10GE SerDes which can be found on MT7988.
-+	  If this kernel should run on SoCs with 10 GBit/s Ethernet you
-+	  will need to select this option to use GMAC2 and GMAC3 with
-+	  external PHYs, SFP(+) cages in 10GBase-R, 5GBase-R or USXGMII
-+	  interface modes.
-+
-+	  Note that as the 2500Base-X/1000Base-X/Cisco SGMII SerDes PCS
-+	  unit (MediaTek LynxI) in MT7988 is connected via the new 10GE
-+	  SerDes, you will also need to select this option in case you
-+	  want to use any of those SerDes modes.
-+
- config NET_MEDIATEK_STAR_EMAC
- 	tristate "MediaTek STAR Ethernet MAC support"
- 	select PHYLIB
---- a/drivers/net/ethernet/mediatek/Makefile
-+++ b/drivers/net/ethernet/mediatek/Makefile
-@@ -5,6 +5,7 @@
- 
- obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
- mtk_eth-y := mtk_eth_soc.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o mtk_ppe_offload.o
-+mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_USXGMII) += mtk_usxgmii.o
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed.o mtk_wed_mcu.o mtk_wed_wo.o
- ifdef CONFIG_DEBUG_FS
- mtk_eth-$(CONFIG_NET_MEDIATEK_SOC_WED) += mtk_wed_debugfs.o
 --- a/drivers/net/ethernet/mediatek/mtk_eth_path.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_path.c
 @@ -31,10 +31,20 @@ static const char *mtk_eth_path_name(u64
@@ -242,14 +203,31 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	/* Setup proper MUXes along the path */
  	return mtk_eth_mux_setup(eth, path);
-@@ -284,4 +398,3 @@ int mtk_gmac_rgmii_path_setup(struct mtk
- 	/* Setup proper MUXes along the path */
- 	return mtk_eth_mux_setup(eth, path);
- }
--
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
-@@ -475,6 +475,30 @@ static void mtk_setup_bridge_switch(stru
+@@ -21,6 +21,8 @@
+ #include <linux/pinctrl/devinfo.h>
+ #include <linux/phylink.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/phy/phy.h>
+ #include <linux/jhash.h>
+ #include <linux/bitfield.h>
+ #include <net/dsa.h>
+@@ -258,12 +260,8 @@ static const char * const mtk_clks_sourc
+ 	"ethwarp_wocpu2",
+ 	"ethwarp_wocpu1",
+ 	"ethwarp_wocpu0",
+-	"top_usxgmii0_sel",
+-	"top_usxgmii1_sel",
+ 	"top_sgm0_sel",
+ 	"top_sgm1_sel",
+-	"top_xfi_phy0_xtal_sel",
+-	"top_xfi_phy1_xtal_sel",
+ 	"top_eth_gmii_sel",
+ 	"top_eth_refck_50m_sel",
+ 	"top_eth_sys_200m_sel",
+@@ -475,6 +473,30 @@ static void mtk_setup_bridge_switch(stru
  		MTK_GSW_CFG);
  }
  
@@ -280,34 +258,29 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  static struct phylink_pcs *mtk_mac_select_pcs(struct phylink_config *config,
  					      phy_interface_t interface)
  {
-@@ -483,12 +507,20 @@ static struct phylink_pcs *mtk_mac_selec
+@@ -483,6 +505,21 @@ static struct phylink_pcs *mtk_mac_selec
  	struct mtk_eth *eth = mac->hw;
  	unsigned int sid;
  
--	if (interface == PHY_INTERFACE_MODE_SGMII ||
--	    phy_interface_mode_is_8023z(interface)) {
--		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
--		       0 : mac->id;
--
--		return eth->sgmii_pcs[sid];
-+	if ((interface == PHY_INTERFACE_MODE_SGMII ||
-+	     phy_interface_mode_is_8023z(interface)) &&
-+	    MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
-+		sid = mtk_mac2xgmii_id(eth, mac->id);
-+		if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII))
-+			return mtk_sgmii_wrapper_select_pcs(eth, mac->id);
-+		else
-+			return eth->sgmii_pcs[sid];
-+	} else if ((interface == PHY_INTERFACE_MODE_USXGMII ||
-+		    interface == PHY_INTERFACE_MODE_10GBASER ||
-+		    interface == PHY_INTERFACE_MODE_5GBASER) &&
-+		   MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII) &&
-+		   mac->id != MTK_GMAC1_ID) {
-+		return mtk_usxgmii_select_pcs(eth, mac->id);
- 	}
- 
- 	return NULL;
-@@ -544,7 +576,22 @@ static void mtk_mac_config(struct phylin
++	if (mtk_is_netsys_v3_or_greater(eth)) {
++		switch (interface) {
++		case PHY_INTERFACE_MODE_1000BASEX:
++		case PHY_INTERFACE_MODE_2500BASEX:
++		case PHY_INTERFACE_MODE_SGMII:
++			return mac->sgmii_pcs;
++		case PHY_INTERFACE_MODE_5GBASER:
++		case PHY_INTERFACE_MODE_10GBASER:
++		case PHY_INTERFACE_MODE_USXGMII:
++			return mac->usxgmii_pcs;
++		default:
++			return NULL;
++		}
++	}
++
+ 	if (interface == PHY_INTERFACE_MODE_SGMII ||
+ 	    phy_interface_mode_is_8023z(interface)) {
+ 		sid = (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII)) ?
+@@ -544,7 +581,22 @@ static void mtk_mac_config(struct phylin
  					goto init_err;
  			}
  			break;
@@ -330,7 +303,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  			break;
  		default:
  			goto err_phy;
-@@ -599,8 +646,6 @@ static void mtk_mac_config(struct phylin
+@@ -599,8 +651,6 @@ static void mtk_mac_config(struct phylin
  		val &= ~SYSCFG0_GE_MODE(SYSCFG0_GE_MASK, mac->id);
  		val |= SYSCFG0_GE_MODE(ge_mode, mac->id);
  		regmap_write(eth->ethsys, ETHSYS_SYSCFG0, val);
@@ -339,7 +312,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	}
  
  	/* SGMII */
-@@ -617,21 +662,40 @@ static void mtk_mac_config(struct phylin
+@@ -617,21 +667,40 @@ static void mtk_mac_config(struct phylin
  
  		/* Save the syscfg0 value for mac_finish */
  		mac->syscfg0 = val;
@@ -387,7 +360,37 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	return;
  
  err_phy:
-@@ -677,10 +741,13 @@ static void mtk_mac_link_down(struct phy
+@@ -644,6 +713,18 @@ init_err:
+ 		mac->id, phy_modes(state->interface), err);
+ }
+ 
++static int mtk_mac_prepare(struct phylink_config *config, unsigned int mode,
++			   phy_interface_t interface)
++{
++	struct mtk_mac *mac = container_of(config, struct mtk_mac,
++					   phylink_config);
++
++	if (mac->pextp && mac->interface != interface)
++		phy_reset(mac->pextp);
++
++	return 0;
++}
++
+ static int mtk_mac_finish(struct phylink_config *config, unsigned int mode,
+ 			  phy_interface_t interface)
+ {
+@@ -652,6 +733,10 @@ static int mtk_mac_finish(struct phylink
+ 	struct mtk_eth *eth = mac->hw;
+ 	u32 mcr_cur, mcr_new;
+ 
++	/* Setup PMA/PMD */
++	if (mac->pextp)
++		phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
++
+ 	/* Enable SGMII */
+ 	if (interface == PHY_INTERFACE_MODE_SGMII ||
+ 	    phy_interface_mode_is_8023z(interface))
+@@ -677,10 +762,13 @@ static void mtk_mac_link_down(struct phy
  {
  	struct mtk_mac *mac = container_of(config, struct mtk_mac,
  					   phylink_config);
@@ -404,7 +407,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  }
  
  static void mtk_set_queue_speed(struct mtk_eth *eth, unsigned int idx,
-@@ -752,13 +819,11 @@ static void mtk_set_queue_speed(struct m
+@@ -752,13 +840,11 @@ static void mtk_set_queue_speed(struct m
  	mtk_w32(eth, val, soc->reg_map->qdma.qtx_sch + ofs);
  }
  
@@ -422,7 +425,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	u32 mcr;
  
  	mcr = mtk_r32(mac->hw, MTK_MAC_MCR(mac->id));
-@@ -792,6 +857,55 @@ static void mtk_mac_link_up(struct phyli
+@@ -792,9 +878,63 @@ static void mtk_mac_link_up(struct phyli
  	mtk_w32(mac->hw, mcr, MTK_MAC_MCR(mac->id));
  }
  
@@ -473,12 +476,98 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
 +	else
 +		mtk_gdm_mac_link_up(mac, phy, mode, interface, speed, duplex,
 +				    tx_pause, rx_pause);
++
++	/* Repeat pextp setup to tune link */
++	if (mac->pextp)
++		phy_set_mode_ext(mac->pextp, PHY_MODE_ETHERNET, interface);
 +}
 +
  static const struct phylink_mac_ops mtk_phylink_ops = {
- 	.validate = phylink_generic_validate,
  	.mac_select_pcs = mtk_mac_select_pcs,
-@@ -4617,8 +4731,21 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	.mac_config = mtk_mac_config,
++	.mac_prepare = mtk_mac_prepare,
+ 	.mac_finish = mtk_mac_finish,
+ 	.mac_link_down = mtk_mac_link_down,
+ 	.mac_link_up = mtk_mac_link_up,
+@@ -3373,6 +3513,9 @@ static int mtk_open(struct net_device *d
+ 	struct mtk_eth *eth = mac->hw;
+ 	int i, err;
+ 
++	if (mac->pextp)
++		phy_power_on(mac->pextp);
++
+ 	err = phylink_of_phy_connect(mac->phylink, mac->of_node, 0);
+ 	if (err) {
+ 		netdev_err(dev, "%s: could not attach PHY: %d\n", __func__,
+@@ -3501,6 +3644,9 @@ static int mtk_stop(struct net_device *d
+ 	for (i = 0; i < ARRAY_SIZE(eth->ppe); i++)
+ 		mtk_ppe_stop(eth->ppe[i]);
+ 
++	if (mac->pextp)
++		phy_power_off(mac->pextp);
++
+ 	return 0;
+ }
+ 
+@@ -4498,6 +4644,7 @@ static const struct net_device_ops mtk_n
+ static int mtk_add_mac(struct mtk_eth *eth, struct device_node *np)
+ {
+ 	const __be32 *_id = of_get_property(np, "reg", NULL);
++	struct device_node *pcs_np;
+ 	phy_interface_t phy_mode;
+ 	struct phylink *phylink;
+ 	struct mtk_mac *mac;
+@@ -4533,16 +4680,41 @@ static int mtk_add_mac(struct mtk_eth *e
+ 	mac->id = id;
+ 	mac->hw = eth;
+ 	mac->of_node = np;
++	pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 0);
++	if (pcs_np) {
++		mac->sgmii_pcs = mtk_pcs_lynxi_get(eth->dev, pcs_np);
++		if (IS_ERR(mac->sgmii_pcs)) {
++			if (PTR_ERR(mac->sgmii_pcs) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
+ 
+-	err = of_get_ethdev_address(mac->of_node, eth->netdev[id]);
+-	if (err == -EPROBE_DEFER)
+-		return err;
++			dev_err(eth->dev, "cannot select SGMII PCS, error %ld\n",
++				PTR_ERR(mac->sgmii_pcs));
++			return PTR_ERR(mac->sgmii_pcs);
++		}
++	}
+ 
+-	if (err) {
+-		/* If the mac address is invalid, use random mac address */
+-		eth_hw_addr_random(eth->netdev[id]);
+-		dev_err(eth->dev, "generated random MAC address %pM\n",
+-			eth->netdev[id]->dev_addr);
++	pcs_np = of_parse_phandle(mac->of_node, "pcs-handle", 1);
++	if (pcs_np) {
++		mac->usxgmii_pcs = mtk_usxgmii_pcs_get(eth->dev, pcs_np);
++		if (IS_ERR(mac->usxgmii_pcs)) {
++			if (PTR_ERR(mac->usxgmii_pcs) == -EPROBE_DEFER)
++				return -EPROBE_DEFER;
++
++			dev_err(eth->dev, "cannot select USXGMII PCS, error %ld\n",
++				PTR_ERR(mac->usxgmii_pcs));
++			return PTR_ERR(mac->usxgmii_pcs);
++		}
++	}
++
++	if (mtk_is_netsys_v3_or_greater(eth) && (mac->sgmii_pcs || mac->usxgmii_pcs)) {
++		mac->pextp = devm_of_phy_get(eth->dev, mac->of_node, NULL);
++		if (IS_ERR(mac->pextp)) {
++			if (PTR_ERR(mac->pextp) != -EPROBE_DEFER)
++				dev_err(eth->dev, "cannot get PHY, error %ld\n",
++					PTR_ERR(mac->pextp));
++
++			return PTR_ERR(mac->pextp);
++		}
+ 	}
+ 
+ 	memset(mac->hwlro_ip, 0, sizeof(mac->hwlro_ip));
+@@ -4616,8 +4788,21 @@ static int mtk_add_mac(struct mtk_eth *e
  		phy_interface_zero(mac->phylink_config.supported_interfaces);
  		__set_bit(PHY_INTERFACE_MODE_INTERNAL,
  			  mac->phylink_config.supported_interfaces);
@@ -500,23 +589,91 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	phylink = phylink_create(&mac->phylink_config,
  				 of_fwnode_handle(mac->of_node),
  				 phy_mode, &mtk_phylink_ops);
-@@ -4811,6 +4938,13 @@ static int mtk_probe(struct platform_dev
+@@ -4662,6 +4847,26 @@ free_netdev:
+ 	return err;
+ }
+ 
++static int mtk_mac_assign_address(struct mtk_eth *eth, int i, bool test_defer_only)
++{
++	int err = of_get_ethdev_address(eth->mac[i]->of_node, eth->netdev[i]);
++
++	if (err == -EPROBE_DEFER)
++		return err;
++
++	if (test_defer_only)
++		return 0;
++
++	if (err) {
++		/* If the mac address is invalid, use random mac address */
++		eth_hw_addr_random(eth->netdev[i]);
++		dev_err(eth->dev, "generated random MAC address %pM\n",
++			eth->netdev[i]);
++	}
++
++	return 0;
++}
++
+ void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev)
+ {
+ 	struct net_device *dev, *tmp;
+@@ -4805,7 +5010,8 @@ static int mtk_probe(struct platform_dev
+ 			regmap_write(cci, 0, 3);
+ 	}
+ 
+-	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII)) {
++	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SGMII) &&
++	    !mtk_is_netsys_v3_or_greater(eth)) {
+ 		err = mtk_sgmii_init(eth);
  
  		if (err)
- 			return err;
+@@ -4916,6 +5122,24 @@ static int mtk_probe(struct platform_dev
+ 		}
+ 	}
+ 
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
++
++		err = mtk_mac_assign_address(eth, i, true);
++		if (err)
++			goto err_deinit_hw;
 +	}
 +
-+	if (MTK_HAS_CAPS(eth->soc->caps, MTK_USXGMII)) {
-+		err = mtk_usxgmii_init(eth);
++	for (i = 0; i < MTK_MAX_DEVS; i++) {
++		if (!eth->netdev[i])
++			continue;
 +
++		err = mtk_mac_assign_address(eth, i, false);
 +		if (err)
-+			return err;
++			goto err_deinit_hw;
++	}
++
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_INT)) {
+ 		err = devm_request_irq(eth->dev, eth->irq[0],
+ 				       mtk_handle_irq, 0,
+@@ -5018,6 +5242,11 @@ static int mtk_remove(struct platform_de
+ 		mtk_stop(eth->netdev[i]);
+ 		mac = netdev_priv(eth->netdev[i]);
+ 		phylink_disconnect_phy(mac->phylink);
++		if (mac->sgmii_pcs)
++			mtk_pcs_lynxi_put(mac->sgmii_pcs);
++
++		if (mac->usxgmii_pcs)
++			mtk_usxgmii_pcs_put(mac->usxgmii_pcs);
  	}
  
- 	if (eth->soc->required_pctl) {
+ 	mtk_wed_exit();
 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
-@@ -502,6 +502,21 @@
+@@ -15,6 +15,7 @@
+ #include <linux/u64_stats_sync.h>
+ #include <linux/refcount.h>
+ #include <linux/phylink.h>
++#include <linux/reset.h>
+ #include <linux/rhashtable.h>
+ #include <linux/dim.h>
+ #include <linux/bitfield.h>
+@@ -502,6 +503,21 @@
  #define INTF_MODE_RGMII_1000    (TRGMII_MODE | TRGMII_CENTRAL_ALIGNED)
  #define INTF_MODE_RGMII_10_100  0
  
@@ -538,7 +695,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* GPIO port control registers for GMAC 2*/
  #define GPIO_OD33_CTRL8		0x4c0
  #define GPIO_BIAS_CTRL		0xed0
-@@ -527,6 +542,7 @@
+@@ -527,6 +543,7 @@
  #define SYSCFG0_SGMII_GMAC2    ((3 << 8) & SYSCFG0_SGMII_MASK)
  #define SYSCFG0_SGMII_GMAC1_V2 BIT(9)
  #define SYSCFG0_SGMII_GMAC2_V2 BIT(8)
@@ -546,72 +703,9 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  
  /* ethernet subsystem clock register */
-@@ -559,12 +575,74 @@
- #define ETHSYS_DMA_AG_MAP_QDMA	BIT(1)
- #define ETHSYS_DMA_AG_MAP_PPE	BIT(2)
- 
-+/* USXGMII subsystem config registers */
-+/* Register to control speed */
-+#define RG_PHY_TOP_SPEED_CTRL1	0x80C
-+#define USXGMII_RATE_UPDATE_MODE	BIT(31)
-+#define USXGMII_MAC_CK_GATED	BIT(29)
-+#define USXGMII_IF_FORCE_EN	BIT(28)
-+#define USXGMII_RATE_ADAPT_MODE	GENMASK(10, 8)
-+#define USXGMII_RATE_ADAPT_MODE_X1	0
-+#define USXGMII_RATE_ADAPT_MODE_X2	1
-+#define USXGMII_RATE_ADAPT_MODE_X4	2
-+#define USXGMII_RATE_ADAPT_MODE_X10	3
-+#define USXGMII_RATE_ADAPT_MODE_X100	4
-+#define USXGMII_RATE_ADAPT_MODE_X5	5
-+#define USXGMII_RATE_ADAPT_MODE_X50	6
-+#define USXGMII_XFI_RX_MODE	GENMASK(6, 4)
-+#define USXGMII_XFI_RX_MODE_10G	0
-+#define USXGMII_XFI_RX_MODE_5G	1
-+#define USXGMII_XFI_TX_MODE	GENMASK(2, 0)
-+#define USXGMII_XFI_TX_MODE_10G	0
-+#define USXGMII_XFI_TX_MODE_5G	1
-+
-+/* Register to control PCS AN */
-+#define RG_PCS_AN_CTRL0		0x810
-+#define USXGMII_AN_RESTART	BIT(31)
-+#define USXGMII_AN_SYNC_CNT	GENMASK(30, 11)
-+#define USXGMII_AN_ENABLE	BIT(0)
-+
-+#define RG_PCS_AN_CTRL2		0x818
-+#define USXGMII_LINK_TIMER_IDLE_DETECT	GENMASK(29, 20)
-+#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
-+#define USXGMII_LINK_TIMER_AN_RESTART	GENMASK(9, 0)
-+
-+/* Register to read PCS AN status */
-+#define RG_PCS_AN_STS0		0x81c
-+#define USXGMII_PCS_AN_WORD	GENMASK(15, 0)
-+#define USXGMII_LPA_LATCH	BIT(31)
-+
-+/* Register to control USXGMII XFI PLL digital */
-+#define XFI_PLL_DIG_GLB8	0x08
-+#define RG_XFI_PLL_EN		BIT(31)
-+
-+/* Register to control USXGMII XFI PLL analog */
-+#define XFI_PLL_ANA_GLB8	0x108
-+#define RG_XFI_PLL_ANA_SWWA	0x02283248
-+
- /* Infrasys subsystem config registers */
- #define INFRA_MISC2            0x70c
- #define CO_QPHY_SEL            BIT(0)
+@@ -565,6 +582,11 @@
  #define GEPHY_MAC_SEL          BIT(1)
  
-+/* Toprgu subsystem config registers */
-+#define TOPRGU_SWSYSRST		0x18
-+#define SWSYSRST_UNLOCK_KEY	GENMASK(31, 24)
-+#define SWSYSRST_XFI_PLL_GRST	BIT(16)
-+#define SWSYSRST_XFI_PEXPT1_GRST	BIT(15)
-+#define SWSYSRST_XFI_PEXPT0_GRST	BIT(14)
-+#define SWSYSRST_XFI1_GRST	BIT(13)
-+#define SWSYSRST_XFI0_GRST	BIT(12)
-+#define SWSYSRST_SGMII1_GRST	BIT(2)
-+#define SWSYSRST_SGMII0_GRST	BIT(1)
-+#define TOPRGU_SWSYSRST_EN		0xFC
-+
  /* Top misc registers */
 +#define TOP_MISC_NETSYS_PCS_MUX	0x84
 +#define NETSYS_PCS_MUX_MASK	GENMASK(1, 0)
@@ -621,7 +715,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define USB_PHY_SWITCH_REG	0x218
  #define QPHY_SEL_MASK		GENMASK(1, 0)
  #define SGMII_QPHY_SEL		0x2
-@@ -589,6 +667,8 @@
+@@ -589,6 +611,8 @@
  #define MT7628_SDM_RBCNT	(MT7628_SDM_OFFSET + 0x10c)
  #define MT7628_SDM_CS_ERR	(MT7628_SDM_OFFSET + 0x110)
  
@@ -630,7 +724,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_FE_CDM1_FSM		0x220
  #define MTK_FE_CDM2_FSM		0x224
  #define MTK_FE_CDM3_FSM		0x238
-@@ -597,6 +677,11 @@
+@@ -597,6 +621,11 @@
  #define MTK_FE_CDM6_FSM		0x328
  #define MTK_FE_GDM1_FSM		0x228
  #define MTK_FE_GDM2_FSM		0x22C
@@ -642,7 +736,40 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_MAC_FSM(x)		(0x1010C + ((x) * 0x100))
  
-@@ -943,6 +1028,8 @@ enum mkt_eth_capabilities {
+@@ -721,12 +750,8 @@ enum mtk_clks_map {
+ 	MTK_CLK_ETHWARP_WOCPU2,
+ 	MTK_CLK_ETHWARP_WOCPU1,
+ 	MTK_CLK_ETHWARP_WOCPU0,
+-	MTK_CLK_TOP_USXGMII_SBUS_0_SEL,
+-	MTK_CLK_TOP_USXGMII_SBUS_1_SEL,
+ 	MTK_CLK_TOP_SGM_0_SEL,
+ 	MTK_CLK_TOP_SGM_1_SEL,
+-	MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL,
+-	MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL,
+ 	MTK_CLK_TOP_ETH_GMII_SEL,
+ 	MTK_CLK_TOP_ETH_REFCK_50M_SEL,
+ 	MTK_CLK_TOP_ETH_SYS_200M_SEL,
+@@ -797,19 +822,9 @@ enum mtk_clks_map {
+ 				 BIT_ULL(MTK_CLK_GP3) | BIT_ULL(MTK_CLK_XGP1) | \
+ 				 BIT_ULL(MTK_CLK_XGP2) | BIT_ULL(MTK_CLK_XGP3) | \
+ 				 BIT_ULL(MTK_CLK_CRYPTO) | \
+-				 BIT_ULL(MTK_CLK_SGMII_TX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII_RX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII2_TX_250M) | \
+-				 BIT_ULL(MTK_CLK_SGMII2_RX_250M) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU2) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU1) | \
+ 				 BIT_ULL(MTK_CLK_ETHWARP_WOCPU0) | \
+-				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_0_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_USXGMII_SBUS_1_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_SGM_0_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_SGM_1_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_0_XTAL_SEL) | \
+-				 BIT_ULL(MTK_CLK_TOP_XFI_PHY_1_XTAL_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_GMII_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_REFCK_50M_SEL) | \
+ 				 BIT_ULL(MTK_CLK_TOP_ETH_SYS_200M_SEL) | \
+@@ -943,6 +958,8 @@ enum mkt_eth_capabilities {
  	MTK_RGMII_BIT = 0,
  	MTK_TRGMII_BIT,
  	MTK_SGMII_BIT,
@@ -651,7 +778,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  	MTK_ESW_BIT,
  	MTK_GEPHY_BIT,
  	MTK_MUX_BIT,
-@@ -963,8 +1050,11 @@ enum mkt_eth_capabilities {
+@@ -963,8 +980,11 @@ enum mkt_eth_capabilities {
  	MTK_ETH_MUX_GDM1_TO_GMAC1_ESW_BIT,
  	MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT,
  	MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT,
@@ -663,7 +790,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  	/* PATH BITS */
  	MTK_ETH_PATH_GMAC1_RGMII_BIT,
-@@ -972,14 +1062,21 @@ enum mkt_eth_capabilities {
+@@ -972,14 +992,21 @@ enum mkt_eth_capabilities {
  	MTK_ETH_PATH_GMAC1_SGMII_BIT,
  	MTK_ETH_PATH_GMAC2_RGMII_BIT,
  	MTK_ETH_PATH_GMAC2_SGMII_BIT,
@@ -685,7 +812,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_ESW			BIT_ULL(MTK_ESW_BIT)
  #define MTK_GEPHY		BIT_ULL(MTK_GEPHY_BIT)
  #define MTK_MUX			BIT_ULL(MTK_MUX_BIT)
-@@ -1002,10 +1099,16 @@ enum mkt_eth_capabilities {
+@@ -1002,10 +1029,16 @@ enum mkt_eth_capabilities {
  	BIT_ULL(MTK_ETH_MUX_GMAC2_GMAC0_TO_GEPHY_BIT)
  #define MTK_ETH_MUX_U3_GMAC2_TO_QPHY		\
  	BIT_ULL(MTK_ETH_MUX_U3_GMAC2_TO_QPHY_BIT)
@@ -702,7 +829,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  /* Supported path present on SoCs */
  #define MTK_ETH_PATH_GMAC1_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_RGMII_BIT)
-@@ -1013,8 +1116,13 @@ enum mkt_eth_capabilities {
+@@ -1013,8 +1046,13 @@ enum mkt_eth_capabilities {
  #define MTK_ETH_PATH_GMAC1_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC1_SGMII_BIT)
  #define MTK_ETH_PATH_GMAC2_RGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_RGMII_BIT)
  #define MTK_ETH_PATH_GMAC2_SGMII	BIT_ULL(MTK_ETH_PATH_GMAC2_SGMII_BIT)
@@ -716,7 +843,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  #define MTK_GMAC1_RGMII		(MTK_ETH_PATH_GMAC1_RGMII | MTK_RGMII)
  #define MTK_GMAC1_TRGMII	(MTK_ETH_PATH_GMAC1_TRGMII | MTK_TRGMII)
-@@ -1022,7 +1130,12 @@ enum mkt_eth_capabilities {
+@@ -1022,7 +1060,12 @@ enum mkt_eth_capabilities {
  #define MTK_GMAC2_RGMII		(MTK_ETH_PATH_GMAC2_RGMII | MTK_RGMII)
  #define MTK_GMAC2_SGMII		(MTK_ETH_PATH_GMAC2_SGMII | MTK_SGMII)
  #define MTK_GMAC2_GEPHY		(MTK_ETH_PATH_GMAC2_GEPHY | MTK_GEPHY)
@@ -729,7 +856,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  /* MUXes present on SoCs */
  /* 0: GDM1 -> GMAC1, 1: GDM1 -> ESW */
-@@ -1041,10 +1154,20 @@ enum mkt_eth_capabilities {
+@@ -1041,10 +1084,20 @@ enum mkt_eth_capabilities {
  	(MTK_ETH_MUX_GMAC1_GMAC2_TO_SGMII_RGMII | MTK_MUX | \
  	MTK_SHARED_SGMII)
  
@@ -750,7 +877,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  #define MTK_HAS_CAPS(caps, _x)		(((caps) & (_x)) == (_x))
  
  #define MT7621_CAPS  (MTK_GMAC1_RGMII | MTK_GMAC1_TRGMII | \
-@@ -1076,8 +1199,12 @@ enum mkt_eth_capabilities {
+@@ -1076,8 +1129,12 @@ enum mkt_eth_capabilities {
  		      MTK_MUX_GMAC12_TO_GEPHY_SGMII | MTK_QDMA | \
  		      MTK_RSTCTRL_PPE1 | MTK_SRAM)
  
@@ -765,56 +892,17 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  struct mtk_tx_dma_desc_info {
  	dma_addr_t	addr;
-@@ -1187,6 +1314,24 @@ struct mtk_soc_data {
- /* currently no SoC has more than 3 macs */
- #define MTK_MAX_DEVS	3
- 
-+/* struct mtk_usxgmii_pcs - This structure holds each usxgmii regmap and
-+ *			associated data
-+ * @regmap:		The register map pointing at the range used to setup
-+ *			USXGMII modes
-+ * @interface:		Currently selected interface mode
-+ * @id:			The element is used to record the index of PCS
-+ * @pcs:		Phylink PCS structure
-+ */
-+struct mtk_usxgmii_pcs {
-+	struct mtk_eth		*eth;
-+	struct regmap		*regmap;
-+	struct phylink_pcs	*wrapped_sgmii_pcs;
-+	phy_interface_t		interface;
-+	u8			id;
-+	unsigned int		mode;
-+	struct phylink_pcs	pcs;
-+};
-+
- /* struct mtk_eth -	This is the main datasructure for holding the state
-  *			of the driver
-  * @dev:		The device pointer
-@@ -1207,6 +1352,12 @@ struct mtk_soc_data {
-  * @infra:              The register map pointing at the range used to setup
-  *                      SGMII and GePHY path
-  * @sgmii_pcs:		Pointers to mtk-pcs-lynxi phylink_pcs instances
-+ * @sgmii_wrapped_pcs:	Pointers to NETSYSv3 wrapper PCS instances
-+ * @usxgmii_pll:	The register map pointing at the range used to control
-+ *			the USXGMII SerDes PLL
-+ * @regmap_pextp:	The register map pointing at the range used to setup
-+ *			PHYA
-+ * @usxgmii_pcs:	Pointer to array of pointers to struct for USXGMII PCS
-  * @pctl:		The register map pointing at the range used to setup
-  *			GMAC port drive/slew values
-  * @dma_refcnt:		track how many netdevs are using the DMA engine
-@@ -1250,6 +1401,10 @@ struct mtk_eth {
- 	struct regmap			*ethsys;
- 	struct regmap			*infra;
- 	struct phylink_pcs		*sgmii_pcs[MTK_MAX_DEVS];
-+	struct regmap			*toprgu;
-+	struct regmap			*usxgmii_pll;
-+	struct regmap			*regmap_pextp[MTK_MAX_DEVS];
-+	struct mtk_usxgmii_pcs		*usxgmii_pcs[MTK_MAX_DEVS];
- 	struct regmap			*pctl;
- 	bool				hwlro;
- 	refcount_t			dma_refcnt;
-@@ -1437,6 +1592,19 @@ static inline u32 mtk_get_ib2_multicast_
+@@ -1314,6 +1371,9 @@ struct mtk_mac {
+ 	struct device_node		*of_node;
+ 	struct phylink			*phylink;
+ 	struct phylink_config		phylink_config;
++	struct phylink_pcs		*sgmii_pcs;
++	struct phylink_pcs		*usxgmii_pcs;
++	struct phy			*pextp;
+ 	struct mtk_eth			*hw;
+ 	struct mtk_hw_stats		*hw_stats;
+ 	__be32				hwlro_ip[MTK_MAX_LRO_IP_CNT];
+@@ -1437,6 +1497,19 @@ static inline u32 mtk_get_ib2_multicast_
  	return MTK_FOE_IB2_MULTICAST;
  }
  
@@ -834,7 +922,7 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  /* read the hardware status register */
  void mtk_stats_update_mac(struct mtk_mac *mac);
  
-@@ -1445,8 +1613,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
+@@ -1445,8 +1518,10 @@ u32 mtk_r32(struct mtk_eth *eth, unsigne
  u32 mtk_m32(struct mtk_eth *eth, u32 mask, u32 set, unsigned int reg);
  
  int mtk_gmac_sgmii_path_setup(struct mtk_eth *eth, int mac_id);
@@ -845,760 +933,3 @@ Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  
  int mtk_eth_offload_init(struct mtk_eth *eth);
  int mtk_eth_setup_tc(struct net_device *dev, enum tc_setup_type type,
-@@ -1456,5 +1626,63 @@ int mtk_flow_offload_cmd(struct mtk_eth
- void mtk_flow_offload_cleanup(struct mtk_eth *eth, struct list_head *list);
- void mtk_eth_set_dma_device(struct mtk_eth *eth, struct device *dma_dev);
- 
-+static inline int mtk_mac2xgmii_id(struct mtk_eth *eth, int mac_id)
-+{
-+	int xgmii_id = mac_id;
-+
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
-+		switch (mac_id) {
-+		case MTK_GMAC1_ID:
-+		case MTK_GMAC2_ID:
-+			xgmii_id = 1;
-+			break;
-+		case MTK_GMAC3_ID:
-+			xgmii_id = 0;
-+			break;
-+		default:
-+			xgmii_id = -1;
-+		}
-+	}
-+
-+	return MTK_HAS_CAPS(eth->soc->caps, MTK_SHARED_SGMII) ? 0 : xgmii_id;
-+}
-+
-+static inline int mtk_xgmii2mac_id(struct mtk_eth *eth, int xgmii_id)
-+{
-+	int mac_id = xgmii_id;
-+
-+	if (mtk_is_netsys_v3_or_greater(eth)) {
-+		switch (xgmii_id) {
-+		case 0:
-+			mac_id = 2;
-+			break;
-+		case 1:
-+			mac_id = 1;
-+			break;
-+		default:
-+			mac_id = -1;
-+		}
-+	}
-+
-+	return mac_id;
-+}
-+
-+#ifdef CONFIG_NET_MEDIATEK_SOC_USXGMII
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id);
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id);
-+int mtk_usxgmii_init(struct mtk_eth *eth);
-+#else
-+static inline struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int id)
-+{
-+	return NULL;
-+}
-+
-+static inline struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int id)
-+{
-+	return NULL;
-+}
-+
-+static inline int mtk_usxgmii_init(struct mtk_eth *eth) { return 0; }
-+#endif /* NET_MEDIATEK_SOC_USXGMII */
- 
- #endif /* MTK_ETH_H */
---- /dev/null
-+++ b/drivers/net/ethernet/mediatek/mtk_usxgmii.c
-@@ -0,0 +1,690 @@
-+// SPDX-License-Identifier: GPL-2.0
-+/*
-+ * Copyright (c) 2023 MediaTek Inc.
-+ * Author: Henry Yen <henry.yen@mediatek.com>
-+ *         Daniel Golle <daniel@makrotopia.org>
-+ */
-+
-+#include <linux/mfd/syscon.h>
-+#include <linux/of.h>
-+#include <linux/regmap.h>
-+#include "mtk_eth_soc.h"
-+
-+static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
-+{
-+	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
-+}
-+
-+static int mtk_xfi_pextp_init(struct mtk_eth *eth)
-+{
-+	struct device *dev = eth->dev;
-+	struct device_node *r = dev->of_node;
-+	struct device_node *np;
-+	int i;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		np = of_parse_phandle(r, "mediatek,xfi-pextp", i);
-+		if (!np)
-+			break;
-+
-+		eth->regmap_pextp[i] = syscon_node_to_regmap(np);
-+		if (IS_ERR(eth->regmap_pextp[i]))
-+			return PTR_ERR(eth->regmap_pextp[i]);
-+	}
-+
-+	return 0;
-+}
-+
-+static int mtk_xfi_pll_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(r, "mediatek,xfi-pll", 0);
-+	if (!np)
-+		return -1;
-+
-+	eth->usxgmii_pll = syscon_node_to_regmap(np);
-+	if (IS_ERR(eth->usxgmii_pll))
-+		return PTR_ERR(eth->usxgmii_pll);
-+
-+	return 0;
-+}
-+
-+static int mtk_toprgu_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device_node *np;
-+
-+	np = of_parse_phandle(r, "mediatek,toprgu", 0);
-+	if (!np)
-+		return -1;
-+
-+	eth->toprgu = syscon_node_to_regmap(np);
-+	if (IS_ERR(eth->toprgu))
-+		return PTR_ERR(eth->toprgu);
-+
-+	return 0;
-+}
-+
-+static int mtk_xfi_pll_enable(struct mtk_eth *eth)
-+{
-+	u32 val = 0;
-+
-+	if (!eth->usxgmii_pll)
-+		return -EINVAL;
-+
-+	/* Add software workaround for USXGMII PLL TCL issue */
-+	regmap_write(eth->usxgmii_pll, XFI_PLL_ANA_GLB8, RG_XFI_PLL_ANA_SWWA);
-+
-+	regmap_read(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, &val);
-+	val |= RG_XFI_PLL_EN;
-+	regmap_write(eth->usxgmii_pll, XFI_PLL_DIG_GLB8, val);
-+
-+	return 0;
-+}
-+
-+static void mtk_usxgmii_setup_phya(struct regmap *pextp, phy_interface_t interface, int id)
-+{
-+	bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
-+		       interface == PHY_INTERFACE_MODE_USXGMII);
-+	bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
-+	bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
-+
-+	/* Setup operation mode */
-+	if (is_10g)
-+		regmap_write(pextp, 0x9024, 0x00C9071C);
-+	else
-+		regmap_write(pextp, 0x9024, 0x00D9071C);
-+
-+	if (is_5g)
-+		regmap_write(pextp, 0x2020, 0xAAA5A5AA);
-+	else
-+		regmap_write(pextp, 0x2020, 0xAA8585AA);
-+
-+	if (is_2p5g || is_5g || is_10g) {
-+		regmap_write(pextp, 0x2030, 0x0C020707);
-+		regmap_write(pextp, 0x2034, 0x0E050F0F);
-+		regmap_write(pextp, 0x2040, 0x00140032);
-+	} else {
-+		regmap_write(pextp, 0x2030, 0x0C020207);
-+		regmap_write(pextp, 0x2034, 0x0E05050F);
-+		regmap_write(pextp, 0x2040, 0x00200032);
-+	}
-+
-+	if (is_2p5g || is_10g)
-+		regmap_write(pextp, 0x50F0, 0x00C014AA);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x50F0, 0x00C018AA);
-+	else
-+		regmap_write(pextp, 0x50F0, 0x00C014BA);
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50E0, 0x3777812B);
-+		regmap_write(pextp, 0x506C, 0x005C9CFF);
-+		regmap_write(pextp, 0x5070, 0x9DFAFAFA);
-+		regmap_write(pextp, 0x5074, 0x273F3F3F);
-+		regmap_write(pextp, 0x5078, 0xA8883868);
-+		regmap_write(pextp, 0x507C, 0x14661466);
-+	} else {
-+		regmap_write(pextp, 0x50E0, 0x3777C12B);
-+		regmap_write(pextp, 0x506C, 0x005F9CFF);
-+		regmap_write(pextp, 0x5070, 0x9D9DFAFA);
-+		regmap_write(pextp, 0x5074, 0x27273F3F);
-+		regmap_write(pextp, 0x5078, 0xA7883C68);
-+		regmap_write(pextp, 0x507C, 0x11661166);
-+	}
-+
-+	if (is_2p5g || is_10g) {
-+		regmap_write(pextp, 0x5080, 0x0E000AAF);
-+		regmap_write(pextp, 0x5084, 0x08080D0D);
-+		regmap_write(pextp, 0x5088, 0x02030909);
-+	} else if (is_5g) {
-+		regmap_write(pextp, 0x5080, 0x0E001ABF);
-+		regmap_write(pextp, 0x5084, 0x080B0D0D);
-+		regmap_write(pextp, 0x5088, 0x02050909);
-+	} else {
-+		regmap_write(pextp, 0x5080, 0x0E000EAF);
-+		regmap_write(pextp, 0x5084, 0x08080E0D);
-+		regmap_write(pextp, 0x5088, 0x02030B09);
-+	}
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50E4, 0x0C000000);
-+		regmap_write(pextp, 0x50E8, 0x04000000);
-+	} else {
-+		regmap_write(pextp, 0x50E4, 0x0C0C0000);
-+		regmap_write(pextp, 0x50E8, 0x04040000);
-+	}
-+
-+	if (is_2p5g || mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x50EC, 0x0F0F0C06);
-+	else
-+		regmap_write(pextp, 0x50EC, 0x0F0F0606);
-+
-+	if (is_5g) {
-+		regmap_write(pextp, 0x50A8, 0x50808C8C);
-+		regmap_write(pextp, 0x6004, 0x18000000);
-+	} else {
-+		regmap_write(pextp, 0x50A8, 0x506E8C8C);
-+		regmap_write(pextp, 0x6004, 0x18190000);
-+	}
-+
-+	if (is_10g)
-+		regmap_write(pextp, 0x00F8, 0x01423342);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x00F8, 0x00A132A1);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x00F8, 0x009C329C);
-+	else
-+		regmap_write(pextp, 0x00F8, 0x00FA32FA);
-+
-+	/* Force SGDT_OUT off and select PCS */
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x00F4, 0x80201F20);
-+	else
-+		regmap_write(pextp, 0x00F4, 0x80201F21);
-+
-+	/* Force GLB_CKDET_OUT */
-+	regmap_write(pextp, 0x0030, 0x00050C00);
-+
-+	/* Force AEQ on */
-+	regmap_write(pextp, 0x0070, 0x02002800);
-+	ndelay(1020);
-+
-+	/* Setup DA default value */
-+	regmap_write(pextp, 0x30B0, 0x00000020);
-+	regmap_write(pextp, 0x3028, 0x00008A01);
-+	regmap_write(pextp, 0x302C, 0x0000A884);
-+	regmap_write(pextp, 0x3024, 0x00083002);
-+	if (mtk_interface_mode_is_xgmii(interface)) {
-+		regmap_write(pextp, 0x3010, 0x00022220);
-+		regmap_write(pextp, 0x5064, 0x0F020A01);
-+		regmap_write(pextp, 0x50B4, 0x06100600);
-+		if (interface == PHY_INTERFACE_MODE_USXGMII)
-+			regmap_write(pextp, 0x3048, 0x40704000);
-+		else
-+			regmap_write(pextp, 0x3048, 0x47684100);
-+	} else {
-+		regmap_write(pextp, 0x3010, 0x00011110);
-+		regmap_write(pextp, 0x3048, 0x40704000);
-+	}
-+
-+	if (!mtk_interface_mode_is_xgmii(interface) && !is_2p5g)
-+		regmap_write(pextp, 0x3064, 0x0000C000);
-+
-+	if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+		regmap_write(pextp, 0x3050, 0xA8000000);
-+		regmap_write(pextp, 0x3054, 0x000000AA);
-+	} else if (mtk_interface_mode_is_xgmii(interface)) {
-+		regmap_write(pextp, 0x3050, 0x00000000);
-+		regmap_write(pextp, 0x3054, 0x00000000);
-+	} else {
-+		regmap_write(pextp, 0x3050, 0xA8000000);
-+		regmap_write(pextp, 0x3054, 0x000000AA);
-+	}
-+
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x306C, 0x00000F00);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x306C, 0x22000F00);
-+	else
-+		regmap_write(pextp, 0x306C, 0x20200F00);
-+
-+	if (interface == PHY_INTERFACE_MODE_10GBASER && id == 0)
-+		regmap_write(pextp, 0xA008, 0x0007B400);
-+
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0xA060, 0x00040000);
-+	else
-+		regmap_write(pextp, 0xA060, 0x00050000);
-+
-+	if (is_10g)
-+		regmap_write(pextp, 0x90D0, 0x00000001);
-+	else if (is_5g)
-+		regmap_write(pextp, 0x90D0, 0x00000003);
-+	else if (is_2p5g)
-+		regmap_write(pextp, 0x90D0, 0x00000005);
-+	else
-+		regmap_write(pextp, 0x90D0, 0x00000007);
-+
-+	/* Release reset */
-+	regmap_write(pextp, 0x0070, 0x0200E800);
-+	usleep_range(150, 500);
-+
-+	/* Switch to P0 */
-+	regmap_write(pextp, 0x0070, 0x0200C111);
-+	ndelay(1020);
-+	regmap_write(pextp, 0x0070, 0x0200C101);
-+	usleep_range(15, 50);
-+
-+	if (mtk_interface_mode_is_xgmii(interface)) {
-+		/* Switch to Gen3 */
-+		regmap_write(pextp, 0x0070, 0x0202C111);
-+	} else {
-+		/* Switch to Gen2 */
-+		regmap_write(pextp, 0x0070, 0x0201C111);
-+	}
-+	ndelay(1020);
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x0070, 0x0202C101);
-+	else
-+		regmap_write(pextp, 0x0070, 0x0201C101);
-+	usleep_range(100, 500);
-+	regmap_write(pextp, 0x30B0, 0x00000030);
-+	if (mtk_interface_mode_is_xgmii(interface))
-+		regmap_write(pextp, 0x00F4, 0x80201F00);
-+	else
-+		regmap_write(pextp, 0x00F4, 0x80201F01);
-+
-+	regmap_write(pextp, 0x3040, 0x30000000);
-+	usleep_range(400, 1000);
-+}
-+
-+static void mtk_usxgmii_reset(struct mtk_eth *eth, int id)
-+{
-+	u32 toggle, val;
-+
-+	if (id >= MTK_MAX_DEVS || !eth->toprgu)
-+		return;
-+
-+	switch (id) {
-+	case 0:
-+		toggle = SWSYSRST_XFI_PEXPT0_GRST | SWSYSRST_XFI0_GRST |
-+			 SWSYSRST_SGMII0_GRST;
-+		break;
-+	case 1:
-+		toggle = SWSYSRST_XFI_PEXPT1_GRST | SWSYSRST_XFI1_GRST |
-+			 SWSYSRST_SGMII1_GRST;
-+		break;
-+	default:
-+		return;
-+	}
-+
-+	/* Enable software reset */
-+	regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+	/* Assert USXGMII reset */
-+	regmap_set_bits(eth->toprgu, TOPRGU_SWSYSRST,
-+			FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88) | toggle);
-+
-+	usleep_range(100, 500);
-+
-+	/* De-assert USXGMII reset */
-+	regmap_read(eth->toprgu, TOPRGU_SWSYSRST, &val);
-+	val |= FIELD_PREP(SWSYSRST_UNLOCK_KEY, 0x88);
-+	val &= ~toggle;
-+	regmap_write(eth->toprgu, TOPRGU_SWSYSRST, val);
-+
-+	/* Disable software reset */
-+	regmap_clear_bits(eth->toprgu, TOPRGU_SWSYSRST_EN, toggle);
-+
-+	mdelay(10);
-+}
-+
-+/* As the USXGMII PHYA is shared with the 1000Base-X/2500Base-X/Cisco SGMII unit
-+ * the psc-mtk-lynxi instance needs to be wrapped, so that calls to .pcs_config
-+ * also trigger an initial reset and subsequent configuration of the PHYA.
-+ */
-+struct mtk_sgmii_wrapper_pcs {
-+	struct mtk_eth		*eth;
-+	struct phylink_pcs	*wrapped_pcs;
-+	u8			id;
-+	struct phylink_pcs	pcs;
-+};
-+
-+static int mtk_sgmii_wrapped_pcs_config(struct phylink_pcs *pcs,
-+					unsigned int mode,
-+					phy_interface_t interface,
-+					const unsigned long *advertising,
-+					bool permit_pause_to_mac)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+	bool full_reconf;
-+	int ret;
-+
-+	full_reconf = interface != wp->eth->usxgmii_pcs[wp->id]->interface;
-+	if (full_reconf) {
-+		mtk_xfi_pll_enable(wp->eth);
-+		mtk_usxgmii_reset(wp->eth, wp->id);
-+	}
-+
-+	ret = wp->wrapped_pcs->ops->pcs_config(wp->wrapped_pcs, mode, interface,
-+					       advertising, permit_pause_to_mac);
-+
-+	if (full_reconf)
-+		mtk_usxgmii_setup_phya(wp->eth->regmap_pextp[wp->id], interface, wp->id);
-+
-+	wp->eth->usxgmii_pcs[wp->id]->interface = interface;
-+
-+	return ret;
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_get_state(struct phylink_pcs *pcs,
-+					    struct phylink_link_state *state)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	return wp->wrapped_pcs->ops->pcs_get_state(wp->wrapped_pcs, state);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_an_restart(struct phylink_pcs *pcs)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_an_restart(wp->wrapped_pcs);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_link_up(struct phylink_pcs *pcs,
-+					  unsigned int mode,
-+					  phy_interface_t interface, int speed,
-+					  int duplex)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_link_up(wp->wrapped_pcs, mode, interface, speed, duplex);
-+}
-+
-+static void mtk_sgmii_wrapped_pcs_disable(struct phylink_pcs *pcs)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp = container_of(pcs, struct mtk_sgmii_wrapper_pcs, pcs);
-+
-+	wp->wrapped_pcs->ops->pcs_disable(wp->wrapped_pcs);
-+
-+	wp->eth->usxgmii_pcs[wp->id]->interface = PHY_INTERFACE_MODE_NA;
-+}
-+
-+static const struct phylink_pcs_ops mtk_sgmii_wrapped_pcs_ops = {
-+	.pcs_get_state = mtk_sgmii_wrapped_pcs_get_state,
-+	.pcs_config = mtk_sgmii_wrapped_pcs_config,
-+	.pcs_an_restart = mtk_sgmii_wrapped_pcs_an_restart,
-+	.pcs_link_up = mtk_sgmii_wrapped_pcs_link_up,
-+	.pcs_disable = mtk_sgmii_wrapped_pcs_disable,
-+};
-+
-+static int mtk_sgmii_wrapper_init(struct mtk_eth *eth)
-+{
-+	struct mtk_sgmii_wrapper_pcs *wp;
-+	int i;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		if (!eth->sgmii_pcs[i])
-+			continue;
-+
-+		if (!eth->usxgmii_pcs[i])
-+			continue;
-+
-+		/* Make sure all PCS ops are supported by wrapped PCS */
-+		if (!eth->sgmii_pcs[i]->ops->pcs_get_state ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_config ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_an_restart ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_link_up ||
-+		    !eth->sgmii_pcs[i]->ops->pcs_disable)
-+			return -EOPNOTSUPP;
-+
-+		wp = devm_kzalloc(eth->dev, sizeof(*wp), GFP_KERNEL);
-+		if (!wp)
-+			return -ENOMEM;
-+
-+		wp->wrapped_pcs = eth->sgmii_pcs[i];
-+		wp->id = i;
-+		wp->pcs.poll = true;
-+		wp->pcs.ops = &mtk_sgmii_wrapped_pcs_ops;
-+		wp->eth = eth;
-+
-+		eth->usxgmii_pcs[i]->wrapped_sgmii_pcs = &wp->pcs;
-+	}
-+
-+	return 0;
-+}
-+
-+struct phylink_pcs *mtk_sgmii_wrapper_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+	if (!eth->usxgmii_pcs[xgmii_id])
-+		return NULL;
-+
-+	return eth->usxgmii_pcs[xgmii_id]->wrapped_sgmii_pcs;
-+}
-+
-+static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
-+				  phy_interface_t interface,
-+				  const unsigned long *advertising,
-+				  bool permit_pause_to_mac)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	struct mtk_eth *eth = mpcs->eth;
-+	struct regmap *pextp = eth->regmap_pextp[mpcs->id];
-+	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
-+	bool mode_changed = false;
-+
-+	if (!pextp)
-+		return -ENODEV;
-+
-+	if (interface == PHY_INTERFACE_MODE_USXGMII) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+	} else if (interface == PHY_INTERFACE_MODE_10GBASER) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_10G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_10G);
-+		adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
-+		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
-+		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
-+			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
-+		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_RX_MODE_5G) |
-+			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_TX_MODE_5G);
-+		adapt_mode = USXGMII_RATE_UPDATE_MODE;
-+	} else {
-+		return -EINVAL;
-+	}
-+
-+	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
-+
-+	if (mpcs->interface != interface) {
-+		mpcs->interface = interface;
-+		mode_changed = true;
-+	}
-+
-+	mtk_xfi_pll_enable(eth);
-+	mtk_usxgmii_reset(eth, mpcs->id);
-+
-+	/* Setup USXGMII AN ctrl */
-+	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL0,
-+			   USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
-+			   an_ctrl);
-+
-+	regmap_update_bits(mpcs->regmap, RG_PCS_AN_CTRL2,
-+			   USXGMII_LINK_TIMER_IDLE_DETECT |
-+			   USXGMII_LINK_TIMER_COMP_ACK_DETECT |
-+			   USXGMII_LINK_TIMER_AN_RESTART,
-+			   link_timer);
-+
-+	mpcs->mode = mode;
-+
-+	/* Gated MAC CK */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
-+
-+	/* Enable interface force mode */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
-+
-+	/* Setup USXGMII adapt mode */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
-+			   adapt_mode);
-+
-+	/* Setup USXGMII speed */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
-+			   xfi_mode);
-+
-+	usleep_range(1, 10);
-+
-+	/* Un-gated MAC CK */
-+	regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+			   USXGMII_MAC_CK_GATED, 0);
-+
-+	usleep_range(1, 10);
-+
-+	/* Disable interface force mode for the AN mode */
-+	if (an_ctrl & USXGMII_AN_ENABLE)
-+		regmap_update_bits(mpcs->regmap, RG_PHY_TOP_SPEED_CTRL1,
-+				   USXGMII_IF_FORCE_EN, 0);
-+
-+	/* Setup USXGMIISYS with the determined property */
-+	mtk_usxgmii_setup_phya(pextp, interface, mpcs->id);
-+
-+	return mode_changed;
-+}
-+
-+static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
-+				      struct phylink_link_state *state)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	struct mtk_eth *eth = mpcs->eth;
-+	struct mtk_mac *mac = eth->mac[mtk_xgmii2mac_id(eth, mpcs->id)];
-+	u32 val = 0;
-+
-+	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+	if (FIELD_GET(USXGMII_AN_ENABLE, val)) {
-+		/* Refresh LPA by inverting LPA_LATCH */
-+		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+		regmap_update_bits(mpcs->regmap, RG_PCS_AN_STS0,
-+				   USXGMII_LPA_LATCH,
-+				   !(val & USXGMII_LPA_LATCH));
-+
-+		regmap_read(mpcs->regmap, RG_PCS_AN_STS0, &val);
-+
-+		phylink_decode_usxgmii_word(state, FIELD_GET(USXGMII_PCS_AN_WORD,
-+							     val));
-+
-+		state->interface = mpcs->interface;
-+	} else {
-+		val = mtk_r32(mac->hw, MTK_XGMAC_STS(mac->id));
-+
-+		if (mac->id == MTK_GMAC2_ID)
-+			val >>= 16;
-+
-+		switch (FIELD_GET(MTK_USXGMII_PCS_MODE, val)) {
-+		case 0:
-+			state->speed = SPEED_10000;
-+			break;
-+		case 1:
-+			state->speed = SPEED_5000;
-+			break;
-+		case 2:
-+			state->speed = SPEED_2500;
-+			break;
-+		case 3:
-+			state->speed = SPEED_1000;
-+			break;
-+		}
-+
-+		state->interface = mpcs->interface;
-+		state->link = FIELD_GET(MTK_USXGMII_PCS_LINK, val);
-+		state->duplex = DUPLEX_FULL;
-+	}
-+
-+	/* Continuously repeat re-configuration sequence until link comes up */
-+	if (state->link == 0)
-+		mtk_usxgmii_pcs_config(pcs, mpcs->mode,
-+				       state->interface, NULL, false);
-+}
-+
-+static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
-+{
-+	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
-+	unsigned int val = 0;
-+
-+	if (!mpcs->regmap)
-+		return;
-+
-+	regmap_read(mpcs->regmap, RG_PCS_AN_CTRL0, &val);
-+	val |= USXGMII_AN_RESTART;
-+	regmap_write(mpcs->regmap, RG_PCS_AN_CTRL0, val);
-+}
-+
-+static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
-+				    phy_interface_t interface,
-+				    int speed, int duplex)
-+{
-+	/* Reconfiguring USXGMII to ensure the quality of the RX signal
-+	 * after the line side link up.
-+	 */
-+	mtk_usxgmii_pcs_config(pcs, mode,
-+			       interface, NULL, false);
-+}
-+
-+static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
-+	.pcs_config = mtk_usxgmii_pcs_config,
-+	.pcs_get_state = mtk_usxgmii_pcs_get_state,
-+	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
-+	.pcs_link_up = mtk_usxgmii_pcs_link_up,
-+};
-+
-+int mtk_usxgmii_init(struct mtk_eth *eth)
-+{
-+	struct device_node *r = eth->dev->of_node;
-+	struct device *dev = eth->dev;
-+	struct device_node *np;
-+	int i, ret;
-+
-+	for (i = 0; i < MTK_MAX_DEVS; i++) {
-+		np = of_parse_phandle(r, "mediatek,usxgmiisys", i);
-+		if (!np)
-+			break;
-+
-+		eth->usxgmii_pcs[i] = devm_kzalloc(dev, sizeof(*eth->usxgmii_pcs[i]), GFP_KERNEL);
-+		if (!eth->usxgmii_pcs[i])
-+			return -ENOMEM;
-+
-+		eth->usxgmii_pcs[i]->id = i;
-+		eth->usxgmii_pcs[i]->eth = eth;
-+		eth->usxgmii_pcs[i]->regmap = syscon_node_to_regmap(np);
-+		if (IS_ERR(eth->usxgmii_pcs[i]->regmap))
-+			return PTR_ERR(eth->usxgmii_pcs[i]->regmap);
-+
-+		eth->usxgmii_pcs[i]->pcs.ops = &mtk_usxgmii_pcs_ops;
-+		eth->usxgmii_pcs[i]->pcs.poll = true;
-+		eth->usxgmii_pcs[i]->interface = PHY_INTERFACE_MODE_NA;
-+		eth->usxgmii_pcs[i]->mode = -1;
-+
-+		of_node_put(np);
-+	}
-+
-+	ret = mtk_xfi_pextp_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	ret = mtk_xfi_pll_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	ret = mtk_toprgu_init(eth);
-+	if (ret)
-+		return ret;
-+
-+	return mtk_sgmii_wrapper_init(eth);
-+}
-+
-+struct phylink_pcs *mtk_usxgmii_select_pcs(struct mtk_eth *eth, int mac_id)
-+{
-+	u32 xgmii_id = mtk_mac2xgmii_id(eth, mac_id);
-+
-+	if (!eth->usxgmii_pcs[xgmii_id]->regmap)
-+		return NULL;
-+
-+	return &eth->usxgmii_pcs[xgmii_id]->pcs;
-+}
diff --git a/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch b/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
new file mode 100644
index 00000000000..b598d15866e
--- /dev/null
+++ b/target/linux/generic/pending-6.1/738-net-ethernet-mtk_eth_soc-set-coherent-mask-to-get-PP.patch
@@ -0,0 +1,46 @@
+From dee3f591103910c8d8b2a6d57879ccd2a4be4b10 Mon Sep 17 00:00:00 2001
+Message-ID: <dee3f591103910c8d8b2a6d57879ccd2a4be4b10.1706067287.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 03:19:49 +0000
+Subject: [PATCH net] net: ethernet: mtk_eth_soc: set coherent mask to get PPE
+ working
+To: Felix Fietkau <nbd@nbd.name>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Mark Lee <Mark-MC.Lee@mediatek.com>,
+    Lorenzo Bianconi <lorenzo@kernel.org>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Set DMA coherent mask to 32-bit which makes PPE offloading engine start
+working on BPi-R4 which got 4 GiB of RAM.
+
+Fixes: 2d75891ebc09 ("net: ethernet: mtk_eth_soc: support 36-bit DMA addressing on MT7988")
+Suggested-by: Elad Yifee <eladwf@users.github.com>
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/ethernet/mediatek/mtk_eth_soc.c | 5 ++++-
+ 1 file changed, 4 insertions(+), 1 deletion(-)
+
+--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
++++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
+@@ -4963,7 +4963,10 @@ static int mtk_probe(struct platform_dev
+ 	}
+ 
+ 	if (MTK_HAS_CAPS(eth->soc->caps, MTK_36BIT_DMA)) {
+-		err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36));
++		err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(36));
++		if (!err)
++			err = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
++
+ 		if (err) {
+ 			dev_err(&pdev->dev, "Wrong DMA config\n");
+ 			return -EINVAL;
diff --git a/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch b/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch
new file mode 100644
index 00000000000..1f1c40b1d91
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-01-dt-bindings-phy-mediatek-xfi-tphy-add-new-bindings.patch
@@ -0,0 +1,136 @@
+From patchwork Thu Feb  1 21:52:20 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541842
+Date: Thu, 1 Feb 2024 21:52:20 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+	Steven Liu <steven.liu@mediatek.com>,
+	John Crispin <john@phrozen.org>,
+	Chunfeng Yun <chunfeng.yun@mediatek.com>,
+	Vinod Koul <vkoul@kernel.org>,
+	Kishon Vijay Abraham I <kishon@kernel.org>,
+	Rob Herring <robh@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Qingfang Deng <dqfext@gmail.com>,
+	SkyLake Huang <SkyLake.Huang@mediatek.com>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	linux-arm-kernel@lists.infradead.org,
+	linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+	netdev@vger.kernel.org
+Subject: [PATCH 1/2] dt-bindings: phy: mediatek,xfi-tphy: add new bindings
+Message-ID: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add bindings for the MediaTek XFI T-PHY Ethernet SerDes PHY found in the
+MediaTek MT7988 SoC which can operate at various interfaces modes:
+
+via USXGMII PCS:
+ * USXGMII
+ * 10GBase-R
+ * 5GBase-R
+
+via LynxI SGMII PCS:
+ * 2500Base-X
+ * 1000Base-X
+ * Cisco SGMII (MAC side)
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/phy/mediatek,xfi-tphy.yaml       | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/mediatek,xfi-tphy.yaml
+@@ -0,0 +1,80 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/mediatek,xfi-tphy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek XFI T-PHY
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek XFI SerDes T-PHY provides the physical SerDes lanes
++  used by the (10G/5G) USXGMII PCS and (1G/2.5G) LynxI PCS found in
++  MediaTek's 10G-capabale SoCs.
++
++properties:
++  $nodename:
++    pattern: "^phy@[0-9a-f]+$"
++
++  compatible:
++    const: mediatek,mt7988-xfi-tphy
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: XFI PHY clock
++      - description: XFI register clock
++
++  clock-names:
++    items:
++      - const: xfipll
++      - const: topxtal
++
++  resets:
++    items:
++      - description: PEXTP reset
++
++  mediatek,usxgmii-performance-errata:
++    $ref: /schemas/types.yaml#/definitions/flag
++    description:
++      One instance of the T-PHY on MT7988 suffers from a performance
++      problem in 10GBase-R mode which needs a work-around in the driver.
++      The work-around is enabled using this flag.
++
++  "#phy-cells":
++    const: 0
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - resets
++  - "#phy-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      phy@11f20000 {
++        compatible = "mediatek,mt7988-xfi-tphy";
++        reg = <0 0x11f20000 0 0x10000>;
++        clocks = <&xfi_pll CLK_XFIPLL_PLL_EN>,
++                 <&topckgen CLK_TOP_XFI_PHY_0_XTAL_SEL>;
++        clock-names = "xfipll", "topxtal";
++        resets = <&watchdog 14>;
++        mediatek,usxgmii-performance-errata;
++        #phy-cells = <0>;
++      };
++    };
++
++...
diff --git a/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
new file mode 100644
index 00000000000..d7424020a78
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-02-phy-add-driver-for-MediaTek-XFI-T-PHY.patch
@@ -0,0 +1,497 @@
+From patchwork Thu Feb  1 21:53:06 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
+X-Patchwork-Id: 13541843
+Date: Thu, 1 Feb 2024 21:53:06 +0000
+From: Daniel Golle <daniel@makrotopia.org>
+To: Bc-bocun Chen <bc-bocun.chen@mediatek.com>,
+	Chunfeng Yun <chunfeng.yun@mediatek.com>,
+	Vinod Koul <vkoul@kernel.org>,
+	Kishon Vijay Abraham I <kishon@kernel.org>,
+	Rob Herring <robh@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Qingfang Deng <dqfext@gmail.com>,
+	SkyLake Huang <SkyLake.Huang@mediatek.com>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	Philipp Zabel <p.zabel@pengutronix.de>,
+	linux-arm-kernel@lists.infradead.org,
+	linux-mediatek@lists.infradead.org, linux-phy@lists.infradead.org,
+	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
+	netdev@vger.kernel.org
+Subject: [PATCH 2/2] phy: add driver for MediaTek XFI T-PHY
+Message-ID: 
+ <dd6b40ea1f7f8459a9a2cfe7fa60c1108332ade6.1706823233.git.daniel@makrotopia.org>
+References: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+MIME-Version: 1.0
+Content-Disposition: inline
+In-Reply-To: 
+ <702afb0c1246d95c90b22e57105304028bdd3083.1706823233.git.daniel@makrotopia.org>
+List-Id: Linux Phy Mailing list <linux-phy.lists.infradead.org>
+
+Add driver for MediaTek's XFI T-PHY, 10 Gigabit/s Ethernet SerDes PHY
+which can be found in the MT7988 SoC.
+
+The PHY can operates only in PHY_MODE_ETHERNET, the submode is one of
+PHY_INTERFACE_MODE_* corresponding to the supported modes:
+
+ * USXGMII                 \
+ * 10GBase-R                }- USXGMII PCS - XGDM  \
+ * 5GBase-R                /                        \
+                                                     }- Ethernet MAC
+ * 2500Base-X              \                        /
+ * 1000Base-X               }- LynxI PCS - GDM     /
+ * Cisco SGMII (MAC side)  /
+
+In order to work-around a performance issue present on the first of
+two XFI T-PHYs present in MT7988, special tuning is applied which can be
+selected by adding the 'mediatek,usxgmii-performance-errata' property to
+the device tree node.
+
+There is no documentation for most registers used for the
+analog/tuning part, however, most of the registers have been partially
+reverse-engineered from MediaTek's SDK implementation (an opaque
+sequence of 32-bit register writes) and descriptions for all relevant
+digital registers and bits such as resets and muxes have been supplied
+by MediaTek.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                             |   1 +
+ drivers/phy/mediatek/Kconfig            |  12 +
+ drivers/phy/mediatek/Makefile           |   1 +
+ drivers/phy/mediatek/phy-mtk-xfi-tphy.c | 392 ++++++++++++++++++++++++
+ 4 files changed, 406 insertions(+)
+ create mode 100644 drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+
+--- a/drivers/phy/mediatek/Kconfig
++++ b/drivers/phy/mediatek/Kconfig
+@@ -13,6 +13,18 @@ config PHY_MTK_PCIE
+ 	  callback for PCIe GEN3 port, it supports software efuse
+ 	  initialization.
+ 
++config PHY_MTK_XFI_TPHY
++	tristate "MediaTek XFI T-PHY Driver"
++	depends on ARCH_MEDIATEK || COMPILE_TEST
++	depends on OF && OF_ADDRESS
++	depends on HAS_IOMEM
++	select GENERIC_PHY
++	help
++	  Say 'Y' here to add support for MediaTek XFI T-PHY driver.
++	  The driver provides access to the Ethernet SerDes T-PHY supporting
++	  1GE and 2.5GE modes via the LynxI PCS, and 5GE and 10GE modes
++	  via the USXGMII PCS found in MediaTek SoCs with 10G Ethernet.
++
+ config PHY_MTK_TPHY
+ 	tristate "MediaTek T-PHY Driver"
+ 	depends on ARCH_MEDIATEK || COMPILE_TEST
+--- a/drivers/phy/mediatek/Makefile
++++ b/drivers/phy/mediatek/Makefile
+@@ -8,6 +8,7 @@ obj-$(CONFIG_PHY_MTK_PCIE)		+= phy-mtk-p
+ obj-$(CONFIG_PHY_MTK_TPHY)		+= phy-mtk-tphy.o
+ obj-$(CONFIG_PHY_MTK_UFS)		+= phy-mtk-ufs.o
+ obj-$(CONFIG_PHY_MTK_XSPHY)		+= phy-mtk-xsphy.o
++obj-$(CONFIG_PHY_MTK_XFI_TPHY)		+= phy-mtk-xfi-tphy.o
+ 
+ phy-mtk-hdmi-drv-y			:= phy-mtk-hdmi.o
+ phy-mtk-hdmi-drv-y			+= phy-mtk-hdmi-mt2701.o
+--- /dev/null
++++ b/drivers/phy/mediatek/phy-mtk-xfi-tphy.c
+@@ -0,0 +1,392 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/* MediaTek 10GE SerDes PHY driver
++ *
++ * Copyright (c) 2024 Daniel Golle <daniel@makrotopia.org>
++ *                    Bc-bocun Chen <bc-bocun.chen@mediatek.com>
++ * based on mtk_usxgmii.c found in MediaTek's SDK released under GPL-2.0
++ * Copyright (c) 2022 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ */
++
++#include <linux/module.h>
++#include <linux/device.h>
++#include <linux/platform_device.h>
++#include <linux/of.h>
++#include <linux/io.h>
++#include <linux/clk.h>
++#include <linux/reset.h>
++#include <linux/phy.h>
++#include <linux/phy/phy.h>
++
++#define MTK_XFI_TPHY_NUM_CLOCKS		2
++
++#define REG_DIG_GLB_70			0x0070
++#define  XTP_PCS_RX_EQ_IN_PROGRESS(x)	FIELD_PREP(GENMASK(25, 24), (x))
++#define  XTP_PCS_MODE_MASK		GENMASK(17, 16)
++#define  XTP_PCS_MODE(x)		FIELD_PREP(GENMASK(17, 16), (x))
++#define  XTP_PCS_RST_B			BIT(15)
++#define  XTP_FRC_PCS_RST_B		BIT(14)
++#define  XTP_PCS_PWD_SYNC_MASK		GENMASK(13, 12)
++#define  XTP_PCS_PWD_SYNC(x)		FIELD_PREP(XTP_PCS_PWD_SYNC_MASK, (x))
++#define  XTP_PCS_PWD_ASYNC_MASK		GENMASK(11, 10)
++#define  XTP_PCS_PWD_ASYNC(x)		FIELD_PREP(XTP_PCS_PWD_ASYNC_MASK, (x))
++#define  XTP_FRC_PCS_PWD_ASYNC		BIT(8)
++#define  XTP_PCS_UPDT			BIT(4)
++#define  XTP_PCS_IN_FR_RG		BIT(0)
++
++#define REG_DIG_GLB_F4			0x00f4
++#define  XFI_DPHY_PCS_SEL		BIT(0)
++#define   XFI_DPHY_PCS_SEL_SGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 1)
++#define   XFI_DPHY_PCS_SEL_USXGMII	FIELD_PREP(XFI_DPHY_PCS_SEL, 0)
++#define  XFI_DPHY_AD_SGDT_FRC_EN	BIT(5)
++
++#define REG_DIG_LN_TRX_40		0x3040
++#define  XTP_LN_FRC_TX_DATA_EN		BIT(29)
++#define  XTP_LN_TX_DATA_EN		BIT(28)
++
++#define REG_DIG_LN_TRX_B0		0x30b0
++#define  XTP_LN_FRC_TX_MACCK_EN		BIT(5)
++#define  XTP_LN_TX_MACCK_EN		BIT(4)
++
++#define REG_ANA_GLB_D0			0x90d0
++#define  XTP_GLB_USXGMII_SEL_MASK	GENMASK(3, 1)
++#define  XTP_GLB_USXGMII_SEL(x)		FIELD_PREP(GENMASK(3, 1), (x))
++#define  XTP_GLB_USXGMII_EN		BIT(0)
++
++struct mtk_xfi_tphy {
++	void __iomem		*base;
++	struct device		*dev;
++	struct reset_control	*reset;
++	struct clk_bulk_data	clocks[MTK_XFI_TPHY_NUM_CLOCKS];
++	bool			da_war;
++};
++
++static void mtk_xfi_tphy_write(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			       u32 value)
++{
++	iowrite32(value, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_rmw(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			     u32 clr, u32 set)
++{
++	u32 val;
++
++	val = ioread32(xfi_tphy->base + reg);
++	val &= ~clr;
++	val |= set;
++	iowrite32(val, xfi_tphy->base + reg);
++}
++
++static void mtk_xfi_tphy_set(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			     u32 set)
++{
++	mtk_xfi_tphy_rmw(xfi_tphy, reg, 0, set);
++}
++
++static void mtk_xfi_tphy_clear(struct mtk_xfi_tphy *xfi_tphy, u16 reg,
++			       u32 clr)
++{
++	mtk_xfi_tphy_rmw(xfi_tphy, reg, clr, 0);
++}
++
++static void mtk_xfi_tphy_setup(struct mtk_xfi_tphy *xfi_tphy,
++			       phy_interface_t interface)
++{
++	bool is_2p5g = (interface == PHY_INTERFACE_MODE_2500BASEX);
++	bool is_1g = (interface == PHY_INTERFACE_MODE_1000BASEX ||
++		      interface == PHY_INTERFACE_MODE_SGMII);
++	bool is_10g = (interface == PHY_INTERFACE_MODE_10GBASER ||
++		       interface == PHY_INTERFACE_MODE_USXGMII);
++	bool is_5g = (interface == PHY_INTERFACE_MODE_5GBASER);
++	bool is_xgmii = (is_10g || is_5g);
++
++	dev_dbg(xfi_tphy->dev, "setting up for mode %s\n", phy_modes(interface));
++
++	/* Setup PLL setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x9024, 0x100000, is_10g ? 0x0 : 0x100000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2020, 0x202000, is_5g ? 0x202000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2030, 0x500, is_1g ? 0x0 : 0x500);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2034, 0xa00, is_1g ? 0x0 : 0xa00);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x2040, 0x340000, is_1g ? 0x200000 :
++							     0x140000);
++
++	/* Setup RXFE BW setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50f0, 0xc10, is_1g ? 0x410 :
++							  is_5g ? 0x800 : 0x400);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e0, 0x4000, is_5g ? 0x0 : 0x4000);
++
++	/* Setup RX CDR setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x506c, 0x30000, is_5g ? 0x0 : 0x30000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5070, 0x670000, is_5g ? 0x620000 : 0x50000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5074, 0x180000, is_5g ? 0x180000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5078, 0xf000400, is_5g ? 0x8000000 :
++							      0x7000400);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x507c, 0x5000500, is_5g ? 0x4000400 :
++							      0x1000100);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5080, 0x1410, is_1g ? 0x400 :
++							   is_5g ? 0x1010 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5084, 0x30300, is_1g ? 0x30300 :
++							    is_5g ? 0x30100 :
++								    0x100);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x5088, 0x60200, is_1g ? 0x20200 :
++							 is_5g ? 0x40000 :
++								 0x20000);
++
++	/* Setting RXFE adaptation range setting */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e4, 0xc0000, is_5g ? 0x0 : 0xc0000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50e8, 0x40000, is_5g ? 0x0 : 0x40000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50ec, 0xa00, is_1g ? 0x200 : 0x800);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x50a8, 0xee0000, is_5g ? 0x800000 :
++							     0x6e0000);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x6004, 0x190000, is_5g ? 0x0 : 0x190000);
++	if (is_10g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x01423342);
++	else if (is_5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00a132a1);
++	else if (is_2p5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x009c329c);
++	else
++		mtk_xfi_tphy_write(xfi_tphy, 0x00f8, 0x00fa32fa);
++
++	/* Force SGDT_OUT off and select PCS */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_F4,
++			 XFI_DPHY_AD_SGDT_FRC_EN | XFI_DPHY_PCS_SEL,
++			 XFI_DPHY_AD_SGDT_FRC_EN |
++			 (is_xgmii ? XFI_DPHY_PCS_SEL_USXGMII :
++				     XFI_DPHY_PCS_SEL_SGMII));
++
++
++	/* Force GLB_CKDET_OUT */
++	mtk_xfi_tphy_set(xfi_tphy, 0x0030, 0xc00);
++
++	/* Force AEQ on */
++	mtk_xfi_tphy_write(xfi_tphy, REG_DIG_GLB_70,
++			   XTP_PCS_RX_EQ_IN_PROGRESS(2) |
++			   XTP_PCS_PWD_SYNC(2) |
++			   XTP_PCS_PWD_ASYNC(2));
++
++	usleep_range(1, 5);
++
++	/* Setup TX DA default value */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x30b0, 0x30, 0x20);
++	mtk_xfi_tphy_write(xfi_tphy, 0x3028, 0x00008a01);
++	mtk_xfi_tphy_write(xfi_tphy, 0x302c, 0x0000a884);
++	mtk_xfi_tphy_write(xfi_tphy, 0x3024, 0x00083002);
++
++	/* Setup RG default value */
++	if (is_xgmii) {
++		mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00022220);
++		mtk_xfi_tphy_write(xfi_tphy, 0x5064, 0x0f020a01);
++		mtk_xfi_tphy_write(xfi_tphy, 0x50b4, 0x06100600);
++		if (interface == PHY_INTERFACE_MODE_USXGMII)
++			mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++		else
++			mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x47684100);
++	} else {
++		mtk_xfi_tphy_write(xfi_tphy, 0x3010, 0x00011110);
++		mtk_xfi_tphy_write(xfi_tphy, 0x3048, 0x40704000);
++	}
++
++	if (is_1g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x3064, 0x0000c000);
++
++	/* Setup RX EQ initial value */
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x3050, 0xa8000000,
++			 (interface != PHY_INTERFACE_MODE_10GBASER) ?
++			  0xa8000000 : 0x0);
++	mtk_xfi_tphy_rmw(xfi_tphy, 0x3054, 0xaa,
++			 (interface != PHY_INTERFACE_MODE_10GBASER) ?
++			  0xaa : 0x0);
++
++	if (is_xgmii)
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x00000f00);
++	else if (is_2p5g)
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x22000f00);
++	else
++		mtk_xfi_tphy_write(xfi_tphy, 0x306c, 0x20200f00);
++
++	if (interface == PHY_INTERFACE_MODE_10GBASER && xfi_tphy->da_war)
++		mtk_xfi_tphy_rmw(xfi_tphy, 0xa008, 0x10000, 0x10000);
++
++	mtk_xfi_tphy_rmw(xfi_tphy, 0xa060, 0x50000, is_xgmii ? 0x40000 :
++							       0x50000);
++
++	/* Setup PHYA speed */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_ANA_GLB_D0,
++			 XTP_GLB_USXGMII_SEL_MASK | XTP_GLB_USXGMII_EN,
++			 is_10g ?  XTP_GLB_USXGMII_SEL(0) :
++			 is_5g ?   XTP_GLB_USXGMII_SEL(1) :
++			 is_2p5g ? XTP_GLB_USXGMII_SEL(2) :
++				   XTP_GLB_USXGMII_SEL(3));
++	mtk_xfi_tphy_set(xfi_tphy, REG_ANA_GLB_D0, XTP_GLB_USXGMII_EN);
++
++	/* Release reset */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_GLB_70,
++			 XTP_PCS_RST_B | XTP_FRC_PCS_RST_B);
++	usleep_range(150, 500);
++
++	/* Switch to P0 */
++	mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++			 XTP_PCS_PWD_SYNC_MASK |
++			 XTP_PCS_PWD_ASYNC_MASK,
++			 XTP_FRC_PCS_PWD_ASYNC |
++			 XTP_PCS_UPDT | XTP_PCS_IN_FR_RG);
++	usleep_range(1, 5);
++
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++	usleep_range(15, 50);
++
++	if (is_xgmii) {
++		/* Switch to Gen3 */
++		mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++				 XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++				 XTP_PCS_MODE(2) | XTP_PCS_UPDT);
++	} else {
++		/* Switch to Gen2 */
++		mtk_xfi_tphy_rmw(xfi_tphy, REG_DIG_GLB_70,
++				 XTP_PCS_MODE_MASK | XTP_PCS_UPDT,
++				 XTP_PCS_MODE(1) | XTP_PCS_UPDT);
++	}
++	usleep_range(1, 5);
++
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_70, XTP_PCS_UPDT);
++
++	usleep_range(100, 500);
++
++	/* Enable MAC CK */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_B0, XTP_LN_TX_MACCK_EN);
++	mtk_xfi_tphy_clear(xfi_tphy, REG_DIG_GLB_F4, XFI_DPHY_AD_SGDT_FRC_EN);
++
++	/* Enable TX data */
++	mtk_xfi_tphy_set(xfi_tphy, REG_DIG_LN_TRX_40,
++			 XTP_LN_FRC_TX_DATA_EN | XTP_LN_TX_DATA_EN);
++	usleep_range(400, 1000);
++}
++
++static int mtk_xfi_tphy_set_mode(struct phy *phy, enum phy_mode mode, int
++				 submode)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	if (mode != PHY_MODE_ETHERNET)
++		return -EINVAL;
++
++	switch (submode) {
++	case PHY_INTERFACE_MODE_1000BASEX:
++	case PHY_INTERFACE_MODE_2500BASEX:
++	case PHY_INTERFACE_MODE_SGMII:
++	case PHY_INTERFACE_MODE_5GBASER:
++	case PHY_INTERFACE_MODE_10GBASER:
++	case PHY_INTERFACE_MODE_USXGMII:
++		mtk_xfi_tphy_setup(xfi_tphy, submode);
++		return 0;
++	default:
++		return -EINVAL;
++	}
++}
++
++static int mtk_xfi_tphy_reset(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	reset_control_assert(xfi_tphy->reset);
++	usleep_range(100, 500);
++	reset_control_deassert(xfi_tphy->reset);
++	usleep_range(1, 10);
++
++	return 0;
++}
++
++static int mtk_xfi_tphy_power_on(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	return clk_bulk_prepare_enable(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++}
++
++static int mtk_xfi_tphy_power_off(struct phy *phy)
++{
++	struct mtk_xfi_tphy *xfi_tphy = phy_get_drvdata(phy);
++
++	clk_bulk_disable_unprepare(MTK_XFI_TPHY_NUM_CLOCKS, xfi_tphy->clocks);
++
++	return 0;
++}
++
++static const struct phy_ops mtk_xfi_tphy_ops = {
++	.power_on	= mtk_xfi_tphy_power_on,
++	.power_off	= mtk_xfi_tphy_power_off,
++	.set_mode	= mtk_xfi_tphy_set_mode,
++	.reset		= mtk_xfi_tphy_reset,
++	.owner		= THIS_MODULE,
++};
++
++static int mtk_xfi_tphy_probe(struct platform_device *pdev)
++{
++	struct device_node *np = pdev->dev.of_node;
++	struct phy_provider *phy_provider;
++	struct mtk_xfi_tphy *xfi_tphy;
++	struct phy *phy;
++
++	if (!np)
++		return -ENODEV;
++
++	xfi_tphy = devm_kzalloc(&pdev->dev, sizeof(*xfi_tphy), GFP_KERNEL);
++	if (!xfi_tphy)
++		return -ENOMEM;
++
++	xfi_tphy->base = devm_of_iomap(&pdev->dev, np, 0, NULL);
++	if (!xfi_tphy->base)
++		return -EIO;
++
++	xfi_tphy->dev = &pdev->dev;
++
++	xfi_tphy->clocks[0].id = "topxtal";
++	xfi_tphy->clocks[0].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[0].id);
++	if (IS_ERR(xfi_tphy->clocks[0].clk))
++		return PTR_ERR(xfi_tphy->clocks[0].clk);
++
++	xfi_tphy->clocks[1].id = "xfipll";
++	xfi_tphy->clocks[1].clk = devm_clk_get(&pdev->dev, xfi_tphy->clocks[1].id);
++	if (IS_ERR(xfi_tphy->clocks[1].clk))
++		return PTR_ERR(xfi_tphy->clocks[1].clk);
++
++	xfi_tphy->reset = devm_reset_control_get_exclusive(&pdev->dev, NULL);
++	if (IS_ERR(xfi_tphy->reset))
++		return PTR_ERR(xfi_tphy->reset);
++
++	xfi_tphy->da_war = of_property_read_bool(np,
++						 "mediatek,usxgmii-performance-errata");
++
++	phy = devm_phy_create(&pdev->dev, NULL, &mtk_xfi_tphy_ops);
++	if (IS_ERR(phy))
++		return PTR_ERR(phy);
++
++	phy_set_drvdata(phy, xfi_tphy);
++
++	phy_provider = devm_of_phy_provider_register(&pdev->dev,
++						     of_phy_simple_xlate);
++
++	return PTR_ERR_OR_ZERO(phy_provider);
++}
++
++static const struct of_device_id mtk_xfi_tphy_match[] = {
++	{ .compatible = "mediatek,mt7988-xfi-tphy", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, mtk_xfi_tphy_match);
++
++static struct platform_driver mtk_xfi_tphy_driver = {
++	.probe = mtk_xfi_tphy_probe,
++	.driver = {
++		.name = "mtk-xfi-tphy",
++		.of_match_table = mtk_xfi_tphy_match,
++	},
++};
++module_platform_driver(mtk_xfi_tphy_driver);
++
++MODULE_DESCRIPTION("MediaTek XFI T-PHY driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_AUTHOR("Bc-bocun Chen <bc-bocun.chen@mediatek.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch b/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
new file mode 100644
index 00000000000..adb95e9587f
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-03-net-pcs-pcs-mtk-lynxi-add-platform-driver-for-MT7988.patch
@@ -0,0 +1,371 @@
+From 4b1a2716299c0e96a698044aebf3f80513509ae7 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:18 +0000
+Subject: [PATCH 3/5] net: pcs: pcs-mtk-lynxi: add platform driver for MT7988
+
+Introduce a proper platform MFD driver for the LynxI (H)SGMII PCS which
+is going to initially be used for the MT7988 SoC.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/pcs/pcs-mtk-lynxi.c   | 227 ++++++++++++++++++++++++++++--
+ include/linux/pcs/pcs-mtk-lynxi.h |  11 ++
+ 2 files changed, 227 insertions(+), 11 deletions(-)
+
+--- a/drivers/net/pcs/pcs-mtk-lynxi.c
++++ b/drivers/net/pcs/pcs-mtk-lynxi.c
+@@ -1,6 +1,6 @@
+ // SPDX-License-Identifier: GPL-2.0
+ // Copyright (c) 2018-2019 MediaTek Inc.
+-/* A library for MediaTek SGMII circuit
++/* A library and platform driver for the MediaTek LynxI SGMII circuit
+  *
+  * Author: Sean Wang <sean.wang@mediatek.com>
+  * Author: Alexander Couzens <lynxis@fe80.eu>
+@@ -8,11 +8,17 @@
+  *
+  */
+ 
++#include <linux/clk.h>
+ #include <linux/mdio.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mutex.h>
+ #include <linux/of.h>
++#include <linux/of_platform.h>
+ #include <linux/pcs/pcs-mtk-lynxi.h>
+ #include <linux/phylink.h>
++#include <linux/platform_device.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+ 
+ /* SGMII subsystem config registers */
+ /* BMCR (low 16) BMSR (high 16) */
+@@ -65,6 +71,8 @@
+ #define SGMII_PN_SWAP_MASK		GENMASK(1, 0)
+ #define SGMII_PN_SWAP_TX_RX		(BIT(0) | BIT(1))
+ 
++#define MTK_NETSYS_V3_AMA_RGC3		0x128
++
+ /* struct mtk_pcs_lynxi -  This structure holds each sgmii regmap andassociated
+  *                         data
+  * @regmap:                The register map pointing at the range used to setup
+@@ -74,15 +82,29 @@
+  * @interface:             Currently configured interface mode
+  * @pcs:                   Phylink PCS structure
+  * @flags:                 Flags indicating hardware properties
++ * @rstc:                  Reset controller
++ * @sgmii_sel:             SGMII Register Clock
++ * @sgmii_rx:              SGMII RX Clock
++ * @sgmii_tx:              SGMII TX Clock
++ * @node:                  List node
+  */
+ struct mtk_pcs_lynxi {
+ 	struct regmap		*regmap;
++	struct device		*dev;
+ 	u32			ana_rgc3;
+ 	phy_interface_t		interface;
+ 	struct			phylink_pcs pcs;
+ 	u32			flags;
++	struct reset_control	*rstc;
++	struct clk		*sgmii_sel;
++	struct clk		*sgmii_rx;
++	struct clk		*sgmii_tx;
++	struct list_head	node;
+ };
+ 
++static LIST_HEAD(mtk_pcs_lynxi_instances);
++static DEFINE_MUTEX(instance_mutex);
++
+ static struct mtk_pcs_lynxi *pcs_to_mtk_pcs_lynxi(struct phylink_pcs *pcs)
+ {
+ 	return container_of(pcs, struct mtk_pcs_lynxi, pcs);
+@@ -102,6 +124,17 @@ static void mtk_pcs_lynxi_get_state(stru
+ 					 FIELD_GET(SGMII_LPA, adv));
+ }
+ 
++static void mtk_sgmii_reset(struct mtk_pcs_lynxi *mpcs)
++{
++	if (!mpcs->rstc)
++		return;
++
++	reset_control_assert(mpcs->rstc);
++	udelay(100);
++	reset_control_deassert(mpcs->rstc);
++	mdelay(1);
++}
++
+ static int mtk_pcs_lynxi_config(struct phylink_pcs *pcs, unsigned int neg_mode,
+ 				phy_interface_t interface,
+ 				const unsigned long *advertising,
+@@ -148,6 +181,7 @@ static int mtk_pcs_lynxi_config(struct p
+ 				SGMII_PHYA_PWD);
+ 
+ 		/* Reset SGMII PCS state */
++		mtk_sgmii_reset(mpcs);
+ 		regmap_set_bits(mpcs->regmap, SGMSYS_RESERVED_0,
+ 				SGMII_SW_RESET);
+ 
+@@ -234,10 +268,29 @@ static void mtk_pcs_lynxi_link_up(struct
+ 	}
+ }
+ 
++static int mtk_pcs_lynxi_enable(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
++
++	if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++		clk_prepare_enable(mpcs->sgmii_rx);
++		clk_prepare_enable(mpcs->sgmii_tx);
++	}
++
++	return 0;
++}
++
+ static void mtk_pcs_lynxi_disable(struct phylink_pcs *pcs)
+ {
+ 	struct mtk_pcs_lynxi *mpcs = pcs_to_mtk_pcs_lynxi(pcs);
+ 
++	regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++	if (mpcs->sgmii_tx && mpcs->sgmii_rx) {
++		clk_disable_unprepare(mpcs->sgmii_tx);
++		clk_disable_unprepare(mpcs->sgmii_rx);
++	}
++
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ }
+ 
+@@ -247,11 +300,12 @@ static const struct phylink_pcs_ops mtk_
+ 	.pcs_an_restart = mtk_pcs_lynxi_restart_an,
+ 	.pcs_link_up = mtk_pcs_lynxi_link_up,
+ 	.pcs_disable = mtk_pcs_lynxi_disable,
++	.pcs_enable = mtk_pcs_lynxi_enable,
+ };
+ 
+-struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
+-					 struct regmap *regmap, u32 ana_rgc3,
+-					 u32 flags)
++static struct phylink_pcs *mtk_pcs_lynxi_init(struct device *dev, struct regmap *regmap,
++					      u32 ana_rgc3, u32 flags,
++					      struct mtk_pcs_lynxi *prealloc)
+ {
+ 	struct mtk_pcs_lynxi *mpcs;
+ 	u32 id, ver;
+@@ -259,29 +313,33 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 
+ 	ret = regmap_read(regmap, SGMSYS_PCS_DEVICE_ID, &id);
+ 	if (ret < 0)
+-		return NULL;
++		return ERR_PTR(ret);
+ 
+ 	if (id != SGMII_LYNXI_DEV_ID) {
+ 		dev_err(dev, "unknown PCS device id %08x\n", id);
+-		return NULL;
++		return ERR_PTR(-ENODEV);
+ 	}
+ 
+ 	ret = regmap_read(regmap, SGMSYS_PCS_SCRATCH, &ver);
+ 	if (ret < 0)
+-		return NULL;
++		return ERR_PTR(ret);
+ 
+ 	ver = FIELD_GET(SGMII_DEV_VERSION, ver);
+ 	if (ver != 0x1) {
+ 		dev_err(dev, "unknown PCS device version %04x\n", ver);
+-		return NULL;
++		return ERR_PTR(-ENODEV);
+ 	}
+ 
+ 	dev_dbg(dev, "MediaTek LynxI SGMII PCS (id 0x%08x, ver 0x%04x)\n", id,
+ 		ver);
+ 
+-	mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
+-	if (!mpcs)
+-		return NULL;
++	if (prealloc) {
++		mpcs = prealloc;
++	} else {
++		mpcs = kzalloc(sizeof(*mpcs), GFP_KERNEL);
++		if (!mpcs)
++			return ERR_PTR(-ENOMEM);
++	};
+ 
+ 	mpcs->ana_rgc3 = ana_rgc3;
+ 	mpcs->regmap = regmap;
+@@ -292,6 +350,13 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 	mpcs->interface = PHY_INTERFACE_MODE_NA;
+ 
+ 	return &mpcs->pcs;
++};
++
++struct phylink_pcs *mtk_pcs_lynxi_create(struct device *dev,
++					 struct regmap *regmap, u32 ana_rgc3,
++					 u32 flags)
++{
++	return mtk_pcs_lynxi_init(dev, regmap, ana_rgc3, flags, NULL);
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_create);
+ 
+@@ -304,4 +369,144 @@ void mtk_pcs_lynxi_destroy(struct phylin
+ }
+ EXPORT_SYMBOL(mtk_pcs_lynxi_destroy);
+ 
++static int mtk_pcs_lynxi_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct mtk_pcs_lynxi *mpcs;
++	struct phylink_pcs *pcs;
++	struct regmap *regmap;
++	u32 flags = 0;
++
++	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++	if (!mpcs)
++		return -ENOMEM;
++
++	mpcs->dev = dev;
++	regmap = syscon_node_to_regmap(np->parent);
++	if (IS_ERR(regmap))
++		return PTR_ERR(regmap);
++
++	if (of_property_read_bool(np->parent, "mediatek,pnswap"))
++		flags |= MTK_SGMII_FLAG_PN_SWAP;
++
++	mpcs->rstc = of_reset_control_get_shared(np->parent, NULL);
++	if (IS_ERR(mpcs->rstc))
++		return PTR_ERR(mpcs->rstc);
++
++	reset_control_deassert(mpcs->rstc);
++	mpcs->sgmii_sel = devm_clk_get_enabled(dev, "sgmii_sel");
++	if (IS_ERR(mpcs->sgmii_sel))
++		return PTR_ERR(mpcs->sgmii_sel);
++
++	mpcs->sgmii_rx = devm_clk_get(dev, "sgmii_rx");
++	if (IS_ERR(mpcs->sgmii_rx))
++		return PTR_ERR(mpcs->sgmii_rx);
++
++	mpcs->sgmii_tx = devm_clk_get(dev, "sgmii_tx");
++	if (IS_ERR(mpcs->sgmii_tx))
++		return PTR_ERR(mpcs->sgmii_tx);
++
++	pcs = mtk_pcs_lynxi_init(dev, regmap, (uintptr_t)of_device_get_match_data(dev),
++				 flags, mpcs);
++	if (IS_ERR(pcs))
++		return PTR_ERR(pcs);
++
++	regmap_set_bits(mpcs->regmap, SGMSYS_QPHY_PWR_STATE_CTRL, SGMII_PHYA_PWD);
++
++	platform_set_drvdata(pdev, mpcs);
++
++	mutex_lock(&instance_mutex);
++	list_add_tail(&mpcs->node, &mtk_pcs_lynxi_instances);
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static int mtk_pcs_lynxi_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_pcs_lynxi *cur, *tmp;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry_safe(cur, tmp, &mtk_pcs_lynxi_instances, node)
++		if (cur->dev == dev) {
++			list_del(&cur->node);
++			kfree(cur);
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_pcs_lynxi_of_match[] = {
++	{ .compatible = "mediatek,mt7988-sgmii", .data = (void *)MTK_NETSYS_V3_AMA_RGC3 },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_pcs_lynxi_of_match);
++
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct mtk_pcs_lynxi *mpcs;
++
++	if (!np)
++		return NULL;
++
++	if (!of_device_is_available(np))
++		return ERR_PTR(-ENODEV);
++
++	if (!of_match_node(mtk_pcs_lynxi_of_match, np))
++		return ERR_PTR(-EINVAL);
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev || !platform_get_drvdata(pdev)) {
++		if (pdev)
++			put_device(&pdev->dev);
++		return ERR_PTR(-EPROBE_DEFER);
++	}
++
++	mpcs = platform_get_drvdata(pdev);
++	device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++	return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_get);
++
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs)
++{
++	struct mtk_pcs_lynxi *cur, *mpcs = NULL;
++
++	if (!pcs)
++		return;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry(cur, &mtk_pcs_lynxi_instances, node)
++		if (pcs == &cur->pcs) {
++			mpcs = cur;
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	if (WARN_ON(!mpcs))
++		return;
++
++	put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_pcs_lynxi_put);
++
++static struct platform_driver mtk_pcs_lynxi_driver = {
++	.driver = {
++		.name			= "mtk-pcs-lynxi",
++		.suppress_bind_attrs	= true,
++		.of_match_table		= mtk_pcs_lynxi_of_match,
++	},
++	.probe = mtk_pcs_lynxi_probe,
++	.remove = mtk_pcs_lynxi_remove,
++};
++module_platform_driver(mtk_pcs_lynxi_driver);
++
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
++MODULE_DESCRIPTION("MediaTek LynxI HSGMII PCS");
+ MODULE_LICENSE("GPL");
+--- a/include/linux/pcs/pcs-mtk-lynxi.h
++++ b/include/linux/pcs/pcs-mtk-lynxi.h
+@@ -10,4 +10,15 @@ struct phylink_pcs *mtk_pcs_lynxi_create
+ 					 struct regmap *regmap,
+ 					 u32 ana_rgc3, u32 flags);
+ void mtk_pcs_lynxi_destroy(struct phylink_pcs *pcs);
++
++#if IS_ENABLED(CONFIG_PCS_MTK_LYNXI)
++struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np);
++void mtk_pcs_lynxi_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_pcs_lynxi_get(struct device *dev, struct device_node *np)
++{
++	return NULL;
++}
++static inline void mtk_pcs_lynxi_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_LYNXI) */
+ #endif
diff --git a/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch b/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
new file mode 100644
index 00000000000..215bd2ca2ef
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-04-dt-bindings-net-pcs-add-bindings-for-MediaTek-USXGMI.patch
@@ -0,0 +1,81 @@
+From 7d88d79c0f65b27a92754d7547f7af098b3de67b Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:31 +0000
+Subject: [PATCH 4/5] dt-bindings: net: pcs: add bindings for MediaTek USXGMII
+ PCS
+
+MediaTek's USXGMII can be found in the MT7988 SoC. We need to access
+it in order to configure and monitor the Ethernet SerDes link in
+USXGMII, 10GBase-R and 5GBase-R mode. By including a wrapped
+legacy 1000Base-X/2500Base-X/Cisco SGMII LynxI PCS as well, those
+interface modes are also available.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ .../bindings/net/pcs/mediatek,usxgmii.yaml    | 60 +++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/net/pcs/mediatek,usxgmii.yaml
+@@ -0,0 +1,60 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/net/pcs/mediatek,usxgmii.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: MediaTek USXGMII PCS
++
++maintainers:
++  - Daniel Golle <daniel@makrotopia.org>
++
++description:
++  The MediaTek USXGMII PCS provides physical link control and status
++  for USXGMII, 10GBase-R and 5GBase-R links on the SerDes interfaces
++  provided by the PEXTP PHY.
++  In order to also support legacy 2500Base-X, 1000Base-X and Cisco
++  SGMII an existing mediatek,*-sgmiisys LynxI PCS is wrapped to
++  provide those interfaces modes on the same SerDes interfaces shared
++  with the USXGMII PCS.
++
++properties:
++  $nodename:
++    pattern: "^pcs@[0-9a-f]+$"
++
++  compatible:
++    const: mediatek,mt7988-usxgmiisys
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: USXGMII top-level clock
++
++  resets:
++    items:
++      - description: XFI reset
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - resets
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/mediatek,mt7988-clk.h>
++    #define MT7988_TOPRGU_XFI0_GRST 12
++    soc {
++      #address-cells = <2>;
++      #size-cells = <2>;
++        usxgmiisys0: pcs@10080000 {
++          compatible = "mediatek,mt7988-usxgmiisys";
++          reg = <0 0x10080000 0 0x1000>;
++          clocks = <&topckgen CLK_TOP_USXGMII_SBUS_0_SEL>;
++          resets = <&watchdog MT7988_TOPRGU_XFI0_GRST>;
++        };
++    };
diff --git a/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch b/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
new file mode 100644
index 00000000000..5bd2850fec2
--- /dev/null
+++ b/target/linux/generic/pending-6.1/739-05-net-pcs-add-driver-for-MediaTek-USXGMII-PCS.patch
@@ -0,0 +1,547 @@
+From dde0e95fff92e9f5009f3bea75278e0e34a48822 Mon Sep 17 00:00:00 2001
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Tue, 12 Dec 2023 03:47:47 +0000
+Subject: [PATCH 5/5] net: pcs: add driver for MediaTek USXGMII PCS
+
+Add driver for USXGMII PCS found in the MediaTek MT7988 SoC and supporting
+USXGMII, 10GBase-R and 5GBase-R interface modes.
+
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ MAINTAINERS                         |   2 +
+ drivers/net/pcs/Kconfig             |  11 +
+ drivers/net/pcs/Makefile            |   1 +
+ drivers/net/pcs/pcs-mtk-usxgmii.c   | 456 ++++++++++++++++++++++++++++
+ include/linux/pcs/pcs-mtk-usxgmii.h |  27 ++
+ 5 files changed, 497 insertions(+)
+ create mode 100644 drivers/net/pcs/pcs-mtk-usxgmii.c
+ create mode 100644 include/linux/pcs/pcs-mtk-usxgmii.h
+
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -12934,7 +12934,9 @@ M:	Daniel Golle <daniel@makrotopia.org>
+ L:	netdev@vger.kernel.org
+ S:	Maintained
+ F:	drivers/net/pcs/pcs-mtk-lynxi.c
++F:	drivers/net/pcs/pcs-mtk-usxgmii.c
+ F:	include/linux/pcs/pcs-mtk-lynxi.h
++F:	include/linux/pcs/pcs-mtk-usxgmii.h
+ 
+ MEDIATEK I2C CONTROLLER DRIVER
+ M:	Qii Wang <qii.wang@mediatek.com>
+--- a/drivers/net/pcs/Kconfig
++++ b/drivers/net/pcs/Kconfig
+@@ -18,6 +18,17 @@ config PCS_LYNX
+ 	  This module provides helpers to phylink for managing the Lynx PCS
+ 	  which is part of the Layerscape and QorIQ Ethernet SERDES.
+ 
++config PCS_MTK_USXGMII
++	tristate "MediaTek USXGMII PCS"
++	select PCS_MTK_LYNXI
++	select PHY_MTK_PEXTP
++	select PHYLINK
++	help
++	  This module provides a driver for MediaTek's USXGMII PCS supporting
++	  10GBase-R, 5GBase-R and USXGMII interface modes.
++	  1000Base-X, 2500Base-X and Cisco SGMII are supported on the same
++	  differential pairs via an embedded LynxI PHY.
++
+ config PCS_RZN1_MIIC
+ 	tristate "Renesas RZ/N1 MII converter"
+ 	depends on OF && (ARCH_RZN1 || COMPILE_TEST)
+--- a/drivers/net/pcs/Makefile
++++ b/drivers/net/pcs/Makefile
+@@ -8,3 +8,4 @@ obj-$(CONFIG_PCS_LYNX)		+= pcs-lynx.o
+ obj-$(CONFIG_PCS_RZN1_MIIC)	+= pcs-rzn1-miic.o
+ obj-$(CONFIG_PCS_ALTERA_TSE)	+= pcs-altera-tse.o
+ obj-$(CONFIG_PCS_MTK_LYNXI)	+= pcs-mtk-lynxi.o
++obj-$(CONFIG_PCS_MTK_USXGMII)	+= pcs-mtk-usxgmii.o
+--- /dev/null
++++ b/drivers/net/pcs/pcs-mtk-usxgmii.c
+@@ -0,0 +1,456 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2023 MediaTek Inc.
++ * Author: Henry Yen <henry.yen@mediatek.com>
++ *         Daniel Golle <daniel@makrotopia.org>
++ */
++
++#include <linux/clk.h>
++#include <linux/io.h>
++#include <linux/mfd/syscon.h>
++#include <linux/mdio.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_platform.h>
++#include <linux/reset.h>
++#include <linux/pcs/pcs-mtk-usxgmii.h>
++#include <linux/platform_device.h>
++
++/* USXGMII subsystem config registers */
++/* Register to control speed */
++#define RG_PHY_TOP_SPEED_CTRL1			0x80c
++#define USXGMII_RATE_UPDATE_MODE		BIT(31)
++#define USXGMII_MAC_CK_GATED			BIT(29)
++#define USXGMII_IF_FORCE_EN			BIT(28)
++#define USXGMII_RATE_ADAPT_MODE			GENMASK(10, 8)
++#define USXGMII_RATE_ADAPT_MODE_X1		0
++#define USXGMII_RATE_ADAPT_MODE_X2		1
++#define USXGMII_RATE_ADAPT_MODE_X4		2
++#define USXGMII_RATE_ADAPT_MODE_X10		3
++#define USXGMII_RATE_ADAPT_MODE_X100		4
++#define USXGMII_RATE_ADAPT_MODE_X5		5
++#define USXGMII_RATE_ADAPT_MODE_X50		6
++#define USXGMII_XFI_RX_MODE			GENMASK(6, 4)
++#define USXGMII_XFI_TX_MODE			GENMASK(2, 0)
++#define USXGMII_XFI_MODE_10G			0
++#define USXGMII_XFI_MODE_5G			1
++#define USXGMII_XFI_MODE_2P5G			3
++
++/* Register to control PCS AN */
++#define RG_PCS_AN_CTRL0				0x810
++#define USXGMII_AN_RESTART			BIT(31)
++#define USXGMII_AN_SYNC_CNT			GENMASK(30, 11)
++#define USXGMII_AN_ENABLE			BIT(0)
++
++#define RG_PCS_AN_CTRL2				0x818
++#define USXGMII_LINK_TIMER_IDLE_DETECT		GENMASK(29, 20)
++#define USXGMII_LINK_TIMER_COMP_ACK_DETECT	GENMASK(19, 10)
++#define USXGMII_LINK_TIMER_AN_RESTART		GENMASK(9, 0)
++
++/* Register to read PCS AN status */
++#define RG_PCS_AN_STS0				0x81c
++#define USXGMII_LPA				GENMASK(15, 0)
++#define USXGMII_LPA_LATCH			BIT(31)
++
++/* Register to read PCS link status */
++#define RG_PCS_RX_STATUS0			0x904
++#define RG_PCS_RX_STATUS_UPDATE			BIT(16)
++#define RG_PCS_RX_LINK_STATUS			BIT(2)
++
++/* struct mtk_usxgmii_pcs - This structure holds each usxgmii PCS
++ * @pcs:		Phylink PCS structure
++ * @dev:		Pointer to device structure
++ * @base:		IO memory to access PCS hardware
++ * @clk:		Pointer to USXGMII clk
++ * @reset:		Pointer to USXGMII reset control
++ * @interface:		Currently selected interface mode
++ * @neg_mode:		Currently used phylink neg_mode
++ * @node:		List node
++ */
++struct mtk_usxgmii_pcs {
++	struct phylink_pcs		pcs;
++	struct device			*dev;
++	void __iomem			*base;
++	struct clk			*clk;
++	struct reset_control		*reset;
++	phy_interface_t			interface;
++	unsigned int			neg_mode;
++	struct list_head		node;
++};
++
++static LIST_HEAD(mtk_usxgmii_pcs_instances);
++static DEFINE_MUTEX(instance_mutex);
++
++static u32 mtk_r32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg)
++{
++	return ioread32(mpcs->base + reg);
++}
++
++static void mtk_m32(struct mtk_usxgmii_pcs *mpcs, unsigned int reg, u32 mask, u32 set)
++{
++	u32 val;
++
++	val = ioread32(mpcs->base + reg);
++	val &= ~mask;
++	val |= set;
++	iowrite32(val, mpcs->base + reg);
++}
++
++static struct mtk_usxgmii_pcs *pcs_to_mtk_usxgmii_pcs(struct phylink_pcs *pcs)
++{
++	return container_of(pcs, struct mtk_usxgmii_pcs, pcs);
++}
++
++static void mtk_usxgmii_reset(struct mtk_usxgmii_pcs *mpcs)
++{
++	reset_control_assert(mpcs->reset);
++	udelay(100);
++	reset_control_deassert(mpcs->reset);
++
++	mdelay(10);
++}
++
++static int mtk_usxgmii_pcs_config(struct phylink_pcs *pcs, unsigned int neg_mode,
++				  phy_interface_t interface,
++				  const unsigned long *advertising,
++				  bool permit_pause_to_mac)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++	unsigned int an_ctrl = 0, link_timer = 0, xfi_mode = 0, adapt_mode = 0;
++	bool mode_changed = false;
++
++	if (interface == PHY_INTERFACE_MODE_USXGMII) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF) | USXGMII_AN_ENABLE;
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++	} else if (interface == PHY_INTERFACE_MODE_10GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0x1FF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x7B) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x7B);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_10G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_10G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else if (interface == PHY_INTERFACE_MODE_5GBASER) {
++		an_ctrl = FIELD_PREP(USXGMII_AN_SYNC_CNT, 0xFF);
++		link_timer = FIELD_PREP(USXGMII_LINK_TIMER_IDLE_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_COMP_ACK_DETECT, 0x3D) |
++			     FIELD_PREP(USXGMII_LINK_TIMER_AN_RESTART, 0x3D);
++		xfi_mode = FIELD_PREP(USXGMII_XFI_RX_MODE, USXGMII_XFI_MODE_5G) |
++			   FIELD_PREP(USXGMII_XFI_TX_MODE, USXGMII_XFI_MODE_5G);
++		adapt_mode = USXGMII_RATE_UPDATE_MODE;
++	} else {
++		return -EINVAL;
++	}
++
++	adapt_mode |= FIELD_PREP(USXGMII_RATE_ADAPT_MODE, USXGMII_RATE_ADAPT_MODE_X1);
++
++	if (mpcs->interface != interface) {
++		mpcs->interface = interface;
++		mode_changed = true;
++	}
++
++	mtk_usxgmii_reset(mpcs);
++
++	/* Setup USXGMII AN ctrl */
++	mtk_m32(mpcs, RG_PCS_AN_CTRL0,
++		USXGMII_AN_SYNC_CNT | USXGMII_AN_ENABLE,
++		an_ctrl);
++
++	mtk_m32(mpcs, RG_PCS_AN_CTRL2,
++		USXGMII_LINK_TIMER_IDLE_DETECT |
++		USXGMII_LINK_TIMER_COMP_ACK_DETECT |
++		USXGMII_LINK_TIMER_AN_RESTART,
++		link_timer);
++
++	mpcs->neg_mode = neg_mode;
++
++	/* Gated MAC CK */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_MAC_CK_GATED, USXGMII_MAC_CK_GATED);
++
++	/* Enable interface force mode */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_IF_FORCE_EN, USXGMII_IF_FORCE_EN);
++
++	/* Setup USXGMII adapt mode */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_RATE_UPDATE_MODE | USXGMII_RATE_ADAPT_MODE,
++		adapt_mode);
++
++	/* Setup USXGMII speed */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1,
++		USXGMII_XFI_RX_MODE | USXGMII_XFI_TX_MODE,
++		xfi_mode);
++
++	usleep_range(1, 10);
++
++	/* Un-gated MAC CK */
++	mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_MAC_CK_GATED, 0);
++
++	usleep_range(1, 10);
++
++	/* Disable interface force mode for the AN mode */
++	if (an_ctrl & USXGMII_AN_ENABLE)
++		mtk_m32(mpcs, RG_PHY_TOP_SPEED_CTRL1, USXGMII_IF_FORCE_EN, 0);
++
++	return mode_changed;
++}
++
++static void mtk_usxgmii_pcs_get_fixed_speed(struct mtk_usxgmii_pcs *mpcs,
++					    struct phylink_link_state *state)
++{
++	u32 val = mtk_r32(mpcs, RG_PHY_TOP_SPEED_CTRL1);
++	int speed;
++
++	/* Calculate speed from interface speed and rate adapt mode */
++	switch (FIELD_GET(USXGMII_XFI_RX_MODE, val)) {
++	case USXGMII_XFI_MODE_10G:
++		speed = 10000;
++		break;
++	case USXGMII_XFI_MODE_5G:
++		speed = 5000;
++		break;
++	case USXGMII_XFI_MODE_2P5G:
++		speed = 2500;
++		break;
++	default:
++		state->speed = SPEED_UNKNOWN;
++		return;
++	}
++
++	switch (FIELD_GET(USXGMII_RATE_ADAPT_MODE, val)) {
++	case USXGMII_RATE_ADAPT_MODE_X100:
++		speed /= 100;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X50:
++		speed /= 50;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X10:
++		speed /= 10;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X5:
++		speed /= 5;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X4:
++		speed /= 4;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X2:
++		speed /= 2;
++		break;
++	case USXGMII_RATE_ADAPT_MODE_X1:
++		break;
++	default:
++		state->speed = SPEED_UNKNOWN;
++		return;
++	}
++
++	state->speed = speed;
++	state->duplex = DUPLEX_FULL;
++}
++
++static void mtk_usxgmii_pcs_get_an_state(struct mtk_usxgmii_pcs *mpcs,
++					 struct phylink_link_state *state)
++{
++	u16 lpa;
++
++	/* Refresh LPA by toggling LPA_LATCH */
++	mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, USXGMII_LPA_LATCH);
++	ndelay(1020);
++	mtk_m32(mpcs, RG_PCS_AN_STS0, USXGMII_LPA_LATCH, 0);
++	ndelay(1020);
++	lpa = FIELD_GET(USXGMII_LPA, mtk_r32(mpcs, RG_PCS_AN_STS0));
++
++	phylink_decode_usxgmii_word(state, lpa);
++}
++
++static void mtk_usxgmii_pcs_get_state(struct phylink_pcs *pcs,
++				      struct phylink_link_state *state)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	/* Refresh USXGMII link status by toggling RG_PCS_AN_STATUS_UPDATE */
++	mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE,
++		RG_PCS_RX_STATUS_UPDATE);
++	ndelay(1020);
++	mtk_m32(mpcs, RG_PCS_RX_STATUS0, RG_PCS_RX_STATUS_UPDATE, 0);
++	ndelay(1020);
++
++	/* Read USXGMII link status */
++	state->link = FIELD_GET(RG_PCS_RX_LINK_STATUS,
++				mtk_r32(mpcs, RG_PCS_RX_STATUS0));
++
++	/* Continuously repeat re-configuration sequence until link comes up */
++	if (!state->link) {
++		mtk_usxgmii_pcs_config(pcs, mpcs->neg_mode,
++				       state->interface, NULL, false);
++		return;
++	}
++
++	if (FIELD_GET(USXGMII_AN_ENABLE, mtk_r32(mpcs, RG_PCS_AN_CTRL0)))
++		mtk_usxgmii_pcs_get_an_state(mpcs, state);
++	else
++		mtk_usxgmii_pcs_get_fixed_speed(mpcs, state);
++}
++
++static void mtk_usxgmii_pcs_restart_an(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	mtk_m32(mpcs, RG_PCS_AN_CTRL0, USXGMII_AN_RESTART, USXGMII_AN_RESTART);
++}
++
++static void mtk_usxgmii_pcs_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
++				    phy_interface_t interface,
++				    int speed, int duplex)
++{
++	/* Reconfiguring USXGMII to ensure the quality of the RX signal
++	 * after the line side link up.
++	 */
++	mtk_usxgmii_pcs_config(pcs, neg_mode, interface, NULL, false);
++}
++
++static void mtk_usxgmii_pcs_disable(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *mpcs = pcs_to_mtk_usxgmii_pcs(pcs);
++
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++	mpcs->neg_mode = -1;
++}
++
++static const struct phylink_pcs_ops mtk_usxgmii_pcs_ops = {
++	.pcs_config = mtk_usxgmii_pcs_config,
++	.pcs_get_state = mtk_usxgmii_pcs_get_state,
++	.pcs_an_restart = mtk_usxgmii_pcs_restart_an,
++	.pcs_link_up = mtk_usxgmii_pcs_link_up,
++	.pcs_disable = mtk_usxgmii_pcs_disable,
++};
++
++static int mtk_usxgmii_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_usxgmii_pcs *mpcs;
++
++	mpcs = devm_kzalloc(dev, sizeof(*mpcs), GFP_KERNEL);
++	if (!mpcs)
++		return -ENOMEM;
++
++	mpcs->base = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(mpcs->base))
++		return PTR_ERR(mpcs->base);
++
++	mpcs->dev = dev;
++	mpcs->pcs.ops = &mtk_usxgmii_pcs_ops;
++	mpcs->pcs.poll = true;
++	mpcs->pcs.neg_mode = true;
++	mpcs->interface = PHY_INTERFACE_MODE_NA;
++	mpcs->neg_mode = -1;
++
++	mpcs->clk = devm_clk_get_enabled(mpcs->dev, NULL);
++	if (IS_ERR(mpcs->clk))
++		return PTR_ERR(mpcs->clk);
++
++	mpcs->reset = devm_reset_control_get_shared(dev, NULL);
++	if (IS_ERR(mpcs->reset))
++		return PTR_ERR(mpcs->reset);
++
++	reset_control_deassert(mpcs->reset);
++
++	platform_set_drvdata(pdev, mpcs);
++
++	mutex_lock(&instance_mutex);
++	list_add_tail(&mpcs->node, &mtk_usxgmii_pcs_instances);
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static int mtk_usxgmii_remove(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct mtk_usxgmii_pcs *cur, *tmp;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry_safe(cur, tmp, &mtk_usxgmii_pcs_instances, node)
++		if (cur->dev == dev) {
++			list_del(&cur->node);
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	return 0;
++}
++
++static const struct of_device_id mtk_usxgmii_of_mtable[] = {
++	{ .compatible = "mediatek,mt7988-usxgmiisys" },
++	{ /* sentinel */ },
++};
++MODULE_DEVICE_TABLE(of, mtk_usxgmii_of_mtable);
++
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++	struct platform_device *pdev;
++	struct mtk_usxgmii_pcs *mpcs;
++
++	if (!np)
++		return NULL;
++
++	if (!of_device_is_available(np))
++		return ERR_PTR(-ENODEV);
++
++	if (!of_match_node(mtk_usxgmii_of_mtable, np))
++		return ERR_PTR(-EINVAL);
++
++	pdev = of_find_device_by_node(np);
++	if (!pdev || !platform_get_drvdata(pdev)) {
++		if (pdev)
++			put_device(&pdev->dev);
++		return ERR_PTR(-EPROBE_DEFER);
++	}
++
++	mpcs = platform_get_drvdata(pdev);
++	device_link_add(dev, mpcs->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
++
++	return &mpcs->pcs;
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_get);
++
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs)
++{
++	struct mtk_usxgmii_pcs *cur, *mpcs = NULL;
++
++	if (!pcs)
++		return;
++
++	mutex_lock(&instance_mutex);
++	list_for_each_entry(cur, &mtk_usxgmii_pcs_instances, node)
++		if (pcs == &cur->pcs) {
++			mpcs = cur;
++			break;
++		}
++	mutex_unlock(&instance_mutex);
++
++	if (WARN_ON(!mpcs))
++		return;
++
++	put_device(mpcs->dev);
++}
++EXPORT_SYMBOL(mtk_usxgmii_pcs_put);
++
++static struct platform_driver mtk_usxgmii_driver = {
++	.driver = {
++		.name			= "mtk_usxgmii",
++		.suppress_bind_attrs	= true,
++		.of_match_table		= mtk_usxgmii_of_mtable,
++	},
++	.probe = mtk_usxgmii_probe,
++	.remove = mtk_usxgmii_remove,
++};
++module_platform_driver(mtk_usxgmii_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_DESCRIPTION("MediaTek USXGMII PCS driver");
++MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
+--- /dev/null
++++ b/include/linux/pcs/pcs-mtk-usxgmii.h
+@@ -0,0 +1,27 @@
++/* SPDX-License-Identifier: GPL-2.0 */
++#ifndef __LINUX_PCS_MTK_USXGMII_H
++#define __LINUX_PCS_MTK_USXGMII_H
++
++#include <linux/phylink.h>
++
++/**
++ * mtk_usxgmii_select_pcs() - Get MediaTek PCS instance
++ * @np:		Pointer to device node indentifying a MediaTek USXGMII PCS
++ * @mode:	Ethernet PHY interface mode
++ *
++ * Return PCS identified by a device node and the PHY interface mode in use
++ *
++ * Return:	Pointer to phylink PCS instance of NULL
++ */
++#if IS_ENABLED(CONFIG_PCS_MTK_USXGMII)
++struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np);
++void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs);
++#else
++static inline struct phylink_pcs *mtk_usxgmii_pcs_get(struct device *dev, struct device_node *np)
++{
++	return NULL;
++}
++static inline void mtk_usxgmii_pcs_put(struct phylink_pcs *pcs) { }
++#endif /* IS_ENABLED(CONFIG_PCS_MTK_USXGMII) */
++
++#endif /* __LINUX_PCS_MTK_USXGMII_H */
diff --git a/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
new file mode 100644
index 00000000000..1dfa1366ebf
--- /dev/null
+++ b/target/linux/generic/pending-6.1/750-net-phy-airoha-Add-the-Airoha-EN8811H-PHY-driver.patch
@@ -0,0 +1,1115 @@
+From patchwork Tue Feb  6 19:47:51 2024
+Content-Type: text/plain; charset="utf-8"
+MIME-Version: 1.0
+Content-Transfer-Encoding: 7bit
+X-Patchwork-Submitter: Eric Woudstra <ericwouds@gmail.com>
+X-Patchwork-Id: 13547762
+X-Patchwork-Delegate: kuba@kernel.org
+From: Eric Woudstra <ericwouds@gmail.com>
+To: "David S. Miller" <davem@davemloft.net>,
+	Eric Dumazet <edumazet@google.com>,
+	Jakub Kicinski <kuba@kernel.org>,
+	Paolo Abeni <pabeni@redhat.com>,
+	Rob Herring <robh+dt@kernel.org>,
+	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
+	Conor Dooley <conor+dt@kernel.org>,
+	Andrew Lunn <andrew@lunn.ch>,
+	Heiner Kallweit <hkallweit1@gmail.com>,
+	Russell King <linux@armlinux.org.uk>,
+	Matthias Brugger <matthias.bgg@gmail.com>,
+	AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+	"Frank Wunderlich" <frank-w@public-files.de>,
+	Daniel Golle <daniel@makrotopia.org>,
+	Lucien Jheng  <lucien.jheng@airoha.com>,
+	Zhi-Jun You <hujy652@protonmail.com>
+Cc: netdev@vger.kernel.org,
+	devicetree@vger.kernel.org,
+	Eric Woudstra <ericwouds@gmail.com>
+Subject: [PATCH net-next 2/2] net: phy: air_en8811h: Add the Airoha EN8811H
+ PHY driver
+Date: Tue,  6 Feb 2024 20:47:51 +0100
+Message-ID: <20240206194751.1901802-3-ericwouds@gmail.com>
+X-Mailer: git-send-email 2.42.1
+In-Reply-To: <20240206194751.1901802-1-ericwouds@gmail.com>
+References: <20240206194751.1901802-1-ericwouds@gmail.com>
+Precedence: bulk
+X-Mailing-List: netdev@vger.kernel.org
+List-Id: <netdev.vger.kernel.org>
+List-Subscribe: <mailto:netdev+subscribe@vger.kernel.org>
+List-Unsubscribe: <mailto:netdev+unsubscribe@vger.kernel.org>
+MIME-Version: 1.0
+X-Patchwork-Delegate: kuba@kernel.org
+
+* Source originated from airoha's en8811h v1.2.1 driver
+ * Moved air_en8811h.h to air_en8811h.c
+ * Removed air_pbus_reg_write() as it writes to another device on mdio-bus
+ * Load firmware from /lib/firmware/airoha/ instead of /lib/firmware/
+ * Added .get_rate_matching()
+ * Use generic phy_read/write() and phy_read/write_mmd()
+ * Edited .get_features() to use generic C45 functions
+ * Edited .config_aneg() and .read_status() to use a mix of generic C22/C45
+ * Use led handling functions from mediatek-ge-soc.c
+ * Simplified led handling by storing led rules
+ * Cleanup macro definitions
+ * Cleanup code to pass checkpatch.pl
+ * General code cleanup
+
+Changes from original RFC patch:
+
+ * Use the correct order in Kconfig and Makefile
+ * Change some register naming to correspond with datasheet
+ * Use phy_driver .read_page() and .write_page()
+ * Use module_phy_driver()
+ * Use get_unaligned_le16() instead of macro
+ * In .config_aneg() and .read_status() use genphy_xxx() C22
+ * Use another vendor register to read real speed
+ * Load firmware only once and store firmware version
+ * Apply 2.5G LPA work-around (firmware before 24011202)
+ * Read 2.5G LPA from vendor register (firmware 24011202 and later)
+
+Changes to be committed:
+	modified:   drivers/net/phy/Kconfig
+	modified:   drivers/net/phy/Makefile
+	new file:   drivers/net/phy/air_en8811h.c
+
+Signed-off-by: Eric Woudstra <ericwouds@gmail.com>
+---
+ drivers/net/phy/Kconfig       |    5 +
+ drivers/net/phy/Makefile      |    1 +
+ drivers/net/phy/air_en8811h.c | 1006 +++++++++++++++++++++++++++++++++
+ 3 files changed, 1012 insertions(+)
+ create mode 100644 drivers/net/phy/air_en8811h.c
+
+--- a/drivers/net/phy/Kconfig
++++ b/drivers/net/phy/Kconfig
+@@ -69,6 +69,11 @@ config SFP
+ 
+ comment "MII PHY device drivers"
+ 
++config AIR_EN8811H_PHY
++	tristate "Airoha EN8811H 2.5 Gigabit PHY"
++	help
++	  Currently supports the Airoha EN8811H PHY.
++
+ config AMD_PHY
+ 	tristate "AMD and Altima PHYs"
+ 	help
+--- a/drivers/net/phy/Makefile
++++ b/drivers/net/phy/Makefile
+@@ -32,6 +32,7 @@ obj-y				+= $(sfp-obj-y) $(sfp-obj-m)
+ 
+ obj-$(CONFIG_ADIN_PHY)		+= adin.o
+ obj-$(CONFIG_ADIN1100_PHY)	+= adin1100.o
++obj-$(CONFIG_AIR_EN8811H_PHY)   += air_en8811h.o
+ obj-$(CONFIG_AMD_PHY)		+= amd.o
+ obj-$(CONFIG_AQUANTIA_PHY)	+= aquantia/
+ obj-$(CONFIG_AX88796B_PHY)	+= ax88796b.o
+--- /dev/null
++++ b/drivers/net/phy/air_en8811h.c
+@@ -0,0 +1,1006 @@
++// SPDX-License-Identifier: GPL-2.0+
++/*
++ * Driver for Airoha Ethernet PHYs
++ *
++ * Currently supporting the EN8811H.
++ *
++ * Limitations of the EN8811H:
++ * - Only full duplex supported
++ * - Forced speed (AN off) is not supported by hardware (100Mbps)
++ *
++ * Source originated from airoha's en8811h.c and en8811h.h v1.2.1
++ *
++ * Copyright (C) 2023 Airoha Technology Corp.
++ */
++
++#include <linux/phy.h>
++#include <linux/firmware.h>
++#include <linux/property.h>
++#include <asm/unaligned.h>
++
++#define EN8811H_PHY_ID		0x03a2a411
++
++#define EN8811H_MD32_DM		"airoha/EthMD32.dm.bin"
++#define EN8811H_MD32_DSP	"airoha/EthMD32.DSP.bin"
++
++#define AIR_FW_ADDR_DM	0x00000000
++#define AIR_FW_ADDR_DSP	0x00100000
++
++/* u32 (DWORD) component macros */
++#define LOWORD(d) ((u16)(u32)(d))
++#define HIWORD(d) ((u16)(((u32)(d)) >> 16))
++
++/* MII Registers */
++#define AIR_AUX_CTRL_STATUS	0x1d
++#define   AIR_AUX_CTRL_STATUS_SPEED_MASK	GENMASK(4, 2)
++#define   AIR_AUX_CTRL_STATUS_SPEED_100		0x4
++#define   AIR_AUX_CTRL_STATUS_SPEED_1000	0x8
++#define   AIR_AUX_CTRL_STATUS_SPEED_2500	0xc
++
++#define AIR_EXT_PAGE_ACCESS		0x1f
++#define   AIR_PHY_PAGE_STANDARD			0x0000
++#define   AIR_PHY_PAGE_EXTENDED_4		0x0004
++
++/* MII Registers Page 4*/
++#define AIR_PBUS_MODE			0x10
++#define   AIR_PBUS_MODE_ADDR_FIXED		0x0000
++#define   AIR_PBUS_MODE_ADDR_INCR		BIT(15)
++#define AIR_PBUS_WR_ADDR_HIGH		0x11
++#define AIR_PBUS_WR_ADDR_LOW		0x12
++#define AIR_PBUS_WR_DATA_HIGH		0x13
++#define AIR_PBUS_WR_DATA_LOW		0x14
++#define AIR_PBUS_RD_ADDR_HIGH		0x15
++#define AIR_PBUS_RD_ADDR_LOW		0x16
++#define AIR_PBUS_RD_DATA_HIGH		0x17
++#define AIR_PBUS_RD_DATA_LOW		0x18
++
++/* Registers on MDIO_MMD_VEND1 */
++#define EN8811H_PHY_FW_STATUS		0x8009
++#define   EN8811H_PHY_READY			0x02
++
++#define AIR_PHY_HOST_CMD_1		0x800c
++#define AIR_PHY_HOST_CMD_1_MODE1		0x0
++#define AIR_PHY_HOST_CMD_2		0x800d
++#define AIR_PHY_HOST_CMD_2_MODE1		0x0
++#define AIR_PHY_HOST_CMD_3		0x800e
++#define AIR_PHY_HOST_CMD_3_MODE1		0x1101
++#define AIR_PHY_HOST_CMD_3_DOCMD		0x1100
++#define AIR_PHY_HOST_CMD_4		0x800f
++#define AIR_PHY_HOST_CMD_4_MODE1		0x0002
++#define AIR_PHY_HOST_CMD_4_INTCLR		0x00e4
++
++/* Registers on MDIO_MMD_VEND2 */
++#define AIR_PHY_LED_BCR			0x021
++#define   AIR_PHY_LED_BCR_MODE_MASK		GENMASK(1, 0)
++#define   AIR_PHY_LED_BCR_TIME_TEST		BIT(2)
++#define   AIR_PHY_LED_BCR_CLK_EN		BIT(3)
++#define   AIR_PHY_LED_BCR_EXT_CTRL		BIT(15)
++
++#define AIR_PHY_LED_DUR_ON		0x022
++
++#define AIR_PHY_LED_DUR_BLINK		0x023
++
++#define AIR_PHY_LED_ON(i)	       (0x024 + ((i) * 2))
++#define   AIR_PHY_LED_ON_MASK			(GENMASK(6, 0) | BIT(8))
++#define   AIR_PHY_LED_ON_LINK1000		BIT(0)
++#define   AIR_PHY_LED_ON_LINK100		BIT(1)
++#define   AIR_PHY_LED_ON_LINK10			BIT(2)
++#define   AIR_PHY_LED_ON_LINKDOWN		BIT(3)
++#define   AIR_PHY_LED_ON_FDX			BIT(4) /* Full duplex */
++#define   AIR_PHY_LED_ON_HDX			BIT(5) /* Half duplex */
++#define   AIR_PHY_LED_ON_FORCE_ON		BIT(6)
++#define   AIR_PHY_LED_ON_LINK2500		BIT(8)
++#define   AIR_PHY_LED_ON_POLARITY		BIT(14)
++#define   AIR_PHY_LED_ON_ENABLE			BIT(15)
++
++#define AIR_PHY_LED_BLINK(i)	       (0x025 + ((i) * 2))
++#define   AIR_PHY_LED_BLINK_1000TX		BIT(0)
++#define   AIR_PHY_LED_BLINK_1000RX		BIT(1)
++#define   AIR_PHY_LED_BLINK_100TX		BIT(2)
++#define   AIR_PHY_LED_BLINK_100RX		BIT(3)
++#define   AIR_PHY_LED_BLINK_10TX		BIT(4)
++#define   AIR_PHY_LED_BLINK_10RX		BIT(5)
++#define   AIR_PHY_LED_BLINK_COLLISION		BIT(6)
++#define   AIR_PHY_LED_BLINK_RX_CRC_ERR		BIT(7)
++#define   AIR_PHY_LED_BLINK_RX_IDLE_ERR		BIT(8)
++#define   AIR_PHY_LED_BLINK_FORCE_BLINK		BIT(9)
++#define   AIR_PHY_LED_BLINK_2500TX		BIT(10)
++#define   AIR_PHY_LED_BLINK_2500RX		BIT(11)
++
++/* Registers on BUCKPBUS */
++#define EN8811H_2P5G_LPA		0x3b30
++#define   EN8811H_2P5G_LPA_2P5G			BIT(0)
++
++#define EN8811H_FW_VERSION		0x3b3c
++
++#define EN8811H_POLARITY		0xca0f8
++#define   EN8811H_POLARITY_TX_NORMAL		BIT(0)
++#define   EN8811H_POLARITY_RX_REVERSE		BIT(1)
++
++#define EN8811H_GPIO_OUTPUT		0xcf8b8
++#define   EN8811H_GPIO_OUTPUT_345		(BIT(3) | BIT(4) | BIT(5))
++
++#define EN8811H_FW_CTRL_1		0x0f0018
++#define   EN8811H_FW_CTRL_1_START		0x0
++#define   EN8811H_FW_CTRL_1_FINISH		0x1
++#define EN8811H_FW_CTRL_2		0x800000
++#define EN8811H_FW_CTRL_2_LOADING		BIT(11)
++
++#define EN8811H_LED_COUNT	3
++
++/* GPIO5  <-> BASE_T_LED0
++ * GPIO4  <-> BASE_T_LED1
++ * GPIO3  <-> BASE_T_LED2
++ *
++ * Default setup suitable for 2 leds connected:
++ *    100M link up triggers led0, only led0 blinking on traffic
++ *   1000M link up triggers led1, only led1 blinking on traffic
++ *   2500M link up triggers led0 and led1, both blinking on traffic
++ * Also suitable for 1 led connected:
++ *     any link up triggers led2
++ */
++#define AIR_DEFAULT_TRIGGER_LED0 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_100)  | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED1 (BIT(TRIGGER_NETDEV_LINK_2500) | \
++				  BIT(TRIGGER_NETDEV_LINK_1000) | \
++				  BIT(TRIGGER_NETDEV_RX)        | \
++				  BIT(TRIGGER_NETDEV_TX))
++#define AIR_DEFAULT_TRIGGER_LED2  BIT(TRIGGER_NETDEV_LINK)
++
++struct led {
++	unsigned long rules;
++	unsigned long state;
++};
++
++struct en8811h_priv {
++	u32		firmware_version;
++	struct led	led[EN8811H_LED_COUNT];
++};
++
++enum {
++	AIR_PHY_LED_STATE_FORCE_ON,
++	AIR_PHY_LED_STATE_FORCE_BLINK,
++};
++
++enum {
++	AIR_PHY_LED_DUR_BLINK_32M,
++	AIR_PHY_LED_DUR_BLINK_64M,
++	AIR_PHY_LED_DUR_BLINK_128M,
++	AIR_PHY_LED_DUR_BLINK_256M,
++	AIR_PHY_LED_DUR_BLINK_512M,
++	AIR_PHY_LED_DUR_BLINK_1024M,
++};
++
++enum {
++	AIR_LED_DISABLE,
++	AIR_LED_ENABLE,
++};
++
++enum {
++	AIR_ACTIVE_LOW,
++	AIR_ACTIVE_HIGH,
++};
++
++enum {
++	AIR_LED_MODE_DISABLE,
++	AIR_LED_MODE_USER_DEFINE,
++};
++
++#define AIR_PHY_LED_DUR_UNIT	1024
++#define AIR_PHY_LED_DUR (AIR_PHY_LED_DUR_UNIT << AIR_PHY_LED_DUR_BLINK_64M)
++
++static const unsigned long en8811h_led_trig = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
++					       BIT(TRIGGER_NETDEV_LINK)        |
++					       BIT(TRIGGER_NETDEV_LINK_10)     |
++					       BIT(TRIGGER_NETDEV_LINK_100)    |
++					       BIT(TRIGGER_NETDEV_LINK_1000)   |
++					       BIT(TRIGGER_NETDEV_LINK_2500)   |
++					       BIT(TRIGGER_NETDEV_RX)          |
++					       BIT(TRIGGER_NETDEV_TX));
++
++static int air_phy_read_page(struct phy_device *phydev)
++{
++	return __phy_read(phydev, AIR_EXT_PAGE_ACCESS);
++}
++
++static int air_phy_write_page(struct phy_device *phydev, int page)
++{
++	return __phy_write(phydev, AIR_EXT_PAGE_ACCESS, page);
++}
++
++static int __air_buckpbus_reg_write(struct phy_device *phydev,
++				    u32 pbus_address, u32 pbus_data)
++{
++	int ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, HIWORD(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW,  LOWORD(pbus_data));
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int air_buckpbus_reg_write(struct phy_device *phydev,
++				  u32 pbus_address, u32 pbus_data)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_buckpbus_reg_write(phydev, pbus_address, pbus_data);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   pbus_address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++;
++}
++
++static int __air_buckpbus_reg_read(struct phy_device *phydev,
++				   u32 pbus_address, u32 *pbus_data)
++{
++	int pbus_data_low, pbus_data_high;
++	int ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_FIXED);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_HIGH, HIWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_RD_ADDR_LOW,  LOWORD(pbus_address));
++	if (ret < 0)
++		return ret;
++
++	pbus_data_high = __phy_read(phydev, AIR_PBUS_RD_DATA_HIGH);
++	if (pbus_data_high < 0)
++		return ret;
++
++	pbus_data_low = __phy_read(phydev, AIR_PBUS_RD_DATA_LOW);
++	if (pbus_data_low < 0)
++		return ret;
++
++	*pbus_data = (u16)pbus_data_low | ((u32)(u16)pbus_data_high << 16);
++	return 0;
++}
++
++static int air_buckpbus_reg_read(struct phy_device *phydev,
++				 u32 pbus_address, u32 *pbus_data)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_buckpbus_reg_read(phydev, pbus_address, pbus_data);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   pbus_address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int __air_write_buf(struct phy_device *phydev, u32 address,
++			   const struct firmware *fw)
++{
++	unsigned int offset;
++	int ret;
++	u16 val;
++
++	ret = __phy_write(phydev, AIR_PBUS_MODE, AIR_PBUS_MODE_ADDR_INCR);
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_HIGH, HIWORD(address));
++	if (ret < 0)
++		return ret;
++
++	ret = __phy_write(phydev, AIR_PBUS_WR_ADDR_LOW,  LOWORD(address));
++	if (ret < 0)
++		return ret;
++
++	for (offset = 0; offset < fw->size; offset += 4) {
++		val = get_unaligned_le16(&fw->data[offset + 2]);
++		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_HIGH, val);
++		if (ret < 0)
++			return ret;
++
++		val = get_unaligned_le16(&fw->data[offset]);
++		ret = __phy_write(phydev, AIR_PBUS_WR_DATA_LOW, val);
++		if (ret < 0)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int air_write_buf(struct phy_device *phydev, u32 address,
++			 const struct firmware *fw)
++{
++	int ret, saved_page;
++
++	saved_page = phy_select_page(phydev, AIR_PHY_PAGE_EXTENDED_4);
++
++	ret = __air_write_buf(phydev, address, fw);
++	if (ret < 0)
++		phydev_err(phydev, "%s 0x%08x failed: %d\n", __func__,
++			   address, ret);
++
++	return phy_restore_page(phydev, saved_page, ret);
++}
++
++static int en8811h_load_firmware(struct phy_device *phydev)
++{
++	struct device *dev = &phydev->mdio.dev;
++	const struct firmware *fw1, *fw2;
++	u32 pbus_value;
++	int ret;
++
++	ret = request_firmware_direct(&fw1, EN8811H_MD32_DM, dev);
++	if (ret < 0)
++		return ret;
++
++	ret = request_firmware_direct(&fw2, EN8811H_MD32_DSP, dev);
++	if (ret < 0)
++		goto en8811h_load_firmware_rel1;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++	pbus_value |= EN8811H_FW_CTRL_2_LOADING;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DM,  fw1);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_write_buf(phydev, AIR_FW_ADDR_DSP, fw2);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_CTRL_2, &pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++	pbus_value &= ~EN8811H_FW_CTRL_2_LOADING;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_2, pbus_value);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++	if (ret < 0)
++		goto en8811h_load_firmware_out;
++
++	ret = 0;
++
++en8811h_load_firmware_out:
++	release_firmware(fw2);
++
++en8811h_load_firmware_rel1:
++	release_firmware(fw1);
++
++	if (ret < 0)
++		phydev_err(phydev, "Load firmware failed: %d\n", ret);
++
++	return ret;
++}
++
++static int en8811h_restart_host(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_START);
++	if (ret < 0)
++		return ret;
++
++	return air_buckpbus_reg_write(phydev, EN8811H_FW_CTRL_1,
++				     EN8811H_FW_CTRL_1_FINISH);
++}
++
++static int air_hw_led_on_set(struct phy_device *phydev, u8 index, bool on)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (on)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_ON,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
++				      AIR_PHY_LED_ON(index),
++				      AIR_PHY_LED_ON_MASK,
++				      on ? AIR_PHY_LED_ON_FORCE_ON : 0);
++
++	return 0;
++}
++
++static int air_hw_led_blink_set(struct phy_device *phydev, u8 index,
++				bool blinking)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool changed;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (blinking)
++		changed = !test_and_set_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					    &priv->led[index].state);
++	else
++		changed = !!test_and_clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK,
++					       &priv->led[index].state);
++
++	changed |= (priv->led[index].rules != 0);
++
++	if (changed)
++		return phy_write_mmd(phydev, MDIO_MMD_VEND2,
++				     AIR_PHY_LED_BLINK(index),
++				     blinking ?
++				     AIR_PHY_LED_BLINK_FORCE_BLINK : 0);
++	else
++		return 0;
++}
++
++static int air_led_blink_set(struct phy_device *phydev, u8 index,
++			     unsigned long *delay_on,
++			     unsigned long *delay_off)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	bool blinking = false;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
++		blinking = true;
++		*delay_on = 50;
++		*delay_off = 50;
++	}
++
++	err = air_hw_led_blink_set(phydev, index, blinking);
++	if (err)
++		return err;
++
++	/* led-blink set, so switch led-on off */
++	err = air_hw_led_on_set(phydev, index, false);
++	if (err)
++		return err;
++
++	/* hw-control is off*/
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_brightness_set(struct phy_device *phydev, u8 index,
++				  enum led_brightness value)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* led-on set, so switch led-blink off */
++	err = air_hw_led_blink_set(phydev, index, false);
++	if (err)
++		return err;
++
++	err = air_hw_led_on_set(phydev, index, (value != LED_OFF));
++	if (err)
++		return err;
++
++	/* hw-control is off */
++	if (!!test_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state))
++		priv->led[index].rules = 0;
++
++	return 0;
++}
++
++static int air_led_hw_control_get(struct phy_device *phydev, u8 index,
++				  unsigned long *rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	*rules = priv->led[index].rules;
++
++	return 0;
++};
++
++static int air_led_hw_control_set(struct phy_device *phydev, u8 index,
++				  unsigned long rules)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u16 on = 0, blink = 0;
++	int ret;
++
++	priv->led[index].rules = rules;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_10)   | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK10;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_10RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_10TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_100)  | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK100;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_100RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_100TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK1000;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_1000RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_1000TX;
++	}
++
++	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK))) {
++		on |= AIR_PHY_LED_ON_LINK2500;
++		if (rules & BIT(TRIGGER_NETDEV_RX))
++			blink |= AIR_PHY_LED_BLINK_2500RX;
++		if (rules & BIT(TRIGGER_NETDEV_TX))
++			blink |= AIR_PHY_LED_BLINK_2500TX;
++	}
++
++	if (on == 0) {
++		if (rules & BIT(TRIGGER_NETDEV_RX)) {
++			blink |= AIR_PHY_LED_BLINK_10RX   |
++				 AIR_PHY_LED_BLINK_100RX  |
++				 AIR_PHY_LED_BLINK_1000RX |
++				 AIR_PHY_LED_BLINK_2500RX;
++		}
++		if (rules & BIT(TRIGGER_NETDEV_TX)) {
++			blink |= AIR_PHY_LED_BLINK_10TX   |
++				 AIR_PHY_LED_BLINK_100TX  |
++				 AIR_PHY_LED_BLINK_1000TX |
++				 AIR_PHY_LED_BLINK_2500TX;
++		}
++	}
++
++	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
++		on |= AIR_PHY_LED_ON_FDX;
++
++	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
++		on |= AIR_PHY_LED_ON_HDX;
++
++	if (blink || on) {
++		/* switch hw-control on, so led-on and led-blink are off */
++		clear_bit(AIR_PHY_LED_STATE_FORCE_ON, &priv->led[index].state);
++		clear_bit(AIR_PHY_LED_STATE_FORCE_BLINK, &priv->led[index].state);
++	} else {
++		priv->led[index].rules = 0;
++	}
++
++	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			     AIR_PHY_LED_ON_MASK, on);
++
++	if (ret < 0)
++		return ret;
++
++	return phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BLINK(index),
++			     blink);
++};
++
++static int air_led_init(struct phy_device *phydev, u8 index, u8 state, u8 pol)
++{
++	int cl45_data;
++	int err;
++
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index));
++	if (cl45_data < 0)
++		return cl45_data;
++
++	if (state == AIR_LED_ENABLE)
++		cl45_data |= AIR_PHY_LED_ON_ENABLE;
++	else
++		cl45_data &= ~AIR_PHY_LED_ON_ENABLE;
++
++	if (pol == AIR_ACTIVE_HIGH)
++		cl45_data |= AIR_PHY_LED_ON_POLARITY;
++	else
++		cl45_data &= ~AIR_PHY_LED_ON_POLARITY;
++
++	err = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_ON(index),
++			    cl45_data);
++	if (err < 0)
++		return err;
++
++	return 0;
++}
++
++static int air_leds_init(struct phy_device *phydev, int num, int dur, int mode)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	int cl45_data = dur;
++	int ret, i;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_BLINK,
++			    cl45_data);
++	if (ret < 0)
++		return ret;
++
++	cl45_data >>= 1;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_DUR_ON,
++			    cl45_data);
++	if (ret < 0)
++		return ret;
++
++	cl45_data = phy_read_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR);
++	if (cl45_data < 0)
++		return cl45_data;
++
++	switch (mode) {
++	case AIR_LED_MODE_DISABLE:
++		cl45_data &= ~AIR_PHY_LED_BCR_EXT_CTRL;
++		cl45_data &= ~AIR_PHY_LED_BCR_MODE_MASK;
++		break;
++	case AIR_LED_MODE_USER_DEFINE:
++		cl45_data |= AIR_PHY_LED_BCR_EXT_CTRL;
++		cl45_data |= AIR_PHY_LED_BCR_CLK_EN;
++		break;
++	default:
++		phydev_err(phydev, "LED mode %d is not supported\n", mode);
++		return -EINVAL;
++	}
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, AIR_PHY_LED_BCR, cl45_data);
++	if (ret < 0)
++		return ret;
++
++	for (i = 0; i < num; ++i) {
++		ret = air_led_init(phydev, i, AIR_LED_ENABLE, AIR_ACTIVE_HIGH);
++		if (ret < 0) {
++			phydev_err(phydev, "LED%d init failed: %d\n", i, ret);
++			return ret;
++		}
++		air_led_hw_control_set(phydev, i, priv->led[i].rules);
++	}
++
++	return 0;
++}
++
++static int en8811h_led_hw_is_supported(struct phy_device *phydev, u8 index,
++				       unsigned long rules)
++{
++	if (index >= EN8811H_LED_COUNT)
++		return -EINVAL;
++
++	/* All combinations of the supported triggers are allowed */
++	if (rules & ~en8811h_led_trig)
++		return -EOPNOTSUPP;
++
++	return 0;
++};
++
++static int en8811h_probe(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv;
++
++	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct en8811h_priv),
++			    GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	priv->led[0].rules = AIR_DEFAULT_TRIGGER_LED0;
++	priv->led[1].rules = AIR_DEFAULT_TRIGGER_LED1;
++	priv->led[2].rules = AIR_DEFAULT_TRIGGER_LED2;
++
++	phydev->priv = priv;
++
++	/* MDIO_DEVS1/2 empty, so set mmds_present bits here */
++	phydev->c45_ids.mmds_present |= MDIO_DEVS_PMAPMD | MDIO_DEVS_AN;
++
++	return 0;
++}
++
++static int en8811h_config_init(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	struct device *dev = &phydev->mdio.dev;
++	int ret, pollret, reg_value;
++	u32 pbus_value;
++
++	if (!priv->firmware_version)
++		ret = en8811h_load_firmware(phydev);
++	else
++		ret = en8811h_restart_host(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Because of mdio-lock, may have to wait for multiple loads */
++	pollret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1,
++					    EN8811H_PHY_FW_STATUS, reg_value,
++					    reg_value == EN8811H_PHY_READY,
++					    20000, 7500000, true);
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_FW_VERSION, &pbus_value);
++	if (ret < 0)
++		return ret;
++
++	if (pollret || !pbus_value) {
++		phydev_err(phydev, "Firmware not ready: 0x%x\n", reg_value);
++		return -ENODEV;
++	}
++
++	if (!priv->firmware_version) {
++		phydev_info(phydev, "MD32 firmware version: %08x\n", pbus_value);
++		priv->firmware_version = pbus_value;
++	}
++
++	/* Select mode 1, the only mode supported */
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_1,
++			    AIR_PHY_HOST_CMD_1_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_2,
++			    AIR_PHY_HOST_CMD_2_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
++			    AIR_PHY_HOST_CMD_3_MODE1);
++	if (ret < 0)
++		return ret;
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
++			    AIR_PHY_HOST_CMD_4_MODE1);
++	if (ret < 0)
++		return ret;
++
++	/* Serdes polarity */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_POLARITY, &pbus_value);
++	if (ret < 0)
++		return ret;
++	if (device_property_read_bool(dev, "airoha,pnswap-rx"))
++		pbus_value |=  EN8811H_POLARITY_RX_REVERSE;
++	else
++		pbus_value &= ~EN8811H_POLARITY_RX_REVERSE;
++	if (device_property_read_bool(dev, "airoha,pnswap-tx"))
++		pbus_value &= ~EN8811H_POLARITY_TX_NORMAL;
++	else
++		pbus_value |=  EN8811H_POLARITY_TX_NORMAL;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_POLARITY, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	ret = air_leds_init(phydev, EN8811H_LED_COUNT, AIR_PHY_LED_DUR,
++			    AIR_LED_MODE_USER_DEFINE);
++	if (ret < 0) {
++		phydev_err(phydev, "Failed to initialize leds: %d\n", ret);
++		return ret;
++	}
++
++	ret = air_buckpbus_reg_read(phydev, EN8811H_GPIO_OUTPUT, &pbus_value);
++	if (ret < 0)
++		return ret;
++	pbus_value |= EN8811H_GPIO_OUTPUT_345;
++	ret = air_buckpbus_reg_write(phydev, EN8811H_GPIO_OUTPUT, pbus_value);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static int en8811h_get_features(struct phy_device *phydev)
++{
++	linkmode_set_bit_array(phy_basic_ports_array,
++			       ARRAY_SIZE(phy_basic_ports_array),
++			       phydev->supported);
++
++	return genphy_c45_pma_read_abilities(phydev);
++}
++
++static int en8811h_get_rate_matching(struct phy_device *phydev,
++				     phy_interface_t iface)
++{
++	return RATE_MATCH_PAUSE;
++}
++
++static int en8811h_config_aneg(struct phy_device *phydev)
++{
++	bool changed = false;
++	int err, val;
++
++	val = 0;
++	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			      phydev->advertising))
++		val |= MDIO_AN_10GBT_CTRL_ADV2_5G;
++	err =  phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
++				      MDIO_AN_10GBT_CTRL_ADV2_5G, val);
++	if (err < 0)
++		return err;
++	if (err > 0)
++		changed = true;
++
++	return __genphy_config_aneg(phydev, changed);
++}
++
++static int en8811h_read_status(struct phy_device *phydev)
++{
++	struct en8811h_priv *priv = phydev->priv;
++	u32 pbus_value;
++	int ret, val;
++
++	ret = genphy_update_link(phydev);
++	if (ret)
++		return ret;
++
++	phydev->master_slave_get = MASTER_SLAVE_CFG_UNSUPPORTED;
++	phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED;
++	phydev->speed = SPEED_UNKNOWN;
++	phydev->duplex = DUPLEX_UNKNOWN;
++	phydev->pause = 0;
++	phydev->asym_pause = 0;
++
++	ret = genphy_read_master_slave(phydev);
++	if (ret < 0)
++		return ret;
++
++	ret = genphy_read_lpa(phydev);
++	if (ret < 0)
++		return ret;
++
++	/* Get link partner 2.5GBASE-T ability from vendor register */
++	ret = air_buckpbus_reg_read(phydev, EN8811H_2P5G_LPA, &pbus_value);
++	if (ret < 0)
++		return ret;
++	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++			 phydev->lp_advertising,
++			 pbus_value & EN8811H_2P5G_LPA_2P5G);
++
++	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete)
++		phy_resolve_aneg_pause(phydev);
++
++	if (!phydev->link)
++		return 0;
++
++	/* Get real speed from vendor register */
++	val = phy_read(phydev, AIR_AUX_CTRL_STATUS);
++	if (val < 0)
++		return val;
++	switch (val & AIR_AUX_CTRL_STATUS_SPEED_MASK) {
++	case AIR_AUX_CTRL_STATUS_SPEED_2500:
++		phydev->speed = SPEED_2500;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_1000:
++		phydev->speed = SPEED_1000;
++		break;
++	case AIR_AUX_CTRL_STATUS_SPEED_100:
++		phydev->speed = SPEED_100;
++		break;
++	}
++
++	/* BUG in PHY firmware: MDIO_AN_10GBT_STAT_LP2_5G does not get set.
++	 * Firmware before version 24011202 has no vendor register 2P5G_LPA.
++	 * Assume link partner advertised it if connected at 2500Mbps.
++	 */
++	if (priv->firmware_version < 0x24011202) {
++		linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
++				 phydev->lp_advertising,
++				 phydev->speed == SPEED_2500);
++	}
++
++	/* Only supports full duplex */
++	phydev->duplex = DUPLEX_FULL;
++
++	return 0;
++}
++
++static int en8811h_clear_intr(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_3,
++			    AIR_PHY_HOST_CMD_3_DOCMD);
++	if (ret < 0)
++		return ret;
++
++	ret = phy_write_mmd(phydev, MDIO_MMD_VEND1, AIR_PHY_HOST_CMD_4,
++			    AIR_PHY_HOST_CMD_4_INTCLR);
++	if (ret < 0)
++		return ret;
++
++	return 0;
++}
++
++static irqreturn_t en8811h_handle_interrupt(struct phy_device *phydev)
++{
++	int ret;
++
++	ret = en8811h_clear_intr(phydev);
++	if (ret < 0) {
++		phy_error(phydev);
++		return IRQ_NONE;
++	}
++
++	phy_trigger_machine(phydev);
++
++	return IRQ_HANDLED;
++}
++
++static struct phy_driver en8811h_driver[] = {
++{
++	PHY_ID_MATCH_MODEL(EN8811H_PHY_ID),
++	.name			= "Airoha EN8811H",
++	.probe			= en8811h_probe,
++	.get_features		= en8811h_get_features,
++	.config_init		= en8811h_config_init,
++	.get_rate_matching	= en8811h_get_rate_matching,
++	.config_aneg		= en8811h_config_aneg,
++	.read_status		= en8811h_read_status,
++	.config_intr		= en8811h_clear_intr,
++	.handle_interrupt	= en8811h_handle_interrupt,
++	.led_hw_is_supported	= en8811h_led_hw_is_supported,
++	.read_page		= air_phy_read_page,
++	.write_page		= air_phy_write_page,
++	.led_blink_set		= air_led_blink_set,
++	.led_brightness_set	= air_led_brightness_set,
++	.led_hw_control_set	= air_led_hw_control_set,
++	.led_hw_control_get	= air_led_hw_control_get,
++} };
++
++module_phy_driver(en8811h_driver);
++
++static struct mdio_device_id __maybe_unused en8811h_tbl[] = {
++	{ PHY_ID_MATCH_MODEL(EN8811H_PHY_ID) },
++	{ }
++};
++MODULE_DEVICE_TABLE(mdio, en8811h_tbl);
++MODULE_FIRMWARE(EN8811H_MD32_DM);
++MODULE_FIRMWARE(EN8811H_MD32_DSP);
++
++MODULE_DESCRIPTION("Airoha EN8811H PHY drivers");
++MODULE_AUTHOR("Airoha");
++MODULE_AUTHOR("Eric Woudstra <ericwouds@gmail.com>");
++MODULE_LICENSE("GPL");
diff --git a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
index baaf850fe40..42c8519c905 100644
--- a/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
+++ b/target/linux/generic/pending-6.1/760-net-core-add-optional-threading-for-backlog-processi.patch
@@ -12,7 +12,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
 
 --- a/include/linux/netdevice.h
 +++ b/include/linux/netdevice.h
-@@ -520,6 +520,7 @@ static inline bool napi_complete(struct
+@@ -543,6 +543,7 @@ static inline bool napi_complete(struct
  }
  
  int dev_set_threaded(struct net_device *dev, bool threaded);
@@ -20,7 +20,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  
  /**
   *	napi_disable - prevent NAPI from scheduling
-@@ -3129,6 +3130,7 @@ struct softnet_data {
+@@ -3152,6 +3153,7 @@ struct softnet_data {
  	unsigned int		processed;
  	unsigned int		time_squeeze;
  	unsigned int		received_rps;
@@ -167,7 +167,7 @@ Signed-off-by: Felix Fietkau <nbd@nbd.name>
  #ifdef CONFIG_RPS
  	remsd = oldsd->rps_ipi_list;
  	oldsd->rps_ipi_list = NULL;
-@@ -11471,6 +11545,7 @@ static int __init net_dev_init(void)
+@@ -11480,6 +11554,7 @@ static int __init net_dev_init(void)
  		INIT_CSD(&sd->defer_csd, trigger_rx_softirq, sd);
  		spin_lock_init(&sd->defer_lock);
  
diff --git a/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch b/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
index 874df43e7ce..f239355594a 100644
--- a/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
+++ b/target/linux/generic/pending-6.1/790-bus-mhi-core-add-SBL-state-callback.patch
@@ -20,7 +20,7 @@ Signed-off-by: Robert Marko <robimarko@gmail.com>
 
 --- a/drivers/bus/mhi/host/main.c
 +++ b/drivers/bus/mhi/host/main.c
-@@ -900,6 +900,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
+@@ -905,6 +905,7 @@ int mhi_process_ctrl_ev_ring(struct mhi_
  			switch (event) {
  			case MHI_EE_SBL:
  				st = DEV_ST_TRANSITION_SBL;
diff --git a/target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
new file mode 100644
index 00000000000..47e3b140c81
--- /dev/null
+++ b/target/linux/generic/pending-6.1/796-net-dsa-mt7530-fix-10M-100M-speed-on-MT7988-switch.patch
@@ -0,0 +1,45 @@
+From a444877c10a665cd8a869e6d37facdb89fd95f79 Mon Sep 17 00:00:00 2001
+Message-ID: <a444877c10a665cd8a869e6d37facdb89fd95f79.1706070008.git.daniel@makrotopia.org>
+From: Daniel Golle <daniel@makrotopia.org>
+Date: Wed, 24 Jan 2024 04:17:11 +0000
+Subject: [PATCH net] net: dsa: mt7530: fix 10M/100M speed on MT7988 switch
+To: Arınç ÜNAL <arinc.unal@arinc9.com>,
+    Daniel Golle <daniel@makrotopia.org>,
+    DENG Qingfang <dqfext@gmail.com>,
+    Sean Wang <sean.wang@mediatek.com>,
+    Andrew Lunn <andrew@lunn.ch>,
+    Florian Fainelli <f.fainelli@gmail.com>,
+    Vladimir Oltean <olteanv@gmail.com>,
+    David S. Miller <davem@davemloft.net>,
+    Eric Dumazet <edumazet@google.com>,
+    Jakub Kicinski <kuba@kernel.org>,
+    Paolo Abeni <pabeni@redhat.com>,
+    Matthias Brugger <matthias.bgg@gmail.com>,
+    AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
+    netdev@vger.kernel.org,
+    linux-kernel@vger.kernel.org,
+    linux-arm-kernel@lists.infradead.org,
+    linux-mediatek@lists.infradead.org
+
+Setup PMCR port register for actual speed and duplex on internally
+connected PHYs of the MT7988 built-in switch. This fixes links with
+speeds other than 1000M.
+
+Fixes: ("110c18bfed414 net: dsa: mt7530: introduce driver for MT7988 built-in switch")
+Signed-off-by: Daniel Golle <daniel@makrotopia.org>
+---
+ drivers/net/dsa/mt7530.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/mt7530.c
++++ b/drivers/net/dsa/mt7530.c
+@@ -2849,8 +2849,7 @@ static void mt753x_phylink_mac_link_up(s
+ 	/* MT753x MAC works in 1G full duplex mode for all up-clocked
+ 	 * variants.
+ 	 */
+-	if (interface == PHY_INTERFACE_MODE_INTERNAL ||
+-	    interface == PHY_INTERFACE_MODE_TRGMII ||
++	if (interface == PHY_INTERFACE_MODE_TRGMII ||
+ 	    (phy_interface_mode_is_8023z(interface))) {
+ 		speed = SPEED_1000;
+ 		duplex = DUPLEX_FULL;
diff --git a/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch b/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch
index 68ac12f996d..ba06196f7cb 100644
--- a/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch
+++ b/target/linux/generic/pending-6.1/810-pci_disable_common_quirks.patch
@@ -33,7 +33,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  /*
   * The Mellanox Tavor device gives false positive parity errors.  Disable
   * parity error reporting.
-@@ -3390,6 +3391,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
+@@ -3393,6 +3394,8 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_I
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
  
@@ -42,7 +42,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  /*
   * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum.
   * To work around this, query the size it should be configured to by the
-@@ -3415,6 +3418,8 @@ static void quirk_intel_ntb(struct pci_d
+@@ -3418,6 +3421,8 @@ static void quirk_intel_ntb(struct pci_d
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
  DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
  
@@ -51,7 +51,7 @@ Signed-off-by: Gabor Juhos <juhosg@openwrt.org>
  /*
   * Some BIOS implementations leave the Intel GPU interrupts enabled, even
   * though no one is handling them (e.g., if the i915 driver is never
-@@ -3453,6 +3458,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
+@@ -3456,6 +3461,8 @@ DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_IN
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
  DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
  
diff --git a/target/linux/rockchip/armv8/config-6.1 b/target/linux/rockchip/armv8/config-6.1
index b4a4de7101d..becae0770b5 100644
--- a/target/linux/rockchip/armv8/config-6.1
+++ b/target/linux/rockchip/armv8/config-6.1
@@ -1,5 +1,6 @@
 CONFIG_64BIT=y
 CONFIG_AHCI_DWC=y
+# CONFIG_AIR_EN8811H_PHY is not set
 CONFIG_ARCH_BINFMT_ELF_EXTRA_PHDRS=y
 CONFIG_ARCH_CORRECT_STACKTRACE_ON_KRETPROBE=y
 CONFIG_ARCH_DMA_ADDR_T_64BIT=y
@@ -71,6 +72,7 @@ CONFIG_ARM_PSCI_CPUIDLE_DOMAIN=y
 CONFIG_ARM_PSCI_FW=y
 # CONFIG_ARM_RK3328_DMC_DEVFREQ is not set
 # CONFIG_ARM_RK3399_DMC_DEVFREQ is not set
+# CONFIG_ARM_ROCKCHIP_CPUFREQ is not set
 CONFIG_ARM_SCMI_CPUFREQ=y
 CONFIG_ARM_SCMI_HAVE_SHMEM=y
 CONFIG_ARM_SCMI_HAVE_TRANSPORT=y
@@ -117,6 +119,7 @@ CONFIG_CC_HAVE_STACKPROTECTOR_SYSREG=y
 CONFIG_CC_IMPLICIT_FALLTHROUGH="-Wimplicit-fallthrough=5"
 CONFIG_CC_NO_ARRAY_BOUNDS=y
 CONFIG_CHARGER_GPIO=y
+CONFIG_CHARGER_RK817=y
 CONFIG_CHR_DEV_SG=y
 CONFIG_CLKSRC_MMIO=y
 # CONFIG_CLK_PX30 is not set
@@ -125,6 +128,7 @@ CONFIG_CLK_RK3328=y
 # CONFIG_CLK_RK3368 is not set
 CONFIG_CLK_RK3399=y
 CONFIG_CLK_RK3568=y
+CONFIG_CLK_RK3588=y
 CONFIG_CLONE_BACKWARDS=y
 CONFIG_CMA=y
 CONFIG_CMA_ALIGNMENT=8
@@ -138,6 +142,7 @@ CONFIG_CMA_SIZE_SEL_MBYTES=y
 # CONFIG_CMA_SIZE_SEL_PERCENTAGE is not set
 # CONFIG_CMA_SYSFS is not set
 CONFIG_COMMON_CLK=y
+CONFIG_COMMON_CLK_RK808=y
 CONFIG_COMMON_CLK_ROCKCHIP=y
 CONFIG_COMMON_CLK_SCMI=y
 CONFIG_COMPACT_UNEVICTABLE_DEFAULT=1
@@ -189,29 +194,45 @@ CONFIG_CRYPTO_CRC32=y
 CONFIG_CRYPTO_CRC32C=y
 CONFIG_CRYPTO_CRC64_ROCKSOFT=y
 CONFIG_CRYPTO_CRCT10DIF=y
-CONFIG_CRYPTO_CRCT10DIF_ARM64_CE=y
 CONFIG_CRYPTO_CRYPTD=y
+CONFIG_CRYPTO_CTS=y
 CONFIG_CRYPTO_DES=y
-CONFIG_CRYPTO_DEV_ROCKCHIP=y
-CONFIG_CRYPTO_DEV_ROCKCHIP2=y
-# CONFIG_CRYPTO_DEV_ROCKCHIP2_DEBUG is not set
-# CONFIG_CRYPTO_DEV_ROCKCHIP_DEBUG is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP is not set
+# CONFIG_CRYPTO_DEV_ROCKCHIP2 is not set
+CONFIG_CRYPTO_DRBG=y
+CONFIG_CRYPTO_DRBG_HMAC=y
+CONFIG_CRYPTO_DRBG_MENU=y
 CONFIG_CRYPTO_ECB=y
-CONFIG_CRYPTO_ENGINE=y
 CONFIG_CRYPTO_GHASH_ARM64_CE=y
+CONFIG_CRYPTO_HMAC=y
 CONFIG_CRYPTO_HW=y
+CONFIG_CRYPTO_JITTERENTROPY=y
 CONFIG_CRYPTO_LIB_BLAKE2S_GENERIC=y
 CONFIG_CRYPTO_LIB_DES=y
 CONFIG_CRYPTO_LIB_SHA1=y
 CONFIG_CRYPTO_LIB_SHA256=y
 CONFIG_CRYPTO_LIB_UTILS=y
 CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_RNG=y
 CONFIG_CRYPTO_RNG2=y
+CONFIG_CRYPTO_RNG_DEFAULT=y
+CONFIG_CRYPTO_SEQIV=y
 CONFIG_CRYPTO_SHA1=y
 CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_SHA256_ARM64=y
+CONFIG_CRYPTO_SHA2_ARM64_CE=y
+CONFIG_CRYPTO_SHA3=y
+CONFIG_CRYPTO_SHA3_ARM64=y
 CONFIG_CRYPTO_SHA512=y
+CONFIG_CRYPTO_SHA512_ARM64=y
+CONFIG_CRYPTO_SHA512_ARM64_CE=y
 CONFIG_CRYPTO_SM3=y
+CONFIG_CRYPTO_SM3_ARM64_CE=y
 CONFIG_CRYPTO_SM3_GENERIC=y
+CONFIG_CRYPTO_SM4=y
+CONFIG_CRYPTO_SM4_ARM64_CE=y
+CONFIG_CRYPTO_SM4_ARM64_CE_BLK=y
+CONFIG_CRYPTO_XTS=y
 CONFIG_DCACHE_WORD_ACCESS=y
 CONFIG_DEBUG_BUGVERBOSE=y
 CONFIG_DEBUG_INFO=y
@@ -337,7 +358,6 @@ CONFIG_HWMON=y
 CONFIG_HWSPINLOCK=y
 CONFIG_HW_CONSOLE=y
 CONFIG_HW_RANDOM=y
-CONFIG_HW_RANDOM_ROCKCHIP=y
 CONFIG_HZ=300
 # CONFIG_HZ_100 is not set
 CONFIG_HZ_300=y
@@ -364,6 +384,7 @@ CONFIG_INPUT_MOUSEDEV=y
 CONFIG_INPUT_MOUSEDEV_PSAUX=y
 CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
 CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_RK805_PWRKEY=y
 CONFIG_INPUT_SPARSEKMAP=y
 CONFIG_IOMMU_API=y
 # CONFIG_IOMMU_DEBUGFS is not set
@@ -421,7 +442,11 @@ CONFIG_MDIO_DEVRES=y
 CONFIG_MEDIATEK_GE_PHY=y
 CONFIG_MEMFD_CREATE=y
 CONFIG_MEMORY_ISOLATION=y
+CONFIG_MFD_CORE=y
 # CONFIG_MFD_KHADAS_MCU is not set
+CONFIG_MFD_RK8XX=y
+CONFIG_MFD_RK8XX_I2C=y
+CONFIG_MFD_RK8XX_SPI=y
 CONFIG_MFD_SYSCON=y
 CONFIG_MIGRATION=y
 CONFIG_MMC=y
@@ -551,6 +576,7 @@ CONFIG_PCS_MTK_LYNXI=y
 CONFIG_PCS_XPCS=y
 CONFIG_PGTABLE_LEVELS=4
 CONFIG_PHYLIB=y
+CONFIG_PHYLIB_LEDS=y
 CONFIG_PHYLINK=y
 CONFIG_PHYS_ADDR_T_64BIT=y
 CONFIG_PHY_ROCKCHIP_DP=y
@@ -565,7 +591,9 @@ CONFIG_PHY_ROCKCHIP_PCIE=y
 CONFIG_PHY_ROCKCHIP_SNPS_PCIE3=y
 CONFIG_PHY_ROCKCHIP_TYPEC=y
 CONFIG_PHY_ROCKCHIP_USB=y
+CONFIG_PHY_ROCKCHIP_USBDP=y
 CONFIG_PINCTRL=y
+CONFIG_PINCTRL_RK805=y
 CONFIG_PINCTRL_ROCKCHIP=y
 # CONFIG_PINCTRL_SINGLE is not set
 CONFIG_PL330_DMA=y
@@ -586,12 +614,9 @@ CONFIG_POWER_RESET_SYSCON_POWEROFF=y
 CONFIG_POWER_SUPPLY=y
 CONFIG_POWER_SUPPLY_HWMON=y
 CONFIG_PPS=y
-CONFIG_PREEMPT=y
-CONFIG_PREEMPTION=y
-CONFIG_PREEMPT_BUILD=y
-CONFIG_PREEMPT_COUNT=y
 # CONFIG_PREEMPT_NONE is not set
-CONFIG_PREEMPT_RCU=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_PREEMPT_VOLUNTARY_BUILD=y
 CONFIG_PRINTK_TIME=y
 # CONFIG_PRINT_QUOTA_WARNING is not set
 CONFIG_PROC_EVENTS=y
@@ -618,13 +643,16 @@ CONFIG_RCU_TRACE=y
 CONFIG_REALTEK_PHY=y
 CONFIG_REGMAP=y
 CONFIG_REGMAP_I2C=y
+CONFIG_REGMAP_IRQ=y
 CONFIG_REGMAP_MMIO=y
+CONFIG_REGMAP_SPI=y
 CONFIG_REGULATOR=y
 # CONFIG_REGULATOR_ARM_SCMI is not set
 CONFIG_REGULATOR_FAN53555=y
 CONFIG_REGULATOR_FIXED_VOLTAGE=y
 CONFIG_REGULATOR_GPIO=y
 CONFIG_REGULATOR_PWM=y
+CONFIG_REGULATOR_RK808=y
 CONFIG_RELOCATABLE=y
 CONFIG_RESET_CONTROLLER=y
 CONFIG_RESET_SCMI=y
@@ -634,7 +662,7 @@ CONFIG_RFS_ACCEL=y
 # CONFIG_ROCKCHIP_CDN_DP is not set
 CONFIG_ROCKCHIP_DW_HDMI=y
 CONFIG_ROCKCHIP_DW_MIPI_DSI=y
-CONFIG_ROCKCHIP_ERRATUM_114514=y
+CONFIG_ROCKCHIP_ERRATUM_3588001=y
 CONFIG_ROCKCHIP_GRF=y
 CONFIG_ROCKCHIP_INNO_HDMI=y
 CONFIG_ROCKCHIP_IODOMAIN=y
@@ -654,6 +682,7 @@ CONFIG_RPS=y
 CONFIG_RSEQ=y
 CONFIG_RTC_CLASS=y
 CONFIG_RTC_DRV_HYM8563=y
+CONFIG_RTC_DRV_RK808=y
 CONFIG_RTC_I2C_AND_SPI=y
 CONFIG_RTC_NVMEM=y
 # CONFIG_RUNTIME_TESTING_MENU is not set
@@ -775,7 +804,6 @@ CONFIG_TYPEC_TCPM=y
 # CONFIG_UACCE is not set
 # CONFIG_UCLAMP_TASK is not set
 # CONFIG_UEVENT_HELPER is not set
-CONFIG_UNINLINE_SPIN_UNLOCK=y
 CONFIG_UNMAP_KERNEL_AT_EL0=y
 CONFIG_USB=y
 CONFIG_USB_COMMON=y
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat-zero-n.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat-zero-n.dts
index eb713f93c7f..9fdcfab0cbf 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat-zero-n.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat-zero-n.dts
@@ -466,18 +466,14 @@
 };
 
 &sdmmc0 {
-    max-frequency = <150000000>;
-    supports-sd;
-    bus-width = <4>;
-    cap-mmc-highspeed;
-    cap-sd-highspeed;
-    disable-wp;
-    sd-uhs-sdr104;
-    vmmc-supply = <&vcc3v3_sd>;
-    vqmmc-supply = <&vccio_sd>;
-    pinctrl-names = "default";
-    pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-    status = "okay";
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
 };
 
 /* USB OTG/USB Host_1 USB 2.0 Comb */
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1.dts
index 95394614661..a737160f5fc 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1.dts
@@ -520,17 +520,13 @@
 };
 
 &sdmmc0 {
-	max-frequency = <150000000>;
-	supports-sd;
 	bus-width = <4>;
-	cap-mmc-highspeed;
 	cap-sd-highspeed;
 	disable-wp;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
 };
 
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1n.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1n.dts
index 6abb14f1564..4fc634b5a36 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1n.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3566-lubancat1n.dts
@@ -447,18 +447,14 @@
 };
 
 &sdmmc0 {
-    max-frequency = <150000000>;
-    supports-sd;
-    bus-width = <4>;
-    cap-mmc-highspeed;
-    cap-sd-highspeed;
-    disable-wp;
-    sd-uhs-sdr104;
-    vmmc-supply = <&vcc3v3_sd>;
-    vqmmc-supply = <&vccio_sd>;
-    pinctrl-names = "default";
-    pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-    status = "okay";
+	bus-width = <4>;
+	cap-sd-highspeed;
+	disable-wp;
+	pinctrl-names = "default";
+	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
+	status = "okay";
 };
 
 /* USB OTG/USB Host_1 USB 2.0 Comb */
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat.dtsi b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat.dtsi
index d4358cb2570..4973fd6ef9d 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat.dtsi
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat.dtsi
@@ -13,8 +13,6 @@
 
 /delete-node/ &gmac0;
 /delete-node/ &gmac1;
-/delete-node/ &pcie3x1;
-/delete-node/ &pcie3x2;
 
 / {
 	gmac0: eth@fe2a0000 {
@@ -110,108 +108,4 @@
 			queue0 {};
 		};
 	};
-
-	pcie3x2: pci@fe280000 {
-		compatible = "rockchip,rk3568-pcie";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		bus-range = <0x20 0x2f>;
-		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
-			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
-			 <&cru CLK_PCIE30X2_AUX_NDFT>;
-		clock-names = "aclk_mst", "aclk_slv",
-			      "aclk_dbi", "pclk", "aux";
-		device_type = "pci";
-		interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
-				<0 0 0 2 &pcie3x2_intc 1>,
-				<0 0 0 3 &pcie3x2_intc 2>,
-				<0 0 0 4 &pcie3x2_intc 3>;
-		linux,pci-domain = <2>;
-		num-ib-windows = <6>;
-		num-ob-windows = <2>;
-		max-link-speed = <3>;
-		msi-map = <0x2000 &its 0x2000 0x1000>;
-		num-lanes = <2>;
-		phys = <&pcie30phy>;
-		phy-names = "pcie-phy";
-		power-domains = <&power RK3568_PD_PIPE>;
-		reg = <0x3 0xc0800000 0x0 0x00400000>,
-		      <0x0 0xfe280000 0x0 0x00010000>,
-		      <0x3 0xbf000000 0x0 0x01000000>;
-		ranges = <0x01000000 0x0 0x3ef00000 0x3 0xbef00000 0x0 0x00100000>,
-			 <0x02000000 0x0 0x00000000 0x3 0x80000000 0x0 0x3ef00000>;
-		reg-names = "dbi", "apb", "config";
-		resets = <&cru SRST_PCIE30X2_POWERUP>;
-		reset-names = "pipe";
-		/* bifurcation; lane0 when using 1+1 */
-		status = "disabled";
-
-		pcie3x2_intc: legacy-interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 162 IRQ_TYPE_EDGE_RISING>;
-		};
-	};
-
-	pcie3x1: pci@fe270000 {
-		compatible = "rockchip,rk3568-pcie";
-		#address-cells = <3>;
-		#size-cells = <2>;
-		bus-range = <0x10 0x1f>;
-		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
-			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
-			 <&cru CLK_PCIE30X1_AUX_NDFT>;
-		clock-names = "aclk_mst", "aclk_slv",
-			      "aclk_dbi", "pclk", "aux";
-		device_type = "pci";
-		interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
-			     <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
-		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
-		#interrupt-cells = <1>;
-		interrupt-map-mask = <0 0 0 7>;
-		interrupt-map = <0 0 0 1 &pcie3x1_intc 0>,
-				<0 0 0 2 &pcie3x1_intc 1>,
-				<0 0 0 3 &pcie3x1_intc 2>,
-				<0 0 0 4 &pcie3x1_intc 3>;
-		linux,pci-domain = <1>;
-		num-ib-windows = <6>;
-		num-ob-windows = <2>;
-		max-link-speed = <3>;
-		msi-map = <0x1000 &its 0x1000 0x1000>;
-		num-lanes = <1>;
-		phys = <&pcie30phy>;
-		phy-names = "pcie-phy";
-		power-domains = <&power RK3568_PD_PIPE>;
-		reg = <0x3 0xc0400000 0x0 0x00400000>,
-		      <0x0 0xfe270000 0x0 0x00010000>,
-		      <0x3 0x7f000000 0x0 0x01000000>;
-		ranges = <0x01000000 0x0 0x3ef00000 0x3 0x7ef00000 0x0 0x00100000>,
-			 <0x02000000 0x0 0x00000000 0x3 0x40000000 0x0 0x3ef00000>;
-		reg-names = "dbi", "apb", "config";
-		resets = <&cru SRST_PCIE30X1_POWERUP>;
-		reset-names = "pipe";
-		/* bifurcation; lane1 when using 1+1 */
-		status = "disabled";
-
-		pcie3x1_intc: legacy-interrupt-controller {
-			interrupt-controller;
-			#address-cells = <0>;
-			#interrupt-cells = <1>;
-			interrupt-parent = <&gic>;
-			interrupts = <GIC_SPI 157 IRQ_TYPE_EDGE_RISING>;
-		};
-	};
 };
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2.dts
index dd5b7963ad2..ab073952fef 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2.dts
@@ -609,18 +609,13 @@
 };
 
 &sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
 	bus-width = <4>;
-	cap-mmc-highspeed;
 	cap-sd-highspeed;
 	disable-wp;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
 };
 
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2io.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2io.dts
index 71bfdf66d9a..f15521a6f1b 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2io.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2io.dts
@@ -603,18 +603,13 @@
 };
 
 &sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
 	bus-width = <4>;
-	cap-mmc-highspeed;
 	cap-sd-highspeed;
 	disable-wp;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
 };
 
diff --git a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2n.dts b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2n.dts
index 76de0277067..0370855c4cc 100644
--- a/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2n.dts
+++ b/target/linux/rockchip/files-6.1/arch/arm64/boot/dts/rockchip/rk3568-lubancat2n.dts
@@ -18,8 +18,6 @@
 	aliases {
 		ethernet0 = &gmac0;
 		ethernet1 = &gmac1;
-		ethernet2 = &rtl8125_2;
-		ethernet3 = &rtl8125_1;
 		mmc0 = &sdmmc0;
 		mmc1 = &sdhci;
 	};
@@ -547,20 +545,6 @@
 	reset-gpios = <&gpio2 RK_PD5 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
-
-	pcie@10 {
-		reg = <0x00100000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		// ETH3 2.5G
-		rtl8125_1: pcie-eth@10,0 {
-			compatible = "pci10ec,8125";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x4078>;
-		};
-	};
 };
 
 &pcie3x2 {
@@ -568,20 +552,6 @@
 	reset-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
-
-	// ETH2 2.5G
-	pcie@20 {
-		reg = <0x00200000 0 0 0 0>;
-		#address-cells = <3>;
-		#size-cells = <2>;
-
-		rtl8125_2: pcie-eth@20,0 {
-			compatible = "pci10ec,8125";
-			reg = <0x000000 0 0 0 0>;
-
-			realtek,led-data = <0x4078>;
-		};
-	};
 };
 
 &pcie2x1 {
@@ -658,18 +628,13 @@
 };
 
 &sdmmc0 {
-	max-frequency = <150000000>;
-	no-sdio;
-	no-mmc;
 	bus-width = <4>;
-	cap-mmc-highspeed;
 	cap-sd-highspeed;
 	disable-wp;
-	sd-uhs-sdr104;
-	vmmc-supply = <&vcc3v3_sd>;
-	vqmmc-supply = <&vccio_sd>;
 	pinctrl-names = "default";
 	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+	vmmc-supply = <&vcc3v3_sd>;
+	vqmmc-supply = <&vccio_sd>;
 	status = "okay";
 };
 
diff --git a/target/linux/rockchip/image/Makefile b/target/linux/rockchip/image/Makefile
index e8aab677fb4..5de053bdb6b 100644
--- a/target/linux/rockchip/image/Makefile
+++ b/target/linux/rockchip/image/Makefile
@@ -21,7 +21,7 @@ endef
 
 define Build/boot-script
 	# Make an U-boot image and copy it to the boot partition
-	mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),mmc).bootscript $@.boot/boot.scr
+	mkimage -A arm -O linux -T script -C none -a 0 -e 0 -d $(if $(1),$(1),default).bootscript $@.boot/boot.scr
 endef
 
 define Build/pine64-img
@@ -44,32 +44,15 @@ define Build/pine64-img
 	dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-u-boot.itb of="$@" seek=16384 conv=notrunc
 endef
 
-define Build/pine64-bin
-	# Typical Rockchip boot flow with Rockchip miniloader
-	# Rockchp idbLoader which is combinded by Rockchip ddr init bin
-	# and miniloader bin from Rockchip rkbin project
-
-	# Generate a new partition table in $@ with 32 MiB of alignment
-	# padding for the idbloader, uboot and trust image to fit:
-	# http://opensource.rock-chips.com/wiki_Boot_option#Boot_flow
-	PADDING=1 $(SCRIPT_DIR)/gen_image_generic.sh \
-		$@ \
-		$(CONFIG_TARGET_KERNEL_PARTSIZE) $@.boot \
-		$(CONFIG_TARGET_ROOTFS_PARTSIZE) $(IMAGE_ROOTFS) \
-		32768
-
-	# Copy the idbloader, uboot and trust image to the image at sector 0x40, 0x4000 and 0x6000
-	dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-idbloader.bin of="$@" seek=64 conv=notrunc
-	dd if="$(STAGING_DIR_IMAGE)"/$(UBOOT_DEVICE_NAME)-uboot.img of="$@" seek=16384 conv=notrunc
-	dd if="$(STAGING_DIR_IMAGE)"/$(SOC)-trust.bin of="$@" seek=24576 conv=notrunc
-endef
-
 ### Devices ###
 define Device/Default
   PROFILES := Default
   KERNEL = kernel-bin | lzma | fit lzma $$(DTS_DIR)/$$(DEVICE_DTS).dtb
+  BOOT_SCRIPT :=
   IMAGES := sysupgrade.img.gz
+  IMAGE/sysupgrade.img.gz = boot-common | boot-script $$(BOOT_SCRIPT) | pine64-img | gzip | append-metadata
   DEVICE_DTS = rockchip/$$(SOC)-$(lastword $(subst _, ,$(1)))
+  UBOOT_DEVICE_NAME = $(lastword $(subst _, ,$(1)))-$$(SOC)
 endef
 
 include $(SUBTARGET).mk
diff --git a/target/linux/rockchip/image/armv8.mk b/target/linux/rockchip/image/armv8.mk
index ba489faf696..1da375c91b3 100644
--- a/target/linux/rockchip/image/armv8.mk
+++ b/target/linux/rockchip/image/armv8.mk
@@ -9,8 +9,7 @@ define Device/embedfire_doornet1
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := DoorNet1
   SOC := rk3328
-  UBOOT_DEVICE_NAME := doornet1-rk3328
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk3328 | pine64-bin | gzip | append-metadata
+  BOOT_FLOW := pine64-bin
   DEVICE_PACKAGES := kmod-usb-net-rtl8152 kmod-rtl8821cu
 endef
 TARGET_DEVICES += embedfire_doornet1
@@ -19,8 +18,7 @@ define Device/embedfire_doornet2
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := DoorNet2
   SOC := rk3399
-  UBOOT_DEVICE_NAME := doornet2-rk3399
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk3399 | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-bin
   DEVICE_PACKAGES := kmod-r8169 -urngd
 endef
 TARGET_DEVICES += embedfire_doornet2
@@ -29,8 +27,7 @@ define Device/embedfire_lubancat-zero-n
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := LubanCat Zero N
   SOC := rk3566
-  UBOOT_DEVICE_NAME := lubancat-zero-n-rk3566
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk356x | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-img
   DEVICE_PACKAGES := kmod-r8125
 endef
 TARGET_DEVICES += embedfire_lubancat-zero-n
@@ -39,8 +36,7 @@ define Device/embedfire_lubancat1
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := LubanCat 1
   SOC := rk3566
-  UBOOT_DEVICE_NAME := lubancat1-rk3566
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk356x | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-img
   DEVICE_PACKAGES := kmod-r8169
 endef
 TARGET_DEVICES += embedfire_lubancat1
@@ -49,8 +45,7 @@ define Device/embedfire_lubancat1n
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := LubanCat 1N
   SOC := rk3566
-  UBOOT_DEVICE_NAME := lubancat1n-rk3566
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk356x | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-img
   DEVICE_PACKAGES := kmod-r8169 -urngd kmod-ata-ahci
 endef
 TARGET_DEVICES += embedfire_lubancat1n
@@ -59,8 +54,7 @@ define Device/embedfire_lubancat2
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := LubanCat 2
   SOC := rk3568
-  UBOOT_DEVICE_NAME := lubancat2-rk3568
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk356x | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-img
   DEVICE_PACKAGES := kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core
 endef
 TARGET_DEVICES += embedfire_lubancat2
@@ -69,8 +63,7 @@ define Device/embedfire_lubancat2n
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := LubanCat 2N
   SOC := rk3568
-  UBOOT_DEVICE_NAME := lubancat2n-rk3568
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk356x | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-img
   DEVICE_PACKAGES := kmod-r8125 kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core
 endef
 TARGET_DEVICES += embedfire_lubancat2n
@@ -79,8 +72,7 @@ define Device/embedfire_lubancat2io
   DEVICE_VENDOR := EmbedFire
   DEVICE_MODEL := LubanCat 2IO
   SOC := rk3568
-  UBOOT_DEVICE_NAME := lubancat2io-rk3568
-  IMAGE/sysupgrade.img.gz := boot-common | boot-script rk356x | pine64-img | gzip | append-metadata
+  BOOT_FLOW := pine64-img
   DEVICE_PACKAGES := kmod-r8125 kmod-ata-ahci kmod-ata-ahci-platform kmod-ata-core
 endef
 TARGET_DEVICES += embedfire_lubancat2io
\ No newline at end of file
diff --git a/target/linux/rockchip/image/default.bootscript b/target/linux/rockchip/image/default.bootscript
new file mode 100644
index 00000000000..e9de14ff7ac
--- /dev/null
+++ b/target/linux/rockchip/image/default.bootscript
@@ -0,0 +1,15 @@
+part uuid ${devtype} ${devnum}:2 uuid
+
+if test $stdout = 'serial@fe660000' ;
+then serial_addr=',0xfe660000';
+elif test $stdout = 'serial@ff130000' ;
+then serial_addr=',0xff130000';
+elif test $stdout = 'serial@ff1a0000' ;
+then serial_addr=',0xff1a0000';
+fi;
+
+setenv bootargs "console=ttyS2,1500000 console=tty1 earlycon=uart8250,mmio32${serial_addr} swiotlb=1 root=PARTUUID=${uuid} rw rootwait";
+
+load ${devtype} ${devnum}:1 ${kernel_addr_r} kernel.img
+
+bootm ${kernel_addr_r}
diff --git a/target/linux/rockchip/image/rk3328.bootscript b/target/linux/rockchip/image/rk3328.bootscript
deleted file mode 100644
index 8f961d37329..00000000000
--- a/target/linux/rockchip/image/rk3328.bootscript
+++ /dev/null
@@ -1,7 +0,0 @@
-part uuid mmc ${devnum}:2 uuid
-
-setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff130000 root=PARTUUID=${uuid} rw rootwait"
-
-load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
-
-bootm ${kernel_addr_r}
diff --git a/target/linux/rockchip/image/rk3399.bootscript b/target/linux/rockchip/image/rk3399.bootscript
deleted file mode 100644
index 1e53200027a..00000000000
--- a/target/linux/rockchip/image/rk3399.bootscript
+++ /dev/null
@@ -1,7 +0,0 @@
-part uuid mmc ${devnum}:2 uuid
-
-setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xff1a0000 root=PARTUUID=${uuid} rw rootwait"
-
-load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
-
-bootm ${kernel_addr_r}
diff --git a/target/linux/rockchip/image/rk356x.bootscript b/target/linux/rockchip/image/rk356x.bootscript
deleted file mode 100644
index 3554df06ebe..00000000000
--- a/target/linux/rockchip/image/rk356x.bootscript
+++ /dev/null
@@ -1,7 +0,0 @@
-part uuid mmc ${devnum}:2 uuid
-
-setenv bootargs "console=ttyS2,1500000 earlycon=uart8250,mmio32,0xfe660000 root=PARTUUID=${uuid} rw rootwait"
-
-load mmc ${devnum}:1 ${kernel_addr_r} kernel.img
-
-bootm ${kernel_addr_r}
diff --git a/target/linux/rockchip/patches-6.1/001-dt-bindings-power-supply-define-monitored-battery-in.patch b/target/linux/rockchip/patches-6.1/001-dt-bindings-power-supply-define-monitored-battery-in.patch
new file mode 100644
index 00000000000..8b2d39f4dd3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/001-dt-bindings-power-supply-define-monitored-battery-in.patch
@@ -0,0 +1,132 @@
+From 6ebc33cf772c022b55df081fbb7b63c09861dfe9 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Wed, 2 Nov 2022 14:44:59 -0400
+Subject: [PATCH 001/383] dt-bindings: power: supply: define monitored-battery
+ in common place
+
+Define the type of monitored-battery in power-supply.yaml common schema.
+Reference the schema where applicable to enforce the above in bindings
+which have monitored-battery property.
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/mfd/ene-kb930.yaml        | 6 +++---
+ Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml   | 2 ++
+ Documentation/devicetree/bindings/power/supply/bq27xxx.yaml | 2 --
+ .../devicetree/bindings/power/supply/ingenic,battery.yaml   | 4 ++--
+ .../devicetree/bindings/power/supply/power-supply.yaml      | 6 ++++++
+ .../devicetree/bindings/power/supply/rohm,bd99954.yaml      | 1 +
+ .../devicetree/bindings/power/supply/sc2731-charger.yaml    | 1 -
+ 7 files changed, 14 insertions(+), 8 deletions(-)
+
+--- a/Documentation/devicetree/bindings/mfd/ene-kb930.yaml
++++ b/Documentation/devicetree/bindings/mfd/ene-kb930.yaml
+@@ -13,6 +13,8 @@ description: |
+ maintainers:
+   - Dmitry Osipenko <digetx@gmail.com>
+ 
++$ref: /schemas/power/supply/power-supply.yaml
++
+ properties:
+   compatible:
+     items:
+@@ -22,15 +24,13 @@ properties:
+   reg:
+     maxItems: 1
+ 
+-  monitored-battery: true
+-  power-supplies: true
+   system-power-controller: true
+ 
+ required:
+   - compatible
+   - reg
+ 
+-additionalProperties: false
++unevaluatedProperties: false
+ 
+ examples:
+   - |
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml
+@@ -124,6 +124,8 @@ properties:
+       The child node for the charger to hold additional properties. If a
+       battery is not in use, this node can be omitted.
+     type: object
++    $ref: /schemas/power/supply/power-supply.yaml
++
+     properties:
+       monitored-battery:
+         description: |
+--- a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
++++ b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml
+@@ -60,13 +60,11 @@ properties:
+ 
+   monitored-battery:
+     description: |
+-       phandle of battery characteristics node.
+        The fuel gauge uses the following battery properties:
+        - energy-full-design-microwatt-hours
+        - charge-full-design-microamp-hours
+        - voltage-min-design-microvolt
+        Both or neither of the *-full-design-*-hours properties must be set.
+-       See Documentation/devicetree/bindings/power/supply/battery.yaml
+ 
+   power-supplies: true
+ 
+--- a/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml
++++ b/Documentation/devicetree/bindings/power/supply/ingenic,battery.yaml
+@@ -10,6 +10,8 @@ title: Ingenic JZ47xx battery bindings
+ maintainers:
+   - Artur Rojek <contact@artur-rojek.eu>
+ 
++$ref: power-supply.yaml#
++
+ properties:
+   compatible:
+     oneOf:
+@@ -28,8 +30,6 @@ properties:
+ 
+   monitored-battery:
+     description: >
+-      phandle to a "simple-battery" compatible node.
+-
+       This property must be a phandle to a node using the format described
+       in battery.yaml, with the following properties being required:
+       - voltage-min-design-microvolt: drained battery voltage,
+--- a/Documentation/devicetree/bindings/power/supply/power-supply.yaml
++++ b/Documentation/devicetree/bindings/power/supply/power-supply.yaml
+@@ -18,4 +18,10 @@ properties:
+       This property is added to a supply in order to list the devices which
+       supply it power, referenced by their phandles.
+ 
++  monitored-battery:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      The battery (with "simple-battery" compatible) being monitored by this
++      power supply.
++
+ additionalProperties: true
+--- a/Documentation/devicetree/bindings/power/supply/rohm,bd99954.yaml
++++ b/Documentation/devicetree/bindings/power/supply/rohm,bd99954.yaml
+@@ -18,6 +18,7 @@ description: |
+   provides a Dual-source Battery Charger, two port BC1.2 detection and a
+   Battery Monitor.
+ 
++$ref: power-supply.yaml#
+ 
+ properties:
+   compatible:
+--- a/Documentation/devicetree/bindings/power/supply/sc2731-charger.yaml
++++ b/Documentation/devicetree/bindings/power/supply/sc2731-charger.yaml
+@@ -28,7 +28,6 @@ properties:
+       The charger uses the following battery properties
+       - charge-term-current-microamp: current for charge termination phase.
+       - constant-charge-voltage-max-microvolt: maximum constant input voltage.
+-      See Documentation/devicetree/bindings/power/supply/battery.yaml
+ 
+ additionalProperties: false
+ 
diff --git a/target/linux/rockchip/patches-6.1/002-dt-bindings-arm-rockchip-add-Theobroma-Systems-PX30-.patch b/target/linux/rockchip/patches-6.1/002-dt-bindings-arm-rockchip-add-Theobroma-Systems-PX30-.patch
new file mode 100644
index 00000000000..48c6b58669e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/002-dt-bindings-arm-rockchip-add-Theobroma-Systems-PX30-.patch
@@ -0,0 +1,36 @@
+From e3051061683448b59745ff4e13b900df25f46b8a Mon Sep 17 00:00:00 2001
+From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+Date: Mon, 17 Oct 2022 12:25:25 +0200
+Subject: [PATCH 002/383] =?UTF-8?q?dt-bindings:=20arm:=20rockchip:=20add?=
+ =?UTF-8?q?=20Theobroma=20Systems=20PX30-=C2=B5Q7=20(Ringneck)=20with=20Ha?=
+ =?UTF-8?q?ikou?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add entry for the Theobroma Systems PX30-µQ7 (Ringneck) with Haikou
+devkit.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+Link: https://lore.kernel.org/r/20220930-upstream-ringneck-v2-2-6671694b6934@theobroma-systems.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -709,6 +709,11 @@ properties:
+           - const: rockchip,rv1108-evb
+           - const: rockchip,rv1108
+ 
++      - description: Theobroma Systems PX30-uQ7 with Haikou baseboard
++        items:
++          - const: tsd,px30-ringneck-haikou
++          - const: rockchip,px30
++
+       - description: Theobroma Systems RK3368-uQ7 with Haikou baseboard
+         items:
+           - const: tsd,rk3368-lion-haikou
diff --git a/target/linux/rockchip/patches-6.1/003-dt-bindings-rockchip-Add-Hardkernel-ODROID-M1-board.patch b/target/linux/rockchip/patches-6.1/003-dt-bindings-rockchip-Add-Hardkernel-ODROID-M1-board.patch
new file mode 100644
index 00000000000..c437a93b655
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/003-dt-bindings-rockchip-Add-Hardkernel-ODROID-M1-board.patch
@@ -0,0 +1,33 @@
+From 9523e1eef4b50b1b463855c59033ba1739f19edd Mon Sep 17 00:00:00 2001
+From: Dongjin Kim <tobetter@gmail.com>
+Date: Fri, 30 Sep 2022 07:12:34 +0200
+Subject: [PATCH 003/383] dt-bindings: rockchip: Add Hardkernel ODROID-M1 board
+
+Add device tree binding for Hardkernel ODROID-M1 board based on RK3568
+SoC.
+
+Signed-off-by: Dongjin Kim <tobetter@gmail.com>
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-2-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -468,6 +468,11 @@ properties:
+           - const: hardkernel,rk3326-odroid-go2
+           - const: rockchip,rk3326
+ 
++      - description: Hardkernel Odroid M1
++        items:
++          - const: rockchip,rk3568-odroid-m1
++          - const: rockchip,rk3568
++
+       - description: Hugsun X99 TV Box
+         items:
+           - const: hugsun,x99
diff --git a/target/linux/rockchip/patches-6.1/004-dt-bindings-arm-rockchip-Add-Anbernic-RG353V-and-RG3.patch b/target/linux/rockchip/patches-6.1/004-dt-bindings-arm-rockchip-Add-Anbernic-RG353V-and-RG3.patch
new file mode 100644
index 00000000000..afa5919281d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/004-dt-bindings-arm-rockchip-Add-Anbernic-RG353V-and-RG3.patch
@@ -0,0 +1,36 @@
+From 1ccf8e2e01f9a55cbef202730e6387718cf7808d Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 28 Oct 2022 13:40:42 -0500
+Subject: [PATCH 004/383] dt-bindings: arm: rockchip: Add Anbernic RG353V and
+ RG353VS
+
+Add entry for the Anbernic RG353V and RG353VS handheld devices.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221028184045.13113-2-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 10 ++++++++++
+ 1 file changed, 10 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -35,6 +35,16 @@ properties:
+           - const: anbernic,rg353p
+           - const: rockchip,rk3566
+ 
++      - description: Anbernic RG353V
++        items:
++          - const: anbernic,rg353v
++          - const: rockchip,rk3566
++
++      - description: Anbernic RG353VS
++        items:
++          - const: anbernic,rg353vs
++          - const: rockchip,rk3566
++
+       - description: Anbernic RG503
+         items:
+           - const: anbernic,rg503
diff --git a/target/linux/rockchip/patches-6.1/005-dt-bindings-rockchip-Add-Rockchip-rk3566-box-demo-bo.patch b/target/linux/rockchip/patches-6.1/005-dt-bindings-rockchip-Add-Rockchip-rk3566-box-demo-bo.patch
new file mode 100644
index 00000000000..f353db62601
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/005-dt-bindings-rockchip-Add-Rockchip-rk3566-box-demo-bo.patch
@@ -0,0 +1,31 @@
+From 99b81719685e53c79b7e7d9a1438478332a6f768 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@163.com>
+Date: Sat, 5 Nov 2022 17:59:35 +0800
+Subject: [PATCH 005/383] dt-bindings: rockchip: Add Rockchip rk3566 box demo
+ board
+
+Add device tree binding for Rockchip rk3566 box demo board.
+
+Signed-off-by: Andy Yan <andyshrk@163.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20221105095935.958144-1-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -749,6 +749,11 @@ properties:
+           - const: zkmagic,a95x-z2
+           - const: rockchip,rk3318
+ 
++      - description: Rockchip RK3566 BOX Evaluation Demo board
++        items:
++          - const: rockchip,rk3566-box-demo
++          - const: rockchip,rk3566
++
+       - description: Rockchip RK3568 Evaluation board
+         items:
+           - const: rockchip,rk3568-evb1-v10
diff --git a/target/linux/rockchip/patches-6.1/006-dt-bindings-arm-rockchip-Add-more-RK3326-devices.patch b/target/linux/rockchip/patches-6.1/006-dt-bindings-arm-rockchip-Add-more-RK3326-devices.patch
new file mode 100644
index 00000000000..51f5645ce95
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/006-dt-bindings-arm-rockchip-Add-more-RK3326-devices.patch
@@ -0,0 +1,48 @@
+From 60d361f57be0444462ab9bb55f965672838ac92e Mon Sep 17 00:00:00 2001
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+Date: Thu, 17 Nov 2022 22:59:51 +0100
+Subject: [PATCH 006/383] dt-bindings: arm: rockchip: Add more RK3326 devices
+
+This patch adds Anbernic RG351M, Odroid Go Advance Black Edition and
+Odroid Go Super into dt bindings.
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221117215954.4114202-3-maccraft123mc@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/arm/rockchip.yaml         | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -30,6 +30,11 @@ properties:
+           - const: amarula,vyasa-rk3288
+           - const: rockchip,rk3288
+ 
++      - description: Anbernic RG351M
++        items:
++          - const: anbernic,rg351m
++          - const: rockchip,rk3326
++
+       - description: Anbernic RG353P
+         items:
+           - const: anbernic,rg353p
+@@ -478,6 +483,16 @@ properties:
+           - const: hardkernel,rk3326-odroid-go2
+           - const: rockchip,rk3326
+ 
++      - description: Hardkernel Odroid Go Advance Black Edition
++        items:
++          - const: hardkernel,rk3326-odroid-go2-v11
++          - const: rockchip,rk3326
++
++      - description: Hardkernel Odroid Go Super
++        items:
++          - const: hardkernel,rk3326-odroid-go3
++          - const: rockchip,rk3326
++
+       - description: Hardkernel Odroid M1
+         items:
+           - const: rockchip,rk3568-odroid-m1
diff --git a/target/linux/rockchip/patches-6.1/007-dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch b/target/linux/rockchip/patches-6.1/007-dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch
new file mode 100644
index 00000000000..e010e481716
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/007-dt-bindings-arm-rockchip-Add-SOQuartz-Blade.patch
@@ -0,0 +1,35 @@
+From 9396658a16c03132f65e294bdb3f32a7ca65e60e Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Wed, 16 Nov 2022 12:53:34 +0100
+Subject: [PATCH 007/383] dt-bindings: arm: rockchip: Add SOQuartz Blade
+
+Add a compatible for the SOQuartz Blade base board to the rockchip
+platforms binding.
+
+The SOQuartz Blade is a PoE-capable carrier board for the CM4 SoM
+form factor, designed around the SOQuartz CM4 System-on-Module.
+
+The board features the usual connectivity (GPIO, USB, HDMI,
+Ethernet) and an M.2 slot for SSDs. It may also be powered from
+a 5V barrel jack input, and has a 3.5mm jack for UART debug
+output.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221116115337.541601-2-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -593,6 +593,7 @@ properties:
+       - description: Pine64 SoQuartz SoM
+         items:
+           - enum:
++              - pine64,soquartz-blade
+               - pine64,soquartz-cm4io
+           - const: pine64,soquartz
+           - const: rockchip,rk3566
diff --git a/target/linux/rockchip/patches-6.1/008-dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch b/target/linux/rockchip/patches-6.1/008-dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch
new file mode 100644
index 00000000000..2a40365d127
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/008-dt-bindings-arm-rockchip-Add-SOQuartz-Model-A.patch
@@ -0,0 +1,35 @@
+From d91efae46ee404f042ecc0946028f578370a29fe Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Wed, 16 Nov 2022 12:53:36 +0100
+Subject: [PATCH 008/383] dt-bindings: arm: rockchip: Add SOQuartz Model A
+
+The SOQuartz Model A base board is a carrier board for the CM4
+form factor, designed around the PINE64 SOQuartz CM4 SoM.
+
+The board sports "Model A" dimensions like the Quartz64 Model A,
+but is not to be confused with that.
+
+As for I/O, it features USB 2 ports, Gigabit Ethernet, a PCIe 2
+x1 slot, HDMI, a 40-pin GPIO header, CSI/DSI connectors, an eDP
+flat-flex cable connector, a 12V DC barrel jack for power input
+and power/reset buttons as well as a microSD card slot.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221116115337.541601-4-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -595,6 +595,7 @@ properties:
+           - enum:
+               - pine64,soquartz-blade
+               - pine64,soquartz-cm4io
++              - pine64,soquartz-model-a
+           - const: pine64,soquartz
+           - const: rockchip,rk3566
+ 
diff --git a/target/linux/rockchip/patches-6.1/009-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch b/target/linux/rockchip/patches-6.1/009-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch
new file mode 100644
index 00000000000..aa398e1c1cd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/009-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch
@@ -0,0 +1,42 @@
+From fa400e7c39596815e354dcafd91ae1b39b475975 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 29 Nov 2022 13:24:22 +0530
+Subject: [PATCH 009/383] dt-bindings: arm: rockchip: Add Edgeble Neural
+ Compute Module 2
+
+Neural Compute Module 2(Neu2) is a 96boards SoM-CB compute module
+based on Rockchip RV1126 from Edgeble AI.
+
+Edgeble Neural Compute Module 2(Neu2) IO board is an industrial
+form factor evaluation board from Edgeble AI.
+
+Neu2 needs to mount on top of this IO board in order to create complete
+Edgeble Neural Compute Module 2(Neu2) IO platform.
+
+Add dt-bindings for it.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20221129075424.189655-7-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -90,6 +90,12 @@ properties:
+           - const: chipspark,rayeager-px2
+           - const: rockchip,rk3066a
+ 
++      - description: Edgeble Neural Compute Module 2(Neu2) SoM based boards
++        items:
++          - const: edgeble,neural-compute-module-2-io   # Edgeble Neural Compute Module 2 IO Board
++          - const: edgeble,neural-compute-module-2      # Edgeble Neural Compute Module 2 SoM
++          - const: rockchip,rv1126
++
+       - description: Elgin RV1108 R1
+         items:
+           - const: elgin,rv1108-r1
diff --git a/target/linux/rockchip/patches-6.1/010-dt-bindings-arm-rockchip-Add-Rockchip-RK3128-Evaluat.patch b/target/linux/rockchip/patches-6.1/010-dt-bindings-arm-rockchip-Add-Rockchip-RK3128-Evaluat.patch
new file mode 100644
index 00000000000..17e71c5ecf6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/010-dt-bindings-arm-rockchip-Add-Rockchip-RK3128-Evaluat.patch
@@ -0,0 +1,31 @@
+From de0a4b22124220244b64ea1022f9ad618eca93b2 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Fri, 28 Oct 2022 16:41:12 +0200
+Subject: [PATCH 010/383] dt-bindings: arm: rockchip: Add Rockchip RK3128
+ Evaluation board
+
+Add Rockchip RK3128 Evaluation board.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/dca18633-54d4-1264-725c-213d82fdf1c5@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -695,6 +695,11 @@ properties:
+           - const: rockchip,rk3036-evb
+           - const: rockchip,rk3036
+ 
++      - description: Rockchip RK3128 Evaluation board
++        items:
++          - const: rockchip,rk3128-evb
++          - const: rockchip,rk3128
++
+       - description: Rockchip RK3228 Evaluation board
+         items:
+           - const: rockchip,rk3228-evb
diff --git a/target/linux/rockchip/patches-6.1/011-dt-bindings-arm-rockchip-add-Radxa-CM3I-E25.patch b/target/linux/rockchip/patches-6.1/011-dt-bindings-arm-rockchip-add-Radxa-CM3I-E25.patch
new file mode 100644
index 00000000000..da19698ed7e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/011-dt-bindings-arm-rockchip-add-Radxa-CM3I-E25.patch
@@ -0,0 +1,34 @@
+From 7f988b71a2a982e6cd4ca79d927c9440fe4b9233 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Fri, 9 Dec 2022 18:25:23 +0800
+Subject: [PATCH 011/383] dt-bindings: arm: rockchip: add Radxa CM3I E25
+
+Radxa CM3 Industrial (CM3I) is an System on Module made by Radxa
+based on the Rockchip RK3568 SoC. The first carrier board supported
+is the Radxa E25. Add devicetree binding documentation for it.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20221209102524.129367-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -605,6 +605,13 @@ properties:
+           - const: pine64,soquartz
+           - const: rockchip,rk3566
+ 
++      - description: Radxa CM3 Industrial
++        items:
++          - enum:
++              - radxa,e25
++          - const: radxa,cm3i
++          - const: rockchip,rk3568
++
+       - description: Radxa Rock
+         items:
+           - const: radxa,rock
diff --git a/target/linux/rockchip/patches-6.1/012-dt-bindings-arm-rockchip-Add-EmbedFire-LubanCat-1.patch b/target/linux/rockchip/patches-6.1/012-dt-bindings-arm-rockchip-Add-EmbedFire-LubanCat-1.patch
new file mode 100644
index 00000000000..be0c61ff066
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/012-dt-bindings-arm-rockchip-Add-EmbedFire-LubanCat-1.patch
@@ -0,0 +1,31 @@
+From c6404d82990ac92dfe4a2d3e458e97bdb9c910be Mon Sep 17 00:00:00 2001
+From: Wenhao Cui <lasstp5011@gmail.com>
+Date: Fri, 23 Dec 2022 11:17:18 +0800
+Subject: [PATCH 012/383] dt-bindings: arm: rockchip: Add EmbedFire LubanCat 1
+
+Add devicetree binding documentation for the EmbedFire LubanCat 1.
+
+Signed-off-by: Wenhao Cui <lasstp5011@gmail.com>
+Signed-off-by: Yuteng Zhong <zonyitoo@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/Y6UdvrhLjS0/8Oic@VM-66-53-centos
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -101,6 +101,11 @@ properties:
+           - const: elgin,rv1108-r1
+           - const: rockchip,rv1108
+ 
++      - description: EmbedFire LubanCat 1
++        items:
++          - const: embedfire,lubancat-1
++          - const: rockchip,rk3566
++
+       - description: Engicam PX30.Core C.TOUCH 2.0
+         items:
+           - const: engicam,px30-core-ctouch2
diff --git a/target/linux/rockchip/patches-6.1/013-dt-bindings-arm-rockchip-Add-EmbedFire-LubanCat-2.patch b/target/linux/rockchip/patches-6.1/013-dt-bindings-arm-rockchip-Add-EmbedFire-LubanCat-2.patch
new file mode 100644
index 00000000000..01c700840c2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/013-dt-bindings-arm-rockchip-Add-EmbedFire-LubanCat-2.patch
@@ -0,0 +1,30 @@
+From 9fd72e168c45bb5b974146f75de0fcfe7cd30177 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@163.com>
+Date: Sun, 8 Jan 2023 19:07:42 +0800
+Subject: [PATCH 013/383] dt-bindings: arm: rockchip: Add EmbedFire LubanCat 2
+
+Add EmbedFire LubanCat 2
+
+Signed-off-by: Andy Yan <andyshrk@163.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230108110742.2214800-1-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -106,6 +106,11 @@ properties:
+           - const: embedfire,lubancat-1
+           - const: rockchip,rk3566
+ 
++      - description: EmbedFire LubanCat 2
++        items:
++          - const: embedfire,lubancat-2
++          - const: rockchip,rk3568
++
+       - description: Engicam PX30.Core C.TOUCH 2.0
+         items:
+           - const: engicam,px30-core-ctouch2
diff --git a/target/linux/rockchip/patches-6.1/014-dt-bindings-arm-rockchip-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-6.1/014-dt-bindings-arm-rockchip-Add-Orange-Pi-R1-Plus.patch
new file mode 100644
index 00000000000..d27251e1b92
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/014-dt-bindings-arm-rockchip-Add-Orange-Pi-R1-Plus.patch
@@ -0,0 +1,30 @@
+From 270210c74ba803d86f4084bb3d29b56aa49dfa58 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sat, 3 Dec 2022 15:41:48 +0800
+Subject: [PATCH 014/383] dt-bindings: arm: rockchip: Add Orange Pi R1 Plus
+
+Add devicetree binding documentation for the Orange Pi R1 Plus.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221203074149.11543-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -789,6 +789,11 @@ properties:
+           - const: tronsmart,orion-r68-meta
+           - const: rockchip,rk3368
+ 
++      - description: Xunlong Orange Pi R1 Plus
++        items:
++          - const: xunlong,orangepi-r1-plus
++          - const: rockchip,rk3328
++
+       - description: Zkmagic A95X Z2
+         items:
+           - const: zkmagic,a95x-z2
diff --git a/target/linux/rockchip/patches-6.1/015-dt-bindings-arm-rockchip-add-initial-rk3588-boards.patch b/target/linux/rockchip/patches-6.1/015-dt-bindings-arm-rockchip-add-initial-rk3588-boards.patch
new file mode 100644
index 00000000000..acf69a29a87
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/015-dt-bindings-arm-rockchip-add-initial-rk3588-boards.patch
@@ -0,0 +1,51 @@
+From 86671c62988ab6ac169e8f2350a370a1a0fa400d Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 9 Jan 2023 16:57:58 +0100
+Subject: [PATCH 015/383] dt-bindings: arm: rockchip: add initial rk3588 boards
+
+Add DT binding documentation for the Rockchip RK3588 EVB1,
+Radxa Rock 5 Model A and B.
+
+Co-Developed-by: Christopher Obbard <chris.obbard@collabora.com>
+Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230109155801.51642-5-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/arm/rockchip.yaml         | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -675,6 +675,16 @@ properties:
+           - const: radxa,rock3a
+           - const: rockchip,rk3568
+ 
++      - description: Radxa ROCK 5 Model A
++        items:
++          - const: radxa,rock-5a
++          - const: rockchip,rk3588s
++
++      - description: Radxa ROCK 5 Model B
++        items:
++          - const: radxa,rock-5b
++          - const: rockchip,rk3588
++
+       - description: Rikomagic MK808 v1
+         items:
+           - const: rikomagic,mk808
+@@ -764,6 +774,11 @@ properties:
+           - const: rockchip,rk3399-sapphire-excavator
+           - const: rockchip,rk3399
+ 
++      - description: Rockchip RK3588 Evaluation board
++        items:
++          - const: rockchip,rk3588-evb1-v10
++          - const: rockchip,rk3588
++
+       - description: Rockchip RV1108 Evaluation board
+         items:
+           - const: rockchip,rv1108-evb
diff --git a/target/linux/rockchip/patches-6.1/016-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch b/target/linux/rockchip/patches-6.1/016-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch
new file mode 100644
index 00000000000..b8e25fae7e1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/016-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch
@@ -0,0 +1,41 @@
+From eda2c77e5dcd500c548f183e0c1a652d28919c64 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 10 Jan 2023 19:16:56 +0530
+Subject: [PATCH 016/383] dt-bindings: arm: rockchip: Add Edgeble Neural
+ Compute Module 6
+
+Neural Compute Module 6(Neu6) is a 96boards SoM-CB compute module
+based on Rockchip RK3588 from Edgeble AI.
+
+Edgeble Neural Compute Module 6(Neu6) IO board is an industrial
+form factor evaluation board from Edgeble AI.
+
+Neu6 needs to mount on top of this IO board in order to create complete
+Edgeble Neural Compute Module 6(Neu6) IO platform.
+
+This patch add dt-bindings for Edgeble Neu6 Model A SoM based IO board.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230110134658.820691-1-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -96,6 +96,12 @@ properties:
+           - const: edgeble,neural-compute-module-2      # Edgeble Neural Compute Module 2 SoM
+           - const: rockchip,rv1126
+ 
++      - description: Edgeble Neural Compute Module 6(Neu6) Model A SoM based boards
++        items:
++          - const: edgeble,neural-compute-module-6a-io  # Edgeble Neural Compute Module 6A IO Board
++          - const: edgeble,neural-compute-module-6a     # Edgeble Neural Compute Module 6A SoM
++          - const: rockchip,rk3588
++
+       - description: Elgin RV1108 R1
+         items:
+           - const: elgin,rv1108-r1
diff --git a/target/linux/rockchip/patches-6.1/017-dt-bindings-arm-rockchip-Add-Radxa-Compute-Module-3.patch b/target/linux/rockchip/patches-6.1/017-dt-bindings-arm-rockchip-Add-Radxa-Compute-Module-3.patch
new file mode 100644
index 00000000000..d198ec4cbc0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/017-dt-bindings-arm-rockchip-Add-Radxa-Compute-Module-3.patch
@@ -0,0 +1,45 @@
+From fc0d6f4066c27c889aac7817927daafe039391db Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Thu, 12 Jan 2023 16:29:00 +0530
+Subject: [PATCH 017/383] dt-bindings: arm: rockchip: Add Radxa Compute Module
+ 3
+
+Radxa Compute Module 3(CM3) is one of the modules from a series
+System On Module based on the Radxa ROCK 3 series and is compatible
+with Raspberry Pi CM4 in pinout and form factor.
+
+Specification:
+- Rockchip RK3566
+- up to 8GB LPDDR4
+- up to 128GB high performance eMMC
+- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
+  BT 5.0, BLE with onboard and external antenna.
+- Gigabit Ethernet PHY
+
+Add dt-bindings for Radxa CM3.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230112105902.192852-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -621,6 +621,13 @@ properties:
+           - const: pine64,soquartz
+           - const: rockchip,rk3566
+ 
++      - description: Radxa Compute Module 3(CM3)
++        items:
++          - enum:
++              - radxa,radxa-cm3-io
++          - const: radxa,radxa-cm3
++          - const: rockchip,rk3566
++
+       - description: Radxa CM3 Industrial
+         items:
+           - enum:
diff --git a/target/linux/rockchip/patches-6.1/018-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/018-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
new file mode 100644
index 00000000000..7dc5ec32e43
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/018-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
@@ -0,0 +1,36 @@
+From 47b85bf0debfdbfaaf70e9c0d9cb7dee49324415 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Mon, 23 Jan 2023 12:46:50 +0530
+Subject: [PATCH 018/383] arm64: dts: rockchip: Fix compatible for Radxa CM3
+
+The compatible string "radxa,radxa-cm3" referring the product name
+as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
+
+Fix the compatible strings.
+
+Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
+Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
+Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
+Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -624,8 +624,8 @@ properties:
+       - description: Radxa Compute Module 3(CM3)
+         items:
+           - enum:
+-              - radxa,radxa-cm3-io
+-          - const: radxa,radxa-cm3
++              - radxa,cm3-io
++          - const: radxa,cm3
+           - const: rockchip,rk3566
+ 
+       - description: Radxa CM3 Industrial
diff --git a/target/linux/rockchip/patches-6.1/019-dt-bindings-arm-rockchip-Add-Khadas-Edge2-board.patch b/target/linux/rockchip/patches-6.1/019-dt-bindings-arm-rockchip-Add-Khadas-Edge2-board.patch
new file mode 100644
index 00000000000..421d75540d7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/019-dt-bindings-arm-rockchip-Add-Khadas-Edge2-board.patch
@@ -0,0 +1,45 @@
+From 8ef1c5a3849ff657f68053d70f51bc12062deb9a Mon Sep 17 00:00:00 2001
+From: Yixun Lan <dlan@gentoo.org>
+Date: Wed, 15 Mar 2023 11:34:40 +0800
+Subject: [PATCH 019/383] dt-bindings: arm: rockchip: Add Khadas Edge2 board
+
+Edge2 is an ultraslim, credit-card sized ARM PC designed by Khadas.
+It has quite a few rich peripherals.
+
+Specification:
+- Rockchip RK3588s
+- 8/16GB LPDDR4
+- 32/64GB eMMC 5.1
+- AP6275P WiFi6 LAN
+- HDMI2.1 Type-A
+- MIPI-CSI x3
+- MIPI-DSI x2
+- usb3.1; usb2.0
+- RTC clock
+- PWM fan
+- SPI Flash
+- Pads expansion board (UART, USB)
+
+Signed-off-by: Yixun Lan <dlan@gentoo.org>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230315033441.32719-2-dlan@gentoo.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -533,6 +533,11 @@ properties:
+               - khadas,edge-v
+           - const: rockchip,rk3399
+ 
++      - description: Khadas Edge2 series boards
++        items:
++          - const: khadas,edge2
++          - const: rockchip,rk3588s
++
+       - description: Kobol Helios64
+         items:
+           - const: kobol,helios64
diff --git a/target/linux/rockchip/patches-6.1/020-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/020-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R5S.patch
new file mode 100644
index 00000000000..26c71b82a5a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/020-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R5S.patch
@@ -0,0 +1,30 @@
+From 07eb6f2a8b4ac909c4f0c9c7fa06d5971f6eaa41 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Tue, 7 Mar 2023 22:32:39 -0800
+Subject: [PATCH 020/383] dt-bindings: Add doc for FriendlyARM NanoPi R5S
+
+Add devicetree binding documentation for the FriendlyARM NanoPi R5S.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230308063240.107178-1-anarsoul@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -201,6 +201,11 @@ properties:
+               - friendlyarm,nanopi-r4s-enterprise
+           - const: rockchip,rk3399
+ 
++      - description: FriendlyElec NanoPi R5S board
++        items:
++          - const: friendlyarm,nanopi-r5s
++          - const: rockchip,rk3568
++
+       - description: GeekBuying GeekBox
+         items:
+           - const: geekbuying,geekbox
diff --git a/target/linux/rockchip/patches-6.1/021-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R5C.patch b/target/linux/rockchip/patches-6.1/021-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R5C.patch
new file mode 100644
index 00000000000..0cc79c62cc9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/021-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R5C.patch
@@ -0,0 +1,32 @@
+From 471052987584a54a8b24c3b79d0fb7d75faf225c Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 18 Mar 2023 16:37:42 +0800
+Subject: [PATCH 021/383] dt-bindings: Add doc for FriendlyARM NanoPi R5C
+
+Add devicetree binding documentation for the FriendlyARM NanoPi R5C.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230318083745.6181-3-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -201,9 +201,11 @@ properties:
+               - friendlyarm,nanopi-r4s-enterprise
+           - const: rockchip,rk3399
+ 
+-      - description: FriendlyElec NanoPi R5S board
++      - description: FriendlyElec NanoPi R5 series boards
+         items:
+-          - const: friendlyarm,nanopi-r5s
++          - enum:
++              - friendlyarm,nanopi-r5c
++              - friendlyarm,nanopi-r5s
+           - const: rockchip,rk3568
+ 
+       - description: GeekBuying GeekBox
diff --git a/target/linux/rockchip/patches-6.1/022-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R2C.patch b/target/linux/rockchip/patches-6.1/022-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R2C.patch
new file mode 100644
index 00000000000..4e0348e5752
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/022-dt-bindings-Add-doc-for-FriendlyARM-NanoPi-R2C.patch
@@ -0,0 +1,33 @@
+From 5baa5279482d86b6eece6b50f2d6f153a94a26db Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 25 Mar 2023 15:40:19 +0800
+Subject: [PATCH 022/383] dt-bindings: Add doc for FriendlyARM NanoPi R2C
+
+Add devicetree binding documentation for the FriendlyARM NanoPi R2C.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
+Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
+Link: https://lore.kernel.org/r/20230325074022.9818-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -185,9 +185,11 @@ properties:
+           - const: firefly,rk3566-roc-pc
+           - const: rockchip,rk3566
+ 
+-      - description: FriendlyElec NanoPi R2S
++      - description: FriendlyElec NanoPi R2 series boards
+         items:
+-          - const: friendlyarm,nanopi-r2s
++          - enum:
++              - friendlyarm,nanopi-r2c
++              - friendlyarm,nanopi-r2s
+           - const: rockchip,rk3328
+ 
+       - description: FriendlyElec NanoPi4 series boards
diff --git a/target/linux/rockchip/patches-6.1/023-dt-bindings-Add-doc-for-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-6.1/023-dt-bindings-Add-doc-for-Xunlong-OrangePi-R1-Plus-LTS.patch
new file mode 100644
index 00000000000..b0fad9b4ce5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/023-dt-bindings-Add-doc-for-Xunlong-OrangePi-R1-Plus-LTS.patch
@@ -0,0 +1,33 @@
+From 9eff27c2f0184b57adf29646fcbe9d963ce6acb1 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 25 Mar 2023 15:40:21 +0800
+Subject: [PATCH 023/383] dt-bindings: Add doc for Xunlong OrangePi R1 Plus LTS
+
+Add devicetree binding documentation for the
+Xunlong OrangePi R1 Plus LTS.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
+Link: https://lore.kernel.org/r/20230325074022.9818-4-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
+ 1 file changed, 4 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -831,9 +831,11 @@ properties:
+           - const: tronsmart,orion-r68-meta
+           - const: rockchip,rk3368
+ 
+-      - description: Xunlong Orange Pi R1 Plus
++      - description: Xunlong Orange Pi R1 Plus / LTS
+         items:
+-          - const: xunlong,orangepi-r1-plus
++          - enum:
++              - xunlong,orangepi-r1-plus
++              - xunlong,orangepi-r1-plus-lts
+           - const: rockchip,rk3328
+ 
+       - description: Zkmagic A95X Z2
diff --git a/target/linux/rockchip/patches-6.1/024-dt-bindings-Add-doc-for-Fastrhino-R66S-R68S.patch b/target/linux/rockchip/patches-6.1/024-dt-bindings-Add-doc-for-Fastrhino-R66S-R68S.patch
new file mode 100644
index 00000000000..c3f927ed435
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/024-dt-bindings-Add-doc-for-Fastrhino-R66S-R68S.patch
@@ -0,0 +1,33 @@
+From 2366f205784eef0093200b38f6f225681aa17bd9 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 6 May 2023 14:11:06 +0800
+Subject: [PATCH 024/383] dt-bindings: Add doc for Fastrhino R66S / R68S
+
+Add devicetree binding documentation for the
+Lunzn Fastrhino R66S and R68S boards.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230506061108.17658-1-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -562,6 +562,13 @@ properties:
+           - const: leez,p710
+           - const: rockchip,rk3399
+ 
++      - description: Lunzn FastRhino R66S / R68S
++        items:
++          - enum:
++              - lunzn,fastrhino-r66s
++              - lunzn,fastrhino-r68s
++          - const: rockchip,rk3568
++
+       - description: mqmaker MiQi
+         items:
+           - const: mqmaker,miqi
diff --git a/target/linux/rockchip/patches-6.1/025-dt-bindings-arm-rockchip-add-Anbernic-RG353PS.patch b/target/linux/rockchip/patches-6.1/025-dt-bindings-arm-rockchip-add-Anbernic-RG353PS.patch
new file mode 100644
index 00000000000..3c01bd2b85d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/025-dt-bindings-arm-rockchip-add-Anbernic-RG353PS.patch
@@ -0,0 +1,34 @@
+From ed65d658e77c0f076699ef1dd623012f27138fc6 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 12 May 2023 11:20:38 -0500
+Subject: [PATCH 025/383] dt-bindings: arm: rockchip: add Anbernic RG353PS
+
+Add devicetree binding for Anbernic RG353PS. This device is identical
+to the RG353P, except it does not have a touchscreen, does not have
+an eMMC, only includes 1GB of RAM, and ships with only the 2nd
+revision panel based on a Sitronix ST7703 controller. Support for the
+panel has been added in a separate commit.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230512162039.31132-2-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -40,6 +40,11 @@ properties:
+           - const: anbernic,rg353p
+           - const: rockchip,rk3566
+ 
++      - description: Anbernic RG353PS
++        items:
++          - const: anbernic,rg353ps
++          - const: rockchip,rk3566
++
+       - description: Anbernic RG353V
+         items:
+           - const: anbernic,rg353v
diff --git a/target/linux/rockchip/patches-6.1/026-dt-bindings-arm-rockchip-add-FriendlyARM-NanoPi-R2C-.patch b/target/linux/rockchip/patches-6.1/026-dt-bindings-arm-rockchip-add-FriendlyARM-NanoPi-R2C-.patch
new file mode 100644
index 00000000000..a170404f753
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/026-dt-bindings-arm-rockchip-add-FriendlyARM-NanoPi-R2C-.patch
@@ -0,0 +1,27 @@
+From eb4c6280f091f1482bc942543e11978023ffb860 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 13 May 2023 21:53:06 +0800
+Subject: [PATCH 026/383] dt-bindings: arm: rockchip: add FriendlyARM NanoPi
+ R2C Plus
+
+Add devicetree binding documentation for the NanoPi R2C Plus.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230513135307.26554-1-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -194,6 +194,7 @@ properties:
+         items:
+           - enum:
+               - friendlyarm,nanopi-r2c
++              - friendlyarm,nanopi-r2c-plus
+               - friendlyarm,nanopi-r2s
+           - const: rockchip,rk3328
+ 
diff --git a/target/linux/rockchip/patches-6.1/027-mailbox-rockchip-Use-device_get_match_data-to-simpli.patch b/target/linux/rockchip/patches-6.1/027-mailbox-rockchip-Use-device_get_match_data-to-simpli.patch
new file mode 100644
index 00000000000..877434acf08
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/027-mailbox-rockchip-Use-device_get_match_data-to-simpli.patch
@@ -0,0 +1,35 @@
+From c462adaba3027526bac3ef4f759c6af3198e0aea Mon Sep 17 00:00:00 2001
+From: ye xingchen <ye.xingchen@zte.com.cn>
+Date: Thu, 17 Nov 2022 19:29:11 +0800
+Subject: [PATCH 027/383] mailbox: rockchip: Use device_get_match_data() to
+ simplify the code
+
+Directly get the match data with device_get_match_data().
+
+Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
+Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mailbox/rockchip-mailbox.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/mailbox/rockchip-mailbox.c
++++ b/drivers/mailbox/rockchip-mailbox.c
+@@ -164,7 +164,6 @@ MODULE_DEVICE_TABLE(of, rockchp_mbox_of_
+ static int rockchip_mbox_probe(struct platform_device *pdev)
+ {
+ 	struct rockchip_mbox *mb;
+-	const struct of_device_id *match;
+ 	const struct rockchip_mbox_data *drv_data;
+ 	struct resource *res;
+ 	int ret, irq, i;
+@@ -172,8 +171,7 @@ static int rockchip_mbox_probe(struct pl
+ 	if (!pdev->dev.of_node)
+ 		return -ENODEV;
+ 
+-	match = of_match_node(rockchip_mbox_of_match, pdev->dev.of_node);
+-	drv_data = (const struct rockchip_mbox_data *)match->data;
++	drv_data = (const struct rockchip_mbox_data *) device_get_match_data(&pdev->dev);
+ 
+ 	mb = devm_kzalloc(&pdev->dev, sizeof(*mb), GFP_KERNEL);
+ 	if (!mb)
diff --git a/target/linux/rockchip/patches-6.1/028-mailbox-rockchip-remove-MODULE_LICENSE-in-non-module.patch b/target/linux/rockchip/patches-6.1/028-mailbox-rockchip-remove-MODULE_LICENSE-in-non-module.patch
new file mode 100644
index 00000000000..7f3ed88185a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/028-mailbox-rockchip-remove-MODULE_LICENSE-in-non-module.patch
@@ -0,0 +1,42 @@
+From 1b4ad47fe5b9952fe49c7f3aef9cc29cac1d46d4 Mon Sep 17 00:00:00 2001
+From: Nick Alcock <nick.alcock@oracle.com>
+Date: Tue, 7 Mar 2023 18:01:40 +0000
+Subject: [PATCH 028/383] mailbox: rockchip: remove MODULE_LICENSE in
+ non-modules
+
+Since commit 8b41fc4454e ("kbuild: create modules.builtin without
+Makefile.modbuiltin or tristate.conf"), MODULE_LICENSE declarations
+are used to identify modules. As a consequence, uses of the macro
+in non-modules will cause modprobe to misidentify their containing
+object file as a module when it is not (false positives), and modprobe
+might succeed rather than failing with a suitable error message.
+
+So remove it in the files in this commit, none of which can be built as
+modules.
+
+Signed-off-by: Nick Alcock <nick.alcock@oracle.com>
+Suggested-by: Luis Chamberlain <mcgrof@kernel.org>
+Cc: Luis Chamberlain <mcgrof@kernel.org>
+Cc: linux-modules@vger.kernel.org
+Cc: linux-kernel@vger.kernel.org
+Cc: Hitomi Hasegawa <hasegawa-hitomi@fujitsu.com>
+Cc: Jassi Brar <jassisinghbrar@gmail.com>
+Cc: Heiko Stuebner <heiko@sntech.de>
+Cc: linux-arm-kernel@lists.infradead.org
+Cc: linux-rockchip@lists.infradead.org
+Signed-off-by: Luis Chamberlain <mcgrof@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mailbox/rockchip-mailbox.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/mailbox/rockchip-mailbox.c
++++ b/drivers/mailbox/rockchip-mailbox.c
+@@ -254,7 +254,6 @@ static struct platform_driver rockchip_m
+ 
+ module_platform_driver(rockchip_mbox_driver);
+ 
+-MODULE_LICENSE("GPL v2");
+ MODULE_DESCRIPTION("Rockchip mailbox: communicate between CPU cores and MCU");
+ MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
+ MODULE_AUTHOR("Caesar Wang <wxt@rock-chips.com>");
diff --git a/target/linux/rockchip/patches-6.1/029-mailbox-rockchip-drop-of_match_ptr-for-ID-table.patch b/target/linux/rockchip/patches-6.1/029-mailbox-rockchip-drop-of_match_ptr-for-ID-table.patch
new file mode 100644
index 00000000000..f85f9441f97
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/029-mailbox-rockchip-drop-of_match_ptr-for-ID-table.patch
@@ -0,0 +1,32 @@
+From 2b4ce6a535954f3020c820fdf492f007ef1db43e Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sat, 11 Mar 2023 12:17:38 +0100
+Subject: [PATCH 029/383] mailbox: rockchip: drop of_match_ptr for ID table
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The driver can match only via the DT table so the table should be always
+used and the of_match_ptr does not have any sense (this also allows ACPI
+matching via PRP0001, even though it might not be relevant here).
+
+  drivers/mailbox/rockchip-mailbox.c:158:34: error: ‘rockchip_mbox_of_match’ defined but not used [-Werror=unused-const-variable=]
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mailbox/rockchip-mailbox.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mailbox/rockchip-mailbox.c
++++ b/drivers/mailbox/rockchip-mailbox.c
+@@ -248,7 +248,7 @@ static struct platform_driver rockchip_m
+ 	.probe	= rockchip_mbox_probe,
+ 	.driver = {
+ 		.name = "rockchip-mailbox",
+-		.of_match_table = of_match_ptr(rockchip_mbox_of_match),
++		.of_match_table = rockchip_mbox_of_match,
+ 	},
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/030-PCI-Remove-unnecessary-linux-of_irq.h-includes.patch b/target/linux/rockchip/patches-6.1/030-PCI-Remove-unnecessary-linux-of_irq.h-includes.patch
new file mode 100644
index 00000000000..e49d44301cc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/030-PCI-Remove-unnecessary-linux-of_irq.h-includes.patch
@@ -0,0 +1,147 @@
+From 7a62decb761a8a2b8bef955090e70aff5a6a9878 Mon Sep 17 00:00:00 2001
+From: Bjorn Helgaas <bhelgaas@google.com>
+Date: Mon, 31 Oct 2022 10:39:54 -0500
+Subject: [PATCH 030/383] PCI: Remove unnecessary <linux/of_irq.h> includes
+
+Many host controller drivers #include <linux/of_irq.h> even though they
+don't need it.  Remove the unnecessary #includes.
+
+Link: https://lore.kernel.org/r/20221031153954.1163623-6-helgaas@kernel.org
+Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
+Acked-by: Roy Zang <roy.zang@nxp.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/pci/controller/cadence/pci-j721e.c   | 1 -
+ drivers/pci/controller/dwc/pci-layerscape.c  | 1 -
+ drivers/pci/controller/dwc/pcie-armada8k.c   | 1 -
+ drivers/pci/controller/dwc/pcie-tegra194.c   | 1 -
+ drivers/pci/controller/pci-v3-semi.c         | 1 -
+ drivers/pci/controller/pcie-altera-msi.c     | 1 -
+ drivers/pci/controller/pcie-iproc-platform.c | 1 -
+ drivers/pci/controller/pcie-iproc.c          | 1 -
+ drivers/pci/controller/pcie-microchip-host.c | 1 -
+ drivers/pci/controller/pcie-rockchip-host.c  | 1 -
+ drivers/pci/controller/pcie-xilinx-cpm.c     | 1 -
+ drivers/pci/controller/pcie-xilinx-nwl.c     | 1 -
+ 12 files changed, 12 deletions(-)
+
+--- a/drivers/pci/controller/cadence/pci-j721e.c
++++ b/drivers/pci/controller/cadence/pci-j721e.c
+@@ -15,7 +15,6 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+-#include <linux/of_irq.h>
+ #include <linux/pci.h>
+ #include <linux/pm_runtime.h>
+ #include <linux/regmap.h>
+--- a/drivers/pci/controller/dwc/pci-layerscape.c
++++ b/drivers/pci/controller/dwc/pci-layerscape.c
+@@ -13,7 +13,6 @@
+ #include <linux/init.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_address.h>
+ #include <linux/pci.h>
+ #include <linux/platform_device.h>
+--- a/drivers/pci/controller/dwc/pcie-armada8k.c
++++ b/drivers/pci/controller/dwc/pcie-armada8k.c
+@@ -21,7 +21,6 @@
+ #include <linux/platform_device.h>
+ #include <linux/resource.h>
+ #include <linux/of_pci.h>
+-#include <linux/of_irq.h>
+ 
+ #include "pcie-designware.h"
+ 
+--- a/drivers/pci/controller/dwc/pcie-tegra194.c
++++ b/drivers/pci/controller/dwc/pcie-tegra194.c
+@@ -22,7 +22,6 @@
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/of_gpio.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/pci.h>
+ #include <linux/phy/phy.h>
+--- a/drivers/pci/controller/pci-v3-semi.c
++++ b/drivers/pci/controller/pci-v3-semi.c
+@@ -22,7 +22,6 @@
+ #include <linux/kernel.h>
+ #include <linux/of_address.h>
+ #include <linux/of_device.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/pci.h>
+ #include <linux/platform_device.h>
+--- a/drivers/pci/controller/pcie-altera-msi.c
++++ b/drivers/pci/controller/pcie-altera-msi.c
+@@ -13,7 +13,6 @@
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_address.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/pci.h>
+ #include <linux/platform_device.h>
+--- a/drivers/pci/controller/pcie-iproc-platform.c
++++ b/drivers/pci/controller/pcie-iproc-platform.c
+@@ -12,7 +12,6 @@
+ #include <linux/platform_device.h>
+ #include <linux/of_address.h>
+ #include <linux/of_pci.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_platform.h>
+ #include <linux/phy/phy.h>
+ 
+--- a/drivers/pci/controller/pcie-iproc.c
++++ b/drivers/pci/controller/pcie-iproc.c
+@@ -18,7 +18,6 @@
+ #include <linux/platform_device.h>
+ #include <linux/of_address.h>
+ #include <linux/of_pci.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_platform.h>
+ #include <linux/phy/phy.h>
+ 
+--- a/drivers/pci/controller/pcie-microchip-host.c
++++ b/drivers/pci/controller/pcie-microchip-host.c
+@@ -12,7 +12,6 @@
+ #include <linux/module.h>
+ #include <linux/msi.h>
+ #include <linux/of_address.h>
+-#include <linux/of_irq.h>
+ #include <linux/of_pci.h>
+ #include <linux/pci-ecam.h>
+ #include <linux/platform_device.h>
+--- a/drivers/pci/controller/pcie-rockchip-host.c
++++ b/drivers/pci/controller/pcie-rockchip-host.c
+@@ -28,7 +28,6 @@
+ #include <linux/of_device.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+-#include <linux/of_irq.h>
+ #include <linux/pci.h>
+ #include <linux/pci_ids.h>
+ #include <linux/phy/phy.h>
+--- a/drivers/pci/controller/pcie-xilinx-cpm.c
++++ b/drivers/pci/controller/pcie-xilinx-cpm.c
+@@ -16,7 +16,6 @@
+ #include <linux/of_address.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+-#include <linux/of_irq.h>
+ #include <linux/pci.h>
+ #include <linux/platform_device.h>
+ #include <linux/pci-ecam.h>
+--- a/drivers/pci/controller/pcie-xilinx-nwl.c
++++ b/drivers/pci/controller/pcie-xilinx-nwl.c
+@@ -17,7 +17,6 @@
+ #include <linux/of_address.h>
+ #include <linux/of_pci.h>
+ #include <linux/of_platform.h>
+-#include <linux/of_irq.h>
+ #include <linux/pci.h>
+ #include <linux/pci-ecam.h>
+ #include <linux/platform_device.h>
diff --git a/target/linux/rockchip/patches-6.1/035-phy-rockchip-pcie-remove-unused-phy_rd_cfg-function.patch b/target/linux/rockchip/patches-6.1/035-phy-rockchip-pcie-remove-unused-phy_rd_cfg-function.patch
new file mode 100644
index 00000000000..be9ee6c67c5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/035-phy-rockchip-pcie-remove-unused-phy_rd_cfg-function.patch
@@ -0,0 +1,44 @@
+From da4893fdb2b1927b303625ddc13f630f69aa621f Mon Sep 17 00:00:00 2001
+From: Tom Rix <trix@redhat.com>
+Date: Tue, 21 Mar 2023 08:25:03 -0400
+Subject: [PATCH 035/383] phy: rockchip-pcie: remove unused phy_rd_cfg function
+
+clang with W=1 reports
+drivers/phy/rockchip/phy-rockchip-pcie.c:122:19: error:
+  unused function 'phy_rd_cfg' [-Werror,-Wunused-function]
+static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
+                  ^
+This function is not used, so remove it.
+
+Signed-off-by: Tom Rix <trix@redhat.com>
+Link: https://lore.kernel.org/r/20230321122503.1783311-1-trix@redhat.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-pcie.c | 15 ---------------
+ 1 file changed, 15 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-pcie.c
++++ b/drivers/phy/rockchip/phy-rockchip-pcie.c
+@@ -119,21 +119,6 @@ static inline void phy_wr_cfg(struct roc
+ 				   PHY_CFG_WR_SHIFT));
+ }
+ 
+-static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
+-			     u32 addr)
+-{
+-	u32 val;
+-
+-	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
+-		     HIWORD_UPDATE(addr,
+-				   PHY_CFG_RD_MASK,
+-				   PHY_CFG_ADDR_SHIFT));
+-	regmap_read(rk_phy->reg_base,
+-		    rk_phy->phy_data->pcie_status,
+-		    &val);
+-	return val;
+-}
+-
+ static int rockchip_pcie_phy_power_off(struct phy *phy)
+ {
+ 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
diff --git a/target/linux/rockchip/patches-6.1/036-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/036-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch
new file mode 100644
index 00000000000..3706fc0f5a8
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/036-phy-rockchip-Add-naneng-combo-phy-support-for-RK3588.patch
@@ -0,0 +1,234 @@
+From 00429c37494fa01fef2b9ae9550d3b2da81a65f6 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 14 Mar 2023 13:55:55 +0000
+Subject: [PATCH 036/383] phy: rockchip: Add naneng combo phy support for
+ RK3588
+
+Add support for RK3588 combo phy
+
+This is based on prior work from XiaoDong Huang and
+Peter Geis fixing this issue specifically for Rockchip 356x.
+
+Co-developed-by: Andrew Powers-Holmes <aholmes@omnom.net>
+Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Link: https://lore.kernel.org/r/20230314135555.44162-4-lucas.tanure@collabora.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../rockchip/phy-rockchip-naneng-combphy.c    | 184 ++++++++++++++++++
+ 1 file changed, 184 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-naneng-combphy.c
+@@ -63,6 +63,9 @@
+ #define PHYREG18			0x44
+ #define PHYREG18_PLL_LOOP		0x32
+ 
++#define PHYREG27			0x6C
++#define PHYREG27_RX_TRIM_RK3588		0x4C
++
+ #define PHYREG32			0x7C
+ #define PHYREG32_SSC_MASK		GENMASK(7, 4)
+ #define PHYREG32_SSC_DIR_SHIFT		4
+@@ -114,7 +117,10 @@ struct rockchip_combphy_grfcfg {
+ 	struct combphy_reg con2_for_sata;
+ 	struct combphy_reg con3_for_sata;
+ 	struct combphy_reg pipe_con0_for_sata;
++	struct combphy_reg pipe_con1_for_sata;
+ 	struct combphy_reg pipe_xpcs_phy_ready;
++	struct combphy_reg pipe_pcie1l0_sel;
++	struct combphy_reg pipe_pcie1l1_sel;
+ };
+ 
+ struct rockchip_combphy_cfg {
+@@ -559,11 +565,189 @@ static const struct rockchip_combphy_cfg
+ 	.combphy_cfg	= rk3568_combphy_cfg,
+ };
+ 
++static int rk3588_combphy_cfg(struct rockchip_combphy_priv *priv)
++{
++	const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg;
++	unsigned long rate;
++	u32 val;
++
++	switch (priv->type) {
++	case PHY_TYPE_PCIE:
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true);
++		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l0_sel, true);
++		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_pcie1l1_sel, true);
++		break;
++	case PHY_TYPE_USB3:
++		/* Set SSC downward spread spectrum */
++		rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK,
++					 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT,
++					 PHYREG32);
++
++		/* Enable adaptive CTLE for USB3.0 Rx. */
++		val = readl(priv->mmio + PHYREG15);
++		val |= PHYREG15_CTLE_EN;
++		writel(val, priv->mmio + PHYREG15);
++
++		/* Set PLL KVCO fine tuning signals. */
++		rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
++					 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT,
++					 PHYREG33);
++
++		/* Enable controlling random jitter. */
++		writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++
++		/* Set PLL input clock divider 1/2. */
++		rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK,
++					 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT,
++					 PHYREG6);
++
++		writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18);
++		writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true);
++		break;
++	case PHY_TYPE_SATA:
++		/* Enable adaptive CTLE for SATA Rx. */
++		val = readl(priv->mmio + PHYREG15);
++		val |= PHYREG15_CTLE_EN;
++		writel(val, priv->mmio + PHYREG15);
++		/*
++		 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA.
++		 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm)
++		 */
++		val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT;
++		val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT;
++		writel(val, priv->mmio + PHYREG7);
++
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true);
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true);
++		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true);
++		rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con1_for_sata, true);
++		break;
++	case PHY_TYPE_SGMII:
++	case PHY_TYPE_QSGMII:
++	default:
++		dev_err(priv->dev, "incompatible PHY type\n");
++		return -EINVAL;
++	}
++
++	rate = clk_get_rate(priv->refclk);
++
++	switch (rate) {
++	case REF_CLOCK_24MHz:
++		if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) {
++			/* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */
++			val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT;
++			rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK,
++						 val, PHYREG15);
++
++			writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16);
++		}
++		break;
++
++	case REF_CLOCK_25MHz:
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true);
++		break;
++	case REF_CLOCK_100MHz:
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true);
++		if (priv->type == PHY_TYPE_PCIE) {
++			/* PLL KVCO fine tuning. */
++			val = 4 << PHYREG33_PLL_KVCO_SHIFT;
++			rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK,
++						 val, PHYREG33);
++
++			/* Enable controlling random jitter. */
++			writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12);
++
++			/* Set up rx_trim: PLL LPF C1 85pf R1 1.25kohm */
++			writel(PHYREG27_RX_TRIM_RK3588, priv->mmio + PHYREG27);
++
++			/* Set up su_trim:  */
++			writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11);
++		} else if (priv->type == PHY_TYPE_SATA) {
++			/* downward spread spectrum +500ppm */
++			val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT;
++			val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT;
++			rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32);
++		}
++		break;
++	default:
++		dev_err(priv->dev, "Unsupported rate: %lu\n", rate);
++		return -EINVAL;
++	}
++
++	if (priv->ext_refclk) {
++		rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true);
++		if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) {
++			val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT;
++			val |= PHYREG13_CKRCV_AMP0;
++			rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13);
++
++			val = readl(priv->mmio + PHYREG14);
++			val |= PHYREG14_CKRCV_AMP1;
++			writel(val, priv->mmio + PHYREG14);
++		}
++	}
++
++	if (priv->enable_ssc) {
++		val = readl(priv->mmio + PHYREG8);
++		val |= PHYREG8_SSC_EN;
++		writel(val, priv->mmio + PHYREG8);
++	}
++
++	return 0;
++}
++
++static const struct rockchip_combphy_grfcfg rk3588_combphy_grfcfgs = {
++	/* pipe-phy-grf */
++	.pcie_mode_set		= { 0x0000, 5, 0, 0x00, 0x11 },
++	.usb_mode_set		= { 0x0000, 5, 0, 0x00, 0x04 },
++	.pipe_rxterm_set	= { 0x0000, 12, 12, 0x00, 0x01 },
++	.pipe_txelec_set	= { 0x0004, 1, 1, 0x00, 0x01 },
++	.pipe_txcomp_set	= { 0x0004, 4, 4, 0x00, 0x01 },
++	.pipe_clk_25m		= { 0x0004, 14, 13, 0x00, 0x01 },
++	.pipe_clk_100m		= { 0x0004, 14, 13, 0x00, 0x02 },
++	.pipe_rxterm_sel	= { 0x0008, 8, 8, 0x00, 0x01 },
++	.pipe_txelec_sel	= { 0x0008, 12, 12, 0x00, 0x01 },
++	.pipe_txcomp_sel	= { 0x0008, 15, 15, 0x00, 0x01 },
++	.pipe_clk_ext		= { 0x000c, 9, 8, 0x02, 0x01 },
++	.pipe_phy_status	= { 0x0034, 6, 6, 0x01, 0x00 },
++	.con0_for_pcie		= { 0x0000, 15, 0, 0x00, 0x1000 },
++	.con1_for_pcie		= { 0x0004, 15, 0, 0x00, 0x0000 },
++	.con2_for_pcie		= { 0x0008, 15, 0, 0x00, 0x0101 },
++	.con3_for_pcie		= { 0x000c, 15, 0, 0x00, 0x0200 },
++	.con0_for_sata		= { 0x0000, 15, 0, 0x00, 0x0129 },
++	.con1_for_sata		= { 0x0004, 15, 0, 0x00, 0x0000 },
++	.con2_for_sata		= { 0x0008, 15, 0, 0x00, 0x80c1 },
++	.con3_for_sata		= { 0x000c, 15, 0, 0x00, 0x0407 },
++	/* pipe-grf */
++	.pipe_con0_for_sata	= { 0x0000, 11, 5, 0x00, 0x22 },
++	.pipe_con1_for_sata	= { 0x0000, 2, 0, 0x00, 0x2 },
++	.pipe_pcie1l0_sel	= { 0x0100, 0, 0, 0x01, 0x0 },
++	.pipe_pcie1l1_sel	= { 0x0100, 1, 1, 0x01, 0x0 },
++};
++
++static const struct rockchip_combphy_cfg rk3588_combphy_cfgs = {
++	.grfcfg		= &rk3588_combphy_grfcfgs,
++	.combphy_cfg	= rk3588_combphy_cfg,
++};
++
+ static const struct of_device_id rockchip_combphy_of_match[] = {
+ 	{
+ 		.compatible = "rockchip,rk3568-naneng-combphy",
+ 		.data = &rk3568_combphy_cfgs,
+ 	},
++	{
++		.compatible = "rockchip,rk3588-naneng-combphy",
++		.data = &rk3588_combphy_cfgs,
++	},
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match);
diff --git a/target/linux/rockchip/patches-6.1/037-phy-rockchip-remove-unused-hw_to_inno-function.patch b/target/linux/rockchip/patches-6.1/037-phy-rockchip-remove-unused-hw_to_inno-function.patch
new file mode 100644
index 00000000000..510664e8cfb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/037-phy-rockchip-remove-unused-hw_to_inno-function.patch
@@ -0,0 +1,35 @@
+From fb8017ddf6a81081e6ab28e4736c5b098612a0f7 Mon Sep 17 00:00:00 2001
+From: Tom Rix <trix@redhat.com>
+Date: Fri, 24 Mar 2023 09:26:49 -0400
+Subject: [PATCH 037/383] phy: rockchip: remove unused hw_to_inno function
+
+clang with W=1 reports
+drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c:284:36: error:
+  unused function 'hw_to_inno' [-Werror,-Wunused-function]
+static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
+                                   ^
+This function is not used so remove it.
+
+Signed-off-by: Tom Rix <trix@redhat.com>
+Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
+Link: https://lore.kernel.org/r/20230324132649.2649166-1-trix@redhat.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c | 5 -----
+ 1 file changed, 5 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-dsidphy.c
+@@ -281,11 +281,6 @@ struct inno_mipi_dphy_timing inno_mipi_d
+ 	{2500000000, 0x15, 0x54, 0x7f, 0x15, 0x6a},
+ };
+ 
+-static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
+-{
+-	return container_of(hw, struct inno_dsidphy, pll.hw);
+-}
+-
+ static void phy_update_bits(struct inno_dsidphy *inno,
+ 			    u8 first, u8 second, u8 mask, u8 val)
+ {
diff --git a/target/linux/rockchip/patches-6.1/038-power-supply-rk817-Drop-unneeded-debugging-code.patch b/target/linux/rockchip/patches-6.1/038-power-supply-rk817-Drop-unneeded-debugging-code.patch
new file mode 100644
index 00000000000..9d0bef83b2e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/038-power-supply-rk817-Drop-unneeded-debugging-code.patch
@@ -0,0 +1,37 @@
+From 5aac5a5d0603677437e4a3fe348d6c3c87c23dd2 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 7 Apr 2023 11:18:26 -0500
+Subject: [PATCH 038/383] power: supply: rk817: Drop unneeded debugging code
+
+Some code was left over from debugging the driver while it was in
+development. Remove this code as it's not needed.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/power/supply/rk817_charger.c | 13 -------------
+ 1 file changed, 13 deletions(-)
+
+--- a/drivers/power/supply/rk817_charger.c
++++ b/drivers/power/supply/rk817_charger.c
+@@ -835,19 +835,6 @@ rk817_read_or_set_full_charge_on_boot(st
+ 		}
+ 	}
+ 
+-	regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_PWRON_VOL_H,
+-			 bulk_reg, 2);
+-	tmp = get_unaligned_be16(bulk_reg);
+-	boot_voltage = (charger->voltage_k * tmp) + 1000 * charger->voltage_b;
+-	regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_Q_PRES_H3,
+-			 bulk_reg, 4);
+-	tmp = get_unaligned_be32(bulk_reg);
+-	boot_charge_mah = ADC_TO_CHARGE_UAH(tmp, charger->res_div) / 1000;
+-	regmap_bulk_read(rk808->regmap, RK817_GAS_GAUGE_OCV_VOL_H,
+-			 bulk_reg, 2);
+-	tmp = get_unaligned_be16(bulk_reg);
+-	boot_voltage = (charger->voltage_k * tmp) + 1000 * charger->voltage_b;
+-
+ 	/*
+ 	 * Now we have our full charge capacity and soc, init the columb
+ 	 * counter.
diff --git a/target/linux/rockchip/patches-6.1/039-iommu-Remove-detach_dev-callbacks.patch b/target/linux/rockchip/patches-6.1/039-iommu-Remove-detach_dev-callbacks.patch
new file mode 100644
index 00000000000..e2f510c418d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/039-iommu-Remove-detach_dev-callbacks.patch
@@ -0,0 +1,37 @@
+From f535338ded5083fb5b57921cd116222452b4c727 Mon Sep 17 00:00:00 2001
+From: Lu Baolu <baolu.lu@linux.intel.com>
+Date: Tue, 10 Jan 2023 10:54:04 +0800
+Subject: [PATCH 039/383] iommu: Remove detach_dev callbacks
+
+The iommu core calls the driver's detach_dev domain op callback only when
+a device is finished assigning to user space and
+iommu_group_release_dma_owner() is called to return the device to the
+kernel, where iommu core wants to set the default domain to the device but
+the driver didn't provide one.
+
+In other words, if any iommu driver provides default domain support, the
+.detach_dev callback will never be called. This removes the detach_dev
+callbacks in those IOMMU drivers that support default domain.
+
+Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
+Reviewed-by: Sven Peter <sven@svenpeter.dev> # apple-dart
+Acked-by: Chunyan Zhang <zhang.lyra@gmail.com> # sprd
+Reviewed-by: Vasant Hegde <vasant.hegde@amd.com> # amd
+Signed-off-by: Lu Baolu <baolu.lu@linux.intel.com>
+Link: https://lore.kernel.org/r/20230110025408.667767-2-baolu.lu@linux.intel.com
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iommu/rockchip-iommu.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/iommu/rockchip-iommu.c
++++ b/drivers/iommu/rockchip-iommu.c
+@@ -1163,7 +1163,6 @@ static const struct iommu_ops rk_iommu_o
+ 	.of_xlate = rk_iommu_of_xlate,
+ 	.default_domain_ops = &(const struct iommu_domain_ops) {
+ 		.attach_dev	= rk_iommu_attach_device,
+-		.detach_dev	= rk_iommu_detach_device,
+ 		.map		= rk_iommu_map,
+ 		.unmap		= rk_iommu_unmap,
+ 		.iova_to_phys	= rk_iommu_iova_to_phys,
diff --git a/target/linux/rockchip/patches-6.1/040-iommu-rockchip-Add-missing-set_platform_dma_ops-call.patch b/target/linux/rockchip/patches-6.1/040-iommu-rockchip-Add-missing-set_platform_dma_ops-call.patch
new file mode 100644
index 00000000000..3f9bb86e100
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/040-iommu-rockchip-Add-missing-set_platform_dma_ops-call.patch
@@ -0,0 +1,178 @@
+From dd064d6d158c9b17a43f2ab308b8a492a5c6c03a Mon Sep 17 00:00:00 2001
+From: Steven Price <steven.price@arm.com>
+Date: Fri, 31 Mar 2023 10:51:54 +0100
+Subject: [PATCH 040/383] iommu/rockchip: Add missing set_platform_dma_ops
+ callback
+
+Similar to exynos, we need a set_platform_dma_ops() callback for proper
+operation on ARM 32 bit after recent changes in the IOMMU framework
+(detach ops removal). But also the use of a NULL domain is confusing.
+
+Rework the code to add support for IOMMU_DOMAIN_IDENTITY and a singleton
+rk_identity_domain which is assigned to domain when using an identity
+mapping rather than "detaching". This makes the code easier to reason about.
+
+Signed-off-by: Steven Price <steven.price@arm.com>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Tested-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20230331095154.2671129-1-steven.price@arm.com
+Signed-off-by: Joerg Roedel <jroedel@suse.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iommu/rockchip-iommu.c | 61 ++++++++++++++++++++++++++--------
+ 1 file changed, 47 insertions(+), 14 deletions(-)
+
+--- a/drivers/iommu/rockchip-iommu.c
++++ b/drivers/iommu/rockchip-iommu.c
+@@ -122,6 +122,7 @@ struct rk_iommudata {
+ 
+ static struct device *dma_dev;
+ static const struct rk_iommu_ops *rk_ops;
++static struct iommu_domain rk_identity_domain;
+ 
+ static inline void rk_table_flush(struct rk_iommu_domain *dom, dma_addr_t dma,
+ 				  unsigned int count)
+@@ -617,7 +618,7 @@ static irqreturn_t rk_iommu_irq(int irq,
+ 			 * Ignore the return code, though, since we always zap cache
+ 			 * and clear the page fault anyway.
+ 			 */
+-			if (iommu->domain)
++			if (iommu->domain != &rk_identity_domain)
+ 				report_iommu_fault(iommu->domain, iommu->dev, iova,
+ 						   flags);
+ 			else
+@@ -951,26 +952,27 @@ out_disable_clocks:
+ 	return ret;
+ }
+ 
+-static void rk_iommu_detach_device(struct iommu_domain *domain,
+-				   struct device *dev)
++static int rk_iommu_identity_attach(struct iommu_domain *identity_domain,
++				    struct device *dev)
+ {
+ 	struct rk_iommu *iommu;
+-	struct rk_iommu_domain *rk_domain = to_rk_domain(domain);
++	struct rk_iommu_domain *rk_domain;
+ 	unsigned long flags;
+ 	int ret;
+ 
+ 	/* Allow 'virtual devices' (eg drm) to detach from domain */
+ 	iommu = rk_iommu_from_dev(dev);
+ 	if (!iommu)
+-		return;
++		return -ENODEV;
++
++	rk_domain = to_rk_domain(iommu->domain);
+ 
+ 	dev_dbg(dev, "Detaching from iommu domain\n");
+ 
+-	/* iommu already detached */
+-	if (iommu->domain != domain)
+-		return;
++	if (iommu->domain == identity_domain)
++		return 0;
+ 
+-	iommu->domain = NULL;
++	iommu->domain = identity_domain;
+ 
+ 	spin_lock_irqsave(&rk_domain->iommus_lock, flags);
+ 	list_del_init(&iommu->node);
+@@ -982,8 +984,31 @@ static void rk_iommu_detach_device(struc
+ 		rk_iommu_disable(iommu);
+ 		pm_runtime_put(iommu->dev);
+ 	}
++
++	return 0;
+ }
+ 
++static void rk_iommu_identity_free(struct iommu_domain *domain)
++{
++}
++
++static struct iommu_domain_ops rk_identity_ops = {
++	.attach_dev = rk_iommu_identity_attach,
++	.free = rk_iommu_identity_free,
++};
++
++static struct iommu_domain rk_identity_domain = {
++	.type = IOMMU_DOMAIN_IDENTITY,
++	.ops = &rk_identity_ops,
++};
++
++#ifdef CONFIG_ARM
++static void rk_iommu_set_platform_dma(struct device *dev)
++{
++	WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev));
++}
++#endif
++
+ static int rk_iommu_attach_device(struct iommu_domain *domain,
+ 		struct device *dev)
+ {
+@@ -1006,8 +1031,9 @@ static int rk_iommu_attach_device(struct
+ 	if (iommu->domain == domain)
+ 		return 0;
+ 
+-	if (iommu->domain)
+-		rk_iommu_detach_device(iommu->domain, dev);
++	ret = rk_iommu_identity_attach(&rk_identity_domain, dev);
++	if (ret)
++		return ret;
+ 
+ 	iommu->domain = domain;
+ 
+@@ -1021,7 +1047,7 @@ static int rk_iommu_attach_device(struct
+ 
+ 	ret = rk_iommu_enable(iommu);
+ 	if (ret)
+-		rk_iommu_detach_device(iommu->domain, dev);
++		WARN_ON(rk_iommu_identity_attach(&rk_identity_domain, dev));
+ 
+ 	pm_runtime_put(iommu->dev);
+ 
+@@ -1032,6 +1058,9 @@ static struct iommu_domain *rk_iommu_dom
+ {
+ 	struct rk_iommu_domain *rk_domain;
+ 
++	if (type == IOMMU_DOMAIN_IDENTITY)
++		return &rk_identity_domain;
++
+ 	if (type != IOMMU_DOMAIN_UNMANAGED && type != IOMMU_DOMAIN_DMA)
+ 		return NULL;
+ 
+@@ -1147,6 +1176,7 @@ static int rk_iommu_of_xlate(struct devi
+ 	iommu_dev = of_find_device_by_node(args->np);
+ 
+ 	data->iommu = platform_get_drvdata(iommu_dev);
++	data->iommu->domain = &rk_identity_domain;
+ 	dev_iommu_priv_set(dev, data);
+ 
+ 	platform_device_put(iommu_dev);
+@@ -1159,6 +1189,9 @@ static const struct iommu_ops rk_iommu_o
+ 	.probe_device = rk_iommu_probe_device,
+ 	.release_device = rk_iommu_release_device,
+ 	.device_group = rk_iommu_device_group,
++#ifdef CONFIG_ARM
++	.set_platform_dma_ops = rk_iommu_set_platform_dma,
++#endif
+ 	.pgsize_bitmap = RK_IOMMU_PGSIZE_BITMAP,
+ 	.of_xlate = rk_iommu_of_xlate,
+ 	.default_domain_ops = &(const struct iommu_domain_ops) {
+@@ -1316,7 +1349,7 @@ static int __maybe_unused rk_iommu_suspe
+ {
+ 	struct rk_iommu *iommu = dev_get_drvdata(dev);
+ 
+-	if (!iommu->domain)
++	if (iommu->domain == &rk_identity_domain)
+ 		return 0;
+ 
+ 	rk_iommu_disable(iommu);
+@@ -1327,7 +1360,7 @@ static int __maybe_unused rk_iommu_resum
+ {
+ 	struct rk_iommu *iommu = dev_get_drvdata(dev);
+ 
+-	if (!iommu->domain)
++	if (iommu->domain == &rk_identity_domain)
+ 		return 0;
+ 
+ 	return rk_iommu_enable(iommu);
diff --git a/target/linux/rockchip/patches-6.1/041-arm64-dts-rockchip-add-PX30-Q7-Ringneck-SoM-with-Hai.patch b/target/linux/rockchip/patches-6.1/041-arm64-dts-rockchip-add-PX30-Q7-Ringneck-SoM-with-Hai.patch
new file mode 100644
index 00000000000..2203afc524a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/041-arm64-dts-rockchip-add-PX30-Q7-Ringneck-SoM-with-Hai.patch
@@ -0,0 +1,674 @@
+From 05012b43293b66586d3fba9e4eb04992a1389dbb Mon Sep 17 00:00:00 2001
+From: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+Date: Mon, 17 Oct 2022 12:25:24 +0200
+Subject: [PATCH 041/383] =?UTF-8?q?arm64:=20dts:=20rockchip:=20add=20PX30-?=
+ =?UTF-8?q?=C2=B5Q7=20(Ringneck)=20SoM=20with=20Haikou=20baseboard?=
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The PX30-uQ7 (Ringneck) SoM is a µQseven-compatible (40mmx70mm, MXM-230
+connector) system-on-module from Theobroma Systems[1], featuring the
+Rockchip PX30.
+
+It provides the following feature set:
+ * up to 4GB DDR4
+ * up to 128GB on-module eMMC (with 8-bit 1.8V interface)
+ * SD card (on a baseboard) via edge connector
+ * Fast Ethernet with on-module TI DP83825I PHY
+ * MIPI-DSI/LVDS
+ * MIPI-CSI
+ * USB
+   - 1x USB 2.0 dual-role
+   - 3x USB 2.0 host
+ * on-module STM32 Cortex-M0 companion controller, implementing:
+   - low-power RTC functionality (ISL1208 emulation)
+   - fan controller (AMC6821 emulation)
+   - USB<->CAN bridge controller
+ * on-module Espressif ESP32 for Bluetooth + 2.4GHz WiFi
+ * on-module NXP SE05x Secure Element
+
+[1] https://www.theobroma-systems.com/som-product/px30-%C2%B5q7/
+
+Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
+Link: https://lore.kernel.org/r/20220930-upstream-ringneck-v2-1-6671694b6934@theobroma-systems.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/px30-ringneck-haikou.dts     | 232 +++++++++++
+ .../boot/dts/rockchip/px30-ringneck.dtsi      | 382 ++++++++++++++++++
+ 3 files changed, 615 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -3,6 +3,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-evb.
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-ctouch2-of10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-engicam-px30-core-edimm2.2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += px30-ringneck-haikou.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-ringneck-haikou.dts
+@@ -0,0 +1,232 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
++ */
++
++/dts-v1/;
++#include "px30-ringneck.dtsi"
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	model = "Theobroma Systems PX30-uQ7 SoM on Haikou devkit";
++	compatible = "tsd,px30-ringneck-haikou", "rockchip,px30";
++
++	aliases {
++		mmc2 = &sdmmc;
++	};
++
++	chosen {
++		stdout-path = "serial0:115200n8";
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-0 = <&haikou_keys_pin>;
++		pinctrl-names = "default";
++
++		button-batlow-n {
++			label = "BATLOW#";
++			linux,code = <KEY_BATTERY>;
++			gpios = <&gpio3 RK_PA7 GPIO_ACTIVE_LOW>;
++		};
++
++		button-slp-btn-n {
++			label = "SLP_BTN#";
++			linux,code = <KEY_SLEEP>;
++			gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
++		};
++
++		button-wake-n {
++			label = "WAKE#";
++			linux,code = <KEY_WAKEUP>;
++			gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
++			wakeup-source;
++		};
++
++		switch-lid-btn-n {
++			label = "LID_BTN#";
++			linux,code = <SW_LID>;
++			linux,input-type = <EV_SW>;
++			gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
++		};
++	};
++
++	leds {
++		pinctrl-0 = <&module_led_pin>, <&sd_card_led_pin>;
++
++		sd_card_led: led-1 {
++			gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "mmc2";
++			function = LED_FUNCTION_SD;
++			color = <LED_COLOR_ID_BLUE>;
++		};
++	};
++
++	i2s0-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "Haikou,I2S-codec";
++		simple-audio-card,mclk-fs = <512>;
++
++		simple-audio-card,codec {
++			clocks = <&sgtl5000_clk>;
++			sound-dai = <&sgtl5000>;
++		};
++
++		simple-audio-card,cpu {
++			bitclock-master;
++			frame-master;
++			sound-dai = <&i2s0_8ch>;
++		};
++	};
++
++	sgtl5000_clk: sgtl5000-oscillator {
++		compatible = "fixed-clock";
++		#clock-cells = <0>;
++		clock-frequency  = <24576000>;
++	};
++
++	dc_12v: dc-12v-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc3v3_baseboard: vcc3v3-baseboard-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_baseboard";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc5v0_baseboard: vcc5v0-baseboard-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_baseboard";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vdda_codec: vdda-codec-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vdda_codec";
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_baseboard>;
++	};
++
++	vddd_codec: vddd-codec-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vddd_codec";
++		regulator-boot-on;
++		regulator-min-microvolt = <1600000>;
++		regulator-max-microvolt = <1600000>;
++		vin-supply = <&vcc5v0_baseboard>;
++	};
++};
++
++&i2c2 {
++	status = "okay";
++	clock-frequency = <400000>;
++
++	sgtl5000: codec@a {
++		compatible = "fsl,sgtl5000";
++		reg = <0x0a>;
++		clocks = <&sgtl5000_clk>;
++		#sound-dai-cells = <0>;
++		VDDA-supply = <&vdda_codec>;
++		VDDIO-supply = <&vcc3v3_baseboard>;
++		VDDD-supply = <&vddd_codec>;
++	};
++};
++
++&i2c3 {
++	eeprom@50 {
++		reg = <0x50>;
++		compatible = "atmel,24c01";
++		pagesize = <8>;
++		size = <128>;
++		vcc-supply = <&vcc3v3_baseboard>;
++	};
++};
++
++&i2s0_8ch {
++	status = "okay";
++};
++
++&gmac {
++	status = "okay";
++};
++
++&pinctrl {
++	haikou {
++		haikou_keys_pin: haikou-keys-pin {
++			rockchip,pins =
++			  /* WAKE# */
++			  <1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
++			  /* SLP_BTN# */
++			  <1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
++			  /* LID_BTN */
++			  <3 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++			  /* BATLOW# */
++			  <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
++			  /* BIOS_DISABLE# */
++			  <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	leds {
++		sd_card_led_pin: sd-card-led-pin {
++			rockchip,pins =
++			  <3 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&sdmmc {
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	vmmc-supply = <&vcc3v3_baseboard>;
++	status = "okay";
++};
++
++&spi1 {
++	status = "okay";
++};
++
++&u2phy_otg {
++	status = "okay";
++};
++
++&uart0 {
++	status = "okay";
++};
++
++&uart5 {
++	pinctrl-0 = <&uart5_xfer>;
++	status = "okay";
++};
++
++&usb20_otg {
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/px30-ringneck.dtsi
+@@ -0,0 +1,382 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Theobroma Systems Design und Consulting GmbH
++ */
++
++/dts-v1/;
++#include "px30.dtsi"
++#include <dt-bindings/leds/common.h>
++
++/ {
++	aliases {
++		mmc0 = &emmc;
++		mmc1 = &sdio;
++		rtc0 = &rtc_twi;
++		rtc1 = &rk809;
++	};
++
++	emmc_pwrseq: emmc-pwrseq {
++		compatible = "mmc-pwrseq-emmc";
++		pinctrl-0 = <&emmc_reset>;
++		pinctrl-names = "default";
++		reset-gpios = <&gpio1 RK_PB3 GPIO_ACTIVE_HIGH>;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&module_led_pin>;
++		status = "okay";
++
++		module_led: led-0 {
++			gpios = <&gpio1 RK_PB0 GPIO_ACTIVE_HIGH>;
++			function = LED_FUNCTION_HEARTBEAT;
++			linux,default-trigger = "heartbeat";
++			color = <LED_COLOR_ID_AMBER>;
++		};
++	};
++
++	vcc5v0_sys: vccsys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	mmc-hs200-1_8v;
++	supports-emmc;
++	mmc-pwrseq = <&emmc_pwrseq>;
++	non-removable;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_emmc>;
++
++	status = "okay";
++};
++
++/* On-module TI DP83825I PHY but no connector, enable in carrierboard */
++&gmac {
++	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	snps,reset-delays-us = <0 50000 50000>;
++	phy-supply = <&vcc_3v3>;
++	clock_in_out = "output";
++};
++
++&gpio2 {
++	/*
++	 * The Qseven BIOS_DISABLE signal on the PX30-µQ7 keeps the on-module
++	 * eMMC powered-down initially (in fact it keeps the reset signal
++	 * asserted). BIOS_DISABLE_OVERRIDE pin allows to re-enable eMMC after
++	 * the SPL has been booted from SD Card.
++	 */
++	bios-disable-override-hog {
++		gpios = <RK_PB5 GPIO_ACTIVE_LOW>;
++		output-high;
++		line-name = "bios_disable_override";
++		gpio-hog;
++	};
++
++	/*
++	 * The BIOS_DISABLE hog is a feedback pin for the actual status of the
++	 * signal, ignoring the BIOS_DISABLE_OVERRIDE logic. This usually
++	 * represents the state of a switch on the baseboard.
++	 */
++	bios-disable-n-hog {
++		gpios = <RK_PC2 GPIO_ACTIVE_LOW>;
++		line-name = "bios_disable";
++		input;
++		gpio-hog;
++	};
++};
++
++&gpu {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-0 = <&pmic_int>;
++		pinctrl-names = "default";
++		#clock-cells = <0>;
++		clock-output-names = "xin32k";
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc_3v3>;
++		vcc6-supply = <&vcc_3v3>;
++		vcc7-supply = <&vcc_3v3>;
++		vcc9-supply = <&vcc5v0_sys>;
++
++		regulators {
++			vdd_log: DCDC_REG1 {
++				regulator-name = "vdd_log";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vdd_arm: DCDC_REG2 {
++				regulator-name = "vdd_arm";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_3v0_1v8: vcc_emmc: DCDC_REG4 {
++				regulator-name = "vcc_3v0_1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3000000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3000000>;
++				};
++			};
++
++			vcc_3v3: DCDC_REG5 {
++				regulator-name = "vcc_3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_1v8: LDO_REG2 {
++				regulator-name = "vcc_1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_1v0: LDO_REG3 {
++				regulator-name = "vcc_1v0";
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_lcd: LDO_REG7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-name = "vcc_lcd";
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vcc_1v8_lcd: LDO_REG8 {
++				regulator-name = "vcc_1v8_lcd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG9 {
++				regulator-name = "vcca_1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++
++	/* SE05x is limited to Fast Mode */
++	clock-frequency = <400000>;
++
++	fan: fan@18 {
++		compatible = "ti,amc6821";
++		reg = <0x18>;
++		#cooling-cells = <2>;
++	};
++
++	rtc_twi: rtc@6f {
++		compatible = "isil,isl1208";
++		reg = <0x6f>;
++	};
++};
++
++&i2c3 {
++	status = "okay";
++};
++
++&i2s0_8ch {
++	rockchip,trcm-sync-tx-only;
++
++	pinctrl-0 = <&i2s0_8ch_sclktx &i2s0_8ch_lrcktx
++		     &i2s0_8ch_sdo0 &i2s0_8ch_sdi0>;
++};
++
++&io_domains {
++	vccio1-supply = <&vcc_3v3>;
++	vccio2-supply = <&vccio_sd>;
++	vccio3-supply = <&vcc_3v3>;
++	vccio4-supply = <&vcc_3v3>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_emmc>;
++	vccio-oscgpi-supply = <&vcc_3v3>;
++
++	status = "okay";
++};
++
++&pinctrl {
++	emmc {
++		emmc_reset: emmc-reset {
++			rockchip,pins = <1 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	leds {
++		module_led_pin: module-led-pin {
++			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic-int {
++			rockchip,pins =
++				<0 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&saradc {
++	vref-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&sdmmc {
++	vqmmc-supply = <&vccio_sd>;
++};
++
++&tsadc {
++	status = "okay";
++};
++
++&u2phy {
++	status = "okay";
++};
++
++&u2phy_host {
++	status = "okay";
++};
++
++/* Mule UCAN */
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&wdt {
++	status = "okay";
++};
diff --git a/package/boot/uboot-rockchip/patches/018-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat1N.patch b/target/linux/rockchip/patches-6.1/042-arm64-dts-rockchip-Add-Hardkernel-ODROID-M1-board.patch
similarity index 61%
rename from package/boot/uboot-rockchip/patches/018-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat1N.patch
rename to target/linux/rockchip/patches-6.1/042-arm64-dts-rockchip-Add-Hardkernel-ODROID-M1-board.patch
index 1264a49ed9f..1f0095aa26d 100644
--- a/package/boot/uboot-rockchip/patches/018-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat1N.patch
+++ b/target/linux/rockchip/patches-6.1/042-arm64-dts-rockchip-Add-Hardkernel-ODROID-M1-board.patch
@@ -1,98 +1,108 @@
+From 6880fb0f4734f7d587e01f2a3b2bc2bd44aaacd5 Mon Sep 17 00:00:00 2001
+From: Dongjin Kim <tobetter@gmail.com>
+Date: Fri, 30 Sep 2022 07:12:35 +0200
+Subject: [PATCH 042/383] arm64: dts: rockchip: Add Hardkernel ODROID-M1 board
+
+This patch is to add a device tree for new board Hardkernel ODROID-M1
+based on Rockchip RK3568, includes basic peripherals -
+uart/eMMC/uSD/i2c and on-board ethernet.
+
+Signed-off-by: Dongjin Kim <tobetter@gmail.com>
+[aurelien@aurel32.net: addressed issues from initial review]
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-3-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 414 ++++++++++++++++++
+ 2 files changed, 415 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -72,4 +72,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
 --- /dev/null
-+++ b/arch/arm/dts/rk3566-lubancat1n.dts
-@@ -0,0 +1,482 @@
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -0,0 +1,414 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
-+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
-+*/
++ * Copyright (c) 2022 Hardkernel Co., Ltd.
++ *
++ */
 +
 +/dts-v1/;
 +#include <dt-bindings/gpio/gpio.h>
 +#include <dt-bindings/leds/common.h>
 +#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3566.dtsi"
++#include "rk3568.dtsi"
 +
 +/ {
-+	model = "EmbedFire LubanCat1N";
-+	compatible = "embedfire,lubancat1n", "rockchip,rk3566";
++	model = "Hardkernel ODROID-M1";
++	compatible = "rockchip,rk3568-odroid-m1", "rockchip,rk3568";
 +
 +	aliases {
-+		ethernet0 = &gmac1;
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
++		ethernet0 = &gmac0;
++		i2c0 = &i2c3;
++		i2c3 = &i2c0;
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc0;
++		serial0 = &uart1;
++		serial1 = &uart0;
 +	};
 +
-+	chosen: chosen {
++	chosen {
 +		stdout-path = "serial2:1500000n8";
 +	};
-+	
-+	gpio-leds {
-+		compatible = "gpio-leds";
-+
-+		sys_led: sys-led {
-+			label = "sys_led";
-+			linux,default-trigger = "heartbeat";
-+			default-state = "on";
-+			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sys_led_pin>;
-+		};
-+	};
 +
-+	dc_5v: dc-5v {
++	dc_12v: dc-12v-regulator {
 +		compatible = "regulator-fixed";
-+		regulator-name = "dc_5v";
++		regulator-name = "dc_12v";
 +		regulator-always-on;
 +		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
 +	};
 +
-+	vcc3v3_sys: vcc3v3-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc5v0_sys>;
++	leds {
++		compatible = "gpio-leds";
++
++		led_power: led-0 {
++			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++			function = LED_FUNCTION_POWER;
++			color = <LED_COLOR_ID_RED>;
++			default-state = "keep";
++			linux,default-trigger = "default-on";
++			pinctrl-names = "default";
++			pinctrl-0 = <&led_power_pin>;
++		};
++		led_work: led-1 {
++			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++			function = LED_FUNCTION_HEARTBEAT;
++			color = <LED_COLOR_ID_BLUE>;
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&led_work_pin>;
++		};
 +	};
 +
-+	vcc5v0_sys: vcc5v0-sys {
++	vcc3v3_sys: vcc3v3-sys-regulator {
 +		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
++		regulator-name = "vcc3v3_sys";
 +		regulator-always-on;
 +		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&dc_5v>;
-+	};
-+
-+	pcie_3v3: pcie2-3v3-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie_3v3";
 +		regulator-min-microvolt = <3300000>;
 +		regulator-max-microvolt = <3300000>;
-+		enable-active-high;
-+		gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
-+		startup-delay-us = <5000>;
-+		vin-supply = <&vcc5v0_sys>;
++		vin-supply = <&dc_12v>;
 +	};
 +};
 +
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&combphy1 {
-+	status = "okay";
-+};
-+
-+&combphy2 {
-+	status = "okay";
-+};
-+
 +&cpu0 {
 +	cpu-supply = <&vdd_cpu>;
 +};
@@ -109,9 +119,24 @@
 +	cpu-supply = <&vdd_cpu>;
 +};
 +
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
++&gmac0 {
++	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
++	assigned-clock-rates = <0>, <125000000>;
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy0>;
++	phy-mode = "rgmii";
++	phy-supply = <&vcc3v3_sys>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac0_miim
++		     &gmac0_tx_bus2
++		     &gmac0_rx_bus2
++		     &gmac0_rgmii_clk
++		     &gmac0_rgmii_bus>;
 +	status = "okay";
++
++	tx_delay = <0x4f>;
++	rx_delay = <0x2d>;
 +};
 +
 +&i2c0 {
@@ -127,7 +152,7 @@
 +		regulator-min-microvolt = <800000>;
 +		regulator-max-microvolt = <1150000>;
 +		regulator-ramp-delay = <2300>;
-+		vin-supply = <&vcc5v0_sys>;
++		vin-supply = <&vcc3v3_sys>;
 +
 +		regulator-state-mem {
 +			regulator-off-in-suspend;
@@ -139,15 +164,10 @@
 +		reg = <0x20>;
 +		interrupt-parent = <&gpio0>;
 +		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
 +		#clock-cells = <1>;
-+		clock-names = "mclk";
-+		clocks = <&cru I2S1_MCLKOUT_TX>;
 +		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
++		pinctrl-0 = <&pmic_int_l>;
 +		rockchip,system-power-controller;
-+		#sound-dai-cells = <0>;
 +		vcc1-supply = <&vcc3v3_sys>;
 +		vcc2-supply = <&vcc3v3_sys>;
 +		vcc3-supply = <&vcc3v3_sys>;
@@ -164,11 +184,11 @@
 +				regulator-name = "vdd_logic";
 +				regulator-always-on;
 +				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
 +				regulator-min-microvolt = <500000>;
 +				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
 +				regulator-ramp-delay = <6001>;
-+				regulator-initial-mode = <0x2>;
 +
 +				regulator-state-mem {
 +					regulator-off-in-suspend;
@@ -178,12 +198,11 @@
 +			vdd_gpu: DCDC_REG2 {
 +				regulator-name = "vdd_gpu";
 +				regulator-always-on;
-+				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
 +				regulator-min-microvolt = <500000>;
 +				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
 +				regulator-ramp-delay = <6001>;
-+				regulator-initial-mode = <0x2>;
 +
 +				regulator-state-mem {
 +					regulator-off-in-suspend;
@@ -203,13 +222,11 @@
 +
 +			vdd_npu: DCDC_REG4 {
 +				regulator-name = "vdd_npu";
-+				regulator-always-on;
-+				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
 +				regulator-min-microvolt = <500000>;
 +				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
 +				regulator-ramp-delay = <6001>;
-+				regulator-initial-mode = <0x2>;
 +
 +				regulator-state-mem {
 +					regulator-off-in-suspend;
@@ -230,7 +247,6 @@
 +
 +			vdda0v9_image: LDO_REG1 {
 +				regulator-name = "vdda0v9_image";
-+				regulator-boot-on;
 +				regulator-always-on;
 +				regulator-min-microvolt = <900000>;
 +				regulator-max-microvolt = <900000>;
@@ -279,8 +295,6 @@
 +
 +			vccio_sd: LDO_REG5 {
 +				regulator-name = "vccio_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
 +				regulator-min-microvolt = <1800000>;
 +				regulator-max-microvolt = <3300000>;
 +
@@ -330,7 +344,6 @@
 +			vcca1v8_image: LDO_REG9 {
 +				regulator-name = "vcca1v8_image";
 +				regulator-always-on;
-+				regulator-boot-on;
 +				regulator-min-microvolt = <1800000>;
 +				regulator-max-microvolt = <1800000>;
 +
@@ -351,8 +364,6 @@
 +
 +			vcc3v3_sd: SWITCH_REG2 {
 +				regulator-name = "vcc3v3_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
 +
 +				regulator-state-mem {
 +					regulator-off-in-suspend;
@@ -362,52 +373,42 @@
 +	};
 +};
 +
-+&i2s1_8ch {
-+	rockchip,trcm-sync-tx-only;
-+	status = "okay";
++&mdio0 {
++	rgmii_phy0: ethernet-phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x0>;
++		reset-assert-us = <20000>;
++		reset-deassert-us = <100000>;
++		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	};
 +};
 +
-+&gmac1 {
-+    phy-mode = "rgmii";
-+    clock_in_out = "output";
-+
-+    snps,reset-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
-+    snps,reset-active-low;
-+    /* Reset time is 100ms, 100ms */
-+    snps,reset-delays-us = <0 75000 100000>;
-+
-+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
-+    assigned-clock-rates = <0>, <125000000>;
-+
-+    pinctrl-names = "default";
-+    pinctrl-0 = <&gmac1m1_miim
-+             &gmac1m1_tx_bus2_level3
-+             &gmac1m1_rx_bus2
-+             &gmac1m1_rgmii_clk_level2
-+             &gmac1m1_rgmii_bus_level3>;
-+
-+    tx_delay = <0x24>;
-+    rx_delay = <0x08>;
-+
-+    phy-handle = <&rgmii_phy1>;
-+    status = "okay";
-+};
++&pinctrl {
++	leds {
++		led_power_pin: led-power-pin {
++			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		led_work_pin: led-work-pin {
++			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
 +
-+&mdio1 {
-+    rgmii_phy1: phy@0 {
-+        compatible = "ethernet-phy-ieee802.3-c22";
-+        reg = <0x0>;
-+    };
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
 +};
 +
 +&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
 +	pmuio2-supply = <&vcc3v3_pmu>;
 +	vccio1-supply = <&vccio_acodec>;
++	vccio2-supply = <&vcc_1v8>;
 +	vccio3-supply = <&vccio_sd>;
 +	vccio4-supply = <&vcc_1v8>;
 +	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
++	vccio6-supply = <&vcc_3v3>;
 +	vccio7-supply = <&vcc_3v3>;
 +	status = "okay";
 +};
@@ -417,97 +418,30 @@
 +	status = "okay";
 +};
 +
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
 +&sdhci {
-+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
-+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
 +	bus-width = <8>;
-+	max-frequency = <150000000>;
-+	mmc-hs200-1_8v;		
-+	non-removable;	
++	max-frequency = <200000000>;
++	non-removable;
 +	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
-+	supports-emmc;
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe &emmc_rstnout>;
 +	vmmc-supply = <&vcc_3v3>;
 +	vqmmc-supply = <&vcc_1v8>;
 +	status = "okay";
 +};
 +
 +&sdmmc0 {
-+    max-frequency = <150000000>;
-+    supports-sd;
-+    bus-width = <4>;
-+    cap-mmc-highspeed;
-+    cap-sd-highspeed;
-+    disable-wp;
-+    sd-uhs-sdr104;
-+    vmmc-supply = <&vcc3v3_sd>;
-+    vqmmc-supply = <&vccio_sd>;
-+    pinctrl-names = "default";
-+    pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+    status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	leds {
-+		sys_led_pin: sys-status-led-pin {
-+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins =
-+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/dts/rk3566-lubancat1n-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
-+ */
-+
-+#include "rk3568-u-boot.dtsi"
-+
-+/ {
-+	chosen {
-+		stdout-path = &uart2;
-+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
-+	};
-+};
-+
-+&sdmmc0 {
 +	bus-width = <4>;
-+	u-boot,dm-spl;
-+	u-boot,spl-fifo-mode;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	sd-uhs-sdr50;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	status = "okay";
 +};
 +
 +&uart2 {
-+	clock-frequency = <24000000>;
-+	u-boot,dm-spl;
 +	status = "okay";
 +};
diff --git a/target/linux/rockchip/patches-6.1/043-arm64-dts-rockchip-add-thermal-support-to-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/043-arm64-dts-rockchip-add-thermal-support-to-ODROID-M1.patch
new file mode 100644
index 00000000000..ce719500c19
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/043-arm64-dts-rockchip-add-thermal-support-to-ODROID-M1.patch
@@ -0,0 +1,32 @@
+From a8e414fb9982356c935799ebccac6e7ee64a5814 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:36 +0200
+Subject: [PATCH 043/383] arm64: dts: rockchip: add thermal support to
+ ODROID-M1
+
+Add the thermal nodes for the ODROID-M1.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-4-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -409,6 +409,12 @@
+ 	status = "okay";
+ };
+ 
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
+ &uart2 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/044-arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/044-arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch
new file mode 100644
index 00000000000..0bb8b193f1c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/044-arm64-dts-rockchip-Add-NOR-flash-to-ODROID-M1.patch
@@ -0,0 +1,96 @@
+From 09f1ea535fa3b171df1c926211e80a17aea62265 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:37 +0200
+Subject: [PATCH 044/383] arm64: dts: rockchip: Add NOR flash to ODROID-M1
+
+Enable the Rockchip Serial Flash Controller for the ODROID-M1 and add
+the corresponding SPI NOR flash entry. The SFC is used in dual I/O mode
+and not quad I/O mode, as the FSPI_D2 pin is shared with the EMMC_RSTn
+pin.
+
+The partitions addresses and sizes are taken from the ODROID-M1
+Partition Table page on the ODROID wiki.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-5-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 58 +++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -351,6 +351,20 @@
+ };
+ 
+ &pinctrl {
++	fspi {
++		fspi_dual_io_pins: fspi-dual-io-pins {
++			rockchip,pins =
++				/* fspi_clk */
++				<1 RK_PD0 1 &pcfg_pull_none>,
++				/* fspi_cs0n */
++				<1 RK_PD3 1 &pcfg_pull_none>,
++				/* fspi_d0 */
++				<1 RK_PD1 1 &pcfg_pull_none>,
++				/* fspi_d1 */
++				<1 RK_PD2 1 &pcfg_pull_none>;
++		};
++	};
++
+ 	leds {
+ 		led_power_pin: led-power-pin {
+ 			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+@@ -409,6 +423,50 @@
+ 	status = "okay";
+ };
+ 
++&sfc {
++	/* Dual I/O mode as the D2 pin conflicts with the eMMC */
++	pinctrl-0 = <&fspi_dual_io_pins>;
++	pinctrl-names = "default";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <100000000>;
++		spi-rx-bus-width = <2>;
++		spi-tx-bus-width = <1>;
++
++		partitions {
++			compatible = "fixed-partitions";
++			#address-cells = <1>;
++			#size-cells = <1>;
++
++			partition@0 {
++				label = "SPL";
++				reg = <0x0 0xe0000>;
++			};
++			partition@e0000 {
++				label = "U-Boot Env";
++				reg = <0xe0000 0x20000>;
++			};
++			partition@100000 {
++				label = "U-Boot";
++				reg = <0x100000 0x200000>;
++			};
++			partition@300000 {
++				label = "splash";
++				reg = <0x300000 0x100000>;
++			};
++			partition@400000 {
++				label = "Filesystem";
++				reg = <0x400000 0xc00000>;
++			};
++		};
++	};
++};
++
+ &tsadc {
+ 	rockchip,hw-tshut-mode = <1>;
+ 	rockchip,hw-tshut-polarity = <0>;
diff --git a/target/linux/rockchip/patches-6.1/045-arm64-dts-rockchip-Add-analog-audio-on-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/045-arm64-dts-rockchip-Add-analog-audio-on-ODROID-M1.patch
new file mode 100644
index 00000000000..7e29e205b36
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/045-arm64-dts-rockchip-Add-analog-audio-on-ODROID-M1.patch
@@ -0,0 +1,95 @@
+From e8e7538110b62bb7970138c461d722c203cb4c4f Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:38 +0200
+Subject: [PATCH 045/383] arm64: dts: rockchip: Add analog audio on ODROID-M1
+
+On the ODROID-M1, the I2S1 TDM controller is connected to the rk809
+codec in I2S mode. It is used to provide a stereo headphones output and
+a mono speaker output. A GPIO with an external pullup is used as an
+headphone detection input.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-6-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 43 ++++++++++++++++++-
+ 1 file changed, 42 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -59,6 +59,31 @@
+ 		};
+ 	};
+ 
++	rk809-sound {
++		compatible = "simple-audio-card";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_det_pin>;
++		simple-audio-card,name = "Analog RK817";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Headphone", "Headphones",
++			"Speaker", "Speaker";
++		simple-audio-card,routing =
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Speaker", "SPKO";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
+ 	vcc3v3_sys: vcc3v3-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+@@ -131,10 +156,15 @@
+ 		reg = <0x20>;
+ 		interrupt-parent = <&gpio0>;
+ 		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
++		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
+ 		#clock-cells = <1>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT_TX>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int_l>;
++		pinctrl-0 = <&pmic_int_l>, <&i2s1m0_mclk>;
+ 		rockchip,system-power-controller;
++		#sound-dai-cells = <0>;
+ 		vcc1-supply = <&vcc3v3_sys>;
+ 		vcc2-supply = <&vcc3v3_sys>;
+ 		vcc3-supply = <&vcc3v3_sys>;
+@@ -340,6 +370,11 @@
+ 	};
+ };
+ 
++&i2s1_8ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
+ &mdio0 {
+ 	rgmii_phy0: ethernet-phy@0 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -379,6 +414,12 @@
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
++
++	rk809 {
++		hp_det_pin: hp-det-pin {
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
diff --git a/target/linux/rockchip/patches-6.1/046-arm64-dts-rockchip-Enable-vop2-and-hdmi-tx-on-ODROID.patch b/target/linux/rockchip/patches-6.1/046-arm64-dts-rockchip-Enable-vop2-and-hdmi-tx-on-ODROID.patch
new file mode 100644
index 00000000000..55ca788cc36
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/046-arm64-dts-rockchip-Enable-vop2-and-hdmi-tx-on-ODROID.patch
@@ -0,0 +1,91 @@
+From 286c987ac577c93b08ecc541f1a9ed78fe1cb7f1 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:39 +0200
+Subject: [PATCH 046/383] arm64: dts: rockchip: Enable vop2 and hdmi tx on
+ ODROID-M1
+
+Enable the RK356x Video Output Processor (VOP) 2 on ODROID M1.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-7-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3568.dtsi"
+ 
+ / {
+@@ -37,6 +38,17 @@
+ 		regulator-max-microvolt = <12000000>;
+ 	};
+ 
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -131,6 +143,24 @@
+ 	rx_delay = <0x2d>;
+ };
+ 
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -517,3 +547,20 @@
+ &uart2 {
+ 	status = "okay";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/047-arm64-dts-rockchip-Enable-HDMI-audio-on-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/047-arm64-dts-rockchip-Enable-HDMI-audio-on-ODROID-M1.patch
new file mode 100644
index 00000000000..749ebbdcb01
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/047-arm64-dts-rockchip-Enable-HDMI-audio-on-ODROID-M1.patch
@@ -0,0 +1,41 @@
+From 0c16d1de85af6fc1a3492043f4f753234f039222 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:40 +0200
+Subject: [PATCH 047/383] arm64: dts: rockchip: Enable HDMI audio on ODROID-M1.
+
+This enables the i2s0 controller and the hdmi-sound node on the
+ODROID-M1.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-8-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -161,6 +161,10 @@
+ 	};
+ };
+ 
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -400,6 +404,10 @@
+ 	};
+ };
+ 
++&i2s0_8ch {
++	status = "okay";
++};
++
+ &i2s1_8ch {
+ 	rockchip,trcm-sync-tx-only;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/048-arm64-dts-rockchip-Enable-the-GPU-on-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/048-arm64-dts-rockchip-Enable-the-GPU-on-ODROID-M1.patch
new file mode 100644
index 00000000000..460a5e96890
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/048-arm64-dts-rockchip-Enable-the-GPU-on-ODROID-M1.patch
@@ -0,0 +1,30 @@
+From 00b3ed9e0018aafc04508b308eb27d217f49f2fd Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:41 +0200
+Subject: [PATCH 048/383] arm64: dts: rockchip: Enable the GPU on ODROID-M1
+
+Enable the GPU core on the Rockchip RK3568 ODROID-M1.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-9-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -143,6 +143,11 @@
+ 	rx_delay = <0x2d>;
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
+ &hdmi {
+ 	avdd-0v9-supply = <&vdda0v9_image>;
+ 	avdd-1v8-supply = <&vcca1v8_image>;
diff --git a/target/linux/rockchip/patches-6.1/049-arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch b/target/linux/rockchip/patches-6.1/049-arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch
new file mode 100644
index 00000000000..9d1f2b43410
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/049-arm64-dts-rockchip-Enable-the-USB-2.0-ports-on-ODROI.patch
@@ -0,0 +1,105 @@
+From c21340cb5528568bc46f11d7d71c8f0699bed4d7 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:42 +0200
+Subject: [PATCH 049/383] arm64: dts: rockchip: Enable the USB 2.0 ports on
+ ODROID-M1
+
+The Rockchip RK3568 has two USB OHCI/EHCI controllers connected to a PHY
+providing one host-only port and one OTG port. On the ODROID-M1, they
+are both used in host mode. The USB ports are powered by a DC/DC
+converter providing 5V and named VCC5V0_SYS on the schematics, followed
+by a power switch.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-10-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 61 +++++++++++++++++++
+ 1 file changed, 61 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -105,6 +105,28 @@
+ 		regulator-max-microvolt = <3300000>;
+ 		vin-supply = <&dc_12v>;
+ 	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb_host";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_host_en_pin>;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
+ };
+ 
+ &cpu0 {
+@@ -463,6 +485,15 @@
+ 			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	usb {
++		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
+@@ -561,6 +592,36 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
+ &vop {
+ 	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ 	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
diff --git a/target/linux/rockchip/patches-6.1/050-arm64-dts-rockchip-Enable-the-USB-3.0-ports-on-ODROI.patch b/target/linux/rockchip/patches-6.1/050-arm64-dts-rockchip-Enable-the-USB-3.0-ports-on-ODROI.patch
new file mode 100644
index 00000000000..c8011f5d7c3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/050-arm64-dts-rockchip-Enable-the-USB-3.0-ports-on-ODROI.patch
@@ -0,0 +1,108 @@
+From aa7171a8c4fde0b4c4561ee2132512c42403e720 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:43 +0200
+Subject: [PATCH 050/383] arm64: dts: rockchip: Enable the USB 3.0 ports on
+ ODROID-M1
+
+The Rockchip RK3568 has two USB XHCI controllers. The USB 2.0 signals
+are connected to a PHY providing one host-only port and one OTG port.
+The USB 3.0 signals are connected to two USB3.0/PCIE/SATA combo PHY.
+
+The ODROID M1 has 2 type A USB 3.0 connectors, with the USB 3.0 signals
+connected to the two combo PHYs. For the USB 2.0 signals, one connector
+is connected to the host-only PHY and uses the same power switch as the
+USB 2.0 ports. The other connector has its own power switch and is
+connected to the OTG PHY, which is also connected to a device only
+micro-USB connector. The purpose of this micro-USB connector is for
+firmware update using the Rockusb vendor specific USB class. Therefore
+it does not make sense to enable this port on Linux, and the PHY is
+forced to host mode.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-11-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 49 ++++++++++++++++++-
+ 1 file changed, 48 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -127,6 +127,30 @@
+ 		regulator-max-microvolt = <5000000>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
++
++	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb_otg";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_otg_en_pin>;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++};
++
++&combphy0 {
++	/* Used for USB3 */
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&combphy1 {
++	/* Used for USB3 */
++	phy-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
+ };
+ 
+ &cpu0 {
+@@ -490,7 +514,7 @@
+ 		vcc5v0_usb_host_en_pin: vcc5v0-usb-host-en-pin {
+ 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+-		vcc5v0_usb_otg_en_pin: vcc5v0-usb-otg-en-pin {
++		vcc5v0_usb_otg_en_pin: vcc5v0-usb-dr-en-pin {
+ 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+@@ -600,6 +624,11 @@
+ 	status = "okay";
+ };
+ 
++&usb_host0_xhci {
++	dr_mode = "host";
++	status = "okay";
++};
++
+ &usb_host1_ehci {
+ 	status = "okay";
+ };
+@@ -608,6 +637,24 @@
+ 	status = "okay";
+ };
+ 
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
++};
++
+ &usb2phy1 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/051-arm64-dts-rockchip-Add-SATA-support-to-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/051-arm64-dts-rockchip-Add-SATA-support-to-ODROID-M1.patch
new file mode 100644
index 00000000000..af86afb8f96
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/051-arm64-dts-rockchip-Add-SATA-support-to-ODROID-M1.patch
@@ -0,0 +1,41 @@
+From 3f203dc5bf6c41f7d0c7ed40417714828e1f1be3 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:44 +0200
+Subject: [PATCH 051/383] arm64: dts: rockchip: Add SATA support to ODROID-M1
+
+Enable the Combo PHY and SATA nodes in ODROID-M1.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-12-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -153,6 +153,11 @@
+ 	status = "okay";
+ };
+ 
++&combphy2 {
++	/* used for SATA */
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_cpu>;
+ };
+@@ -538,6 +543,10 @@
+ 	status = "okay";
+ };
+ 
++&sata2 {
++	status = "okay";
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	max-frequency = <200000000>;
diff --git a/target/linux/rockchip/patches-6.1/052-arm64-dts-rockchip-Add-PCIEe-v3-nodes-to-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/052-arm64-dts-rockchip-Add-PCIEe-v3-nodes-to-ODROID-M1.patch
new file mode 100644
index 00000000000..4b5f96ed8d0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/052-arm64-dts-rockchip-Add-PCIEe-v3-nodes-to-ODROID-M1.patch
@@ -0,0 +1,73 @@
+From e7f9dd0569304541100a44c9caa258b24a38bc98 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:45 +0200
+Subject: [PATCH 052/383] arm64: dts: rockchip: Add PCIEe v3 nodes to ODROID-M1
+
+Add nodes to ODROID-M1 to support PCIe v3 on the M2 slot.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-13-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-odroid-m1.dts    | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -96,6 +96,19 @@
+ 		};
+ 	};
+ 
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		enable-active-high;
++		gpio = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc3v3_pcie_en_pin>;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <5000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
+ 	vcc3v3_sys: vcc3v3-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+@@ -479,6 +492,18 @@
+ 	};
+ };
+ 
++&pcie30phy {
++	status = "okay";
++};
++
++&pcie3x2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_reset_pin>;
++	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
+ &pinctrl {
+ 	fspi {
+ 		fspi_dual_io_pins: fspi-dual-io-pins {
+@@ -503,6 +528,15 @@
+ 		};
+ 	};
+ 
++	pcie {
++		pcie_reset_pin: pcie-reset-pin {
++			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		vcc3v3_pcie_en_pin: vcc3v3-pcie-en-pin {
++			rockchip,pins = <4 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/target/linux/rockchip/patches-6.1/053-arm64-dts-rockchip-Add-IR-receiver-node-to-ODROID-M1.patch b/target/linux/rockchip/patches-6.1/053-arm64-dts-rockchip-Add-IR-receiver-node-to-ODROID-M1.patch
new file mode 100644
index 00000000000..66b1395aa99
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/053-arm64-dts-rockchip-Add-IR-receiver-node-to-ODROID-M1.patch
@@ -0,0 +1,48 @@
+From 864f273ee7a4c441215ade9ac44d21ecba4501c2 Mon Sep 17 00:00:00 2001
+From: Aurelien Jarno <aurelien@aurel32.net>
+Date: Fri, 30 Sep 2022 07:12:46 +0200
+Subject: [PATCH 053/383] arm64: dts: rockchip: Add IR receiver node to
+ ODROID-M1
+
+Add the infrared receiver and its associated pinctrl entry. Note that
+there is an external pullup to VCC3V3_SYS.
+
+Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
+Tested-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20220930051246.391614-14-aurelien@aurel32.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-odroid-m1.dts
+@@ -49,6 +49,13 @@
+ 		};
+ 	};
+ 
++	ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&ir_receiver_pin>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -519,6 +526,13 @@
+ 		};
+ 	};
+ 
++	ir-receiver {
++		ir_receiver_pin: ir-receiver-pin {
++			/* external pullup to VCC3V3_SYS */
++			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	leds {
+ 		led_power_pin: led-power-pin {
+ 			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/target/linux/rockchip/patches-6.1/054-arm64-dts-rockchip-Add-regulator-suffix-to-rock-3a.patch b/target/linux/rockchip/patches-6.1/054-arm64-dts-rockchip-Add-regulator-suffix-to-rock-3a.patch
new file mode 100644
index 00000000000..3790565ed47
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/054-arm64-dts-rockchip-Add-regulator-suffix-to-rock-3a.patch
@@ -0,0 +1,82 @@
+From 3de876fa1abbfd51eb1807ec80051f3b646bc6f9 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Thu, 6 Oct 2022 23:25:23 +0800
+Subject: [PATCH 054/383] arm64: dts: rockchip: Add regulator suffix to rock-3a
+
+Add -regulator suffix to regulator names on Radxa ROCK3 Model A
+board. This makes the naming more consistent.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20221006152524.502445-2-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 14 +++++++-------
+ 1 file changed, 7 insertions(+), 7 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -60,7 +60,7 @@
+ 		};
+ 	};
+ 
+-	vcc12v_dcin: vcc12v-dcin {
++	vcc12v_dcin: vcc12v-dcin-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc12v_dcin";
+ 		regulator-always-on;
+@@ -79,7 +79,7 @@
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
+ 
+-	vcc3v3_sys: vcc3v3-sys {
++	vcc3v3_sys: vcc3v3-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+ 		regulator-always-on;
+@@ -89,7 +89,7 @@
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
+ 
+-	vcc5v0_sys: vcc5v0-sys {
++	vcc5v0_sys: vcc5v0-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_sys";
+ 		regulator-always-on;
+@@ -99,7 +99,7 @@
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
+ 
+-	vcc5v0_usb: vcc5v0-usb {
++	vcc5v0_usb: vcc5v0-usb-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_usb";
+ 		regulator-always-on;
+@@ -109,7 +109,7 @@
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
+ 
+-	vcc5v0_usb_host: vcc5v0-usb-host {
++	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+ 		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+@@ -144,7 +144,7 @@
+ 		vin-supply = <&vcc5v0_usb>;
+ 	};
+ 
+-	vcc_cam: vcc-cam {
++	vcc_cam: vcc-cam-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+ 		gpio = <&gpio1 RK_PB1 GPIO_ACTIVE_HIGH>;
+@@ -160,7 +160,7 @@
+ 		};
+ 	};
+ 
+-	vcc_mipi: vcc-mipi {
++	vcc_mipi: vcc-mipi-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+ 		gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/rockchip/patches-6.1/055-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-rock-3a.patch b/target/linux/rockchip/patches-6.1/055-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-rock-3a.patch
new file mode 100644
index 00000000000..5328622d51d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/055-arm64-dts-rockchip-Add-PCIe-v3-nodes-to-rock-3a.patch
@@ -0,0 +1,76 @@
+From c387e718b0581d7c484064e40ef88a8a97a3e444 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Thu, 6 Oct 2022 23:25:24 +0800
+Subject: [PATCH 055/383] arm64: dts: rockchip: Add PCIe v3 nodes to rock-3a
+
+Add Nodes to Radxa ROCK3 Model A board to support PCIe v3.
+
+Tested-by: Anand Moon <linux.amoon@gmail.com>
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20221006152524.502445-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-rock-3a.dts      | 44 +++++++++++++++++++
+ 1 file changed, 44 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -67,6 +67,37 @@
+ 		regulator-boot-on;
+ 	};
+ 
++	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd0v9";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	/* pi6c pcie clock generator */
++	vcc3v3_pi6c_03: vcc3v3-pi6c-03-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pi6c_03";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
+ 	vcc3v3_pcie: vcc3v3-pcie-regulator {
+ 		compatible = "regulator-fixed";
+ 		enable-active-high;
+@@ -546,6 +577,19 @@
+ 	vpcie3v3-supply = <&vcc3v3_pcie>;
+ 	status = "okay";
+ };
++
++&pcie30phy {
++	phy-supply = <&vcc3v3_pi6c_03>;
++	status = "okay";
++};
++
++&pcie3x2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie30x2m1_pins>;
++	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
+ 
+ &pinctrl {
+ 	cam {
diff --git a/target/linux/rockchip/patches-6.1/056-arm64-dts-rockchip-add-BT-wifi-nodes-to-Pinephone-Pr.patch b/target/linux/rockchip/patches-6.1/056-arm64-dts-rockchip-add-BT-wifi-nodes-to-Pinephone-Pr.patch
new file mode 100644
index 00000000000..0c458df1183
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/056-arm64-dts-rockchip-add-BT-wifi-nodes-to-Pinephone-Pr.patch
@@ -0,0 +1,130 @@
+From f3f4c92922cb0c8fdcf5fe31cb47babba18aab1b Mon Sep 17 00:00:00 2001
+From: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+Date: Sun, 2 Oct 2022 20:28:09 +1100
+Subject: [PATCH 056/383] arm64: dts: rockchip: add BT/wifi nodes to Pinephone
+ Pro
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Pinephone Pro includes a AzureWave AW-CM256SM wifi (sdio0) and
+bt (uart0) combo module, which is based on Cypress
+CYP43455 (BCM43455).
+
+The CYP43455 datasheet ("Power-Up Sequence and Timing") documents:
+* needing to wait 10ms between consecutive WL_REG_ON toggles
+* needing to wait 110ms between power-on and SDIO access.
+
+Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+Reviewed-by: Ondřej Jirman <megi@xff.cz>
+Link: https://lore.kernel.org/r/20221002092809.451501-1-tom@tom-fitzhenry.me.uk
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3399-pinephone-pro.dts     | 76 +++++++++++++++++++
+ 1 file changed, 76 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+@@ -81,6 +81,27 @@
+ 		regulator-max-microvolt = <1800000>;
+ 		vin-supply = <&vcc3v3_sys>;
+ 	};
++
++	wifi_pwrseq: sdio-wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk818 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h_pin>;
++		/*
++		 * Wait between power-on and SDIO access for CYP43455
++		 * POR circuit.
++		 */
++		post-power-on-delay-ms = <110>;
++		/*
++		 * Wait between consecutive toggles for CYP43455 CBUCK
++		 * regulator discharge.
++		 */
++		power-off-delay-us = <10000>;
++
++		/* WL_REG_ON on module */
++		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
++	};
+ };
+ 
+ &cpu_alert0 {
+@@ -367,11 +388,45 @@
+ 		};
+ 	};
+ 
++	sdio-pwrseq {
++		wifi_enable_h_pin: wifi-enable-h-pin {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	sound {
+ 		vcc1v8_codec_en: vcc1v8-codec-en {
+ 			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_down>;
+ 		};
+ 	};
++
++	wireless-bluetooth {
++		bt_wake_pin: bt-wake-pin {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_host_wake_pin: bt-host-wake-pin {
++			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_reset_pin: bt-reset-pin {
++			rockchip,pins = <0 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&sdio0 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	disable-wp;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdio0_bus4 &sdio0_cmd &sdio0_clk>;
++	sd-uhs-sdr104;
++	status = "okay";
+ };
+ 
+ &sdmmc {
+@@ -400,6 +455,27 @@
+ 	status = "okay";
+ };
+ 
++&uart0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
++	uart-has-rtscts;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm4345c5";
++		clocks = <&rk818 1>;
++		clock-names = "lpo";
++		device-wakeup-gpios = <&gpio2 RK_PD2 GPIO_ACTIVE_HIGH>;
++		host-wakeup-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_HIGH>;
++		max-speed = <1500000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake_pin &bt_wake_pin &bt_reset_pin>;
++		shutdown-gpios = <&gpio0 RK_PB1 GPIO_ACTIVE_HIGH>;
++		vbat-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_1v8>;
++	};
++};
++
+ &uart2 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/057-arm64-dts-rockchip-enable-tsadc-for-ROCK-4C.patch b/target/linux/rockchip/patches-6.1/057-arm64-dts-rockchip-enable-tsadc-for-ROCK-4C.patch
new file mode 100644
index 00000000000..82c86cf4e6a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/057-arm64-dts-rockchip-enable-tsadc-for-ROCK-4C.patch
@@ -0,0 +1,30 @@
+From cc2633c6194c9dd199e3a662c70e7ee6139d45de Mon Sep 17 00:00:00 2001
+From: FUKAUMI Naoki <naoki@radxa.com>
+Date: Tue, 18 Oct 2022 07:22:42 +0000
+Subject: [PATCH 057/383] arm64: dts: rockchip: enable tsadc for ROCK 4C+
+
+add and enable Temperature Sensor ADC for Radxa ROCK 4C+
+
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Link: https://lore.kernel.org/r/20221018072242.2348995-1-naoki@radxa.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+@@ -600,6 +600,12 @@
+ 	status = "okay";
+ };
+ 
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <1>;
++	status = "okay";
++};
++
+ &u2phy0 {
+ 	status = "okay";
+ 
diff --git a/target/linux/rockchip/patches-6.1/193-arm64-dts-rockchip-add-rk3328-crypto-node.patch b/target/linux/rockchip/patches-6.1/058-arm64-dts-rockchip-add-rk3328-crypto-node.patch
similarity index 75%
rename from target/linux/rockchip/patches-6.1/193-arm64-dts-rockchip-add-rk3328-crypto-node.patch
rename to target/linux/rockchip/patches-6.1/058-arm64-dts-rockchip-add-rk3328-crypto-node.patch
index ef812d7cdc3..39b0a2187b7 100644
--- a/target/linux/rockchip/patches-6.1/193-arm64-dts-rockchip-add-rk3328-crypto-node.patch
+++ b/target/linux/rockchip/patches-6.1/058-arm64-dts-rockchip-add-rk3328-crypto-node.patch
@@ -1,12 +1,15 @@
-From e39620e4a26f650c72ad5624f27dfe964ccf3e03 Mon Sep 17 00:00:00 2001
+From a0402c4cf070edb8c0c3187a91f3359bfbf3535d Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:05 +0000
-Subject: [PATCH 43/49] arm64: dts: rockchip: add rk3328 crypto node
+Subject: [PATCH 058/383] arm64: dts: rockchip: add rk3328 crypto node
 
 rk3328 has a crypto IP handled by the rk3288 crypto driver so adds a
 node for it.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Link: https://lore.kernel.org/r/20220927075511.3147847-28-clabbe@baylibre.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk3328.dtsi | 11 +++++++++++
  1 file changed, 11 insertions(+)
diff --git a/target/linux/rockchip/patches-6.1/194-arm64-dts-rockchip-rk3399-add-crypto-node.patch b/target/linux/rockchip/patches-6.1/059-arm64-dts-rockchip-rk3399-add-crypto-node.patch
similarity index 77%
rename from target/linux/rockchip/patches-6.1/194-arm64-dts-rockchip-rk3399-add-crypto-node.patch
rename to target/linux/rockchip/patches-6.1/059-arm64-dts-rockchip-rk3399-add-crypto-node.patch
index c99019093bf..01b72f5a1de 100644
--- a/target/linux/rockchip/patches-6.1/194-arm64-dts-rockchip-rk3399-add-crypto-node.patch
+++ b/target/linux/rockchip/patches-6.1/059-arm64-dts-rockchip-rk3399-add-crypto-node.patch
@@ -1,13 +1,17 @@
-From e0d5c068d092b0c1a60f706cb18ac71ff4ec5268 Mon Sep 17 00:00:00 2001
+From d2fd927905eebc785819e714c7bee96508427de4 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:06 +0000
-Subject: [PATCH 44/49] arm64: dts: rockchip: rk3399: add crypto node
+Subject: [PATCH 059/383] arm64: dts: rockchip: rk3399: add crypto node
 
 The rk3399 has a crypto IP handled by the rk3288 crypto driver so adds a
 node for it.
 
 Tested-by Diederik de Haas <didi.debian@cknow.org>
+
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Link: https://lore.kernel.org/r/20220927075511.3147847-29-clabbe@baylibre.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk3399.dtsi | 20 ++++++++++++++++++++
  1 file changed, 20 insertions(+)
@@ -25,7 +29,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
 +		clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
 +		clock-names = "hclk_master", "hclk_slave", "sclk";
 +		resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
-+		reset-names = "master", "slave", "crypto-rst";
++		reset-names = "master", "lave", "crypto";
 +	};
 +
 +	crypto1: crypto@ff8b8000 {
@@ -35,7 +39,7 @@ Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
 +		clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
 +		clock-names = "hclk_master", "hclk_slave", "sclk";
 +		resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
-+		reset-names = "master", "slave", "crypto-rst";
++		reset-names = "master", "slave", "crypto";
 +	};
 +
  	i2c1: i2c@ff110000 {
diff --git a/target/linux/rockchip/patches-6.1/212-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch b/target/linux/rockchip/patches-6.1/060-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch
similarity index 87%
rename from target/linux/rockchip/patches-6.1/212-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch
rename to target/linux/rockchip/patches-6.1/060-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch
index b4615d4fde5..a38f95e308d 100644
--- a/target/linux/rockchip/patches-6.1/212-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch
+++ b/target/linux/rockchip/patches-6.1/060-arm64-dts-rockchip-fix-spdif-fe460000-ordering-on-rk.patch
@@ -1,7 +1,7 @@
-From 59e0ec5e5916ed4fac238a3da39aa0659831c41c Mon Sep 17 00:00:00 2001
+From 3e81ca36ea3d245709b3c7d0b0f905f9980ae7f0 Mon Sep 17 00:00:00 2001
 From: Heiko Stuebner <heiko@sntech.de>
 Date: Sun, 30 Oct 2022 20:34:42 +0100
-Subject: [PATCH 6/7] arm64: dts: rockchip: fix spdif@fe460000 ordering on
+Subject: [PATCH 060/383] arm64: dts: rockchip: fix spdif@fe460000 ordering on
  rk356x
 
 Move the node to its correct position, based on its
@@ -9,13 +9,14 @@ mmio-address.
 
 Link: https://lore.kernel.org/all/20221030193708.1671069-1-heiko@sntech.de
 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 28 ++++++++++++------------
  1 file changed, 14 insertions(+), 14 deletions(-)
 
 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1059,20 +1059,6 @@
+@@ -1051,20 +1051,6 @@
  		status = "disabled";
  	};
  
@@ -36,7 +37,7 @@ Signed-off-by: Heiko Stuebner <heiko@sntech.de>
  	i2s0_8ch: i2s@fe400000 {
  		compatible = "rockchip,rk3568-i2s-tdm";
  		reg = <0x0 0xfe400000 0x0 0x1000>;
-@@ -1151,6 +1137,20 @@
+@@ -1143,6 +1129,20 @@
  		#sound-dai-cells = <0>;
  		status = "disabled";
  	};
diff --git a/target/linux/rockchip/patches-6.1/213-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch b/target/linux/rockchip/patches-6.1/061-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
similarity index 86%
rename from target/linux/rockchip/patches-6.1/213-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
rename to target/linux/rockchip/patches-6.1/061-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
index 85b36e06523..e36cd16bb70 100644
--- a/target/linux/rockchip/patches-6.1/213-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
+++ b/target/linux/rockchip/patches-6.1/061-arm64-dts-rockchip-RK356x-Add-I2S2-device-node.patch
@@ -1,20 +1,21 @@
-From 6c51234cd4e1bfd637c3aab0a94893e832670fe5 Mon Sep 17 00:00:00 2001
+From d6fba133b7d06540f483d9add68a08d2d291ad81 Mon Sep 17 00:00:00 2001
 From: Shengyu Qu <wiagn233@outlook.com>
 Date: Sun, 30 Oct 2022 01:09:04 +0800
-Subject: [PATCH 7/7] arm64: dts: rockchip: RK356x: Add I2S2 device node
+Subject: [PATCH 061/383] arm64: dts: rockchip: RK356x: Add I2S2 device node
 
 This patch adds I2S2 device tree node for RK3566/RK3568.
 
 Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
 Link: https://lore.kernel.org/r/OS3P286MB259771C12F2B15A4DDF435FE98359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 22 ++++++++++++++++++++++
  1 file changed, 22 insertions(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1101,6 +1101,28 @@
+@@ -1093,6 +1093,28 @@
  		status = "disabled";
  	};
  
diff --git a/target/linux/rockchip/patches-6.1/062-arm64-dts-rockchip-Add-I2S2-node-for-RADXA-Rock-3A.patch b/target/linux/rockchip/patches-6.1/062-arm64-dts-rockchip-Add-I2S2-node-for-RADXA-Rock-3A.patch
new file mode 100644
index 00000000000..f05f37d4dc9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/062-arm64-dts-rockchip-Add-I2S2-node-for-RADXA-Rock-3A.patch
@@ -0,0 +1,31 @@
+From 3415222772da49df29e3f69299bc83e0bf23980c Mon Sep 17 00:00:00 2001
+From: Shengyu Qu <wiagn233@outlook.com>
+Date: Sun, 30 Oct 2022 01:09:06 +0800
+Subject: [PATCH 062/383] arm64: dts: rockchip: Add I2S2 node for RADXA Rock 3A
+
+This patch adds I2S2 node for Radxa Rock 3A's M.2 E key slot for
+Bluetooth PCM input. I2S2 is not used now, but could be configured
+for Bluetooth HFP over PCM in future patches.
+
+Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
+Link: https://lore.kernel.org/r/OS3P286MB259791E603F96942F51332D098359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -558,6 +558,11 @@
+ 	status = "okay";
+ };
+ 
++&i2s2_2ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
+ &mdio1 {
+ 	rgmii_phy1: ethernet-phy@0 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
diff --git a/target/linux/rockchip/patches-6.1/063-arm64-dts-rockchip-Add-nodes-for-SDIO-UART-Wi-Fi-Blu.patch b/target/linux/rockchip/patches-6.1/063-arm64-dts-rockchip-Add-nodes-for-SDIO-UART-Wi-Fi-Blu.patch
new file mode 100644
index 00000000000..bf7a5213e35
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/063-arm64-dts-rockchip-Add-nodes-for-SDIO-UART-Wi-Fi-Blu.patch
@@ -0,0 +1,116 @@
+From ca0aad3317915a384099e27252da5a2bd56983c2 Mon Sep 17 00:00:00 2001
+From: Shengyu Qu <wiagn233@outlook.com>
+Date: Sun, 30 Oct 2022 01:09:08 +0800
+Subject: [PATCH 063/383] arm64: dts: rockchip: Add nodes for SDIO/UART
+ Wi-Fi/Bluetooth modules to Radxa Rock 3A
+
+This patch adds related bus/pinctrl/power nodes to enable support for
+Radxa's Wi-Fi Bluetooth combo module.
+Tested with RADXA A6 module, which uses AP6275S (BCM43752A2)
+
+Signed-off-by: Shengyu Qu <wiagn233@outlook.com>
+Link: https://lore.kernel.org/r/OS3P286MB25972313C916A68698B1CD8698359@OS3P286MB2597.JPNP286.PROD.OUTLOOK.COM
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-rock-3a.dts      | 69 +++++++++++++++++++
+ 1 file changed, 69 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -60,6 +60,17 @@
+ 		};
+ 	};
+ 
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk809 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable>;
++		post-power-on-delay-ms = <100>;
++		power-off-delay-us = <5000000>;
++		reset-gpios = <&gpio3 RK_PD4 GPIO_ACTIVE_LOW>;
++	};
++
+ 	vcc12v_dcin: vcc12v-dcin-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc12v_dcin";
+@@ -655,6 +666,26 @@
+ 			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	bt {
++		bt_enable: bt-enable {
++			rockchip,pins = <4 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_host_wake: bt-host-wake {
++			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		bt_wake: bt-wake {
++			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable: wifi-enable {
++			rockchip,pins = <3 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
+@@ -699,12 +730,50 @@
+ 	status = "okay";
+ };
+ 
++&sdmmc2 {
++	supports-sdio;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc2m0_bus4 &sdmmc2m0_cmd &sdmmc2m0_clk>;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc3v3_sys>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
+ &tsadc {
+ 	rockchip,hw-tshut-mode = <1>;
+ 	rockchip,hw-tshut-polarity = <0>;
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
++	uart-has-rtscts;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&rk809 1>;
++		clock-names = "lpo";
++		device-wakeup-gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++		host-wakeup-gpios = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
++		shutdown-gpios = <&gpio4 RK_PB2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake &bt_wake &bt_enable>;
++		vbat-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcc_1v8>;
++		/* vddio comes from regulator on module, use IO bank voltage instead */
++	};
++};
++
+ &uart2 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/064-arm64-dts-rockchip-add-Anbernic-RG353V-and-RG353VS.patch b/target/linux/rockchip/patches-6.1/064-arm64-dts-rockchip-add-Anbernic-RG353V-and-RG353VS.patch
new file mode 100644
index 00000000000..90283a86a75
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/064-arm64-dts-rockchip-add-Anbernic-RG353V-and-RG353VS.patch
@@ -0,0 +1,575 @@
+From e45318fbf5941fc16483e9da65da867643b4cf91 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 28 Oct 2022 13:40:43 -0500
+Subject: [PATCH 064/383] arm64: dts: rockchip: add Anbernic RG353V and RG353VS
+
+Anbernic RG353V and RG353VS are both RK3566 based handheld gaming devices
+from Anbernic.
+
+They are functionally very similar to the RG353P with the following
+distinct differences:
+ - The battery size of the RG353V and RG353VS is 3200mAh instead of
+   3500mAh.
+ - The audio uses the PMIC's internal amplifier for a mono speaker
+   instead of an external amplifier with stereo speakers.
+ - The GPIOs for the R1 and R2 buttons are switched.
+
+As for the differences between the RG353V and RG353VS, they are as
+follows:
+ - The RG353VS has no touchscreen on i2c2.
+ - The RG353VS has no eMMC.
+ - The RG353VS has 1GB of RAM instead of 2GB.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221028184045.13113-3-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   2 +
+ .../dts/rockchip/rk3566-anbernic-rg353p.dts   |  83 +++++++------
+ .../dts/rockchip/rk3566-anbernic-rg353v.dts   | 114 ++++++++++++++++++
+ .../dts/rockchip/rk3566-anbernic-rg353vs.dts  |  87 +++++++++++++
+ .../dts/rockchip/rk3566-anbernic-rg353x.dtsi  |  60 +++++++++
+ .../dts/rockchip/rk3566-anbernic-rg503.dts    |  51 ++++++++
+ .../dts/rockchip/rk3566-anbernic-rgxx3.dtsi   |  46 -------
+ 7 files changed, 358 insertions(+), 85 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -63,6 +63,8 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
+@@ -5,7 +5,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/linux-event-codes.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+-#include "rk3566-anbernic-rgxx3.dtsi"
++#include "rk3566-anbernic-rg353x.dtsi"
+ 
+ / {
+ 	model = "RG353P";
+@@ -18,26 +18,47 @@
+ 		mmc3 = &sdmmc2;
+ 	};
+ 
+-	backlight: backlight {
+-		compatible = "pwm-backlight";
+-		power-supply = <&vcc_sys>;
+-		pwms = <&pwm4 0 25000 0>;
++	/* Channels reversed for both headphones and speakers. */
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "rk817_ext";
++		simple-audio-card,aux-devs = <&spk_amp>;
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphones",
++			"Speaker", "Internal Speakers";
++		simple-audio-card,routing =
++			"MICL", "Mic Jack",
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Internal Speakers", "Speaker Amp OUTL",
++			"Internal Speakers", "Speaker Amp OUTR",
++			"Speaker Amp INL", "HPOL",
++			"Speaker Amp INR", "HPOR";
++		simple-audio-card,pin-switches = "Internal Speakers";
++
++		simple-audio-card,codec {
++			sound-dai = <&rk817>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++	};
++
++	spk_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&spk_amp_enable_h>;
++		pinctrl-names = "default";
++		sound-name-prefix = "Speaker Amp";
+ 	};
+ };
+ 
+ &gpio_keys_control {
+-	button-a {
+-		gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+-		label = "EAST";
+-		linux,code = <BTN_EAST>;
+-	};
+-
+-	button-left {
+-		gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
+-		label = "DPAD-LEFT";
+-		linux,code = <BTN_DPAD_LEFT>;
+-	};
+-
+ 	button-r1 {
+ 		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
+ 		label = "TR";
+@@ -49,27 +70,6 @@
+ 		label = "TR2";
+ 		linux,code = <BTN_TR2>;
+ 	};
+-
+-	button-right {
+-		gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
+-		label = "DPAD-RIGHT";
+-		linux,code = <BTN_DPAD_RIGHT>;
+-	};
+-
+-	button-y {
+-		gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+-		label = "WEST";
+-		linux,code = <BTN_WEST>;
+-	};
+-};
+-
+-&i2c0 {
+-	/* This hardware is physically present but unused. */
+-	power-monitor@62 {
+-		compatible = "cellwise,cw2015";
+-		reg = <0x62>;
+-		status = "disabled";
+-	};
+ };
+ 
+ &i2c2 {
+@@ -78,8 +78,13 @@
+ 	status = "okay";
+ };
+ 
+-&pwm4 {
+-	status = "okay";
++&pinctrl {
++	audio-amplifier {
++		spk_amp_enable_h: spk-amp-enable-h {
++			rockchip,pins =
++				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &sdhci {
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
+@@ -0,0 +1,114 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3566-anbernic-rg353x.dtsi"
++
++/ {
++	model = "RG353V";
++	compatible = "anbernic,rg353v", "rockchip,rk3566";
++
++	aliases {
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc0;
++		mmc2 = &sdmmc1;
++		mmc3 = &sdmmc2;
++	};
++
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <3151000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <117000>;
++		voltage-max-design-microvolt = <4172000>;
++		voltage-min-design-microvolt = <3400000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =  <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
++					<3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
++					<3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
++					<3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
++					<3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
++					<3400000 0>;
++	};
++
++	/* Channels reversed for headphones. */
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "rk817_int";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphones",
++			"Speaker", "Internal Speakers";
++		simple-audio-card,routing =
++			"MICL", "Mic Jack",
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Internal Speakers", "SPKO";
++
++		simple-audio-card,codec {
++			sound-dai = <&rk817>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++	};
++};
++
++&gpio_keys_control {
++	button-r1 {
++		gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
++		label = "TR";
++		linux,code = <BTN_TR>;
++	};
++
++	button-r2 {
++		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
++		label = "TR2";
++		linux,code = <BTN_TR2>;
++	};
++};
++
++&i2c2 {
++	pintctrl-names = "default";
++	pinctrl-0 = <&i2c2m1_xfer>;
++	status = "okay";
++};
++
++&pinctrl {
++	touch {
++		touch_rst: touch-rst {
++			rockchip,pins =
++				<4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&rk817 {
++	rk817_charger: charger {
++		monitored-battery = <&battery>;
++		rockchip,resistor-sense-micro-ohms = <10000>;
++		rockchip,sleep-enter-current-microamp = <300000>;
++		rockchip,sleep-filter-current-microamp = <100000>;
++	};
++};
++
++&sdhci {
++	pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>;
++	pinctrl-names = "default";
++	bus-width = <8>;
++	mmc-hs200-1_8v;
++	non-removable;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353vs.dts
+@@ -0,0 +1,87 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3566-anbernic-rg353x.dtsi"
++
++/ {
++	model = "RG353VS";
++	compatible = "anbernic,rg353vs", "rockchip,rk3566";
++
++	aliases {
++		mmc0 = &sdmmc0;
++		mmc1 = &sdmmc1;
++		mmc2 = &sdmmc2;
++	};
++
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <3151000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <117000>;
++		voltage-max-design-microvolt = <4172000>;
++		voltage-min-design-microvolt = <3400000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =  <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
++					<3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
++					<3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
++					<3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
++					<3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
++					<3400000 0>;
++	};
++
++	/* Channels reversed for headphones. */
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "rk817_int";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphones",
++			"Speaker", "Internal Speakers";
++		simple-audio-card,routing =
++			"MICL", "Mic Jack",
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Internal Speakers", "SPKO";
++
++		simple-audio-card,codec {
++			sound-dai = <&rk817>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++	};
++};
++
++&gpio_keys_control {
++	button-r1 {
++		gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
++		label = "TR";
++		linux,code = <BTN_TR>;
++	};
++
++	button-r2 {
++		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
++		label = "TR2";
++		linux,code = <BTN_TR2>;
++	};
++};
++
++&rk817 {
++	rk817_charger: charger {
++		monitored-battery = <&battery>;
++		rockchip,resistor-sense-micro-ohms = <10000>;
++		rockchip,sleep-enter-current-microamp = <300000>;
++		rockchip,sleep-filter-current-microamp = <100000>;
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
+@@ -0,0 +1,60 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3566-anbernic-rgxx3.dtsi"
++
++/ {
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&vcc_sys>;
++		pwms = <&pwm4 0 25000 0>;
++	};
++};
++
++&cru {
++	assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
++	assigned-clock-rates = <1200000000>, <200000000>, <241500000>;
++};
++
++&gpio_keys_control {
++	button-a {
++		gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
++		label = "EAST";
++		linux,code = <BTN_EAST>;
++	};
++
++	button-left {
++		gpios = <&gpio3 RK_PA6 GPIO_ACTIVE_LOW>;
++		label = "DPAD-LEFT";
++		linux,code = <BTN_DPAD_LEFT>;
++	};
++
++	button-right {
++		gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_LOW>;
++		label = "DPAD-RIGHT";
++		linux,code = <BTN_DPAD_RIGHT>;
++	};
++
++	button-y {
++		gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
++		label = "WEST";
++		linux,code = <BTN_WEST>;
++	};
++};
++
++&i2c0 {
++	/* This hardware is physically present but unused. */
++	power-monitor@62 {
++		compatible = "cellwise,cw2015";
++		reg = <0x62>;
++		status = "disabled";
++	};
++};
++
++&pwm4 {
++	status = "okay";
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+@@ -29,6 +29,50 @@
+ 		cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ 		num-chipselects = <0>;
+ 	};
++
++	/* Channels reversed for both headphones and speakers. */
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "rk817_ext";
++		simple-audio-card,aux-devs = <&spk_amp>;
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphones",
++			"Speaker", "Internal Speakers";
++		simple-audio-card,routing =
++			"MICL", "Mic Jack",
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Internal Speakers", "Speaker Amp OUTL",
++			"Internal Speakers", "Speaker Amp OUTR",
++			"Speaker Amp INL", "HPOL",
++			"Speaker Amp INR", "HPOR";
++		simple-audio-card,pin-switches = "Internal Speakers";
++
++		simple-audio-card,codec {
++			sound-dai = <&rk817>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++	};
++
++	spk_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&spk_amp_enable_h>;
++		pinctrl-names = "default";
++		sound-name-prefix = "Speaker Amp";
++	};
++};
++
++&cru {
++	assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
++	assigned-clock-rates = <1200000000>, <200000000>, <500000000>;
+ };
+ 
+ &gpio_keys_control {
+@@ -76,6 +120,13 @@
+ };
+ 
+ &pinctrl {
++	audio-amplifier {
++		spk_amp_enable_h: spk-amp-enable-h {
++			rockchip,pins =
++				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	gpio-spi {
+ 		spi_pins: spi-pins {
+ 			rockchip,pins =
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
+@@ -217,37 +217,6 @@
+ 		};
+ 	};
+ 
+-	/* Channels reversed for both headphones and speakers. */
+-	sound {
+-		compatible = "simple-audio-card";
+-		simple-audio-card,name = "anbernic_rk817";
+-		simple-audio-card,aux-devs = <&spk_amp>;
+-		simple-audio-card,format = "i2s";
+-		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
+-		simple-audio-card,mclk-fs = <256>;
+-		simple-audio-card,widgets =
+-			"Microphone", "Mic Jack",
+-			"Headphone", "Headphones",
+-			"Speaker", "Internal Speakers";
+-		simple-audio-card,routing =
+-			"MICL", "Mic Jack",
+-			"Headphones", "HPOL",
+-			"Headphones", "HPOR",
+-			"Internal Speakers", "Speaker Amp OUTL",
+-			"Internal Speakers", "Speaker Amp OUTR",
+-			"Speaker Amp INL", "HPOL",
+-			"Speaker Amp INR", "HPOR";
+-		simple-audio-card,pin-switches = "Internal Speakers";
+-
+-		simple-audio-card,codec {
+-			sound-dai = <&rk817>;
+-		};
+-
+-		simple-audio-card,cpu {
+-			sound-dai = <&i2s1_8ch>;
+-		};
+-	};
+-
+ 	sdio_pwrseq: sdio-pwrseq {
+ 		compatible = "mmc-pwrseq-simple";
+ 		clocks = <&rk817 1>;
+@@ -258,14 +227,6 @@
+ 		reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_LOW>;
+ 	};
+ 
+-	spk_amp: audio-amplifier {
+-		compatible = "simple-audio-amplifier";
+-		enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
+-		pinctrl-0 = <&spk_amp_enable_h>;
+-		pinctrl-names = "default";
+-		sound-name-prefix = "Speaker Amp";
+-	};
+-
+ 	vcc3v3_lcd0_n: regulator-vcc3v3-lcd0 {
+ 		compatible = "regulator-fixed";
+ 		gpio = <&gpio0 RK_PC2 GPIO_ACTIVE_HIGH>;
+@@ -607,13 +568,6 @@
+ };
+ 
+ &pinctrl {
+-	audio-amplifier {
+-		spk_amp_enable_h: spk-amp-enable-h {
+-			rockchip,pins =
+-				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-	};
+-
+ 	gpio-btns {
+ 		btn_pins_ctrl: btn-pins-ctrl {
+ 			rockchip,pins =
diff --git a/target/linux/rockchip/patches-6.1/065-arm64-dts-rockchip-add-rk817-chg-to-RG353P-and-RG503.patch b/target/linux/rockchip/patches-6.1/065-arm64-dts-rockchip-add-rk817-chg-to-RG353P-and-RG503.patch
new file mode 100644
index 00000000000..52aff0935a0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/065-arm64-dts-rockchip-add-rk817-chg-to-RG353P-and-RG503.patch
@@ -0,0 +1,104 @@
+From 10f47903476d674e950e6996b5ae02698f4bfbfb Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 28 Oct 2022 13:40:44 -0500
+Subject: [PATCH 065/383] arm64: dts: rockchip: add rk817 chg to RG353P and
+ RG503
+
+Add support for the internal battery and charger for the Anbernic
+RG353P and RG503. Battery values are taken from the BSP Kernel
+device tree.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221028184045.13113-4-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3566-anbernic-rg353p.dts   | 28 +++++++++++++++++++
+ .../dts/rockchip/rk3566-anbernic-rg503.dts    | 28 +++++++++++++++++++
+ 2 files changed, 56 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
+@@ -18,6 +18,25 @@
+ 		mmc3 = &sdmmc2;
+ 	};
+ 
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <3472000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <117000>;
++		voltage-max-design-microvolt = <4172000>;
++		voltage-min-design-microvolt = <3400000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =  <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
++					<3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
++					<3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
++					<3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
++					<3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
++					<3400000 0>;
++	};
++
+ 	/* Channels reversed for both headphones and speakers. */
+ 	sound {
+ 		compatible = "simple-audio-card";
+@@ -87,6 +106,15 @@
+ 	};
+ };
+ 
++&rk817 {
++	rk817_charger: charger {
++		monitored-battery = <&battery>;
++		rockchip,resistor-sense-micro-ohms = <10000>;
++		rockchip,sleep-enter-current-microamp = <300000>;
++		rockchip,sleep-filter-current-microamp = <100000>;
++	};
++};
++
+ &sdhci {
+ 	pinctrl-0 = <&emmc_bus8>, <&emmc_clk>, <&emmc_cmd>, <&emmc_datastrobe>, <&emmc_rstnout>;
+ 	pinctrl-names = "default";
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+@@ -17,6 +17,25 @@
+ 		mmc2 = &sdmmc2;
+ 	};
+ 
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <3472000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <117000>;
++		voltage-max-design-microvolt = <4172000>;
++		voltage-min-design-microvolt = <3400000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =	<4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
++					<3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
++					<3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
++					<3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
++					<3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
++					<3400000 0>;
++	};
++
+ 	gpio_spi: spi {
+ 		compatible = "spi-gpio";
+ 		pinctrl-names = "default";
+@@ -136,3 +155,12 @@
+ 		};
+ 	};
+ };
++
++&rk817 {
++	rk817_charger: charger {
++		monitored-battery = <&battery>;
++		rockchip,resistor-sense-micro-ohms = <10000>;
++		rockchip,sleep-enter-current-microamp = <300000>;
++		rockchip,sleep-filter-current-microamp = <100000>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/066-arm64-dts-rockchip-add-poll-interval-to-RGxx3-device.patch b/target/linux/rockchip/patches-6.1/066-arm64-dts-rockchip-add-poll-interval-to-RGxx3-device.patch
new file mode 100644
index 00000000000..665b526fe28
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/066-arm64-dts-rockchip-add-poll-interval-to-RGxx3-device.patch
@@ -0,0 +1,27 @@
+From 3bde999f5ffca07dee0c9fe900ccb9b29d41c464 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 28 Oct 2022 13:40:45 -0500
+Subject: [PATCH 066/383] arm64: dts: rockchip: add poll-interval to RGxx3
+ devices
+
+Add adc-joystick polling for all Anbernic RGxx3 based devices.
+They are all functionally identical in how they work.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221028184045.13113-5-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
+@@ -22,6 +22,7 @@
+ 			      <&adc_mux 3>;
+ 		pinctrl-0 = <&joy_mux_en>;
+ 		pinctrl-names = "default";
++		poll-interval = <60>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
diff --git a/target/linux/rockchip/patches-6.1/067-arm64-dts-rockchip-Update-joystick-to-polled-for-OG2.patch b/target/linux/rockchip/patches-6.1/067-arm64-dts-rockchip-Update-joystick-to-polled-for-OG2.patch
new file mode 100644
index 00000000000..9b1abcbacf1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/067-arm64-dts-rockchip-Update-joystick-to-polled-for-OG2.patch
@@ -0,0 +1,28 @@
+From cfd8ccee761664838849b4ebb647555b55c2b702 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Tue, 16 Aug 2022 16:04:40 -0500
+Subject: [PATCH 067/383] arm64: dts: rockchip: Update joystick to polled for
+ OG2
+
+Update the Odroid Go Advance to use "poll-interval" from the
+adc-joystick driver.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Link: https://lore.kernel.org/r/20220816210440.14260-4-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+@@ -26,6 +26,7 @@
+ 		compatible = "adc-joystick";
+ 		io-channels = <&saradc 1>,
+ 			      <&saradc 2>;
++		poll-interval = <60>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+ 
diff --git a/target/linux/rockchip/patches-6.1/068-arm64-dts-rockchip-enable-pcie2-on-rk3566-roc-pc.patch b/target/linux/rockchip/patches-6.1/068-arm64-dts-rockchip-enable-pcie2-on-rk3566-roc-pc.patch
new file mode 100644
index 00000000000..5ff7d308ab1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/068-arm64-dts-rockchip-enable-pcie2-on-rk3566-roc-pc.patch
@@ -0,0 +1,80 @@
+From c0602fc3d12777ac879ed9d121c46a7bc1e76fce Mon Sep 17 00:00:00 2001
+From: Furkan Kardame <f.kardame@manjaro.org>
+Date: Wed, 26 Oct 2022 20:21:53 +0300
+Subject: [PATCH 068/383] arm64: dts: rockchip: enable pcie2 on rk3566-roc-pc
+
+This patch adds nodes needed for pcie2
+to work on rk3566-roc-pc
+
+Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
+Link: https://lore.kernel.org/r/20221026172152.64513-1-f.kardame@manjaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 34 +++++++++++++++++++
+ 1 file changed, 34 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+@@ -82,6 +82,18 @@
+ 		vin-supply = <&usb_5v>;
+ 	};
+ 
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_enable_h>;
++		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
+ 	vcc3v3_sys: vcc3v3-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+@@ -122,6 +134,10 @@
+ 	status = "okay";
+ };
+ 
++&combphy2 {
++	status = "okay";
++};
++
+ &cpu0 {
+ 	cpu-supply = <&vdd_cpu>;
+ };
+@@ -443,6 +459,14 @@
+ 	};
+ };
+ 
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_reset_h>;
++	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
+ &pinctrl {
+ 	bt {
+ 		bt_enable_h: bt-enable-h {
+@@ -464,6 +488,16 @@
+ 		};
+ 	};
+ 
++	pcie {
++		pcie_enable_h: pcie-enable-h {
++			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie_reset_h: pcie-reset-h {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int: pmic_int {
+ 			rockchip,pins =
diff --git a/target/linux/rockchip/patches-6.1/070-arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch b/target/linux/rockchip/patches-6.1/070-arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch
new file mode 100644
index 00000000000..d3e510d2b05
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/070-arm64-dts-rockchip-Enable-video-output-and-HDMI-on-S.patch
@@ -0,0 +1,91 @@
+From a98d2da380eb8fea26997e7fc0a52a3fb60cc3e2 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 12 Nov 2022 17:03:59 +0100
+Subject: [PATCH 070/383] arm64: dts: rockchip: Enable video output and HDMI on
+ SOQuartz
+
+This patch adds and enables the necessary device tree nodes to
+enable video output and HDMI functionality on the SOQuartz module.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221112160404.70868-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3566-soquartz.dtsi    | 47 +++++++++++++++++++
+ 1 file changed, 47 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+@@ -4,6 +4,7 @@
+ 
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
+ #include "rk3566.dtsi"
+ 
+ / {
+@@ -28,6 +29,17 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -151,6 +163,24 @@
+ 	status = "okay";
+ };
+ 
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -616,3 +646,20 @@
+ &usb_host0_xhci {
+ 	status = "disabled";
+ };
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/071-arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch b/target/linux/rockchip/patches-6.1/071-arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch
new file mode 100644
index 00000000000..315f1a8198b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/071-arm64-dts-rockchip-Enable-HDMI-sound-on-SOQuartz.patch
@@ -0,0 +1,40 @@
+From 75454028df75b71285e477ac422ef2fba6b83bf0 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 12 Nov 2022 17:04:00 +0100
+Subject: [PATCH 071/383] arm64: dts: rockchip: Enable HDMI sound on SOQuartz
+
+This patch enables the i2s0 node on SOQuartz, which is responsible
+for hdmi audio, and adds an hdmi-sound node to enable said audio.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221112160404.70868-4-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+@@ -181,6 +181,10 @@
+ 	};
+ };
+ 
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -449,6 +453,10 @@
+ 	status = "disabled";
+ };
+ 
++&i2s0_8ch {
++	status = "okay";
++};
++
+ /*
+  * i2s1_8ch is exposed on CM1 / Module1A
+  * pin 24 - i2s1_sdi1_m1
diff --git a/target/linux/rockchip/patches-6.1/072-arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch b/target/linux/rockchip/patches-6.1/072-arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch
new file mode 100644
index 00000000000..5e90a0900de
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/072-arm64-dts-rockchip-Enable-PCIe-2-on-SOQuartz-CM4IO.patch
@@ -0,0 +1,76 @@
+From e038bf77c459d37d636f990b1ed3e213422c2b44 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Sat, 12 Nov 2022 17:04:01 +0100
+Subject: [PATCH 072/383] arm64: dts: rockchip: Enable PCIe 2 on SOQuartz CM4IO
+
+This patch enables the PCIe2 on the CM4IO board when paired with
+a SOQuartz CM4 System-on-Module board. combphy2 also needs to be
+enabled in this case to make the PHY work for this.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221112160404.70868-5-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3566-soquartz-cm4.dts     | 11 +++++++++++
+ arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi | 15 +++++++++++++++
+ 2 files changed, 26 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
+@@ -40,6 +40,12 @@
+ 	};
+ };
+ 
++/* phy for pcie */
++&combphy2 {
++	phy-supply = <&vcc3v3_sys>;
++	status = "okay";
++};
++
+ &gmac1 {
+ 	status = "okay";
+ };
+@@ -115,6 +121,11 @@
+ 	status = "okay";
+ };
+ 
++&pcie2x1 {
++	vpcie3v3-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
+ &rgmii_phy1 {
+ 	status = "okay";
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
+@@ -490,6 +490,12 @@
+ 	};
+ };
+ 
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie_reset_h>;
++	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++};
++
+ &pinctrl {
+ 	bt {
+ 		bt_enable_h: bt-enable-h {
+@@ -515,6 +521,15 @@
+ 		};
+ 	};
+ 
++	pcie {
++		pcie_clkreq_h: pcie-clkreq-h {
++			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++		pcie_reset_h: pcie-reset-h {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
diff --git a/target/linux/rockchip/patches-6.1/073-arm64-dts-rockchip-Add-dts-for-rockchip-rk3566-box-d.patch b/target/linux/rockchip/patches-6.1/073-arm64-dts-rockchip-Add-dts-for-rockchip-rk3566-box-d.patch
new file mode 100644
index 00000000000..92eacddabe0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/073-arm64-dts-rockchip-Add-dts-for-rockchip-rk3566-box-d.patch
@@ -0,0 +1,548 @@
+From 4425c566dc70b1dcf7ebba9ea2bee1386a29843d Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@163.com>
+Date: Sat, 5 Nov 2022 18:00:12 +0800
+Subject: [PATCH 073/383] arm64: dts: rockchip: Add dts for rockchip rk3566 box
+ demo board
+
+This is a rk3566 tv box  evaluation demo board.
+
+Specification:
+- Rockchip RK3566
+- DDR4 4GB
+- TF sd scard slot
+- eMMC
+- AP6398S for WiFi + BT
+- Gigabit ethernet
+- HDMI out
+- USB HOST 2.0 x 2
+- USB 3.0 x 1
+- USB OTG 2.0  x 1
+- 12V DC Power supply
+
+Signed-off-by: Piotr Oniszczuk <piotr.oniszczuk@gmail.com>
+Signed-off-by: Andy Yan <andyshrk@163.com>
+Link: https://lore.kernel.org/r/20221105100012.958252-1-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3566-box-demo.dts     | 503 ++++++++++++++++++
+ 2 files changed, 504 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -72,6 +72,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+@@ -0,0 +1,503 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/*
++ * Author: Piotr Oniszczuk piotr.oniszczuk@gmail.com
++ * Based on Quartz64 DT by: Peter Geis pgwipeout@gmail.com
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3566.dtsi"
++
++/ {
++	model = "Rockchip RK3566 BOX DEMO Board";
++	compatible = "rockchip,rk3566-box-demo", "rockchip,rk3566";
++
++	aliases {
++		ethernet0 = &gmac1;
++		mmc0 = &sdmmc0;
++		mmc1 = &sdmmc1;
++		mmc2 = &sdhci;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gmac1_clkin: external-gmac1-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac1_clkin";
++		#clock-cells = <0>;
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio4 RK_PC3 GPIO_ACTIVE_LOW>;
++		pinctrl-0 = <&ir_int>;
++		linux,rc-map-name = "rc-beelink-gs1";
++		status = "okay";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led_work: led-0 {
++			gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
++			function = LED_FUNCTION_HEARTBEAT;
++			color = <LED_COLOR_ID_BLUE>;
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&led_work_en>;
++		};
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		status = "okay";
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&pmucru CLK_RTC_32K>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_enable_h &wifi_32k>;
++		reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
++	};
++
++	spdif_dit: spdif-dit {
++		compatible = "linux,spdif-dit";
++		#sound-dai-cells = <0>;
++	};
++
++	spdif_sound: spdif-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "SPDIF";
++
++		simple-audio-card,cpu {
++			sound-dai = <&spdif>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&spdif_dit>;
++		};
++	};
++
++	vcc12v0_dcin: regulator-vcc12v0-dcin {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v0_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc5v0_sys: regulator-vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc12v0_dcin>;
++	};
++
++	vcc3v3_sys: regulator-vcc3v3-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc12v0_dcin>;
++	};
++
++	vcc_3v3: regulator-vcc-3v3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_3v3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcc5v0_usb_host: regulator-vcc5v0-usb-host {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_host_en>;
++		regulator-name = "vcc5v0_usb_host";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_usb2_otg: regulator-vcc5v0-usb2-otg {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb2_otg_en>;
++		regulator-name = "vcc5v0_usb_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcca_1v8: regulator-vcca-1v8 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vdda_0v9: regulator-vdda-0v9 {
++		compatible = "regulator-fixed";
++		regulator-name = "vdda_0v9";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vdd_fixed: regulator-vdd-fixed {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd_fixed";
++		regulator-min-microvolt = <950000>;
++		regulator-max-microvolt = <950000>;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vdd_cpu: regulator-vdd-cpu {
++		compatible = "pwm-regulator";
++		pwms = <&pwm0 0 5000 1>;
++		regulator-name = "vdd_cpu";
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1200000>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-settling-time-up-us = <250>;
++		pwm-supply = <&vcc5v0_sys>;
++	};
++
++	vdd_logic: regulator-vdd-logic {
++		compatible = "pwm-regulator";
++		pwms = <&pwm1 0 5000 1>;
++		regulator-name = "vdd_logic";
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1100000>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-settling-time-up-us = <250>;
++		pwm-supply = <&vcc5v0_sys>;
++	};
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gmac1 {
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents =  <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
++	phy-mode = "rgmii";
++	clock_in_out = "input";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m1_miim
++		    &gmac1m1_tx_bus2
++		    &gmac1m1_rx_bus2
++		    &gmac1m1_rgmii_clk
++		    &gmac1m1_rgmii_bus
++		    &gmac1m1_clkinout>;
++	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++
++	tx_delay = <0x4f>;
++	rx_delay = <0x2d>;
++	phy-handle = <&rgmii_phy1>;
++	status = "okay";
++};
++
++&mdio1 {
++	rgmii_phy1: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x1>;
++	};
++};
++
++&hdmi {
++	assigned-clocks = <&cru CLK_HDMI_CEC>;
++	assigned-clock-rates = <32768>;
++	avdd-0v9-supply = <&vdda_0v9>;
++	avdd-1v8-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&gpu {
++	status = "okay";
++};
++
++&i2s0_8ch {
++	status = "okay";
++};
++
++&i2s1_8ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&pinctrl {
++	bt {
++		bt_enable_h: bt-enable-h {
++			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_host_wake_l: bt-host-wake-l {
++			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++
++		bt_wake_l: bt-wake-l {
++			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wifi_32k: wifi-32k {
++			rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb_host_en: vcc5v0_usb_host_en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_usb2_otg_en: vcc5v0_usb2_otg_en {
++			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++	};
++
++	ir {
++		ir_int: ir-int {
++			rockchip,pins = <4 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	led {
++		led_work_en: led_work_en {
++			rockchip,pins = <0 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	mmc-hs200-1_8v;
++	non-removable;
++	status = "okay";
++};
++
++&sdmmc0 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++	disable-wp;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	vmmc-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&sdmmc1 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	disable-wp;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&spdif {
++	status = "okay";
++};
++
++&spi1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
++};
++
++&tsadc {
++	/* tshut mode 0:CRU 1:GPIO */
++	rockchip,hw-tshut-mode = <1>;
++	/* tshut polarity 0:LOW 1:HIGH */
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
++	status = "okay";
++	uart-has-rtscts;
++
++	bluetooth {
++		compatible = "brcm,bcm43438-bt";
++		clocks = <&pmucru CLK_RTC_32K>;
++		clock-names = "ext_clock";
++		device-wake-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
++		shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
++		vbat-supply = <&vcc3v3_sys>;
++		vddio-supply = <&vcca_1v8>;
++	};
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
++
++&vpu {
++	status = "okay";
++};
++
++&vdpu_mmu {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	vbus-supply = <&vcc5v0_usb2_otg>;
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb_host1_xhci {
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/074-arm64-dts-rockchip-Add-HDMI-supplies-on-Rock960.patch b/target/linux/rockchip/patches-6.1/074-arm64-dts-rockchip-Add-HDMI-supplies-on-Rock960.patch
new file mode 100644
index 00000000000..e436c0dd44b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/074-arm64-dts-rockchip-Add-HDMI-supplies-on-Rock960.patch
@@ -0,0 +1,30 @@
+From 78d6459cdd2cd5b9b110fa21bb3818164005d27e Mon Sep 17 00:00:00 2001
+From: Peter Robinson <pbrobinson@gmail.com>
+Date: Wed, 2 Nov 2022 14:32:42 +0000
+Subject: [PATCH 074/383] arm64: dts: rockchip: Add HDMI supplies on Rock960
+
+Add the avdd-0v9-supply and avdd-1v8-supply regulators to
+hdmi node for Rock960 to silence the following dmesg warning.
+
+[    6.582782] dwhdmi-rockchip ff940000.hdmi: supply avdd-0v9 not found, using dummy regulator
+[    6.583094] dwhdmi-rockchip ff940000.hdmi: supply avdd-1v8 not found, using dummy regulator
+
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+Link: https://lore.kernel.org/r/20221102143242.1126229-1-pbrobinson@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi
+@@ -128,6 +128,8 @@
+ };
+ 
+ &hdmi {
++	avdd-0v9-supply = <&vcca0v9_hdmi>;
++	avdd-1v8-supply = <&vcca1v8_hdmi>;
+ 	ddc-i2c-bus = <&i2c3>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&hdmi_cec>;
diff --git a/target/linux/rockchip/patches-6.1/075-arm64-dts-rockchip-Add-support-of-external-clock-to-.patch b/target/linux/rockchip/patches-6.1/075-arm64-dts-rockchip-Add-support-of-external-clock-to-.patch
new file mode 100644
index 00000000000..035c44dcf1c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/075-arm64-dts-rockchip-Add-support-of-external-clock-to-.patch
@@ -0,0 +1,55 @@
+From ada7ae999bade4b7525e41404b8af9f49c0476ba Mon Sep 17 00:00:00 2001
+From: Anand Moon <linux.amoon@gmail.com>
+Date: Wed, 16 Nov 2022 20:01:44 +0000
+Subject: [PATCH 075/383] arm64: dts: rockchip: Add support of external clock
+ to ethernet node on Rock 3A SBC
+
+Add support of external clock gmac1_clkin which is used as input clock
+to ethernet node.
+
+Signed-off-by: Anand Moon <linux.amoon@gmail.com>
+Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
+Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20221116200150.4657-3-linux.amoon@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 13 ++++++++++---
+ 1 file changed, 10 insertions(+), 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -32,6 +32,13 @@
+ 		};
+ 	};
+ 
++	gmac1_clkin: external-gmac1-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac1_clkin";
++		#clock-cells = <0>;
++	};
++
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -249,9 +256,8 @@
+ 
+ &gmac1 {
+ 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+-	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
+-	assigned-clock-rates = <0>, <125000000>;
+-	clock_in_out = "output";
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
++	clock_in_out = "input";
+ 	phy-handle = <&rgmii_phy1>;
+ 	phy-mode = "rgmii-id";
+ 	pinctrl-names = "default";
+@@ -259,6 +265,7 @@
+ 		     &gmac1m1_tx_bus2
+ 		     &gmac1m1_rx_bus2
+ 		     &gmac1m1_rgmii_clk
++		     &gmac1m1_clkinout
+ 		     &gmac1m1_rgmii_bus>;
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/076-arm64-dts-rockchip-Add-support-of-regulator-for-ethe.patch b/target/linux/rockchip/patches-6.1/076-arm64-dts-rockchip-Add-support-of-regulator-for-ethe.patch
new file mode 100644
index 00000000000..81498ddad31
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/076-arm64-dts-rockchip-Add-support-of-regulator-for-ethe.patch
@@ -0,0 +1,31 @@
+From 63923db994aabd2f2124fc78b2fd001c4f4aaf82 Mon Sep 17 00:00:00 2001
+From: Anand Moon <linux.amoon@gmail.com>
+Date: Wed, 16 Nov 2022 20:01:45 +0000
+Subject: [PATCH 076/383] arm64: dts: rockchip: Add support of regulator for
+ ethernet node on Rock 3A SBC
+
+Add regulator support for ethernet node
+
+Fix following warning.
+[    7.365199] rk_gmac-dwmac fe010000.ethernet: no regulator found
+
+Signed-off-by: Anand Moon <linux.amoon@gmail.com>
+Acked-by: Michael Riesch <michael.riesch@wolfvision.net>
+Tested-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20221116200150.4657-4-linux.amoon@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -260,6 +260,7 @@
+ 	clock_in_out = "input";
+ 	phy-handle = <&rgmii_phy1>;
+ 	phy-mode = "rgmii-id";
++	phy-supply = <&vcc_3v3>;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac1m1_miim
+ 		     &gmac1m1_tx_bus2
diff --git a/target/linux/rockchip/patches-6.1/077-arm64-dts-rockchip-Move-most-of-Odroid-Go-Advance-DT.patch b/target/linux/rockchip/patches-6.1/077-arm64-dts-rockchip-Move-most-of-Odroid-Go-Advance-DT.patch
new file mode 100644
index 00000000000..437b8629557
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/077-arm64-dts-rockchip-Move-most-of-Odroid-Go-Advance-DT.patch
@@ -0,0 +1,1280 @@
+From ee0ca0f4f7d59c10264b2fe88f463199550e5438 Mon Sep 17 00:00:00 2001
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+Date: Thu, 17 Nov 2022 22:59:50 +0100
+Subject: [PATCH 077/383] arm64: dts: rockchip: Move most of Odroid Go Advance
+ DTS into a DTSI
+
+To support more devices that are clones of this device or minor
+revisions without duplication move most of go2's dts into a dtsi file.
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Link: https://lore.kernel.org/r/20221117215954.4114202-2-maccraft123mc@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3326-odroid-go.dtsi   | 600 +++++++++++++++++
+ .../boot/dts/rockchip/rk3326-odroid-go2.dts   | 619 +-----------------
+ 2 files changed, 608 insertions(+), 611 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+@@ -0,0 +1,600 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Hardkernel Co., Ltd
++ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
++ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3326.dtsi"
++
++/ {
++	aliases {
++		mmc0 = &sdmmc;
++	};
++
++	chosen {
++		stdout-path = "serial2:115200n8";
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&vcc_bl>;
++		pwms = <&pwm1 0 25000 0>;
++	};
++
++	builtin_gamepad: gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&btn_pins>;
++
++		button-sw1 {
++			gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
++			label = "DPAD-UP";
++			linux,code = <BTN_DPAD_UP>;
++		};
++		button-sw2 {
++			gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
++			label = "DPAD-DOWN";
++			linux,code = <BTN_DPAD_DOWN>;
++		};
++		button-sw3 {
++			gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
++			label = "DPAD-LEFT";
++			linux,code = <BTN_DPAD_LEFT>;
++		};
++		button-sw4 {
++			gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
++			label = "DPAD-RIGHT";
++			linux,code = <BTN_DPAD_RIGHT>;
++		};
++		button-sw5 {
++			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
++			label = "BTN-A";
++			linux,code = <BTN_EAST>;
++		};
++		button-sw6 {
++			gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
++			label = "BTN-B";
++			linux,code = <BTN_SOUTH>;
++		};
++		button-sw7 {
++			gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
++			label = "BTN-Y";
++			linux,code = <BTN_WEST>;
++		};
++		button-sw8 {
++			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
++			label = "BTN-X";
++			linux,code = <BTN_NORTH>;
++		};
++		btn_f1: button-sw9 {
++			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
++			label = "F1";
++			linux,code = <BTN_TRIGGER_HAPPY1>;
++		};
++		btn_f2: button-sw10 {
++			gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
++			label = "F2";
++			linux,code = <BTN_TRIGGER_HAPPY2>;
++		};
++		btn_f3: button-sw11 {
++			gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
++			label = "F3";
++			linux,code = <BTN_TRIGGER_HAPPY3>;
++		};
++		btn_f4: button-sw12 {
++			gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
++			label = "F4";
++			linux,code = <BTN_TRIGGER_HAPPY4>;
++		};
++		btn_f5: button-sw13 {
++			gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
++			label = "F5";
++			linux,code = <BTN_TRIGGER_HAPPY5>;
++		};
++		btn_f6: button-sw14 {
++			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
++			label = "F6";
++			linux,code = <BTN_TRIGGER_HAPPY6>;
++		};
++		button-sw15 {
++			gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
++			label = "TOP-LEFT";
++			linux,code = <BTN_TL>;
++		};
++		button-sw16 {
++			gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
++			label = "TOP-RIGHT";
++			linux,code = <BTN_TR>;
++		};
++	};
++
++	leds: gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&blue_led_pin>;
++
++		blue_led: led-0 {
++			label = "blue:heartbeat";
++			gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	rk817-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "Analog";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphones",
++			"Speaker", "Speaker";
++		simple-audio-card,routing =
++			"MICL", "Mic Jack",
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Speaker", "SPKO";
++
++		simple-audio-card,codec {
++			sound-dai = <&rk817>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_2ch>;
++		};
++	};
++
++	vccsys: vccsys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v8_sys";
++		regulator-always-on;
++		regulator-min-microvolt = <3800000>;
++		regulator-max-microvolt = <3800000>;
++	};
++
++	vcc_host: vcc_host {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_host";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++
++		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++		enable-active-high;
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&usb_midu>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cru {
++	assigned-clocks = <&cru PLL_NPLL>,
++		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
++		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
++		<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
++		<&cru PLL_CPLL>;
++
++	assigned-clock-rates = <1188000000>,
++		<200000000>, <200000000>,
++		<150000000>, <150000000>,
++		<100000000>, <200000000>,
++		<17000000>;
++};
++
++&display_subsystem {
++	status = "okay";
++};
++
++&dsi {
++	status = "okay";
++
++	ports {
++		mipi_out: port@1 {
++			reg = <1>;
++
++			mipi_out_panel: endpoint {
++				remote-endpoint = <&mipi_in_panel>;
++			};
++		};
++	};
++
++	internal_display: panel@0 {
++		reg = <0>;
++		backlight = <&backlight>;
++		iovcc-supply = <&vcc_lcd>;
++		reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
++		rotation = <270>;
++		vdd-supply = <&vcc_lcd>;
++
++		port {
++			mipi_in_panel: endpoint {
++				remote-endpoint = <&mipi_out_panel>;
++			};
++		};
++	};
++};
++
++&dsi_dphy {
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_logic>;
++	status = "okay";
++};
++
++&i2c0 {
++	clock-frequency = <400000>;
++	i2c-scl-falling-time-ns = <16>;
++	i2c-scl-rising-time-ns = <280>;
++	status = "okay";
++
++	rk817: pmic@20 {
++		compatible = "rockchip,rk817";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
++		clock-output-names = "rk808-clkout1", "xin32k";
++		clock-names = "mclk";
++		clocks = <&cru SCLK_I2S1_OUT>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
++		wakeup-source;
++		#clock-cells = <1>;
++		#sound-dai-cells = <0>;
++
++		vcc1-supply = <&vccsys>;
++		vcc2-supply = <&vccsys>;
++		vcc3-supply = <&vccsys>;
++		vcc4-supply = <&vccsys>;
++		vcc5-supply = <&vccsys>;
++		vcc6-supply = <&vccsys>;
++		vcc7-supply = <&vccsys>;
++		vcc8-supply = <&vccsys>;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <1150000>;
++				regulator-ramp-delay = <6001>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vdd_arm: DCDC_REG2 {
++				regulator-name = "vdd_arm";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_3v3: DCDC_REG4 {
++				regulator-name = "vcc_3v3";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_1v8: LDO_REG2 {
++				regulator-name = "vcc_1v8";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_1v0: LDO_REG3 {
++				regulator-name = "vdd_1v0";
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG4 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_sd: LDO_REG6 {
++				regulator-name = "vcc_sd";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_bl: LDO_REG7 {
++				regulator-name = "vcc_bl";
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_lcd: LDO_REG8 {
++				regulator-name = "vcc_lcd";
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <2800000>;
++				};
++			};
++
++			LDO_REG9 {
++				/* unused */
++			};
++
++			usb_midu: BOOST {
++				regulator-name = "usb_midu";
++				regulator-min-microvolt = <5000000>;
++				regulator-max-microvolt = <5400000>;
++				regulator-always-on;
++				regulator-boot-on;
++			};
++		};
++
++		rk817_charger: charger {
++			rockchip,resistor-sense-micro-ohms = <10000>;
++			rockchip,sleep-enter-current-microamp = <300000>;
++			rockchip,sleep-filter-current-microamp = <100000>;
++		};
++
++		rk817_codec: codec {
++			rockchip,mic-in-differential;
++		};
++	};
++};
++
++/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
++&i2c1 {
++	clock-frequency = <400000>;
++	status = "okay";
++};
++
++/* I2S 1 Channel Used */
++&i2s1_2ch {
++	status = "okay";
++};
++
++&io_domains {
++	vccio1-supply = <&vcc_3v3>;
++	vccio2-supply = <&vccio_sd>;
++	vccio3-supply = <&vcc_3v3>;
++	vccio4-supply = <&vcc_3v3>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc3v3_pmu>;
++	status = "okay";
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&sdmmc {
++	cap-sd-highspeed;
++	card-detect-delay = <200>;
++	cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
++	sd-uhs-sdr12;
++	sd-uhs-sdr25;
++	sd-uhs-sdr50;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	status = "okay";
++};
++
++&sfc {
++	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
++	pinctrl-names = "default";
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <108000000>;
++		spi-rx-bus-width = <2>;
++		spi-tx-bus-width = <1>;
++	};
++};
++
++&tsadc {
++	status = "okay";
++};
++
++&u2phy {
++	status = "okay";
++
++	u2phy_host: host-port {
++		status = "okay";
++	};
++
++	u2phy_otg: otg-port {
++		status = "disabled";
++	};
++};
++
++&usb20_otg {
++	status = "okay";
++};
++
++/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1_xfer &uart1_cts>;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart2m1_xfer>;
++	status = "okay";
++};
++
++&vopb {
++	status = "okay";
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&pinctrl {
++	btns {
++		btn_pins: btn-pins {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	headphone {
++		hp_det: hp-det {
++			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	leds {
++		blue_led_pin: blue-led-pin {
++			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		dc_det: dc-det {
++			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pmic_int: pmic-int {
++			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		soc_slppin_gpio: soc_slppin_gpio {
++			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
++		};
++
++		soc_slppin_rst: soc_slppin_rst {
++			rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
++		};
++
++		soc_slppin_slp: soc_slppin_slp {
++			rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
++		};
++	};
++};
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+@@ -2,27 +2,17 @@
+ /*
+  * Copyright (c) 2019 Hardkernel Co., Ltd
+  * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
++ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
+  */
+ 
+ /dts-v1/;
+-#include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/input/input.h>
+-#include <dt-bindings/pinctrl/rockchip.h>
+-#include "rk3326.dtsi"
++#include "rk3326-odroid-go.dtsi"
+ 
+ / {
+ 	model = "ODROID-GO Advance";
+ 	compatible = "hardkernel,rk3326-odroid-go2", "rockchip,rk3326";
+ 
+-	aliases {
+-		mmc0 = &sdmmc;
+-	};
+-
+-	chosen {
+-		stdout-path = "serial2:115200n8";
+-	};
+-
+-	adc-joystick {
++	analog_sticks: adc-joystick {
+ 		compatible = "adc-joystick";
+ 		io-channels = <&saradc 1>,
+ 			      <&saradc 2>;
+@@ -47,12 +37,6 @@
+ 		};
+ 	};
+ 
+-	backlight: backlight {
+-		compatible = "pwm-backlight";
+-		power-supply = <&vcc_bl>;
+-		pwms = <&pwm1 0 25000 0>;
+-	};
+-
+ 	battery: battery {
+ 		compatible = "simple-battery";
+ 		charge-full-design-microamp-hours = <3000000>;
+@@ -64,606 +48,19 @@
+ 		voltage-min-design-microvolt = <3500000>;
+ 
+ 		ocv-capacity-celsius = <20>;
+-		ocv-capacity-table-0 =	<4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
++		ocv-capacity-table-0 =  <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
+ 					<3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>,
+ 					<3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>,
+ 					<3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>,
+ 					<3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>,
+ 					<3574170 0>;
+ 	};
+-
+-	gpio-keys {
+-		compatible = "gpio-keys";
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&btn_pins>;
+-
+-		/*
+-		 *      *** ODROIDGO2-Advance Switch layout ***
+-		 * |------------------------------------------------|
+-		 * | sw15                                      sw16 |
+-		 * |------------------------------------------------|
+-		 * |     sw1      |-------------------|      sw8    |
+-		 * |  sw3   sw4   |                   |   sw7   sw5 |
+-		 * |     sw2      |    LCD Display    |      sw6    |
+-		 * |              |                   |             |
+-		 * |              |-------------------|             |
+-		 * |         sw9 sw10   sw11 sw12   sw13 sw14       |
+-		 * |------------------------------------------------|
+-		 */
+-
+-		button-sw1 {
+-			gpios = <&gpio1 RK_PB4 GPIO_ACTIVE_LOW>;
+-			label = "DPAD-UP";
+-			linux,code = <BTN_DPAD_UP>;
+-		};
+-		button-sw2 {
+-			gpios = <&gpio1 RK_PB5 GPIO_ACTIVE_LOW>;
+-			label = "DPAD-DOWN";
+-			linux,code = <BTN_DPAD_DOWN>;
+-		};
+-		button-sw3 {
+-			gpios = <&gpio1 RK_PB6 GPIO_ACTIVE_LOW>;
+-			label = "DPAD-LEFT";
+-			linux,code = <BTN_DPAD_LEFT>;
+-		};
+-		button-sw4 {
+-			gpios = <&gpio1 RK_PB7 GPIO_ACTIVE_LOW>;
+-			label = "DPAD-RIGHT";
+-			linux,code = <BTN_DPAD_RIGHT>;
+-		};
+-		button-sw5 {
+-			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_LOW>;
+-			label = "BTN-A";
+-			linux,code = <BTN_EAST>;
+-		};
+-		button-sw6 {
+-			gpios = <&gpio1 RK_PA5 GPIO_ACTIVE_LOW>;
+-			label = "BTN-B";
+-			linux,code = <BTN_SOUTH>;
+-		};
+-		button-sw7 {
+-			gpios = <&gpio1 RK_PA6 GPIO_ACTIVE_LOW>;
+-			label = "BTN-Y";
+-			linux,code = <BTN_WEST>;
+-		};
+-		button-sw8 {
+-			gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_LOW>;
+-			label = "BTN-X";
+-			linux,code = <BTN_NORTH>;
+-		};
+-		button-sw9 {
+-			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
+-			label = "F1";
+-			linux,code = <BTN_TRIGGER_HAPPY1>;
+-		};
+-		button-sw10 {
+-			gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
+-			label = "F2";
+-			linux,code = <BTN_TRIGGER_HAPPY2>;
+-		};
+-		button-sw11 {
+-			gpios = <&gpio2 RK_PA2 GPIO_ACTIVE_LOW>;
+-			label = "F3";
+-			linux,code = <BTN_TRIGGER_HAPPY3>;
+-		};
+-		button-sw12 {
+-			gpios = <&gpio2 RK_PA3 GPIO_ACTIVE_LOW>;
+-			label = "F4";
+-			linux,code = <BTN_TRIGGER_HAPPY4>;
+-		};
+-		button-sw13 {
+-			gpios = <&gpio2 RK_PA4 GPIO_ACTIVE_LOW>;
+-			label = "F5";
+-			linux,code = <BTN_TRIGGER_HAPPY5>;
+-		};
+-		button-sw14 {
+-			gpios = <&gpio2 RK_PA5 GPIO_ACTIVE_LOW>;
+-			label = "F6";
+-			linux,code = <BTN_TRIGGER_HAPPY6>;
+-		};
+-		button-sw15 {
+-			gpios = <&gpio2 RK_PA6 GPIO_ACTIVE_LOW>;
+-			label = "TOP-LEFT";
+-			linux,code = <BTN_TL>;
+-		};
+-		button-sw16 {
+-			gpios = <&gpio2 RK_PA7 GPIO_ACTIVE_LOW>;
+-			label = "TOP-RIGHT";
+-			linux,code = <BTN_TR>;
+-		};
+-	};
+-
+-	leds: gpio-leds {
+-		compatible = "gpio-leds";
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&blue_led_pin>;
+-
+-		blue_led: led-0 {
+-			label = "blue:heartbeat";
+-			gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+-			linux,default-trigger = "heartbeat";
+-		};
+-	};
+-
+-	rk817-sound {
+-		compatible = "simple-audio-card";
+-		simple-audio-card,name = "Analog";
+-		simple-audio-card,format = "i2s";
+-		simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+-		simple-audio-card,mclk-fs = <256>;
+-		simple-audio-card,widgets =
+-			"Microphone", "Mic Jack",
+-			"Headphone", "Headphones",
+-			"Speaker", "Speaker";
+-		simple-audio-card,routing =
+-			"MICL", "Mic Jack",
+-			"Headphones", "HPOL",
+-			"Headphones", "HPOR",
+-			"Speaker", "SPKO";
+-
+-		simple-audio-card,codec {
+-			sound-dai = <&rk817>;
+-		};
+-
+-		simple-audio-card,cpu {
+-			sound-dai = <&i2s1_2ch>;
+-		};
+-	};
+-
+-	vccsys: vccsys {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v8_sys";
+-		regulator-always-on;
+-		regulator-min-microvolt = <3800000>;
+-		regulator-max-microvolt = <3800000>;
+-	};
+-
+-	vcc_host: vcc_host {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc_host";
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-
+-		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
+-		enable-active-high;
+-		regulator-always-on;
+-		regulator-boot-on;
+-		vin-supply = <&usb_midu>;
+-	};
+-};
+-
+-&cpu0 {
+-	cpu-supply = <&vdd_arm>;
+-};
+-
+-&cpu1 {
+-	cpu-supply = <&vdd_arm>;
+-};
+-
+-&cpu2 {
+-	cpu-supply = <&vdd_arm>;
+-};
+-
+-&cpu3 {
+-	cpu-supply = <&vdd_arm>;
+-};
+-
+-&cru {
+-	assigned-clocks = <&cru PLL_NPLL>,
+-		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+-		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+-		<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
+-		<&cru PLL_CPLL>;
+-
+-	assigned-clock-rates = <1188000000>,
+-		<200000000>, <200000000>,
+-		<150000000>, <150000000>,
+-		<100000000>, <200000000>,
+-		<17000000>;
+ };
+ 
+-&display_subsystem {
+-	status = "okay";
++&internal_display {
++	compatible = "elida,kd35t133";
+ };
+ 
+-&dsi {
+-	status = "okay";
+-
+-	ports {
+-		mipi_out: port@1 {
+-			reg = <1>;
+-
+-			mipi_out_panel: endpoint {
+-				remote-endpoint = <&mipi_in_panel>;
+-			};
+-		};
+-	};
+-
+-	panel@0 {
+-		compatible = "elida,kd35t133";
+-		reg = <0>;
+-		backlight = <&backlight>;
+-		iovcc-supply = <&vcc_lcd>;
+-		reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+-		rotation = <270>;
+-		vdd-supply = <&vcc_lcd>;
+-
+-		port {
+-			mipi_in_panel: endpoint {
+-				remote-endpoint = <&mipi_out_panel>;
+-			};
+-		};
+-	};
+-};
+-
+-&dsi_dphy {
+-	status = "okay";
+-};
+-
+-&gpu {
+-	mali-supply = <&vdd_logic>;
+-	status = "okay";
+-};
+-
+-&i2c0 {
+-	clock-frequency = <400000>;
+-	i2c-scl-falling-time-ns = <16>;
+-	i2c-scl-rising-time-ns = <280>;
+-	status = "okay";
+-
+-	rk817: pmic@20 {
+-		compatible = "rockchip,rk817";
+-		reg = <0x20>;
+-		interrupt-parent = <&gpio0>;
+-		interrupts = <RK_PB2 IRQ_TYPE_LEVEL_LOW>;
+-		clock-output-names = "rk808-clkout1", "xin32k";
+-		clock-names = "mclk";
+-		clocks = <&cru SCLK_I2S1_OUT>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int>, <&i2s1_2ch_mclk>;
+-		wakeup-source;
+-		#clock-cells = <1>;
+-		#sound-dai-cells = <0>;
+-
+-		vcc1-supply = <&vccsys>;
+-		vcc2-supply = <&vccsys>;
+-		vcc3-supply = <&vccsys>;
+-		vcc4-supply = <&vccsys>;
+-		vcc5-supply = <&vccsys>;
+-		vcc6-supply = <&vccsys>;
+-		vcc7-supply = <&vccsys>;
+-		vcc8-supply = <&vccsys>;
+-
+-		regulators {
+-			vdd_logic: DCDC_REG1 {
+-				regulator-name = "vdd_logic";
+-				regulator-min-microvolt = <950000>;
+-				regulator-max-microvolt = <1150000>;
+-				regulator-ramp-delay = <6001>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <950000>;
+-				};
+-			};
+-
+-			vdd_arm: DCDC_REG2 {
+-				regulator-name = "vdd_arm";
+-				regulator-min-microvolt = <950000>;
+-				regulator-max-microvolt = <1350000>;
+-				regulator-ramp-delay = <6001>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-					regulator-suspend-microvolt = <950000>;
+-				};
+-			};
+-
+-			vcc_ddr: DCDC_REG3 {
+-				regulator-name = "vcc_ddr";
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-				};
+-			};
+-
+-			vcc_3v3: DCDC_REG4 {
+-				regulator-name = "vcc_3v3";
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-					regulator-suspend-microvolt = <3300000>;
+-				};
+-			};
+-
+-			vcc_1v8: LDO_REG2 {
+-				regulator-name = "vcc_1v8";
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <1800000>;
+-				};
+-			};
+-
+-			vdd_1v0: LDO_REG3 {
+-				regulator-name = "vdd_1v0";
+-				regulator-min-microvolt = <1000000>;
+-				regulator-max-microvolt = <1000000>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <1000000>;
+-				};
+-			};
+-
+-			vcc3v3_pmu: LDO_REG4 {
+-				regulator-name = "vcc3v3_pmu";
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <3300000>;
+-				};
+-			};
+-
+-			vccio_sd: LDO_REG5 {
+-				regulator-name = "vccio_sd";
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <3300000>;
+-				};
+-			};
+-
+-			vcc_sd: LDO_REG6 {
+-				regulator-name = "vcc_sd";
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <3300000>;
+-				};
+-			};
+-
+-			vcc_bl: LDO_REG7 {
+-				regulator-name = "vcc_bl";
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-					regulator-suspend-microvolt = <3300000>;
+-				};
+-			};
+-
+-			vcc_lcd: LDO_REG8 {
+-				regulator-name = "vcc_lcd";
+-				regulator-min-microvolt = <2800000>;
+-				regulator-max-microvolt = <2800000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-					regulator-suspend-microvolt = <2800000>;
+-				};
+-			};
+-
+-			vcc_cam: LDO_REG9 {
+-				regulator-name = "vcc_cam";
+-				regulator-min-microvolt = <3000000>;
+-				regulator-max-microvolt = <3000000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-					regulator-suspend-microvolt = <3000000>;
+-				};
+-			};
+-
+-			usb_midu: BOOST {
+-				regulator-name = "usb_midu";
+-				regulator-min-microvolt = <5000000>;
+-				regulator-max-microvolt = <5400000>;
+-				regulator-always-on;
+-				regulator-boot-on;
+-			};
+-		};
+-
+-		rk817_charger: charger {
+-			monitored-battery = <&battery>;
+-			rockchip,resistor-sense-micro-ohms = <10000>;
+-			rockchip,sleep-enter-current-microamp = <300000>;
+-			rockchip,sleep-filter-current-microamp = <100000>;
+-		};
+-
+-		rk817_codec: codec {
+-			rockchip,mic-in-differential;
+-		};
+-	};
+-};
+-
+-/* EXT Header(P2): 7(SCL:GPIO0.C2), 8(SDA:GPIO0.C3) */
+-&i2c1 {
+-	clock-frequency = <400000>;
+-	status = "okay";
+-};
+-
+-/* I2S 1 Channel Used */
+-&i2s1_2ch {
+-	status = "okay";
+-};
+-
+-&io_domains {
+-	vccio1-supply = <&vcc_3v3>;
+-	vccio2-supply = <&vccio_sd>;
+-	vccio3-supply = <&vcc_3v3>;
+-	vccio4-supply = <&vcc_3v3>;
+-	vccio5-supply = <&vcc_3v3>;
+-	vccio6-supply = <&vcc_3v3>;
+-	status = "okay";
+-};
+-
+-&pmu_io_domains {
+-	pmuio1-supply = <&vcc3v3_pmu>;
+-	pmuio2-supply = <&vcc3v3_pmu>;
+-	status = "okay";
+-};
+-
+-&pwm1 {
+-	status = "okay";
+-};
+-
+-&saradc {
+-	vref-supply = <&vcc_1v8>;
+-	status = "okay";
+-};
+-
+-&sdmmc {
+-	cap-sd-highspeed;
+-	card-detect-delay = <200>;
+-	cd-gpios = <&gpio0 RK_PA3 GPIO_ACTIVE_LOW>; /*[> CD GPIO <]*/
+-	sd-uhs-sdr12;
+-	sd-uhs-sdr25;
+-	sd-uhs-sdr50;
+-	sd-uhs-sdr104;
+-	vmmc-supply = <&vcc_sd>;
+-	vqmmc-supply = <&vccio_sd>;
+-	status = "okay";
+-};
+-
+-&sfc {
+-	pinctrl-0 = <&sfc_clk &sfc_cs0 &sfc_bus2>;
+-	pinctrl-names = "default";
+-	#address-cells = <1>;
+-	#size-cells = <0>;
+-	status = "okay";
+-
+-	flash@0 {
+-		compatible = "jedec,spi-nor";
+-		reg = <0>;
+-		spi-max-frequency = <108000000>;
+-		spi-rx-bus-width = <2>;
+-		spi-tx-bus-width = <1>;
+-	};
+-};
+-
+-&tsadc {
+-	status = "okay";
+-};
+-
+-&u2phy {
+-	status = "okay";
+-
+-	u2phy_host: host-port {
+-		status = "okay";
+-	};
+-
+-	u2phy_otg: otg-port {
+-		status = "disabled";
+-	};
+-};
+-
+-&usb20_otg {
+-	status = "okay";
+-};
+-
+-/* EXT Header(P2): 2(RXD:GPIO1.C0),3(TXD:.C1),4(CTS:.C2),5(RTS:.C3) */
+-&uart1 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&uart1_xfer &uart1_cts>;
+-	status = "okay";
+-};
+-
+-&uart2 {
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&uart2m1_xfer>;
+-	status = "okay";
+-};
+-
+-&vopb {
+-	status = "okay";
+-};
+-
+-&vopb_mmu {
+-	status = "okay";
+-};
+-
+-&pinctrl {
+-	btns {
+-		btn_pins: btn-pins {
+-			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
+-					<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>;
+-		};
+-	};
+-
+-	headphone {
+-		hp_det: hp-det {
+-			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_down>;
+-		};
+-	};
+-
+-	leds {
+-		blue_led_pin: blue-led-pin {
+-			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-	};
+-
+-	pmic {
+-		dc_det: dc-det {
+-			rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-
+-		pmic_int: pmic-int {
+-			rockchip,pins = <0 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>;
+-		};
+-
+-		soc_slppin_gpio: soc_slppin_gpio {
+-			rockchip,pins = <0 RK_PA4 RK_FUNC_GPIO &pcfg_output_low>;
+-		};
+-
+-		soc_slppin_rst: soc_slppin_rst {
+-			rockchip,pins = <0 RK_PA4 2 &pcfg_pull_none>;
+-		};
+-
+-		soc_slppin_slp: soc_slppin_slp {
+-			rockchip,pins = <0 RK_PA4 1 &pcfg_pull_none>;
+-		};
+-	};
++&rk817_charger {
++	monitored-battery = <&battery>;
+ };
diff --git a/target/linux/rockchip/patches-6.1/078-arm64-dts-rockchip-Add-Odroid-Go-Advance-Black-Editi.patch b/target/linux/rockchip/patches-6.1/078-arm64-dts-rockchip-Add-Odroid-Go-Advance-Black-Editi.patch
new file mode 100644
index 00000000000..da75568beb8
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/078-arm64-dts-rockchip-Add-Odroid-Go-Advance-Black-Editi.patch
@@ -0,0 +1,188 @@
+From b2fb15ee053aa3d9d0918b246e70603b1560de98 Mon Sep 17 00:00:00 2001
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+Date: Thu, 17 Nov 2022 22:59:52 +0100
+Subject: [PATCH 078/383] arm64: dts: rockchip: Add Odroid Go Advance Black
+ Edition
+
+This device is a minor revision of the origin Odroid Go Advance, with
+added two more buttons and a WiFi card
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Link: https://lore.kernel.org/r/20221117215954.4114202-4-maccraft123mc@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3326-odroid-go2-v11.dts    | 156 ++++++++++++++++++
+ 2 files changed, 157 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -9,6 +9,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts
+@@ -0,0 +1,156 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Hardkernel Co., Ltd
++ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
++ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3326-odroid-go.dtsi"
++
++/ {
++	model = "ODROID-GO Advance Black Edition";
++	compatible = "hardkernel,rk3326-odroid-go2-v11", "rockchip,rk3326";
++
++	aliases {
++		mmc1 = &sdio;
++	};
++
++	analog_sticks: adc-joystick {
++		compatible = "adc-joystick";
++		io-channels = <&saradc 1>,
++			      <&saradc 2>;
++		poll-interval = <60>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		axis@0 {
++			reg = <0>;
++			abs-flat = <10>;
++			abs-fuzz = <10>;
++			abs-range = <172 772>;
++			linux,code = <ABS_X>;
++			};
++
++		axis@1 {
++			reg = <1>;
++			abs-flat = <10>;
++			abs-fuzz = <10>;
++			abs-range = <278 815>;
++			linux,code = <ABS_Y>;
++		};
++	};
++
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <3000000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <180000>;
++		voltage-max-design-microvolt = <4100000>;
++		voltage-min-design-microvolt = <3500000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =  <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
++					<3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>,
++					<3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>,
++					<3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>,
++					<3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>,
++					<3574170 0>;
++	};
++
++	wifi_pwrseq: wifi-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_pwrseq_pins>;
++		reset-gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&builtin_gamepad {
++	button-sw20 {
++		gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++		label = "TOP-LEFT 2";
++		linux,code = <BTN_TL2>;
++	};
++	button-sw21 {
++		gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
++		label = "TOP-RIGHT 2";
++		linux,code = <BTN_TR2>;
++	};
++};
++
++&internal_display {
++	compatible = "elida,kd35t133";
++};
++
++&rk817 {
++	regulators {
++		vcc_wifi: LDO_REG9 {
++			regulator-name = "vcc_wifi";
++			regulator-min-microvolt = <3300000>;
++			regulator-max-microvolt = <3300000>;
++
++			regulator-state-mem {
++				regulator-on-in-suspend;
++				regulator-suspend-microvolt = <3300000>;
++			};
++		};
++	};
++};
++
++&rk817_charger {
++	monitored-battery = <&battery>;
++};
++
++&sdio {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	disable-wp;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&wifi_pwrseq>;
++	non-removable;
++	vmmc-supply = <&vcc_wifi>;
++	#address-cells = <1>;
++	#size-cells = <0>;
++	status = "okay";
++
++	esp8089: wifi@1 {
++		compatible = "esp,esp8089";
++		reg = <1>;
++	};
++};
++
++&pinctrl {
++	btns {
++		btn_pins: btn-pins {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	wifi {
++		wifi_pwrseq_pins: wifi-pwrseq-pins {
++			rockchip,pins = <3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB6 RK_FUNC_GPIO &pcfg_output_high>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/079-arm64-dts-rockchip-Add-Odroid-Go-Super.patch b/target/linux/rockchip/patches-6.1/079-arm64-dts-rockchip-Add-Odroid-Go-Super.patch
new file mode 100644
index 00000000000..5014c9ca6b6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/079-arm64-dts-rockchip-Add-Odroid-Go-Super.patch
@@ -0,0 +1,217 @@
+From 19f84e5fa3eecbbb5f470f387fb49268c4978c29 Mon Sep 17 00:00:00 2001
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+Date: Thu, 17 Nov 2022 22:59:53 +0100
+Subject: [PATCH 079/383] arm64: dts: rockchip: Add Odroid Go Super
+
+This device is another revision of Odroid Go Advance, with added two
+volume buttons, a second analog stick and a bigger screen that isn't yet
+supported in the mainline kernel.
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Link: https://lore.kernel.org/r/20221117215954.4114202-5-maccraft123mc@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3326-odroid-go3.dts   | 185 ++++++++++++++++++
+ 2 files changed, 186 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
+@@ -0,0 +1,185 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Hardkernel Co., Ltd
++ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
++ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3326-odroid-go.dtsi"
++
++/ {
++	model = "ODROID-GO Super";
++	compatible = "hardkernel,rk3326-odroid-go3", "rockchip,rk3326";
++
++	joystick_mux_controller: mux-controller {
++		compatible = "gpio-mux";
++		pinctrl = <&mux_en_pins>;
++		#mux-control-cells = <0>;
++
++		mux-gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>,
++			    <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++	};
++
++	joystick_mux: adc-mux {
++		compatible = "io-channel-mux";
++		io-channels = <&saradc 1>;
++		io-channel-names = "parent";
++		#io-channel-cells = <1>;
++
++		mux-controls = <&joystick_mux_controller>;
++		channels = "0", "1", "2", "3";
++	};
++
++	analog_sticks: adc-joystick {
++		compatible = "adc-joystick";
++		io-channels = <&joystick_mux 0>,
++			      <&joystick_mux 1>,
++			      <&joystick_mux 2>,
++			      <&joystick_mux 3>;
++		poll-interval = <60>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		axis@0 {
++			reg = <0>;
++			abs-flat = <10>;
++			abs-fuzz = <10>;
++			abs-range = <180 800>;
++			linux,code = <ABS_X>;
++		};
++
++		axis@1 {
++			reg = <1>;
++			abs-flat = <10>;
++			abs-fuzz = <10>;
++			abs-range = <180 800>;
++			linux,code = <ABS_RX>;
++		};
++
++		axis@2 {
++			reg = <2>;
++			abs-flat = <10>;
++			abs-fuzz = <10>;
++			abs-range = <180 800>;
++			linux,code = <ABS_Y>;
++		};
++
++		axis@3 {
++			reg = <3>;
++			abs-flat = <10>;
++			abs-fuzz = <10>;
++			abs-range = <180 800>;
++			linux,code = <ABS_RY>;
++		};
++	};
++
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <4000000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <180000>;
++		voltage-max-design-microvolt = <4100000>;
++		voltage-min-design-microvolt = <3500000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =  <4046950 100>, <4001920 95>, <3967900 90>, <3919950 85>,
++					<3888450 80>, <3861850 75>, <3831540 70>, <3799130 65>,
++					<3768190 60>, <3745650 55>, <3726610 50>, <3711630 45>,
++					<3696720 40>, <3685660 35>, <3674950 30>, <3663050 25>,
++					<3649470 20>, <3635260 15>, <3616920 10>, <3592440 5>,
++					<3574170 0>;
++	};
++
++	gpio-keys-vol {
++		compatible = "gpio-keys";
++		autorepeat;
++		pinctrl-0 = <&btn_pins_vol>;
++		pinctrl-names = "default";
++
++		button-vol-down {
++			gpios = <&gpio2 RK_PA1 GPIO_ACTIVE_LOW>;
++			label = "VOLUMEDOWN";
++			linux,code = <KEY_VOLUMEDOWN>;
++		};
++
++		button-volume-up {
++			gpios = <&gpio2 RK_PA0 GPIO_ACTIVE_LOW>;
++			label = "VOLUMEUP";
++			linux,code = <KEY_VOLUMEUP>;
++		};
++	};
++};
++
++/* f1 and f2 conflict with volume buttons */
++/delete-node/ &btn_f1;
++/delete-node/ &btn_f2;
++
++&builtin_gamepad {
++	button-sw19 {
++		gpios = <&gpio3 RK_PB1 GPIO_ACTIVE_LOW>;
++		label = "SELECT";
++		linux,code = <BTN_SELECT>;
++	};
++	/* note that TR2 and TL2 are swapped */
++	button-sw20 {
++		gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++		label = "TOP-RIGHT 2";
++		linux,code = <BTN_TR2>;
++	};
++	button-sw21 {
++		gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
++		label = "TOP-LEFT 2";
++		linux,code = <BTN_TL2>;
++	};
++	button-sw22 {
++		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
++		label = "START";
++		linux,code = <BTN_START>;
++	};
++};
++
++&internal_display {
++	status = "disabled";
++};
++
++&rk817_charger {
++	monitored-battery = <&battery>;
++};
++
++&pinctrl {
++	btns {
++		btn_pins: btn-pins {
++			rockchip,pins = <1 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<1 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA5 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA7 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB2 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>,
++					<3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++		btn_pins_vol: btn-pins-vol {
++			rockchip,pins = <2 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>,
++					<2 RK_PA1 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	joystick {
++		mux_en_pins: mux-pins {
++			rockchip,pins = <3 RK_PB5 RK_FUNC_GPIO &pcfg_output_low>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/080-arm64-dts-rockchip-Add-Anbernic-RG351M.patch b/target/linux/rockchip/patches-6.1/080-arm64-dts-rockchip-Add-Anbernic-RG351M.patch
new file mode 100644
index 00000000000..d433c57d41e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/080-arm64-dts-rockchip-Add-Anbernic-RG351M.patch
@@ -0,0 +1,77 @@
+From 67455ae79b7a778bb7be113e20f885690239aece Mon Sep 17 00:00:00 2001
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+Date: Thu, 17 Nov 2022 22:59:54 +0100
+Subject: [PATCH 080/383] arm64: dts: rockchip: Add Anbernic RG351M
+
+This device is a clone of Odroid Go Advance, with added PWM motor, internal
+gamepad connected on USB instead of just having it be on GPIO + ADC, and
+missing battery shunt resistor.
+Due to missing shunt resistor and lack of a workaround in rk817_charger
+driver rk817_charger is not enabled in dts.
+
+There's also an LED on GPIO 77(I *guess* PB5 on &gpio2),
+that is controlled in a weird way:
+
+- It is set to red by setting output value to 1
+- Set to green by setting output value to 0
+- Set to yellow by setting gpio direction to input
+
+I have no idea how to describe that in DTS, without adding a custom
+driver, for now it's just left out.
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Link: https://lore.kernel.org/r/20221117215954.4114202-6-maccraft123mc@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../dts/rockchip/rk3326-anbernic-rg351m.dts   | 33 +++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -8,6 +8,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-ev
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-roc-cc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3308-rock-pi-s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a95x-z2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-anbernic-rg351m.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2-v11.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2019 Hardkernel Co., Ltd
++ * Copyright (c) 2020 Theobroma Systems Design und Consulting GmbH
++ * Copyright (c) 2022 Maya Matuszczyk <maccraft123mc@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3326-odroid-go.dtsi"
++
++/ {
++	model = "Anbernic RG351M";
++	compatible = "anbernic,rg351m", "rockchip,rk3326";
++
++	vibrator {
++		compatible = "pwm-vibrator";
++		pwms = <&pwm0 0 1000000 0>;
++		pwm-names = "enable";
++	};
++};
++
++/delete-node/ &builtin_gamepad;
++/delete-node/ &vcc_host; /* conflicts with pwm vibration motor */
++
++&internal_display {
++	compatible = "elida,kd35t133";
++};
++
++&pwm0 {
++	status = "okay";
++};
++
++/delete-node/ &rk817_charger;
diff --git a/target/linux/rockchip/patches-6.1/081-arm64-dts-rockchip-Add-SOQuartz-blade-board.patch b/target/linux/rockchip/patches-6.1/081-arm64-dts-rockchip-Add-SOQuartz-blade-board.patch
new file mode 100644
index 00000000000..656589411ff
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/081-arm64-dts-rockchip-Add-SOQuartz-blade-board.patch
@@ -0,0 +1,235 @@
+From c914739c593e8e2378c14ad89b0c514fbfaaa9cc Mon Sep 17 00:00:00 2001
+From: Andrew Powers-Holmes <aholmes@omnom.net>
+Date: Wed, 16 Nov 2022 12:53:35 +0100
+Subject: [PATCH 081/383] arm64: dts: rockchip: Add SOQuartz blade board
+
+This adds a device tree for the PINE64 SOQuartz blade baseboard,
+a 1U rack mountable baseboard for the CM4 form factor with PoE
+support designed for the SOQuartz CM4 System-on-Module.
+
+The board takes power from either PoE or a 5V DC input, and allows
+for mounting an M.2 SSD.
+
+The board also features one USB 2.0 host port, one HDMI output,
+a 3.5mm jack for UART, and the aforementioned gigabit networking
+port.
+
+Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
+[rebase, squash, reword, misc fixes]
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221116115337.541601-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3566-soquartz-blade.dts    | 194 ++++++++++++++++++
+ 2 files changed, 195 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-blade.dts
+@@ -0,0 +1,194 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++#include "rk3566-soquartz.dtsi"
++
++/ {
++	model = "PINE64 RK3566 SOQuartz on Blade carrier board";
++	compatible = "pine64,soquartz-blade", "pine64,soquartz", "rockchip,rk3566";
++
++	/* labeled VCC3V0_SD in schematic to not conflict with PMIC regulator */
++	vcc3v0_sd: vcc3v0-sd-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v0_sd";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	/* labeled VCC_SSD in schematic */
++	vcc3v3_pcie_p: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie_p";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vbus>;
++	};
++
++	vcc5v_dcin: vcc5v-dcin-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++};
++
++&combphy2 {
++	phy-supply = <&vcc3v3_sys>;
++	status = "okay";
++};
++
++&gmac1 {
++	status = "okay";
++};
++
++/*
++ * i2c1 is exposed on CM1 / Module1A
++ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
++ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
++ */
++&i2c1 {
++	status = "okay";
++
++};
++
++/*
++ * i2c2 is exposed on CM1 / Module1A - to PI40
++ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
++ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
++ */
++&i2c2 {
++	status = "disabled";
++};
++
++/*
++ * i2c3 is exposed on CM1 / Module1A - to PI40
++ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
++ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
++ */
++&i2c3 {
++	status = "disabled";
++};
++
++/*
++ * i2c4 is exposed on CM2 / Module1B - to PI40
++ * pin 45 - GPIO24 - i2c4_scl_m1
++ * pin 47 - GPIO23 - i2c4_sda_m1
++ */
++&i2c4 {
++	status = "disabled";
++};
++
++/*
++ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
++ * pin 24 - GPIO26 - i2s1_sdi1_m1
++ * pin 25 - GPIO21 - i2s1_sdo0_m1
++ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
++ * pin 27 - GPIO20 - i2s1_sdi0_m1
++ * pin 29 - GPIO16 - i2s1_sdi3_m1
++ * pin 30 - GPIO6  - i2s1_sdi2_m1
++ * pin 40 - GPIO9  - i2s1_sdo1_m1, shared with spi3
++ * pin 41 - GPIO25 - i2s1_sdo2_m1
++ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
++ * pin 50 - GPIO17 - i2s1_mclk_m1
++ * pin 56 - GPIO3  - i2s1_sdo3_m1, shared with i2c2
++ */
++&i2s1_8ch {
++	status = "disabled";
++};
++
++&led_diy {
++	color = <LED_COLOR_ID_RED>;
++	function = LED_FUNCTION_DISK_ACTIVITY;
++	linux,default-trigger = "disk-activity";
++	status = "okay";
++};
++
++&led_work {
++	color = <LED_COLOR_ID_GREEN>;
++	function = LED_FUNCTION_STATUS;
++	linux,default-trigger = "heartbeat";
++	status = "okay";
++};
++
++&pcie2x1 {
++	vpcie3v3-supply = <&vcc3v3_pcie_p>;
++	status = "okay";
++};
++
++&rgmii_phy1 {
++	status = "okay";
++};
++
++/*
++ * saradc is exposed on CM1 / Module1A - to J2
++ * pin 94 - AIN1 - saradc_vin3
++ * pin 96 - AIN0 - saradc_vin2
++ */
++&saradc {
++	status = "disabled";
++};
++
++&sdmmc0 {
++	vmmc-supply = <&vcc3v0_sd>;
++	status = "okay";
++};
++
++/*
++ * spi3 is exposed on CM1 / Module1A - to PI40
++ * pin 37 - GPIO7  - spi3_cs1_m0
++ * pin 38 - GPIO11 - spi3_clk_m0
++ * pin 39 - GPIO8  - spi3_cs0_m0
++ * pin 40 - GPIO9  - spi3_miso_m0, shared with i2s1_8ch
++ * pin 44 - GPIO10 - spi3_mosi_m0
++ */
++&spi3 {
++	status = "disabled";
++};
++
++/*
++ * uart2 is exposed on CM1 / Module1A - to PI40
++ * pin 51 - GPIO15 - uart2_rx_m0
++ * pin 55 - GPIO14 - uart2_tx_m0
++ */
++&uart2 {
++	status = "okay";
++};
++
++/*
++ * uart7 is exposed on CM1 / Module1A - to PI40
++ * pin 46 - GPIO22 - uart7_tx_m2
++ * pin 47 - GPIO23 - uart7_rx_m2
++ */
++&uart7 {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vbus>;
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
++&vbus {
++	vin-supply = <&vcc5v_dcin>;
++};
diff --git a/target/linux/rockchip/patches-6.1/082-arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch b/target/linux/rockchip/patches-6.1/082-arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch
new file mode 100644
index 00000000000..58b79794fad
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/082-arm64-dts-rockchip-Add-SOQuartz-Model-A-baseboard.patch
@@ -0,0 +1,272 @@
+From 25aa99f248d8fd05855803a818dabc5580018a51 Mon Sep 17 00:00:00 2001
+From: Andrew Powers-Holmes <aholmes@omnom.net>
+Date: Wed, 16 Nov 2022 12:53:37 +0100
+Subject: [PATCH 082/383] arm64: dts: rockchip: Add SOQuartz Model A baseboard
+
+This patch adds the device tree for the "Model A" baseboard for
+the SOQuartz CM4 SoM, which is not to be confused with the
+Quartz64 Model A, which is the same form factor and SoC, but is
+not a CM4 carrier board.
+
+The board features a PCIe 2 x1 slot, USB 2 host ports, CSI/DSI
+connectors, an eDP FFC connector, gigabit ethernet, HDMI, and a
+12V DC barrel jack. Also present is a microSD card slot, 40-pin
+GPIO, and a power and reset button.
+
+Signed-off-by: Andrew Powers-Holmes <aholmes@omnom.net>
+[rebase, misc fixes, reword]
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221116115337.541601-5-frattaroli.nicolas@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3566-soquartz-model-a.dts  | 232 ++++++++++++++++++
+ 2 files changed, 233 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -76,6 +76,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-model-a.dts
+@@ -0,0 +1,232 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3566-soquartz.dtsi"
++
++/ {
++	model = "PINE64 RK3566 SOQuartz on Model A carrier board";
++	compatible = "pine64,soquartz-model-a", "pine64,soquartz", "rockchip,rk3566";
++
++	/* labeled DCIN_12V in schematic */
++	vcc12v_dcin: vcc12v-dcin-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc5v0_usb: vcc5v0-usb-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc12v_dcin>;
++	};
++
++	/*
++	 * Labelled VCC3V0_SD in schematic to not conflict with PMIC
++	 * regulator, it's 3.3v in actuality
++	 */
++	vcc3v0_sd: vcc3v0-sd-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v0_sd";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc12v_dcin>;
++	};
++
++	vcc12v_pcie: vcc12v-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_pcie";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++		vin-supply = <&vcc12v_dcin>;
++	};
++};
++
++/* phy for pcie */
++&combphy2 {
++	phy-supply = <&vcc3v3_sys>;
++	status = "okay";
++};
++
++&gmac1 {
++	status = "okay";
++};
++
++/*
++ * i2c1 is exposed on CM1 / Module1A
++ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
++ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
++ */
++&i2c1 {
++	status = "okay";
++
++	/*
++	 * the rtc interrupt is tied to PMIC_PWRON,
++	 * it will force reset the board if triggered.
++	 */
++	pcf85063: rtc@51 {
++		compatible = "nxp,pcf85063";
++		reg = <0x51>;
++	};
++};
++
++/*
++ * i2c2 is exposed on CM1 / Module1A - to PI40
++ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
++ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
++ */
++&i2c2 {
++	status = "disabled";
++};
++
++/*
++ * i2c3 is exposed on CM1 / Module1A - to PI40
++ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
++ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
++ */
++&i2c3 {
++	status = "disabled";
++};
++
++/*
++ * i2c4 is exposed on CM2 / Module1B - to PI40
++ * pin 45 - GPIO24 - i2c4_scl_m1
++ * pin 47 - GPIO23 - i2c4_sda_m1
++ */
++&i2c4 {
++	status = "disabled";
++};
++
++/*
++ * i2s1_8ch is exposed on CM1 / Module1A - to PI40
++ * pin 24 - GPIO26 - i2s1_sdi1_m1
++ * pin 25 - GPIO21 - i2s1_sdo0_m1
++ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
++ * pin 27 - GPIO20 - i2s1_sdi0_m1
++ * pin 29 - GPIO16 - i2s1_sdi3_m1
++ * pin 30 - GPIO6  - i2s1_sdi2_m1
++ * pin 40 - GPIO9  - i2s1_sdo1_m1, shared with spi3
++ * pin 41 - GPIO25 - i2s1_sdo2_m1
++ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
++ * pin 50 - GPIO17 - i2s1_mclk_m1
++ * pin 56 - GPIO3  - i2s1_sdo3_m1, shared with i2c2
++ */
++&i2s1_8ch {
++	status = "disabled";
++};
++
++&led_diy {
++	status = "okay";
++};
++
++&led_work {
++	status = "okay";
++};
++
++&pcie2x1 {
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&rgmii_phy1 {
++	status = "okay";
++};
++
++&rgmii_phy1 {
++	status = "okay";
++};
++
++/*
++ * saradc is exposed on CM1 / Module1A - to J2
++ * pin 94 - AIN1 - saradc_vin3
++ * pin 96 - AIN0 - saradc_vin2
++ */
++&saradc {
++	status = "disabled";
++};
++
++/*
++ * vmmc-supply is vcc3v3_sd on v1.0 and vcc3v0_sd on v1.1+
++ * the soquartz SoM has SDMMC_PWR (CM1 pin 75) hardwired to vcc3v3_sys,
++ * so we use vcc3v3_sd here to ensure the regulator is enabled on older boards.
++ */
++&sdmmc0 {
++	vmmc-supply = <&vcc3v3_sd>;
++	status = "okay";
++};
++
++/*
++ * spi3 is exposed on CM1 / Module1A - to PI40
++ * pin 37 - GPIO7  - spi3_cs1_m0
++ * pin 38 - GPIO11 - spi3_clk_m0
++ * pin 39 - GPIO8  - spi3_cs0_m0
++ * pin 40 - GPIO9  - spi3_miso_m0, shared with i2s1_8ch
++ * pin 44 - GPIO10 - spi3_mosi_m0
++ */
++&spi3 {
++	status = "disabled";
++};
++
++/*
++ * uart2 is exposed on CM1 / Module1A - to PI40
++ * pin 51 - GPIO15 - uart2_rx_m0
++ * pin 55 - GPIO14 - uart2_tx_m0
++ */
++&uart2 {
++	status = "okay";
++};
++
++/*
++ * uart7 is exposed on CM1 / Module1A - to PI40
++ * pin 46 - GPIO22 - uart7_tx_m2
++ * pin 47 - GPIO23 - uart7_rx_m2
++ */
++&uart7 {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_usb>;
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
++&vbus {
++	vin-supply = <&vcc5v0_usb>;
++};
++
++&vcc3v3_sd {
++	regulator-always-on;
++	regulator-boot-on;
++	regulator-min-microvolt = <3300000>;
++	regulator-max-microvolt = <3300000>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/083-arm64-dts-rockchip-update-cache-properties-for-rk330.patch b/target/linux/rockchip/patches-6.1/083-arm64-dts-rockchip-update-cache-properties-for-rk330.patch
new file mode 100644
index 00000000000..b08e6b1ed4d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/083-arm64-dts-rockchip-update-cache-properties-for-rk330.patch
@@ -0,0 +1,43 @@
+From 75e4c9ed412120130fb89f2d9ab94a2b1862adae Mon Sep 17 00:00:00 2001
+From: Pierre Gondois <pierre.gondois@arm.com>
+Date: Mon, 7 Nov 2022 16:57:12 +0100
+Subject: [PATCH 083/383] arm64: dts: rockchip: update cache properties for
+ rk3308 and rk3328
+
+The DeviceTree Specification v0.3 specifies that the cache node
+'compatible' and 'cache-level' properties are 'required'. Cf.
+s3.8 Multi-level and Shared Cache Nodes
+The 'cache-unified' property should be present if one of the
+properties for unified cache is present ('cache-size', ...).
+
+Update the Device Trees accordingly.
+
+Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
+Link: https://lore.kernel.org/r/20221107155825.1644604-20-pierre.gondois@arm.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi | 1 +
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -96,6 +96,7 @@
+ 
+ 		l2: l2-cache {
+ 			compatible = "cache";
++			cache-level = <2>;
+ 		};
+ 	};
+ 
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -102,6 +102,7 @@
+ 
+ 		l2: l2-cache0 {
+ 			compatible = "cache";
++			cache-level = <2>;
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/084-arm64-dts-rockchip-use-correct-reset-names-for-rk339.patch b/target/linux/rockchip/patches-6.1/084-arm64-dts-rockchip-use-correct-reset-names-for-rk339.patch
new file mode 100644
index 00000000000..e5a2da051f5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/084-arm64-dts-rockchip-use-correct-reset-names-for-rk339.patch
@@ -0,0 +1,37 @@
+From 07ff3d2c95230e4b64120c66faff85c35be4bac9 Mon Sep 17 00:00:00 2001
+From: Corentin Labbe <clabbe@baylibre.com>
+Date: Mon, 12 Dec 2022 12:44:23 +0000
+Subject: [PATCH 084/383] arm64: dts: rockchip: use correct reset names for
+ rk3399 crypto nodes
+
+The reset names does not follow the binding, use the correct ones.
+
+Fixes: 8c701fa6e38c ("arm64: dts: rockchip: rk3399: add crypto node")
+Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Link: https://lore.kernel.org/r/20221212124423.1239748-1-clabbe@baylibre.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -589,7 +589,7 @@
+ 		clocks = <&cru HCLK_M_CRYPTO0>, <&cru HCLK_S_CRYPTO0>, <&cru SCLK_CRYPTO0>;
+ 		clock-names = "hclk_master", "hclk_slave", "sclk";
+ 		resets = <&cru SRST_CRYPTO0>, <&cru SRST_CRYPTO0_S>, <&cru SRST_CRYPTO0_M>;
+-		reset-names = "master", "lave", "crypto";
++		reset-names = "master", "slave", "crypto-rst";
+ 	};
+ 
+ 	crypto1: crypto@ff8b8000 {
+@@ -599,7 +599,7 @@
+ 		clocks = <&cru HCLK_M_CRYPTO1>, <&cru HCLK_S_CRYPTO1>, <&cru SCLK_CRYPTO1>;
+ 		clock-names = "hclk_master", "hclk_slave", "sclk";
+ 		resets = <&cru SRST_CRYPTO1>, <&cru SRST_CRYPTO1_S>, <&cru SRST_CRYPTO1_M>;
+-		reset-names = "master", "slave", "crypto";
++		reset-names = "master", "slave", "crypto-rst";
+ 	};
+ 
+ 	i2c1: i2c@ff110000 {
diff --git a/target/linux/rockchip/patches-6.1/085-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch b/target/linux/rockchip/patches-6.1/085-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch
new file mode 100644
index 00000000000..33f3a1856bb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/085-arm64-dts-rockchip-Add-Radxa-CM3I-E25.patch
@@ -0,0 +1,690 @@
+From c70ee1dae63aaeaaced4e2689711f3f584a70bfd Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Fri, 9 Dec 2022 18:25:24 +0800
+Subject: [PATCH 085/383] arm64: dts: rockchip: Add Radxa CM3I E25
+
+Radxa E25 is a network application carrier board for the Radxa CM3
+Industrial (CM3I) SoM, which is based on the Rockchip RK3568 SoC.
+
+It has the following features:
+
+- MicroSD card socket, on board eMMC flash
+- 2x 2.5GbE Realtek RTL8125B Ethernet transceiver
+- 1x USB Type-C port (Power and Serial console)
+- 1x USB 3.0 OTG port
+- mini PCIe socket (USB or PCIe)
+- ngff PCIe socket (USB or SATA)
+- 1x User LED and 16x RGB LEDs
+- 26-pin expansion header
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20221209102524.129367-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3568-radxa-cm3i.dtsi  | 416 ++++++++++++++++++
+ .../boot/dts/rockchip/rk3568-radxa-e25.dts    | 229 ++++++++++
+ 3 files changed, 646 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -81,4 +81,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+@@ -0,0 +1,416 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3568.dtsi"
++
++/ {
++	model = "Radxa CM3 Industrial Board";
++	compatible = "radxa,cm3i", "rockchip,rk3568";
++
++	aliases {
++		mmc0 = &sdhci;
++	};
++
++	chosen {
++		stdout-path = "serial2:115200n8";
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++
++		led_user: led-0 {
++			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++			function = LED_FUNCTION_HEARTBEAT;
++			color = <LED_COLOR_ID_GREEN>;
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&led_user_en>;
++		};
++	};
++
++	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd0v9";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v_input>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v_input>;
++	};
++
++	/* labeled +5v_input in schematic */
++	vcc5v_input: vcc5v-input-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v_input";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++};
++
++&combphy0 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&display_subsystem {
++	status = "disabled";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v_input>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-name = "vdd_gpu";
++				regulator-always-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-name = "vdda0v9_image";
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&pinctrl {
++	leds {
++		led_user_en: led_user_en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic_int {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio2-supply = <&vcc_1v8>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	extcon = <&usb2phy0>;
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -0,0 +1,229 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include "rk3568-radxa-cm3i.dtsi"
++
++/ {
++	model = "Radxa E25";
++	compatible = "radxa,e25", "rockchip,rk3568";
++
++	aliases {
++		mmc0 = &sdmmc0;
++		mmc1 = &sdhci;
++	};
++
++	pwm-leds {
++		compatible = "pwm-leds-multicolor";
++
++		multi-led {
++			color = <LED_COLOR_ID_RGB>;
++			max-brightness = <255>;
++
++			led-red {
++				color = <LED_COLOR_ID_RED>;
++				pwms = <&pwm1 0 1000000 0>;
++			};
++
++			led-green {
++				color = <LED_COLOR_ID_GREEN>;
++				pwms = <&pwm2 0 1000000 0>;
++			};
++
++			led-blue {
++				color = <LED_COLOR_ID_BLUE>;
++				pwms = <&pwm12 0 1000000 0>;
++			};
++		};
++	};
++
++	vbus_typec: vbus-typec-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vbus_typec_en>;
++		regulator-name = "vbus_typec";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc3v3_minipcie: vcc3v3-minipcie-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio3 RK_PA7 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&minipcie_enable_h>;
++		regulator-name = "vcc3v3_minipcie";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc3v3_ngff: vcc3v3-ngff-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&ngffpcie_enable_h>;
++		regulator-name = "vcc3v3_ngff";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	/* actually fed by vcc5v0_sys, dependent
++	 * on pi6c clock generator
++	 */
++	vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie30x1_enable_h>;
++		regulator-name = "vcc3v3_pcie30x1";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_pi6c_05>;
++	};
++
++	vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pcie_enable_h>;
++		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++};
++
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie20_reset_h>;
++	reset-gpios = <&gpio1 RK_PB2 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
++	status = "okay";
++};
++
++&pcie30phy {
++	data-lanes = <1 2>;
++	status = "okay";
++};
++
++&pcie3x1 {
++	num-lanes = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie30x1m0_pins>;
++	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie30x1>;
++	status = "okay";
++};
++
++&pcie3x2 {
++	num-lanes = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie30x2_reset_h>;
++	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pi6c_05>;
++	status = "okay";
++};
++
++&pinctrl {
++	pcie {
++		pcie20_reset_h: pcie20-reset-h {
++			rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie30x1_enable_h: pcie30x1-enable-h {
++			rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie30x2_reset_h: pcie30x2-reset-h {
++			rockchip,pins = <2 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		pcie_enable_h: pcie-enable-h {
++			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		minipcie_enable_h: minipcie-enable-h {
++			rockchip,pins = <3 RK_PA7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		ngffpcie_enable_h: ngffpcie-enable-h {
++			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vbus_typec_en: vbus_typec_en {
++			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pwm1 {
++	status = "okay";
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&pwm12 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pwm12m1_pins>;
++	status = "okay";
++};
++
++&sdmmc0 {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
++	/* Also used in pcie30x1_clkreqnm0 */
++	disable-wp;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd>;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vbus_typec>;
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc3v3_minipcie>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc3v3_ngff>;
++	status = "okay";
++};
diff --git a/package/boot/uboot-rockchip/patches/019-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat-Zero-N.patch b/target/linux/rockchip/patches-6.1/086-arm64-dts-rockchip-Add-EmbedFire-LubanCat-1.patch
similarity index 60%
rename from package/boot/uboot-rockchip/patches/019-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat-Zero-N.patch
rename to target/linux/rockchip/patches-6.1/086-arm64-dts-rockchip-Add-EmbedFire-LubanCat-1.patch
index d8ee19fbaab..8c0130cd198 100644
--- a/package/boot/uboot-rockchip/patches/019-rockchip-rk3566-Add-support-for-EmbedFire-LubanCat-Zero-N.patch
+++ b/target/linux/rockchip/patches-6.1/086-arm64-dts-rockchip-Add-EmbedFire-LubanCat-1.patch
@@ -1,513 +1,643 @@
---- /dev/null
-+++ b/arch/arm/dts/rk3566-lubancat-zero-n.dts
-@@ -0,0 +1,482 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+* Copyright (c) 2021 Rockchip Electronics Co., Ltd.
-+* Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
-+*/
-+
-+/dts-v1/;
-+#include <dt-bindings/gpio/gpio.h>
-+#include <dt-bindings/leds/common.h>
-+#include <dt-bindings/pinctrl/rockchip.h>
-+#include "rk3566.dtsi"
-+
-+/ {
-+	model = "EmbedFire LubanCat Zero N";
-+	compatible = "embedfire,lubancat-zero-n", "rockchip,rk3566";
-+
-+	aliases {
-+		ethernet0 = &gmac1;
-+		mmc0 = &sdmmc0;
-+		mmc1 = &sdhci;
-+	};
-+
-+	chosen: chosen {
-+		stdout-path = "serial2:1500000n8";
-+	};
-+	
-+	gpio-leds {
-+		compatible = "gpio-leds";
-+
-+		sys_led: sys-led {
-+			label = "sys_led";
-+			linux,default-trigger = "heartbeat";
-+			default-state = "on";
-+			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
-+			pinctrl-names = "default";
-+			pinctrl-0 = <&sys_led_pin>;
-+		};
-+	};
-+
-+	dc_5v: dc-5v {
-+		compatible = "regulator-fixed";
-+		regulator-name = "dc_5v";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+	};
-+
-+	vcc3v3_sys: vcc3v3-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc3v3_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+
-+	vcc5v0_sys: vcc5v0-sys {
-+		compatible = "regulator-fixed";
-+		regulator-name = "vcc5v0_sys";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		vin-supply = <&dc_5v>;
-+	};
-+
-+	pcie_3v3: pcie2-3v3-regulator {
-+		compatible = "regulator-fixed";
-+		regulator-name = "pcie_3v3";
-+		regulator-min-microvolt = <3300000>;
-+		regulator-max-microvolt = <3300000>;
-+		enable-active-high;
-+		gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
-+		startup-delay-us = <5000>;
-+		vin-supply = <&vcc5v0_sys>;
-+	};
-+};
-+
-+&uart2 {
-+	status = "okay";
-+};
-+
-+&combphy1 {
-+	status = "okay";
-+};
-+
-+&combphy2 {
-+	status = "okay";
-+};
-+
-+&cpu0 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu1 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu2 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&cpu3 {
-+	cpu-supply = <&vdd_cpu>;
-+};
-+
-+&gpu {
-+	mali-supply = <&vdd_gpu>;
-+	status = "okay";
-+};
-+
-+&i2c0 {
-+	status = "okay";
-+
-+	vdd_cpu: regulator@1c {
-+		compatible = "tcs,tcs4525";
-+		reg = <0x1c>;
-+		fcs,suspend-voltage-selector = <1>;
-+		regulator-name = "vdd_cpu";
-+		regulator-always-on;
-+		regulator-boot-on;
-+		regulator-min-microvolt = <800000>;
-+		regulator-max-microvolt = <1150000>;
-+		regulator-ramp-delay = <2300>;
-+		vin-supply = <&vcc5v0_sys>;
-+
-+		regulator-state-mem {
-+			regulator-off-in-suspend;
-+		};
-+	};
-+
-+	rk809: pmic@20 {
-+		compatible = "rockchip,rk809";
-+		reg = <0x20>;
-+		interrupt-parent = <&gpio0>;
-+		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
-+		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
-+		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
-+		#clock-cells = <1>;
-+		clock-names = "mclk";
-+		clocks = <&cru I2S1_MCLKOUT_TX>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&pmic_int>;
-+		rockchip,system-power-controller;
-+		#sound-dai-cells = <0>;
-+		vcc1-supply = <&vcc3v3_sys>;
-+		vcc2-supply = <&vcc3v3_sys>;
-+		vcc3-supply = <&vcc3v3_sys>;
-+		vcc4-supply = <&vcc3v3_sys>;
-+		vcc5-supply = <&vcc3v3_sys>;
-+		vcc6-supply = <&vcc3v3_sys>;
-+		vcc7-supply = <&vcc3v3_sys>;
-+		vcc8-supply = <&vcc3v3_sys>;
-+		vcc9-supply = <&vcc3v3_sys>;
-+		wakeup-source;
-+
-+		regulators {
-+			vdd_logic: DCDC_REG1 {
-+				regulator-name = "vdd_logic";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdd_gpu: DCDC_REG2 {
-+				regulator-name = "vdd_gpu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_ddr: DCDC_REG3 {
-+				regulator-name = "vcc_ddr";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+				};
-+			};
-+
-+			vdd_npu: DCDC_REG4 {
-+				regulator-name = "vdd_npu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <500000>;
-+				regulator-max-microvolt = <1350000>;
-+				regulator-init-microvolt = <900000>;
-+				regulator-ramp-delay = <6001>;
-+				regulator-initial-mode = <0x2>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_1v8: DCDC_REG5 {
-+				regulator-name = "vcc_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_image: LDO_REG1 {
-+				regulator-name = "vdda0v9_image";
-+				regulator-boot-on;
-+				regulator-always-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda_0v9: LDO_REG2 {
-+				regulator-name = "vdda_0v9";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vdda0v9_pmu: LDO_REG3 {
-+				regulator-name = "vdda0v9_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <900000>;
-+				regulator-max-microvolt = <900000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <900000>;
-+				};
-+			};
-+
-+			vccio_acodec: LDO_REG4 {
-+				regulator-name = "vccio_acodec";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vccio_sd: LDO_REG5 {
-+				regulator-name = "vccio_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_pmu: LDO_REG6 {
-+				regulator-name = "vcc3v3_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <3300000>;
-+				regulator-max-microvolt = <3300000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <3300000>;
-+				};
-+			};
-+
-+			vcca_1v8: LDO_REG7 {
-+				regulator-name = "vcca_1v8";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcca1v8_pmu: LDO_REG8 {
-+				regulator-name = "vcca1v8_pmu";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-on-in-suspend;
-+					regulator-suspend-microvolt = <1800000>;
-+				};
-+			};
-+
-+			vcca1v8_image: LDO_REG9 {
-+				regulator-name = "vcca1v8_image";
-+				regulator-always-on;
-+				regulator-boot-on;
-+				regulator-min-microvolt = <1800000>;
-+				regulator-max-microvolt = <1800000>;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc_3v3: SWITCH_REG1 {
-+				regulator-name = "vcc_3v3";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+
-+			vcc3v3_sd: SWITCH_REG2 {
-+				regulator-name = "vcc3v3_sd";
-+				regulator-always-on;
-+				regulator-boot-on;
-+
-+				regulator-state-mem {
-+					regulator-off-in-suspend;
-+				};
-+			};
-+		};
-+	};
-+};
-+
-+&i2s1_8ch {
-+	rockchip,trcm-sync-tx-only;
-+	status = "okay";
-+};
-+
-+&gmac1 {
-+    phy-mode = "rgmii";
-+    clock_in_out = "output";
-+
-+    snps,reset-gpio = <&gpio2 RK_PB2 GPIO_ACTIVE_LOW>;
-+    snps,reset-active-low;
-+    /* Reset time is 100ms, 100ms */
-+    snps,reset-delays-us = <0 75000 100000>;
-+
-+    assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
-+    assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
-+    assigned-clock-rates = <0>, <125000000>;
-+
-+    pinctrl-names = "default";
-+    pinctrl-0 = <&gmac1m1_miim
-+             &gmac1m1_tx_bus2_level3
-+             &gmac1m1_rx_bus2
-+             &gmac1m1_rgmii_clk_level2
-+             &gmac1m1_rgmii_bus_level3>;
-+
-+    tx_delay = <0x24>;
-+    rx_delay = <0x08>;
-+
-+    phy-handle = <&rgmii_phy1>;
-+    status = "okay";
-+};
-+
-+&mdio1 {
-+    rgmii_phy1: phy@0 {
-+        compatible = "ethernet-phy-ieee802.3-c22";
-+        reg = <0x0>;
-+    };
-+};
-+
-+&pmu_io_domains {
-+	pmuio2-supply = <&vcc3v3_pmu>;
-+	vccio1-supply = <&vccio_acodec>;
-+	vccio3-supply = <&vccio_sd>;
-+	vccio4-supply = <&vcc_1v8>;
-+	vccio5-supply = <&vcc_3v3>;
-+	vccio6-supply = <&vcc_1v8>;
-+	vccio7-supply = <&vcc_3v3>;
-+	status = "okay";
-+};
-+
-+&saradc {
-+	vref-supply = <&vcca_1v8>;
-+	status = "okay";
-+};
-+
-+&tsadc {
-+	rockchip,hw-tshut-mode = <1>;
-+	rockchip,hw-tshut-polarity = <0>;
-+	status = "okay";
-+};
-+
-+&sdhci {
-+	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
-+	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
-+	bus-width = <8>;
-+	max-frequency = <150000000>;
-+	mmc-hs200-1_8v;		
-+	non-removable;	
-+	pinctrl-names = "default";
-+	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;	
-+	supports-emmc;
-+	vmmc-supply = <&vcc_3v3>;
-+	vqmmc-supply = <&vcc_1v8>;
-+	status = "okay";
-+};
-+
-+&sdmmc0 {
-+    max-frequency = <150000000>;
-+    supports-sd;
-+    bus-width = <4>;
-+    cap-mmc-highspeed;
-+    cap-sd-highspeed;
-+    disable-wp;
-+    sd-uhs-sdr104;
-+    vmmc-supply = <&vcc3v3_sd>;
-+    vqmmc-supply = <&vccio_sd>;
-+    pinctrl-names = "default";
-+    pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
-+    status = "okay";
-+};
-+
-+&usb_host0_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host0_ohci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ehci {
-+	status = "okay";
-+};
-+
-+&usb_host1_ohci {
-+	status = "okay";
-+};
-+
-+&pinctrl {
-+	leds {
-+		sys_led_pin: sys-status-led-pin {
-+			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
-+
-+	pmic {
-+		pmic_int: pmic_int {
-+			rockchip,pins =
-+				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
-+		};
-+	};
-+};
---- /dev/null
-+++ b/arch/arm/dts/rk3566-lubancat-zero-n-u-boot.dtsi
-@@ -0,0 +1,25 @@
-+// SPDX-License-Identifier: GPL-2.0+
-+/*
-+ * (C) Copyright 2021 Rockchip Electronics Co., Ltd
-+ */
-+
-+#include "rk3568-u-boot.dtsi"
-+
-+/ {
-+	chosen {
-+		stdout-path = &uart2;
-+		u-boot,spl-boot-order = "same-as-spl", &sdmmc0, &sdhci;
-+	};
-+};
-+
-+&sdmmc0 {
-+	bus-width = <4>;
-+	u-boot,dm-spl;
-+	u-boot,spl-fifo-mode;
-+};
-+
-+&uart2 {
-+	clock-frequency = <24000000>;
-+	u-boot,dm-spl;
-+	status = "okay";
-+};
+From 9bec1f11987b47c0eb4fbc45fd30267afc6fa030 Mon Sep 17 00:00:00 2001
+From: Wenhao Cui <lasstp5011@gmail.com>
+Date: Fri, 23 Dec 2022 11:16:30 +0800
+Subject: [PATCH 086/383] arm64: dts: rockchip: Add EmbedFire LubanCat 1
+
+The LubanCat 1 is a RK3566 based SBC, developed by Dongguan EmbedFire
+Electronic Technology Co., Ltd.
+
+It has the following characteristics:
+- MicroSD card slot, onboard eMMC flash memory
+- 1GbE Realtek RTL8211F Ethernet Transceiver
+- 1 USB Type-C port (power and USB2.0 OTG)
+- 1 USB 3.0 Host port
+- 3 USB 2.0 Host ports
+- 1 HDMI
+- 1 infrared receiver
+- 1 MIPI DSI
+- 1 MIPI CSI
+- 1 x 4-section headphone jack
+- Mini PCIe socket (USB or PCIe)
+- 1 SIM Card slot
+- 1 SYS LED and 1 PWR LED
+- 40-pin GPIO expansion header
+
+Signed-off-by: Wenhao Cui <lasstp5011@gmail.com>
+Signed-off-by: Yuteng Zhong <zonyitoo@gmail.com>
+Link: https://lore.kernel.org/r/Y6UdjhBD/Xa7ALya@VM-66-53-centos
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3566-lubancat-1.dts   | 595 ++++++++++++++++++
+ 2 files changed, 596 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -78,6 +78,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-lubancat-1.dts
+@@ -0,0 +1,595 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3566.dtsi"
++
++/ {
++	model = "EmbedFire LubanCat 1";
++	compatible = "embedfire,lubancat-1", "rockchip,rk3566";
++
++	aliases {
++		ethernet0 = &gmac1;
++		mmc0 = &sdmmc0;
++		mmc1 = &sdhci;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gmac1_clkin: external-gmac1-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac1_clkin";
++		#clock-cells = <0>;
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++
++		sys_led: sys-led {
++			label = "sys_led";
++			linux,default-trigger = "heartbeat";
++			default-state = "on";
++			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&sys_led_pin>;
++		};
++	};
++
++	usb_5v: usb-5v-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "usb_5v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&usb_5v>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
++		startup-delay-us = <5000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio2 RK_PB6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb20_host_en>;
++		regulator-name = "vcc5v0_usb20_host";
++		regulator-always-on;
++	};
++
++	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio2 RK_PB5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb30_host_en>;
++		regulator-name = "vcc5v0_usb30_host";
++		regulator-always-on;
++	};
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		clock-output-names = "rk808-clkout1", "rk808-clkout2";
++
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>;
++		rockchip,system-power-controller;
++		wakeup-source;
++		#clock-cells = <1>;
++
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-init-microvolt = <900000>;
++				regulator-ramp-delay = <6001>;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-name = "vdd_gpu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-init-microvolt = <900000>;
++				regulator-ramp-delay = <6001>;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-init-microvolt = <900000>;
++				regulator-ramp-delay = <6001>;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-name = "vdda0v9_image";
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2s1_8ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&gmac1 {
++	phy-mode = "rgmii";
++	clock_in_out = "output";
++	snps,reset-gpio = <&gpio2 RK_PB0 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 75ms, 100ms */
++	snps,reset-delays-us = <0 75000 100000>;
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
++	assigned-clock-rates = <0>, <125000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m1_miim
++			&gmac1m1_tx_bus2_level3
++			&gmac1m1_rx_bus2
++			&gmac1m1_rgmii_clk_level2
++			&gmac1m1_rgmii_bus_level3>;
++	tx_delay = <0x1a>;
++	rx_delay = <0x0c>;
++	phy-handle = <&rgmii_phy1>;
++	status = "okay";
++};
++
++&mdio1 {
++	rgmii_phy1: phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x0>;
++	};
++};
++
++&pcie2x1 {
++	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
++	disable-gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pinctrl {
++	leds {
++		sys_led_pin: sys-status-led-pin {
++			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
++			rockchip,pins = <2 RK_PB6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
++			rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic_int {
++			rockchip,pins =
++				<0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_3v3>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&sdhci {
++	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
++	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
++	supports-emmc;
++	status = "okay";
++};
++
++&sdmmc0 {
++	max-frequency = <150000000>;
++	supports-sd;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	status = "okay";
++};
++
++/* USB OTG/USB Host_1 USB 2.0 Comb */
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++/* USB Host_2/USB Host_3 USB 2.0 Comb */
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++/* USB3.0 Host */
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/087-arm64-dts-rockchip-remove-unsupported-property-from-.patch b/target/linux/rockchip/patches-6.1/087-arm64-dts-rockchip-remove-unsupported-property-from-.patch
new file mode 100644
index 00000000000..3ea76f09ccd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/087-arm64-dts-rockchip-remove-unsupported-property-from-.patch
@@ -0,0 +1,27 @@
+From a21d56b1a3051c07ccaebafe1c9964f38f91277b Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Mon, 19 Dec 2022 18:10:52 +0800
+Subject: [PATCH 087/383] arm64: dts: rockchip: remove unsupported property
+ from sdmmc2 for rock-3a
+
+'supports-sdio' is not part of the DT binding
+and not supported by the Linux driver.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20221219101052.7899-1-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -739,7 +739,6 @@
+ };
+ 
+ &sdmmc2 {
+-	supports-sdio;
+ 	bus-width = <4>;
+ 	disable-wp;
+ 	cap-sd-highspeed;
diff --git a/target/linux/rockchip/patches-6.1/088-arm64-dts-rockchip-add-audio-nodes-to-rk3566-roc-pc.patch b/target/linux/rockchip/patches-6.1/088-arm64-dts-rockchip-add-audio-nodes-to-rk3566-roc-pc.patch
new file mode 100644
index 00000000000..6387694d02e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/088-arm64-dts-rockchip-add-audio-nodes-to-rk3566-roc-pc.patch
@@ -0,0 +1,107 @@
+From bc6cef04f7c3883dbef48280f36f9e378abf55a7 Mon Sep 17 00:00:00 2001
+From: Furkan Kardame <f.kardame@manjaro.org>
+Date: Mon, 9 Jan 2023 23:32:33 +0300
+Subject: [PATCH 088/383] arm64: dts: rockchip: add audio nodes to
+ rk3566-roc-pc
+
+This patch adds simple audio card nodes
+Enabled i2s0_8ch as it is needed for hdmi audio
+
+Added i2s1_8ch as it is needed for 3.5mm audio jack and limit it to a
+single-channel, as i2s1m0_sdo{1,2,3} and i2s1m0_sdi{1,2,3} are used
+by pcie.
+
+Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
+Link: https://lore.kernel.org/r/20230109203232.45192-1-f.kardame@manjaro.org
+[dropped the duplicate i2s@fe410000 node]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 44 ++++++++++++++++++-
+ 1 file changed, 42 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
+@@ -53,6 +53,22 @@
+ 		};
+ 	};
+ 
++	rk809-sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,format = "i2s";
++		simple-audio-card,name = "STATION-M2-FRONT";
++		simple-audio-card,mclk-fs = <256>;
++		status = "okay";
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++
++		simple-audio-card,codec {
++			sound-dai = <&rk809>;
++		};
++	};
++
+ 	sdio_pwrseq: sdio-pwrseq {
+ 		status = "okay";
+ 		compatible = "mmc-pwrseq-simple";
+@@ -200,6 +216,10 @@
+ 	};
+ };
+ 
++&hdmi_sound {
++	status = "okay";
++};
++
+ &i2c0 {
+ 	status = "okay";
+ 
+@@ -226,12 +246,16 @@
+ 		interrupt-parent = <&gpio0>;
+ 		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ 		clock-output-names = "rk808-clkout1", "rk808-clkout2";
+-
++		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
++		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT_TX>;
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int>;
++		pinctrl-0 = <&pmic_int>, <&i2s1m0_mclk>;
+ 		rockchip,system-power-controller;
+ 		wakeup-source;
+ 		#clock-cells = <1>;
++		#sound-dai-cells = <0>;
+ 
+ 		vcc1-supply = <&vcc3v3_sys>;
+ 		vcc2-supply = <&vcc3v3_sys>;
+@@ -243,6 +267,10 @@
+ 		vcc8-supply = <&vcc3v3_sys>;
+ 		vcc9-supply = <&vcc3v3_sys>;
+ 
++		codec {
++			mic-in-differential;
++		};
++
+ 		regulators {
+ 			vdd_log: DCDC_REG1 {
+ 				regulator-name = "vdd_log";
+@@ -452,6 +480,18 @@
+ 	status = "okay";
+ };
+ 
++&i2s0_8ch {
++	status = "okay";
++};
++
++&i2s1_8ch {
++	pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
++			&i2s1m0_lrcktx &i2s1m0_lrckrx
++			&i2s1m0_sdi0   &i2s1m0_sdo0>;
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
+ &mdio1 {
+ 	rgmii_phy1: ethernet-phy@0 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
diff --git a/target/linux/rockchip/patches-6.1/089-arm64-dts-rockchip-Add-dts-for-EmbedFire-rk3568-Luba.patch b/target/linux/rockchip/patches-6.1/089-arm64-dts-rockchip-Add-dts-for-EmbedFire-rk3568-Luba.patch
new file mode 100644
index 00000000000..9fbc5d519b4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/089-arm64-dts-rockchip-Add-dts-for-EmbedFire-rk3568-Luba.patch
@@ -0,0 +1,778 @@
+From 3c681873c055b2a61e8124cd5501ff3fd4dda349 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@163.com>
+Date: Sun, 8 Jan 2023 19:08:17 +0800
+Subject: [PATCH 089/383] arm64: dts: rockchip: Add dts for EmbedFire rk3568
+ LubanCat 2
+
+LubanCat 2 is a rk3568 based SBC from EmbedFire.
+
+Specification:
+- Rockchip rk3568
+- LPDDR4/4X 1/2/4/8 GB
+- TF scard slot
+- eMMC 8/32/64/128 GB
+- Gigabit ethernet x 2
+- HDMI out
+- USB 2.0 Host x 1
+- USB 2.0 Type-C OTG x 1
+- USB 3.0 Host x 1
+- Mini PCIE interface for WIFI/BT module
+- M.2 key for 2280 NVME
+- 40 pin header
+
+Signed-off-by: Andy Yan <andyshrk@163.com>
+Link: https://lore.kernel.org/r/20230108110817.2214859-1-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3568-lubancat-2.dts   | 733 ++++++++++++++++++
+ 2 files changed, 734 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-lubancat-2.dts
+@@ -0,0 +1,733 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2022 EmbedFire <embedfire@embedfire.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++	model = "EmbedFire LubanCat 2";
++	compatible = "embedfire,lubancat-2", "rockchip,rk3568";
++
++	aliases {
++		ethernet0 = &gmac0;
++		ethernet1 = &gmac1;
++		mmc0 = &sdmmc0;
++		mmc1 = &sdhci;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		user_led: user-led {
++			label = "user_led";
++			linux,default-trigger = "heartbeat";
++			default-state = "on";
++			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&user_led_pin>;
++		};
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	dc_5v: dc-5v-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_5v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_5v>;
++	};
++
++	vcc3v3_m2_pcie: vcc3v3-m2-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "m2_pcie_3v3";
++		enable-active-high;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&vcc3v3_m2_pcie_en>;
++		pinctrl-names = "default";
++		startup-delay-us = <200000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc3v3_mini_pcie: vcc3v3-mini-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "minipcie_3v3";
++		enable-active-high;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		gpio = <&gpio3 RK_PC3 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&vcc3v3_mini_pcie_en>;
++		pinctrl-names = "default";
++		startup-delay-us = <5000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_usb20_host: vcc5v0-usb20-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb20_host";
++		enable-active-high;
++		gpio = <&gpio0 RK_PD5 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&vcc5v0_usb20_host_en>;
++		pinctrl-names = "default";
++	};
++
++	vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb30_host";
++		enable-active-high;
++		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&vcc5v0_usb30_host_en>;
++		pinctrl-names = "default";
++	};
++
++	vcc5v0_otg_vbus: vcc5v0-otg-vbus-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_otg_vbus";
++		enable-active-high;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		gpio = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&vcc5v0_otg_vbus_en>;
++		pinctrl-names = "default";
++	};
++};
++
++&combphy0 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		assigned-clocks = <&cru I2S1_MCLKOUT_TX>;
++		assigned-clock-parents = <&cru CLK_I2S1_8CH_TX>;
++		#clock-cells = <1>;
++		clock-names = "mclk";
++		clocks = <&cru I2S1_MCLKOUT_TX>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>;
++		rockchip,system-power-controller;
++		#sound-dai-cells = <0>;
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		wakeup-source;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-init-microvolt = <900000>;
++				regulator-ramp-delay = <6001>;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-name = "vdd_gpu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-init-microvolt = <900000>;
++				regulator-ramp-delay = <6001>;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-init-microvolt = <900000>;
++				regulator-ramp-delay = <6001>;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-name = "vdda0v9_image";
++				regulator-boot-on;
++				regulator-always-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2s1_8ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&gmac0 {
++	phy-mode = "rgmii";
++	clock_in_out = "output";
++
++	snps,reset-gpio = <&gpio2 RK_PD3 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++
++	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac0_miim
++		     &gmac0_tx_bus2
++		     &gmac0_rx_bus2
++		     &gmac0_rgmii_clk
++		     &gmac0_rgmii_bus>;
++
++	tx_delay = <0x22>;
++	rx_delay = <0x0e>;
++
++	phy-handle = <&rgmii_phy0>;
++	status = "okay";
++};
++
++&mdio0 {
++	rgmii_phy0: phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x0>;
++	};
++};
++
++&gmac1 {
++	phy-mode = "rgmii";
++	clock_in_out = "output";
++
++	snps,reset-gpio = <&gpio3 RK_PA2 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m1_miim
++		     &gmac1m1_tx_bus2
++		     &gmac1m1_rx_bus2
++		     &gmac1m1_rgmii_clk
++		     &gmac1m1_rgmii_bus>;
++
++	tx_delay = <0x21>;
++	rx_delay = <0x0e>;
++
++	phy-handle = <&rgmii_phy1>;
++	status = "okay";
++};
++
++&mdio1 {
++	rgmii_phy1: phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x0>;
++	};
++};
++
++&gic {
++	mbi-ranges = <94 31>, <229 31>, <289 31>;
++};
++
++&pcie30phy {
++	status = "okay";
++};
++
++&pcie3x2 {
++	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_m2_pcie>;
++	status = "okay";
++};
++
++&pcie2x1 {
++	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
++	disable-gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_mini_pcie>;
++	status = "okay";
++};
++
++&pmu_io_domains {
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&pwm8 {
++	status = "okay";
++};
++
++&pwm9 {
++	status = "disabled";
++};
++
++&pwm10 {
++	status = "disabled";
++};
++
++&pwm14 {
++	status = "disabled";
++};
++
++&spi3 {
++	pinctrl-0 = <&spi3m1_pins>;
++	status = "disabled";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&uart3 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart3m1_xfer>;
++	status = "disabled";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&sdhci {
++	assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>, <&cru CCLK_EMMC>;
++	assigned-clock-rates = <200000000>, <24000000>, <200000000>;
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
++	supports-emmc;
++	status = "okay";
++};
++
++&sdmmc0 {
++	max-frequency = <150000000>;
++	no-sdio;
++	no-mmc;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	status = "okay";
++};
++
++/* USB OTG/USB Host_1 USB 2.0 Comb */
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb30_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_otg_vbus>;
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++/* USB Host_2/USB Host_3 USB 2.0 Comb */
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	phy-supply = <&vcc5v0_usb20_host>;
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++/* MULTI_PHY0 For SATA0, USB3.0 OTG Only USB2.0 */
++&usb_host0_xhci {
++	phys = <&usb2phy0_otg>;
++	phy-names = "usb2-phy";
++	extcon = <&usb2phy0>;
++	maximum-speed = "high-speed";
++	dr_mode = "host";
++	status = "okay";
++};
++
++&sata0 {
++	status = "okay";
++};
++
++/* USB3.0 Host */
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
++
++&pinctrl {
++	leds {
++		user_led_pin: user-status-led-pin {
++			rockchip,pins = <0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb20_host_en: vcc5v0-usb20-host-en {
++			rockchip,pins = <0 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_usb30_host_en: vcc5v0-usb30-host-en {
++			rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_otg_vbus_en: vcc5v0-otg-vbus-en {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pcie {
++		vcc3v3_m2_pcie_en: vcc3v3-m2-pcie-en {
++			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc3v3_mini_pcie_en: vcc3v3-mini-pcie-en {
++			rockchip,pins = <3 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic-int {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/090-arm64-dts-rockchip-Add-IR-receiver-to-BPI-R2Pro.patch b/target/linux/rockchip/patches-6.1/090-arm64-dts-rockchip-Add-IR-receiver-to-BPI-R2Pro.patch
new file mode 100644
index 00000000000..59dbc97f9b1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/090-arm64-dts-rockchip-Add-IR-receiver-to-BPI-R2Pro.patch
@@ -0,0 +1,48 @@
+From d3df837379b772e85ea00071a01c8eb97593ed32 Mon Sep 17 00:00:00 2001
+From: Alex Riabchenko <d3adme4t@gmail.com>
+Date: Wed, 14 Dec 2022 16:54:33 +0100
+Subject: [PATCH 090/383] arm64: dts: rockchip: Add IR receiver to BPI-R2Pro
+
+Add the infrared receiver and its associated pinctrl entry.
+
+Based on Aurelien Jarno's patchset:
+https://lore.kernel.org/lkml/20220930051246.391614-14-aurelien@aurel32.net/
+
+Signed-off-by: Alex Riabchenko <d3adme4t@gmail.com>
+Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
+Link: https://lore.kernel.org/r/20221214155433.112257-1-linux@fw-web.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts | 13 +++++++++++++
+ 1 file changed, 13 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-bpi-r2-pro.dts
+@@ -66,6 +66,13 @@
+ 		};
+ 	};
+ 
++	ir-receiver {
++		compatible = "gpio-ir-receiver";
++		gpios = <&gpio0 RK_PC2 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&ir_receiver_pin>;
++	};
++
+ 	vcc3v3_sys: vcc3v3-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc3v3_sys";
+@@ -614,6 +621,12 @@
+ 		};
+ 	};
+ 
++	ir-receiver {
++		ir_receiver_pin: ir-receiver-pin {
++			rockchip,pins = <0 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pcie {
+ 		minipcie_enable_h: minipcie-enable-h {
+ 			rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none_drv_level_5>;
diff --git a/target/linux/rockchip/patches-6.1/091-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch b/target/linux/rockchip/patches-6.1/091-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch
new file mode 100644
index 00000000000..8c90c07a432
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/091-arm64-dts-rockchip-rk3328-Add-Orange-Pi-R1-Plus.patch
@@ -0,0 +1,408 @@
+From 80a48862e4e7f33159efc514d1cb0d081a3f7440 Mon Sep 17 00:00:00 2001
+From: Chukun Pan <amadeus@jmu.edu.cn>
+Date: Sat, 3 Dec 2022 15:41:49 +0800
+Subject: [PATCH 091/383] arm64: dts: rockchip: rk3328: Add Orange Pi R1 Plus
+
+Orange Pi R1 Plus is a Rockchip RK3328 based SBC by Xunlong.
+
+This device is similar to the NanoPi R2S, and has a 16MB
+SPI NOR (mx25l12805d). The reset button is changed to
+directly reset the power supply, another detail is that
+both network ports have independent MAC addresses.
+
+Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn>
+Link: https://lore.kernel.org/r/20221203074149.11543-3-amadeus@jmu.edu.cn
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3328-orangepi-r1-plus.dts  | 373 ++++++++++++++++++
+ 2 files changed, 374 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
+@@ -0,0 +1,373 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Based on rk3328-nanopi-r2s.dts, which is:
++ *   Copyright (c) 2020 David Bauer <mail@david-bauer.net>
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include "rk3328.dtsi"
++
++/ {
++	model = "Xunlong Orange Pi R1 Plus";
++	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
++
++	aliases {
++		ethernet1 = &rtl8153;
++		mmc0 = &sdmmc;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gmac_clk: gmac-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac_clkin";
++		#clock-cells = <0>;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-0 = <&lan_led_pin>, <&sys_led_pin>, <&wan_led_pin>;
++		pinctrl-names = "default";
++
++		led-0 {
++			function = LED_FUNCTION_LAN;
++			color = <LED_COLOR_ID_GREEN>;
++			gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-1 {
++			function = LED_FUNCTION_STATUS;
++			color = <LED_COLOR_ID_RED>;
++			gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++		};
++
++		led-2 {
++			function = LED_FUNCTION_WAN;
++			color = <LED_COLOR_ID_GREEN>;
++			gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	vcc_sd: sdmmc-regulator {
++		compatible = "regulator-fixed";
++		gpio = <&gpio0 RK_PD6 GPIO_ACTIVE_LOW>;
++		pinctrl-0 = <&sdmmc0m1_pin>;
++		pinctrl-names = "default";
++		regulator-name = "vcc_sd";
++		regulator-boot-on;
++		vin-supply = <&vcc_io>;
++	};
++
++	vcc_sys: vcc-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vdd_5v_lan: vdd-5v-lan-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&lan_vdd_pin>;
++		pinctrl-names = "default";
++		regulator-name = "vdd_5v_lan";
++		regulator-always-on;
++		regulator-boot-on;
++		vin-supply = <&vcc_sys>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_arm>;
++};
++
++&display_subsystem {
++	status = "disabled";
++};
++
++&gmac2io {
++	assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>;
++	assigned-clock-parents = <&gmac_clk>, <&gmac_clk>;
++	clock_in_out = "input";
++	phy-handle = <&rtl8211e>;
++	phy-mode = "rgmii";
++	phy-supply = <&vcc_io>;
++	pinctrl-0 = <&rgmiim1_pins>;
++	pinctrl-names = "default";
++	snps,aal;
++	rx_delay = <0x18>;
++	tx_delay = <0x24>;
++	status = "okay";
++
++	mdio {
++		compatible = "snps,dwmac-mdio";
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		rtl8211e: ethernet-phy@1 {
++			reg = <1>;
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <10000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
++
++&i2c1 {
++	status = "okay";
++
++	rk805: pmic@18 {
++		compatible = "rockchip,rk805";
++		reg = <0x18>;
++		interrupt-parent = <&gpio1>;
++		interrupts = <24 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		clock-output-names = "xin32k", "rk805-clkout2";
++		gpio-controller;
++		#gpio-cells = <2>;
++		pinctrl-0 = <&pmic_int_l>;
++		pinctrl-names = "default";
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc5-supply = <&vcc_io>;
++		vcc6-supply = <&vcc_sys>;
++
++		regulators {
++			vdd_log: DCDC_REG1 {
++				regulator-name = "vdd_log";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1450000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++
++			vdd_arm: DCDC_REG2 {
++				regulator-name = "vdd_arm";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <712500>;
++				regulator-max-microvolt = <1450000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_io: DCDC_REG4 {
++				regulator-name = "vcc_io";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_18: LDO_REG1 {
++				regulator-name = "vcc_18";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc18_emmc: LDO_REG2 {
++				regulator-name = "vcc18_emmc";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_10: LDO_REG3 {
++				regulator-name = "vdd_10";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1000000>;
++				regulator-max-microvolt = <1000000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1000000>;
++				};
++			};
++		};
++	};
++};
++
++&io_domains {
++	pmuio-supply = <&vcc_io>;
++	vccio1-supply = <&vcc_io>;
++	vccio2-supply = <&vcc18_emmc>;
++	vccio3-supply = <&vcc_io>;
++	vccio4-supply = <&vcc_io>;
++	vccio5-supply = <&vcc_io>;
++	vccio6-supply = <&vcc_io>;
++	status = "okay";
++};
++
++&pinctrl {
++	gmac2io {
++		eth_phy_reset_pin: eth-phy-reset-pin {
++			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	leds {
++		lan_led_pin: lan-led-pin {
++			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		sys_led_pin: sys-led-pin {
++			rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wan_led_pin: wan-led-pin {
++			rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	lan {
++		lan_vdd_pin: lan-vdd-pin {
++			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	disable-wp;
++	pinctrl-0 = <&sdmmc0_clk>, <&sdmmc0_cmd>, <&sdmmc0_dectn>, <&sdmmc0_bus4>;
++	pinctrl-names = "default";
++	vmmc-supply = <&vcc_sd>;
++	status = "okay";
++};
++
++&spi0 {
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0>;
++		spi-max-frequency = <50000000>;
++	};
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <0>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&u2phy {
++	status = "okay";
++};
++
++&u2phy_host {
++	status = "okay";
++};
++
++&u2phy_otg {
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb20_otg {
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usbdrd3 {
++	dr_mode = "host";
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	/* Second port is for USB 3.0 */
++	rtl8153: device@2 {
++		compatible = "usbbda,8153";
++		reg = <2>;
++	};
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/092-arm64-dts-rockchip-Change-audio-card-name-for-Odroid.patch b/target/linux/rockchip/patches-6.1/092-arm64-dts-rockchip-Change-audio-card-name-for-Odroid.patch
new file mode 100644
index 00000000000..e81d5b93a6d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/092-arm64-dts-rockchip-Change-audio-card-name-for-Odroid.patch
@@ -0,0 +1,34 @@
+From 38e13dd40b3c7821da8a11b5c3905268a0def893 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Thu, 1 Dec 2022 14:36:52 -0600
+Subject: [PATCH 092/383] arm64: dts: rockchip: Change audio card name for
+ Odroid Go
+
+Change the audio card name for the Odroid Go Advance series to
+rk817_int. This matches the audio card name of the Anbernic RG353V.
+This is done to provide a consistent card name so that a single ALSA
+UCM file can be used for all (identical) implementations of this codec
+and configuration combo. The rk817_int configuration is for when the
+internal speaker amplifier of the rk817 is used. The other Anbernic
+devices have the name as rk817_ext for when an external speaker
+amplifier is used.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221201203655.1245-2-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+@@ -127,7 +127,7 @@
+ 
+ 	rk817-sound {
+ 		compatible = "simple-audio-card";
+-		simple-audio-card,name = "Analog";
++		simple-audio-card,name = "rk817_int";
+ 		simple-audio-card,format = "i2s";
+ 		simple-audio-card,hp-det-gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
+ 		simple-audio-card,mclk-fs = <256>;
diff --git a/target/linux/rockchip/patches-6.1/093-arm64-dts-rockchip-don-t-set-cpll-rate-for-Odroid-Go.patch b/target/linux/rockchip/patches-6.1/093-arm64-dts-rockchip-don-t-set-cpll-rate-for-Odroid-Go.patch
new file mode 100644
index 00000000000..86245c0e95d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/093-arm64-dts-rockchip-don-t-set-cpll-rate-for-Odroid-Go.patch
@@ -0,0 +1,38 @@
+From 29d572b918fc509a518b8464f4c768ddac70cc5a Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Thu, 1 Dec 2022 14:36:53 -0600
+Subject: [PATCH 093/383] arm64: dts: rockchip: don't set cpll rate for Odroid
+ Go
+
+The Odroid Go Advance devicetree tries to set the rate for the cpll
+clock to 17MHz, which is not a supported rate. This fails, and triggers
+the error of "clk: couldn't set cpll clk rate to 17000000 (-22),
+current rate: 17000000" in the dmesg log. Remove the incorrect rate.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221201203655.1245-3-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi | 6 ++----
+ 1 file changed, 2 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+@@ -192,14 +192,12 @@
+ 	assigned-clocks = <&cru PLL_NPLL>,
+ 		<&cru ACLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
+ 		<&cru HCLK_BUS_PRE>, <&cru HCLK_PERI_PRE>,
+-		<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>,
+-		<&cru PLL_CPLL>;
++		<&cru PCLK_BUS_PRE>, <&cru SCLK_GPU>;
+ 
+ 	assigned-clock-rates = <1188000000>,
+ 		<200000000>, <200000000>,
+ 		<150000000>, <150000000>,
+-		<100000000>, <200000000>,
+-		<17000000>;
++		<100000000>, <200000000>;
+ };
+ 
+ &display_subsystem {
diff --git a/target/linux/rockchip/patches-6.1/094-arm64-dts-rockchip-update-px30-thermal-zones-for-GPU.patch b/target/linux/rockchip/patches-6.1/094-arm64-dts-rockchip-update-px30-thermal-zones-for-GPU.patch
new file mode 100644
index 00000000000..5949f684b12
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/094-arm64-dts-rockchip-update-px30-thermal-zones-for-GPU.patch
@@ -0,0 +1,75 @@
+From 13ef5bfa596a6afed92018ee8c42de17ea856dfd Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Thu, 1 Dec 2022 14:36:54 -0600
+Subject: [PATCH 094/383] arm64: dts: rockchip: update px30 thermal zones for
+ GPU
+
+Without the trips, the following errors are received in the dmesg
+log and the rockchip-thermal driver fails to load the gpu sensor:
+
+"thermal_sys: Failed to find 'trips' node"
+"rockchip-thermal ff280000.tsadc: failed to register sensor 1: -22"
+
+Trip values are assumed, unfortunately, as the same values as the
+CPU. The datasheet and TRM didn't appear to have any information
+regarding thermals for the GPU.
+
+Stress tested successfully on my Odroid Go Advance.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221201203655.1245-4-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/px30.dtsi | 33 +++++++++++++++++++++-----
+ 1 file changed, 27 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
+@@ -210,12 +210,6 @@
+ 					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+ 					contribution = <4096>;
+ 				};
+-
+-				map1 {
+-					trip = <&target>;
+-					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
+-					contribution = <4096>;
+-				};
+ 			};
+ 		};
+ 
+@@ -223,6 +217,33 @@
+ 			polling-delay-passive = <100>; /* milliseconds */
+ 			polling-delay = <1000>; /* milliseconds */
+ 			thermal-sensors = <&tsadc 1>;
++
++			trips {
++				gpu_threshold: gpu-threshold {
++					temperature = <70000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				gpu_target: gpu-target {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++
++				gpu_crit: gpu-crit {
++					temperature = <115000>;
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&gpu_target>;
++					cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++				};
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/095-arm64-dts-rockchip-Update-leds-for-Odroid-Go-Advance.patch b/target/linux/rockchip/patches-6.1/095-arm64-dts-rockchip-Update-leds-for-Odroid-Go-Advance.patch
new file mode 100644
index 00000000000..4e0497a086b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/095-arm64-dts-rockchip-Update-leds-for-Odroid-Go-Advance.patch
@@ -0,0 +1,91 @@
+From 762b0235a905118ec7f1fe316334dcfa833b371f Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Thu, 1 Dec 2022 14:36:55 -0600
+Subject: [PATCH 095/383] arm64: dts: rockchip: Update leds for Odroid Go
+ Advance
+
+Update the blue LED to be controlled via pwm to enable control of LED
+brightness. Add red LED as a GPIO controlled LED. The documentation
+stated "label" was depreciated so function and color was used instead.
+The LED names (led-2 and led-3) are given because that is what they
+are numbered on the board itself; LED 1 is wired directly into an
+always on regulator and is not controllable. LED 2 is labelled "alive"
+on the board and documentation recommends we set the function as
+status over other miscellaneous functions. LED 3 is labelled "chg" on
+the board.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221201203655.1245-5-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3326-odroid-go.dtsi   | 33 +++++++++++++++----
+ 1 file changed, 26 insertions(+), 7 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+@@ -8,6 +8,7 @@
+ /dts-v1/;
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include "rk3326.dtsi"
+ 
+@@ -113,15 +114,29 @@
+ 		};
+ 	};
+ 
+-	leds: gpio-leds {
++	/* led-1 is wired directly to output of always-on regulator */
++
++	gpio_led: gpio-leds {
+ 		compatible = "gpio-leds";
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&blue_led_pin>;
++		pinctrl-0 = <&red_led_pin>;
++
++		red_led: led-3 {
++			color = <LED_COLOR_ID_RED>;
++			gpios = <&gpio0 RK_PB5 GPIO_ACTIVE_HIGH>;
++			function = LED_FUNCTION_CHARGING;
++		};
++	};
+ 
+-		blue_led: led-0 {
+-			label = "blue:heartbeat";
+-			gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
++	pwm_led: led-controller {
++		compatible = "pwm-leds";
++
++		blue_led: led-2 {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
+ 			linux,default-trigger = "heartbeat";
++			max-brightness = <255>;
++			pwms = <&pwm3 0 25000 0>;
+ 		};
+ 	};
+ 
+@@ -465,6 +480,10 @@
+ 	status = "okay";
+ };
+ 
++&pwm3 {
++	status = "okay";
++};
++
+ &saradc {
+ 	vref-supply = <&vcc_1v8>;
+ 	status = "okay";
+@@ -569,8 +588,8 @@
+ 	};
+ 
+ 	leds {
+-		blue_led_pin: blue-led-pin {
+-			rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		red_led_pin: red-led-pin {
++			rockchip,pins = <0 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/096-arm64-dts-rockchip-increase-spi-max-frequency-of-nor.patch b/target/linux/rockchip/patches-6.1/096-arm64-dts-rockchip-increase-spi-max-frequency-of-nor.patch
new file mode 100644
index 00000000000..590de2d50aa
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/096-arm64-dts-rockchip-increase-spi-max-frequency-of-nor.patch
@@ -0,0 +1,29 @@
+From 7ac9682ef12c0e09fdc2b3ec96263714d727996e Mon Sep 17 00:00:00 2001
+From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Date: Thu, 24 Nov 2022 12:57:14 +0530
+Subject: [PATCH 096/383] arm64: dts: rockchip: increase spi-max-frequency of
+ nor flash for roc-rk3399-pc
+
+Increase the spi-max-frequency of nor flash from 10Mhz to 30Mhz,this improves the
+flash raw write speed by 0.9 MB/s to 1.6MB/s and the time taken to write is
+get reduced from 36 seconds to 20 seconds.
+
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20221124072714.450223-1-abbaraju.manojsai@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-roc-pc.dtsi
+@@ -735,7 +735,7 @@
+ 	flash@0 {
+ 		compatible = "jedec,spi-nor";
+ 		reg = <0>;
+-		spi-max-frequency = <10000000>;
++		spi-max-frequency = <30000000>;
+ 	};
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/097-arm64-dts-rockchip-Add-rk3588-pinctrl-data.patch b/target/linux/rockchip/patches-6.1/097-arm64-dts-rockchip-Add-rk3588-pinctrl-data.patch
new file mode 100644
index 00000000000..38e4b7646b2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/097-arm64-dts-rockchip-Add-rk3588-pinctrl-data.patch
@@ -0,0 +1,3958 @@
+From fda50f49149e179885f0bfe32357c8b6d1558415 Mon Sep 17 00:00:00 2001
+From: Jianqun Xu <jay.xu@rock-chips.com>
+Date: Mon, 9 Jan 2023 16:57:56 +0100
+Subject: [PATCH 097/383] arm64: dts: rockchip: Add rk3588 pinctrl data
+
+This adds the pin controller data for rk3588 and rk3588s.
+
+Co-Developed-by: Shengfei Xu <xsf@rock-chips.com>
+Signed-off-by: Shengfei Xu <xsf@rock-chips.com>
+Co-Developed-by: Damon Ding <damon.ding@rock-chips.com>
+Signed-off-by: Damon Ding <damon.ding@rock-chips.com>
+Co-Developed-by: Steven Liu <steven.liu@rock-chips.com>
+Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
+Co-Developed-by: Jon Lin <jon.lin@rock-chips.com>
+Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
+Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
+[port from vendor tree merging all fixes]
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Jagan Teki <jagan@edgeble.ai>
+Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-neu6a
+Link: https://lore.kernel.org/r/20230109155801.51642-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-pinctrl.dtsi     |  516 +++
+ .../boot/dts/rockchip/rk3588s-pinctrl.dtsi    | 3403 +++++++++++++++++
+ 2 files changed, 3919 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-pinctrl.dtsi
+@@ -0,0 +1,516 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rockchip-pinconf.dtsi"
++
++/*
++ * This file is auto generated by pin2dts tool, please keep these code
++ * by adding changes at end of this file.
++ */
++&pinctrl {
++	clk32k {
++		/omit-if-no-ref/
++		clk32k_out1: clk32k-out1 {
++			rockchip,pins =
++				/* clk32k_out1 */
++				<2 RK_PC5 1 &pcfg_pull_none>;
++		};
++
++	};
++
++	eth0 {
++		/omit-if-no-ref/
++		eth0_pins: eth0-pins {
++			rockchip,pins =
++				/* eth0_refclko_25m */
++				<2 RK_PC3 1 &pcfg_pull_none>;
++		};
++
++	};
++
++	fspi {
++		/omit-if-no-ref/
++		fspim1_pins: fspim1-pins {
++			rockchip,pins =
++				/* fspi_clk_m1 */
++				<2 RK_PB3 3 &pcfg_pull_up_drv_level_2>,
++				/* fspi_cs0n_m1 */
++				<2 RK_PB4 3 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d0_m1 */
++				<2 RK_PA6 3 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d1_m1 */
++				<2 RK_PA7 3 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d2_m1 */
++				<2 RK_PB0 3 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d3_m1 */
++				<2 RK_PB1 3 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		fspim1_cs1: fspim1-cs1 {
++			rockchip,pins =
++				/* fspi_cs1n_m1 */
++				<2 RK_PB5 3 &pcfg_pull_up_drv_level_2>;
++		};
++	};
++
++	gmac0 {
++		/omit-if-no-ref/
++		gmac0_miim: gmac0-miim {
++			rockchip,pins =
++				/* gmac0_mdc */
++				<4 RK_PC4 1 &pcfg_pull_none>,
++				/* gmac0_mdio */
++				<4 RK_PC5 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_clkinout: gmac0-clkinout {
++			rockchip,pins =
++				/* gmac0_mclkinout */
++				<4 RK_PC3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_rx_bus2: gmac0-rx-bus2 {
++			rockchip,pins =
++				/* gmac0_rxd0 */
++				<2 RK_PC1 1 &pcfg_pull_none>,
++				/* gmac0_rxd1 */
++				<2 RK_PC2 1 &pcfg_pull_none>,
++				/* gmac0_rxdv_crs */
++				<4 RK_PC2 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_tx_bus2: gmac0-tx-bus2 {
++			rockchip,pins =
++				/* gmac0_txd0 */
++				<2 RK_PB6 1 &pcfg_pull_none>,
++				/* gmac0_txd1 */
++				<2 RK_PB7 1 &pcfg_pull_none>,
++				/* gmac0_txen */
++				<2 RK_PC0 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_rgmii_clk: gmac0-rgmii-clk {
++			rockchip,pins =
++				/* gmac0_rxclk */
++				<2 RK_PB0 1 &pcfg_pull_none>,
++				/* gmac0_txclk */
++				<2 RK_PB3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_rgmii_bus: gmac0-rgmii-bus {
++			rockchip,pins =
++				/* gmac0_rxd2 */
++				<2 RK_PA6 1 &pcfg_pull_none>,
++				/* gmac0_rxd3 */
++				<2 RK_PA7 1 &pcfg_pull_none>,
++				/* gmac0_txd2 */
++				<2 RK_PB1 1 &pcfg_pull_none>,
++				/* gmac0_txd3 */
++				<2 RK_PB2 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_ppsclk: gmac0-ppsclk {
++			rockchip,pins =
++				/* gmac0_ppsclk */
++				<2 RK_PC4 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_ppstring: gmac0-ppstring {
++			rockchip,pins =
++				/* gmac0_ppstring */
++				<2 RK_PB5 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_ptp_refclk: gmac0-ptp-refclk {
++			rockchip,pins =
++				/* gmac0_ptp_refclk */
++				<2 RK_PB4 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac0_txer: gmac0-txer {
++			rockchip,pins =
++				/* gmac0_txer */
++				<4 RK_PC6 1 &pcfg_pull_none>;
++		};
++
++	};
++
++	hdmi {
++		/omit-if-no-ref/
++		hdmim0_tx1_cec: hdmim0-tx1-cec {
++			rockchip,pins =
++				/* hdmim0_tx1_cec */
++				<2 RK_PC4 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx1_scl: hdmim0-tx1-scl {
++			rockchip,pins =
++				/* hdmim0_tx1_scl */
++				<2 RK_PB5 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx1_sda: hdmim0-tx1-sda {
++			rockchip,pins =
++				/* hdmim0_tx1_sda */
++				<2 RK_PB4 4 &pcfg_pull_none>;
++		};
++	};
++
++	i2c0 {
++		/omit-if-no-ref/
++		i2c0m1_xfer: i2c0m1-xfer {
++			rockchip,pins =
++				/* i2c0_scl_m1 */
++				<4 RK_PC5 9 &pcfg_pull_none_smt>,
++				/* i2c0_sda_m1 */
++				<4 RK_PC6 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c2 {
++		/omit-if-no-ref/
++		i2c2m1_xfer: i2c2m1-xfer {
++			rockchip,pins =
++				/* i2c2_scl_m1 */
++				<2 RK_PC1 9 &pcfg_pull_none_smt>,
++				/* i2c2_sda_m1 */
++				<2 RK_PC0 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c3 {
++		/omit-if-no-ref/
++		i2c3m3_xfer: i2c3m3-xfer {
++			rockchip,pins =
++				/* i2c3_scl_m3 */
++				<2 RK_PB2 9 &pcfg_pull_none_smt>,
++				/* i2c3_sda_m3 */
++				<2 RK_PB3 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c4 {
++		/omit-if-no-ref/
++		i2c4m1_xfer: i2c4m1-xfer {
++			rockchip,pins =
++				/* i2c4_scl_m1 */
++				<2 RK_PB5 9 &pcfg_pull_none_smt>,
++				/* i2c4_sda_m1 */
++				<2 RK_PB4 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c5 {
++		/omit-if-no-ref/
++		i2c5m4_xfer: i2c5m4-xfer {
++			rockchip,pins =
++				/* i2c5_scl_m4 */
++				<2 RK_PB6 9 &pcfg_pull_none_smt>,
++				/* i2c5_sda_m4 */
++				<2 RK_PB7 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c6 {
++		/omit-if-no-ref/
++		i2c6m2_xfer: i2c6m2-xfer {
++			rockchip,pins =
++				/* i2c6_scl_m2 */
++				<2 RK_PC3 9 &pcfg_pull_none_smt>,
++				/* i2c6_sda_m2 */
++				<2 RK_PC2 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c7 {
++		/omit-if-no-ref/
++		i2c7m1_xfer: i2c7m1-xfer {
++			rockchip,pins =
++				/* i2c7_scl_m1 */
++				<4 RK_PC3 9 &pcfg_pull_none_smt>,
++				/* i2c7_sda_m1 */
++				<4 RK_PC4 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c8 {
++		/omit-if-no-ref/
++		i2c8m1_xfer: i2c8m1-xfer {
++			rockchip,pins =
++				/* i2c8_scl_m1 */
++				<2 RK_PB0 9 &pcfg_pull_none_smt>,
++				/* i2c8_sda_m1 */
++				<2 RK_PB1 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2s2 {
++		/omit-if-no-ref/
++		i2s2m0_lrck: i2s2m0-lrck {
++			rockchip,pins =
++				/* i2s2m0_lrck */
++				<2 RK_PC0 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_mclk: i2s2m0-mclk {
++			rockchip,pins =
++				/* i2s2m0_mclk */
++				<2 RK_PB6 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_sclk: i2s2m0-sclk {
++			rockchip,pins =
++				/* i2s2m0_sclk */
++				<2 RK_PB7 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_sdi: i2s2m0-sdi {
++			rockchip,pins =
++				/* i2s2m0_sdi */
++				<2 RK_PC3 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_sdo: i2s2m0-sdo {
++			rockchip,pins =
++				/* i2s2m0_sdo */
++				<4 RK_PC3 2 &pcfg_pull_none>;
++		};
++	};
++
++	pwm2 {
++		/omit-if-no-ref/
++		pwm2m2_pins: pwm2m2-pins {
++			rockchip,pins =
++				/* pwm2_m2 */
++				<4 RK_PC2 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm4 {
++		/omit-if-no-ref/
++		pwm4m1_pins: pwm4m1-pins {
++			rockchip,pins =
++				/* pwm4_m1 */
++				<4 RK_PC3 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm5 {
++		/omit-if-no-ref/
++		pwm5m2_pins: pwm5m2-pins {
++			rockchip,pins =
++				/* pwm5_m2 */
++				<4 RK_PC4 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm6 {
++		/omit-if-no-ref/
++		pwm6m2_pins: pwm6m2-pins {
++			rockchip,pins =
++				/* pwm6_m2 */
++				<4 RK_PC5 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm7 {
++		/omit-if-no-ref/
++		pwm7m3_pins: pwm7m3-pins {
++			rockchip,pins =
++				/* pwm7_ir_m3 */
++				<4 RK_PC6 11 &pcfg_pull_none>;
++		};
++	};
++
++	sdio {
++		/omit-if-no-ref/
++		sdiom0_pins: sdiom0-pins {
++			rockchip,pins =
++				/* sdio_clk_m0 */
++				<2 RK_PB3 2 &pcfg_pull_none>,
++				/* sdio_cmd_m0 */
++				<2 RK_PB2 2 &pcfg_pull_none>,
++				/* sdio_d0_m0 */
++				<2 RK_PA6 2 &pcfg_pull_none>,
++				/* sdio_d1_m0 */
++				<2 RK_PA7 2 &pcfg_pull_none>,
++				/* sdio_d2_m0 */
++				<2 RK_PB0 2 &pcfg_pull_none>,
++				/* sdio_d3_m0 */
++				<2 RK_PB1 2 &pcfg_pull_none>;
++		};
++	};
++
++	spi1 {
++		/omit-if-no-ref/
++		spi1m0_pins: spi1m0-pins {
++			rockchip,pins =
++				/* spi1_clk_m0 */
++				<2 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi1_miso_m0 */
++				<2 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
++				/* spi1_mosi_m0 */
++				<2 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m0_cs0: spi1m0-cs0 {
++			rockchip,pins =
++				/* spi1_cs0_m0 */
++				<2 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m0_cs1: spi1m0-cs1 {
++			rockchip,pins =
++				/* spi1_cs1_m0 */
++				<2 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	spi3 {
++		/omit-if-no-ref/
++		spi3m0_pins: spi3m0-pins {
++			rockchip,pins =
++				/* spi3_clk_m0 */
++				<4 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_miso_m0 */
++				<4 RK_PC4 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_mosi_m0 */
++				<4 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m0_cs0: spi3m0-cs0 {
++			rockchip,pins =
++				/* spi3_cs0_m0 */
++				<4 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m0_cs1: spi3m0-cs1 {
++			rockchip,pins =
++				/* spi3_cs1_m0 */
++				<4 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	uart1 {
++		/omit-if-no-ref/
++		uart1m0_xfer: uart1m0-xfer {
++			rockchip,pins =
++				/* uart1_rx_m0 */
++				<2 RK_PB6 10 &pcfg_pull_up>,
++				/* uart1_tx_m0 */
++				<2 RK_PB7 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart1m0_ctsn: uart1m0-ctsn {
++			rockchip,pins =
++				/* uart1m0_ctsn */
++				<2 RK_PC1 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart1m0_rtsn: uart1m0-rtsn {
++			rockchip,pins =
++				/* uart1m0_rtsn */
++				<2 RK_PC0 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart6 {
++		/omit-if-no-ref/
++		uart6m0_xfer: uart6m0-xfer {
++			rockchip,pins =
++				/* uart6_rx_m0 */
++				<2 RK_PA6 10 &pcfg_pull_up>,
++				/* uart6_tx_m0 */
++				<2 RK_PA7 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart6m0_ctsn: uart6m0-ctsn {
++			rockchip,pins =
++				/* uart6m0_ctsn */
++				<2 RK_PB1 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart6m0_rtsn: uart6m0-rtsn {
++			rockchip,pins =
++				/* uart6m0_rtsn */
++				<2 RK_PB0 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart7 {
++		/omit-if-no-ref/
++		uart7m0_xfer: uart7m0-xfer {
++			rockchip,pins =
++				/* uart7_rx_m0 */
++				<2 RK_PB4 10 &pcfg_pull_up>,
++				/* uart7_tx_m0 */
++				<2 RK_PB5 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart7m0_ctsn: uart7m0-ctsn {
++			rockchip,pins =
++				/* uart7m0_ctsn */
++				<4 RK_PC6 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart7m0_rtsn: uart7m0-rtsn {
++			rockchip,pins =
++				/* uart7m0_rtsn */
++				<4 RK_PC2 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart9 {
++		/omit-if-no-ref/
++		uart9m0_xfer: uart9m0-xfer {
++			rockchip,pins =
++				/* uart9_rx_m0 */
++				<2 RK_PC4 10 &pcfg_pull_up>,
++				/* uart9_tx_m0 */
++				<2 RK_PC2 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart9m0_ctsn: uart9m0-ctsn {
++			rockchip,pins =
++				/* uart9m0_ctsn */
++				<4 RK_PC5 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart9m0_rtsn: uart9m0-rtsn {
++			rockchip,pins =
++				/* uart9m0_rtsn */
++				<4 RK_PC4 10 &pcfg_pull_none>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
+@@ -0,0 +1,3403 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rockchip-pinconf.dtsi"
++
++/*
++ * This file is auto generated by pin2dts tool, please keep these code
++ * by adding changes at end of this file.
++ */
++&pinctrl {
++	auddsm {
++		/omit-if-no-ref/
++		auddsm_pins: auddsm-pins {
++			rockchip,pins =
++				/* auddsm_ln */
++				<3 RK_PA1 4 &pcfg_pull_none>,
++				/* auddsm_lp */
++				<3 RK_PA2 4 &pcfg_pull_none>,
++				/* auddsm_rn */
++				<3 RK_PA3 4 &pcfg_pull_none>,
++				/* auddsm_rp */
++				<3 RK_PA4 4 &pcfg_pull_none>;
++		};
++	};
++
++	bt1120 {
++		/omit-if-no-ref/
++		bt1120_pins: bt1120-pins {
++			rockchip,pins =
++				/* bt1120_clkout */
++				<4 RK_PB0 2 &pcfg_pull_none>,
++				/* bt1120_d0 */
++				<4 RK_PA0 2 &pcfg_pull_none>,
++				/* bt1120_d1 */
++				<4 RK_PA1 2 &pcfg_pull_none>,
++				/* bt1120_d2 */
++				<4 RK_PA2 2 &pcfg_pull_none>,
++				/* bt1120_d3 */
++				<4 RK_PA3 2 &pcfg_pull_none>,
++				/* bt1120_d4 */
++				<4 RK_PA4 2 &pcfg_pull_none>,
++				/* bt1120_d5 */
++				<4 RK_PA5 2 &pcfg_pull_none>,
++				/* bt1120_d6 */
++				<4 RK_PA6 2 &pcfg_pull_none>,
++				/* bt1120_d7 */
++				<4 RK_PA7 2 &pcfg_pull_none>,
++				/* bt1120_d8 */
++				<4 RK_PB2 2 &pcfg_pull_none>,
++				/* bt1120_d9 */
++				<4 RK_PB3 2 &pcfg_pull_none>,
++				/* bt1120_d10 */
++				<4 RK_PB4 2 &pcfg_pull_none>,
++				/* bt1120_d11 */
++				<4 RK_PB5 2 &pcfg_pull_none>,
++				/* bt1120_d12 */
++				<4 RK_PB6 2 &pcfg_pull_none>,
++				/* bt1120_d13 */
++				<4 RK_PB7 2 &pcfg_pull_none>,
++				/* bt1120_d14 */
++				<4 RK_PC0 2 &pcfg_pull_none>,
++				/* bt1120_d15 */
++				<4 RK_PC1 2 &pcfg_pull_none>;
++		};
++	};
++
++	can0 {
++		/omit-if-no-ref/
++		can0m0_pins: can0m0-pins {
++			rockchip,pins =
++				/* can0_rx_m0 */
++				<0 RK_PC0 11 &pcfg_pull_none>,
++				/* can0_tx_m0 */
++				<0 RK_PB7 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		can0m1_pins: can0m1-pins {
++			rockchip,pins =
++				/* can0_rx_m1 */
++				<4 RK_PD5 9 &pcfg_pull_none>,
++				/* can0_tx_m1 */
++				<4 RK_PD4 9 &pcfg_pull_none>;
++		};
++	};
++
++	can1 {
++		/omit-if-no-ref/
++		can1m0_pins: can1m0-pins {
++			rockchip,pins =
++				/* can1_rx_m0 */
++				<3 RK_PB5 9 &pcfg_pull_none>,
++				/* can1_tx_m0 */
++				<3 RK_PB6 9 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		can1m1_pins: can1m1-pins {
++			rockchip,pins =
++				/* can1_rx_m1 */
++				<4 RK_PB2 12 &pcfg_pull_none>,
++				/* can1_tx_m1 */
++				<4 RK_PB3 12 &pcfg_pull_none>;
++		};
++	};
++
++	can2 {
++		/omit-if-no-ref/
++		can2m0_pins: can2m0-pins {
++			rockchip,pins =
++				/* can2_rx_m0 */
++				<3 RK_PC4 9 &pcfg_pull_none>,
++				/* can2_tx_m0 */
++				<3 RK_PC5 9 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		can2m1_pins: can2m1-pins {
++			rockchip,pins =
++				/* can2_rx_m1 */
++				<0 RK_PD4 10 &pcfg_pull_none>,
++				/* can2_tx_m1 */
++				<0 RK_PD5 10 &pcfg_pull_none>;
++		};
++	};
++
++	cif {
++		/omit-if-no-ref/
++		cif_clk: cif-clk {
++			rockchip,pins =
++				/* cif_clkout */
++				<4 RK_PB4 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		cif_dvp_clk: cif-dvp-clk {
++			rockchip,pins =
++				/* cif_clkin */
++				<4 RK_PB0 1 &pcfg_pull_none>,
++				/* cif_href */
++				<4 RK_PB2 1 &pcfg_pull_none>,
++				/* cif_vsync */
++				<4 RK_PB3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		cif_dvp_bus16: cif-dvp-bus16 {
++			rockchip,pins =
++				/* cif_d8 */
++				<3 RK_PC4 1 &pcfg_pull_none>,
++				/* cif_d9 */
++				<3 RK_PC5 1 &pcfg_pull_none>,
++				/* cif_d10 */
++				<3 RK_PC6 1 &pcfg_pull_none>,
++				/* cif_d11 */
++				<3 RK_PC7 1 &pcfg_pull_none>,
++				/* cif_d12 */
++				<3 RK_PD0 1 &pcfg_pull_none>,
++				/* cif_d13 */
++				<3 RK_PD1 1 &pcfg_pull_none>,
++				/* cif_d14 */
++				<3 RK_PD2 1 &pcfg_pull_none>,
++				/* cif_d15 */
++				<3 RK_PD3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		cif_dvp_bus8: cif-dvp-bus8 {
++			rockchip,pins =
++				/* cif_d0 */
++				<4 RK_PA0 1 &pcfg_pull_none>,
++				/* cif_d1 */
++				<4 RK_PA1 1 &pcfg_pull_none>,
++				/* cif_d2 */
++				<4 RK_PA2 1 &pcfg_pull_none>,
++				/* cif_d3 */
++				<4 RK_PA3 1 &pcfg_pull_none>,
++				/* cif_d4 */
++				<4 RK_PA4 1 &pcfg_pull_none>,
++				/* cif_d5 */
++				<4 RK_PA5 1 &pcfg_pull_none>,
++				/* cif_d6 */
++				<4 RK_PA6 1 &pcfg_pull_none>,
++				/* cif_d7 */
++				<4 RK_PA7 1 &pcfg_pull_none>;
++		};
++	};
++
++	clk32k {
++		/omit-if-no-ref/
++		clk32k_in: clk32k-in {
++			rockchip,pins =
++				/* clk32k_in */
++				<0 RK_PB2 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		clk32k_out0: clk32k-out0 {
++			rockchip,pins =
++				/* clk32k_out0 */
++				<0 RK_PB2 2 &pcfg_pull_none>;
++		};
++	};
++
++	cpu {
++		/omit-if-no-ref/
++		cpu_pins: cpu-pins {
++			rockchip,pins =
++				/* cpu_big0_avs */
++				<0 RK_PD1 2 &pcfg_pull_none>,
++				/* cpu_big1_avs */
++				<0 RK_PD5 2 &pcfg_pull_none>;
++		};
++	};
++
++	ddrphych0 {
++		/omit-if-no-ref/
++		ddrphych0_pins: ddrphych0-pins {
++			rockchip,pins =
++				/* ddrphych0_dtb0 */
++				<4 RK_PA0 7 &pcfg_pull_none>,
++				/* ddrphych0_dtb1 */
++				<4 RK_PA1 7 &pcfg_pull_none>,
++				/* ddrphych0_dtb2 */
++				<4 RK_PA2 7 &pcfg_pull_none>,
++				/* ddrphych0_dtb3 */
++				<4 RK_PA3 7 &pcfg_pull_none>;
++		};
++	};
++
++	ddrphych1 {
++		/omit-if-no-ref/
++		ddrphych1_pins: ddrphych1-pins {
++			rockchip,pins =
++				/* ddrphych1_dtb0 */
++				<4 RK_PA4 7 &pcfg_pull_none>,
++				/* ddrphych1_dtb1 */
++				<4 RK_PA5 7 &pcfg_pull_none>,
++				/* ddrphych1_dtb2 */
++				<4 RK_PA6 7 &pcfg_pull_none>,
++				/* ddrphych1_dtb3 */
++				<4 RK_PA7 7 &pcfg_pull_none>;
++		};
++	};
++
++	ddrphych2 {
++		/omit-if-no-ref/
++		ddrphych2_pins: ddrphych2-pins {
++			rockchip,pins =
++				/* ddrphych2_dtb0 */
++				<4 RK_PB0 7 &pcfg_pull_none>,
++				/* ddrphych2_dtb1 */
++				<4 RK_PB1 7 &pcfg_pull_none>,
++				/* ddrphych2_dtb2 */
++				<4 RK_PB2 7 &pcfg_pull_none>,
++				/* ddrphych2_dtb3 */
++				<4 RK_PB3 7 &pcfg_pull_none>;
++		};
++	};
++
++	ddrphych3 {
++		/omit-if-no-ref/
++		ddrphych3_pins: ddrphych3-pins {
++			rockchip,pins =
++				/* ddrphych3_dtb0 */
++				<4 RK_PB4 7 &pcfg_pull_none>,
++				/* ddrphych3_dtb1 */
++				<4 RK_PB5 7 &pcfg_pull_none>,
++				/* ddrphych3_dtb2 */
++				<4 RK_PB6 7 &pcfg_pull_none>,
++				/* ddrphych3_dtb3 */
++				<4 RK_PB7 7 &pcfg_pull_none>;
++		};
++	};
++
++	dp0 {
++		/omit-if-no-ref/
++		dp0m0_pins: dp0m0-pins {
++			rockchip,pins =
++				/* dp0_hpdin_m0 */
++				<4 RK_PB4 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		dp0m1_pins: dp0m1-pins {
++			rockchip,pins =
++				/* dp0_hpdin_m1 */
++				<0 RK_PC4 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		dp0m2_pins: dp0m2-pins {
++			rockchip,pins =
++				/* dp0_hpdin_m2 */
++				<1 RK_PA0 5 &pcfg_pull_none>;
++		};
++	};
++
++	dp1 {
++		/omit-if-no-ref/
++		dp1m0_pins: dp1m0-pins {
++			rockchip,pins =
++				/* dp1_hpdin_m0 */
++				<3 RK_PD5 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		dp1m1_pins: dp1m1-pins {
++			rockchip,pins =
++				/* dp1_hpdin_m1 */
++				<0 RK_PC5 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		dp1m2_pins: dp1m2-pins {
++			rockchip,pins =
++				/* dp1_hpdin_m2 */
++				<1 RK_PA1 5 &pcfg_pull_none>;
++		};
++	};
++
++	emmc {
++		/omit-if-no-ref/
++		emmc_rstnout: emmc-rstnout {
++			rockchip,pins =
++				/* emmc_rstn */
++				<2 RK_PA3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		emmc_bus8: emmc-bus8 {
++			rockchip,pins =
++				/* emmc_d0 */
++				<2 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d1 */
++				<2 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d2 */
++				<2 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d3 */
++				<2 RK_PD3 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d4 */
++				<2 RK_PD4 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d5 */
++				<2 RK_PD5 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d6 */
++				<2 RK_PD6 1 &pcfg_pull_up_drv_level_2>,
++				/* emmc_d7 */
++				<2 RK_PD7 1 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		emmc_clk: emmc-clk {
++			rockchip,pins =
++				/* emmc_clkout */
++				<2 RK_PA1 1 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		emmc_cmd: emmc-cmd {
++			rockchip,pins =
++				/* emmc_cmd */
++				<2 RK_PA0 1 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		emmc_data_strobe: emmc-data-strobe {
++			rockchip,pins =
++				/* emmc_data_strobe */
++				<2 RK_PA2 1 &pcfg_pull_none>;
++		};
++	};
++
++	eth1 {
++		/omit-if-no-ref/
++		eth1_pins: eth1-pins {
++			rockchip,pins =
++				/* eth1_refclko_25m */
++				<3 RK_PA6 1 &pcfg_pull_none>;
++		};
++	};
++
++	fspi {
++		/omit-if-no-ref/
++		fspim0_pins: fspim0-pins {
++			rockchip,pins =
++				/* fspi_clk_m0 */
++				<2 RK_PA0 2 &pcfg_pull_up_drv_level_2>,
++				/* fspi_cs0n_m0 */
++				<2 RK_PD6 2 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d0_m0 */
++				<2 RK_PD0 2 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d1_m0 */
++				<2 RK_PD1 2 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d2_m0 */
++				<2 RK_PD2 2 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d3_m0 */
++				<2 RK_PD3 2 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		fspim0_cs1: fspim0-cs1 {
++			rockchip,pins =
++				/* fspi_cs1n_m0 */
++				<2 RK_PD7 2 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		fspim2_pins: fspim2-pins {
++			rockchip,pins =
++				/* fspi_clk_m2 */
++				<3 RK_PA5 5 &pcfg_pull_up_drv_level_2>,
++				/* fspi_cs0n_m2 */
++				<3 RK_PC4 2 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d0_m2 */
++				<3 RK_PA0 5 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d1_m2 */
++				<3 RK_PA1 5 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d2_m2 */
++				<3 RK_PA2 5 &pcfg_pull_up_drv_level_2>,
++				/* fspi_d3_m2 */
++				<3 RK_PA3 5 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		fspim2_cs1: fspim2-cs1 {
++			rockchip,pins =
++				/* fspi_cs1n_m2 */
++				<3 RK_PC5 2 &pcfg_pull_up_drv_level_2>;
++		};
++	};
++
++	gmac1 {
++		/omit-if-no-ref/
++		gmac1_miim: gmac1-miim {
++			rockchip,pins =
++				/* gmac1_mdc */
++				<3 RK_PC2 1 &pcfg_pull_none>,
++				/* gmac1_mdio */
++				<3 RK_PC3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_clkinout: gmac1-clkinout {
++			rockchip,pins =
++				/* gmac1_mclkinout */
++				<3 RK_PB6 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_rx_bus2: gmac1-rx-bus2 {
++			rockchip,pins =
++				/* gmac1_rxd0 */
++				<3 RK_PA7 1 &pcfg_pull_none>,
++				/* gmac1_rxd1 */
++				<3 RK_PB0 1 &pcfg_pull_none>,
++				/* gmac1_rxdv_crs */
++				<3 RK_PB1 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_tx_bus2: gmac1-tx-bus2 {
++			rockchip,pins =
++				/* gmac1_txd0 */
++				<3 RK_PB3 1 &pcfg_pull_none>,
++				/* gmac1_txd1 */
++				<3 RK_PB4 1 &pcfg_pull_none>,
++				/* gmac1_txen */
++				<3 RK_PB5 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_rgmii_clk: gmac1-rgmii-clk {
++			rockchip,pins =
++				/* gmac1_rxclk */
++				<3 RK_PA5 1 &pcfg_pull_none>,
++				/* gmac1_txclk */
++				<3 RK_PA4 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_rgmii_bus: gmac1-rgmii-bus {
++			rockchip,pins =
++				/* gmac1_rxd2 */
++				<3 RK_PA2 1 &pcfg_pull_none>,
++				/* gmac1_rxd3 */
++				<3 RK_PA3 1 &pcfg_pull_none>,
++				/* gmac1_txd2 */
++				<3 RK_PA0 1 &pcfg_pull_none>,
++				/* gmac1_txd3 */
++				<3 RK_PA1 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_ppsclk: gmac1-ppsclk {
++			rockchip,pins =
++				/* gmac1_ppsclk */
++				<3 RK_PC1 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_ppstrig: gmac1-ppstrig {
++			rockchip,pins =
++				/* gmac1_ppstrig */
++				<3 RK_PC0 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_ptp_ref_clk: gmac1-ptp-ref-clk {
++			rockchip,pins =
++				/* gmac1_ptp_ref_clk */
++				<3 RK_PB7 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		gmac1_txer: gmac1-txer {
++			rockchip,pins =
++				/* gmac1_txer */
++				<3 RK_PB2 1 &pcfg_pull_none>;
++		};
++	};
++
++	gpu {
++		/omit-if-no-ref/
++		gpu_pins: gpu-pins {
++			rockchip,pins =
++				/* gpu_avs */
++				<0 RK_PC5 2 &pcfg_pull_none>;
++		};
++	};
++
++	hdmi {
++		/omit-if-no-ref/
++		hdmim0_rx_cec: hdmim0-rx-cec {
++			rockchip,pins =
++				/* hdmim0_rx_cec */
++				<4 RK_PB5 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_rx_hpdin: hdmim0-rx-hpdin {
++			rockchip,pins =
++				/* hdmim0_rx_hpdin */
++				<4 RK_PB6 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_rx_scl: hdmim0-rx-scl {
++			rockchip,pins =
++				/* hdmim0_rx_scl */
++				<0 RK_PD2 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_rx_sda: hdmim0-rx-sda {
++			rockchip,pins =
++				/* hdmim0_rx_sda */
++				<0 RK_PD1 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx0_cec: hdmim0-tx0-cec {
++			rockchip,pins =
++				/* hdmim0_tx0_cec */
++				<4 RK_PC1 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx0_hpd: hdmim0-tx0-hpd {
++			rockchip,pins =
++				/* hdmim0_tx0_hpd */
++				<1 RK_PA5 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx0_scl: hdmim0-tx0-scl {
++			rockchip,pins =
++				/* hdmim0_tx0_scl */
++				<4 RK_PB7 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx0_sda: hdmim0-tx0-sda {
++			rockchip,pins =
++				/* hdmim0_tx0_sda */
++				<4 RK_PC0 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim0_tx1_hpd: hdmim0-tx1-hpd {
++			rockchip,pins =
++				/* hdmim0_tx1_hpd */
++				<1 RK_PA6 5 &pcfg_pull_none>;
++		};
++		/omit-if-no-ref/
++		hdmim1_rx_cec: hdmim1-rx-cec {
++			rockchip,pins =
++				/* hdmim1_rx_cec */
++				<3 RK_PD1 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_hpdin: hdmim1-rx-hpdin {
++			rockchip,pins =
++				/* hdmim1_rx_hpdin */
++				<3 RK_PD4 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_scl: hdmim1-rx-scl {
++			rockchip,pins =
++				/* hdmim1_rx_scl */
++				<3 RK_PD2 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_rx_sda: hdmim1-rx-sda {
++			rockchip,pins =
++				/* hdmim1_rx_sda */
++				<3 RK_PD3 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx0_cec: hdmim1-tx0-cec {
++			rockchip,pins =
++				/* hdmim1_tx0_cec */
++				<0 RK_PD1 13 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx0_hpd: hdmim1-tx0-hpd {
++			rockchip,pins =
++				/* hdmim1_tx0_hpd */
++				<3 RK_PD4 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx0_scl: hdmim1-tx0-scl {
++			rockchip,pins =
++				/* hdmim1_tx0_scl */
++				<0 RK_PD5 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx0_sda: hdmim1-tx0-sda {
++			rockchip,pins =
++				/* hdmim1_tx0_sda */
++				<0 RK_PD4 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx1_cec: hdmim1-tx1-cec {
++			rockchip,pins =
++				/* hdmim1_tx1_cec */
++				<0 RK_PD2 13 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx1_hpd: hdmim1-tx1-hpd {
++			rockchip,pins =
++				/* hdmim1_tx1_hpd */
++				<3 RK_PB7 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx1_scl: hdmim1-tx1-scl {
++			rockchip,pins =
++				/* hdmim1_tx1_scl */
++				<3 RK_PC6 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim1_tx1_sda: hdmim1-tx1-sda {
++			rockchip,pins =
++				/* hdmim1_tx1_sda */
++				<3 RK_PC5 5 &pcfg_pull_none>;
++		};
++		/omit-if-no-ref/
++		hdmim2_rx_cec: hdmim2-rx-cec {
++			rockchip,pins =
++				/* hdmim2_rx_cec */
++				<1 RK_PB7 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_rx_hpdin: hdmim2-rx-hpdin {
++			rockchip,pins =
++				/* hdmim2_rx_hpdin */
++				<1 RK_PB6 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_rx_scl: hdmim2-rx-scl {
++			rockchip,pins =
++				/* hdmim2_rx_scl */
++				<1 RK_PD6 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_rx_sda: hdmim2-rx-sda {
++			rockchip,pins =
++				/* hdmim2_rx_sda */
++				<1 RK_PD7 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_tx0_scl: hdmim2-tx0-scl {
++			rockchip,pins =
++				/* hdmim2_tx0_scl */
++				<3 RK_PC7 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_tx0_sda: hdmim2-tx0-sda {
++			rockchip,pins =
++				/* hdmim2_tx0_sda */
++				<3 RK_PD0 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_tx1_cec: hdmim2-tx1-cec {
++			rockchip,pins =
++				/* hdmim2_tx1_cec */
++				<3 RK_PC4 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_tx1_scl: hdmim2-tx1-scl {
++			rockchip,pins =
++				/* hdmim2_tx1_scl */
++				<1 RK_PA4 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmim2_tx1_sda: hdmim2-tx1-sda {
++			rockchip,pins =
++				/* hdmim2_tx1_sda */
++				<1 RK_PA3 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug0: hdmi-debug0 {
++			rockchip,pins =
++				/* hdmi_debug0 */
++				<1 RK_PA7 7 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug1: hdmi-debug1 {
++			rockchip,pins =
++				/* hdmi_debug1 */
++				<1 RK_PB0 7 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug2: hdmi-debug2 {
++			rockchip,pins =
++				/* hdmi_debug2 */
++				<1 RK_PB1 7 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug3: hdmi-debug3 {
++			rockchip,pins =
++				/* hdmi_debug3 */
++				<1 RK_PB2 7 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug4: hdmi-debug4 {
++			rockchip,pins =
++				/* hdmi_debug4 */
++				<1 RK_PB3 7 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug5: hdmi-debug5 {
++			rockchip,pins =
++				/* hdmi_debug5 */
++				<1 RK_PB4 7 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		hdmi_debug6: hdmi-debug6 {
++			rockchip,pins =
++				/* hdmi_debug6 */
++				<1 RK_PA0 7 &pcfg_pull_none>;
++		};
++	};
++
++	i2c0 {
++		/omit-if-no-ref/
++		i2c0m0_xfer: i2c0m0-xfer {
++			rockchip,pins =
++				/* i2c0_scl_m0 */
++				<0 RK_PB3 2 &pcfg_pull_none_smt>,
++				/* i2c0_sda_m0 */
++				<0 RK_PA6 2 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c0m2_xfer: i2c0m2-xfer {
++			rockchip,pins =
++				/* i2c0_scl_m2 */
++				<0 RK_PD1 3 &pcfg_pull_none_smt>,
++				/* i2c0_sda_m2 */
++				<0 RK_PD2 3 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c1 {
++		/omit-if-no-ref/
++		i2c1m0_xfer: i2c1m0-xfer {
++			rockchip,pins =
++				/* i2c1_scl_m0 */
++				<0 RK_PB5 9 &pcfg_pull_none_smt>,
++				/* i2c1_sda_m0 */
++				<0 RK_PB6 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c1m1_xfer: i2c1m1-xfer {
++			rockchip,pins =
++				/* i2c1_scl_m1 */
++				<0 RK_PB0 2 &pcfg_pull_none_smt>,
++				/* i2c1_sda_m1 */
++				<0 RK_PB1 2 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c1m2_xfer: i2c1m2-xfer {
++			rockchip,pins =
++				/* i2c1_scl_m2 */
++				<0 RK_PD4 9 &pcfg_pull_none_smt>,
++				/* i2c1_sda_m2 */
++				<0 RK_PD5 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c1m3_xfer: i2c1m3-xfer {
++			rockchip,pins =
++				/* i2c1_scl_m3 */
++				<2 RK_PD4 9 &pcfg_pull_none_smt>,
++				/* i2c1_sda_m3 */
++				<2 RK_PD5 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c1m4_xfer: i2c1m4-xfer {
++			rockchip,pins =
++				/* i2c1_scl_m4 */
++				<1 RK_PD2 9 &pcfg_pull_none_smt>,
++				/* i2c1_sda_m4 */
++				<1 RK_PD3 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c2 {
++		/omit-if-no-ref/
++		i2c2m0_xfer: i2c2m0-xfer {
++			rockchip,pins =
++				/* i2c2_scl_m0 */
++				<0 RK_PB7 9 &pcfg_pull_none_smt>,
++				/* i2c2_sda_m0 */
++				<0 RK_PC0 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c2m2_xfer: i2c2m2-xfer {
++			rockchip,pins =
++				/* i2c2_scl_m2 */
++				<2 RK_PA3 9 &pcfg_pull_none_smt>,
++				/* i2c2_sda_m2 */
++				<2 RK_PA2 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c2m3_xfer: i2c2m3-xfer {
++			rockchip,pins =
++				/* i2c2_scl_m3 */
++				<1 RK_PC5 9 &pcfg_pull_none_smt>,
++				/* i2c2_sda_m3 */
++				<1 RK_PC4 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c2m4_xfer: i2c2m4-xfer {
++			rockchip,pins =
++				/* i2c2_scl_m4 */
++				<1 RK_PA1 9 &pcfg_pull_none_smt>,
++				/* i2c2_sda_m4 */
++				<1 RK_PA0 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c3 {
++		/omit-if-no-ref/
++		i2c3m0_xfer: i2c3m0-xfer {
++			rockchip,pins =
++				/* i2c3_scl_m0 */
++				<1 RK_PC1 9 &pcfg_pull_none_smt>,
++				/* i2c3_sda_m0 */
++				<1 RK_PC0 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c3m1_xfer: i2c3m1-xfer {
++			rockchip,pins =
++				/* i2c3_scl_m1 */
++				<3 RK_PB7 9 &pcfg_pull_none_smt>,
++				/* i2c3_sda_m1 */
++				<3 RK_PC0 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c3m2_xfer: i2c3m2-xfer {
++			rockchip,pins =
++				/* i2c3_scl_m2 */
++				<4 RK_PA4 9 &pcfg_pull_none_smt>,
++				/* i2c3_sda_m2 */
++				<4 RK_PA5 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c3m4_xfer: i2c3m4-xfer {
++			rockchip,pins =
++				/* i2c3_scl_m4 */
++				<4 RK_PD0 9 &pcfg_pull_none_smt>,
++				/* i2c3_sda_m4 */
++				<4 RK_PD1 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c4 {
++		/omit-if-no-ref/
++		i2c4m0_xfer: i2c4m0-xfer {
++			rockchip,pins =
++				/* i2c4_scl_m0 */
++				<3 RK_PA6 9 &pcfg_pull_none_smt>,
++				/* i2c4_sda_m0 */
++				<3 RK_PA5 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c4m2_xfer: i2c4m2-xfer {
++			rockchip,pins =
++				/* i2c4_scl_m2 */
++				<0 RK_PC5 9 &pcfg_pull_none_smt>,
++				/* i2c4_sda_m2 */
++				<0 RK_PC4 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c4m3_xfer: i2c4m3-xfer {
++			rockchip,pins =
++				/* i2c4_scl_m3 */
++				<1 RK_PA3 9 &pcfg_pull_none_smt>,
++				/* i2c4_sda_m3 */
++				<1 RK_PA2 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c4m4_xfer: i2c4m4-xfer {
++			rockchip,pins =
++				/* i2c4_scl_m4 */
++				<1 RK_PC7 9 &pcfg_pull_none_smt>,
++				/* i2c4_sda_m4 */
++				<1 RK_PC6 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c5 {
++		/omit-if-no-ref/
++		i2c5m0_xfer: i2c5m0-xfer {
++			rockchip,pins =
++				/* i2c5_scl_m0 */
++				<3 RK_PC7 9 &pcfg_pull_none_smt>,
++				/* i2c5_sda_m0 */
++				<3 RK_PD0 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c5m1_xfer: i2c5m1-xfer {
++			rockchip,pins =
++				/* i2c5_scl_m1 */
++				<4 RK_PB6 9 &pcfg_pull_none_smt>,
++				/* i2c5_sda_m1 */
++				<4 RK_PB7 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c5m2_xfer: i2c5m2-xfer {
++			rockchip,pins =
++				/* i2c5_scl_m2 */
++				<4 RK_PA6 9 &pcfg_pull_none_smt>,
++				/* i2c5_sda_m2 */
++				<4 RK_PA7 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c5m3_xfer: i2c5m3-xfer {
++			rockchip,pins =
++				/* i2c5_scl_m3 */
++				<1 RK_PB6 9 &pcfg_pull_none_smt>,
++				/* i2c5_sda_m3 */
++				<1 RK_PB7 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c6 {
++		/omit-if-no-ref/
++		i2c6m0_xfer: i2c6m0-xfer {
++			rockchip,pins =
++				/* i2c6_scl_m0 */
++				<0 RK_PD0 9 &pcfg_pull_none_smt>,
++				/* i2c6_sda_m0 */
++				<0 RK_PC7 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c6m1_xfer: i2c6m1-xfer {
++			rockchip,pins =
++				/* i2c6_scl_m1 */
++				<1 RK_PC3 9 &pcfg_pull_none_smt>,
++				/* i2c6_sda_m1 */
++				<1 RK_PC2 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c6m3_xfer: i2c6m3-xfer {
++			rockchip,pins =
++				/* i2c6_scl_m3 */
++				<4 RK_PB1 9 &pcfg_pull_none_smt>,
++				/* i2c6_sda_m3 */
++				<4 RK_PB0 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c6m4_xfer: i2c6m4-xfer {
++			rockchip,pins =
++				/* i2c6_scl_m4 */
++				<3 RK_PA1 9 &pcfg_pull_none_smt>,
++				/* i2c6_sda_m4 */
++				<3 RK_PA0 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c7 {
++		/omit-if-no-ref/
++		i2c7m0_xfer: i2c7m0-xfer {
++			rockchip,pins =
++				/* i2c7_scl_m0 */
++				<1 RK_PD0 9 &pcfg_pull_none_smt>,
++				/* i2c7_sda_m0 */
++				<1 RK_PD1 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c7m2_xfer: i2c7m2-xfer {
++			rockchip,pins =
++				/* i2c7_scl_m2 */
++				<3 RK_PD2 9 &pcfg_pull_none_smt>,
++				/* i2c7_sda_m2 */
++				<3 RK_PD3 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c7m3_xfer: i2c7m3-xfer {
++			rockchip,pins =
++				/* i2c7_scl_m3 */
++				<4 RK_PB2 9 &pcfg_pull_none_smt>,
++				/* i2c7_sda_m3 */
++				<4 RK_PB3 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2c8 {
++		/omit-if-no-ref/
++		i2c8m0_xfer: i2c8m0-xfer {
++			rockchip,pins =
++				/* i2c8_scl_m0 */
++				<4 RK_PD2 9 &pcfg_pull_none_smt>,
++				/* i2c8_sda_m0 */
++				<4 RK_PD3 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c8m2_xfer: i2c8m2-xfer {
++			rockchip,pins =
++				/* i2c8_scl_m2 */
++				<1 RK_PD6 9 &pcfg_pull_none_smt>,
++				/* i2c8_sda_m2 */
++				<1 RK_PD7 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c8m3_xfer: i2c8m3-xfer {
++			rockchip,pins =
++				/* i2c8_scl_m3 */
++				<4 RK_PC0 9 &pcfg_pull_none_smt>,
++				/* i2c8_sda_m3 */
++				<4 RK_PC1 9 &pcfg_pull_none_smt>;
++		};
++
++		/omit-if-no-ref/
++		i2c8m4_xfer: i2c8m4-xfer {
++			rockchip,pins =
++				/* i2c8_scl_m4 */
++				<3 RK_PC2 9 &pcfg_pull_none_smt>,
++				/* i2c8_sda_m4 */
++				<3 RK_PC3 9 &pcfg_pull_none_smt>;
++		};
++	};
++
++	i2s0 {
++		/omit-if-no-ref/
++		i2s0_lrck: i2s0-lrck {
++			rockchip,pins =
++				/* i2s0_lrck */
++				<1 RK_PC5 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_mclk: i2s0-mclk {
++			rockchip,pins =
++				/* i2s0_mclk */
++				<1 RK_PC2 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sclk: i2s0-sclk {
++			rockchip,pins =
++				/* i2s0_sclk */
++				<1 RK_PC3 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdi0: i2s0-sdi0 {
++			rockchip,pins =
++				/* i2s0_sdi0 */
++				<1 RK_PD4 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdi1: i2s0-sdi1 {
++			rockchip,pins =
++				/* i2s0_sdi1 */
++				<1 RK_PD3 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdi2: i2s0-sdi2 {
++			rockchip,pins =
++				/* i2s0_sdi2 */
++				<1 RK_PD2 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdi3: i2s0-sdi3 {
++			rockchip,pins =
++				/* i2s0_sdi3 */
++				<1 RK_PD1 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdo0: i2s0-sdo0 {
++			rockchip,pins =
++				/* i2s0_sdo0 */
++				<1 RK_PC7 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdo1: i2s0-sdo1 {
++			rockchip,pins =
++				/* i2s0_sdo1 */
++				<1 RK_PD0 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdo2: i2s0-sdo2 {
++			rockchip,pins =
++				/* i2s0_sdo2 */
++				<1 RK_PD1 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s0_sdo3: i2s0-sdo3 {
++			rockchip,pins =
++				/* i2s0_sdo3 */
++				<1 RK_PD2 1 &pcfg_pull_none>;
++		};
++	};
++
++	i2s1 {
++		/omit-if-no-ref/
++		i2s1m0_lrck: i2s1m0-lrck {
++			rockchip,pins =
++				/* i2s1m0_lrck */
++				<4 RK_PA2 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_mclk: i2s1m0-mclk {
++			rockchip,pins =
++				/* i2s1m0_mclk */
++				<4 RK_PA0 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sclk: i2s1m0-sclk {
++			rockchip,pins =
++				/* i2s1m0_sclk */
++				<4 RK_PA1 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdi0: i2s1m0-sdi0 {
++			rockchip,pins =
++				/* i2s1m0_sdi0 */
++				<4 RK_PA5 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdi1: i2s1m0-sdi1 {
++			rockchip,pins =
++				/* i2s1m0_sdi1 */
++				<4 RK_PA6 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdi2: i2s1m0-sdi2 {
++			rockchip,pins =
++				/* i2s1m0_sdi2 */
++				<4 RK_PA7 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdi3: i2s1m0-sdi3 {
++			rockchip,pins =
++				/* i2s1m0_sdi3 */
++				<4 RK_PB0 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdo0: i2s1m0-sdo0 {
++			rockchip,pins =
++				/* i2s1m0_sdo0 */
++				<4 RK_PB1 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdo1: i2s1m0-sdo1 {
++			rockchip,pins =
++				/* i2s1m0_sdo1 */
++				<4 RK_PB2 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdo2: i2s1m0-sdo2 {
++			rockchip,pins =
++				/* i2s1m0_sdo2 */
++				<4 RK_PB3 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m0_sdo3: i2s1m0-sdo3 {
++			rockchip,pins =
++				/* i2s1m0_sdo3 */
++				<4 RK_PB4 3 &pcfg_pull_none>;
++		};
++		/omit-if-no-ref/
++		i2s1m1_lrck: i2s1m1-lrck {
++			rockchip,pins =
++				/* i2s1m1_lrck */
++				<0 RK_PB7 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_mclk: i2s1m1-mclk {
++			rockchip,pins =
++				/* i2s1m1_mclk */
++				<0 RK_PB5 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sclk: i2s1m1-sclk {
++			rockchip,pins =
++				/* i2s1m1_sclk */
++				<0 RK_PB6 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdi0: i2s1m1-sdi0 {
++			rockchip,pins =
++				/* i2s1m1_sdi0 */
++				<0 RK_PC5 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdi1: i2s1m1-sdi1 {
++			rockchip,pins =
++				/* i2s1m1_sdi1 */
++				<0 RK_PC6 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdi2: i2s1m1-sdi2 {
++			rockchip,pins =
++				/* i2s1m1_sdi2 */
++				<0 RK_PC7 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdi3: i2s1m1-sdi3 {
++			rockchip,pins =
++				/* i2s1m1_sdi3 */
++				<0 RK_PD0 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdo0: i2s1m1-sdo0 {
++			rockchip,pins =
++				/* i2s1m1_sdo0 */
++				<0 RK_PD1 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdo1: i2s1m1-sdo1 {
++			rockchip,pins =
++				/* i2s1m1_sdo1 */
++				<0 RK_PD2 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdo2: i2s1m1-sdo2 {
++			rockchip,pins =
++				/* i2s1m1_sdo2 */
++				<0 RK_PD4 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s1m1_sdo3: i2s1m1-sdo3 {
++			rockchip,pins =
++				/* i2s1m1_sdo3 */
++				<0 RK_PD5 1 &pcfg_pull_none>;
++		};
++	};
++
++	i2s2 {
++		/omit-if-no-ref/
++		i2s2m1_lrck: i2s2m1-lrck {
++			rockchip,pins =
++				/* i2s2m1_lrck */
++				<3 RK_PB6 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m1_mclk: i2s2m1-mclk {
++			rockchip,pins =
++				/* i2s2m1_mclk */
++				<3 RK_PB4 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m1_sclk: i2s2m1-sclk {
++			rockchip,pins =
++				/* i2s2m1_sclk */
++				<3 RK_PB5 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m1_sdi: i2s2m1-sdi {
++			rockchip,pins =
++				/* i2s2m1_sdi */
++				<3 RK_PB2 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m1_sdo: i2s2m1-sdo {
++			rockchip,pins =
++				/* i2s2m1_sdo */
++				<3 RK_PB3 3 &pcfg_pull_none>;
++		};
++	};
++
++	i2s3 {
++		/omit-if-no-ref/
++		i2s3_lrck: i2s3-lrck {
++			rockchip,pins =
++				/* i2s3_lrck */
++				<3 RK_PA2 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s3_mclk: i2s3-mclk {
++			rockchip,pins =
++				/* i2s3_mclk */
++				<3 RK_PA0 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s3_sclk: i2s3-sclk {
++			rockchip,pins =
++				/* i2s3_sclk */
++				<3 RK_PA1 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s3_sdi: i2s3-sdi {
++			rockchip,pins =
++				/* i2s3_sdi */
++				<3 RK_PA4 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s3_sdo: i2s3-sdo {
++			rockchip,pins =
++				/* i2s3_sdo */
++				<3 RK_PA3 3 &pcfg_pull_none>;
++		};
++	};
++
++	jtag {
++		/omit-if-no-ref/
++		jtagm0_pins: jtagm0-pins {
++			rockchip,pins =
++				/* jtag_tck_m0 */
++				<4 RK_PD2 5 &pcfg_pull_none>,
++				/* jtag_tms_m0 */
++				<4 RK_PD3 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		jtagm1_pins: jtagm1-pins {
++			rockchip,pins =
++				/* jtag_tck_m1 */
++				<4 RK_PD0 5 &pcfg_pull_none>,
++				/* jtag_tms_m1 */
++				<4 RK_PD1 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		jtagm2_pins: jtagm2-pins {
++			rockchip,pins =
++				/* jtag_tck_m2 */
++				<0 RK_PB5 2 &pcfg_pull_none>,
++				/* jtag_tms_m2 */
++				<0 RK_PB6 2 &pcfg_pull_none>;
++		};
++	};
++
++	litcpu {
++		/omit-if-no-ref/
++		litcpu_pins: litcpu-pins {
++			rockchip,pins =
++				/* litcpu_avs */
++				<0 RK_PD3 1 &pcfg_pull_none>;
++		};
++	};
++
++	mcu {
++		/omit-if-no-ref/
++		mcum0_pins: mcum0-pins {
++			rockchip,pins =
++				/* mcu_jtag_tck_m0 */
++				<4 RK_PD4 5 &pcfg_pull_none>,
++				/* mcu_jtag_tms_m0 */
++				<4 RK_PD5 5 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mcum1_pins: mcum1-pins {
++			rockchip,pins =
++				/* mcu_jtag_tck_m1 */
++				<3 RK_PD4 6 &pcfg_pull_none>,
++				/* mcu_jtag_tms_m1 */
++				<3 RK_PD5 6 &pcfg_pull_none>;
++		};
++	};
++
++	mipi {
++		/omit-if-no-ref/
++		mipim0_camera0_clk: mipim0-camera0-clk {
++			rockchip,pins =
++				/* mipim0_camera0_clk */
++				<4 RK_PB1 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim0_camera1_clk: mipim0-camera1-clk {
++			rockchip,pins =
++				/* mipim0_camera1_clk */
++				<1 RK_PB6 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim0_camera2_clk: mipim0-camera2-clk {
++			rockchip,pins =
++				/* mipim0_camera2_clk */
++				<1 RK_PB7 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim0_camera3_clk: mipim0-camera3-clk {
++			rockchip,pins =
++				/* mipim0_camera3_clk */
++				<1 RK_PD6 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim0_camera4_clk: mipim0-camera4-clk {
++			rockchip,pins =
++				/* mipim0_camera4_clk */
++				<1 RK_PD7 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim1_camera0_clk: mipim1-camera0-clk {
++			rockchip,pins =
++				/* mipim1_camera0_clk */
++				<3 RK_PA5 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim1_camera1_clk: mipim1-camera1-clk {
++			rockchip,pins =
++				/* mipim1_camera1_clk */
++				<3 RK_PA6 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim1_camera2_clk: mipim1-camera2-clk {
++			rockchip,pins =
++				/* mipim1_camera2_clk */
++				<3 RK_PA7 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim1_camera3_clk: mipim1-camera3-clk {
++			rockchip,pins =
++				/* mipim1_camera3_clk */
++				<3 RK_PB0 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipim1_camera4_clk: mipim1-camera4-clk {
++			rockchip,pins =
++				/* mipim1_camera4_clk */
++				<3 RK_PB1 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipi_te0: mipi-te0 {
++			rockchip,pins =
++				/* mipi_te0 */
++				<3 RK_PC2 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		mipi_te1: mipi-te1 {
++			rockchip,pins =
++				/* mipi_te1 */
++				<3 RK_PC3 2 &pcfg_pull_none>;
++		};
++	};
++
++	npu {
++		/omit-if-no-ref/
++		npu_pins: npu-pins {
++			rockchip,pins =
++				/* npu_avs */
++				<0 RK_PC6 2 &pcfg_pull_none>;
++		};
++	};
++
++	pcie20x1 {
++		/omit-if-no-ref/
++		pcie20x1m0_pins: pcie20x1m0-pins {
++			rockchip,pins =
++				/* pcie20x1_2_clkreqn_m0 */
++				<3 RK_PC7 4 &pcfg_pull_none>,
++				/* pcie20x1_2_perstn_m0 */
++				<3 RK_PD1 4 &pcfg_pull_none>,
++				/* pcie20x1_2_waken_m0 */
++				<3 RK_PD0 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie20x1m1_pins: pcie20x1m1-pins {
++			rockchip,pins =
++				/* pcie20x1_2_clkreqn_m1 */
++				<4 RK_PB7 4 &pcfg_pull_none>,
++				/* pcie20x1_2_perstn_m1 */
++				<4 RK_PC1 4 &pcfg_pull_none>,
++				/* pcie20x1_2_waken_m1 */
++				<4 RK_PC0 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie20x1_2_button_rstn: pcie20x1-2-button-rstn {
++			rockchip,pins =
++				/* pcie20x1_2_button_rstn */
++				<4 RK_PB3 4 &pcfg_pull_none>;
++		};
++	};
++
++	pcie30phy {
++		/omit-if-no-ref/
++		pcie30phy_pins: pcie30phy-pins {
++			rockchip,pins =
++				/* pcie30phy_dtb0 */
++				<1 RK_PC4 4 &pcfg_pull_none>,
++				/* pcie30phy_dtb1 */
++				<1 RK_PD1 4 &pcfg_pull_none>;
++		};
++	};
++
++	pcie30x1 {
++		/omit-if-no-ref/
++		pcie30x1m0_pins: pcie30x1m0-pins {
++			rockchip,pins =
++				/* pcie30x1_0_clkreqn_m0 */
++				<0 RK_PC0 12 &pcfg_pull_none>,
++				/* pcie30x1_0_perstn_m0 */
++				<0 RK_PC5 12 &pcfg_pull_none>,
++				/* pcie30x1_0_waken_m0 */
++				<0 RK_PC4 12 &pcfg_pull_none>,
++				/* pcie30x1_1_clkreqn_m0 */
++				<0 RK_PB5 12 &pcfg_pull_none>,
++				/* pcie30x1_1_perstn_m0 */
++				<0 RK_PB7 12 &pcfg_pull_none>,
++				/* pcie30x1_1_waken_m0 */
++				<0 RK_PB6 12 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x1m1_pins: pcie30x1m1-pins {
++			rockchip,pins =
++				/* pcie30x1_0_clkreqn_m1 */
++				<4 RK_PA3 4 &pcfg_pull_none>,
++				/* pcie30x1_0_perstn_m1 */
++				<4 RK_PA5 4 &pcfg_pull_none>,
++				/* pcie30x1_0_waken_m1 */
++				<4 RK_PA4 4 &pcfg_pull_none>,
++				/* pcie30x1_1_clkreqn_m1 */
++				<4 RK_PA0 4 &pcfg_pull_none>,
++				/* pcie30x1_1_perstn_m1 */
++				<4 RK_PA2 4 &pcfg_pull_none>,
++				/* pcie30x1_1_waken_m1 */
++				<4 RK_PA1 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x1m2_pins: pcie30x1m2-pins {
++			rockchip,pins =
++				/* pcie30x1_0_clkreqn_m2 */
++				<1 RK_PB5 4 &pcfg_pull_none>,
++				/* pcie30x1_0_perstn_m2 */
++				<1 RK_PB4 4 &pcfg_pull_none>,
++				/* pcie30x1_0_waken_m2 */
++				<1 RK_PB3 4 &pcfg_pull_none>,
++				/* pcie30x1_1_clkreqn_m2 */
++				<1 RK_PA0 4 &pcfg_pull_none>,
++				/* pcie30x1_1_perstn_m2 */
++				<1 RK_PA7 4 &pcfg_pull_none>,
++				/* pcie30x1_1_waken_m2 */
++				<1 RK_PA1 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x1_0_button_rstn: pcie30x1-0-button-rstn {
++			rockchip,pins =
++				/* pcie30x1_0_button_rstn */
++				<4 RK_PB1 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x1_1_button_rstn: pcie30x1-1-button-rstn {
++			rockchip,pins =
++				/* pcie30x1_1_button_rstn */
++				<4 RK_PB2 4 &pcfg_pull_none>;
++		};
++	};
++
++	pcie30x2 {
++		/omit-if-no-ref/
++		pcie30x2m0_pins: pcie30x2m0-pins {
++			rockchip,pins =
++				/* pcie30x2_clkreqn_m0 */
++				<0 RK_PD1 12 &pcfg_pull_none>,
++				/* pcie30x2_perstn_m0 */
++				<0 RK_PD4 12 &pcfg_pull_none>,
++				/* pcie30x2_waken_m0 */
++				<0 RK_PD2 12 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x2m1_pins: pcie30x2m1-pins {
++			rockchip,pins =
++				/* pcie30x2_clkreqn_m1 */
++				<4 RK_PA6 4 &pcfg_pull_none>,
++				/* pcie30x2_perstn_m1 */
++				<4 RK_PB0 4 &pcfg_pull_none>,
++				/* pcie30x2_waken_m1 */
++				<4 RK_PA7 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x2m2_pins: pcie30x2m2-pins {
++			rockchip,pins =
++				/* pcie30x2_clkreqn_m2 */
++				<3 RK_PD2 4 &pcfg_pull_none>,
++				/* pcie30x2_perstn_m2 */
++				<3 RK_PD4 4 &pcfg_pull_none>,
++				/* pcie30x2_waken_m2 */
++				<3 RK_PD3 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x2m3_pins: pcie30x2m3-pins {
++			rockchip,pins =
++				/* pcie30x2_clkreqn_m3 */
++				<1 RK_PD7 4 &pcfg_pull_none>,
++				/* pcie30x2_perstn_m3 */
++				<1 RK_PB7 4 &pcfg_pull_none>,
++				/* pcie30x2_waken_m3 */
++				<1 RK_PB6 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x2_button_rstn: pcie30x2-button-rstn {
++			rockchip,pins =
++				/* pcie30x2_button_rstn */
++				<3 RK_PC1 4 &pcfg_pull_none>;
++		};
++	};
++
++	pcie30x4 {
++		/omit-if-no-ref/
++		pcie30x4m0_pins: pcie30x4m0-pins {
++			rockchip,pins =
++				/* pcie30x4_clkreqn_m0 */
++				<0 RK_PC6 12 &pcfg_pull_none>,
++				/* pcie30x4_perstn_m0 */
++				<0 RK_PD0 12 &pcfg_pull_none>,
++				/* pcie30x4_waken_m0 */
++				<0 RK_PC7 12 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x4m1_pins: pcie30x4m1-pins {
++			rockchip,pins =
++				/* pcie30x4_clkreqn_m1 */
++				<4 RK_PB4 4 &pcfg_pull_none>,
++				/* pcie30x4_perstn_m1 */
++				<4 RK_PB6 4 &pcfg_pull_none>,
++				/* pcie30x4_waken_m1 */
++				<4 RK_PB5 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x4m2_pins: pcie30x4m2-pins {
++			rockchip,pins =
++				/* pcie30x4_clkreqn_m2 */
++				<3 RK_PC4 4 &pcfg_pull_none>,
++				/* pcie30x4_perstn_m2 */
++				<3 RK_PC6 4 &pcfg_pull_none>,
++				/* pcie30x4_waken_m2 */
++				<3 RK_PC5 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x4m3_pins: pcie30x4m3-pins {
++			rockchip,pins =
++				/* pcie30x4_clkreqn_m3 */
++				<1 RK_PB0 4 &pcfg_pull_none>,
++				/* pcie30x4_perstn_m3 */
++				<1 RK_PB2 4 &pcfg_pull_none>,
++				/* pcie30x4_waken_m3 */
++				<1 RK_PB1 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pcie30x4_button_rstn: pcie30x4-button-rstn {
++			rockchip,pins =
++				/* pcie30x4_button_rstn */
++				<3 RK_PD5 4 &pcfg_pull_none>;
++		};
++	};
++
++	pdm0 {
++		/omit-if-no-ref/
++		pdm0m0_clk: pdm0m0-clk {
++			rockchip,pins =
++				/* pdm0_clk0_m0 */
++				<1 RK_PC6 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m0_clk1: pdm0m0-clk1 {
++			rockchip,pins =
++				/* pdm0m0_clk1 */
++				<1 RK_PC4 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m0_sdi0: pdm0m0-sdi0 {
++			rockchip,pins =
++				/* pdm0m0_sdi0 */
++				<1 RK_PD5 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m0_sdi1: pdm0m0-sdi1 {
++			rockchip,pins =
++				/* pdm0m0_sdi1 */
++				<1 RK_PD1 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m0_sdi2: pdm0m0-sdi2 {
++			rockchip,pins =
++				/* pdm0m0_sdi2 */
++				<1 RK_PD2 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m0_sdi3: pdm0m0-sdi3 {
++			rockchip,pins =
++				/* pdm0m0_sdi3 */
++				<1 RK_PD3 3 &pcfg_pull_none>;
++		};
++		/omit-if-no-ref/
++		pdm0m1_clk: pdm0m1-clk {
++			rockchip,pins =
++				/* pdm0_clk0_m1 */
++				<0 RK_PC0 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m1_clk1: pdm0m1-clk1 {
++			rockchip,pins =
++				/* pdm0m1_clk1 */
++				<0 RK_PC4 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m1_sdi0: pdm0m1-sdi0 {
++			rockchip,pins =
++				/* pdm0m1_sdi0 */
++				<0 RK_PC7 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m1_sdi1: pdm0m1-sdi1 {
++			rockchip,pins =
++				/* pdm0m1_sdi1 */
++				<0 RK_PD0 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m1_sdi2: pdm0m1-sdi2 {
++			rockchip,pins =
++				/* pdm0m1_sdi2 */
++				<0 RK_PD4 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm0m1_sdi3: pdm0m1-sdi3 {
++			rockchip,pins =
++				/* pdm0m1_sdi3 */
++				<0 RK_PD6 2 &pcfg_pull_none>;
++		};
++	};
++
++	pdm1 {
++		/omit-if-no-ref/
++		pdm1m0_clk: pdm1m0-clk {
++			rockchip,pins =
++				/* pdm1_clk0_m0 */
++				<4 RK_PD5 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m0_clk1: pdm1m0-clk1 {
++			rockchip,pins =
++				/* pdm1m0_clk1 */
++				<4 RK_PD4 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m0_sdi0: pdm1m0-sdi0 {
++			rockchip,pins =
++				/* pdm1m0_sdi0 */
++				<4 RK_PD3 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m0_sdi1: pdm1m0-sdi1 {
++			rockchip,pins =
++				/* pdm1m0_sdi1 */
++				<4 RK_PD2 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m0_sdi2: pdm1m0-sdi2 {
++			rockchip,pins =
++				/* pdm1m0_sdi2 */
++				<4 RK_PD1 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m0_sdi3: pdm1m0-sdi3 {
++			rockchip,pins =
++				/* pdm1m0_sdi3 */
++				<4 RK_PD0 2 &pcfg_pull_none>;
++		};
++		/omit-if-no-ref/
++		pdm1m1_clk: pdm1m1-clk {
++			rockchip,pins =
++				/* pdm1_clk0_m1 */
++				<1 RK_PB4 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m1_clk1: pdm1m1-clk1 {
++			rockchip,pins =
++				/* pdm1m1_clk1 */
++				<1 RK_PB3 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m1_sdi0: pdm1m1-sdi0 {
++			rockchip,pins =
++				/* pdm1m1_sdi0 */
++				<1 RK_PA7 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m1_sdi1: pdm1m1-sdi1 {
++			rockchip,pins =
++				/* pdm1m1_sdi1 */
++				<1 RK_PB0 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m1_sdi2: pdm1m1-sdi2 {
++			rockchip,pins =
++				/* pdm1m1_sdi2 */
++				<1 RK_PB1 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pdm1m1_sdi3: pdm1m1-sdi3 {
++			rockchip,pins =
++				/* pdm1m1_sdi3 */
++				<1 RK_PB2 2 &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		/omit-if-no-ref/
++		pmic_pins: pmic-pins {
++			rockchip,pins =
++				/* pmic_int_l */
++				<0 RK_PA7 0 &pcfg_pull_up>,
++				/* pmic_sleep1 */
++				<0 RK_PA2 1 &pcfg_pull_none>,
++				/* pmic_sleep2 */
++				<0 RK_PA3 1 &pcfg_pull_none>,
++				/* pmic_sleep3 */
++				<0 RK_PC1 1 &pcfg_pull_none>,
++				/* pmic_sleep4 */
++				<0 RK_PC2 1 &pcfg_pull_none>,
++				/* pmic_sleep5 */
++				<0 RK_PC3 1 &pcfg_pull_none>,
++				/* pmic_sleep6 */
++				<0 RK_PD6 1 &pcfg_pull_none>;
++		};
++	};
++
++	pmu {
++		/omit-if-no-ref/
++		pmu_pins: pmu-pins {
++			rockchip,pins =
++				/* pmu_debug */
++				<0 RK_PA5 3 &pcfg_pull_none>;
++		};
++	};
++
++	pwm0 {
++		/omit-if-no-ref/
++		pwm0m0_pins: pwm0m0-pins {
++			rockchip,pins =
++				/* pwm0_m0 */
++				<0 RK_PB7 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm0m1_pins: pwm0m1-pins {
++			rockchip,pins =
++				/* pwm0_m1 */
++				<1 RK_PD2 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm0m2_pins: pwm0m2-pins {
++			rockchip,pins =
++				/* pwm0_m2 */
++				<1 RK_PA2 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm1 {
++		/omit-if-no-ref/
++		pwm1m0_pins: pwm1m0-pins {
++			rockchip,pins =
++				/* pwm1_m0 */
++				<0 RK_PC0 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm1m1_pins: pwm1m1-pins {
++			rockchip,pins =
++				/* pwm1_m1 */
++				<1 RK_PD3 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm1m2_pins: pwm1m2-pins {
++			rockchip,pins =
++				/* pwm1_m2 */
++				<1 RK_PA3 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm2 {
++		/omit-if-no-ref/
++		pwm2m0_pins: pwm2m0-pins {
++			rockchip,pins =
++				/* pwm2_m0 */
++				<0 RK_PC4 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm2m1_pins: pwm2m1-pins {
++			rockchip,pins =
++				/* pwm2_m1 */
++				<3 RK_PB1 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm3 {
++		/omit-if-no-ref/
++		pwm3m0_pins: pwm3m0-pins {
++			rockchip,pins =
++				/* pwm3_ir_m0 */
++				<0 RK_PD4 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm3m1_pins: pwm3m1-pins {
++			rockchip,pins =
++				/* pwm3_ir_m1 */
++				<3 RK_PB2 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm3m2_pins: pwm3m2-pins {
++			rockchip,pins =
++				/* pwm3_ir_m2 */
++				<1 RK_PC2 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm3m3_pins: pwm3m3-pins {
++			rockchip,pins =
++				/* pwm3_ir_m3 */
++				<1 RK_PA7 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm4 {
++		/omit-if-no-ref/
++		pwm4m0_pins: pwm4m0-pins {
++			rockchip,pins =
++				/* pwm4_m0 */
++				<0 RK_PC5 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm5 {
++		/omit-if-no-ref/
++		pwm5m0_pins: pwm5m0-pins {
++			rockchip,pins =
++				/* pwm5_m0 */
++				<0 RK_PB1 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm5m1_pins: pwm5m1-pins {
++			rockchip,pins =
++				/* pwm5_m1 */
++				<0 RK_PC6 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm6 {
++		/omit-if-no-ref/
++		pwm6m0_pins: pwm6m0-pins {
++			rockchip,pins =
++				/* pwm6_m0 */
++				<0 RK_PC7 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm6m1_pins: pwm6m1-pins {
++			rockchip,pins =
++				/* pwm6_m1 */
++				<4 RK_PC1 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm7 {
++		/omit-if-no-ref/
++		pwm7m0_pins: pwm7m0-pins {
++			rockchip,pins =
++				/* pwm7_ir_m0 */
++				<0 RK_PD0 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm7m1_pins: pwm7m1-pins {
++			rockchip,pins =
++				/* pwm7_ir_m1 */
++				<4 RK_PD4 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm7m2_pins: pwm7m2-pins {
++			rockchip,pins =
++				/* pwm7_ir_m2 */
++				<1 RK_PC3 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm8 {
++		/omit-if-no-ref/
++		pwm8m0_pins: pwm8m0-pins {
++			rockchip,pins =
++				/* pwm8_m0 */
++				<3 RK_PA7 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm8m1_pins: pwm8m1-pins {
++			rockchip,pins =
++				/* pwm8_m1 */
++				<4 RK_PD0 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm8m2_pins: pwm8m2-pins {
++			rockchip,pins =
++				/* pwm8_m2 */
++				<3 RK_PD0 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm9 {
++		/omit-if-no-ref/
++		pwm9m0_pins: pwm9m0-pins {
++			rockchip,pins =
++				/* pwm9_m0 */
++				<3 RK_PB0 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm9m1_pins: pwm9m1-pins {
++			rockchip,pins =
++				/* pwm9_m1 */
++				<4 RK_PD1 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm9m2_pins: pwm9m2-pins {
++			rockchip,pins =
++				/* pwm9_m2 */
++				<3 RK_PD1 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm10 {
++		/omit-if-no-ref/
++		pwm10m0_pins: pwm10m0-pins {
++			rockchip,pins =
++				/* pwm10_m0 */
++				<3 RK_PA0 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm10m1_pins: pwm10m1-pins {
++			rockchip,pins =
++				/* pwm10_m1 */
++				<4 RK_PD3 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm10m2_pins: pwm10m2-pins {
++			rockchip,pins =
++				/* pwm10_m2 */
++				<3 RK_PD3 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm11 {
++		/omit-if-no-ref/
++		pwm11m0_pins: pwm11m0-pins {
++			rockchip,pins =
++				/* pwm11_ir_m0 */
++				<3 RK_PA1 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm11m1_pins: pwm11m1-pins {
++			rockchip,pins =
++				/* pwm11_ir_m1 */
++				<4 RK_PB4 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm11m2_pins: pwm11m2-pins {
++			rockchip,pins =
++				/* pwm11_ir_m2 */
++				<1 RK_PC4 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm11m3_pins: pwm11m3-pins {
++			rockchip,pins =
++				/* pwm11_ir_m3 */
++				<3 RK_PD5 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm12 {
++		/omit-if-no-ref/
++		pwm12m0_pins: pwm12m0-pins {
++			rockchip,pins =
++				/* pwm12_m0 */
++				<3 RK_PB5 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm12m1_pins: pwm12m1-pins {
++			rockchip,pins =
++				/* pwm12_m1 */
++				<4 RK_PB5 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm13 {
++		/omit-if-no-ref/
++		pwm13m0_pins: pwm13m0-pins {
++			rockchip,pins =
++				/* pwm13_m0 */
++				<3 RK_PB6 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm13m1_pins: pwm13m1-pins {
++			rockchip,pins =
++				/* pwm13_m1 */
++				<4 RK_PB6 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm13m2_pins: pwm13m2-pins {
++			rockchip,pins =
++				/* pwm13_m2 */
++				<1 RK_PB7 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm14 {
++		/omit-if-no-ref/
++		pwm14m0_pins: pwm14m0-pins {
++			rockchip,pins =
++				/* pwm14_m0 */
++				<3 RK_PC2 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm14m1_pins: pwm14m1-pins {
++			rockchip,pins =
++				/* pwm14_m1 */
++				<4 RK_PB2 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm14m2_pins: pwm14m2-pins {
++			rockchip,pins =
++				/* pwm14_m2 */
++				<1 RK_PD6 11 &pcfg_pull_none>;
++		};
++	};
++
++	pwm15 {
++		/omit-if-no-ref/
++		pwm15m0_pins: pwm15m0-pins {
++			rockchip,pins =
++				/* pwm15_ir_m0 */
++				<3 RK_PC3 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm15m1_pins: pwm15m1-pins {
++			rockchip,pins =
++				/* pwm15_ir_m1 */
++				<4 RK_PB3 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm15m2_pins: pwm15m2-pins {
++			rockchip,pins =
++				/* pwm15_ir_m2 */
++				<1 RK_PC6 11 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		pwm15m3_pins: pwm15m3-pins {
++			rockchip,pins =
++				/* pwm15_ir_m3 */
++				<1 RK_PD7 11 &pcfg_pull_none>;
++		};
++	};
++
++	refclk {
++		/omit-if-no-ref/
++		refclk_pins: refclk-pins {
++			rockchip,pins =
++				/* refclk_out */
++				<0 RK_PA0 1 &pcfg_pull_none>;
++		};
++	};
++
++	sata {
++		/omit-if-no-ref/
++		sata_pins: sata-pins {
++			rockchip,pins =
++				/* sata_cp_pod */
++				<0 RK_PC6 13 &pcfg_pull_none>,
++				/* sata_cpdet */
++				<0 RK_PD4 13 &pcfg_pull_none>,
++				/* sata_mp_switch */
++				<0 RK_PD5 13 &pcfg_pull_none>;
++		};
++	};
++
++	sata0 {
++		/omit-if-no-ref/
++		sata0m0_pins: sata0m0-pins {
++			rockchip,pins =
++				/* sata0_act_led_m0 */
++				<4 RK_PB6 6 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		sata0m1_pins: sata0m1-pins {
++			rockchip,pins =
++				/* sata0_act_led_m1 */
++				<1 RK_PB3 6 &pcfg_pull_none>;
++		};
++	};
++
++	sata1 {
++		/omit-if-no-ref/
++		sata1m0_pins: sata1m0-pins {
++			rockchip,pins =
++				/* sata1_act_led_m0 */
++				<4 RK_PB5 6 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		sata1m1_pins: sata1m1-pins {
++			rockchip,pins =
++				/* sata1_act_led_m1 */
++				<1 RK_PA1 6 &pcfg_pull_none>;
++		};
++	};
++
++	sata2 {
++		/omit-if-no-ref/
++		sata2m0_pins: sata2m0-pins {
++			rockchip,pins =
++				/* sata2_act_led_m0 */
++				<4 RK_PB1 6 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		sata2m1_pins: sata2m1-pins {
++			rockchip,pins =
++				/* sata2_act_led_m1 */
++				<1 RK_PB7 6 &pcfg_pull_none>;
++		};
++	};
++
++	sdio {
++		/omit-if-no-ref/
++		sdiom1_pins: sdiom1-pins {
++			rockchip,pins =
++				/* sdio_clk_m1 */
++				<3 RK_PA5 2 &pcfg_pull_none>,
++				/* sdio_cmd_m1 */
++				<3 RK_PA4 2 &pcfg_pull_none>,
++				/* sdio_d0_m1 */
++				<3 RK_PA0 2 &pcfg_pull_none>,
++				/* sdio_d1_m1 */
++				<3 RK_PA1 2 &pcfg_pull_none>,
++				/* sdio_d2_m1 */
++				<3 RK_PA2 2 &pcfg_pull_none>,
++				/* sdio_d3_m1 */
++				<3 RK_PA3 2 &pcfg_pull_none>;
++		};
++	};
++
++	sdmmc {
++		/omit-if-no-ref/
++		sdmmc_bus4: sdmmc-bus4 {
++			rockchip,pins =
++				/* sdmmc_d0 */
++				<4 RK_PD0 1 &pcfg_pull_up_drv_level_2>,
++				/* sdmmc_d1 */
++				<4 RK_PD1 1 &pcfg_pull_up_drv_level_2>,
++				/* sdmmc_d2 */
++				<4 RK_PD2 1 &pcfg_pull_up_drv_level_2>,
++				/* sdmmc_d3 */
++				<4 RK_PD3 1 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		sdmmc_clk: sdmmc-clk {
++			rockchip,pins =
++				/* sdmmc_clk */
++				<4 RK_PD5 1 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		sdmmc_cmd: sdmmc-cmd {
++			rockchip,pins =
++				/* sdmmc_cmd */
++				<4 RK_PD4 1 &pcfg_pull_up_drv_level_2>;
++		};
++
++		/omit-if-no-ref/
++		sdmmc_det: sdmmc-det {
++			rockchip,pins =
++				/* sdmmc_det */
++				<0 RK_PA4 1 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		sdmmc_pwren: sdmmc-pwren {
++			rockchip,pins =
++				/* sdmmc_pwren */
++				<0 RK_PA5 2 &pcfg_pull_none>;
++		};
++	};
++
++	spdif0 {
++		/omit-if-no-ref/
++		spdif0m0_tx: spdif0m0-tx {
++			rockchip,pins =
++				/* spdif0m0_tx */
++				<1 RK_PB6 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		spdif0m1_tx: spdif0m1-tx {
++			rockchip,pins =
++				/* spdif0m1_tx */
++				<4 RK_PB4 6 &pcfg_pull_none>;
++		};
++	};
++
++	spdif1 {
++		/omit-if-no-ref/
++		spdif1m0_tx: spdif1m0-tx {
++			rockchip,pins =
++				/* spdif1m0_tx */
++				<1 RK_PB7 3 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		spdif1m1_tx: spdif1m1-tx {
++			rockchip,pins =
++				/* spdif1m1_tx */
++				<4 RK_PB1 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		spdif1m2_tx: spdif1m2-tx {
++			rockchip,pins =
++				/* spdif1m2_tx */
++				<4 RK_PC1 3 &pcfg_pull_none>;
++		};
++	};
++
++	spi0 {
++		/omit-if-no-ref/
++		spi0m0_pins: spi0m0-pins {
++			rockchip,pins =
++				/* spi0_clk_m0 */
++				<0 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_miso_m0 */
++				<0 RK_PC7 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_mosi_m0 */
++				<0 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m0_cs0: spi0m0-cs0 {
++			rockchip,pins =
++				/* spi0_cs0_m0 */
++				<0 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m0_cs1: spi0m0-cs1 {
++			rockchip,pins =
++				/* spi0_cs1_m0 */
++				<0 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
++		};
++		/omit-if-no-ref/
++		spi0m1_pins: spi0m1-pins {
++			rockchip,pins =
++				/* spi0_clk_m1 */
++				<4 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_miso_m1 */
++				<4 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_mosi_m1 */
++				<4 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m1_cs0: spi0m1-cs0 {
++			rockchip,pins =
++				/* spi0_cs0_m1 */
++				<4 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m1_cs1: spi0m1-cs1 {
++			rockchip,pins =
++				/* spi0_cs1_m1 */
++				<4 RK_PB1 8 &pcfg_pull_up_drv_level_1>;
++		};
++		/omit-if-no-ref/
++		spi0m2_pins: spi0m2-pins {
++			rockchip,pins =
++				/* spi0_clk_m2 */
++				<1 RK_PB3 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_miso_m2 */
++				<1 RK_PB1 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_mosi_m2 */
++				<1 RK_PB2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m2_cs0: spi0m2-cs0 {
++			rockchip,pins =
++				/* spi0_cs0_m2 */
++				<1 RK_PB4 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m2_cs1: spi0m2-cs1 {
++			rockchip,pins =
++				/* spi0_cs1_m2 */
++				<1 RK_PB5 8 &pcfg_pull_up_drv_level_1>;
++		};
++		/omit-if-no-ref/
++		spi0m3_pins: spi0m3-pins {
++			rockchip,pins =
++				/* spi0_clk_m3 */
++				<3 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_miso_m3 */
++				<3 RK_PD1 8 &pcfg_pull_up_drv_level_1>,
++				/* spi0_mosi_m3 */
++				<3 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m3_cs0: spi0m3-cs0 {
++			rockchip,pins =
++				/* spi0_cs0_m3 */
++				<3 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi0m3_cs1: spi0m3-cs1 {
++			rockchip,pins =
++				/* spi0_cs1_m3 */
++				<3 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	spi1 {
++		/omit-if-no-ref/
++		spi1m1_pins: spi1m1-pins {
++			rockchip,pins =
++				/* spi1_clk_m1 */
++				<3 RK_PC1 8 &pcfg_pull_up_drv_level_1>,
++				/* spi1_miso_m1 */
++				<3 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi1_mosi_m1 */
++				<3 RK_PB7 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m1_cs0: spi1m1-cs0 {
++			rockchip,pins =
++				/* spi1_cs0_m1 */
++				<3 RK_PC2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m1_cs1: spi1m1-cs1 {
++			rockchip,pins =
++				/* spi1_cs1_m1 */
++				<3 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m2_pins: spi1m2-pins {
++			rockchip,pins =
++				/* spi1_clk_m2 */
++				<1 RK_PD2 8 &pcfg_pull_up_drv_level_1>,
++				/* spi1_miso_m2 */
++				<1 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi1_mosi_m2 */
++				<1 RK_PD1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m2_cs0: spi1m2-cs0 {
++			rockchip,pins =
++				/* spi1_cs0_m2 */
++				<1 RK_PD3 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi1m2_cs1: spi1m2-cs1 {
++			rockchip,pins =
++				/* spi1_cs1_m2 */
++				<1 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	spi2 {
++		/omit-if-no-ref/
++		spi2m0_pins: spi2m0-pins {
++			rockchip,pins =
++				/* spi2_clk_m0 */
++				<1 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
++				/* spi2_miso_m0 */
++				<1 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
++				/* spi2_mosi_m0 */
++				<1 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m0_cs0: spi2m0-cs0 {
++			rockchip,pins =
++				/* spi2_cs0_m0 */
++				<1 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m0_cs1: spi2m0-cs1 {
++			rockchip,pins =
++				/* spi2_cs1_m0 */
++				<1 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m1_pins: spi2m1-pins {
++			rockchip,pins =
++				/* spi2_clk_m1 */
++				<4 RK_PA6 8 &pcfg_pull_up_drv_level_1>,
++				/* spi2_miso_m1 */
++				<4 RK_PA4 8 &pcfg_pull_up_drv_level_1>,
++				/* spi2_mosi_m1 */
++				<4 RK_PA5 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m1_cs0: spi2m1-cs0 {
++			rockchip,pins =
++				/* spi2_cs0_m1 */
++				<4 RK_PA7 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m1_cs1: spi2m1-cs1 {
++			rockchip,pins =
++				/* spi2_cs1_m1 */
++				<4 RK_PB0 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m2_pins: spi2m2-pins {
++			rockchip,pins =
++				/* spi2_clk_m2 */
++				<0 RK_PA5 1 &pcfg_pull_up_drv_level_1>,
++				/* spi2_miso_m2 */
++				<0 RK_PB3 1 &pcfg_pull_up_drv_level_1>,
++				/* spi2_mosi_m2 */
++				<0 RK_PA6 1 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m2_cs0: spi2m2-cs0 {
++			rockchip,pins =
++				/* spi2_cs0_m2 */
++				<0 RK_PB1 1 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi2m2_cs1: spi2m2-cs1 {
++			rockchip,pins =
++				/* spi2_cs1_m2 */
++				<0 RK_PB0 1 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	spi3 {
++		/omit-if-no-ref/
++		spi3m1_pins: spi3m1-pins {
++			rockchip,pins =
++				/* spi3_clk_m1 */
++				<4 RK_PB7 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_miso_m1 */
++				<4 RK_PB5 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_mosi_m1 */
++				<4 RK_PB6 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m1_cs0: spi3m1-cs0 {
++			rockchip,pins =
++				/* spi3_cs0_m1 */
++				<4 RK_PC0 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m1_cs1: spi3m1-cs1 {
++			rockchip,pins =
++				/* spi3_cs1_m1 */
++				<4 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m2_pins: spi3m2-pins {
++			rockchip,pins =
++				/* spi3_clk_m2 */
++				<0 RK_PD3 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_miso_m2 */
++				<0 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_mosi_m2 */
++				<0 RK_PD2 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m2_cs0: spi3m2-cs0 {
++			rockchip,pins =
++				/* spi3_cs0_m2 */
++				<0 RK_PD4 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m2_cs1: spi3m2-cs1 {
++			rockchip,pins =
++				/* spi3_cs1_m2 */
++				<0 RK_PD5 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m3_pins: spi3m3-pins {
++			rockchip,pins =
++				/* spi3_clk_m3 */
++				<3 RK_PD0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_miso_m3 */
++				<3 RK_PC6 8 &pcfg_pull_up_drv_level_1>,
++				/* spi3_mosi_m3 */
++				<3 RK_PC7 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m3_cs0: spi3m3-cs0 {
++			rockchip,pins =
++				/* spi3_cs0_m3 */
++				<3 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi3m3_cs1: spi3m3-cs1 {
++			rockchip,pins =
++				/* spi3_cs1_m3 */
++				<3 RK_PC5 8 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	spi4 {
++		/omit-if-no-ref/
++		spi4m0_pins: spi4m0-pins {
++			rockchip,pins =
++				/* spi4_clk_m0 */
++				<1 RK_PC2 8 &pcfg_pull_up_drv_level_1>,
++				/* spi4_miso_m0 */
++				<1 RK_PC0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi4_mosi_m0 */
++				<1 RK_PC1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m0_cs0: spi4m0-cs0 {
++			rockchip,pins =
++				/* spi4_cs0_m0 */
++				<1 RK_PC3 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m0_cs1: spi4m0-cs1 {
++			rockchip,pins =
++				/* spi4_cs1_m0 */
++				<1 RK_PC4 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m1_pins: spi4m1-pins {
++			rockchip,pins =
++				/* spi4_clk_m1 */
++				<3 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
++				/* spi4_miso_m1 */
++				<3 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi4_mosi_m1 */
++				<3 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m1_cs0: spi4m1-cs0 {
++			rockchip,pins =
++				/* spi4_cs0_m1 */
++				<3 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m1_cs1: spi4m1-cs1 {
++			rockchip,pins =
++				/* spi4_cs1_m1 */
++				<3 RK_PA4 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m2_pins: spi4m2-pins {
++			rockchip,pins =
++				/* spi4_clk_m2 */
++				<1 RK_PA2 8 &pcfg_pull_up_drv_level_1>,
++				/* spi4_miso_m2 */
++				<1 RK_PA0 8 &pcfg_pull_up_drv_level_1>,
++				/* spi4_mosi_m2 */
++				<1 RK_PA1 8 &pcfg_pull_up_drv_level_1>;
++		};
++
++		/omit-if-no-ref/
++		spi4m2_cs0: spi4m2-cs0 {
++			rockchip,pins =
++				/* spi4_cs0_m2 */
++				<1 RK_PA3 8 &pcfg_pull_up_drv_level_1>;
++		};
++	};
++
++	tsadc {
++		/omit-if-no-ref/
++		tsadcm1_shut: tsadcm1-shut {
++			rockchip,pins =
++				/* tsadcm1_shut */
++				<0 RK_PA2 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		tsadc_shut: tsadc-shut {
++			rockchip,pins =
++				/* tsadc_shut */
++				<0 RK_PA1 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		tsadc_shut_org: tsadc-shut-org {
++			rockchip,pins =
++				/* tsadc_shut_org */
++				<0 RK_PA1 1 &pcfg_pull_none>;
++		};
++	};
++
++	uart0 {
++		/omit-if-no-ref/
++		uart0m0_xfer: uart0m0-xfer {
++			rockchip,pins =
++				/* uart0_rx_m0 */
++				<0 RK_PC4 4 &pcfg_pull_up>,
++				/* uart0_tx_m0 */
++				<0 RK_PC5 4 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart0m1_xfer: uart0m1-xfer {
++			rockchip,pins =
++				/* uart0_rx_m1 */
++				<0 RK_PB0 4 &pcfg_pull_up>,
++				/* uart0_tx_m1 */
++				<0 RK_PB1 4 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart0m2_xfer: uart0m2-xfer {
++			rockchip,pins =
++				/* uart0_rx_m2 */
++				<4 RK_PA4 10 &pcfg_pull_up>,
++				/* uart0_tx_m2 */
++				<4 RK_PA3 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart0_ctsn: uart0-ctsn {
++			rockchip,pins =
++				/* uart0_ctsn */
++				<0 RK_PD1 4 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart0_rtsn: uart0-rtsn {
++			rockchip,pins =
++				/* uart0_rtsn */
++				<0 RK_PC6 4 &pcfg_pull_none>;
++		};
++	};
++
++	uart1 {
++		/omit-if-no-ref/
++		uart1m1_xfer: uart1m1-xfer {
++			rockchip,pins =
++				/* uart1_rx_m1 */
++				<1 RK_PB7 10 &pcfg_pull_up>,
++				/* uart1_tx_m1 */
++				<1 RK_PB6 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart1m1_ctsn: uart1m1-ctsn {
++			rockchip,pins =
++				/* uart1m1_ctsn */
++				<1 RK_PD7 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart1m1_rtsn: uart1m1-rtsn {
++			rockchip,pins =
++				/* uart1m1_rtsn */
++				<1 RK_PD6 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart1m2_xfer: uart1m2-xfer {
++			rockchip,pins =
++				/* uart1_rx_m2 */
++				<0 RK_PD2 10 &pcfg_pull_up>,
++				/* uart1_tx_m2 */
++				<0 RK_PD1 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart1m2_ctsn: uart1m2-ctsn {
++			rockchip,pins =
++				/* uart1m2_ctsn */
++				<0 RK_PD0 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart1m2_rtsn: uart1m2-rtsn {
++			rockchip,pins =
++				/* uart1m2_rtsn */
++				<0 RK_PC7 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart2 {
++		/omit-if-no-ref/
++		uart2m0_xfer: uart2m0-xfer {
++			rockchip,pins =
++				/* uart2_rx_m0 */
++				<0 RK_PB6 10 &pcfg_pull_up>,
++				/* uart2_tx_m0 */
++				<0 RK_PB5 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart2m1_xfer: uart2m1-xfer {
++			rockchip,pins =
++				/* uart2_rx_m1 */
++				<4 RK_PD1 10 &pcfg_pull_up>,
++				/* uart2_tx_m1 */
++				<4 RK_PD0 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart2m2_xfer: uart2m2-xfer {
++			rockchip,pins =
++				/* uart2_rx_m2 */
++				<3 RK_PB2 10 &pcfg_pull_up>,
++				/* uart2_tx_m2 */
++				<3 RK_PB1 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart2_ctsn: uart2-ctsn {
++			rockchip,pins =
++				/* uart2_ctsn */
++				<3 RK_PB4 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart2_rtsn: uart2-rtsn {
++			rockchip,pins =
++				/* uart2_rtsn */
++				<3 RK_PB3 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart3 {
++		/omit-if-no-ref/
++		uart3m0_xfer: uart3m0-xfer {
++			rockchip,pins =
++				/* uart3_rx_m0 */
++				<1 RK_PC0 10 &pcfg_pull_up>,
++				/* uart3_tx_m0 */
++				<1 RK_PC1 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart3m1_xfer: uart3m1-xfer {
++			rockchip,pins =
++				/* uart3_rx_m1 */
++				<3 RK_PB6 10 &pcfg_pull_up>,
++				/* uart3_tx_m1 */
++				<3 RK_PB5 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart3m2_xfer: uart3m2-xfer {
++			rockchip,pins =
++				/* uart3_rx_m2 */
++				<4 RK_PA6 10 &pcfg_pull_up>,
++				/* uart3_tx_m2 */
++				<4 RK_PA5 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart3_ctsn: uart3-ctsn {
++			rockchip,pins =
++				/* uart3_ctsn */
++				<1 RK_PC3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart3_rtsn: uart3-rtsn {
++			rockchip,pins =
++				/* uart3_rtsn */
++				<1 RK_PC2 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart4 {
++		/omit-if-no-ref/
++		uart4m0_xfer: uart4m0-xfer {
++			rockchip,pins =
++				/* uart4_rx_m0 */
++				<1 RK_PD3 10 &pcfg_pull_up>,
++				/* uart4_tx_m0 */
++				<1 RK_PD2 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart4m1_xfer: uart4m1-xfer {
++			rockchip,pins =
++				/* uart4_rx_m1 */
++				<3 RK_PD0 10 &pcfg_pull_up>,
++				/* uart4_tx_m1 */
++				<3 RK_PD1 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart4m2_xfer: uart4m2-xfer {
++			rockchip,pins =
++				/* uart4_rx_m2 */
++				<1 RK_PB2 10 &pcfg_pull_up>,
++				/* uart4_tx_m2 */
++				<1 RK_PB3 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart4_ctsn: uart4-ctsn {
++			rockchip,pins =
++				/* uart4_ctsn */
++				<1 RK_PC7 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart4_rtsn: uart4-rtsn {
++			rockchip,pins =
++				/* uart4_rtsn */
++				<1 RK_PC5 10 &pcfg_pull_none>;
++		};
++	};
++
++	uart5 {
++		/omit-if-no-ref/
++		uart5m0_xfer: uart5m0-xfer {
++			rockchip,pins =
++				/* uart5_rx_m0 */
++				<4 RK_PD4 10 &pcfg_pull_up>,
++				/* uart5_tx_m0 */
++				<4 RK_PD5 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart5m0_ctsn: uart5m0-ctsn {
++			rockchip,pins =
++				/* uart5m0_ctsn */
++				<4 RK_PD2 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart5m0_rtsn: uart5m0-rtsn {
++			rockchip,pins =
++				/* uart5m0_rtsn */
++				<4 RK_PD3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart5m1_xfer: uart5m1-xfer {
++			rockchip,pins =
++				/* uart5_rx_m1 */
++				<3 RK_PC5 10 &pcfg_pull_up>,
++				/* uart5_tx_m1 */
++				<3 RK_PC4 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart5m1_ctsn: uart5m1-ctsn {
++			rockchip,pins =
++				/* uart5m1_ctsn */
++				<2 RK_PA2 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart5m1_rtsn: uart5m1-rtsn {
++			rockchip,pins =
++				/* uart5m1_rtsn */
++				<2 RK_PA3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart5m2_xfer: uart5m2-xfer {
++			rockchip,pins =
++				/* uart5_rx_m2 */
++				<2 RK_PD4 10 &pcfg_pull_up>,
++				/* uart5_tx_m2 */
++				<2 RK_PD5 10 &pcfg_pull_up>;
++		};
++	};
++
++	uart6 {
++		/omit-if-no-ref/
++		uart6m1_xfer: uart6m1-xfer {
++			rockchip,pins =
++				/* uart6_rx_m1 */
++				<1 RK_PA0 10 &pcfg_pull_up>,
++				/* uart6_tx_m1 */
++				<1 RK_PA1 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart6m1_ctsn: uart6m1-ctsn {
++			rockchip,pins =
++				/* uart6m1_ctsn */
++				<1 RK_PA3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart6m1_rtsn: uart6m1-rtsn {
++			rockchip,pins =
++				/* uart6m1_rtsn */
++				<1 RK_PA2 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart6m2_xfer: uart6m2-xfer {
++			rockchip,pins =
++				/* uart6_rx_m2 */
++				<1 RK_PD1 10 &pcfg_pull_up>,
++				/* uart6_tx_m2 */
++				<1 RK_PD0 10 &pcfg_pull_up>;
++		};
++	};
++
++	uart7 {
++		/omit-if-no-ref/
++		uart7m1_xfer: uart7m1-xfer {
++			rockchip,pins =
++				/* uart7_rx_m1 */
++				<3 RK_PC1 10 &pcfg_pull_up>,
++				/* uart7_tx_m1 */
++				<3 RK_PC0 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart7m1_ctsn: uart7m1-ctsn {
++			rockchip,pins =
++				/* uart7m1_ctsn */
++				<3 RK_PC3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart7m1_rtsn: uart7m1-rtsn {
++			rockchip,pins =
++				/* uart7m1_rtsn */
++				<3 RK_PC2 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart7m2_xfer: uart7m2-xfer {
++			rockchip,pins =
++				/* uart7_rx_m2 */
++				<1 RK_PB4 10 &pcfg_pull_up>,
++				/* uart7_tx_m2 */
++				<1 RK_PB5 10 &pcfg_pull_up>;
++		};
++	};
++
++	uart8 {
++		/omit-if-no-ref/
++		uart8m0_xfer: uart8m0-xfer {
++			rockchip,pins =
++				/* uart8_rx_m0 */
++				<4 RK_PB1 10 &pcfg_pull_up>,
++				/* uart8_tx_m0 */
++				<4 RK_PB0 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart8m0_ctsn: uart8m0-ctsn {
++			rockchip,pins =
++				/* uart8m0_ctsn */
++				<4 RK_PB3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart8m0_rtsn: uart8m0-rtsn {
++			rockchip,pins =
++				/* uart8m0_rtsn */
++				<4 RK_PB2 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart8m1_xfer: uart8m1-xfer {
++			rockchip,pins =
++				/* uart8_rx_m1 */
++				<3 RK_PA3 10 &pcfg_pull_up>,
++				/* uart8_tx_m1 */
++				<3 RK_PA2 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart8m1_ctsn: uart8m1-ctsn {
++			rockchip,pins =
++				/* uart8m1_ctsn */
++				<3 RK_PA5 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart8m1_rtsn: uart8m1-rtsn {
++			rockchip,pins =
++				/* uart8m1_rtsn */
++				<3 RK_PA4 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart8_xfer: uart8-xfer {
++			rockchip,pins =
++				/* uart8_rx_ */
++				<4 RK_PB1 10 &pcfg_pull_up>;
++		};
++	};
++
++	uart9 {
++		/omit-if-no-ref/
++		uart9m1_xfer: uart9m1-xfer {
++			rockchip,pins =
++				/* uart9_rx_m1 */
++				<4 RK_PB5 10 &pcfg_pull_up>,
++				/* uart9_tx_m1 */
++				<4 RK_PB4 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart9m1_ctsn: uart9m1-ctsn {
++			rockchip,pins =
++				/* uart9m1_ctsn */
++				<4 RK_PA1 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart9m1_rtsn: uart9m1-rtsn {
++			rockchip,pins =
++				/* uart9m1_rtsn */
++				<4 RK_PA0 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart9m2_xfer: uart9m2-xfer {
++			rockchip,pins =
++				/* uart9_rx_m2 */
++				<3 RK_PD4 10 &pcfg_pull_up>,
++				/* uart9_tx_m2 */
++				<3 RK_PD5 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
++		uart9m2_ctsn: uart9m2-ctsn {
++			rockchip,pins =
++				/* uart9m2_ctsn */
++				<3 RK_PD3 10 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		uart9m2_rtsn: uart9m2-rtsn {
++			rockchip,pins =
++				/* uart9m2_rtsn */
++				<3 RK_PD2 10 &pcfg_pull_none>;
++		};
++	};
++
++	vop {
++		/omit-if-no-ref/
++		vop_pins: vop-pins {
++			rockchip,pins =
++				/* vop_post_empty */
++				<1 RK_PA2 1 &pcfg_pull_none>;
++		};
++	};
++};
++
++/*
++ * This part is edited handly.
++ */
++&pinctrl {
++	bt656 {
++		/omit-if-no-ref/
++		bt656_pins: bt656-pins {
++			rockchip,pins =
++				/* bt1120_clkout */
++				<4 RK_PB0 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d0 */
++				<4 RK_PA0 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d1 */
++				<4 RK_PA1 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d2 */
++				<4 RK_PA2 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d3 */
++				<4 RK_PA3 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d4 */
++				<4 RK_PA4 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d5 */
++				<4 RK_PA5 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d6 */
++				<4 RK_PA6 2 &pcfg_pull_none_drv_level_2>,
++				/* bt1120_d7 */
++				<4 RK_PA7 2 &pcfg_pull_none_drv_level_2>;
++		};
++	};
++
++	gpio-func {
++		/omit-if-no-ref/
++		tsadc_gpio_func: tsadc-gpio-func {
++			rockchip,pins =
++				<0 RK_PA1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/098-arm64-dts-rockchip-Add-base-DT-for-rk3588-SoC.patch b/target/linux/rockchip/patches-6.1/098-arm64-dts-rockchip-Add-base-DT-for-rk3588-SoC.patch
new file mode 100644
index 00000000000..37556d862c0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/098-arm64-dts-rockchip-Add-base-DT-for-rk3588-SoC.patch
@@ -0,0 +1,1800 @@
+From c056fa6c2f8bc96b1e5b410f363b458315857a10 Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Mon, 9 Jan 2023 16:57:57 +0100
+Subject: [PATCH 098/383] arm64: dts: rockchip: Add base DT for rk3588 SoC
+
+This initial version supports CPU, dma, interrupts, timers, UART and
+SDHCI (everything necessary to boot Linux on this system on chip) as
+well as Ethernet, I2C, PWM and SPI.
+
+The DT is split into rk3588 and rk3588s, which is a reduced version
+(i.e. with less peripherals) of the former.
+
+Co-Developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
+Co-Developed-by: Elaine Zhang <zhangqing@rock-chips.com>
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Co-Developed-by: Sugar Zhang <sugar.zhang@rock-chips.com>
+Signed-off-by: Sugar Zhang <sugar.zhang@rock-chips.com>
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+[rebase, squash and reword commit message]
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Jagan Teki <jagan@edgeble.ai>
+Tested-by: Jagan Teki <jagan@edgeble.ai> # edgeble-neu6a
+Link: https://lore.kernel.org/r/20230109155801.51642-4-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  |   58 +
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1703 +++++++++++++++++++++
+ 2 files changed, 1761 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -0,0 +1,58 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++#include "rk3588s.dtsi"
++#include "rk3588-pinctrl.dtsi"
++
++/ {
++	gmac0: ethernet@fe1b0000 {
++		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
++		reg = <0x0 0xfe1b0000 0x0 0x10000>;
++		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "macirq", "eth_wake_irq";
++		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
++			 <&cru PCLK_GMAC0>, <&cru ACLK_GMAC0>,
++			 <&cru CLK_GMAC0_PTP_REF>;
++		clock-names = "stmmaceth", "clk_mac_ref",
++			      "pclk_mac", "aclk_mac",
++			      "ptp_ref";
++		power-domains = <&power RK3588_PD_GMAC>;
++		resets = <&cru SRST_A_GMAC0>;
++		reset-names = "stmmaceth";
++		rockchip,grf = <&sys_grf>;
++		rockchip,php-grf = <&php_grf>;
++		snps,axi-config = <&gmac0_stmmac_axi_setup>;
++		snps,mixed-burst;
++		snps,mtl-rx-config = <&gmac0_mtl_rx_setup>;
++		snps,mtl-tx-config = <&gmac0_mtl_tx_setup>;
++		snps,tso;
++		status = "disabled";
++
++		mdio0: mdio {
++			compatible = "snps,dwmac-mdio";
++			#address-cells = <0x1>;
++			#size-cells = <0x0>;
++		};
++
++		gmac0_stmmac_axi_setup: stmmac-axi-config {
++			snps,blen = <0 0 0 0 16 8 4>;
++			snps,wr_osr_lmt = <4>;
++			snps,rd_osr_lmt = <8>;
++		};
++
++		gmac0_mtl_rx_setup: rx-queues-config {
++			snps,rx-queues-to-use = <2>;
++			queue0 {};
++			queue1 {};
++		};
++
++		gmac0_mtl_tx_setup: tx-queues-config {
++			snps,tx-queues-to-use = <2>;
++			queue0 {};
++			queue1 {};
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -0,0 +1,1703 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++#include <dt-bindings/clock/rockchip,rk3588-cru.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/irq.h>
++#include <dt-bindings/power/rk3588-power.h>
++#include <dt-bindings/reset/rockchip,rk3588-cru.h>
++
++/ {
++	compatible = "rockchip,rk3588";
++
++	interrupt-parent = <&gic>;
++	#address-cells = <2>;
++	#size-cells = <2>;
++
++	cpus {
++		#address-cells = <1>;
++		#size-cells = <0>;
++
++		cpu-map {
++			cluster0 {
++				core0 {
++					cpu = <&cpu_l0>;
++				};
++				core1 {
++					cpu = <&cpu_l1>;
++				};
++				core2 {
++					cpu = <&cpu_l2>;
++				};
++				core3 {
++					cpu = <&cpu_l3>;
++				};
++			};
++			cluster1 {
++				core0 {
++					cpu = <&cpu_b0>;
++				};
++				core1 {
++					cpu = <&cpu_b1>;
++				};
++			};
++			cluster2 {
++				core0 {
++					cpu = <&cpu_b2>;
++				};
++				core1 {
++					cpu = <&cpu_b3>;
++				};
++			};
++		};
++
++		cpu_l0: cpu@0 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a55";
++			reg = <0x0>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <530>;
++			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <32768>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <128>;
++			d-cache-size = <32768>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <128>;
++			next-level-cache = <&l2_cache_l0>;
++			dynamic-power-coefficient = <228>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_l1: cpu@100 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a55";
++			reg = <0x100>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <530>;
++			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <32768>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <128>;
++			d-cache-size = <32768>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <128>;
++			next-level-cache = <&l2_cache_l1>;
++			dynamic-power-coefficient = <228>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_l2: cpu@200 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a55";
++			reg = <0x200>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <530>;
++			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <32768>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <128>;
++			d-cache-size = <32768>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <128>;
++			next-level-cache = <&l2_cache_l2>;
++			dynamic-power-coefficient = <228>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_l3: cpu@300 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a55";
++			reg = <0x300>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <530>;
++			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <32768>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <128>;
++			d-cache-size = <32768>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <128>;
++			next-level-cache = <&l2_cache_l3>;
++			dynamic-power-coefficient = <228>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_b0: cpu@400 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a76";
++			reg = <0x400>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <1024>;
++			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <65536>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <256>;
++			d-cache-size = <65536>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <256>;
++			next-level-cache = <&l2_cache_b0>;
++			dynamic-power-coefficient = <416>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_b1: cpu@500 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a76";
++			reg = <0x500>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <1024>;
++			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <65536>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <256>;
++			d-cache-size = <65536>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <256>;
++			next-level-cache = <&l2_cache_b1>;
++			dynamic-power-coefficient = <416>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_b2: cpu@600 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a76";
++			reg = <0x600>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <1024>;
++			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <65536>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <256>;
++			d-cache-size = <65536>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <256>;
++			next-level-cache = <&l2_cache_b2>;
++			dynamic-power-coefficient = <416>;
++			#cooling-cells = <2>;
++		};
++
++		cpu_b3: cpu@700 {
++			device_type = "cpu";
++			compatible = "arm,cortex-a76";
++			reg = <0x700>;
++			enable-method = "psci";
++			capacity-dmips-mhz = <1024>;
++			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
++			cpu-idle-states = <&CPU_SLEEP>;
++			i-cache-size = <65536>;
++			i-cache-line-size = <64>;
++			i-cache-sets = <256>;
++			d-cache-size = <65536>;
++			d-cache-line-size = <64>;
++			d-cache-sets = <256>;
++			next-level-cache = <&l2_cache_b3>;
++			dynamic-power-coefficient = <416>;
++			#cooling-cells = <2>;
++		};
++
++		idle-states {
++			entry-method = "psci";
++			CPU_SLEEP: cpu-sleep {
++				compatible = "arm,idle-state";
++				local-timer-stop;
++				arm,psci-suspend-param = <0x0010000>;
++				entry-latency-us = <100>;
++				exit-latency-us = <120>;
++				min-residency-us = <1000>;
++			};
++		};
++
++		l2_cache_l0: l2-cache-l0 {
++			compatible = "cache";
++			cache-size = <131072>;
++			cache-line-size = <64>;
++			cache-sets = <512>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_l1: l2-cache-l1 {
++			compatible = "cache";
++			cache-size = <131072>;
++			cache-line-size = <64>;
++			cache-sets = <512>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_l2: l2-cache-l2 {
++			compatible = "cache";
++			cache-size = <131072>;
++			cache-line-size = <64>;
++			cache-sets = <512>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_l3: l2-cache-l3 {
++			compatible = "cache";
++			cache-size = <131072>;
++			cache-line-size = <64>;
++			cache-sets = <512>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_b0: l2-cache-b0 {
++			compatible = "cache";
++			cache-size = <524288>;
++			cache-line-size = <64>;
++			cache-sets = <1024>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_b1: l2-cache-b1 {
++			compatible = "cache";
++			cache-size = <524288>;
++			cache-line-size = <64>;
++			cache-sets = <1024>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_b2: l2-cache-b2 {
++			compatible = "cache";
++			cache-size = <524288>;
++			cache-line-size = <64>;
++			cache-sets = <1024>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l2_cache_b3: l2-cache-b3 {
++			compatible = "cache";
++			cache-size = <524288>;
++			cache-line-size = <64>;
++			cache-sets = <1024>;
++			next-level-cache = <&l3_cache>;
++		};
++
++		l3_cache: l3-cache {
++			compatible = "cache";
++			cache-size = <3145728>;
++			cache-line-size = <64>;
++			cache-sets = <4096>;
++		};
++	};
++
++	firmware {
++		optee: optee {
++			compatible = "linaro,optee-tz";
++			method = "smc";
++		};
++
++		scmi: scmi {
++			compatible = "arm,scmi-smc";
++			arm,smc-id = <0x82000010>;
++			shmem = <&scmi_shmem>;
++			#address-cells = <1>;
++			#size-cells = <0>;
++
++			scmi_clk: protocol@14 {
++				reg = <0x14>;
++				assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
++						  <&scmi_clk SCMI_CLK_CPUB23>;
++				assigned-clock-rates = <1200000000>,
++						       <1200000000>;
++				#clock-cells = <1>;
++			};
++
++			scmi_reset: protocol@16 {
++				reg = <0x16>;
++				#reset-cells = <1>;
++			};
++		};
++	};
++
++	pmu-a55 {
++		compatible = "arm,cortex-a55-pmu";
++		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition0>;
++	};
++
++	pmu-a76 {
++		compatible = "arm,cortex-a76-pmu";
++		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_partition1>;
++	};
++
++	psci {
++		compatible = "arm,psci-1.0";
++		method = "smc";
++	};
++
++	spll: clock-0 {
++		compatible = "fixed-clock";
++		clock-frequency = <702000000>;
++		clock-output-names = "spll";
++		#clock-cells = <0>;
++	};
++
++	timer {
++		compatible = "arm,armv8-timer";
++		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_PPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt";
++	};
++
++	xin24m: clock-1 {
++		compatible = "fixed-clock";
++		clock-frequency = <24000000>;
++		clock-output-names = "xin24m";
++		#clock-cells = <0>;
++	};
++
++	xin32k: clock-2 {
++		compatible = "fixed-clock";
++		clock-frequency = <32768>;
++		clock-output-names = "xin32k";
++		#clock-cells = <0>;
++	};
++
++	pmu_sram: sram@10f000 {
++		compatible = "mmio-sram";
++		reg = <0x0 0x0010f000 0x0 0x100>;
++		ranges = <0 0x0 0x0010f000 0x100>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		scmi_shmem: sram@0 {
++			compatible = "arm,scmi-shmem";
++			reg = <0x0 0x100>;
++		};
++	};
++
++	sys_grf: syscon@fd58c000 {
++		compatible = "rockchip,rk3588-sys-grf", "syscon";
++		reg = <0x0 0xfd58c000 0x0 0x1000>;
++	};
++
++	php_grf: syscon@fd5b0000 {
++		compatible = "rockchip,rk3588-php-grf", "syscon";
++		reg = <0x0 0xfd5b0000 0x0 0x1000>;
++	};
++
++	ioc: syscon@fd5f0000 {
++		compatible = "rockchip,rk3588-ioc", "syscon";
++		reg = <0x0 0xfd5f0000 0x0 0x10000>;
++	};
++
++	system_sram1: sram@fd600000 {
++		compatible = "mmio-sram";
++		reg = <0x0 0xfd600000 0x0 0x100000>;
++		ranges = <0x0 0x0 0xfd600000 0x100000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++	};
++
++	cru: clock-controller@fd7c0000 {
++		compatible = "rockchip,rk3588-cru";
++		reg = <0x0 0xfd7c0000 0x0 0x5c000>;
++		assigned-clocks =
++			<&cru PLL_PPLL>, <&cru PLL_AUPLL>,
++			<&cru PLL_NPLL>, <&cru PLL_GPLL>,
++			<&cru ACLK_CENTER_ROOT>,
++			<&cru HCLK_CENTER_ROOT>, <&cru ACLK_CENTER_LOW_ROOT>,
++			<&cru ACLK_TOP_ROOT>, <&cru PCLK_TOP_ROOT>,
++			<&cru ACLK_LOW_TOP_ROOT>, <&cru PCLK_PMU0_ROOT>,
++			<&cru HCLK_PMU_CM0_ROOT>, <&cru ACLK_VOP>,
++			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
++			<&cru CLK_GPU>;
++		assigned-clock-rates =
++			<100000000>, <786432000>,
++			<850000000>, <1188000000>,
++			<702000000>,
++			<400000000>, <500000000>,
++			<800000000>, <100000000>,
++			<400000000>, <100000000>,
++			<200000000>, <500000000>,
++			<375000000>, <150000000>,
++			<200000000>;
++		rockchip,grf = <&php_grf>;
++		#clock-cells = <1>;
++		#reset-cells = <1>;
++	};
++
++	i2c0: i2c@fd880000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfd880000 0x0 0x1000>;
++		interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_I2C0>, <&cru PCLK_I2C0>;
++		clock-names = "i2c", "pclk";
++		pinctrl-0 = <&i2c0m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	uart0: serial@fd890000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfd890000 0x0 0x100>;
++		interrupts = <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac0 6>, <&dmac0 7>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart0m1_xfer>;
++		pinctrl-names = "default";
++		reg-shift = <2>;
++		reg-io-width = <4>;
++		status = "disabled";
++	};
++
++	pwm0: pwm@fd8b0000 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfd8b0000 0x0 0x10>;
++		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm0m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm1: pwm@fd8b0010 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfd8b0010 0x0 0x10>;
++		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm1m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm2: pwm@fd8b0020 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfd8b0020 0x0 0x10>;
++		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm2m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm3: pwm@fd8b0030 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfd8b0030 0x0 0x10>;
++		clocks = <&cru CLK_PMU1PWM>, <&cru PCLK_PMU1PWM>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm3m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pmu: power-management@fd8d8000 {
++		compatible = "rockchip,rk3588-pmu", "syscon", "simple-mfd";
++		reg = <0x0 0xfd8d8000 0x0 0x400>;
++
++		power: power-controller {
++			compatible = "rockchip,rk3588-power-controller";
++			#address-cells = <1>;
++			#power-domain-cells = <1>;
++			#size-cells = <0>;
++			status = "okay";
++
++			/* These power domains are grouped by VD_NPU */
++			power-domain@RK3588_PD_NPU {
++				reg = <RK3588_PD_NPU>;
++				#power-domain-cells = <0>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++
++				power-domain@RK3588_PD_NPUTOP {
++					reg = <RK3588_PD_NPUTOP>;
++					clocks = <&cru HCLK_NPU_ROOT>,
++						 <&cru PCLK_NPU_ROOT>,
++						 <&cru CLK_NPU_DSU0>,
++						 <&cru HCLK_NPU_CM0_ROOT>;
++					pm_qos = <&qos_npu0_mwr>,
++						 <&qos_npu0_mro>,
++						 <&qos_mcu_npu>;
++					#power-domain-cells = <0>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++
++					power-domain@RK3588_PD_NPU1 {
++						reg = <RK3588_PD_NPU1>;
++						clocks = <&cru HCLK_NPU_ROOT>,
++							 <&cru PCLK_NPU_ROOT>,
++							 <&cru CLK_NPU_DSU0>;
++						pm_qos = <&qos_npu1>;
++						#power-domain-cells = <0>;
++					};
++					power-domain@RK3588_PD_NPU2 {
++						reg = <RK3588_PD_NPU2>;
++						clocks = <&cru HCLK_NPU_ROOT>,
++							 <&cru PCLK_NPU_ROOT>,
++							 <&cru CLK_NPU_DSU0>;
++						pm_qos = <&qos_npu2>;
++						#power-domain-cells = <0>;
++					};
++				};
++			};
++			/* These power domains are grouped by VD_GPU */
++			power-domain@RK3588_PD_GPU {
++				reg = <RK3588_PD_GPU>;
++				clocks = <&cru CLK_GPU>,
++					 <&cru CLK_GPU_COREGROUP>,
++					 <&cru CLK_GPU_STACKS>;
++				pm_qos = <&qos_gpu_m0>,
++					 <&qos_gpu_m1>,
++					 <&qos_gpu_m2>,
++					 <&qos_gpu_m3>;
++				#power-domain-cells = <0>;
++			};
++			/* These power domains are grouped by VD_VCODEC */
++			power-domain@RK3588_PD_VCODEC {
++				reg = <RK3588_PD_VCODEC>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++				#power-domain-cells = <0>;
++
++				power-domain@RK3588_PD_RKVDEC0 {
++					reg = <RK3588_PD_RKVDEC0>;
++					clocks = <&cru HCLK_RKVDEC0>,
++						 <&cru HCLK_VDPU_ROOT>,
++						 <&cru ACLK_VDPU_ROOT>,
++						 <&cru ACLK_RKVDEC0>,
++						 <&cru ACLK_RKVDEC_CCU>;
++					pm_qos = <&qos_rkvdec0>;
++					#power-domain-cells = <0>;
++				};
++				power-domain@RK3588_PD_RKVDEC1 {
++					reg = <RK3588_PD_RKVDEC1>;
++					clocks = <&cru HCLK_RKVDEC1>,
++						 <&cru HCLK_VDPU_ROOT>,
++						 <&cru ACLK_VDPU_ROOT>,
++						 <&cru ACLK_RKVDEC1>;
++					pm_qos = <&qos_rkvdec1>;
++					#power-domain-cells = <0>;
++				};
++				power-domain@RK3588_PD_VENC0 {
++					reg = <RK3588_PD_VENC0>;
++					clocks = <&cru HCLK_RKVENC0>,
++						 <&cru ACLK_RKVENC0>;
++					pm_qos = <&qos_rkvenc0_m0ro>,
++						 <&qos_rkvenc0_m1ro>,
++						 <&qos_rkvenc0_m2wo>;
++					#address-cells = <1>;
++					#size-cells = <0>;
++					#power-domain-cells = <0>;
++
++					power-domain@RK3588_PD_VENC1 {
++						reg = <RK3588_PD_VENC1>;
++						clocks = <&cru HCLK_RKVENC1>,
++							 <&cru HCLK_RKVENC0>,
++							 <&cru ACLK_RKVENC0>,
++							 <&cru ACLK_RKVENC1>;
++						pm_qos = <&qos_rkvenc1_m0ro>,
++							 <&qos_rkvenc1_m1ro>,
++							 <&qos_rkvenc1_m2wo>;
++						#power-domain-cells = <0>;
++					};
++				};
++			};
++			/* These power domains are grouped by VD_LOGIC */
++			power-domain@RK3588_PD_VDPU {
++				reg = <RK3588_PD_VDPU>;
++				clocks = <&cru HCLK_VDPU_ROOT>,
++					 <&cru ACLK_VDPU_LOW_ROOT>,
++					 <&cru ACLK_VDPU_ROOT>,
++					 <&cru ACLK_JPEG_DECODER_ROOT>,
++					 <&cru ACLK_IEP2P0>,
++					 <&cru HCLK_IEP2P0>,
++					 <&cru ACLK_JPEG_ENCODER0>,
++					 <&cru HCLK_JPEG_ENCODER0>,
++					 <&cru ACLK_JPEG_ENCODER1>,
++					 <&cru HCLK_JPEG_ENCODER1>,
++					 <&cru ACLK_JPEG_ENCODER2>,
++					 <&cru HCLK_JPEG_ENCODER2>,
++					 <&cru ACLK_JPEG_ENCODER3>,
++					 <&cru HCLK_JPEG_ENCODER3>,
++					 <&cru ACLK_JPEG_DECODER>,
++					 <&cru HCLK_JPEG_DECODER>,
++					 <&cru ACLK_RGA2>,
++					 <&cru HCLK_RGA2>;
++				pm_qos = <&qos_iep>,
++					 <&qos_jpeg_dec>,
++					 <&qos_jpeg_enc0>,
++					 <&qos_jpeg_enc1>,
++					 <&qos_jpeg_enc2>,
++					 <&qos_jpeg_enc3>,
++					 <&qos_rga2_mro>,
++					 <&qos_rga2_mwo>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++				#power-domain-cells = <0>;
++
++
++				power-domain@RK3588_PD_AV1 {
++					reg = <RK3588_PD_AV1>;
++					clocks = <&cru PCLK_AV1>,
++						 <&cru ACLK_AV1>,
++						 <&cru HCLK_VDPU_ROOT>;
++					pm_qos = <&qos_av1>;
++					#power-domain-cells = <0>;
++				};
++				power-domain@RK3588_PD_RKVDEC0 {
++					reg = <RK3588_PD_RKVDEC0>;
++					clocks = <&cru HCLK_RKVDEC0>,
++						 <&cru HCLK_VDPU_ROOT>,
++						 <&cru ACLK_VDPU_ROOT>,
++						 <&cru ACLK_RKVDEC0>;
++					pm_qos = <&qos_rkvdec0>;
++					#power-domain-cells = <0>;
++				};
++				power-domain@RK3588_PD_RKVDEC1 {
++					reg = <RK3588_PD_RKVDEC1>;
++					clocks = <&cru HCLK_RKVDEC1>,
++						 <&cru HCLK_VDPU_ROOT>,
++						 <&cru ACLK_VDPU_ROOT>;
++					pm_qos = <&qos_rkvdec1>;
++					#power-domain-cells = <0>;
++				};
++				power-domain@RK3588_PD_RGA30 {
++					reg = <RK3588_PD_RGA30>;
++					clocks = <&cru ACLK_RGA3_0>,
++						 <&cru HCLK_RGA3_0>;
++					pm_qos = <&qos_rga3_0>;
++					#power-domain-cells = <0>;
++				};
++			};
++			power-domain@RK3588_PD_VOP {
++				reg = <RK3588_PD_VOP>;
++				clocks = <&cru PCLK_VOP_ROOT>,
++					 <&cru HCLK_VOP_ROOT>,
++					 <&cru ACLK_VOP>;
++				pm_qos = <&qos_vop_m0>,
++					 <&qos_vop_m1>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++				#power-domain-cells = <0>;
++
++				power-domain@RK3588_PD_VO0 {
++					reg = <RK3588_PD_VO0>;
++					clocks = <&cru PCLK_VO0_ROOT>,
++						 <&cru PCLK_VO0_S_ROOT>,
++						 <&cru HCLK_VO0_S_ROOT>,
++						 <&cru ACLK_VO0_ROOT>,
++						 <&cru HCLK_HDCP0>,
++						 <&cru ACLK_HDCP0>,
++						 <&cru HCLK_VOP_ROOT>;
++					pm_qos = <&qos_hdcp0>;
++					#power-domain-cells = <0>;
++				};
++			};
++			power-domain@RK3588_PD_VO1 {
++				reg = <RK3588_PD_VO1>;
++				clocks = <&cru PCLK_VO1_ROOT>,
++					 <&cru PCLK_VO1_S_ROOT>,
++					 <&cru HCLK_VO1_S_ROOT>,
++					 <&cru HCLK_HDCP1>,
++					 <&cru ACLK_HDCP1>,
++					 <&cru ACLK_HDMIRX_ROOT>,
++					 <&cru HCLK_VO1USB_TOP_ROOT>;
++				pm_qos = <&qos_hdcp1>,
++					 <&qos_hdmirx>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_VI {
++				reg = <RK3588_PD_VI>;
++				clocks = <&cru HCLK_VI_ROOT>,
++					 <&cru PCLK_VI_ROOT>,
++					 <&cru HCLK_ISP0>,
++					 <&cru ACLK_ISP0>,
++					 <&cru HCLK_VICAP>,
++					 <&cru ACLK_VICAP>;
++				pm_qos = <&qos_isp0_mro>,
++					 <&qos_isp0_mwo>,
++					 <&qos_vicap_m0>,
++					 <&qos_vicap_m1>;
++				#address-cells = <1>;
++				#size-cells = <0>;
++				#power-domain-cells = <0>;
++
++				power-domain@RK3588_PD_ISP1 {
++					reg = <RK3588_PD_ISP1>;
++					clocks = <&cru HCLK_ISP1>,
++						 <&cru ACLK_ISP1>,
++						 <&cru HCLK_VI_ROOT>,
++						 <&cru PCLK_VI_ROOT>;
++					pm_qos = <&qos_isp1_mwo>,
++						 <&qos_isp1_mro>;
++					#power-domain-cells = <0>;
++				};
++				power-domain@RK3588_PD_FEC {
++					reg = <RK3588_PD_FEC>;
++					clocks = <&cru HCLK_FISHEYE0>,
++						 <&cru ACLK_FISHEYE0>,
++						 <&cru HCLK_FISHEYE1>,
++						 <&cru ACLK_FISHEYE1>,
++						 <&cru PCLK_VI_ROOT>;
++					pm_qos = <&qos_fisheye0>,
++						 <&qos_fisheye1>;
++					#power-domain-cells = <0>;
++				};
++			};
++			power-domain@RK3588_PD_RGA31 {
++				reg = <RK3588_PD_RGA31>;
++				clocks = <&cru HCLK_RGA3_1>,
++					 <&cru ACLK_RGA3_1>;
++				pm_qos = <&qos_rga3_1>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_USB {
++				reg = <RK3588_PD_USB>;
++				clocks = <&cru PCLK_PHP_ROOT>,
++					 <&cru ACLK_USB_ROOT>,
++					 <&cru HCLK_USB_ROOT>,
++					 <&cru HCLK_HOST0>,
++					 <&cru HCLK_HOST_ARB0>,
++					 <&cru HCLK_HOST1>,
++					 <&cru HCLK_HOST_ARB1>;
++				pm_qos = <&qos_usb3_0>,
++					 <&qos_usb3_1>,
++					 <&qos_usb2host_0>,
++					 <&qos_usb2host_1>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_GMAC {
++				reg = <RK3588_PD_GMAC>;
++				clocks = <&cru PCLK_PHP_ROOT>,
++					 <&cru ACLK_PCIE_ROOT>,
++					 <&cru ACLK_PHP_ROOT>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_PCIE {
++				reg = <RK3588_PD_PCIE>;
++				clocks = <&cru PCLK_PHP_ROOT>,
++					 <&cru ACLK_PCIE_ROOT>,
++					 <&cru ACLK_PHP_ROOT>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_SDIO {
++				reg = <RK3588_PD_SDIO>;
++				clocks = <&cru HCLK_SDIO>,
++					 <&cru HCLK_NVM_ROOT>;
++				pm_qos = <&qos_sdio>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_AUDIO {
++				reg = <RK3588_PD_AUDIO>;
++				clocks = <&cru HCLK_AUDIO_ROOT>,
++					 <&cru PCLK_AUDIO_ROOT>;
++				#power-domain-cells = <0>;
++			};
++			power-domain@RK3588_PD_SDMMC {
++				reg = <RK3588_PD_SDMMC>;
++				pm_qos = <&qos_sdmmc>;
++				#power-domain-cells = <0>;
++			};
++		};
++	};
++
++	qos_gpu_m0: qos@fdf35000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf35000 0x0 0x20>;
++	};
++
++	qos_gpu_m1: qos@fdf35200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf35200 0x0 0x20>;
++	};
++
++	qos_gpu_m2: qos@fdf35400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf35400 0x0 0x20>;
++	};
++
++	qos_gpu_m3: qos@fdf35600 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf35600 0x0 0x20>;
++	};
++
++	qos_rga3_1: qos@fdf36000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf36000 0x0 0x20>;
++	};
++
++	qos_sdio: qos@fdf39000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf39000 0x0 0x20>;
++	};
++
++	qos_sdmmc: qos@fdf3d800 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf3d800 0x0 0x20>;
++	};
++
++	qos_usb3_1: qos@fdf3e000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf3e000 0x0 0x20>;
++	};
++
++	qos_usb3_0: qos@fdf3e200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf3e200 0x0 0x20>;
++	};
++
++	qos_usb2host_0: qos@fdf3e400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf3e400 0x0 0x20>;
++	};
++
++	qos_usb2host_1: qos@fdf3e600 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf3e600 0x0 0x20>;
++	};
++
++	qos_fisheye0: qos@fdf40000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf40000 0x0 0x20>;
++	};
++
++	qos_fisheye1: qos@fdf40200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf40200 0x0 0x20>;
++	};
++
++	qos_isp0_mro: qos@fdf40400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf40400 0x0 0x20>;
++	};
++
++	qos_isp0_mwo: qos@fdf40500 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf40500 0x0 0x20>;
++	};
++
++	qos_vicap_m0: qos@fdf40600 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf40600 0x0 0x20>;
++	};
++
++	qos_vicap_m1: qos@fdf40800 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf40800 0x0 0x20>;
++	};
++
++	qos_isp1_mwo: qos@fdf41000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf41000 0x0 0x20>;
++	};
++
++	qos_isp1_mro: qos@fdf41100 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf41100 0x0 0x20>;
++	};
++
++	qos_rkvenc0_m0ro: qos@fdf60000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf60000 0x0 0x20>;
++	};
++
++	qos_rkvenc0_m1ro: qos@fdf60200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf60200 0x0 0x20>;
++	};
++
++	qos_rkvenc0_m2wo: qos@fdf60400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf60400 0x0 0x20>;
++	};
++
++	qos_rkvenc1_m0ro: qos@fdf61000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf61000 0x0 0x20>;
++	};
++
++	qos_rkvenc1_m1ro: qos@fdf61200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf61200 0x0 0x20>;
++	};
++
++	qos_rkvenc1_m2wo: qos@fdf61400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf61400 0x0 0x20>;
++	};
++
++	qos_rkvdec0: qos@fdf62000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf62000 0x0 0x20>;
++	};
++
++	qos_rkvdec1: qos@fdf63000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf63000 0x0 0x20>;
++	};
++
++	qos_av1: qos@fdf64000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf64000 0x0 0x20>;
++	};
++
++	qos_iep: qos@fdf66000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66000 0x0 0x20>;
++	};
++
++	qos_jpeg_dec: qos@fdf66200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66200 0x0 0x20>;
++	};
++
++	qos_jpeg_enc0: qos@fdf66400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66400 0x0 0x20>;
++	};
++
++	qos_jpeg_enc1: qos@fdf66600 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66600 0x0 0x20>;
++	};
++
++	qos_jpeg_enc2: qos@fdf66800 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66800 0x0 0x20>;
++	};
++
++	qos_jpeg_enc3: qos@fdf66a00 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66a00 0x0 0x20>;
++	};
++
++	qos_rga2_mro: qos@fdf66c00 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66c00 0x0 0x20>;
++	};
++
++	qos_rga2_mwo: qos@fdf66e00 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf66e00 0x0 0x20>;
++	};
++
++	qos_rga3_0: qos@fdf67000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf67000 0x0 0x20>;
++	};
++
++	qos_vdpu: qos@fdf67200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf67200 0x0 0x20>;
++	};
++
++	qos_npu1: qos@fdf70000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf70000 0x0 0x20>;
++	};
++
++	qos_npu2: qos@fdf71000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf71000 0x0 0x20>;
++	};
++
++	qos_npu0_mwr: qos@fdf72000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf72000 0x0 0x20>;
++	};
++
++	qos_npu0_mro: qos@fdf72200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf72200 0x0 0x20>;
++	};
++
++	qos_mcu_npu: qos@fdf72400 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf72400 0x0 0x20>;
++	};
++
++	qos_hdcp0: qos@fdf80000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf80000 0x0 0x20>;
++	};
++
++	qos_hdcp1: qos@fdf81000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf81000 0x0 0x20>;
++	};
++
++	qos_hdmirx: qos@fdf81200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf81200 0x0 0x20>;
++	};
++
++	qos_vop_m0: qos@fdf82000 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf82000 0x0 0x20>;
++	};
++
++	qos_vop_m1: qos@fdf82200 {
++		compatible = "rockchip,rk3588-qos", "syscon";
++		reg = <0x0 0xfdf82200 0x0 0x20>;
++	};
++
++	gmac1: ethernet@fe1c0000 {
++		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
++		reg = <0x0 0xfe1c0000 0x0 0x10000>;
++		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "macirq", "eth_wake_irq";
++		clocks = <&cru CLK_GMAC_125M>, <&cru CLK_GMAC_50M>,
++			 <&cru PCLK_GMAC1>, <&cru ACLK_GMAC1>,
++			 <&cru CLK_GMAC1_PTP_REF>;
++		clock-names = "stmmaceth", "clk_mac_ref",
++			      "pclk_mac", "aclk_mac",
++			      "ptp_ref";
++		power-domains = <&power RK3588_PD_GMAC>;
++		resets = <&cru SRST_A_GMAC1>;
++		reset-names = "stmmaceth";
++		rockchip,grf = <&sys_grf>;
++		rockchip,php-grf = <&php_grf>;
++		snps,axi-config = <&gmac1_stmmac_axi_setup>;
++		snps,mixed-burst;
++		snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
++		snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
++		snps,tso;
++		status = "disabled";
++
++		mdio1: mdio {
++			compatible = "snps,dwmac-mdio";
++			#address-cells = <0x1>;
++			#size-cells = <0x0>;
++		};
++
++		gmac1_stmmac_axi_setup: stmmac-axi-config {
++			snps,blen = <0 0 0 0 16 8 4>;
++			snps,wr_osr_lmt = <4>;
++			snps,rd_osr_lmt = <8>;
++		};
++
++		gmac1_mtl_rx_setup: rx-queues-config {
++			snps,rx-queues-to-use = <2>;
++			queue0 {};
++			queue1 {};
++		};
++
++		gmac1_mtl_tx_setup: tx-queues-config {
++			snps,tx-queues-to-use = <2>;
++			queue0 {};
++			queue1 {};
++		};
++	};
++
++	sdhci: mmc@fe2e0000 {
++		compatible = "rockchip,rk3588-dwcmshc";
++		reg = <0x0 0xfe2e0000 0x0 0x10000>;
++		interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH 0>;
++		assigned-clocks = <&cru BCLK_EMMC>, <&cru TMCLK_EMMC>, <&cru CCLK_EMMC>;
++		assigned-clock-rates = <200000000>, <24000000>, <200000000>;
++		clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
++			 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
++			 <&cru TMCLK_EMMC>;
++		clock-names = "core", "bus", "axi", "block", "timer";
++		max-frequency = <200000000>;
++		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
++			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
++			 <&cru SRST_T_EMMC>;
++		reset-names = "core", "bus", "axi", "block", "timer";
++		status = "disabled";
++	};
++
++	gic: interrupt-controller@fe600000 {
++		compatible = "arm,gic-v3";
++		reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
++		      <0x0 0xfe680000 0 0x100000>; /* GICR */
++		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-controller;
++		mbi-alias = <0x0 0xfe610000>;
++		mbi-ranges = <424 56>;
++		msi-controller;
++		#interrupt-cells = <4>;
++
++		ppi-partitions {
++			ppi_partition0: interrupt-partition-0 {
++				affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
++			};
++
++			ppi_partition1: interrupt-partition-1 {
++				affinity = <&cpu_b0 &cpu_b1 &cpu_b2 &cpu_b3>;
++			};
++		};
++	};
++
++	dmac0: dma-controller@fea10000 {
++		compatible = "arm,pl330", "arm,primecell";
++		reg = <0x0 0xfea10000 0x0 0x4000>;
++		interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH 0>;
++		arm,pl330-periph-burst;
++		clocks = <&cru ACLK_DMAC0>;
++		clock-names = "apb_pclk";
++		#dma-cells = <1>;
++	};
++
++	dmac1: dma-controller@fea30000 {
++		compatible = "arm,pl330", "arm,primecell";
++		reg = <0x0 0xfea30000 0x0 0x4000>;
++		interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH 0>;
++		arm,pl330-periph-burst;
++		clocks = <&cru ACLK_DMAC1>;
++		clock-names = "apb_pclk";
++		#dma-cells = <1>;
++	};
++
++	i2c1: i2c@fea90000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfea90000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c1m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c2: i2c@feaa0000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfeaa0000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c2m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c3: i2c@feab0000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfeab0000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c3m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c4: i2c@feac0000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfeac0000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c4m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c5: i2c@fead0000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfead0000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c5m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	spi0: spi@feb00000 {
++		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
++		reg = <0x0 0xfeb00000 0x0 0x1000>;
++		interrupts = <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
++		clock-names = "spiclk", "apb_pclk";
++		dmas = <&dmac0 14>, <&dmac0 15>;
++		dma-names = "tx", "rx";
++		num-cs = <2>;
++		pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	spi1: spi@feb10000 {
++		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
++		reg = <0x0 0xfeb10000 0x0 0x1000>;
++		interrupts = <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
++		clock-names = "spiclk", "apb_pclk";
++		dmas = <&dmac0 16>, <&dmac0 17>;
++		dma-names = "tx", "rx";
++		num-cs = <2>;
++		pinctrl-0 = <&spi1m1_cs0 &spi1m1_cs1 &spi1m1_pins>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	spi2: spi@feb20000 {
++		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
++		reg = <0x0 0xfeb20000 0x0 0x1000>;
++		interrupts = <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
++		clock-names = "spiclk", "apb_pclk";
++		dmas = <&dmac1 15>, <&dmac1 16>;
++		dma-names = "tx", "rx";
++		num-cs = <2>;
++		pinctrl-0 = <&spi2m2_cs0 &spi2m2_cs1 &spi2m2_pins>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	spi3: spi@feb30000 {
++		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
++		reg = <0x0 0xfeb30000 0x0 0x1000>;
++		interrupts = <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
++		clock-names = "spiclk", "apb_pclk";
++		dmas = <&dmac1 17>, <&dmac1 18>;
++		dma-names = "tx", "rx";
++		num-cs = <2>;
++		pinctrl-0 = <&spi3m1_cs0 &spi3m1_cs1 &spi3m1_pins>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	uart1: serial@feb40000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeb40000 0x0 0x100>;
++		interrupts = <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac0 8>, <&dmac0 9>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart1m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart2: serial@feb50000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeb50000 0x0 0x100>;
++		interrupts = <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac0 10>, <&dmac0 11>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart2m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart3: serial@feb60000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeb60000 0x0 0x100>;
++		interrupts = <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac0 12>, <&dmac0 13>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart3m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart4: serial@feb70000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeb70000 0x0 0x100>;
++		interrupts = <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac1 9>, <&dmac1 10>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart4m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart5: serial@feb80000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeb80000 0x0 0x100>;
++		interrupts = <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac1 11>, <&dmac1 12>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart5m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart6: serial@feb90000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeb90000 0x0 0x100>;
++		interrupts = <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac1 13>, <&dmac1 14>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart6m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart7: serial@feba0000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfeba0000 0x0 0x100>;
++		interrupts = <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac2 7>, <&dmac2 8>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart7m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart8: serial@febb0000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfebb0000 0x0 0x100>;
++		interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac2 9>, <&dmac2 10>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart8m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	uart9: serial@febc0000 {
++		compatible = "rockchip,rk3588-uart", "snps,dw-apb-uart";
++		reg = <0x0 0xfebc0000 0x0 0x100>;
++		interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
++		clock-names = "baudclk", "apb_pclk";
++		dmas = <&dmac2 11>, <&dmac2 12>;
++		dma-names = "tx", "rx";
++		pinctrl-0 = <&uart9m1_xfer>;
++		pinctrl-names = "default";
++		reg-io-width = <4>;
++		reg-shift = <2>;
++		status = "disabled";
++	};
++
++	pwm4: pwm@febd0000 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebd0000 0x0 0x10>;
++		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm4m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm5: pwm@febd0010 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebd0010 0x0 0x10>;
++		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm5m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm6: pwm@febd0020 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebd0020 0x0 0x10>;
++		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm6m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm7: pwm@febd0030 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebd0030 0x0 0x10>;
++		clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm7m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm8: pwm@febe0000 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebe0000 0x0 0x10>;
++		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm8m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm9: pwm@febe0010 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebe0010 0x0 0x10>;
++		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm9m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm10: pwm@febe0020 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebe0020 0x0 0x10>;
++		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm10m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm11: pwm@febe0030 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebe0030 0x0 0x10>;
++		clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm11m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm12: pwm@febf0000 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebf0000 0x0 0x10>;
++		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm12m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm13: pwm@febf0010 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebf0010 0x0 0x10>;
++		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm13m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm14: pwm@febf0020 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebf0020 0x0 0x10>;
++		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm14m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	pwm15: pwm@febf0030 {
++		compatible = "rockchip,rk3588-pwm", "rockchip,rk3328-pwm";
++		reg = <0x0 0xfebf0030 0x0 0x10>;
++		clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
++		clock-names = "pwm", "pclk";
++		pinctrl-0 = <&pwm15m0_pins>;
++		pinctrl-names = "default";
++		#pwm-cells = <3>;
++		status = "disabled";
++	};
++
++	i2c6: i2c@fec80000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfec80000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C6>, <&cru PCLK_I2C6>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c6m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c7: i2c@fec90000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfec90000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C7>, <&cru PCLK_I2C7>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c7m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	i2c8: i2c@feca0000 {
++		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
++		reg = <0x0 0xfeca0000 0x0 0x1000>;
++		clocks = <&cru CLK_I2C8>, <&cru PCLK_I2C8>;
++		clock-names = "i2c", "pclk";
++		interrupts = <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH 0>;
++		pinctrl-0 = <&i2c8m0_xfer>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	spi4: spi@fecb0000 {
++		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
++		reg = <0x0 0xfecb0000 0x0 0x1000>;
++		interrupts = <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_SPI4>, <&cru PCLK_SPI4>;
++		clock-names = "spiclk", "apb_pclk";
++		dmas = <&dmac2 13>, <&dmac2 14>;
++		dma-names = "tx", "rx";
++		num-cs = <2>;
++		pinctrl-0 = <&spi4m0_cs0 &spi4m0_cs1 &spi4m0_pins>;
++		pinctrl-names = "default";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
++	dmac2: dma-controller@fed10000 {
++		compatible = "arm,pl330", "arm,primecell";
++		reg = <0x0 0xfed10000 0x0 0x4000>;
++		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH 0>;
++		arm,pl330-periph-burst;
++		clocks = <&cru ACLK_DMAC2>;
++		clock-names = "apb_pclk";
++		#dma-cells = <1>;
++	};
++
++	system_sram2: sram@ff001000 {
++		compatible = "mmio-sram";
++		reg = <0x0 0xff001000 0x0 0xef000>;
++		ranges = <0x0 0x0 0xff001000 0xef000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++	};
++
++	pinctrl: pinctrl {
++		compatible = "rockchip,rk3588-pinctrl";
++		ranges;
++		rockchip,grf = <&ioc>;
++		#address-cells = <2>;
++		#size-cells = <2>;
++
++		gpio0: gpio@fd8a0000 {
++			compatible = "rockchip,gpio-bank";
++			reg = <0x0 0xfd8a0000 0x0 0x100>;
++			interrupts = <GIC_SPI 277 IRQ_TYPE_LEVEL_HIGH 0>;
++			clocks = <&cru PCLK_GPIO0>, <&cru DBCLK_GPIO0>;
++			gpio-controller;
++			gpio-ranges = <&pinctrl 0 0 32>;
++			interrupt-controller;
++			#gpio-cells = <2>;
++			#interrupt-cells = <2>;
++		};
++
++		gpio1: gpio@fec20000 {
++			compatible = "rockchip,gpio-bank";
++			reg = <0x0 0xfec20000 0x0 0x100>;
++			interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH 0>;
++			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
++			gpio-controller;
++			gpio-ranges = <&pinctrl 0 32 32>;
++			interrupt-controller;
++			#gpio-cells = <2>;
++			#interrupt-cells = <2>;
++		};
++
++		gpio2: gpio@fec30000 {
++			compatible = "rockchip,gpio-bank";
++			reg = <0x0 0xfec30000 0x0 0x100>;
++			interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH 0>;
++			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
++			gpio-controller;
++			gpio-ranges = <&pinctrl 0 64 32>;
++			interrupt-controller;
++			#gpio-cells = <2>;
++			#interrupt-cells = <2>;
++		};
++
++		gpio3: gpio@fec40000 {
++			compatible = "rockchip,gpio-bank";
++			reg = <0x0 0xfec40000 0x0 0x100>;
++			interrupts = <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH 0>;
++			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
++			gpio-controller;
++			gpio-ranges = <&pinctrl 0 96 32>;
++			interrupt-controller;
++			#gpio-cells = <2>;
++			#interrupt-cells = <2>;
++		};
++
++		gpio4: gpio@fec50000 {
++			compatible = "rockchip,gpio-bank";
++			reg = <0x0 0xfec50000 0x0 0x100>;
++			interrupts = <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH 0>;
++			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
++			gpio-controller;
++			gpio-ranges = <&pinctrl 0 128 32>;
++			interrupt-controller;
++			#gpio-cells = <2>;
++			#interrupt-cells = <2>;
++		};
++	};
++};
++
++#include "rk3588s-pinctrl.dtsi"
diff --git a/target/linux/rockchip/patches-6.1/099-arm64-dts-rockchip-Add-rk3588-evb1-board.patch b/target/linux/rockchip/patches-6.1/099-arm64-dts-rockchip-Add-rk3588-evb1-board.patch
new file mode 100644
index 00000000000..abcba2a2826
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/099-arm64-dts-rockchip-Add-rk3588-evb1-board.patch
@@ -0,0 +1,163 @@
+From be1bd63277dcc65665eed8599d58099e1dc541f1 Mon Sep 17 00:00:00 2001
+From: Kever Yang <kever.yang@rock-chips.com>
+Date: Mon, 9 Jan 2023 16:57:59 +0100
+Subject: [PATCH 099/383] arm64: dts: rockchip: Add rk3588-evb1 board
+
+Add board file for the RK3588 evaluation board. While the hardware
+offers plenty of peripherals and connectivity this basic implementation
+just handles things required to successfully boot Linux from eMMC,
+connect via UART or Ethernet.
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+[rebase, update commit message, use EVB1 for SoC bringup]
+Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230109155801.51642-6-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 129 ++++++++++++++++++
+ 2 files changed, 130 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -86,3 +86,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -0,0 +1,129 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ *
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3588.dtsi"
++
++/ {
++	model = "Rockchip RK3588 EVB1 V10 Board";
++	compatible = "rockchip,rk3588-evb1-v10", "rockchip,rk3588";
++
++	aliases {
++		mmc0 = &sdhci;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		power-supply = <&vcc12v_dcin>;
++		pwms = <&pwm2 0 25000 0>;
++	};
++
++	vcc12v_dcin: vcc12v-dcin-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc12v_dcin>;
++	};
++};
++
++&gmac0 {
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy>;
++	phy-mode = "rgmii-rxid";
++	pinctrl-0 = <&gmac0_miim
++		     &gmac0_tx_bus2
++		     &gmac0_rx_bus2
++		     &gmac0_rgmii_clk
++		     &gmac0_rgmii_bus>;
++	pinctrl-names = "default";
++	rx_delay = <0x00>;
++	tx_delay = <0x43>;
++	status = "okay";
++};
++
++&i2c2 {
++	status = "okay";
++
++	hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-output-names = "hym8563";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hym8563_int>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PD4 IRQ_TYPE_LEVEL_LOW>;
++		wakeup-source;
++	};
++};
++
++&mdio0 {
++	rgmii_phy: ethernet-phy@1 {
++		/* RTL8211F */
++		compatible = "ethernet-phy-id001c.c916";
++		reg = <0x1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&rtl8211f_rst>;
++		reset-assert-us = <20000>;
++		reset-deassert-us = <100000>;
++		reset-gpios = <&gpio4 RK_PB3 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&pinctrl {
++	rtl8211f {
++		rtl8211f_rst: rtl8211f-rst {
++			rockchip,pins = <4 RK_PB3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++	};
++
++	hym8563 {
++		hym8563_int: hym8563-int {
++			rockchip,pins = <0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&pwm2 {
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	max-frequency = <200000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/100-arm64-dts-rockchip-Add-rock-5a-board.patch b/target/linux/rockchip/patches-6.1/100-arm64-dts-rockchip-Add-rock-5a-board.patch
new file mode 100644
index 00000000000..73f697548bf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/100-arm64-dts-rockchip-Add-rock-5a-board.patch
@@ -0,0 +1,105 @@
+From 70746bf047e0ece5084d1227d6b2db64764d5ea1 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 9 Jan 2023 16:58:00 +0100
+Subject: [PATCH 100/383] arm64: dts: rockchip: Add rock-5a board
+
+Add board file for the RK3588s Rock 5A board. While the hardware
+offers plenty of peripherals and connectivity this basic implementation
+just handles things required to access eMMC, UART and Ethernet (i.e.
+enough to successfully boot Linux).
+
+Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
+Tested-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230109155801.51642-7-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../boot/dts/rockchip/rk3588s-rock-5a.dts     | 73 +++++++++++++++++++
+ 2 files changed, 74 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -87,3 +87,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -0,0 +1,73 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3588s.dtsi"
++
++/ {
++	model = "Radxa ROCK 5 Model A";
++	compatible = "radxa,rock-5a", "rockchip,rk3588s";
++
++	aliases {
++		mmc1 = &sdhci;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++};
++
++&gmac1 {
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy1>;
++	phy-mode = "rgmii-rxid";
++	pinctrl-0 = <&gmac1_miim
++		     &gmac1_tx_bus2
++		     &gmac1_rx_bus2
++		     &gmac1_rgmii_clk
++		     &gmac1_rgmii_bus>;
++	pinctrl-names = "default";
++	tx_delay = <0x3a>;
++	status = "okay";
++};
++
++&mdio1 {
++	rgmii_phy1: ethernet-phy@1 {
++		/* RTL8211F */
++		compatible = "ethernet-phy-id001c.c916";
++		reg = <0x1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&rtl8211f_rst>;
++		reset-assert-us = <20000>;
++		reset-deassert-us = <100000>;
++		reset-gpios = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&pinctrl {
++	rtl8211f {
++		rtl8211f_rst: rtl8211f-rst {
++			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++	};
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	max-frequency = <200000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
deleted file mode 100644
index 05112451923..00000000000
--- a/target/linux/rockchip/patches-6.1/100-rockchip-use-system-LED-for-OpenWrt.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 6731d2c9039fbe1ecf21915eab3acee0a999508a Mon Sep 17 00:00:00 2001
-From: David Bauer <mail@david-bauer.net>
-Date: Fri, 10 Jul 2020 21:38:20 +0200
-Subject: [PATCH] rockchip: use system LED for OpenWrt
-
-Use the SYS LED on the casing for showing system status.
-
-This patch is kept separate from the NanoPi R2S support patch, as i plan
-on submitting the device support upstream.
-
-Signed-off-by: David Bauer <mail@david-bauer.net>
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 9 ++++++++-
- 1 file changed, 8 insertions(+), 1 deletion(-)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -18,6 +18,13 @@
- 		mmc0 = &sdmmc;
- 	};
- 
-+	aliases {
-+		led-boot = &sys_led;
-+		led-failsafe = &sys_led;
-+		led-running = &sys_led;
-+		led-upgrade = &sys_led;
-+	};
-+
- 	chosen {
- 		stdout-path = "serial2:1500000n8";
- 	};
---- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -19,6 +19,13 @@
- 	model = "FriendlyElec NanoPi R4S";
- 	compatible = "friendlyarm,nanopi-r4s", "rockchip,rk3399";
- 
-+	aliases {
-+		led-boot = &sys_led;
-+		led-failsafe = &sys_led;
-+		led-running = &sys_led;
-+		led-upgrade = &sys_led;
-+	};
-+
- 	/delete-node/ display-subsystem;
- 
- 	gpio-leds {
diff --git a/target/linux/rockchip/patches-6.1/101-arm64-dts-rockchip-Add-rock-5b-board.patch b/target/linux/rockchip/patches-6.1/101-arm64-dts-rockchip-Add-rock-5b-board.patch
new file mode 100644
index 00000000000..021e72d16dd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/101-arm64-dts-rockchip-Add-rock-5b-board.patch
@@ -0,0 +1,79 @@
+From 17668bfb96ee2d1cb98c9e30d051cd7f55659d7e Mon Sep 17 00:00:00 2001
+From: Christopher Obbard <chris.obbard@collabora.com>
+Date: Mon, 9 Jan 2023 16:58:01 +0100
+Subject: [PATCH 101/383] arm64: dts: rockchip: Add rock-5b board
+
+Add board file for the RK3588 Rock 5B board. This is a basic
+implementation which just brings up the eMMC and UART which is
+enough to successfully boot Linux.
+
+The ethernet controller is connected via PCIe so support will
+come in a follow-up patch.
+
+Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
+Reviewed-by: Michael Riesch <michael.riesch@wolfvision.net>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230109155801.51642-8-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 44 +++++++++++++++++++
+ 2 files changed, 45 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -87,4 +87,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -0,0 +1,44 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include "rk3588.dtsi"
++
++/ {
++	model = "Radxa ROCK 5 Model B";
++	compatible = "radxa,rock-5b", "rockchip,rk3588";
++
++	aliases {
++		mmc1 = &sdhci;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	max-frequency = <200000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/102-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5a.patch b/target/linux/rockchip/patches-6.1/102-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5a.patch
new file mode 100644
index 00000000000..44c80215af0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/102-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5a.patch
@@ -0,0 +1,29 @@
+From 4d7fef3e2b8cc2be36e61b2cf8628e7cb39b0331 Mon Sep 17 00:00:00 2001
+From: Christopher Obbard <chris.obbard@collabora.com>
+Date: Tue, 10 Jan 2023 19:53:50 +0000
+Subject: [PATCH 102/383] arm64: dts: rockchip: Update sdhci alias for rock-5a
+
+In the previous version, the sdhci alias was set to mmc1: an artifact
+leftover from the port from vendor kernel. Update the alias to mmc0 to
+match the device's boot order.
+
+Fixes: a4a8f1afb360 ("arm64: dts: rockchip: Add rock-5a board")
+Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
+Link: https://lore.kernel.org/r/20230110195352.272360-2-chris.obbard@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -11,7 +11,7 @@
+ 	compatible = "radxa,rock-5a", "rockchip,rk3588s";
+ 
+ 	aliases {
+-		mmc1 = &sdhci;
++		mmc0 = &sdhci;
+ 		serial2 = &uart2;
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/103-arm64-dts-rockchip-Remove-empty-line-from-rock-5a.patch b/target/linux/rockchip/patches-6.1/103-arm64-dts-rockchip-Remove-empty-line-from-rock-5a.patch
new file mode 100644
index 00000000000..6fb94a3b43d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/103-arm64-dts-rockchip-Remove-empty-line-from-rock-5a.patch
@@ -0,0 +1,26 @@
+From 67dd5f396038773b9034ce374ce3a60562069fd1 Mon Sep 17 00:00:00 2001
+From: Christopher Obbard <chris.obbard@collabora.com>
+Date: Tue, 10 Jan 2023 19:53:51 +0000
+Subject: [PATCH 103/383] arm64: dts: rockchip: Remove empty line from rock-5a
+
+There is a line which is empty. Remove it.
+
+Fixes: a4a8f1afb360 ("arm64: dts: rockchip: Add rock-5a board")
+Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
+Link: https://lore.kernel.org/r/20230110195352.272360-3-chris.obbard@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -52,7 +52,6 @@
+ 		rtl8211f_rst: rtl8211f-rst {
+ 			rockchip,pins = <3 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+-
+ 	};
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/104-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5b.patch b/target/linux/rockchip/patches-6.1/104-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5b.patch
new file mode 100644
index 00000000000..43a76bf762b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/104-arm64-dts-rockchip-Update-sdhci-alias-for-rock-5b.patch
@@ -0,0 +1,29 @@
+From e30c39a20633f13637c088a8767e3dd008ff6ff0 Mon Sep 17 00:00:00 2001
+From: Christopher Obbard <chris.obbard@collabora.com>
+Date: Tue, 10 Jan 2023 19:53:52 +0000
+Subject: [PATCH 104/383] arm64: dts: rockchip: Update sdhci alias for rock-5b
+
+In the previous version, the sdhci alias was set to mmc1: an artifact
+leftover from the port from vendor kernel. Update the alias to mmc0 to
+match the device's boot order.
+
+Fixes: 6fb2d1549786 ("arm64: dts: rockchip: Add rock-5b board")
+Signed-off-by: Christopher Obbard <chris.obbard@collabora.com>
+Link: https://lore.kernel.org/r/20230110195352.272360-4-chris.obbard@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -9,7 +9,7 @@
+ 	compatible = "radxa,rock-5b", "rockchip,rk3588";
+ 
+ 	aliases {
+-		mmc1 = &sdhci;
++		mmc0 = &sdhci;
+ 		serial2 = &uart2;
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/006-v6.3-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k.patch b/target/linux/rockchip/patches-6.1/105-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k-on-rk3.patch
similarity index 84%
rename from target/linux/rockchip/patches-6.1/006-v6.3-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k.patch
rename to target/linux/rockchip/patches-6.1/105-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k-on-rk3.patch
index bf7001572a1..69a7b3bf969 100644
--- a/target/linux/rockchip/patches-6.1/006-v6.3-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k.patch
+++ b/target/linux/rockchip/patches-6.1/105-arm64-dts-rockchip-assign-rate-to-clk_rtc_32k-on-rk3.patch
@@ -1,7 +1,8 @@
-From 64b69474edf3b885c19a89bb165f978ba1b4be00 Mon Sep 17 00:00:00 2001
+From 8b5c6876e115144379c646c3c4d4beb86d86adba Mon Sep 17 00:00:00 2001
 From: Jonas Karlman <jonas@kwiboo.se>
 Date: Tue, 10 Jan 2023 22:55:50 +0000
-Subject: [PATCH] arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x
+Subject: [PATCH 105/383] arm64: dts: rockchip: assign rate to clk_rtc_32k on
+ rk356x
 
 clk_rtc_32k and its child clock clk_hdmi_cec detauls to a rate of 24 MHz
 and not to 32 kHz on RK356x.
@@ -12,6 +13,7 @@ to clk_rtc32k_frac.
 Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
 Link: https://lore.kernel.org/r/20230110225547.1563119-2-jonas@kwiboo.se
 Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++--
  1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/105-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-6.1/105-mmc-core-set-initial-signal-voltage-on-power-off.patch
deleted file mode 100644
index d462899007c..00000000000
--- a/target/linux/rockchip/patches-6.1/105-mmc-core-set-initial-signal-voltage-on-power-off.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 20 Feb 2019 07:38:34 +0000
-Subject: [PATCH] mmc: core: set initial signal voltage on power off
-
-Some boards have SD card connectors where the power rail cannot be switched
-off by the driver. If the card has not been power cycled, it may still be
-using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
-will fail to boot from a UHS card that continue to use 1.8V signaling.
-
-Set initial signal voltage in mmc_power_off() to allow re-boot to function.
-
-This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
-same issue have been seen on some Rockchip RK3399 boards.
-
-I am sending this as a RFC because I have no insights into SD/MMC subsystem,
-this change fix a re-boot issue on my boards and does not break emmc/sdio.
-Is this an acceptable workaround? Any advice is appreciated.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/mmc/core/core.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/mmc/core/core.c
-+++ b/drivers/mmc/core/core.c
-@@ -1371,6 +1371,8 @@ void mmc_power_off(struct mmc_host *host
- 
- 	mmc_pwrseq_power_off(host);
- 
-+	mmc_set_initial_signal_voltage(host);
-+
- 	host->ios.clock = 0;
- 	host->ios.vdd = 0;
- 
diff --git a/target/linux/rockchip/patches-6.1/106-arm64-dts-rockchip-fix-hdmi-cec-on-rock-3a.patch b/target/linux/rockchip/patches-6.1/106-arm64-dts-rockchip-fix-hdmi-cec-on-rock-3a.patch
new file mode 100644
index 00000000000..20b4e30738e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/106-arm64-dts-rockchip-fix-hdmi-cec-on-rock-3a.patch
@@ -0,0 +1,33 @@
+From 6b7d515e904851a2c7939bd08740eb0359bc89d0 Mon Sep 17 00:00:00 2001
+From: Jonas Karlman <jonas@kwiboo.se>
+Date: Tue, 10 Jan 2023 22:55:59 +0000
+Subject: [PATCH 106/383] arm64: dts: rockchip: fix hdmi cec on rock-3a
+
+HDMI CEC is configured to select HDMITX_CEC_M0 function of GPIO0_C7 by
+default in rk356x.dtsi. On Radxa ROCK 3 Model A it is routed to
+HDMITX_CEC_M1 according to board schematic [1].
+
+Fix HDMI CEC by overriding pinctrl in hdmi node to select HDMITX_CEC_M1.
+
+[1] https://dl.radxa.com/rock3/docs/hw/3a/ROCK-3A-V1.3-SCH.pdf
+
+Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
+Link: https://lore.kernel.org/r/20230110225547.1563119-3-jonas@kwiboo.se
+[added pinctrl-names duplicate]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -279,6 +279,8 @@
+ &hdmi {
+ 	avdd-0v9-supply = <&vdda0v9_image>;
+ 	avdd-1v8-supply = <&vcca1v8_image>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm1_cec>;
+ 	status = "okay";
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-A-S.patch b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-A-S.patch
new file mode 100644
index 00000000000..89a6f5c01ac
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/107-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-A-S.patch
@@ -0,0 +1,68 @@
+From 83352781760580b7e638e7a4556a27f56a37832f Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 10 Jan 2023 19:16:57 +0530
+Subject: [PATCH 107/383] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model
+ A SoM
+
+Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
+based on Rockchip RK3588 from Edgeble AI.
+
+General features:
+- Rockchip RK3588
+- up to 32GB LPDDR4x
+- up to 128GB eMMC
+- 2x MIPI CSI2 FPC
+
+On module WiFi6/BT5 is available in the following Neu6 variants.
+
+Neu6 needs to mount on top of associated Edgeble IO boards for
+creating complete platform solutions.
+
+Enable eMMC for now to boot Linux successfully.
+
+Add support for Edgeble Neu6 Model A SoM.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230110134658.820691-2-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3588-edgeble-neu6a.dtsi    | 32 +++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a.dtsi
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
++ */
++
++/ {
++	compatible = "edgeble,neural-compute-module-6a", "rockchip,rk3588";
++
++	aliases {
++		mmc0 = &sdhci;
++	};
++
++	vcc12v_dcin: vcc12v-dcin-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	max-frequency = <200000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch b/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
deleted file mode 100644
index 9acefd0939b..00000000000
--- a/target/linux/rockchip/patches-6.1/107-mmc-core-set-initial-signal-voltage-on-power-off.patch
+++ /dev/null
@@ -1,35 +0,0 @@
-From 0d329112c709d6cfedf0fffb19f0cc6b19043f6b Mon Sep 17 00:00:00 2001
-From: Jonas Karlman <jonas@kwiboo.se>
-Date: Wed, 20 Feb 2019 07:38:34 +0000
-Subject: [PATCH] mmc: core: set initial signal voltage on power off
-
-Some boards have SD card connectors where the power rail cannot be switched
-off by the driver. If the card has not been power cycled, it may still be
-using 1.8V signaling after a warm re-boot. Bootroms expecting 3.3V signaling
-will fail to boot from a UHS card that continue to use 1.8V signaling.
-
-Set initial signal voltage in mmc_power_off() to allow re-boot to function.
-
-This fixes re-boot with UHS cards on Asus Tinker Board (Rockchip RK3288),
-same issue have been seen on some Rockchip RK3399 boards.
-
-I am sending this as a RFC because I have no insights into SD/MMC subsystem,
-this change fix a re-boot issue on my boards and does not break emmc/sdio.
-Is this an acceptable workaround? Any advice is appreciated.
-
-Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
----
- drivers/mmc/core/core.c | 2 ++
- 1 file changed, 2 insertions(+)
-
---- a/drivers/mmc/core/core.c
-+++ b/drivers/mmc/core/core.c
-@@ -1373,6 +1373,8 @@ void mmc_power_off(struct mmc_host *host
- 
- 	mmc_set_initial_signal_voltage(host);
- 
-+	mmc_set_initial_signal_voltage(host);
-+
- 	host->ios.clock = 0;
- 	host->ios.vdd = 0;
- 
diff --git a/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-A-I.patch b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-A-I.patch
new file mode 100644
index 00000000000..6898877cbe1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/108-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-A-I.patch
@@ -0,0 +1,68 @@
+From 597824e3fa45fc2ed527667c07d01c3dc1863f02 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 10 Jan 2023 19:16:58 +0530
+Subject: [PATCH 108/383] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model
+ A IO
+
+Neural Compute Module 6(Neu6) IO board is an industrial form factor
+ready-to-use IO board from Edgeble AI.
+
+IO board offers plenty of peripherals and connectivity options and
+this patch enables basic eMMC and UART which is enough to successfully
+boot Linux.
+
+Neu6 needs to mount on top of this IO board in order to create a
+complete Edgeble Neural Compute Module 6(Neu6) IO platform.
+
+Add support for Edgeble Neu6 Model A IO Board.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230110134658.820691-3-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../dts/rockchip/rk3588-edgeble-neu6a-io.dts  | 27 +++++++++++++++++++
+ 2 files changed, 28 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6a-io.dts
+@@ -0,0 +1,27 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
++ */
++
++/dts-v1/;
++#include "rk3588.dtsi"
++#include "rk3588-edgeble-neu6a.dtsi"
++
++/ {
++	model = "Edgeble Neu6A IO Board";
++	compatible = "edgeble,neural-compute-module-6a-io",
++		     "edgeble,neural-compute-module-6a", "rockchip,rk3588";
++
++	aliases {
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-add-io-domain-setting-to-rk3566-b.patch b/target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-add-io-domain-setting-to-rk3566-b.patch
new file mode 100644
index 00000000000..a0cd404ef5d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/109-arm64-dts-rockchip-add-io-domain-setting-to-rk3566-b.patch
@@ -0,0 +1,38 @@
+From c25657a6a9546070671f9f7b8ed7ceb353e3a35c Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@163.com>
+Date: Thu, 29 Dec 2022 19:50:43 +0800
+Subject: [PATCH 109/383] arm64: dts: rockchip: add io domain setting to
+ rk3566-box-demo
+
+Add the missing pmu_io_domains setting, the gmac can't work well
+without this.
+
+Fixes: 2e0537b16b25 ("arm64: dts: rockchip: Add dts for rockchip rk3566 box demo board")
+Signed-off-by: Andy Yan <andyshrk@163.com>
+Link: https://lore.kernel.org/r/20221229115043.3899733-1-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+@@ -353,6 +353,17 @@
+ 	};
+ };
+ 
++&pmu_io_domains {
++	pmuio2-supply = <&vcc_3v3>;
++	vccio1-supply = <&vcc_3v3>;
++	vccio3-supply = <&vcc_3v3>;
++	vccio4-supply = <&vcca_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcca_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
+ &pwm0 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Enable-wifi-module-AP6398s-for-rk.patch b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Enable-wifi-module-AP6398s-for-rk.patch
new file mode 100644
index 00000000000..1dccb7cdb8e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/110-arm64-dts-rockchip-Enable-wifi-module-AP6398s-for-rk.patch
@@ -0,0 +1,67 @@
+From 487d614d0cd7cc61f7ad28f2527c5dc88539f792 Mon Sep 17 00:00:00 2001
+From: Andy Yan <andyshrk@163.com>
+Date: Thu, 29 Dec 2022 19:51:11 +0800
+Subject: [PATCH 110/383] arm64: dts: rockchip: Enable wifi module AP6398s for
+ rk3566 box demo
+
+There is a AP6398s wifi/bt module on this board.
+Fix the sdmmc1 dt node to make wifi work.
+
+Signed-off-by: Andy Yan <andyshrk@163.com>
+Link: https://lore.kernel.org/r/20221229115111.3899793-1-andyshrk@163.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3566-box-demo.dts     | 24 +++++++++++++++++--
+ 1 file changed, 22 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+@@ -324,8 +324,12 @@
+ 			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 
++		wifi_host_wake_h: wifi-host-wake-l {
++			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
+ 		wifi_32k: wifi-32k {
+-			rockchip,pins = <0 RK_PB0 2 &pcfg_pull_none>;
++			rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
+ 		};
+ 	};
+ 
+@@ -391,9 +395,15 @@
+ };
+ 
+ &sdmmc1 {
++	/* WiFi & BT combo module AMPAK AP6398S */
++	#address-cells = <1>;
++	#size-cells = <0>;
+ 	bus-width = <4>;
++	clock-frequency = <150000000>;
++	cap-sdio-irq;
+ 	cap-sd-highspeed;
+-	disable-wp;
++	sd-uhs-sdr104;
++	keep-power-in-suspend;
+ 	mmc-pwrseq = <&sdio_pwrseq>;
+ 	non-removable;
+ 	pinctrl-names = "default";
+@@ -401,6 +411,16 @@
+ 	vmmc-supply = <&vcc_3v3>;
+ 	vqmmc-supply = <&vcca_1v8>;
+ 	status = "okay";
++
++	brcmf: wifi@1 {
++		compatible = "brcm,bcm4329-fmac";
++		reg = <1>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <RK_PB2 GPIO_ACTIVE_HIGH>;
++		interrupt-names = "host-wake";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake_h>;
++	};
+ };
+ 
+ &spdif {
diff --git a/target/linux/rockchip/patches-6.1/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch b/target/linux/rockchip/patches-6.1/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
deleted file mode 100644
index e44d5198082..00000000000
--- a/target/linux/rockchip/patches-6.1/110-arm64-rk3568-update-gicv3-its-and-pci-msi-map.patch
+++ /dev/null
@@ -1,94 +0,0 @@
---- a/arch/arm64/Kconfig
-+++ b/arch/arm64/Kconfig
-@@ -1165,6 +1165,14 @@ config SOCIONEXT_SYNQUACER_PREITS
- 
- 	  If unsure, say Y.
- 
-+config ROCKCHIP_ERRATUM_114514
-+	bool "Rockchip RK3568 force no_local_cache"
-+	default y
-+	help
-+	  They consider this as a SoC implement design instead of a bug.
-+
-+	  If unsure, say Y.
-+
- endmenu # "ARM errata workarounds via the alternatives framework"
- 
- choice
---- a/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
-@@ -64,7 +64,7 @@
- 		compatible = "rockchip,rk3568-pcie";
- 		#address-cells = <3>;
- 		#size-cells = <2>;
--		bus-range = <0x0 0xf>;
-+		bus-range = <0x10 0x1f>;
- 		clocks = <&cru ACLK_PCIE30X1_MST>, <&cru ACLK_PCIE30X1_SLV>,
- 			 <&cru ACLK_PCIE30X1_DBI>, <&cru PCLK_PCIE30X1>,
- 			 <&cru CLK_PCIE30X1_AUX_NDFT>;
-@@ -87,7 +87,7 @@
- 		num-ib-windows = <6>;
- 		num-ob-windows = <2>;
- 		max-link-speed = <3>;
--		msi-map = <0x0 &gic 0x1000 0x1000>;
-+		msi-map = <0x1000 &its 0x1000 0x1000>;
- 		num-lanes = <1>;
- 		phys = <&pcie30phy>;
- 		phy-names = "pcie-phy";
-@@ -117,7 +117,7 @@
- 		compatible = "rockchip,rk3568-pcie";
- 		#address-cells = <3>;
- 		#size-cells = <2>;
--		bus-range = <0x0 0xf>;
-+		bus-range = <0x20 0x2f>;
- 		clocks = <&cru ACLK_PCIE30X2_MST>, <&cru ACLK_PCIE30X2_SLV>,
- 			 <&cru ACLK_PCIE30X2_DBI>, <&cru PCLK_PCIE30X2>,
- 			 <&cru CLK_PCIE30X2_AUX_NDFT>;
-@@ -140,7 +140,7 @@
- 		num-ib-windows = <6>;
- 		num-ob-windows = <2>;
- 		max-link-speed = <3>;
--		msi-map = <0x0 &gic 0x2000 0x1000>;
-+		msi-map = <0x2000 &its 0x2000 0x1000>;
- 		num-lanes = <2>;
- 		phys = <&pcie30phy>;
- 		phy-names = "pcie-phy";
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -315,14 +315,21 @@
- 
- 	gic: interrupt-controller@fd400000 {
- 		compatible = "arm,gic-v3";
-+		#interrupt-cells = <3>;
-+		#address-cells = <2>;
-+		#size-cells = <2>;
-+		ranges;
-+		interrupt-controller;
-+
- 		reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
--		      <0x0 0xfd460000 0 0x80000>; /* GICR */
-+		      <0x0 0xfd460000 0 0xc0000>; /* GICR */
- 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
--		interrupt-controller;
--		#interrupt-cells = <3>;
--		mbi-alias = <0x0 0xfd410000>;
--		mbi-ranges = <296 24>;
--		msi-controller;
-+		its: interrupt-controller@fd440000 {
-+			compatible = "arm,gic-v3-its";
-+			msi-controller;
-+			#msi-cells = <1>;
-+			reg = <0x0 0xfd440000 0x0 0x20000>;
-+		};
- 	};
- 
- 	usb_host0_ehci: usb@fd800000 {
-@@ -977,7 +984,7 @@
- 		num-ib-windows = <6>;
- 		num-ob-windows = <2>;
- 		max-link-speed = <2>;
--		msi-map = <0x0 &gic 0x0 0x1000>;
-+		msi-map = <0x0 &its 0x0 0x1000>;
- 		num-lanes = <1>;
- 		phys = <&combphy2 PHY_TYPE_PCIE>;
- 		phy-names = "pcie-phy";
diff --git a/target/linux/rockchip/patches-6.1/111-arm64-dts-rockchip-add-Hynitron-cst340-for-Anbernic-.patch b/target/linux/rockchip/patches-6.1/111-arm64-dts-rockchip-add-Hynitron-cst340-for-Anbernic-.patch
new file mode 100644
index 00000000000..1cc81165d87
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/111-arm64-dts-rockchip-add-Hynitron-cst340-for-Anbernic-.patch
@@ -0,0 +1,80 @@
+From 8150eba8fbed88b7484ca5579db8d8e73d473107 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Mon, 28 Nov 2022 17:15:28 -0600
+Subject: [PATCH 111/383] arm64: dts: rockchip: add Hynitron cst340 for
+ Anbernic 353 series
+
+Add support for the Hynitron cst340 touchscreen driver to the Anbernic
+RG353P and RG353V devices. Note the RG353VS device does not have a
+touchscreen.
+
+https://lore.kernel.org/linux-input/Y1y9e9sgE%2FDck9fB@google.com/
+
+Changes since V1:
+ - Removed 'status = "okay";', as it was never disabled.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221128231528.23360-1-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3566-anbernic-rg353p.dts   | 19 +++++++++++++++++++
+ .../dts/rockchip/rk3566-anbernic-rg353v.dts   | 12 ++++++++++++
+ 2 files changed, 31 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353p.dts
+@@ -95,6 +95,18 @@
+ 	pintctrl-names = "default";
+ 	pinctrl-0 = <&i2c2m1_xfer>;
+ 	status = "okay";
++
++	touch@1a {
++		compatible = "hynitron,cst340";
++		reg = <0x1a>;
++		interrupt-parent = <&gpio4>;
++		interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>;
++		pinctrl-0 = <&touch_rst>;
++		pinctrl-names = "default";
++		reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>;
++		touchscreen-size-x = <640>;
++		touchscreen-size-y = <480>;
++	};
+ };
+ 
+ &pinctrl {
+@@ -104,6 +116,13 @@
+ 				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	touch {
++		touch_rst: touch-rst {
++			rockchip,pins =
++				<4 RK_PA6 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
+ };
+ 
+ &rk817 {
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353v.dts
+@@ -82,6 +82,18 @@
+ 	pintctrl-names = "default";
+ 	pinctrl-0 = <&i2c2m1_xfer>;
+ 	status = "okay";
++
++	touch@1a {
++		compatible = "hynitron,cst340";
++		reg = <0x1a>;
++		interrupt-parent = <&gpio4>;
++		interrupts = <RK_PB1 IRQ_TYPE_EDGE_FALLING>;
++		pinctrl-0 = <&touch_rst>;
++		pinctrl-names = "default";
++		reset-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_LOW>;
++		touchscreen-size-x = <640>;
++		touchscreen-size-y = <480>;
++	};
+ };
+ 
+ &pinctrl {
diff --git a/target/linux/rockchip/patches-6.1/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch b/target/linux/rockchip/patches-6.1/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
deleted file mode 100644
index d07012384d2..00000000000
--- a/target/linux/rockchip/patches-6.1/111-irqchip-gic-v3-add-hackaround-for-rk3568-its.patch
+++ /dev/null
@@ -1,198 +0,0 @@
-From 536378a084c6a4148141e132efee2fa9a464e007 Mon Sep 17 00:00:00 2001
-From: Peter Geis <pgwipeout@gmail.com>
-Date: Thu, 3 Jun 2021 11:36:35 -0400
-Subject: [PATCH] irqchip: gic-v3: add hackaround for rk3568 its
-
----
- drivers/irqchip/irq-gic-v3-its.c | 70 +++++++++++++++++++++++++++++---
- 1 file changed, 65 insertions(+), 5 deletions(-)
-
---- a/drivers/irqchip/irq-gic-v3-its.c
-+++ b/drivers/irqchip/irq-gic-v3-its.c
-@@ -45,6 +45,7 @@
- 
- #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
- #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
-+#define RDIST_FLAGS_FORCE_NO_LOCAL_CACHE	(1 << 2)
- 
- #define RD_LOCAL_LPI_ENABLED                    BIT(0)
- #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
-@@ -2203,6 +2204,11 @@ static struct page *its_allocate_prop_ta
- {
- 	struct page *prop_page;
- 
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
-+		pr_err("ITS ALLOCATE PROP WORKAROUND\n");
-+		gfp_flags |= GFP_DMA;
-+	}
-+
- 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
- 	if (!prop_page)
- 		return NULL;
-@@ -2326,6 +2332,7 @@ static int its_setup_baser(struct its_no
- 	u32 alloc_pages, psz;
- 	struct page *page;
- 	void *base;
-+	gfp_t gfp_flags;
- 
- 	psz = baser->psz;
- 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
-@@ -2337,7 +2344,10 @@ static int its_setup_baser(struct its_no
- 		order = get_order(GITS_BASER_PAGES_MAX * psz);
- 	}
- 
--	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
-+	gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		gfp_flags |= GFP_DMA;
-+	page = alloc_pages_node(its->numa_node, gfp_flags, order);
- 	if (!page)
- 		return -ENOMEM;
- 
-@@ -2384,6 +2394,13 @@ retry_baser:
- 	its_write_baser(its, baser, val);
- 	tmp = baser->val;
- 
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
-+		if (tmp & GITS_BASER_SHAREABILITY_MASK)
-+			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
-+		else
-+			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
-+	}
-+
- 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
- 		/*
- 		 * Shareability didn't stick. Just use
-@@ -2966,6 +2983,10 @@ static struct page *its_allocate_pending
- {
- 	struct page *pend_page;
- 
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
-+		gfp_flags |= GFP_DMA;
-+	}
-+
- 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
- 				get_order(LPI_PENDBASE_SZ));
- 	if (!pend_page)
-@@ -3121,6 +3142,9 @@ static void its_cpu_init_lpis(void)
- 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
- 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
- 
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
-+
- 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
- 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
- 			/*
-@@ -3145,6 +3169,9 @@ static void its_cpu_init_lpis(void)
- 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
- 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
- 
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
-+
- 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
- 		/*
- 		 * The HW reports non-shareable, we must remove the
-@@ -3308,7 +3335,12 @@ static bool its_alloc_table_entry(struct
- 
- 	/* Allocate memory for 2nd level table */
- 	if (!table[idx]) {
--		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
-+		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
-+		if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE) {
-+			gfp_flags |= GFP_DMA;
-+		}
-+
-+		page = alloc_pages_node(its->numa_node, gfp_flags,
- 					get_order(baser->psz));
- 		if (!page)
- 			return false;
-@@ -3397,6 +3429,7 @@ static struct its_device *its_create_dev
- 	int nr_lpis;
- 	int nr_ites;
- 	int sz;
-+	gfp_t gfp_flags;
- 
- 	if (!its_alloc_device_table(its, dev_id))
- 		return NULL;
-@@ -3404,7 +3437,11 @@ static struct its_device *its_create_dev
- 	if (WARN_ON(!is_power_of_2(nvecs)))
- 		nvecs = roundup_pow_of_two(nvecs);
- 
--	dev = kzalloc(sizeof(*dev), GFP_KERNEL);
-+	gfp_flags = GFP_KERNEL;
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		gfp_flags |= GFP_DMA;
-+
-+	dev = kzalloc(sizeof(*dev), gfp_flags);
- 	/*
- 	 * Even if the device wants a single LPI, the ITT must be
- 	 * sized as a power of two (and you need at least one bit...).
-@@ -3412,7 +3449,7 @@ static struct its_device *its_create_dev
- 	nr_ites = max(2, nvecs);
- 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
- 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
--	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
-+	itt = kzalloc_node(sz, gfp_flags, its->numa_node);
- 	if (alloc_lpis) {
- 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
- 		if (lpi_map)
-@@ -4727,6 +4764,13 @@ static bool __maybe_unused its_enable_qu
- 	return true;
- }
- 
-+static bool __maybe_unused its_enable_quirk_rk3568(void *data)
-+{
-+	gic_rdists->flags |= RDIST_FLAGS_FORCE_NO_LOCAL_CACHE;
-+
-+	return true;
-+}
-+
- static const struct gic_quirk its_quirks[] = {
- #ifdef CONFIG_CAVIUM_ERRATUM_22375
- 	{
-@@ -4773,6 +4817,14 @@ static const struct gic_quirk its_quirks
- 		.init	= its_enable_quirk_hip07_161600802,
- 	},
- #endif
-+#ifdef CONFIG_ROCKCHIP_ERRATUM_114514
-+	{
-+		.desc	= "ITS: Rockchip erratum 114514",
-+		.iidr	= 0x0201743b,
-+		.mask	= 0xffffffff,
-+		.init	= its_enable_quirk_rk3568,
-+	},
-+#endif
- 	{
- 	}
- };
-@@ -5028,6 +5080,7 @@ static int __init its_probe_one(struct r
- 	struct page *page;
- 	u32 ctlr;
- 	int err;
-+	gfp_t gfp_flags;
- 
- 	its_base = its_map_one(res, &err);
- 	if (!its_base)
-@@ -5081,7 +5134,9 @@ static int __init its_probe_one(struct r
- 
- 	its->numa_node = numa_node;
- 
--	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
-+	gfp_flags = GFP_KERNEL | __GFP_ZERO | GFP_DMA;
-+
-+	page = alloc_pages_node(its->numa_node, gfp_flags,
- 				get_order(ITS_CMD_QUEUE_SZ));
- 	if (!page) {
- 		err = -ENOMEM;
-@@ -5112,6 +5167,9 @@ static int __init its_probe_one(struct r
- 	gits_write_cbaser(baser, its->base + GITS_CBASER);
- 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
- 
-+	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NO_LOCAL_CACHE)
-+		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
-+
- 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
- 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
- 			/*
diff --git a/target/linux/rockchip/patches-6.1/112-arm64-dts-rockchip-Fix-RX-delay-for-ethernet-phy-on-.patch b/target/linux/rockchip/patches-6.1/112-arm64-dts-rockchip-Fix-RX-delay-for-ethernet-phy-on-.patch
new file mode 100644
index 00000000000..d0006cd7e1d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/112-arm64-dts-rockchip-Fix-RX-delay-for-ethernet-phy-on-.patch
@@ -0,0 +1,38 @@
+From 1b6f611c644c6c2aa673294937d205f801afa62a Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Fri, 13 Jan 2023 13:02:20 +0000
+Subject: [PATCH 112/383] arm64: dts: rockchip: Fix RX delay for ethernet phy
+ on rk3588s-rock5a
+
+Add network PHY rx delay and change type to rgmii, so
+that it is applied. This fixes packet loss when more
+than a few packets are exchanged.
+
+Fixes: d1824cf95799 ("arm64: dts: rockchip: Add rock-5a board")
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Link: https://lore.kernel.org/r/20230113130220.662194-1-lucas.tanure@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -23,7 +23,7 @@
+ &gmac1 {
+ 	clock_in_out = "output";
+ 	phy-handle = <&rgmii_phy1>;
+-	phy-mode = "rgmii-rxid";
++	phy-mode = "rgmii";
+ 	pinctrl-0 = <&gmac1_miim
+ 		     &gmac1_tx_bus2
+ 		     &gmac1_rx_bus2
+@@ -31,6 +31,7 @@
+ 		     &gmac1_rgmii_bus>;
+ 	pinctrl-names = "default";
+ 	tx_delay = <0x3a>;
++	rx_delay = <0x3e>;
+ 	status = "okay";
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/112-rfkill-gpio-add-of_match_table-support.patch b/target/linux/rockchip/patches-6.1/112-rfkill-gpio-add-of_match_table-support.patch
deleted file mode 100644
index 6594a675ee3..00000000000
--- a/target/linux/rockchip/patches-6.1/112-rfkill-gpio-add-of_match_table-support.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From b4aeb93e697e4dbe2d336d01290e92e98acfd83c Mon Sep 17 00:00:00 2001
-From: jensen <jensenhuang@friendlyarm.com>
-Date: Sat, 15 Oct 2022 18:47:24 +0800
-Subject: [PATCH] rfkill: gpio: add of_match_table support
-
-Signed-off-by: jensen <jensenhuang@friendlyarm.com>
----
- net/rfkill/rfkill-gpio.c | 8 ++++++++
- 1 file changed, 8 insertions(+)
-
---- a/net/rfkill/rfkill-gpio.c
-+++ b/net/rfkill/rfkill-gpio.c
-@@ -164,6 +164,13 @@ static const struct acpi_device_id rfkil
- };
- MODULE_DEVICE_TABLE(acpi, rfkill_acpi_match);
- #endif
-+#ifdef CONFIG_OF
-+static struct of_device_id rfkill_gpio_of_match[] = {
-+	{ .compatible = "rfkill-gpio" },
-+	{ },
-+};
-+MODULE_DEVICE_TABLE(of, rfkill_gpio_of_match);
-+#endif
- 
- static struct platform_driver rfkill_gpio_driver = {
- 	.probe = rfkill_gpio_probe,
-@@ -171,6 +178,7 @@ static struct platform_driver rfkill_gpi
- 	.driver = {
- 		.name = "rfkill_gpio",
- 		.acpi_match_table = ACPI_PTR(rfkill_acpi_match),
-+		.of_match_table = of_match_ptr(rfkill_gpio_of_match),
- 	},
- };
- 
diff --git a/target/linux/rockchip/patches-6.1/113-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Mo.patch b/target/linux/rockchip/patches-6.1/113-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Mo.patch
new file mode 100644
index 00000000000..485b3744a07
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/113-arm64-dts-rockchip-Add-rk3566-based-Radxa-Compute-Mo.patch
@@ -0,0 +1,388 @@
+From 0777633d71b4fa8003d6eeda21633915a49d5b19 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Thu, 12 Jan 2023 16:29:01 +0530
+Subject: [PATCH 113/383] arm64: dts: rockchip: Add rk3566 based Radxa Compute
+ Module 3
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Radxa Compute Module 3(CM3) is one of the modules from a series
+System On Module based on the Radxa ROCK 3 series and is compatible
+with Raspberry Pi CM4 pinout and form factor.
+
+Specification:
+- Rockchip RK3566
+- up to 8GB LPDDR4
+- up to 128GB high performance eMMC
+- Optional wireless LAN, 2.4GHz and 5.0GHz IEEE 802.11b/g/n/ac wireless,
+  BT 5.0, BLE with onboard and external antenna.
+- Gigabit Ethernet PHY
+
+Radxa CM3 needs to mount on top of this IO board in order to create
+complete Radxa CM3 IO board platform.
+
+Since Radxa CM3 is compatible with Raspberry Pi CM4 pinout so it is
+possible to mount Radxa CM3 on top of the Rasberry Pi CM4 IO board.
+
+Add support for Radxa CM3.
+
+Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230112105902.192852-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 345 ++++++++++++++++++
+ 1 file changed, 345 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -0,0 +1,345 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Radxa Limited
++ * Copyright (c) 2022 Amarula Solutions(India)
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++
++/ {
++	compatible = "radxa,radxa-cm3", "rockchip,rk3566";
++
++	aliases {
++		mmc0 = &sdhci;
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-0 {
++			gpios = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_STATUS;
++			linux,default-trigger = "timer";
++			default-state = "on";
++			pinctrl-names = "default";
++			pinctrl-0 = <&user_led2>;
++		};
++	};
++
++	vcc_sys: vcc-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc_1v8: vcc-1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8_p>;
++	};
++
++	vcc_3v3: vcc-3v3-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_3v3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	vcca_1v8: vcca-1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca_1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8_p>;
++	};
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu_npu>;
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <712500>;
++		regulator-max-microvolt = <1390000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk817: pmic@20 {
++		compatible = "rockchip,rk817";
++		reg = <0x20>;
++		#clock-cells = <1>;
++		clock-output-names = "rk817-clkout1", "rk817-clkout2";
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int_l>;
++		rockchip,system-power-controller;
++		wakeup-source;
++
++		vcc1-supply = <&vcc_sys>;
++		vcc2-supply = <&vcc_sys>;
++		vcc3-supply = <&vcc_sys>;
++		vcc4-supply = <&vcc_sys>;
++		vcc5-supply = <&vcc_sys>;
++		vcc6-supply = <&vcc_sys>;
++		vcc7-supply = <&vcc_sys>;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vdd_gpu_npu: DCDC_REG2 {
++				regulator-name = "vdd_gpu_npu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc3v3_sys: DCDC_REG4 {
++				regulator-name = "vcc3v3_sys";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG1 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_1v8_p: LDO_REG7 {
++				regulator-name = "vcc_1v8_p";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc1v8_dvp: LDO_REG8 {
++				regulator-name = "vcc1v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc2v8_dvp: LDO_REG9 {
++				regulator-name = "vcc2v8_dvp";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++		};
++	};
++};
++
++&pinctrl {
++	pmic {
++		pmic_int_l: pmic-int-l {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	leds {
++		user_led2: user-led2 {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc_3v3>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio2-supply = <&vcc_1v8>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_3v3>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/114-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-boa.patch b/target/linux/rockchip/patches-6.1/114-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-boa.patch
new file mode 100644
index 00000000000..49b926dea3c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/114-arm64-dts-rockchip-Add-Radxa-Compute-Module-3-IO-boa.patch
@@ -0,0 +1,235 @@
+From efde50f3a700466ec0721ab69f6aea84075ac5c7 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Thu, 12 Jan 2023 16:29:02 +0530
+Subject: [PATCH 114/383] arm64: dts: rockchip: Add Radxa Compute Module 3 IO
+ board
+
+Radxa Compute Module 3(CM3) IO board is an application board from Radxa
+and is compatible with Raspberry Pi CM4 IO form factor.
+
+Specification:
+- 1x HDMI,
+- 2x MIPI DSI
+- 2x MIPI CSI2
+- 1x eDP
+- 1x PCIe card
+- 2x SATA
+- 2x USB 2.0 Host
+- 1x USB 3.0
+- 1x USB 2.0 OTG
+- Phone jack
+- microSD slot
+- 40-pin GPIO expansion header
+- 12V DC
+
+Radxa CM3 needs to mount on top of this IO board in order to create
+complete Radxa CM3 IO board platform.
+
+Add support for Radxa CM3 IO Board.
+
+Co-developed-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: FUKAUMI Naoki <naoki@radxa.com>
+Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230112105902.192852-3-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 179 ++++++++++++++++++
+ 2 files changed, 180 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -74,6 +74,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pi
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-radxa-cm3-io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-blade.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -0,0 +1,179 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Radxa Limited
++ * Copyright (c) 2022 Amarula Solutions(India)
++ */
++
++/dts-v1/;
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3566.dtsi"
++#include "rk3566-radxa-cm3.dtsi"
++
++/ {
++	model = "Radxa Compute Module 3(CM3) IO Board";
++	compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
++
++	aliases {
++		mmc1 = &sdmmc0;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++
++		led-1 {
++			gpios = <&gpio4 RK_PA4 GPIO_ACTIVE_LOW>;
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_ACTIVITY;
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&pi_nled_activity>;
++		};
++	};
++
++	vcc5v0_usb30: vcc5v0-usb30-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb30";
++		enable-active-high;
++		gpio = <&gpio3 RK_PC2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb30_en_h>;
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc_sys>;
++	};
++
++	vcca1v8_image: vcca1v8-image-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca1v8_image";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc_1v8_p>;
++	};
++
++	vdda0v9_image: vdda0v9-image-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcca0v9_image";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vdda_0v9>;
++	};
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&pinctrl {
++	leds {
++		pi_nled_activity: pi-nled-activity {
++			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdcard {
++		sdmmc_pwren: sdmmc-pwren {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb30_en_h: vcc5v0-host-en-h {
++			rockchip,pins = <3 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&sdmmc0 {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	vqmmc-supply = <&vccio_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det &sdmmc0_pwren>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb30>;
++	status = "okay";
++};
++
++&usb2phy1_host {
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/115-arm64-dts-rockchip-Update-eMMC-SD-aliases-for-Radxa-.patch b/target/linux/rockchip/patches-6.1/115-arm64-dts-rockchip-Update-eMMC-SD-aliases-for-Radxa-.patch
new file mode 100644
index 00000000000..524524d7f54
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/115-arm64-dts-rockchip-Update-eMMC-SD-aliases-for-Radxa-.patch
@@ -0,0 +1,49 @@
+From b5b96b10b8989841b83884b7a20a6082a79dfaca Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Wed, 18 Jan 2023 13:34:53 +0530
+Subject: [PATCH 115/383] arm64: dts: rockchip: Update eMMC, SD aliases for
+ Radxa SoM boards
+
+Radxa has produced Compute Modules like RK3399pro VMARC and CM3i with
+onboarding eMMC flash, so the eMMC is the primary MMC device.
+
+On the other hand, Rockchip boot orders start from eMMC from an MMC
+device perspective.
+
+Mark, the eMMC has mmc0 to satisfy the above two conditions.
+
+Reported-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230118080454.11643-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi | 4 ++--
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts     | 3 +--
+ 2 files changed, 3 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399pro-vmarc-som.dtsi
+@@ -13,8 +13,8 @@
+ 	compatible = "vamrs,rk3399pro-vmarc-som", "rockchip,rk3399pro";
+ 
+ 	aliases {
+-		mmc0 = &sdmmc;
+-		mmc1 = &sdhci;
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc;
+ 	};
+ 
+ 	vcc3v3_pcie: vcc-pcie-regulator {
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -8,8 +8,7 @@
+ 	compatible = "radxa,e25", "rockchip,rk3568";
+ 
+ 	aliases {
+-		mmc0 = &sdmmc0;
+-		mmc1 = &sdhci;
++		mmc1 = &sdmmc0;
+ 	};
+ 
+ 	pwm-leds {
diff --git a/target/linux/rockchip/patches-6.1/116-arm64-dts-rockchip-Update-eMMC-SD-aliases-for-Radxa-.patch b/target/linux/rockchip/patches-6.1/116-arm64-dts-rockchip-Update-eMMC-SD-aliases-for-Radxa-.patch
new file mode 100644
index 00000000000..75db99df3e8
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/116-arm64-dts-rockchip-Update-eMMC-SD-aliases-for-Radxa-.patch
@@ -0,0 +1,62 @@
+From 79856afa43cdcf166a806021792aed3b2fb6297d Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Wed, 18 Jan 2023 13:34:54 +0530
+Subject: [PATCH 116/383] arm64: dts: rockchip: Update eMMC, SD aliases for
+ Radxa SBC boards
+
+Radxa SBC boards like ROCK 3A/4 models do support eMMC and SDcard
+via external connector slots.
+
+Mark, the eMMC has mmc0 by considering the Rockchip boot order priority
+as both MMC devices are connected externally.
+
+Reported-by: FUKAUMI Naoki <naoki@radxa.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230118080454.11643-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts | 4 ++--
+ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi   | 4 ++--
+ arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts      | 4 ++--
+ 3 files changed, 6 insertions(+), 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-4c-plus.dts
+@@ -15,8 +15,8 @@
+ 	compatible = "radxa,rock-4c-plus", "rockchip,rk3399";
+ 
+ 	aliases {
+-		mmc0 = &sdmmc;
+-		mmc1 = &sdhci;
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc;
+ 	};
+ 
+ 	chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4.dtsi
+@@ -13,8 +13,8 @@
+ 
+ / {
+ 	aliases {
+-		mmc0 = &sdmmc;
+-		mmc1 = &sdhci;
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc;
+ 	};
+ 
+ 	chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -13,8 +13,8 @@
+ 
+ 	aliases {
+ 		ethernet0 = &gmac1;
+-		mmc0 = &sdmmc0;
+-		mmc1 = &sdhci;
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc0;
+ 	};
+ 
+ 	chosen: chosen {
diff --git a/target/linux/rockchip/patches-6.1/117-arm64-dts-rockchip-add-pinctrls-for-16-bit-18-bit-rg.patch b/target/linux/rockchip/patches-6.1/117-arm64-dts-rockchip-add-pinctrls-for-16-bit-18-bit-rg.patch
new file mode 100644
index 00000000000..2a28d18c130
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/117-arm64-dts-rockchip-add-pinctrls-for-16-bit-18-bit-rg.patch
@@ -0,0 +1,122 @@
+From c593b2f170bbfb2dae049c83fab6a37d1ffd00d9 Mon Sep 17 00:00:00 2001
+From: Michael Riesch <michael.riesch@wolfvision.net>
+Date: Tue, 24 Jan 2023 06:47:06 +0100
+Subject: [PATCH 117/383] arm64: dts: rockchip: add pinctrls for 16-bit/18-bit
+ rgb interface to rk356x
+
+The rk3568-pinctrl.dtsi only defines the 24-bit RGB interface. Add separate
+nodes for the 16-bit and 18-bit version, respectively. While at it, split
+off the clock/sync signals from the data signals.
+
+The exact mapping of the data pins was discussed here:
+https://lore.kernel.org/linux-rockchip/f33a0488-528c-99de-3279-3c0346a03fd6@wolfvision.net/T/
+
+Signed-off-by: Michael Riesch <michael.riesch@wolfvision.net>
+Link: https://lore.kernel.org/r/20230124054706.3921383-7-michael.riesch@wolfvision.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-pinctrl.dtsi     | 94 +++++++++++++++++++
+ 1 file changed, 94 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
+@@ -3117,4 +3117,98 @@
+ 				<0 RK_PA1 0 &pcfg_pull_none>;
+ 		};
+ 	};
++
++	lcdc {
++		/omit-if-no-ref/
++		lcdc_clock: lcdc-clock {
++			rockchip,pins =
++				/* lcdc_clk */
++				<3 RK_PA0 1 &pcfg_pull_none>,
++				/* lcdc_den */
++				<3 RK_PC3 1 &pcfg_pull_none>,
++				/* lcdc_hsync */
++				<3 RK_PC1 1 &pcfg_pull_none>,
++				/* lcdc_vsync */
++				<3 RK_PC2 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		lcdc_data16: lcdc-data16 {
++			rockchip,pins =
++				/* lcdc_d3 */
++				<2 RK_PD3 1 &pcfg_pull_none>,
++				/* lcdc_d4 */
++				<2 RK_PD4 1 &pcfg_pull_none>,
++				/* lcdc_d5 */
++				<2 RK_PD5 1 &pcfg_pull_none>,
++				/* lcdc_d6 */
++				<2 RK_PD6 1 &pcfg_pull_none>,
++				/* lcdc_d7 */
++				<2 RK_PD7 1 &pcfg_pull_none>,
++				/* lcdc_d10 */
++				<3 RK_PA3 1 &pcfg_pull_none>,
++				/* lcdc_d11 */
++				<3 RK_PA4 1 &pcfg_pull_none>,
++				/* lcdc_d12 */
++				<3 RK_PA5 1 &pcfg_pull_none>,
++				/* lcdc_d13 */
++				<3 RK_PA6 1 &pcfg_pull_none>,
++				/* lcdc_d14 */
++				<3 RK_PA7 1 &pcfg_pull_none>,
++				/* lcdc_d15 */
++				<3 RK_PB0 1 &pcfg_pull_none>,
++				/* lcdc_d19 */
++				<3 RK_PB4 1 &pcfg_pull_none>,
++				/* lcdc_d20 */
++				<3 RK_PB5 1 &pcfg_pull_none>,
++				/* lcdc_d21 */
++				<3 RK_PB6 1 &pcfg_pull_none>,
++				/* lcdc_d22 */
++				<3 RK_PB7 1 &pcfg_pull_none>,
++				/* lcdc_d23 */
++				<3 RK_PC0 1 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		lcdc_data18: lcdc-data18 {
++			rockchip,pins =
++				/* lcdc_d2 */
++				<2 RK_PD2 1 &pcfg_pull_none>,
++				/* lcdc_d3 */
++				<2 RK_PD3 1 &pcfg_pull_none>,
++				/* lcdc_d4 */
++				<2 RK_PD4 1 &pcfg_pull_none>,
++				/* lcdc_d5 */
++				<2 RK_PD5 1 &pcfg_pull_none>,
++				/* lcdc_d6 */
++				<2 RK_PD6 1 &pcfg_pull_none>,
++				/* lcdc_d7 */
++				<2 RK_PD7 1 &pcfg_pull_none>,
++				/* lcdc_d10 */
++				<3 RK_PA3 1 &pcfg_pull_none>,
++				/* lcdc_d11 */
++				<3 RK_PA4 1 &pcfg_pull_none>,
++				/* lcdc_d12 */
++				<3 RK_PA5 1 &pcfg_pull_none>,
++				/* lcdc_d13 */
++				<3 RK_PA6 1 &pcfg_pull_none>,
++				/* lcdc_d14 */
++				<3 RK_PA7 1 &pcfg_pull_none>,
++				/* lcdc_d15 */
++				<3 RK_PB0 1 &pcfg_pull_none>,
++				/* lcdc_d18 */
++				<3 RK_PB3 1 &pcfg_pull_none>,
++				/* lcdc_d19 */
++				<3 RK_PB4 1 &pcfg_pull_none>,
++				/* lcdc_d20 */
++				<3 RK_PB5 1 &pcfg_pull_none>,
++				/* lcdc_d21 */
++				<3 RK_PB6 1 &pcfg_pull_none>,
++				/* lcdc_d22 */
++				<3 RK_PB7 1 &pcfg_pull_none>,
++				/* lcdc_d23 */
++				<3 RK_PC0 1 &pcfg_pull_none>;
++		};
++	};
++
+ };
diff --git a/target/linux/rockchip/patches-6.1/118-arm64-dts-rockchip-add-display-to-RG503.patch b/target/linux/rockchip/patches-6.1/118-arm64-dts-rockchip-add-display-to-RG503.patch
new file mode 100644
index 00000000000..62babcc5b42
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/118-arm64-dts-rockchip-add-display-to-RG503.patch
@@ -0,0 +1,99 @@
+From af433f48b5c43dda7886aca794eaae4c712da0d3 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Mon, 23 Jan 2023 09:46:03 -0600
+Subject: [PATCH 118/383] arm64: dts: rockchip: add display to RG503
+
+Add Samsung AMS495QA01 panel to RG503.
+
+Co-developed-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20230123154603.1315112-5-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3566-anbernic-rg503.dts    | 55 +++++++++++++++++++
+ 1 file changed, 55 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+@@ -47,6 +47,21 @@
+ 		mosi-gpios = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
+ 		cs-gpios = <&gpio4 RK_PA7 GPIO_ACTIVE_HIGH>;
+ 		num-chipselects = <0>;
++
++		panel@0 {
++			compatible = "samsung,ams495qa01";
++			reg = <0>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&lcd_reset>;
++			reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
++			vdd-supply = <&vcc_3v3>;
++
++			port {
++				mipi_in_panel: endpoint {
++					remote-endpoint = <&mipi_out_panel>;
++				};
++			};
++		};
+ 	};
+ 
+ 	/* Channels reversed for both headphones and speakers. */
+@@ -94,6 +109,32 @@
+ 	assigned-clock-rates = <1200000000>, <200000000>, <500000000>;
+ };
+ 
++&dsi_dphy0 {
++	status = "okay";
++};
++
++&dsi0 {
++	status = "okay";
++
++	ports {
++		dsi0_in: port@0 {
++			reg = <0>;
++
++			dsi0_in_vp1: endpoint {
++				remote-endpoint = <&vp1_out_dsi0>;
++			};
++		};
++
++		dsi0_out: port@1 {
++			reg = <1>;
++
++			mipi_out_panel: endpoint {
++				remote-endpoint = <&mipi_in_panel>;
++			};
++		};
++	};
++};
++
+ &gpio_keys_control {
+ 	button-a {
+ 		gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_LOW>;
+@@ -146,6 +187,13 @@
+ 		};
+ 	};
+ 
++	gpio-lcd {
++		lcd_reset: lcd-reset {
++			rockchip,pins =
++				<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	gpio-spi {
+ 		spi_pins: spi-pins {
+ 			rockchip,pins =
+@@ -164,3 +212,10 @@
+ 		rockchip,sleep-filter-current-microamp = <100000>;
+ 	};
+ };
++
++&vp1 {
++	vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
++		reg = <ROCKCHIP_VOP2_EP_MIPI0>;
++		remote-endpoint = <&dsi0_in_vp1>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/119-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch b/target/linux/rockchip/patches-6.1/119-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch
new file mode 100644
index 00000000000..a4c1170a798
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/119-arm64-dts-rockchip-Enable-Ethernet-for-Radxa-CM3-IO.patch
@@ -0,0 +1,133 @@
+From 15b062e1b66d6976b1bd0a8db7455510dd9874e4 Mon Sep 17 00:00:00 2001
+From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Date: Wed, 25 Jan 2023 21:40:22 +0530
+Subject: [PATCH 119/383] arm64: dts: rockchip: Enable Ethernet for Radxa CM3
+ IO
+
+Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
+
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
+ 1 file changed, 93 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -21,6 +21,13 @@
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
++	gmac1_clkin: external-gmac1-clock {
++		compatible = "fixed-clock";
++		clock-frequency = <125000000>;
++		clock-output-names = "gmac1_clkin";
++		#clock-cells = <0>;
++	};
++
+ 	hdmi-con {
+ 		compatible = "hdmi-connector";
+ 		type = "a";
+@@ -83,6 +90,29 @@
+ 	status = "okay";
+ };
+ 
++&gmac1 {
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
++	assigned-clock-rates = <0>, <125000000>;
++	clock_in_out = "input";
++	phy-handle = <&rgmii_phy1>;
++	phy-mode = "rgmii";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m0_miim
++		     &gmac1m0_tx_bus2
++		     &gmac1m0_rx_bus2
++		     &gmac1m0_rgmii_clk
++		     &gmac1m0_rgmii_bus
++		     &gmac1m0_clkinout>;
++	snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++	tx_delay = <0x46>;
++	rx_delay = <0x2e>;
++	status = "okay";
++};
++
+ &hdmi {
+ 	avdd-0v9-supply = <&vdda0v9_image>;
+ 	avdd-1v8-supply = <&vcca1v8_image>;
+@@ -105,7 +135,70 @@
+ 	status = "okay";
+ };
+ 
++&mdio1 {
++	rgmii_phy1: ethernet-phy@0 {
++		compatible="ethernet-phy-ieee802.3-c22";
++		reg= <0x0>;
++	};
++};
++
+ &pinctrl {
++	gmac1 {
++		gmac1m0_miim: gmac1m0-miim {
++			rockchip,pins =
++				/* gmac1_mdcm0 */
++				<3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_mdiom0 */
++				<3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
++			rockchip,pins =
++				/* gmac1_rxd0m0 */
++				<3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_rxd1m0 */
++				<3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_rxdvcrsm0 */
++				<3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
++			rockchip,pins =
++				/* gmac1_txd0m0 */
++				<3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txd1m0 */
++				<3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txenm0 */
++				<3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
++			rockchip,pins =
++				/* gmac1_rxclkm0 */
++				<3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txclkm0 */
++				<3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
++			rockchip,pins =
++				/* gmac1_rxd2m0 */
++				<3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_rxd3m0 */
++				<3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txd2m0 */
++				<3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
++				/* gmac1_txd3m0 */
++				<3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
++		};
++
++		gmac1m0_clkinout: gmac1m0-clkinout {
++			rockchip,pins =
++				/* gmac1_mclkinoutm0 */
++				<3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
++		};
++	};
++
+ 	leds {
+ 		pi_nled_activity: pi-nled-activity {
+ 			rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
diff --git a/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3566-Enable-WiFi-BT-support-for.patch b/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3566-Enable-WiFi-BT-support-for.patch
new file mode 100644
index 00000000000..fbe65341111
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/120-arm64-dts-rockchip-rk3566-Enable-WiFi-BT-support-for.patch
@@ -0,0 +1,135 @@
+From cbcada7c703e87c990bc18eb25da7eebcd38cc40 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Wed, 25 Jan 2023 21:40:23 +0530
+Subject: [PATCH 120/383] arm64: dts: rockchip: rk3566: Enable WiFi, BT support
+ for Radxa CM3
+
+Radxa Compute Module 3 has an onboard AW_CM256SM WiFi/BT module.
+
+Add nodes for enabling it.
+
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230125161023.12115-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 80 +++++++++++++++++++
+ 1 file changed, 80 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -66,6 +66,15 @@
+ 		regulator-max-microvolt = <1800000>;
+ 		vin-supply = <&vcc_1v8_p>;
+ 	};
++
++	sdio_pwrseq: pwrseq-sdio {
++		compatible = "mmc-pwrseq-simple";
++		clocks = <&rk817 1>;
++		clock-names = "ext_clock";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_reg_on_h>;
++		reset-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_LOW>;
++	};
+ };
+ 
+ &cpu0 {
+@@ -287,6 +296,20 @@
+ };
+ 
+ &pinctrl {
++	bluetooth {
++		bt_host_wake_h: bt-host-wake-h {
++			rockchip,pins = <2 RK_PB2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_reg_on_h: bt-reg-on-h {
++			rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_wake_host_h: bt-wake-host-h {
++			rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
+ 	pmic {
+ 		pmic_int_l: pmic-int-l {
+ 			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+@@ -298,6 +321,16 @@
+ 			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	wifi {
++		wifi_reg_on_h: wifi-reg-on-h {
++			rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wifi_host_wake_h: wifi-host-wake-h {
++			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pmu_io_domains {
+@@ -318,6 +351,34 @@
+ 	status = "okay";
+ };
+ 
++&sdmmc1 {
++	#address-cells = <1>;
++	#size-cells = <0>;
++	bus-width = <4>;
++	disable-wp;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	keep-power-in-suspend;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_clk &sdmmc1_cmd>;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3>;
++	vqmmc-supply = <&vcc_1v8>;
++	status = "okay";
++
++	wifi@1 {
++		compatible = "brcm,bcm43455-fmac";
++		reg = <1>;
++		interrupt-parent = <&gpio2>;
++		interrupts = <RK_PC1 IRQ_TYPE_LEVEL_HIGH>;
++		interrupt-names = "host-wake";
++		pinctrl-names = "default";
++		pinctrl-0 = <&wifi_host_wake_h>;
++	};
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	max-frequency = <200000000>;
+@@ -330,6 +391,25 @@
+ 	status = "okay";
+ };
+ 
++&uart1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&uart1m0_ctsn &uart1m0_rtsn &uart1m0_xfer>;
++	status = "okay";
++
++	bluetooth {
++		compatible = "brcm,bcm4345c5";
++		clocks = <&rk817 1>;
++		clock-names = "lpo";
++		device-wakeup-gpios = <&gpio2 RK_PB2 GPIO_ACTIVE_HIGH>;
++		host-wakeup-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_HIGH>;
++		reset-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&bt_host_wake_h &bt_reg_on_h &bt_wake_host_h>;
++		vbat-supply = <&vcc_3v3>;
++		vddio-supply = <&vcc_1v8>;
++	};
++};
++
+ &usb2phy0 {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/121-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/121-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
new file mode 100644
index 00000000000..e871b2f818b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/121-arm64-dts-rockchip-Fix-compatible-for-Radxa-CM3.patch
@@ -0,0 +1,46 @@
+From 2ea55b76fffaffc4476b29ee9a41c4e37abade53 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Mon, 23 Jan 2023 12:46:50 +0530
+Subject: [PATCH 121/383] arm64: dts: rockchip: Fix compatible for Radxa CM3
+
+The compatible string "radxa,radxa-cm3" referring the product name
+as "Radxa Radxa CM3" but the actual product name is "Radxa CM3".
+
+Fix the compatible strings.
+
+Fixes: 24a28d3eb07d ("dt-bindings: arm: rockchip: Add Radxa Compute Module 3")
+Fixes: 7469ab529bca ("arm64: dts: rockchip: Add rk3566 based Radxa Compute Module 3")
+Fixes: 096ebfb74b19 ("arm64: dts: rockchip: Add Radxa Compute Module 3 IO board")
+Suggested-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230123071654.73139-1-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi   | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -11,7 +11,7 @@
+ 
+ / {
+ 	model = "Radxa Compute Module 3(CM3) IO Board";
+-	compatible = "radxa,radxa-cm3-io", "radxa,radxa-cm3", "rockchip,rk3566";
++	compatible = "radxa,cm3-io", "radxa,cm3", "rockchip,rk3566";
+ 
+ 	aliases {
+ 		mmc1 = &sdmmc0;
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3.dtsi
+@@ -8,7 +8,7 @@
+ #include <dt-bindings/leds/common.h>
+ 
+ / {
+-	compatible = "radxa,radxa-cm3", "rockchip,rk3566";
++	compatible = "radxa,cm3", "rockchip,rk3566";
+ 
+ 	aliases {
+ 		mmc0 = &sdhci;
diff --git a/target/linux/rockchip/patches-6.1/122-arm64-dts-rockchip-Add-missing-CM3i-fallback-compati.patch b/target/linux/rockchip/patches-6.1/122-arm64-dts-rockchip-Add-missing-CM3i-fallback-compati.patch
new file mode 100644
index 00000000000..7fd7ecbd1d1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/122-arm64-dts-rockchip-Add-missing-CM3i-fallback-compati.patch
@@ -0,0 +1,36 @@
+From 3841198dce5a655ba87d2d97c913a57bd227f520 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Mon, 23 Jan 2023 12:46:51 +0530
+Subject: [PATCH 122/383] arm64: dts: rockchip: Add missing CM3i fallback
+ compatible for Radxa E25
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In order to function the Radxa E25 Carrier board, it is mandatory to
+mount the Radxa CM3i module. 
+
+Add Radxa CM3i compatible as fallback compatible to string to satisfy
+the Module and Carrier board topology.
+
+Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
+Cc: Chukun Pan <amadeus@jmu.edu.cn>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230123071654.73139-2-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -5,7 +5,7 @@
+ 
+ / {
+ 	model = "Radxa E25";
+-	compatible = "radxa,e25", "rockchip,rk3568";
++	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
+ 
+ 	aliases {
+ 		mmc1 = &sdmmc0;
diff --git a/target/linux/rockchip/patches-6.1/123-arm64-dts-rockchip-Drop-unneeded-model-for-Radxa-CM3.patch b/target/linux/rockchip/patches-6.1/123-arm64-dts-rockchip-Drop-unneeded-model-for-Radxa-CM3.patch
new file mode 100644
index 00000000000..95fb44dd303
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/123-arm64-dts-rockchip-Drop-unneeded-model-for-Radxa-CM3.patch
@@ -0,0 +1,39 @@
+From 884bdd194a5d198d8c228f59637c9e270a9e1623 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Mon, 23 Jan 2023 12:46:52 +0530
+Subject: [PATCH 123/383] arm64: dts: rockchip: Drop unneeded model for Radxa
+ CM3i
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+With module and carrier board topology, carrier board dts will include
+module dtsi files for creating complete platform.
+
+The carrier board dts will have final model name and compatible string
+so any model name added in module dtsi will eventually replaced.
+
+This happened for any devicetree property if the same property is updated
+or added twice.
+
+So, drop this unneeded model name from module dtsi.
+
+Cc: Chukun Pan <amadeus@jmu.edu.cn>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230123071654.73139-3-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-cm3i.dtsi
+@@ -6,7 +6,6 @@
+ #include "rk3568.dtsi"
+ 
+ / {
+-	model = "Radxa CM3 Industrial Board";
+ 	compatible = "radxa,cm3i", "rockchip,rk3568";
+ 
+ 	aliases {
diff --git a/target/linux/rockchip/patches-6.1/124-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-.patch b/target/linux/rockchip/patches-6.1/124-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-.patch
new file mode 100644
index 00000000000..a91a560a4d7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/124-arm64-dts-rockchip-Correct-the-model-name-for-Radxa-.patch
@@ -0,0 +1,30 @@
+From 30fe85597fa7932fabca07e4b82a7f51de1b93c3 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@amarulasolutions.com>
+Date: Mon, 23 Jan 2023 12:46:53 +0530
+Subject: [PATCH 124/383] arm64: dts: rockchip: Correct the model name for
+ Radxa E25
+
+Radxa E25 is a Carrier board, so update the model name for Radxa E25
+as suggested by the Radxa website.
+
+Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25")
+Cc: Chukun Pan <amadeus@jmu.edu.cn>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230123071654.73139-4-jagan@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts
+@@ -4,7 +4,7 @@
+ #include "rk3568-radxa-cm3i.dtsi"
+ 
+ / {
+-	model = "Radxa E25";
++	model = "Radxa E25 Carrier Board";
+ 	compatible = "radxa,e25", "radxa,cm3i", "rockchip,rk3568";
+ 
+ 	aliases {
diff --git a/target/linux/rockchip/patches-6.1/125-arm64-dts-rockchip-Fix-rk3399-GICv3-ITS-node-name.patch b/target/linux/rockchip/patches-6.1/125-arm64-dts-rockchip-Fix-rk3399-GICv3-ITS-node-name.patch
new file mode 100644
index 00000000000..f7fa3470961
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/125-arm64-dts-rockchip-Fix-rk3399-GICv3-ITS-node-name.patch
@@ -0,0 +1,27 @@
+From 1534825aab467b500751db6f32c73c9209c92064 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Tue, 7 Feb 2023 17:47:49 -0600
+Subject: [PATCH 125/383] arm64: dts: rockchip: Fix rk3399 GICv3 ITS node name
+
+The GICv3 ITS is an MSI controller, therefore its node name should be
+'msi-controller'.
+
+Signed-off-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230207234750.202154-1-robh@kernel.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -552,7 +552,7 @@
+ 		      <0x0 0xfff10000 0 0x10000>, /* GICH */
+ 		      <0x0 0xfff20000 0 0x10000>; /* GICV */
+ 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+-		its: interrupt-controller@fee20000 {
++		its: msi-controller@fee20000 {
+ 			compatible = "arm,gic-v3-its";
+ 			msi-controller;
+ 			#msi-cells = <1>;
diff --git a/target/linux/rockchip/patches-6.1/126-arm64-dts-rockchip-Lower-SD-card-speed-on-rk3399-Pin.patch b/target/linux/rockchip/patches-6.1/126-arm64-dts-rockchip-Lower-SD-card-speed-on-rk3399-Pin.patch
new file mode 100644
index 00000000000..cd06e69b00e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/126-arm64-dts-rockchip-Lower-SD-card-speed-on-rk3399-Pin.patch
@@ -0,0 +1,37 @@
+From e439396603ba9f13adbf453a0d3cc9e2f48d2389 Mon Sep 17 00:00:00 2001
+From: Dan Johansen <strit@manjaro.org>
+Date: Sun, 5 Mar 2023 11:47:31 +0100
+Subject: [PATCH 126/383] arm64: dts: rockchip: Lower SD card speed on rk3399
+ Pinebook Pro
+
+MicroSD card slot in the Pinebook Pro is located on a separate
+daughterboard that's connected to the mainboard using a rather
+long flat cable.  The resulting signal degradation causes many
+perfectly fine microSD cards not to work in the Pinebook Pro,
+which is a common source of frustration among the owners.
+
+Changing the mode and lowering the speed reportedly fixes this
+issue and makes many microSD cards work as expected.
+
+Co-developed-by: Dragan Simic <dragan.simic@gmail.com>
+Signed-off-by: Dragan Simic <dragan.simic@gmail.com>
+Tested-by: JR Gonzalez <jrg@scientiam.org>
+Signed-off-by: Dan Johansen <strit@manjaro.org>
+Link: https://lore.kernel.org/r/20230305104730.15849-1-strit@manjaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -943,7 +943,7 @@
+ 	disable-wp;
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_bus4>;
+-	sd-uhs-sdr104;
++	sd-uhs-sdr50;
+ 	vmmc-supply = <&vcc3v0_sd>;
+ 	vqmmc-supply = <&vcc_sdio>;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/127-arm64-dts-rockchip-Add-sdmmc-node-to-rk3588.patch b/target/linux/rockchip/patches-6.1/127-arm64-dts-rockchip-Add-sdmmc-node-to-rk3588.patch
new file mode 100644
index 00000000000..74358bd103e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/127-arm64-dts-rockchip-Add-sdmmc-node-to-rk3588.patch
@@ -0,0 +1,41 @@
+From 09f20610b2f3fd00408004c92494c6e56f60a015 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 28 Feb 2023 10:36:10 +0000
+Subject: [PATCH 127/383] arm64: dts: rockchip: Add sdmmc node to rk3588
+
+Add SD Card node for RK3588s and RK3588.
+
+Co-developed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Link: https://lore.kernel.org/r/20230228103610.25108-1-lucas.tanure@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1099,6 +1099,21 @@
+ 		};
+ 	};
+ 
++	sdmmc: mmc@fe2c0000 {
++		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
++		reg = <0x0 0xfe2c0000 0x0 0x4000>;
++		interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&scmi_clk SCMI_HCLK_SD>, <&scmi_clk SCMI_CCLK_SD>,
++			 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
++		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		fifo-depth = <0x100>;
++		max-frequency = <200000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sdmmc_clk &sdmmc_cmd &sdmmc_det &sdmmc_bus4>;
++		power-domains = <&power RK3588_PD_SDMMC>;
++		status = "disabled";
++	};
++
+ 	sdhci: mmc@fe2e0000 {
+ 		compatible = "rockchip,rk3588-dwcmshc";
+ 		reg = <0x0 0xfe2e0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-6.1/128-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-C.patch b/target/linux/rockchip/patches-6.1/128-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-C.patch
new file mode 100644
index 00000000000..ee121b7afe0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/128-arm64-dts-rockchip-Enable-USB-OTG-for-rk3566-Radxa-C.patch
@@ -0,0 +1,34 @@
+From ddbf1a97819e2baa63d833d2a606bbb267d87f1b Mon Sep 17 00:00:00 2001
+From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Date: Thu, 23 Feb 2023 19:29:29 +0530
+Subject: [PATCH 128/383] arm64: dts: rockchip: Enable USB OTG for rk3566 Radxa
+ CM3
+
+Enable USB OTG support for Radxa Compute Module 3 IO Board
+
+Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
+Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
+Link: https://lore.kernel.org/r/20230223135929.630787-1-abbaraju.manojsai@amarulasolutions.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
+@@ -254,6 +254,14 @@
+ 	status = "okay";
+ };
+ 
++&usb2phy0_otg {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	status = "okay";
++};
++
+ &vop {
+ 	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+ 	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
diff --git a/target/linux/rockchip/patches-6.1/129-arm64-dts-rockchip-Add-display-support-to-Odroid-Go-.patch b/target/linux/rockchip/patches-6.1/129-arm64-dts-rockchip-Add-display-support-to-Odroid-Go-.patch
new file mode 100644
index 00000000000..51069f9f227
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/129-arm64-dts-rockchip-Add-display-support-to-Odroid-Go-.patch
@@ -0,0 +1,31 @@
+From 88f7d5f4fe56051fd293370ccec2a474d1e51a0b Mon Sep 17 00:00:00 2001
+From: Maya Matuszczyk <maccraft123mc@gmail.com>
+Date: Mon, 13 Feb 2023 16:38:16 +0100
+Subject: [PATCH 129/383] arm64: dts: rockchip: Add display support to Odroid
+ Go Super
+
+Note that orientation property in ST7701 driver is currently missing,
+And that ST7701 panel driver uses different regulator names compared to
+driver for Elida KD35T133 driver.
+
+Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
+Link: https://lore.kernel.org/r/20230213153816.213526-5-maccraft123mc@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
+@@ -142,7 +142,9 @@
+ };
+ 
+ &internal_display {
+-	status = "disabled";
++	compatible = "elida,kd50t048a", "sitronix,st7701";
++	reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
++	VCC-supply = <&vcc_lcd>;
+ };
+ 
+ &rk817_charger {
diff --git a/target/linux/rockchip/patches-6.1/130-arm64-dts-rockchip-Add-Khadas-edge2-board.patch b/target/linux/rockchip/patches-6.1/130-arm64-dts-rockchip-Add-Khadas-edge2-board.patch
new file mode 100644
index 00000000000..d2ca2db0afd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/130-arm64-dts-rockchip-Add-Khadas-edge2-board.patch
@@ -0,0 +1,69 @@
+From df3613e14a0670b41a682232f17640b5d93c93a4 Mon Sep 17 00:00:00 2001
+From: Yixun Lan <dlan@gentoo.org>
+Date: Wed, 15 Mar 2023 11:34:41 +0800
+Subject: [PATCH 130/383] arm64: dts: rockchip: Add Khadas edge2 board
+
+Edge2 is an ultraslim, credit-card sized ARM PC designed by Khadas.
+
+In this patch, we will add basic device tree support for this board,
+Only eMMC, UART are enabled, so it's capable of booting into
+a basic linux system from eMMC via serial console.
+
+Signed-off-by: Yixun Lan <dlan@gentoo.org>
+Link: https://lore.kernel.org/r/20230315033441.32719-3-dlan@gentoo.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../dts/rockchip/rk3588s-khadas-edge2.dts     | 37 +++++++++++++++++++
+ 2 files changed, 38 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -90,4 +90,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-ro
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-khadas-edge2.dts
+@@ -0,0 +1,37 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3588s.dtsi"
++
++/ {
++	model = "Khadas Edge2";
++	compatible = "khadas,edge2", "rockchip,rk3588s";
++
++	aliases {
++		mmc0 = &sdhci;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	max-frequency = <200000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/131-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch b/target/linux/rockchip/patches-6.1/131-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch
new file mode 100644
index 00000000000..83bac3bba00
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/131-arm64-dts-rockchip-Add-FriendlyElec-Nanopi-R5S.patch
@@ -0,0 +1,757 @@
+From 0f79c66cb5322cabc70b528beba81e81e8d52ca0 Mon Sep 17 00:00:00 2001
+From: Vasily Khoruzhick <anarsoul@gmail.com>
+Date: Tue, 7 Mar 2023 22:32:40 -0800
+Subject: [PATCH 131/383] arm64: dts: rockchip: Add FriendlyElec Nanopi R5S
+
+FriendlyElec Nanopi R5S is an open-sourced mini IoT gateway device.
+
+Board Specifications
+- Rockchip RK3568
+- 2 or 4GB LPDDR4X
+- 8GB or 16GB eMMC, SD card slot
+- GbE LAN (Native)
+- 2x 2.5G LAN (PCIe)
+- M.2 Connector
+- HDMI 2.0, MIPI DSI/CSI
+- 2xUSB 3.0 Host
+- USB Type C PD, 5V/9V/12V
+- GPIO: 12-pin 0.5mm FPC connector
+
+Based on Tianling Shen's <cnsztl@gmail.com> work.
+
+Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
+Link: https://lore.kernel.org/r/20230308063240.107178-2-anarsoul@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3568-nanopi-r5s.dts   | 713 ++++++++++++++++++
+ 2 files changed, 714 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -0,0 +1,713 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ *
++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++	model = "FriendlyElec NanoPi R5S";
++	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
++
++	aliases {
++		ethernet0 = &gmac0;
++		mmc0 = &sdmmc0;
++		mmc1 = &sdhci;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
++
++		led-lan1 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_LAN;
++			function-enumerator = <1>;
++			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-lan2 {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_LAN;
++			function-enumerator = <2>;
++			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
++		};
++
++		power_led: led-power {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_POWER;
++			linux,default-trigger = "heartbeat";
++			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-wan {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_WAN;
++			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
++		};
++	};
++
++	vdd_usbc: vdd-usbc-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd_usbc";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vdd_usbc>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vdd_usbc>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++		startup-delay-us = <200000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_usb: vcc5v0-usb-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vdd_usbc>;
++	};
++
++	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_host_en>;
++		regulator-name = "vcc5v0_usb_host";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_otg_en>;
++		regulator-name = "vcc5v0_usb_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd0v9";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++};
++
++&combphy0 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gmac0 {
++	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>, <&cru CLK_MAC0_2TOP>;
++	assigned-clock-rates = <0>, <125000000>;
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy0>;
++	phy-mode = "rgmii-id";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac0_miim
++		     &gmac0_tx_bus2
++		     &gmac0_rx_bus2
++		     &gmac0_rgmii_clk
++		     &gmac0_rgmii_bus>;
++	snps,reset-gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 15ms, 50ms for rtl8211f */
++	snps,reset-delays-us = <0 15000 50000>;
++	tx_delay = <0x3c>;
++	rx_delay = <0x2f>;
++	status = "okay";
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>;
++		rockchip,system-power-controller;
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		wakeup-source;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-name = "vdd_gpu";
++				regulator-always-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-name = "vdda0v9_image";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <950000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++
++	};
++};
++
++&i2c5 {
++	status = "okay";
++
++	hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <0>;
++		clock-output-names = "rtcic_32kout";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hym8563_int>;
++		wakeup-source;
++	};
++};
++
++&i2s0_8ch {
++	status = "okay";
++};
++
++&i2s1_8ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&mdio0 {
++	rgmii_phy0: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++		pinctrl-0 = <&eth_phy0_reset_pin>;
++		pinctrl-names = "default";
++		reset-assert-us = <10000>;
++		reset-deassert-us = <50000>;
++		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&pcie2x1 {
++	num-lanes = <1>;
++	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++};
++
++&pcie30phy {
++	data-lanes = <1 2>;
++	status = "okay";
++};
++
++&pcie3x1 {
++	num-lanes = <1>;
++	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pcie3x2 {
++	num-lanes = <1>;
++	num-ib-windows = <8>;
++	num-ob-windows = <8>;
++	reset-gpios = <&gpio2 RK_PD6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pinctrl {
++	gmac0 {
++		eth_phy0_reset_pin: eth-phy0-reset-pin {
++			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	gpio-leds {
++		lan1_led_pin: lan1-led-pin {
++			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan2_led_pin: lan2-led-pin {
++			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		power_led_pin: power-led-pin {
++			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wan_led_pin: wan-led-pin {
++			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	hym8563 {
++		hym8563_int: hym8563-int {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic-int {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
++	status = "okay";
++};
++
++&sdmmc0 {
++	max-frequency = <150000000>;
++	no-sdio;
++	no-mmc;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	extcon = <&usb2phy0>;
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/132-arm64-dts-rockchip-add-rk3588-cache-level-informatio.patch b/target/linux/rockchip/patches-6.1/132-arm64-dts-rockchip-add-rk3588-cache-level-informatio.patch
new file mode 100644
index 00000000000..19be66ae3b9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/132-arm64-dts-rockchip-add-rk3588-cache-level-informatio.patch
@@ -0,0 +1,90 @@
+From 2a90aa575ceb94acb70407a08d058af02419e034 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 17 Mar 2023 18:41:02 +0100
+Subject: [PATCH 132/383] arm64: dts: rockchip: add rk3588 cache level
+ information
+
+Add missing, mandatory cache-level information for RK3588.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230317174102.61209-1-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -222,6 +222,7 @@
+ 			cache-size = <131072>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -230,6 +231,7 @@
+ 			cache-size = <131072>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -238,6 +240,7 @@
+ 			cache-size = <131072>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -246,6 +249,7 @@
+ 			cache-size = <131072>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -254,6 +258,7 @@
+ 			cache-size = <524288>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -262,6 +267,7 @@
+ 			cache-size = <524288>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -270,6 +276,7 @@
+ 			cache-size = <524288>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -278,6 +285,7 @@
+ 			cache-size = <524288>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
++			cache-level = <2>;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -286,6 +294,7 @@
+ 			cache-size = <3145728>;
+ 			cache-line-size = <64>;
+ 			cache-sets = <4096>;
++			cache-level = <3>;
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/133-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-.patch b/target/linux/rockchip/patches-6.1/133-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-.patch
new file mode 100644
index 00000000000..ec4c42f6db1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/133-arm64-dts-rockchip-create-common-dtsi-for-NanoPi-R5-.patch
@@ -0,0 +1,1228 @@
+From d4c4f4d2f6ab28eb99fe790dda61b5b24fb3da7a Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 18 Mar 2023 16:37:41 +0800
+Subject: [PATCH 133/383] arm64: dts: rockchip: create common dtsi for NanoPi
+ R5 series
+
+Create common dtsi for the FriendlyElec NanoPi R5 series.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230318083745.6181-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-nanopi-r5s.dts   | 575 +----------------
+ .../boot/dts/rockchip/rk3568-nanopi-r5s.dtsi  | 596 ++++++++++++++++++
+ 2 files changed, 597 insertions(+), 574 deletions(-)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -7,12 +7,7 @@
+  */
+ 
+ /dts-v1/;
+-#include <dt-bindings/gpio/gpio.h>
+-#include <dt-bindings/input/input.h>
+-#include <dt-bindings/leds/common.h>
+-#include <dt-bindings/pinctrl/rockchip.h>
+-#include <dt-bindings/soc/rockchip,vop2.h>
+-#include "rk3568.dtsi"
++#include "rk3568-nanopi-r5s.dtsi"
+ 
+ / {
+ 	model = "FriendlyElec NanoPi R5S";
+@@ -20,23 +15,6 @@
+ 
+ 	aliases {
+ 		ethernet0 = &gmac0;
+-		mmc0 = &sdmmc0;
+-		mmc1 = &sdhci;
+-	};
+-
+-	chosen: chosen {
+-		stdout-path = "serial2:1500000n8";
+-	};
+-
+-	hdmi-con {
+-		compatible = "hdmi-connector";
+-		type = "a";
+-
+-		port {
+-			hdmi_con_in: endpoint {
+-				remote-endpoint = <&hdmi_out_con>;
+-			};
+-		};
+ 	};
+ 
+ 	gpio-leds {
+@@ -71,130 +49,6 @@
+ 			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ 		};
+ 	};
+-
+-	vdd_usbc: vdd-usbc-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vdd_usbc";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-	};
+-
+-	vcc3v3_sys: vcc3v3-sys-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v3_sys";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-		vin-supply = <&vdd_usbc>;
+-	};
+-
+-	vcc5v0_sys: vcc5v0-sys-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_sys";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-		vin-supply = <&vdd_usbc>;
+-	};
+-
+-	vcc3v3_pcie: vcc3v3-pcie-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc3v3_pcie";
+-		regulator-min-microvolt = <3300000>;
+-		regulator-max-microvolt = <3300000>;
+-		enable-active-high;
+-		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
+-		startup-delay-us = <200000>;
+-		vin-supply = <&vcc5v0_sys>;
+-	};
+-
+-	vcc5v0_usb: vcc5v0-usb-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "vcc5v0_usb";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-		vin-supply = <&vdd_usbc>;
+-	};
+-
+-	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
+-		compatible = "regulator-fixed";
+-		enable-active-high;
+-		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&vcc5v0_usb_host_en>;
+-		regulator-name = "vcc5v0_usb_host";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-		vin-supply = <&vcc5v0_usb>;
+-	};
+-
+-	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+-		compatible = "regulator-fixed";
+-		enable-active-high;
+-		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&vcc5v0_usb_otg_en>;
+-		regulator-name = "vcc5v0_usb_otg";
+-		regulator-min-microvolt = <5000000>;
+-		regulator-max-microvolt = <5000000>;
+-		vin-supply = <&vcc5v0_usb>;
+-	};
+-
+-	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "pcie30_avdd0v9";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <900000>;
+-		regulator-max-microvolt = <900000>;
+-		vin-supply = <&vcc3v3_sys>;
+-	};
+-
+-	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
+-		compatible = "regulator-fixed";
+-		regulator-name = "pcie30_avdd1v8";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <1800000>;
+-		regulator-max-microvolt = <1800000>;
+-		vin-supply = <&vcc3v3_sys>;
+-	};
+-};
+-
+-&combphy0 {
+-	status = "okay";
+-};
+-
+-&combphy1 {
+-	status = "okay";
+-};
+-
+-&combphy2 {
+-	status = "okay";
+-};
+-
+-&cpu0 {
+-	cpu-supply = <&vdd_cpu>;
+-};
+-
+-&cpu1 {
+-	cpu-supply = <&vdd_cpu>;
+-};
+-
+-&cpu2 {
+-	cpu-supply = <&vdd_cpu>;
+-};
+-
+-&cpu3 {
+-	cpu-supply = <&vdd_cpu>;
+ };
+ 
+ &gmac0 {
+@@ -219,292 +73,6 @@
+ 	status = "okay";
+ };
+ 
+-&gpu {
+-	mali-supply = <&vdd_gpu>;
+-	status = "okay";
+-};
+-
+-&hdmi {
+-	avdd-0v9-supply = <&vdda0v9_image>;
+-	avdd-1v8-supply = <&vcca1v8_image>;
+-	status = "okay";
+-};
+-
+-&hdmi_in {
+-	hdmi_in_vp0: endpoint {
+-		remote-endpoint = <&vp0_out_hdmi>;
+-	};
+-};
+-
+-&hdmi_out {
+-	hdmi_out_con: endpoint {
+-		remote-endpoint = <&hdmi_con_in>;
+-	};
+-};
+-
+-&hdmi_sound {
+-	status = "okay";
+-};
+-
+-&i2c0 {
+-	status = "okay";
+-
+-	vdd_cpu: regulator@1c {
+-		compatible = "tcs,tcs4525";
+-		reg = <0x1c>;
+-		fcs,suspend-voltage-selector = <1>;
+-		regulator-name = "vdd_cpu";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		regulator-min-microvolt = <800000>;
+-		regulator-max-microvolt = <1150000>;
+-		regulator-ramp-delay = <2300>;
+-		vin-supply = <&vcc5v0_sys>;
+-
+-		regulator-state-mem {
+-			regulator-off-in-suspend;
+-		};
+-	};
+-
+-	rk809: pmic@20 {
+-		compatible = "rockchip,rk809";
+-		reg = <0x20>;
+-		interrupt-parent = <&gpio0>;
+-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+-		#clock-cells = <1>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&pmic_int>;
+-		rockchip,system-power-controller;
+-		vcc1-supply = <&vcc3v3_sys>;
+-		vcc2-supply = <&vcc3v3_sys>;
+-		vcc3-supply = <&vcc3v3_sys>;
+-		vcc4-supply = <&vcc3v3_sys>;
+-		vcc5-supply = <&vcc3v3_sys>;
+-		vcc6-supply = <&vcc3v3_sys>;
+-		vcc7-supply = <&vcc3v3_sys>;
+-		vcc8-supply = <&vcc3v3_sys>;
+-		vcc9-supply = <&vcc3v3_sys>;
+-		wakeup-source;
+-
+-		regulators {
+-			vdd_logic: DCDC_REG1 {
+-				regulator-name = "vdd_logic";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-init-microvolt = <900000>;
+-				regulator-initial-mode = <0x2>;
+-				regulator-min-microvolt = <500000>;
+-				regulator-max-microvolt = <1350000>;
+-				regulator-ramp-delay = <6001>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vdd_gpu: DCDC_REG2 {
+-				regulator-name = "vdd_gpu";
+-				regulator-always-on;
+-				regulator-init-microvolt = <900000>;
+-				regulator-initial-mode = <0x2>;
+-				regulator-min-microvolt = <500000>;
+-				regulator-max-microvolt = <1350000>;
+-				regulator-ramp-delay = <6001>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vcc_ddr: DCDC_REG3 {
+-				regulator-name = "vcc_ddr";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-initial-mode = <0x2>;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-				};
+-			};
+-
+-			vdd_npu: DCDC_REG4 {
+-				regulator-name = "vdd_npu";
+-				regulator-init-microvolt = <900000>;
+-				regulator-initial-mode = <0x2>;
+-				regulator-min-microvolt = <500000>;
+-				regulator-max-microvolt = <1350000>;
+-				regulator-ramp-delay = <6001>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vcc_1v8: DCDC_REG5 {
+-				regulator-name = "vcc_1v8";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vdda0v9_image: LDO_REG1 {
+-				regulator-name = "vdda0v9_image";
+-				regulator-min-microvolt = <950000>;
+-				regulator-max-microvolt = <950000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vdda_0v9: LDO_REG2 {
+-				regulator-name = "vdda_0v9";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <900000>;
+-				regulator-max-microvolt = <900000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vdda0v9_pmu: LDO_REG3 {
+-				regulator-name = "vdda0v9_pmu";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <900000>;
+-				regulator-max-microvolt = <900000>;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <900000>;
+-				};
+-			};
+-
+-			vccio_acodec: LDO_REG4 {
+-				regulator-name = "vccio_acodec";
+-				regulator-always-on;
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vccio_sd: LDO_REG5 {
+-				regulator-name = "vccio_sd";
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <3300000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vcc3v3_pmu: LDO_REG6 {
+-				regulator-name = "vcc3v3_pmu";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <3300000>;
+-				regulator-max-microvolt = <3300000>;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <3300000>;
+-				};
+-			};
+-
+-			vcca_1v8: LDO_REG7 {
+-				regulator-name = "vcca_1v8";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vcca1v8_pmu: LDO_REG8 {
+-				regulator-name = "vcca1v8_pmu";
+-				regulator-always-on;
+-				regulator-boot-on;
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-
+-				regulator-state-mem {
+-					regulator-on-in-suspend;
+-					regulator-suspend-microvolt = <1800000>;
+-				};
+-			};
+-
+-			vcca1v8_image: LDO_REG9 {
+-				regulator-name = "vcca1v8_image";
+-				regulator-min-microvolt = <1800000>;
+-				regulator-max-microvolt = <1800000>;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vcc_3v3: SWITCH_REG1 {
+-				regulator-name = "vcc_3v3";
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-
+-			vcc3v3_sd: SWITCH_REG2 {
+-				regulator-name = "vcc3v3_sd";
+-				regulator-always-on;
+-				regulator-boot-on;
+-
+-				regulator-state-mem {
+-					regulator-off-in-suspend;
+-				};
+-			};
+-		};
+-
+-	};
+-};
+-
+-&i2c5 {
+-	status = "okay";
+-
+-	hym8563: rtc@51 {
+-		compatible = "haoyu,hym8563";
+-		reg = <0x51>;
+-		interrupt-parent = <&gpio0>;
+-		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
+-		#clock-cells = <0>;
+-		clock-output-names = "rtcic_32kout";
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&hym8563_int>;
+-		wakeup-source;
+-	};
+-};
+-
+-&i2s0_8ch {
+-	status = "okay";
+-};
+-
+-&i2s1_8ch {
+-	rockchip,trcm-sync-tx-only;
+-	status = "okay";
+-};
+-
+ &mdio0 {
+ 	rgmii_phy0: ethernet-phy@1 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+@@ -568,146 +136,5 @@
+ 			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+-
+-	hym8563 {
+-		hym8563_int: hym8563-int {
+-			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
+-		};
+-	};
+-
+-	pmic {
+-		pmic_int: pmic-int {
+-			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+-		};
+-	};
+-
+-	usb {
+-		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
+-			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-
+-		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
+-			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-	};
+-};
+-
+-&pmu_io_domains {
+-	pmuio1-supply = <&vcc3v3_pmu>;
+-	pmuio2-supply = <&vcc3v3_pmu>;
+-	vccio1-supply = <&vccio_acodec>;
+-	vccio3-supply = <&vccio_sd>;
+-	vccio4-supply = <&vcc_1v8>;
+-	vccio5-supply = <&vcc_3v3>;
+-	vccio6-supply = <&vcc_1v8>;
+-	vccio7-supply = <&vcc_3v3>;
+-	status = "okay";
+-};
+-
+-&saradc {
+-	vref-supply = <&vcca_1v8>;
+-	status = "okay";
+-};
+-
+-&sdhci {
+-	bus-width = <8>;
+-	max-frequency = <200000000>;
+-	non-removable;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
+-	status = "okay";
+-};
+-
+-&sdmmc0 {
+-	max-frequency = <150000000>;
+-	no-sdio;
+-	no-mmc;
+-	bus-width = <4>;
+-	cap-mmc-highspeed;
+-	cap-sd-highspeed;
+-	disable-wp;
+-	vmmc-supply = <&vcc3v3_sd>;
+-	vqmmc-supply = <&vccio_sd>;
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+-	status = "okay";
+-};
+-
+-&tsadc {
+-	rockchip,hw-tshut-mode = <1>;
+-	rockchip,hw-tshut-polarity = <0>;
+-	status = "okay";
+-};
+-
+-&uart2 {
+-	status = "okay";
+-};
+-
+-&usb_host0_ehci {
+-	status = "okay";
+-};
+-
+-&usb_host0_ohci {
+-	status = "okay";
+-};
+-
+-&usb_host0_xhci {
+-	extcon = <&usb2phy0>;
+-	dr_mode = "host";
+-	status = "okay";
+-};
+-
+-&usb_host1_ehci {
+-	status = "okay";
+-};
+-
+-&usb_host1_ohci {
+-	status = "okay";
+ };
+ 
+-&usb_host1_xhci {
+-	status = "okay";
+-};
+-
+-&usb2phy0 {
+-	status = "okay";
+-};
+-
+-&usb2phy0_host {
+-	phy-supply = <&vcc5v0_usb_host>;
+-	status = "okay";
+-};
+-
+-&usb2phy0_otg {
+-	status = "okay";
+-};
+-
+-&usb2phy1 {
+-	status = "okay";
+-};
+-
+-&usb2phy1_host {
+-	phy-supply = <&vcc5v0_usb_otg>;
+-	status = "okay";
+-};
+-
+-&usb2phy1_otg {
+-	status = "okay";
+-};
+-
+-&vop {
+-	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
+-	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
+-	status = "okay";
+-};
+-
+-&vop_mmu {
+-	status = "okay";
+-};
+-
+-&vp0 {
+-	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
+-		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
+-		remote-endpoint = <&hdmi_in_vp0>;
+-	};
+-};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+@@ -0,0 +1,596 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ *
++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++	aliases {
++		mmc0 = &sdmmc0;
++		mmc1 = &sdhci;
++	};
++
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	hdmi-con {
++		compatible = "hdmi-connector";
++		type = "a";
++
++		port {
++			hdmi_con_in: endpoint {
++				remote-endpoint = <&hdmi_out_con>;
++			};
++		};
++	};
++
++	vdd_usbc: vdd-usbc-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vdd_usbc";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vdd_usbc>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vdd_usbc>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		enable-active-high;
++		gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++		startup-delay-us = <200000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_usb: vcc5v0-usb-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vdd_usbc>;
++	};
++
++	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA6 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_host_en>;
++		regulator-name = "vcc5v0_usb_host";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_otg_en>;
++		regulator-name = "vcc5v0_usb_otg";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	pcie30_avdd0v9: pcie30-avdd0v9-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd0v9";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <900000>;
++		regulator-max-microvolt = <900000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++
++	pcie30_avdd1v8: pcie30-avdd1v8-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie30_avdd1v8";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys>;
++	};
++};
++
++&combphy0 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&combphy2 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&hdmi {
++	avdd-0v9-supply = <&vdda0v9_image>;
++	avdd-1v8-supply = <&vcca1v8_image>;
++	status = "okay";
++};
++
++&hdmi_in {
++	hdmi_in_vp0: endpoint {
++		remote-endpoint = <&vp0_out_hdmi>;
++	};
++};
++
++&hdmi_out {
++	hdmi_out_con: endpoint {
++		remote-endpoint = <&hdmi_con_in>;
++	};
++};
++
++&hdmi_sound {
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>;
++		rockchip,system-power-controller;
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		wakeup-source;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-name = "vdd_gpu";
++				regulator-always-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-name = "vdda0v9_image";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <950000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++
++	};
++};
++
++&i2c5 {
++	status = "okay";
++
++	hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PD3 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <0>;
++		clock-output-names = "rtcic_32kout";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hym8563_int>;
++		wakeup-source;
++	};
++};
++
++&i2s0_8ch {
++	status = "okay";
++};
++
++&i2s1_8ch {
++	rockchip,trcm-sync-tx-only;
++	status = "okay";
++};
++
++&pcie30phy {
++	data-lanes = <1 2>;
++	status = "okay";
++};
++
++&pinctrl {
++	hym8563 {
++		hym8563_int: hym8563-int {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic-int {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb_host_en: vcc5v0-usb-host-en {
++			rockchip,pins = <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd>;
++	status = "okay";
++};
++
++&sdmmc0 {
++	max-frequency = <150000000>;
++	no-sdio;
++	no-mmc;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	extcon = <&usb2phy0>;
++	dr_mode = "host";
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	status = "okay";
++};
++
++&usb2phy1 {
++	status = "okay";
++};
++
++&usb2phy1_host {
++	phy-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
++};
++
++&usb2phy1_otg {
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
++
++&vp0 {
++	vp0_out_hdmi: endpoint@ROCKCHIP_VOP2_EP_HDMI0 {
++		reg = <ROCKCHIP_VOP2_EP_HDMI0>;
++		remote-endpoint = <&hdmi_in_vp0>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/134-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch b/target/linux/rockchip/patches-6.1/134-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch
new file mode 100644
index 00000000000..e474edf2a6d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/134-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R5C.patch
@@ -0,0 +1,154 @@
+From 89148f6f48c81638e0cc875eb233ac25ce4bb218 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 18 Mar 2023 16:37:43 +0800
+Subject: [PATCH 134/383] arm64: dts: rockchip: Add FriendlyARM NanoPi R5C
+
+FriendlyARM NanoPi R5C is an open-sourced mini IoT gateway device.
+
+Specification:
+- Rockchip RK3568
+- 1/4GB LPDDR4X RAM
+- 8/32GB eMMC
+- SD card slot
+- M.2 Connector
+- 2x USB 3.0 Port
+- 2x 2500 Base-T (PCIe, r8125)
+- HDMI 2.0
+- MIPI DSI/CSI
+- USB Type C 5V
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230318083745.6181-4-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3568-nanopi-r5c.dts   | 112 ++++++++++++++++++
+ 2 files changed, 113 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -84,6 +84,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+@@ -0,0 +1,112 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ *
++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3568-nanopi-r5s.dtsi"
++
++/ {
++	model = "FriendlyElec NanoPi R5C";
++	compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&reset_button_pin>;
++
++		button-reset {
++			debounce-interval = <50>;
++			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
++
++		led-lan {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_LAN;
++			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
++		};
++
++		power_led: led-power {
++			color = <LED_COLOR_ID_RED>;
++			function = LED_FUNCTION_POWER;
++			linux,default-trigger = "heartbeat";
++			gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-wan {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_WAN;
++			gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
++		};
++
++		led-wlan {
++			color = <LED_COLOR_ID_GREEN>;
++			function = LED_FUNCTION_WLAN;
++			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
++		};
++	};
++};
++
++&pcie2x1 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&pcie20_reset_pin>;
++	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
++	status = "okay";
++};
++
++&pcie3x1 {
++	num-lanes = <1>;
++	reset-gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pcie3x2 {
++	num-lanes = <1>;
++	reset-gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pinctrl {
++	gpio-leds {
++		lan_led_pin: lan-led-pin {
++			rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		power_led_pin: power-led-pin {
++			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wan_led_pin: wan-led-pin {
++			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wlan_led_pin: wlan-led-pin {
++			rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pcie {
++		pcie20_reset_pin: pcie20-reset-pin {
++			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	rockchip-key {
++		reset_button_pin: reset-button-pin {
++			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/135-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch b/target/linux/rockchip/patches-6.1/135-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch
new file mode 100644
index 00000000000..6ebc7e3e5bb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/135-arm64-dts-rockchip-fix-gmac-support-for-NanoPi-R5S.patch
@@ -0,0 +1,50 @@
+From 3c1ea479e5e18645315760fb75ddd81ab16ccfb5 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 18 Mar 2023 16:37:44 +0800
+Subject: [PATCH 135/383] arm64: dts: rockchip: fix gmac support for NanoPi R5S
+
+- Changed phy-mode to rgmii.
+
+- Fixed pull type in pinctrl for gmac0.
+
+- Removed duplicate properties in mdio node.
+  These properties are defined in the gmac0 node already.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230318083745.6181-5-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 7 ++-----
+ 1 file changed, 2 insertions(+), 5 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -57,7 +57,7 @@
+ 	assigned-clock-rates = <0>, <125000000>;
+ 	clock_in_out = "output";
+ 	phy-handle = <&rgmii_phy0>;
+-	phy-mode = "rgmii-id";
++	phy-mode = "rgmii";
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac0_miim
+ 		     &gmac0_tx_bus2
+@@ -79,9 +79,6 @@
+ 		reg = <1>;
+ 		pinctrl-0 = <&eth_phy0_reset_pin>;
+ 		pinctrl-names = "default";
+-		reset-assert-us = <10000>;
+-		reset-deassert-us = <50000>;
+-		reset-gpios = <&gpio0 RK_PC4 GPIO_ACTIVE_LOW>;
+ 	};
+ };
+ 
+@@ -115,7 +112,7 @@
+ &pinctrl {
+ 	gmac0 {
+ 		eth_phy0_reset_pin: eth-phy0-reset-pin {
+-			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_down>;
++			rockchip,pins = <0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/136-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-Nano.patch b/target/linux/rockchip/patches-6.1/136-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-Nano.patch
new file mode 100644
index 00000000000..a4e4e9e0986
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/136-arm64-dts-rockchip-remove-I2S1-TDM-node-for-the-Nano.patch
@@ -0,0 +1,40 @@
+From dbef06e05d620ef35c670f9b1433f4bb05185499 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 18 Mar 2023 16:37:45 +0800
+Subject: [PATCH 136/383] arm64: dts: rockchip: remove I2S1 TDM node for the
+ NanoPi R5 series
+
+This is for the audio output which does not exist on the boards.
+Also disable regulator-always-on for vccio_acodec since it's only
+used by the audio output.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230318083745.6181-6-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi | 6 ------
+ 1 file changed, 6 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dtsi
+@@ -330,7 +330,6 @@
+ 
+ 			vccio_acodec: LDO_REG4 {
+ 				regulator-name = "vccio_acodec";
+-				regulator-always-on;
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 
+@@ -441,11 +440,6 @@
+ 	status = "okay";
+ };
+ 
+-&i2s1_8ch {
+-	rockchip,trcm-sync-tx-only;
+-	status = "okay";
+-};
+-
+ &pcie30phy {
+ 	data-lanes = <1 2>;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/137-arm64-dts-rockchip-fix-px30-lvds-node.patch b/target/linux/rockchip/patches-6.1/137-arm64-dts-rockchip-fix-px30-lvds-node.patch
new file mode 100644
index 00000000000..1b7e0de6a23
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/137-arm64-dts-rockchip-fix-px30-lvds-node.patch
@@ -0,0 +1,39 @@
+From c25db3e701a6675f9210979adcb8eefff62ed61a Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:31:22 +0100
+Subject: [PATCH 137/383] arm64: dts: rockchip: fix px30 lvds node
+
+With the conversion of rockchip,lvds.yaml a port@1 node
+is required, so add a node with label lvds_out.
+Also add label lvds_in to port@0.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/99895a4b-25c4-4b64-42ac-6f70940ab56e@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
+@@ -474,7 +474,7 @@
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+ 
+-				port@0 {
++				lvds_in: port@0 {
+ 					reg = <0>;
+ 					#address-cells = <1>;
+ 					#size-cells = <0>;
+@@ -489,6 +489,10 @@
+ 						remote-endpoint = <&vopl_out_lvds>;
+ 					};
+ 				};
++
++				lvds_out: port@1 {
++					reg = <1>;
++				};
+ 			};
+ 		};
+ 	};
diff --git a/target/linux/rockchip/patches-6.1/138-arm64-dts-rockchip-fix-px30-dsi-node.patch b/target/linux/rockchip/patches-6.1/138-arm64-dts-rockchip-fix-px30-dsi-node.patch
new file mode 100644
index 00000000000..b4a1e858892
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/138-arm64-dts-rockchip-fix-px30-dsi-node.patch
@@ -0,0 +1,39 @@
+From c12b0800b6142ca203bba89fba0ce7bcf63dc2cb Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:31:52 +0100
+Subject: [PATCH 138/383] arm64: dts: rockchip: fix px30 dsi node
+
+With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node
+is required, so add a node with label dsi_out.
+Also add label dsi_in to port@0.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/1ee3e676-aef4-f464-82b0-8fb39ba5c60d@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/px30.dtsi | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/px30.dtsi
++++ b/arch/arm64/boot/dts/rockchip/px30.dtsi
+@@ -1138,7 +1138,7 @@
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
+ 
+-			port@0 {
++			dsi_in: port@0 {
+ 				reg = <0>;
+ 				#address-cells = <1>;
+ 				#size-cells = <0>;
+@@ -1153,6 +1153,10 @@
+ 					remote-endpoint = <&vopl_out_dsi>;
+ 				};
+ 			};
++
++			dsi_out: port@1 {
++				reg = <1>;
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/139-arm64-dts-rockchip-fix-rk3399-dsi-node.patch b/target/linux/rockchip/patches-6.1/139-arm64-dts-rockchip-fix-rk3399-dsi-node.patch
new file mode 100644
index 00000000000..d0e3edc994c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/139-arm64-dts-rockchip-fix-rk3399-dsi-node.patch
@@ -0,0 +1,62 @@
+From d31d4d1aa41eadca15589d78168c41abce5a2413 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:32:22 +0100
+Subject: [PATCH 139/383] arm64: dts: rockchip: fix rk3399 dsi node
+
+Use generic node name for rk3399.dtsi dsi node.
+With the conversion of rockchip,dw-mipi-dsi.yaml a port@1 node
+is required, so add a node with label mipi_out.
+Also restyle.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/1e019e9e-a8da-3d57-2770-f6b81bbbf591@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1956,7 +1956,7 @@
+ 		};
+ 	};
+ 
+-	mipi_dsi: mipi@ff960000 {
++	mipi_dsi: dsi@ff960000 {
+ 		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+ 		reg = <0x0 0xff960000 0x0 0x8000>;
+ 		interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
+@@ -1984,15 +1984,20 @@
+ 					reg = <0>;
+ 					remote-endpoint = <&vopb_out_mipi>;
+ 				};
++
+ 				mipi_in_vopl: endpoint@1 {
+ 					reg = <1>;
+ 					remote-endpoint = <&vopl_out_mipi>;
+ 				};
+ 			};
++
++			mipi_out: port@1 {
++				reg = <1>;
++			};
+ 		};
+ 	};
+ 
+-	mipi_dsi1: mipi@ff968000 {
++	mipi_dsi1: dsi@ff968000 {
+ 		compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
+ 		reg = <0x0 0xff968000 0x0 0x8000>;
+ 		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
+@@ -2027,6 +2032,10 @@
+ 					remote-endpoint = <&vopl_out_mipi1>;
+ 				};
+ 			};
++
++			mipi1_out: port@1 {
++				reg = <1>;
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/140-arm64-dts-rockchip-fix-rk3399-dp-node.patch b/target/linux/rockchip/patches-6.1/140-arm64-dts-rockchip-fix-rk3399-dp-node.patch
new file mode 100644
index 00000000000..8f01bc32beb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/140-arm64-dts-rockchip-fix-rk3399-dp-node.patch
@@ -0,0 +1,48 @@
+From d46c8d56170e8ac81e41ffbe4614793070d7c24f Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:32:52 +0100
+Subject: [PATCH 140/383] arm64: dts: rockchip: fix rk3399 dp node
+
+Use generic node name for rk3399.dtsi dp node.
+With the conversion of rockchip,analogix-dp.yaml a port@1 node
+is required, so add a node with label edp_out.
+Also restyle.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/f6008819-db9b-0944-3f5b-5522b7cd8a8d@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 7 ++++++-
+ 1 file changed, 6 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -2039,7 +2039,7 @@
+ 		};
+ 	};
+ 
+-	edp: edp@ff970000 {
++	edp: dp@ff970000 {
+ 		compatible = "rockchip,rk3399-edp";
+ 		reg = <0x0 0xff970000 0x0 0x8000>;
+ 		interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+@@ -2056,6 +2056,7 @@
+ 		ports {
+ 			#address-cells = <1>;
+ 			#size-cells = <0>;
++
+ 			edp_in: port@0 {
+ 				reg = <0>;
+ 				#address-cells = <1>;
+@@ -2071,6 +2072,10 @@
+ 					remote-endpoint = <&vopl_out_edp>;
+ 				};
+ 			};
++
++			edp_out: port@1 {
++				reg = <1>;
++			};
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/141-arm64-dts-rockchip-rename-vbus-supply-to-phy-supply-.patch b/target/linux/rockchip/patches-6.1/141-arm64-dts-rockchip-rename-vbus-supply-to-phy-supply-.patch
new file mode 100644
index 00000000000..ba6e6c55454
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/141-arm64-dts-rockchip-rename-vbus-supply-to-phy-supply-.patch
@@ -0,0 +1,28 @@
+From 686856ab04d1115c5eac7cb82db933fbfd00e375 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:33:22 +0100
+Subject: [PATCH 141/383] arm64: dts: rockchip: rename vbus-supply to
+ phy-supply in rk3566-box-demo.dts
+
+'vbus-supply' does not match any of the regexes in rk3566-box-demo.dts
+in the usb2phy0_otg node, so rename vbus-supply to phy-supply.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/1889d8ee-e119-4a52-33a1-b990a41a137c@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-box-demo.dts
+@@ -495,7 +495,7 @@
+ };
+ 
+ &usb2phy0_otg {
+-	vbus-supply = <&vcc5v0_usb2_otg>;
++	phy-supply = <&vcc5v0_usb2_otg>;
+ 	status = "okay";
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/142-arm64-dts-rockchip-remove-hclk-from-dsi-node-on-rk35.patch b/target/linux/rockchip/patches-6.1/142-arm64-dts-rockchip-remove-hclk-from-dsi-node-on-rk35.patch
new file mode 100644
index 00000000000..49dd1168338
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/142-arm64-dts-rockchip-remove-hclk-from-dsi-node-on-rk35.patch
@@ -0,0 +1,41 @@
+From 4679a2891b7e97702281e7e2c65346750aa13bf6 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:33:49 +0100
+Subject: [PATCH 142/383] arm64: dts: rockchip: remove hclk from dsi node on
+ rk356x
+
+The hclk is not used in the dw-mipi-dsi binding,
+so remove hclk from the rk356x.dtsi dsi node.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Link: https://lore.kernel.org/r/4df211eb-4fcd-ee20-48a1-ce7712de552c@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -744,8 +744,8 @@
+ 		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+ 		reg = <0x00 0xfe060000 0x00 0x10000>;
+ 		interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
+-		clock-names = "pclk", "hclk";
+-		clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
++		clock-names = "pclk";
++		clocks = <&cru PCLK_DSITX_0>;
+ 		phy-names = "dphy";
+ 		phys = <&dsi_dphy0>;
+ 		power-domains = <&power RK3568_PD_VO>;
+@@ -772,8 +772,8 @@
+ 		compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
+ 		reg = <0x0 0xfe070000 0x0 0x10000>;
+ 		interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
+-		clock-names = "pclk", "hclk";
+-		clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
++		clock-names = "pclk";
++		clocks = <&cru PCLK_DSITX_1>;
+ 		phy-names = "dphy";
+ 		phys = <&dsi_dphy1>;
+ 		power-domains = <&power RK3568_PD_VO>;
diff --git a/target/linux/rockchip/patches-6.1/143-arm64-dts-rockchip-Enable-watchdog-support-for-RK358.patch b/target/linux/rockchip/patches-6.1/143-arm64-dts-rockchip-Enable-watchdog-support-for-RK358.patch
new file mode 100644
index 00000000000..15b888658fe
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/143-arm64-dts-rockchip-Enable-watchdog-support-for-RK358.patch
@@ -0,0 +1,33 @@
+From 14552b6a5f3c13ef73ed6bb9d6c8b56a38548596 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 29 Mar 2023 02:30:47 +0530
+Subject: [PATCH 143/383] arm64: dts: rockchip: Enable watchdog support for
+ RK3588
+
+Add DT node for watchdog support in RK3588.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Link: https://lore.kernel.org/r/20230328210048.195124-2-shreeya.patel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1250,6 +1250,14 @@
+ 		status = "disabled";
+ 	};
+ 
++	wdt: watchdog@feaf0000 {
++		compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
++		reg = <0x0 0xfeaf0000 0x0 0x100>;
++		clocks = <&cru TCLK_WDT0>, <&cru PCLK_WDT0>;
++		clock-names = "tclk", "pclk";
++		interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH 0>;
++	};
++
+ 	spi0: spi@feb00000 {
+ 		compatible = "rockchip,rk3588-spi", "rockchip,rk3066-spi";
+ 		reg = <0x0 0xfeb00000 0x0 0x1000>;
diff --git a/target/linux/rockchip/patches-6.1/144-arm64-dts-rockchip-Add-internal-display-support-to-r.patch b/target/linux/rockchip/patches-6.1/144-arm64-dts-rockchip-Add-internal-display-support-to-r.patch
new file mode 100644
index 00000000000..9faab1dd004
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/144-arm64-dts-rockchip-Add-internal-display-support-to-r.patch
@@ -0,0 +1,162 @@
+From fa5877341e5a4716b550ea13d79792b152cbae69 Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Tue, 28 Mar 2023 09:33:08 +0200
+Subject: [PATCH 144/383] arm64: dts: rockchip: Add internal display support to
+ rk3399-pinephone-pro
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The phone's display is using a Hannstar LCD panel. Support it by adding a
+panel DT node and all needed nodes (backlight, MIPI DSI, regulators, etc).
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Co-developed-by: Kamil Trzciński <ayufan@ayufan.eu>
+Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu>
+Co-developed-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
+Tested-by: Ondrej Jirman <megi@xff.cz>
+Link: https://lore.kernel.org/r/20230328073309.1743112-2-javierm@redhat.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3399-pinephone-pro.dts     | 95 +++++++++++++++++++
+ 1 file changed, 95 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+@@ -29,6 +29,11 @@
+ 		stdout-path = "serial2:115200n8";
+ 	};
+ 
++	backlight: backlight {
++		compatible = "pwm-backlight";
++		pwms = <&pwm0 0 50000 0>;
++	};
++
+ 	gpio-keys {
+ 		compatible = "gpio-keys";
+ 		pinctrl-names = "default";
+@@ -102,6 +107,30 @@
+ 		/* WL_REG_ON on module */
+ 		reset-gpios = <&gpio0 RK_PB2 GPIO_ACTIVE_LOW>;
+ 	};
++
++	/* MIPI DSI panel 1.8v supply */
++	vcc1v8_lcd: vcc1v8-lcd {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		regulator-name = "vcc1v8_lcd";
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&vcc3v3_sys>;
++		gpio = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++	};
++
++	/* MIPI DSI panel 2.8v supply */
++	vcc2v8_lcd: vcc2v8-lcd {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		regulator-name = "vcc2v8_lcd";
++		regulator-min-microvolt = <2800000>;
++		regulator-max-microvolt = <2800000>;
++		vin-supply = <&vcc3v3_sys>;
++		gpio = <&gpio3 RK_PA1 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++	};
+ };
+ 
+ &cpu_alert0 {
+@@ -139,6 +168,11 @@
+ 	status = "okay";
+ };
+ 
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
+ &i2c0 {
+ 	clock-frequency = <400000>;
+ 	i2c-scl-rising-time-ns = <168>;
+@@ -362,6 +396,39 @@
+ 	status = "okay";
+ };
+ 
++&mipi_dsi {
++	status = "okay";
++	clock-master;
++
++	ports {
++		mipi_out: port@1 {
++			#address-cells = <0>;
++			#size-cells = <0>;
++			reg = <1>;
++
++			mipi_out_panel: endpoint {
++				remote-endpoint = <&mipi_in_panel>;
++			};
++		};
++	};
++
++	panel@0 {
++		compatible = "hannstar,hsd060bhw4";
++		reg = <0>;
++		backlight = <&backlight>;
++		reset-gpios = <&gpio4 RK_PD1 GPIO_ACTIVE_LOW>;
++		vcc-supply = <&vcc2v8_lcd>;
++		iovcc-supply = <&vcc1v8_lcd>;
++		pinctrl-names = "default";
++
++		port {
++			mipi_in_panel: endpoint {
++				remote-endpoint = <&mipi_out_panel>;
++			};
++		};
++	};
++};
++
+ &pmu_io_domains {
+ 	pmu1830-supply = <&vcc_1v8>;
+ 	status = "okay";
+@@ -429,6 +496,10 @@
+ 	status = "okay";
+ };
+ 
++&pwm0 {
++	status = "okay";
++};
++
+ &sdmmc {
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
+@@ -479,3 +550,27 @@
+ &uart2 {
+ 	status = "okay";
+ };
++
++&vopb {
++	status = "okay";
++	assigned-clocks = <&cru DCLK_VOP0_DIV>, <&cru DCLK_VOP0>,
++			  <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
++	assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
++	assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP0_DIV>;
++};
++
++&vopb_mmu {
++	status = "okay";
++};
++
++&vopl {
++	status = "okay";
++	assigned-clocks = <&cru DCLK_VOP1_DIV>, <&cru DCLK_VOP1>,
++			  <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
++	assigned-clock-rates = <0>, <0>, <400000000>, <100000000>;
++	assigned-clock-parents = <&cru PLL_GPLL>, <&cru DCLK_VOP1_DIV>;
++};
++
++&vopl_mmu {
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/145-arm64-dts-rockchip-Add-touchscreen-support-to-rk3399.patch b/target/linux/rockchip/patches-6.1/145-arm64-dts-rockchip-Add-touchscreen-support-to-rk3399.patch
new file mode 100644
index 00000000000..4282168c86f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/145-arm64-dts-rockchip-Add-touchscreen-support-to-rk3399.patch
@@ -0,0 +1,52 @@
+From caba6877299a8c0cc9a6e4b4f25c97389e054b19 Mon Sep 17 00:00:00 2001
+From: Martijn Braam <martijn@brixit.nl>
+Date: Tue, 28 Mar 2023 09:33:09 +0200
+Subject: [PATCH 145/383] arm64: dts: rockchip: Add touchscreen support to
+ rk3399-pinephone-pro
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The phone has a Goodix GT1158 touchscreen, add a DT node for it.
+
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Co-developed-by: Kamil Trzciński <ayufan@ayufan.eu>
+Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu>
+Co-developed-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
+Link: https://lore.kernel.org/r/20230328073309.1743112-3-javierm@redhat.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3399-pinephone-pro.dts     | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+@@ -367,6 +367,25 @@
+ 	};
+ };
+ 
++&i2c3 {
++	i2c-scl-rising-time-ns = <450>;
++	i2c-scl-falling-time-ns = <15>;
++	status = "okay";
++
++	touchscreen@14 {
++		compatible = "goodix,gt1158";
++		reg = <0x14>;
++		interrupt-parent = <&gpio3>;
++		interrupts = <RK_PB5 IRQ_TYPE_EDGE_RISING>;
++		irq-gpios = <&gpio3 RK_PB5 GPIO_ACTIVE_HIGH>;
++		reset-gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_HIGH>;
++		AVDD28-supply = <&vcc3v0_touch>;
++		VDDIO-supply = <&vcc3v0_touch>;
++		touchscreen-size-x = <720>;
++		touchscreen-size-y = <1440>;
++	};
++};
++
+ &cluster0_opp {
+ 	opp04 {
+ 		status = "disabled";
diff --git a/target/linux/rockchip/patches-6.1/146-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch b/target/linux/rockchip/patches-6.1/146-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch
new file mode 100644
index 00000000000..669d6c2f185
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/146-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C.patch
@@ -0,0 +1,71 @@
+From fb1a87598595d73d2bfab098476f587b29362fda Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 25 Mar 2023 15:40:20 +0800
+Subject: [PATCH 146/383] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C
+
+The NanoPi R2C is a minor variant of NanoPi R2S with the on-board NIC
+chip changed from rtl8211e to yt8521s, and otherwise identical to R2S.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230325074022.9818-3-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../boot/dts/rockchip/rk3328-nanopi-r2c.dts   | 40 +++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -14,6 +14,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go3.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
+@@ -0,0 +1,40 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3328-nanopi-r2s.dts"
++
++/ {
++	model = "FriendlyElec NanoPi R2C";
++	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
++};
++
++&gmac2io {
++	phy-handle = <&yt8521s>;
++	tx_delay = <0x22>;
++	rx_delay = <0x12>;
++
++	mdio {
++		/delete-node/ ethernet-phy@1;
++
++		yt8521s: ethernet-phy@3 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <3>;
++
++			motorcomm,clk-out-frequency-hz = <125000000>;
++			motorcomm,keep-pll-enabled;
++			motorcomm,auto-sleep-disabled;
++
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <10000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/147-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-6.1/147-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch
new file mode 100644
index 00000000000..9f948727fa1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/147-arm64-dts-rockchip-Add-Xunlong-OrangePi-R1-Plus-LTS.patch
@@ -0,0 +1,73 @@
+From 15c6c09f40537d14737612ba8fd9b8de3e6850fa Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 25 Mar 2023 15:40:22 +0800
+Subject: [PATCH 147/383] arm64: dts: rockchip: Add Xunlong OrangePi R1 Plus
+ LTS
+
+The OrangePi R1 Plus LTS is a minor variant of OrangePi R1 Plus with
+the on-board NIC chip changed from rtl8211e to yt8531c, and otherwise
+identical to OrangePi R1 Plus.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230325074022.9818-5-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../rockchip/rk3328-orangepi-r1-plus-lts.dts  | 40 +++++++++++++++++++
+ 2 files changed, 41 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -17,6 +17,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ev
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
+@@ -0,0 +1,40 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
++ * (http://www.orangepi.org)
++ *
++ * Copyright (c) 2021-2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3328-orangepi-r1-plus.dts"
++
++/ {
++	model = "Xunlong Orange Pi R1 Plus LTS";
++	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
++};
++
++&gmac2io {
++	phy-handle = <&yt8531c>;
++	tx_delay = <0x19>;
++	rx_delay = <0x05>;
++
++	mdio {
++		/delete-node/ ethernet-phy@1;
++
++		yt8531c: ethernet-phy@0 {
++			compatible = "ethernet-phy-ieee802.3-c22";
++			reg = <0>;
++
++			motorcomm,clk-out-frequency-hz = <125000000>;
++			motorcomm,keep-pll-enabled;
++			motorcomm,auto-sleep-disabled;
++
++			pinctrl-0 = <&eth_phy_reset_pin>;
++			pinctrl-names = "default";
++			reset-assert-us = <15000>;
++			reset-deassert-us = <50000>;
++			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/148-arm64-dts-rockchip-Add-clk_rtc_32k-to-Anbernic-xx3-D.patch b/target/linux/rockchip/patches-6.1/148-arm64-dts-rockchip-Add-clk_rtc_32k-to-Anbernic-xx3-D.patch
new file mode 100644
index 00000000000..5fb3d2a1118
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/148-arm64-dts-rockchip-Add-clk_rtc_32k-to-Anbernic-xx3-D.patch
@@ -0,0 +1,51 @@
+From 7b268a51ebd90f68bb40844f89ae432bec92cdc1 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Mon, 27 Mar 2023 10:35:47 -0500
+Subject: [PATCH 148/383] arm64: dts: rockchip: Add clk_rtc_32k to Anbernic xx3
+ Devices
+
+For the Anbernic devices to display properly, we need to specify the
+clock frequency of the PLL_VPLL. Adding the parent clock in the
+rk356x.dtsi requires us to update our clock definitions to accomplish
+this.
+
+Fixes: 64b69474edf3 ("arm64: dts: rockchip: assign rate to clk_rtc_32k on rk356x")
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20230327153547.821822-1-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi | 6 ++++--
+ arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts   | 6 ++++--
+ 2 files changed, 8 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
+@@ -16,8 +16,10 @@
+ };
+ 
+ &cru {
+-	assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+-	assigned-clock-rates = <1200000000>, <200000000>, <241500000>;
++	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
++			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
++	assigned-clock-rates = <32768>, <1200000000>,
++			       <200000000>, <241500000>;
+ };
+ 
+ &gpio_keys_control {
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg503.dts
+@@ -105,8 +105,10 @@
+ };
+ 
+ &cru {
+-	assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
+-	assigned-clock-rates = <1200000000>, <200000000>, <500000000>;
++	assigned-clocks = <&pmucru CLK_RTC_32K>, <&cru PLL_GPLL>,
++			  <&pmucru PLL_PPLL>, <&cru PLL_VPLL>;
++	assigned-clock-rates = <32768>, <1200000000>,
++			       <200000000>, <500000000>;
+ };
+ 
+ &dsi_dphy0 {
diff --git a/target/linux/rockchip/patches-6.1/149-arm64-dts-rockchip-Remove-non-existing-pwm-delay-us-.patch b/target/linux/rockchip/patches-6.1/149-arm64-dts-rockchip-Remove-non-existing-pwm-delay-us-.patch
new file mode 100644
index 00000000000..86f8848fe6e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/149-arm64-dts-rockchip-Remove-non-existing-pwm-delay-us-.patch
@@ -0,0 +1,60 @@
+From c11e35a6da6663398bccac7dcd9e4eebfdce73bf Mon Sep 17 00:00:00 2001
+From: Javier Martinez Canillas <javierm@redhat.com>
+Date: Fri, 31 Mar 2023 01:19:23 +0200
+Subject: [PATCH 149/383] arm64: dts: rockchip: Remove non-existing
+ pwm-delay-us property
+
+There is neither a driver that parses this nor a DT binding schema that
+documents it, so let's remove from the DTS files that make use of this.
+
+The properties that exist are post-pwm-on-delay-ms and pwm-off-delay-ms,
+defined in the pwm-backlight DT binding. If the delays are really needed
+then those properties should be used instead.
+
+Brian Norris mentioned though that looking at the first downstream usage
+of the pwm-delay-us property for RK3399 Gru systems in ChromiumOS tree,
+he couldn't find a spec reference that said that this was really needed.
+
+So perhaps it was unnecessary added and a simple removal would be enough.
+
+Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
+Reviewed-by: Brian Norris <briannorris@chromium.org>
+Link: https://lore.kernel.org/r/20230330231924.2404747-1-javierm@redhat.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi            | 1 -
+ arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi | 1 -
+ arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi    | 1 -
+ 3 files changed, 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3368-evb.dtsi
+@@ -61,7 +61,6 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&bl_en>;
+ 		pwms = <&pwm0 0 1000000 PWM_POLARITY_INVERTED>;
+-		pwm-delay-us = <10000>;
+ 	};
+ 
+ 	emmc_pwrseq: emmc-pwrseq {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-chromebook.dtsi
+@@ -198,7 +198,6 @@
+ 		power-supply = <&pp3300_disp>;
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&bl_en>;
+-		pwm-delay-us = <10000>;
+ 	};
+ 
+ 	gpio_keys: gpio-keys {
+--- a/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi
+@@ -167,7 +167,6 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&bl_en>;
+ 		pwms = <&pwm1 0 1000000 0>;
+-		pwm-delay-us = <10000>;
+ 	};
+ 
+ 	dmic: dmic {
diff --git a/target/linux/rockchip/patches-6.1/150-arm64-dts-rockchip-Enable-RTC-support-for-Rock-5B.patch b/target/linux/rockchip/patches-6.1/150-arm64-dts-rockchip-Enable-RTC-support-for-Rock-5B.patch
new file mode 100644
index 00000000000..3257cc99cc9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/150-arm64-dts-rockchip-Enable-RTC-support-for-Rock-5B.patch
@@ -0,0 +1,50 @@
+From 2ab1aada5a2d3a51cd7bfe18ecb1359dc3353db9 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 5 Apr 2023 13:57:11 +0530
+Subject: [PATCH 150/383] arm64: dts: rockchip: Enable RTC support for Rock 5B
+
+Add DT node to enable RTC support for Rock 5B board.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
+Link: https://lore.kernel.org/r/20230405082711.46303-1-shreeya.patel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 25 +++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -27,6 +27,31 @@
+ 	};
+ };
+ 
++&i2c6 {
++	status = "okay";
++
++	hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		clock-output-names = "hym8563";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hym8563_int>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++		wakeup-source;
++	};
++};
++
++&pinctrl {
++	hym8563 {
++		hym8563_int: hym8563-int {
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	no-sdio;
diff --git a/target/linux/rockchip/patches-6.1/151-arm64-dts-rockchip-Add-pwm-fan-to-rk3588-rock-5b.patch b/target/linux/rockchip/patches-6.1/151-arm64-dts-rockchip-Add-pwm-fan-to-rk3588-rock-5b.patch
new file mode 100644
index 00000000000..7d8ac5e36a4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/151-arm64-dts-rockchip-Add-pwm-fan-to-rk3588-rock-5b.patch
@@ -0,0 +1,45 @@
+From cd0096a45cf33db5b4bc903871ec754660b5dab5 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Tue, 4 Apr 2023 20:38:07 +0300
+Subject: [PATCH 151/383] arm64: dts: rockchip: Add pwm-fan to rk3588-rock-5b
+
+Add the necessary DT changes for the Rock 5B board to enable support for
+the PWM controlled heat sink fan.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
+Link: https://lore.kernel.org/r/20230404173807.490520-3-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -17,6 +17,14 @@
+ 		stdout-path = "serial2:1500000n8";
+ 	};
+ 
++	fan: pwm-fan {
++		compatible = "pwm-fan";
++		cooling-levels = <0 95 145 195 255>;
++		fan-supply = <&vcc5v0_sys>;
++		pwms = <&pwm1 0 50000 0>;
++		#cooling-cells = <2>;
++	};
++
+ 	vcc5v0_sys: vcc5v0-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_sys";
+@@ -52,6 +60,10 @@
+ 	};
+ };
+ 
++&pwm1 {
++	status = "okay";
++};
++
+ &sdhci {
+ 	bus-width = <8>;
+ 	no-sdio;
diff --git a/target/linux/rockchip/patches-6.1/152-arm64-dts-rockchip-add-rk3588-thermal-sensor.patch b/target/linux/rockchip/patches-6.1/152-arm64-dts-rockchip-add-rk3588-thermal-sensor.patch
new file mode 100644
index 00000000000..3dd7ad49b33
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/152-arm64-dts-rockchip-add-rk3588-thermal-sensor.patch
@@ -0,0 +1,53 @@
+From 3629ee581f873ab6ed9cf0f47038ba55293d0da7 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 4 Apr 2023 17:44:29 +0200
+Subject: [PATCH 152/383] arm64: dts: rockchip: add rk3588 thermal sensor
+
+Add thermal sensor IP, which allows monitoring temperatures at
+seven different places in the SoC:
+
+* Chip Center
+* CPU Cluster 1 (Dual A76 "Big" Cores)
+* CPU Cluster 2 (Dual A76 "Big" Cores)
+* CPU Cluster 0 (Quad A55 "Little" Cores)
+* Power Domain Center
+* Graphics Processing Unit
+* Neural Processing Unit
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230404154429.51601-1-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 20 ++++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1589,6 +1589,26 @@
+ 		status = "disabled";
+ 	};
+ 
++	tsadc: tsadc@fec00000 {
++		compatible = "rockchip,rk3588-tsadc";
++		reg = <0x0 0xfec00000 0x0 0x400>;
++		interrupts = <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
++		clock-names = "tsadc", "apb_pclk";
++		assigned-clocks = <&cru CLK_TSADC>;
++		assigned-clock-rates = <2000000>;
++		resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>;
++		reset-names = "tsadc-apb", "tsadc";
++		rockchip,hw-tshut-temp = <120000>;
++		rockchip,hw-tshut-mode = <0>; /* tshut mode 0:CRU 1:GPIO */
++		rockchip,hw-tshut-polarity = <0>; /* tshut polarity 0:LOW 1:HIGH */
++		pinctrl-0 = <&tsadc_gpio_func>;
++		pinctrl-1 = <&tsadc_shut>;
++		pinctrl-names = "gpio", "otpout";
++		#thermal-sensor-cells = <1>;
++		status = "disabled";
++	};
++
+ 	i2c6: i2c@fec80000 {
+ 		compatible = "rockchip,rk3588-i2c", "rockchip,rk3399-i2c";
+ 		reg = <0x0 0xfec80000 0x0 0x1000>;
diff --git a/target/linux/rockchip/patches-6.1/153-arm64-dts-rockchip-Fix-SCMI-assigned-clocks-on-rk358.patch b/target/linux/rockchip/patches-6.1/153-arm64-dts-rockchip-Fix-SCMI-assigned-clocks-on-rk358.patch
new file mode 100644
index 00000000000..c299a372627
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/153-arm64-dts-rockchip-Fix-SCMI-assigned-clocks-on-rk358.patch
@@ -0,0 +1,70 @@
+From 2462789ac5edbc4900abd610a8b0d0bd12467e81 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 2 Apr 2023 12:50:50 +0300
+Subject: [PATCH 153/383] arm64: dts: rockchip: Fix SCMI assigned clocks on
+ rk3588s
+
+Since commit df4fdd0db475 ("dt-bindings: firmware: arm,scmi: Restrict
+protocol child node properties") the following dtbs_check warning is
+shown:
+
+  rk3588-rock-5b.dtb: scmi: protocol@14: Unevaluated properties are not
+  allowed ('assigned-clock-rates', 'assigned-clocks' were unexpected)
+
+Because adding the missing properties to firmware/arm,scmi.yaml binding
+document was not an acceptable solution, move SCMI_CLK_CPUB01 and
+SCMI_CLK_CPUB23 assigned clocks to the related CPU nodes and also add
+the missing SCMI_CLK_CPUL.
+
+Additionally, adjust frequency to 816 MHz for all the above mentioned
+assigned clocks, in order to match the firmware defaults.
+
+Suggested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230402095054.384739-2-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 10 ++++++----
+ 1 file changed, 6 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -60,6 +60,8 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <530>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			assigned-clock-rates = <816000000>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <32768>;
+ 			i-cache-line-size = <64>;
+@@ -136,6 +138,8 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <1024>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
++			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
++			assigned-clock-rates = <816000000>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <65536>;
+ 			i-cache-line-size = <64>;
+@@ -174,6 +178,8 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <1024>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
++			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
++			assigned-clock-rates = <816000000>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <65536>;
+ 			i-cache-line-size = <64>;
+@@ -313,10 +319,6 @@
+ 
+ 			scmi_clk: protocol@14 {
+ 				reg = <0x14>;
+-				assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>,
+-						  <&scmi_clk SCMI_CLK_CPUB23>;
+-				assigned-clock-rates = <1200000000>,
+-						       <1200000000>;
+ 				#clock-cells = <1>;
+ 			};
+ 
diff --git a/target/linux/rockchip/patches-6.1/154-arm64-dts-rockchip-Assign-PLL_PPLL-clock-rate-to-1.1.patch b/target/linux/rockchip/patches-6.1/154-arm64-dts-rockchip-Assign-PLL_PPLL-clock-rate-to-1.1.patch
new file mode 100644
index 00000000000..29bd6124e96
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/154-arm64-dts-rockchip-Assign-PLL_PPLL-clock-rate-to-1.1.patch
@@ -0,0 +1,30 @@
+From 8a4582d1cf7c9713af3994d20770a483223213f8 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 2 Apr 2023 12:50:51 +0300
+Subject: [PATCH 154/383] arm64: dts: rockchip: Assign PLL_PPLL clock rate to
+ 1.1 GHz on rk3588s
+
+The clock rate for PLL_PPLL has been wrongly initialized to 100 MHz
+instead of 1.1 GHz. Fix it.
+
+Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
+Reported-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230402095054.384739-3-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -425,7 +425,7 @@
+ 			<&cru ACLK_BUS_ROOT>, <&cru CLK_150M_SRC>,
+ 			<&cru CLK_GPU>;
+ 		assigned-clock-rates =
+-			<100000000>, <786432000>,
++			<1100000000>, <786432000>,
+ 			<850000000>, <1188000000>,
+ 			<702000000>,
+ 			<400000000>, <500000000>,
diff --git a/target/linux/rockchip/patches-6.1/155-arm64-dts-rockchip-Add-rk3588s-I2S-nodes.patch b/target/linux/rockchip/patches-6.1/155-arm64-dts-rockchip-Add-rk3588s-I2S-nodes.patch
new file mode 100644
index 00000000000..9b04ab5fa8a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/155-arm64-dts-rockchip-Add-rk3588s-I2S-nodes.patch
@@ -0,0 +1,186 @@
+From 55cd36ea5741f8a9a5112fc9af8a6f5ea85ecb06 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 2 Apr 2023 12:50:52 +0300
+Subject: [PATCH 155/383] arm64: dts: rockchip: Add rk3588s I2S nodes
+
+There are five I2S/PCM/TDM controllers and two I2S/PCM controllers
+embedded in the RK3588 and RK3588S SoCs.
+
+Add the DT nodes corresponding to the above mentioned Rockchip
+controllers.
+
+Also note RK3588 SoC contains four additional I2S/PCM/TDM controllers,
+which are handled via a separate patch.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230402095054.384739-4-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 148 ++++++++++++++++++++++
+ 1 file changed, 148 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -821,6 +821,57 @@
+ 		};
+ 	};
+ 
++	i2s4_8ch: i2s@fddc0000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfddc0000 0x0 0x1000>;
++		interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S4_8CH_TX>, <&cru MCLK_I2S4_8CH_TX>, <&cru HCLK_I2S4_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S4_8CH_TX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 0>;
++		dma-names = "tx";
++		power-domains = <&power RK3588_PD_VO0>;
++		resets = <&cru SRST_M_I2S4_8CH_TX>;
++		reset-names = "tx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s5_8ch: i2s@fddf0000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfddf0000 0x0 0x1000>;
++		interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S5_8CH_TX>, <&cru MCLK_I2S5_8CH_TX>, <&cru HCLK_I2S5_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S5_8CH_TX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 2>;
++		dma-names = "tx";
++		power-domains = <&power RK3588_PD_VO1>;
++		resets = <&cru SRST_M_I2S5_8CH_TX>;
++		reset-names = "tx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s9_8ch: i2s@fddfc000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfddfc000 0x0 0x1000>;
++		interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S9_8CH_RX>, <&cru MCLK_I2S9_8CH_RX>, <&cru HCLK_I2S9_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S9_8CH_RX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 23>;
++		dma-names = "rx";
++		power-domains = <&power RK3588_PD_VO1>;
++		resets = <&cru SRST_M_I2S9_8CH_RX>;
++		reset-names = "rx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
+ 	qos_gpu_m0: qos@fdf35000 {
+ 		compatible = "rockchip,rk3588-qos", "syscon";
+ 		reg = <0x0 0xfdf35000 0x0 0x20>;
+@@ -1143,6 +1194,103 @@
+ 		status = "disabled";
+ 	};
+ 
++	i2s0_8ch: i2s@fe470000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfe470000 0x0 0x1000>;
++		interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>, <&cru PLL_AUPLL>;
++		dmas = <&dmac0 0>, <&dmac0 1>;
++		dma-names = "tx", "rx";
++		power-domains = <&power RK3588_PD_AUDIO>;
++		resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,trcm-sync-tx-only;
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s0_lrck
++			     &i2s0_sclk
++			     &i2s0_sdi0
++			     &i2s0_sdi1
++			     &i2s0_sdi2
++			     &i2s0_sdi3
++			     &i2s0_sdo0
++			     &i2s0_sdo1
++			     &i2s0_sdo2
++			     &i2s0_sdo3>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s1_8ch: i2s@fe480000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfe480000 0x0 0x1000>;
++		interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>, <&cru HCLK_I2S1_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		dmas = <&dmac0 2>, <&dmac0 3>;
++		dma-names = "tx", "rx";
++		resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
++		reset-names = "tx-m", "rx-m";
++		rockchip,trcm-sync-tx-only;
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s1m0_lrck
++			     &i2s1m0_sclk
++			     &i2s1m0_sdi0
++			     &i2s1m0_sdi1
++			     &i2s1m0_sdi2
++			     &i2s1m0_sdi3
++			     &i2s1m0_sdo0
++			     &i2s1m0_sdo1
++			     &i2s1m0_sdo2
++			     &i2s1m0_sdo3>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s2_2ch: i2s@fe490000 {
++		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
++		reg = <0x0 0xfe490000 0x0 0x1000>;
++		interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
++		clock-names = "i2s_clk", "i2s_hclk";
++		assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac1 0>, <&dmac1 1>;
++		dma-names = "tx", "rx";
++		power-domains = <&power RK3588_PD_AUDIO>;
++		rockchip,trcm-sync-tx-only;
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s2m1_lrck
++			     &i2s2m1_sclk
++			     &i2s2m1_sdi
++			     &i2s2m1_sdo>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s3_2ch: i2s@fe4a0000 {
++		compatible = "rockchip,rk3588-i2s", "rockchip,rk3066-i2s";
++		reg = <0x0 0xfe4a0000 0x0 0x1000>;
++		interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S3_2CH>, <&cru HCLK_I2S3_2CH>;
++		clock-names = "i2s_clk", "i2s_hclk";
++		assigned-clocks = <&cru CLK_I2S3_2CH_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac1 2>, <&dmac1 3>;
++		dma-names = "tx", "rx";
++		power-domains = <&power RK3588_PD_AUDIO>;
++		rockchip,trcm-sync-tx-only;
++		pinctrl-names = "default";
++		pinctrl-0 = <&i2s3_lrck
++			     &i2s3_sclk
++			     &i2s3_sdi
++			     &i2s3_sdo>;
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
+ 	gic: interrupt-controller@fe600000 {
+ 		compatible = "arm,gic-v3";
+ 		reg = <0x0 0xfe600000 0 0x10000>, /* GICD */
diff --git a/target/linux/rockchip/patches-6.1/156-arm64-dts-rockchip-Add-I2S-rk3588-nodes.patch b/target/linux/rockchip/patches-6.1/156-arm64-dts-rockchip-Add-I2S-rk3588-nodes.patch
new file mode 100644
index 00000000000..6d2dbd906b6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/156-arm64-dts-rockchip-Add-I2S-rk3588-nodes.patch
@@ -0,0 +1,96 @@
+From 45e4f004fba8e9989ca760a14c47fd37799bb53b Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 2 Apr 2023 12:50:53 +0300
+Subject: [PATCH 156/383] arm64: dts: rockchip: Add I2S rk3588 nodes
+
+In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM
+controllers shared between the RK3588 and RK3588S SoCs, RK3588 provides
+another group of four I2S/PCM/TDM controllers.
+
+Add the DT nodes corresponding to the additional controllers.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230402095054.384739-5-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 68 ++++++++++++++++++++++++
+ 1 file changed, 68 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -7,6 +7,74 @@
+ #include "rk3588-pinctrl.dtsi"
+ 
+ / {
++	i2s8_8ch: i2s@fddc8000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfddc8000 0x0 0x1000>;
++		interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S8_8CH_TX>, <&cru MCLK_I2S8_8CH_TX>, <&cru HCLK_I2S8_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S8_8CH_TX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 22>;
++		dma-names = "tx";
++		power-domains = <&power RK3588_PD_VO0>;
++		resets = <&cru SRST_M_I2S8_8CH_TX>;
++		reset-names = "tx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s6_8ch: i2s@fddf4000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfddf4000 0x0 0x1000>;
++		interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S6_8CH_TX>, <&cru MCLK_I2S6_8CH_TX>, <&cru HCLK_I2S6_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S6_8CH_TX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 4>;
++		dma-names = "tx";
++		power-domains = <&power RK3588_PD_VO1>;
++		resets = <&cru SRST_M_I2S6_8CH_TX>;
++		reset-names = "tx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s7_8ch: i2s@fddf8000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfddf8000 0x0 0x1000>;
++		interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S7_8CH_RX>, <&cru MCLK_I2S7_8CH_RX>, <&cru HCLK_I2S7_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S7_8CH_RX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 21>;
++		dma-names = "rx";
++		power-domains = <&power RK3588_PD_VO1>;
++		resets = <&cru SRST_M_I2S7_8CH_RX>;
++		reset-names = "rx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
++	i2s10_8ch: i2s@fde00000 {
++		compatible = "rockchip,rk3588-i2s-tdm";
++		reg = <0x0 0xfde00000 0x0 0x1000>;
++		interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru MCLK_I2S10_8CH_RX>, <&cru MCLK_I2S10_8CH_RX>, <&cru HCLK_I2S10_8CH>;
++		clock-names = "mclk_tx", "mclk_rx", "hclk";
++		assigned-clocks = <&cru CLK_I2S10_8CH_RX_SRC>;
++		assigned-clock-parents = <&cru PLL_AUPLL>;
++		dmas = <&dmac2 24>;
++		dma-names = "rx";
++		power-domains = <&power RK3588_PD_VO1>;
++		resets = <&cru SRST_M_I2S10_8CH_RX>;
++		reset-names = "rx-m";
++		#sound-dai-cells = <0>;
++		status = "disabled";
++	};
++
+ 	gmac0: ethernet@fe1b0000 {
+ 		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ 		reg = <0x0 0xfe1b0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-6.1/157-arm64-dts-rockchip-Add-rk3588-rock-5b-analog-audio.patch b/target/linux/rockchip/patches-6.1/157-arm64-dts-rockchip-Add-rk3588-rock-5b-analog-audio.patch
new file mode 100644
index 00000000000..4683737be89
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/157-arm64-dts-rockchip-Add-rk3588-rock-5b-analog-audio.patch
@@ -0,0 +1,107 @@
+From 358d23d0a3b127816ba84a788b242d7a28b1443f Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sun, 2 Apr 2023 12:50:54 +0300
+Subject: [PATCH 157/383] arm64: dts: rockchip: Add rk3588-rock-5b analog audio
+
+Add the necessary DT nodes for the Rock 5B board to enable the analog
+audio support provided by the Everest Semi ES8316 codec.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Reviewed-by: Christopher Obbard <chris.obbard@collabora.com>
+Link: https://lore.kernel.org/r/20230402095054.384739-6-cristian.ciocaltea@collabora.com
+[adapted to the fan addition I applied slightly earlier]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 60 +++++++++++++++++++
+ 1 file changed, 60 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -2,6 +2,7 @@
+ 
+ /dts-v1/;
+ 
++#include <dt-bindings/gpio/gpio.h>
+ #include "rk3588.dtsi"
+ 
+ / {
+@@ -25,6 +26,23 @@
+ 		#cooling-cells = <2>;
+ 	};
+ 
++	sound {
++		compatible = "audio-graph-card";
++		label = "Analog";
++
++		widgets = "Microphone", "Mic Jack",
++			  "Headphone", "Headphones";
++
++		routing = "MIC2", "Mic Jack",
++			  "Headphones", "HPOL",
++			  "Headphones", "HPOR";
++
++		dais = <&i2s0_8ch_p0>;
++		hp-det-gpio = <&gpio1 RK_PD5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&hp_detect>;
++	};
++
+ 	vcc5v0_sys: vcc5v0-sys-regulator {
+ 		compatible = "regulator-fixed";
+ 		regulator-name = "vcc5v0_sys";
+@@ -52,12 +70,54 @@
+ 	};
+ };
+ 
++&i2c7 {
++	status = "okay";
++
++	es8316: es8316@11 {
++		compatible = "everest,es8316";
++		reg = <0x11>;
++		clocks = <&cru I2S0_8CH_MCLKOUT>;
++		clock-names = "mclk";
++		#sound-dai-cells = <0>;
++
++		port {
++			es8316_p0_0: endpoint {
++				remote-endpoint = <&i2s0_8ch_p0_0>;
++			};
++		};
++	};
++};
++
++&i2s0_8ch {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s0_lrck
++		     &i2s0_mclk
++		     &i2s0_sclk
++		     &i2s0_sdi0
++		     &i2s0_sdo0>;
++	status = "okay";
++
++	i2s0_8ch_p0: port {
++		i2s0_8ch_p0_0: endpoint {
++			dai-format = "i2s";
++			mclk-fs = <256>;
++			remote-endpoint = <&es8316_p0_0>;
++		};
++	};
++};
++
+ &pinctrl {
+ 	hym8563 {
+ 		hym8563_int: hym8563-int {
+ 			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
++
++	sound {
++		hp_detect: hp-detect {
++			rockchip,pins = <1 RK_PD5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
+ };
+ 
+ &pwm1 {
diff --git a/target/linux/rockchip/patches-6.1/158-arm64-dts-rockchip-use-just-port-in-panel-on-Pineboo.patch b/target/linux/rockchip/patches-6.1/158-arm64-dts-rockchip-use-just-port-in-panel-on-Pineboo.patch
new file mode 100644
index 00000000000..1ef416231d4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/158-arm64-dts-rockchip-use-just-port-in-panel-on-Pineboo.patch
@@ -0,0 +1,44 @@
+From 6c28de010652ee73b2480688d79e004127ec132b Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 26 Mar 2023 22:45:19 +0200
+Subject: [PATCH 158/383] arm64: dts: rockchip: use just "port" in panel on
+ Pinebook Pro
+
+The panel bindings expect to have only one port, thus they do not allow
+to use "ports" node:
+
+  rk3399-pinebook-pro.dtb: edp-panel: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+'
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230326204520.80859-2-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3399-pinebook-pro.dts    | 16 +++-------------
+ 1 file changed, 3 insertions(+), 13 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -50,19 +50,9 @@
+ 		pinctrl-0 = <&panel_en_pin>;
+ 		power-supply = <&vcc3v3_panel>;
+ 
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			port@0 {
+-				reg = <0>;
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				panel_in_edp: endpoint@0 {
+-					reg = <0>;
+-					remote-endpoint = <&edp_out_panel>;
+-				};
++		port {
++			panel_in_edp: endpoint {
++				remote-endpoint = <&edp_out_panel>;
+ 			};
+ 		};
+ 	};
diff --git a/target/linux/rockchip/patches-6.1/159-arm64-dts-rockchip-use-just-port-in-panel-on-RockPro.patch b/target/linux/rockchip/patches-6.1/159-arm64-dts-rockchip-use-just-port-in-panel-on-RockPro.patch
new file mode 100644
index 00000000000..184d72531a7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/159-arm64-dts-rockchip-use-just-port-in-panel-on-RockPro.patch
@@ -0,0 +1,43 @@
+From a1e2c3f0aa7a71028de4f8ddd858ee728b6f43c5 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 26 Mar 2023 22:45:20 +0200
+Subject: [PATCH 159/383] arm64: dts: rockchip: use just "port" in panel on
+ RockPro64
+
+The panel bindings expect to have only one port, thus they do not allow
+to use "ports" node:
+
+  rk3399-rockpro64.dtb: panel@0: 'ports' does not match any of the regexes: 'pinctrl-[0-9]+'
+
+There is only one endpoint, so use simpler form without "reg".
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230326204520.80859-3-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi | 12 +++---------
+ 1 file changed, 3 insertions(+), 9 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rockpro64.dtsi
+@@ -647,16 +647,10 @@
+ 		avdd-supply = <&avdd>;
+ 		backlight = <&backlight>;
+ 		dvdd-supply = <&vcc3v3_s0>;
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+ 
+-			port@0 {
+-				reg = <0>;
+-
+-				mipi_in_panel: endpoint {
+-					remote-endpoint = <&mipi_out_panel>;
+-				};
++		port {
++			mipi_in_panel: endpoint {
++				remote-endpoint = <&mipi_out_panel>;
+ 			};
+ 		};
+ 	};
diff --git a/target/linux/rockchip/patches-6.1/160-arm64-dts-rockchip-correct-panel-supplies-on-some-rk.patch b/target/linux/rockchip/patches-6.1/160-arm64-dts-rockchip-correct-panel-supplies-on-some-rk.patch
new file mode 100644
index 00000000000..5db24cc5d8f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/160-arm64-dts-rockchip-correct-panel-supplies-on-some-rk.patch
@@ -0,0 +1,70 @@
+From 8f658ba59ceb18deb3b544d3251fac6f3d7abb5b Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 26 Mar 2023 22:45:18 +0200
+Subject: [PATCH 160/383] arm64: dts: rockchip: correct panel supplies on some
+ rk3326 boards
+
+The Anbernic and Odroid Go have different panels and take differently
+named supplies, so move all the supplies to DTS defining actual panel to
+fix warnings like:
+
+  rk3326-odroid-go3.dtb: panel@0: 'IOVCC-supply' is a required property
+  rk3326-odroid-go3.dtb: panel@0: 'iovcc-supply', 'vdd-supply' do not match any of the regexes: 'pinctrl-[0-9]+'
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230326204520.80859-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts | 2 ++
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi      | 2 --
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts  | 2 ++
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts      | 2 ++
+ 4 files changed, 6 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-anbernic-rg351m.dts
+@@ -24,6 +24,8 @@
+ 
+ &internal_display {
+ 	compatible = "elida,kd35t133";
++	iovcc-supply = <&vcc_lcd>;
++	vdd-supply = <&vcc_lcd>;
+ };
+ 
+ &pwm0 {
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go.dtsi
+@@ -235,10 +235,8 @@
+ 	internal_display: panel@0 {
+ 		reg = <0>;
+ 		backlight = <&backlight>;
+-		iovcc-supply = <&vcc_lcd>;
+ 		reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ 		rotation = <270>;
+-		vdd-supply = <&vcc_lcd>;
+ 
+ 		port {
+ 			mipi_in_panel: endpoint {
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2-v11.dts
+@@ -83,6 +83,8 @@
+ 
+ &internal_display {
+ 	compatible = "elida,kd35t133";
++	iovcc-supply = <&vcc_lcd>;
++	vdd-supply = <&vcc_lcd>;
+ };
+ 
+ &rk817 {
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go2.dts
+@@ -59,6 +59,8 @@
+ 
+ &internal_display {
+ 	compatible = "elida,kd35t133";
++	iovcc-supply = <&vcc_lcd>;
++	vdd-supply = <&vcc_lcd>;
+ };
+ 
+ &rk817_charger {
diff --git a/target/linux/rockchip/patches-6.1/161-arm64-dts-rockchip-correct-panel-supplies-on-Odroid-.patch b/target/linux/rockchip/patches-6.1/161-arm64-dts-rockchip-correct-panel-supplies-on-Odroid-.patch
new file mode 100644
index 00000000000..4cfb8447dde
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/161-arm64-dts-rockchip-correct-panel-supplies-on-Odroid-.patch
@@ -0,0 +1,31 @@
+From 102925b3c60b45c0f32a6ebcde1b1d5d6ea4e19a Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sun, 26 Mar 2023 22:45:18 +0200
+Subject: [PATCH 161/383] arm64: dts: rockchip: correct panel supplies on
+ Odroid Go Super
+
+The Anbernic and Odroid Go have different panels and take differently
+named supplies, so move all the supplies to DTS defining actual panel to
+fix warnings like:
+
+  rk3326-odroid-go3.dtb: panel@0: 'IOVCC-supply' is a required property
+  rk3326-odroid-go3.dtb: panel@0: 'iovcc-supply', 'vdd-supply' do not match any of the regexes: 'pinctrl-[0-9]+'
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230326204520.80859-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3326-odroid-go3.dts
+@@ -144,6 +144,7 @@
+ &internal_display {
+ 	compatible = "elida,kd50t048a", "sitronix,st7701";
+ 	reset-gpios = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
++	IOVCC-supply = <&vcc_lcd>;
+ 	VCC-supply = <&vcc_lcd>;
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/162-arm64-dts-rockchip-Add-pinctrl-gpio-ranges-for-rk356.patch b/target/linux/rockchip/patches-6.1/162-arm64-dts-rockchip-Add-pinctrl-gpio-ranges-for-rk356.patch
new file mode 100644
index 00000000000..ea2f644c7f5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/162-arm64-dts-rockchip-Add-pinctrl-gpio-ranges-for-rk356.patch
@@ -0,0 +1,58 @@
+From d4a587e6ecc35c1d9786c2435d5378b3f43d9cf7 Mon Sep 17 00:00:00 2001
+From: John Clark <inindev@gmail.com>
+Date: Thu, 13 Apr 2023 13:03:37 -0400
+Subject: [PATCH 162/383] arm64: dts: rockchip: Add pinctrl gpio-ranges for
+ rk356x
+
+Add gpio-range properties to the pinctrl gpio nodes in rk356x.dtsi
+
+Signed-off-by: John Clark <inindev@gmail.com>
+Link: https://lore.kernel.org/r/20230413170337.6815-1-inindev@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -1809,6 +1809,7 @@
+ 			interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
+ 			gpio-controller;
++			gpio-ranges = <&pinctrl 0 0 32>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+@@ -1820,6 +1821,7 @@
+ 			interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
+ 			gpio-controller;
++			gpio-ranges = <&pinctrl 0 32 32>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+@@ -1831,6 +1833,7 @@
+ 			interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
+ 			gpio-controller;
++			gpio-ranges = <&pinctrl 0 64 32>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+@@ -1842,6 +1845,7 @@
+ 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
+ 			gpio-controller;
++			gpio-ranges = <&pinctrl 0 96 32>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
+@@ -1853,6 +1857,7 @@
+ 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+ 			clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
+ 			gpio-controller;
++			gpio-ranges = <&pinctrl 0 128 32>;
+ 			#gpio-cells = <2>;
+ 			interrupt-controller;
+ 			#interrupt-cells = <2>;
diff --git a/target/linux/rockchip/patches-6.1/163-arm64-dts-rockchip-Drop-RTC-clock-frequency-on-rk358.patch b/target/linux/rockchip/patches-6.1/163-arm64-dts-rockchip-Drop-RTC-clock-frequency-on-rk358.patch
new file mode 100644
index 00000000000..97bfadda63e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/163-arm64-dts-rockchip-Drop-RTC-clock-frequency-on-rk358.patch
@@ -0,0 +1,33 @@
+From c329fa6c1f185b79d732ebe3c0b74b7fa6654caf Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 14 Apr 2023 15:54:23 +0300
+Subject: [PATCH 163/383] arm64: dts: rockchip: Drop RTC clock-frequency on
+ rk3588-rock-5b
+
+The hym8563 RTC driver doesn't handle the 'clock-frequency' property,
+which is also indicated by the following dtbs_check warning:
+
+  rk3588-rock-5b.dtb: rtc@51: Unevaluated properties are not allowed ('clock-frequency' was unexpected)
+  From schema: Documentation/devicetree/bindings/rtc/haoyu,hym8563.yaml
+
+Drop the unsupported property.
+
+Fixes: 1e9c2404d887 ("arm64: dts: rockchip: Enable RTC support for Rock 5B")
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230414125425.124994-2-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -60,7 +60,6 @@
+ 		compatible = "haoyu,hym8563";
+ 		reg = <0x51>;
+ 		#clock-cells = <0>;
+-		clock-frequency = <32768>;
+ 		clock-output-names = "hym8563";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&hym8563_int>;
diff --git a/target/linux/rockchip/patches-6.1/164-arm64-dts-rockchip-Use-generic-name-for-es8316-on-Pi.patch b/target/linux/rockchip/patches-6.1/164-arm64-dts-rockchip-Use-generic-name-for-es8316-on-Pi.patch
new file mode 100644
index 00000000000..2bce66c5335
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/164-arm64-dts-rockchip-Use-generic-name-for-es8316-on-Pi.patch
@@ -0,0 +1,40 @@
+From b6ac28925881e504ef86de592b8895123cd40884 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 14 Apr 2023 15:54:24 +0300
+Subject: [PATCH 164/383] arm64: dts: rockchip: Use generic name for es8316 on
+ Pinebook Pro and Rock 5B
+
+Use generic 'audio-codec' name for es8316 node on Pinebook Pro and Rock
+5B boards.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230414125425.124994-3-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts      | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinebook-pro.dts
+@@ -665,7 +665,7 @@
+ 	i2c-scl-rising-time-ns = <168>;
+ 	status = "okay";
+ 
+-	es8316: es8316@11 {
++	es8316: audio-codec@11 {
+ 		compatible = "everest,es8316";
+ 		reg = <0x11>;
+ 		clocks = <&cru SCLK_I2S_8CH_OUT>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -72,7 +72,7 @@
+ &i2c7 {
+ 	status = "okay";
+ 
+-	es8316: es8316@11 {
++	es8316: audio-codec@11 {
+ 		compatible = "everest,es8316";
+ 		reg = <0x11>;
+ 		clocks = <&cru I2S0_8CH_MCLKOUT>;
diff --git a/target/linux/rockchip/patches-6.1/165-arm64-dts-rockchip-Add-vdd_cpu_big-regulators-to-rk3.patch b/target/linux/rockchip/patches-6.1/165-arm64-dts-rockchip-Add-vdd_cpu_big-regulators-to-rk3.patch
new file mode 100644
index 00000000000..b98bbe647a4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/165-arm64-dts-rockchip-Add-vdd_cpu_big-regulators-to-rk3.patch
@@ -0,0 +1,85 @@
+From 1208018acd7fe0bdfec13c3f1608d87aa3ab2fc3 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Fri, 14 Apr 2023 15:54:25 +0300
+Subject: [PATCH 165/383] arm64: dts: rockchip: Add vdd_cpu_big regulators to
+ rk3588-rock-5b
+
+The RK8602 and RK8603 voltage regulators on the Rock 5B board provide
+the power lines vdd_cpu_big0 and vdd_cpu_big1, respectively.
+
+Add the necessary device tree nodes and bind them to the corresponding
+CPU big core nodes.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230414125425.124994-4-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 56 +++++++++++++++++++
+ 1 file changed, 56 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -53,6 +53,62 @@
+ 	};
+ };
+ 
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++	cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++	cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0m2_xfer>;
++	status = "okay";
++
++	vdd_cpu_big0_s0: regulator@42 {
++		compatible = "rockchip,rk8602";
++		reg = <0x42>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_big0_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <1050000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_cpu_big1_s0: regulator@43 {
++		compatible = "rockchip,rk8603", "rockchip,rk8602";
++		reg = <0x43>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_big1_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <1050000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
+ &i2c6 {
+ 	status = "okay";
+ 
diff --git a/target/linux/rockchip/patches-6.1/166-arm64-dts-rockchip-Add-support-for-volume-keys-to-rk.patch b/target/linux/rockchip/patches-6.1/166-arm64-dts-rockchip-Add-support-for-volume-keys-to-rk.patch
new file mode 100644
index 00000000000..26af75a0d65
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/166-arm64-dts-rockchip-Add-support-for-volume-keys-to-rk.patch
@@ -0,0 +1,76 @@
+From adad13f8ccd4ab71e027a0ebcea88ecaa003df9b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Wed, 5 Apr 2023 13:38:13 +0100
+Subject: [PATCH 166/383] arm64: dts: rockchip: Add support for volume keys to
+ rk3399-pinephone-pro
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+These are implemented via regular ADC, so regular polling is needed,
+for these keys to work.
+
+Co-developed-by: Martijn Braam <martijn@brixit.nl>
+Signed-off-by: Martijn Braam <martijn@brixit.nl>
+Co-developed-by: Kamil Trzciński <ayufan@ayufan.eu>
+Signed-off-by: Kamil Trzciński <ayufan@ayufan.eu>
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
+Tested-by: Ondrej Jirman <megi@xff.cz>
+Link: https://lore.kernel.org/r/20230405123813.2272919-1-pbrobinson@gmail.com
+[increased Volume-Down voltage to 600mV as suggested by Ondrej]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3399-pinephone-pro.dts     | 26 +++++++++++++++++++
+ 1 file changed, 26 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-pinephone-pro.dts
+@@ -10,6 +10,7 @@
+  */
+ 
+ /dts-v1/;
++#include <dt-bindings/input/gpio-keys.h>
+ #include <dt-bindings/input/linux-event-codes.h>
+ #include "rk3399.dtsi"
+ #include "rk3399-opp.dtsi"
+@@ -29,6 +30,26 @@
+ 		stdout-path = "serial2:115200n8";
+ 	};
+ 
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 1>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1600000>;
++		poll-interval = <100>;
++
++		button-up {
++			label = "Volume Up";
++			linux,code = <KEY_VOLUMEUP>;
++			press-threshold-microvolt = <100000>;
++		};
++
++		button-down {
++			label = "Volume Down";
++			linux,code = <KEY_VOLUMEDOWN>;
++			press-threshold-microvolt = <600000>;
++		};
++	};
++
+ 	backlight: backlight {
+ 		compatible = "pwm-backlight";
+ 		pwms = <&pwm0 0 50000 0>;
+@@ -519,6 +540,11 @@
+ 	status = "okay";
+ };
+ 
++&saradc {
++	vref-supply = <&vcca1v8_s3>;
++	status = "okay";
++};
++
+ &sdmmc {
+ 	bus-width = <4>;
+ 	cap-sd-highspeed;
diff --git a/target/linux/rockchip/patches-6.1/167-arm64-dts-rockchip-Update-compatible-for-bluetooth.patch b/target/linux/rockchip/patches-6.1/167-arm64-dts-rockchip-Update-compatible-for-bluetooth.patch
new file mode 100644
index 00000000000..17d61168f91
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/167-arm64-dts-rockchip-Update-compatible-for-bluetooth.patch
@@ -0,0 +1,25 @@
+From be401be5ce967e8530ba3b78aa5383497389cacd Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Tue, 28 Feb 2023 09:22:05 -0600
+Subject: [PATCH 167/383] arm64: dts: rockchip: Update compatible for bluetooth
+
+Update the compatible for the Realtek RTL8821CS bluetooth node.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Signed-off-by: Luiz Augusto von Dentz <luiz.von.dentz@intel.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
+@@ -716,7 +716,7 @@
+ 	status = "okay";
+ 
+ 	bluetooth {
+-		compatible = "realtek,rtl8821cs-bt";
++		compatible = "realtek,rtl8821cs-bt", "realtek,rtl8822cs-bt";
+ 		device-wake-gpios = <&gpio4 4 GPIO_ACTIVE_HIGH>;
+ 		enable-gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>;
+ 		host-wake-gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>;
diff --git a/target/linux/rockchip/patches-6.1/168-arm64-dts-rockchip-add-panel-to-Anbernic-RG353-serie.patch b/target/linux/rockchip/patches-6.1/168-arm64-dts-rockchip-add-panel-to-Anbernic-RG353-serie.patch
new file mode 100644
index 00000000000..74f292de290
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/168-arm64-dts-rockchip-add-panel-to-Anbernic-RG353-serie.patch
@@ -0,0 +1,91 @@
+From 50974c17b775bec188ac036c4dc9adb7e99f8fe4 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 25 Nov 2022 19:14:32 -0600
+Subject: [PATCH 168/383] arm64: dts: rockchip: add panel to Anbernic RG353
+ series
+
+Add support for the newly mainlined panel to the RG353 series of
+devices.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20221126011432.22891-2-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3566-anbernic-rg353x.dtsi  | 58 +++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353x.dtsi
+@@ -22,6 +22,48 @@
+ 			       <200000000>, <241500000>;
+ };
+ 
++&dsi_dphy0 {
++	status = "okay";
++};
++
++&dsi0 {
++	status = "okay";
++	#address-cells = <1>;
++	#size-cells = <0>;
++
++	ports {
++		dsi0_in: port@0 {
++			reg = <0>;
++			dsi0_in_vp1: endpoint {
++				remote-endpoint = <&vp1_out_dsi0>;
++			};
++		};
++
++		dsi0_out: port@1 {
++			reg = <1>;
++			mipi_out_panel: endpoint {
++				remote-endpoint = <&mipi_in_panel>;
++			};
++		};
++	};
++
++	panel: panel@0 {
++		compatible = "anbernic,rg353p-panel", "newvision,nv3051d";
++		reg = <0>;
++		backlight = <&backlight>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&lcd_rst>;
++		reset-gpios = <&gpio4 RK_PA0 GPIO_ACTIVE_LOW>;
++		vdd-supply = <&vcc3v3_lcd0_n>;
++
++		port {
++			mipi_in_panel: endpoint {
++				remote-endpoint = <&mipi_out_panel>;
++			};
++		};
++	};
++};
++
+ &gpio_keys_control {
+ 	button-a {
+ 		gpios = <&gpio3 RK_PC2 GPIO_ACTIVE_LOW>;
+@@ -57,6 +99,22 @@
+ 	};
+ };
+ 
++&pinctrl {
++	gpio-lcd {
++		lcd_rst: lcd-rst {
++			rockchip,pins =
++				<4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
+ &pwm4 {
+ 	status = "okay";
+ };
++
++&vp1 {
++	vp1_out_dsi0: endpoint@ROCKCHIP_VOP2_EP_MIPI0 {
++		reg = <ROCKCHIP_VOP2_EP_MIPI0>;
++		remote-endpoint = <&dsi0_in_vp1>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/169-arm64-dts-rockchip-fix-USB-regulator-on-ROCK64.patch b/target/linux/rockchip/patches-6.1/169-arm64-dts-rockchip-fix-USB-regulator-on-ROCK64.patch
new file mode 100644
index 00000000000..b0851a0d1d7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/169-arm64-dts-rockchip-fix-USB-regulator-on-ROCK64.patch
@@ -0,0 +1,62 @@
+From 5658597f406cb3075561b187bc413a9547b1fe4b Mon Sep 17 00:00:00 2001
+From: Lorenz Brun <lorenz@brun.one>
+Date: Fri, 21 Apr 2023 23:38:41 +0200
+Subject: [PATCH 169/383] arm64: dts: rockchip: fix USB regulator on ROCK64
+
+Currently the ROCK64 device tree specifies two regulators, vcc_host_5v
+and vcc_host1_5v for USB VBUS on the device. Both of those are however
+specified with RK_PA2 as the GPIO enabling them, causing the following
+error when booting:
+
+  rockchip-pinctrl pinctrl: pin gpio0-2 already requested by vcc-host-5v-regulator; cannot claim for vcc-host1-5v-regulator
+  rockchip-pinctrl pinctrl: pin-2 (vcc-host1-5v-regulator) status -22
+  rockchip-pinctrl pinctrl: could not request pin 2 (gpio0-2) from group usb20-host-drv  on device rockchip-pinctrl
+  reg-fixed-voltage vcc-host1-5v-regulator: Error applying setting, reverse things back
+
+Looking at the schematic, there are in fact three USB regulators,
+vcc_host_5v, vcc_host1_5v and vcc_otg_v5. But the enable signal for all
+three is driven by Q2604 which is in turn driven by GPIO_A2/PA2.
+
+Since these three regulators are not controllable separately, I removed
+the second one which was causing the error and added labels for all
+rails to the single regulator.
+
+Signed-off-by: Lorenz Brun <lorenz@brun.one>
+Tested-by: Diederik de Haas <didi.debian@cknow.org>
+Link: https://lore.kernel.org/r/20230421213841.3079632-1-lorenz@brun.one
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-rock64.dts | 14 ++------------
+ 1 file changed, 2 insertions(+), 12 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-rock64.dts
+@@ -37,7 +37,8 @@
+ 		vin-supply = <&vcc_io>;
+ 	};
+ 
+-	vcc_host_5v: vcc-host-5v-regulator {
++	/* Common enable line for all of the rails mentioned in the labels */
++	vcc_host_5v: vcc_host1_5v: vcc_otg_5v: vcc-host-5v-regulator {
+ 		compatible = "regulator-fixed";
+ 		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+ 		pinctrl-names = "default";
+@@ -46,17 +47,6 @@
+ 		regulator-always-on;
+ 		regulator-boot-on;
+ 		vin-supply = <&vcc_sys>;
+-	};
+-
+-	vcc_host1_5v: vcc_otg_5v: vcc-host1-5v-regulator {
+-		compatible = "regulator-fixed";
+-		gpio = <&gpio0 RK_PA2 GPIO_ACTIVE_LOW>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&usb20_host_drv>;
+-		regulator-name = "vcc_host1_5v";
+-		regulator-always-on;
+-		regulator-boot-on;
+-		vin-supply = <&vcc_sys>;
+ 	};
+ 
+ 	vcc_sys: vcc-sys {
diff --git a/target/linux/rockchip/patches-6.1/170-arm64-dts-rockchip-add-missing-cache-properties.patch b/target/linux/rockchip/patches-6.1/170-arm64-dts-rockchip-add-missing-cache-properties.patch
new file mode 100644
index 00000000000..7d65c2c5f95
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/170-arm64-dts-rockchip-add-missing-cache-properties.patch
@@ -0,0 +1,114 @@
+From 16037c793235f5043c1b04076a057cc7729080d8 Mon Sep 17 00:00:00 2001
+From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Date: Sat, 22 Apr 2023 00:31:48 +0200
+Subject: [PATCH 170/383] arm64: dts: rockchip: add missing cache properties
+
+As all level 2 and level 3 caches are unified, add required
+cache-unified properties to fix warnings like:
+
+  rk3588s-khadas-edge2.dtb: l3-cache: 'cache-unified' is a dependency of 'cache-size'
+
+Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230421223149.115185-1-krzysztof.kozlowski@linaro.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3308.dtsi  | 1 +
+ arch/arm64/boot/dts/rockchip/rk3328.dtsi  | 1 +
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 9 +++++++++
+ 3 files changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3308.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3308.dtsi
+@@ -97,6 +97,7 @@
+ 		l2: l2-cache {
+ 			compatible = "cache";
+ 			cache-level = <2>;
++			cache-unified;
+ 		};
+ 	};
+ 
+--- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
+@@ -103,6 +103,7 @@
+ 		l2: l2-cache0 {
+ 			compatible = "cache";
+ 			cache-level = <2>;
++			cache-unified;
+ 		};
+ 	};
+ 
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -229,6 +229,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -238,6 +239,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -247,6 +249,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -256,6 +259,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <512>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -265,6 +269,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -274,6 +279,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -283,6 +289,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -292,6 +299,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <1024>;
+ 			cache-level = <2>;
++			cache-unified;
+ 			next-level-cache = <&l3_cache>;
+ 		};
+ 
+@@ -301,6 +309,7 @@
+ 			cache-line-size = <64>;
+ 			cache-sets = <4096>;
+ 			cache-level = <3>;
++			cache-unified;
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/172-arm64-dts-rockchip-add-GIC-ITS-support-to-rk3588.patch b/target/linux/rockchip/patches-6.1/172-arm64-dts-rockchip-add-GIC-ITS-support-to-rk3588.patch
new file mode 100644
index 00000000000..6f166bb2866
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/172-arm64-dts-rockchip-add-GIC-ITS-support-to-rk3588.patch
@@ -0,0 +1,46 @@
+From 90d5c1eb04ccff2a14be69d8ff30737b5aafebab Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 18 Apr 2023 16:21:09 +0200
+Subject: [PATCH 172/383] arm64: dts: rockchip: add GIC ITS support to rk3588
+
+Add the two Interrupt Translation Service (ITS) IPs that are part of the
+GIC-600. They are mainly required for PCIe Message Signalled Interrupts
+(MSI).
+
+Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230418142109.49762-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 17 +++++++++++++++++
+ 1 file changed, 17 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1309,7 +1309,24 @@
+ 		mbi-alias = <0x0 0xfe610000>;
+ 		mbi-ranges = <424 56>;
+ 		msi-controller;
++		ranges;
++		#address-cells = <2>;
+ 		#interrupt-cells = <4>;
++		#size-cells = <2>;
++
++		its0: msi-controller@fe640000 {
++			compatible = "arm,gic-v3-its";
++			reg = <0x0 0xfe640000 0x0 0x20000>;
++			msi-controller;
++			#msi-cells = <1>;
++		};
++
++		its1: msi-controller@fe660000 {
++			compatible = "arm,gic-v3-its";
++			reg = <0x0 0xfe660000 0x0 0x20000>;
++			msi-controller;
++			#msi-cells = <1>;
++		};
+ 
+ 		ppi-partitions {
+ 			ppi_partition0: interrupt-partition-0 {
diff --git a/target/linux/rockchip/patches-6.1/173-arm64-dts-rockchip-Add-rk3588-timer.patch b/target/linux/rockchip/patches-6.1/173-arm64-dts-rockchip-Add-rk3588-timer.patch
new file mode 100644
index 00000000000..e6a1fd2365c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/173-arm64-dts-rockchip-Add-rk3588-timer.patch
@@ -0,0 +1,32 @@
+From d6b9406805470684aab0b7ce852d3403193c2ef0 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 19 Apr 2023 21:13:09 +0300
+Subject: [PATCH 173/383] arm64: dts: rockchip: Add rk3588 timer
+
+Add DT node for Rockchip RK3588/RK3588S SoC timer.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230419181309.338354-4-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1426,6 +1426,14 @@
+ 		status = "disabled";
+ 	};
+ 
++	timer0: timer@feae0000 {
++		compatible = "rockchip,rk3588-timer", "rockchip,rk3288-timer";
++		reg = <0x0 0xfeae0000 0x0 0x20>;
++		interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru PCLK_BUSTIMER0>, <&cru CLK_BUSTIMER0>;
++		clock-names = "pclk", "timer";
++	};
++
+ 	wdt: watchdog@feaf0000 {
+ 		compatible = "rockchip,rk3588-wdt", "snps,dw-wdt";
+ 		reg = <0x0 0xfeaf0000 0x0 0x100>;
diff --git a/target/linux/rockchip/patches-6.1/174-arm64-dts-rockchip-Add-Lunzn-Fastrhino-R66S.patch b/target/linux/rockchip/patches-6.1/174-arm64-dts-rockchip-Add-Lunzn-Fastrhino-R66S.patch
new file mode 100644
index 00000000000..582d3f621d9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/174-arm64-dts-rockchip-Add-Lunzn-Fastrhino-R66S.patch
@@ -0,0 +1,554 @@
+From a4be8686beaa7102a97574e215d63c7ea7d2c5ec Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 6 May 2023 14:11:07 +0800
+Subject: [PATCH 174/383] arm64: dts: rockchip: Add Lunzn Fastrhino R66S
+
+Lunzn Fastrhino R66S is a high-performance mini router.
+
+Specification:
+- Rockchip RK3568
+- 1/2GB LPDDR4 RAM
+- SD card slot
+- 2x USB 3.0 Port
+- 2x 2500 Base-T (PCIe, r8125b)
+- 12v DC Jack
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230506061108.17658-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3568-fastrhino-r66s.dts    |  27 +
+ .../dts/rockchip/rk3568-fastrhino-r66s.dtsi   | 484 ++++++++++++++++++
+ 3 files changed, 512 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -85,6 +85,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-bo
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dts
+@@ -0,0 +1,27 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include "rk3568-fastrhino-r66s.dtsi"
++
++/ {
++	model = "Lunzn FastRhino R66S";
++	compatible = "lunzn,fastrhino-r66s", "rockchip,rk3568";
++
++	aliases {
++		mmc0 = &sdmmc0;
++	};
++};
++
++&sdmmc0 {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	max-frequency = <150000000>;
++	no-sdio;
++	no-mmc;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
++	vmmc-supply = <&vcc3v3_sd>;
++	vqmmc-supply = <&vccio_sd>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r66s.dtsi
+@@ -0,0 +1,484 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++/dts-v1/;
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/soc/rockchip,vop2.h>
++#include "rk3568.dtsi"
++
++/ {
++	chosen: chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&reset_button_pin>;
++
++		button-reset {
++			debounce-interval = <50>;
++			gpios = <&gpio0 RK_PB6 GPIO_ACTIVE_LOW>;
++			label = "reset";
++			linux,code = <KEY_RESTART>;
++		};
++	};
++
++	gpio-leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 = <&status_led_pin>;
++
++		status_led: led-status {
++			color = <LED_COLOR_ID_BLUE>;
++			function = LED_FUNCTION_STATUS;
++			gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_HIGH>;
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	dc_12v: dc-12v-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "dc_12v";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc3v3_pcie: vcc3v3-pcie-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc3v3_sys: vcc3v3-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&dc_12v>;
++	};
++
++	vcc5v0_usb_host: vcc5v0-usb-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb_host";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_usb_otg_en>;
++		regulator-name = "vcc5v0_usb_otg";
++		regulator-always-on;
++		regulator-boot-on;
++	};
++};
++
++&combphy0 {
++	status = "okay";
++};
++
++&combphy1 {
++	status = "okay";
++};
++
++&cpu0 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu1 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu2 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&cpu3 {
++	cpu-supply = <&vdd_cpu>;
++};
++
++&gpu {
++	mali-supply = <&vdd_gpu>;
++	status = "okay";
++};
++
++&i2c0 {
++	status = "okay";
++
++	vdd_cpu: regulator@1c {
++		compatible = "tcs,tcs4525";
++		reg = <0x1c>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <800000>;
++		regulator-max-microvolt = <1150000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	rk809: pmic@20 {
++		compatible = "rockchip,rk809";
++		reg = <0x20>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
++		#clock-cells = <1>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_int>;
++		rockchip,system-power-controller;
++		vcc1-supply = <&vcc3v3_sys>;
++		vcc2-supply = <&vcc3v3_sys>;
++		vcc3-supply = <&vcc3v3_sys>;
++		vcc4-supply = <&vcc3v3_sys>;
++		vcc5-supply = <&vcc3v3_sys>;
++		vcc6-supply = <&vcc3v3_sys>;
++		vcc7-supply = <&vcc3v3_sys>;
++		vcc8-supply = <&vcc3v3_sys>;
++		vcc9-supply = <&vcc3v3_sys>;
++		wakeup-source;
++
++		regulators {
++			vdd_logic: DCDC_REG1 {
++				regulator-name = "vdd_logic";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_gpu: DCDC_REG2 {
++				regulator-name = "vdd_gpu";
++				regulator-always-on;
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_ddr: DCDC_REG3 {
++				regulator-name = "vcc_ddr";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-initial-mode = <0x2>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vdd_npu: DCDC_REG4 {
++				regulator-name = "vdd_npu";
++				regulator-init-microvolt = <900000>;
++				regulator-initial-mode = <0x2>;
++				regulator-min-microvolt = <500000>;
++				regulator-max-microvolt = <1350000>;
++				regulator-ramp-delay = <6001>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8: DCDC_REG5 {
++				regulator-name = "vcc_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_image: LDO_REG1 {
++				regulator-name = "vdda0v9_image";
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <950000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v9: LDO_REG2 {
++				regulator-name = "vdda_0v9";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda0v9_pmu: LDO_REG3 {
++				regulator-name = "vdda0v9_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vccio_acodec: LDO_REG4 {
++				regulator-name = "vccio_acodec";
++				regulator-always-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd: LDO_REG5 {
++				regulator-name = "vccio_sd";
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_pmu: LDO_REG6 {
++				regulator-name = "vcc3v3_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcca_1v8: LDO_REG7 {
++				regulator-name = "vcca_1v8";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca1v8_pmu: LDO_REG8 {
++				regulator-name = "vcca1v8_pmu";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcca1v8_image: LDO_REG9 {
++				regulator-name = "vcca1v8_image";
++				regulator-init-microvolt = <950000>;
++				regulator-min-microvolt = <950000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <950000>;
++				};
++			};
++
++			vcc_3v3: SWITCH_REG1 {
++				regulator-name = "vcc_3v3";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc3v3_sd: SWITCH_REG2 {
++				regulator-name = "vcc3v3_sd";
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&pcie30phy {
++	data-lanes = <1 2>;
++	status = "okay";
++};
++
++&pcie3x1 {
++	num-lanes = <1>;
++	reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pcie3x2 {
++	num-lanes = <1>;
++	reset-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie>;
++	status = "okay";
++};
++
++&pinctrl {
++	gpio-leds {
++		status_led_pin: status-led-pin {
++			rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	pmic {
++		pmic_int: pmic-int {
++			rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	rockchip-key {
++		reset_button_pin: reset-button-pin {
++			rockchip,pins = <0 RK_PB6 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb {
++		vcc5v0_usb_otg_en: vcc5v0-usb-otg-en {
++			rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&pmu_io_domains {
++	pmuio1-supply = <&vcc3v3_pmu>;
++	pmuio2-supply = <&vcc3v3_pmu>;
++	vccio1-supply = <&vccio_acodec>;
++	vccio3-supply = <&vccio_sd>;
++	vccio4-supply = <&vcc_1v8>;
++	vccio5-supply = <&vcc_3v3>;
++	vccio6-supply = <&vcc_1v8>;
++	vccio7-supply = <&vcc_3v3>;
++	status = "okay";
++};
++
++&saradc {
++	vref-supply = <&vcca_1v8>;
++	status = "okay";
++};
++
++&tsadc {
++	rockchip,hw-tshut-mode = <1>;
++	rockchip,hw-tshut-polarity = <0>;
++	status = "okay";
++};
++
++&uart2 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host0_xhci {
++	dr_mode = "host";
++	extcon = <&usb2phy0>;
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&usb_host1_xhci {
++	status = "okay";
++};
++
++&usb2phy0 {
++	status = "okay";
++};
++
++&usb2phy0_host {
++	phy-supply = <&vcc5v0_usb_host>;
++	status = "okay";
++};
++
++&usb2phy0_otg {
++	phy-supply = <&vcc5v0_usb_otg>;
++	status = "okay";
++};
++
++&vop {
++	assigned-clocks = <&cru DCLK_VOP0>, <&cru DCLK_VOP1>;
++	assigned-clock-parents = <&pmucru PLL_HPLL>, <&cru PLL_VPLL>;
++	status = "okay";
++};
++
++&vop_mmu {
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/175-arm64-dts-rockchip-Add-Lunzn-Fastrhino-R68S.patch b/target/linux/rockchip/patches-6.1/175-arm64-dts-rockchip-Add-Lunzn-Fastrhino-R68S.patch
new file mode 100644
index 00000000000..eb73eb8ac7f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/175-arm64-dts-rockchip-Add-Lunzn-Fastrhino-R68S.patch
@@ -0,0 +1,147 @@
+From 950da0bca31a30ea6a772c55ae3a063796861442 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 6 May 2023 14:11:08 +0800
+Subject: [PATCH 175/383] arm64: dts: rockchip: Add Lunzn Fastrhino R68S
+
+It's similar to Fastrhino R66S with the following changes:
++ 2/4GB LPDDR4 RAM
++ 2x 1000 Base-T (native, RTL8211f)
++ ADC button
++ 16GB eMMC on-board
+- No SD card slot
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230506061108.17658-3-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3568-fastrhino-r68s.dts    | 112 ++++++++++++++++++
+ 2 files changed, 113 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -86,6 +86,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lu
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3568-fastrhino-r68s.dts
+@@ -0,0 +1,112 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++
++#include "rk3568-fastrhino-r66s.dtsi"
++
++/ {
++	model = "Lunzn FastRhino R68S";
++	compatible = "lunzn,fastrhino-r68s", "rockchip,rk3568";
++
++	aliases {
++		ethernet0 = &gmac0;
++		ethernet1 = &gmac1;
++		mmc0 = &sdhci;
++	};
++
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 0>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1800000>;
++
++		button-recovery {
++			label = "Recovery";
++			linux,code = <KEY_VENDOR>;
++			press-threshold-microvolt = <1750>;
++		};
++	};
++};
++
++&gmac0 {
++	assigned-clocks = <&cru SCLK_GMAC0_RX_TX>, <&cru SCLK_GMAC0>;
++	assigned-clock-parents = <&cru SCLK_GMAC0_RGMII_SPEED>;
++	assigned-clock-rates = <0>, <125000000>;
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy0>;
++	phy-mode = "rgmii-id";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac0_miim
++		     &gmac0_tx_bus2
++		     &gmac0_rx_bus2
++		     &gmac0_rgmii_clk
++		     &gmac0_rgmii_bus>;
++	snps,reset-gpio = <&gpio0 RK_PB0 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 15ms, 50ms for rtl8211f */
++	snps,reset-delays-us = <0 15000 50000>;
++	tx_delay = <0x3c>;
++	rx_delay = <0x2f>;
++	status = "okay";
++};
++
++&gmac1 {
++	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>;
++	assigned-clock-rates = <0>, <125000000>;
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy1>;
++	phy-mode = "rgmii-id";
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1m1_miim
++		     &gmac1m1_tx_bus2
++		     &gmac1m1_rx_bus2
++		     &gmac1m1_rgmii_clk
++		     &gmac1m1_rgmii_bus>;
++	snps,reset-gpio = <&gpio0 RK_PB1 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 15ms, 50ms for rtl8211f */
++	snps,reset-delays-us = <0 15000 50000>;
++	tx_delay = <0x4f>;
++	rx_delay = <0x26>;
++	status = "okay";
++};
++
++&mdio0 {
++	rgmii_phy0: ethernet-phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0>;
++		pinctrl-0 = <&eth_phy0_reset_pin>;
++		pinctrl-names = "default";
++	};
++};
++
++&mdio1 {
++	rgmii_phy1: ethernet-phy@0 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0>;
++		pinctrl-0 = <&eth_phy1_reset_pin>;
++		pinctrl-names = "default";
++	};
++};
++
++&pinctrl {
++	gmac0 {
++		eth_phy0_reset_pin: eth-phy0-reset-pin {
++			rockchip,pins = <1 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	gmac1 {
++		eth_phy1_reset_pin: eth-phy1-reset-pin {
++			rockchip,pins = <1 RK_PB1 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&sdhci {
++	bus-width = <8>;
++	max-frequency = <200000000>;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_bus8 &emmc_clk &emmc_cmd &emmc_datastrobe>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/176-arm64-dts-rockchip-add-Anbernic-RG353PS.patch b/target/linux/rockchip/patches-6.1/176-arm64-dts-rockchip-add-Anbernic-RG353PS.patch
new file mode 100644
index 00000000000..1435b9e9d56
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/176-arm64-dts-rockchip-add-Anbernic-RG353PS.patch
@@ -0,0 +1,154 @@
+From c16b4db57554778ae3e8283b5720864a325921f7 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 12 May 2023 11:20:39 -0500
+Subject: [PATCH 176/383] arm64: dts: rockchip: add Anbernic RG353PS
+
+Add support for the Anbernic RG353PS. This device is identical in form
+factor to the RG353P and has the following hardware differences:
+ - No touchscreen is present on i2c2 (or at all).
+ - Only contains 1GB of RAM.
+ - Has no eMMC.
+ - Only appears to ship with the 2nd revision of the display panel.
+
+Note that the display panel has been added to the st7703 panel driver
+in a separate commit series.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20230512162039.31132-3-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3566-anbernic-rg353ps.dts  | 116 ++++++++++++++++++
+ 2 files changed, 117 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sa
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-sapphire-excavator.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353p.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353ps.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353v.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg353vs.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-anbernic-rg503.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rg353ps.dts
+@@ -0,0 +1,116 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/linux-event-codes.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3566-anbernic-rg353x.dtsi"
++
++/ {
++	model = "RG353PS";
++	compatible = "anbernic,rg353ps", "rockchip,rk3566";
++
++	aliases {
++		mmc0 = &sdmmc0;
++		mmc1 = &sdmmc1;
++		mmc2 = &sdmmc2;
++	};
++
++	battery: battery {
++		compatible = "simple-battery";
++		charge-full-design-microamp-hours = <3472000>;
++		charge-term-current-microamp = <300000>;
++		constant-charge-current-max-microamp = <2000000>;
++		constant-charge-voltage-max-microvolt = <4200000>;
++		factory-internal-resistance-micro-ohms = <117000>;
++		voltage-max-design-microvolt = <4172000>;
++		voltage-min-design-microvolt = <3400000>;
++
++		ocv-capacity-celsius = <20>;
++		ocv-capacity-table-0 =  <4172000 100>, <4054000 95>, <3984000 90>, <3926000 85>,
++					<3874000 80>, <3826000 75>, <3783000 70>, <3746000 65>,
++					<3714000 60>, <3683000 55>, <3650000 50>, <3628000 45>,
++					<3612000 40>, <3600000 35>, <3587000 30>, <3571000 25>,
++					<3552000 20>, <3525000 15>, <3492000 10>, <3446000 5>,
++					<3400000 0>;
++	};
++
++	/* Channels reversed for both headphones and speakers. */
++	sound {
++		compatible = "simple-audio-card";
++		simple-audio-card,name = "rk817_ext";
++		simple-audio-card,aux-devs = <&spk_amp>;
++		simple-audio-card,format = "i2s";
++		simple-audio-card,hp-det-gpio = <&gpio4 RK_PC6 GPIO_ACTIVE_HIGH>;
++		simple-audio-card,mclk-fs = <256>;
++		simple-audio-card,widgets =
++			"Microphone", "Mic Jack",
++			"Headphone", "Headphones",
++			"Speaker", "Internal Speakers";
++		simple-audio-card,routing =
++			"MICL", "Mic Jack",
++			"Headphones", "HPOL",
++			"Headphones", "HPOR",
++			"Internal Speakers", "Speaker Amp OUTL",
++			"Internal Speakers", "Speaker Amp OUTR",
++			"Speaker Amp INL", "HPOL",
++			"Speaker Amp INR", "HPOR";
++		simple-audio-card,pin-switches = "Internal Speakers";
++
++		simple-audio-card,codec {
++			sound-dai = <&rk817>;
++		};
++
++		simple-audio-card,cpu {
++			sound-dai = <&i2s1_8ch>;
++		};
++	};
++
++	spk_amp: audio-amplifier {
++		compatible = "simple-audio-amplifier";
++		enable-gpios = <&gpio4 RK_PC2 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&spk_amp_enable_h>;
++		pinctrl-names = "default";
++		sound-name-prefix = "Speaker Amp";
++	};
++};
++
++&gpio_keys_control {
++	button-r1 {
++		gpios = <&gpio3 RK_PB4 GPIO_ACTIVE_LOW>;
++		label = "TR";
++		linux,code = <BTN_TR>;
++	};
++
++	button-r2 {
++		gpios = <&gpio3 RK_PB3 GPIO_ACTIVE_LOW>;
++		label = "TR2";
++		linux,code = <BTN_TR2>;
++	};
++};
++
++&panel {
++	compatible = "anbernic,rg353v-panel-v2";
++	iovcc-supply = <&vcc3v3_lcd0_n>;
++	vcc-supply = <&vcc3v3_lcd0_n>;
++	/delete-property/ vdd-supply;
++};
++
++&pinctrl {
++	audio-amplifier {
++		spk_amp_enable_h: spk-amp-enable-h {
++			rockchip,pins =
++				<4 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&rk817 {
++	rk817_charger: charger {
++		monitored-battery = <&battery>;
++		rockchip,resistor-sense-micro-ohms = <10000>;
++		rockchip,sleep-enter-current-microamp = <300000>;
++		rockchip,sleep-filter-current-microamp = <100000>;
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/177-arm64-dts-rockchip-Update-leds-for-Anbernic-RGxx3-Se.patch b/target/linux/rockchip/patches-6.1/177-arm64-dts-rockchip-Update-leds-for-Anbernic-RGxx3-Se.patch
new file mode 100644
index 00000000000..67524e28938
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/177-arm64-dts-rockchip-Update-leds-for-Anbernic-RGxx3-Se.patch
@@ -0,0 +1,101 @@
+From 300e77f77e1e73b1e2bb47b931bf5e593a434a4e Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Fri, 12 May 2023 14:16:33 -0500
+Subject: [PATCH 177/383] arm64: dts: rockchip: Update leds for Anbernic RGxx3
+ Series
+
+Each of the LEDs on the RGxx3 which is currently controlled via GPIO
+can also be controlled via a PWM. Change each of the LEDs to PWM so
+that users have the ability to adjust the brightness of the LEDs
+according to their preference.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Link: https://lore.kernel.org/r/20230512191633.33416-1-macroalpha82@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3566-anbernic-rgxx3.dtsi   | 39 +++++++++++--------
+ 1 file changed, 22 insertions(+), 17 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3566-anbernic-rgxx3.dtsi
+@@ -191,30 +191,30 @@
+ 		};
+ 	};
+ 
+-	leds: gpio-leds {
+-		compatible = "gpio-leds";
+-		pinctrl-0 = <&led_pins>;
+-		pinctrl-names = "default";
++	leds: pwm-leds {
++		compatible = "pwm-leds";
+ 
+ 		green_led: led-0 {
+ 			color = <LED_COLOR_ID_GREEN>;
+ 			default-state = "on";
+ 			function = LED_FUNCTION_POWER;
+-			gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++			max-brightness = <255>;
++			pwms = <&pwm6 0 25000 0>;
+ 		};
+ 
+ 		amber_led: led-1 {
+ 			color = <LED_COLOR_ID_AMBER>;
+ 			function = LED_FUNCTION_CHARGING;
+-			gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+-			retain-state-suspended;
++			max-brightness = <255>;
++			pwms = <&pwm7 0 25000 0>;
+ 		};
+ 
+ 		red_led: led-2 {
+ 			color = <LED_COLOR_ID_RED>;
+ 			default-state = "off";
+ 			function = LED_FUNCTION_STATUS;
+-			gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_HIGH>;
++			max-brightness = <255>;
++			pwms = <&pwm0 0 25000 0>;
+ 		};
+ 	};
+ 
+@@ -597,15 +597,6 @@
+ 		};
+ 	};
+ 
+-	gpio-led {
+-		led_pins: led-pins {
+-			rockchip,pins =
+-				<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>,
+-				<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-	};
+-
+ 	joy-mux {
+ 		joy_mux_en: joy-mux-en {
+ 			rockchip,pins =
+@@ -654,10 +645,24 @@
+ 	vccio7-supply = <&vcc_3v3>;
+ };
+ 
++&pwm0 {
++	pinctrl-0 = <&pwm0m1_pins>;
++	pinctrl-names = "default";
++	status = "okay";
++};
++
+ &pwm5 {
+ 	status = "okay";
+ };
+ 
++&pwm6 {
++	status = "okay";
++};
++
++&pwm7 {
++	status = "okay";
++};
++
+ &saradc {
+ 	vref-supply = <&vcc_1v8>;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/178-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch b/target/linux/rockchip/patches-6.1/178-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch
new file mode 100644
index 00000000000..73121dc1223
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/178-arm64-dts-rockchip-Add-FriendlyARM-NanoPi-R2C-Plus.patch
@@ -0,0 +1,64 @@
+From 45902bac55d540baee5489f8caba2a733503a0ff Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Sat, 13 May 2023 21:53:07 +0800
+Subject: [PATCH 178/383] arm64: dts: rockchip: Add FriendlyARM NanoPi R2C Plus
+
+The NanoPi R2C Plus is a small variant of NanoPi R2C with a on-board
+eMMC flash (8G) included.
+
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230513135307.26554-2-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../dts/rockchip/rk3328-nanopi-r2c-plus.dts   | 33 +++++++++++++++++++
+ 2 files changed, 34 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -15,6 +15,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c-plus.dts
+@@ -0,0 +1,33 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyarm.com)
++ *
++ * Copyright (c) 2023 Tianling Shen <cnsztl@gmail.com>
++ */
++
++/dts-v1/;
++#include "rk3328-nanopi-r2c.dts"
++
++/ {
++	model = "FriendlyElec NanoPi R2C Plus";
++	compatible = "friendlyarm,nanopi-r2c-plus", "rockchip,rk3328";
++
++	aliases {
++		mmc1 = &emmc;
++	};
++};
++
++&emmc {
++	bus-width = <8>;
++	cap-mmc-highspeed;
++	max-frequency = <150000000>;
++	mmc-ddr-1_8v;
++	mmc-hs200-1_8v;
++	non-removable;
++	pinctrl-names = "default";
++	pinctrl-0 = <&emmc_clk &emmc_cmd &emmc_bus8>;
++	vmmc-supply = <&vcc_io_33>;
++	vqmmc-supply = <&vcc18_emmc>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/179-arm64-dts-rockchip-Add-rk3588-OTP-node.patch b/target/linux/rockchip/patches-6.1/179-arm64-dts-rockchip-Add-rk3588-OTP-node.patch
new file mode 100644
index 00000000000..266cafb6fa2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/179-arm64-dts-rockchip-Add-rk3588-OTP-node.patch
@@ -0,0 +1,82 @@
+From 454d8712e9dbc16c0bff1333745959bbe3e5fb28 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 4 May 2023 23:06:48 +0300
+Subject: [PATCH 179/383] arm64: dts: rockchip: Add rk3588 OTP node
+
+Add DT node for Rockchip RK3588/RK3588S OTP memory.
+
+Co-developed-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
+[moved cpu-version subnode down, to be sorted by address]
+Link: https://lore.kernel.org/r/20230504200648.1119866-9-cristian.ciocaltea@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 54 +++++++++++++++++++++++
+ 1 file changed, 54 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1848,6 +1848,60 @@
+ 		status = "disabled";
+ 	};
+ 
++	otp: efuse@fecc0000 {
++		compatible = "rockchip,rk3588-otp";
++		reg = <0x0 0xfecc0000 0x0 0x400>;
++		clocks = <&cru CLK_OTPC_NS>, <&cru PCLK_OTPC_NS>,
++			 <&cru CLK_OTP_PHY_G>, <&cru CLK_OTPC_ARB>;
++		clock-names = "otp", "apb_pclk", "phy", "arb";
++		resets = <&cru SRST_OTPC_NS>, <&cru SRST_P_OTPC_NS>,
++			 <&cru SRST_OTPC_ARB>;
++		reset-names = "otp", "apb", "arb";
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		cpu_code: cpu-code@2 {
++			reg = <0x02 0x2>;
++		};
++
++		otp_id: id@7 {
++			reg = <0x07 0x10>;
++		};
++
++		cpub0_leakage: cpu-leakage@17 {
++			reg = <0x17 0x1>;
++		};
++
++		cpub1_leakage: cpu-leakage@18 {
++			reg = <0x18 0x1>;
++		};
++
++		cpul_leakage: cpu-leakage@19 {
++			reg = <0x19 0x1>;
++		};
++
++		log_leakage: log-leakage@1a {
++			reg = <0x1a 0x1>;
++		};
++
++		gpu_leakage: gpu-leakage@1b {
++			reg = <0x1b 0x1>;
++		};
++
++		otp_cpu_version: cpu-version@1c {
++			reg = <0x1c 0x1>;
++			bits = <3 3>;
++		};
++
++		npu_leakage: npu-leakage@28 {
++			reg = <0x28 0x1>;
++		};
++
++		codec_leakage: codec-leakage@29 {
++			reg = <0x29 0x1>;
++		};
++	};
++
+ 	dmac2: dma-controller@fed10000 {
+ 		compatible = "arm,pl330", "arm,primecell";
+ 		reg = <0x0 0xfed10000 0x0 0x4000>;
diff --git a/target/linux/rockchip/patches-6.1/180-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r.patch b/target/linux/rockchip/patches-6.1/180-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r.patch
new file mode 100644
index 00000000000..d4bde5bfb83
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/180-arm64-dts-rockchip-fix-button-reset-pin-for-nanopi-r.patch
@@ -0,0 +1,39 @@
+From 14646477019b635150b5f4c9ee5ee45f287498a1 Mon Sep 17 00:00:00 2001
+From: Tianling Shen <cnsztl@gmail.com>
+Date: Thu, 11 May 2023 00:18:50 +0800
+Subject: [PATCH 180/383] arm64: dts: rockchip: fix button reset pin for nanopi
+ r5c
+
+The reset pin was wrongly assigned due to a copy/paste error,
+fix it to match actual gpio pin.
+
+While at it, remove a blank line from nanopi r5s dts.
+
+Fixes: 05620031408a ("arm64: dts: rockchip: Add FriendlyARM NanoPi R5C")
+Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Link: https://lore.kernel.org/r/20230510161850.4866-1-cnsztl@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts | 2 +-
+ arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts | 1 -
+ 2 files changed, 1 insertion(+), 2 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+@@ -106,7 +106,7 @@
+ 
+ 	rockchip-key {
+ 		reset_button_pin: reset-button-pin {
+-			rockchip,pins = <4 RK_PA0 RK_FUNC_GPIO &pcfg_pull_up>;
++			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -134,4 +134,3 @@
+ 		};
+ 	};
+ };
+-
diff --git a/target/linux/rockchip/patches-6.1/181-soc-rockchip-dtpm-use-C99-array-init-syntax.patch b/target/linux/rockchip/patches-6.1/181-soc-rockchip-dtpm-use-C99-array-init-syntax.patch
new file mode 100644
index 00000000000..55b5f9504fb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/181-soc-rockchip-dtpm-use-C99-array-init-syntax.patch
@@ -0,0 +1,94 @@
+From 6481be2f2c900518340458510c3411075823d5f9 Mon Sep 17 00:00:00 2001
+From: Randy Dunlap <rdunlap@infradead.org>
+Date: Sun, 30 Apr 2023 19:49:50 -0700
+Subject: [PATCH 181/383] soc: rockchip: dtpm: use C99 array init syntax
+
+Eliminate sparse warnings in soc/rockchip/dtpm.c:
+
+drivers/soc/rockchip/dtpm.c:15:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:17:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:20:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:23:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:26:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:29:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:32:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:35:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:38:12: sparse: warning: obsolete array initializer, use C99 syntax
+drivers/soc/rockchip/dtpm.c:41:12: sparse: warning: obsolete array initializer, use C99 syntax
+
+Fixes: b9d6c47a2be8 ("rockchip/soc/drivers: Add DTPM description for rk3399")
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Cc: Heiko Stuebner <heiko@sntech.de>
+Cc: linux-rockchip@lists.infradead.org
+Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230501024950.31518-1-rdunlap@infradead.org
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/soc/rockchip/dtpm.c | 54 ++++++++++++++++++-------------------
+ 1 file changed, 27 insertions(+), 27 deletions(-)
+
+--- a/drivers/soc/rockchip/dtpm.c
++++ b/drivers/soc/rockchip/dtpm.c
+@@ -12,33 +12,33 @@
+ #include <linux/platform_device.h>
+ 
+ static struct dtpm_node __initdata rk3399_hierarchy[] = {
+-	[0]{ .name = "rk3399",
+-	     .type = DTPM_NODE_VIRTUAL },
+-	[1]{ .name = "package",
+-	     .type = DTPM_NODE_VIRTUAL,
+-	     .parent = &rk3399_hierarchy[0] },
+-	[2]{ .name = "/cpus/cpu@0",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[3]{ .name = "/cpus/cpu@1",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[4]{ .name = "/cpus/cpu@2",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[5]{ .name = "/cpus/cpu@3",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[6]{ .name = "/cpus/cpu@100",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[7]{ .name = "/cpus/cpu@101",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[8]{ .name = "/gpu@ff9a0000",
+-	     .type = DTPM_NODE_DT,
+-	     .parent = &rk3399_hierarchy[1] },
+-	[9]{ /* sentinel */ }
++	[0] = { .name = "rk3399",
++		.type = DTPM_NODE_VIRTUAL },
++	[1] = { .name = "package",
++		.type = DTPM_NODE_VIRTUAL,
++		.parent = &rk3399_hierarchy[0] },
++	[2] = { .name = "/cpus/cpu@0",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[3] = { .name = "/cpus/cpu@1",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[4] = { .name = "/cpus/cpu@2",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[5] = { .name = "/cpus/cpu@3",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[6] = { .name = "/cpus/cpu@100",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[7] = { .name = "/cpus/cpu@101",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[8] = { .name = "/gpu@ff9a0000",
++		.type = DTPM_NODE_DT,
++		.parent = &rk3399_hierarchy[1] },
++	[9] = { /* sentinel */ }
+ };
+ 
+ static struct of_device_id __initdata rockchip_dtpm_match_table[] = {
diff --git a/target/linux/rockchip/patches-6.1/182-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch b/target/linux/rockchip/patches-6.1/182-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch
new file mode 100644
index 00000000000..1c81b72efe5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/182-soc-rockchip-power-domain-add-rk3588-mem-module-supp.patch
@@ -0,0 +1,264 @@
+From 016f7ae354e6ea8952cf1c042ef91ec8c989a2a3 Mon Sep 17 00:00:00 2001
+From: Boris Brezillon <boris.brezillon@collabora.com>
+Date: Mon, 3 Apr 2023 21:32:50 +0200
+Subject: [PATCH 182/383] soc: rockchip: power-domain: add rk3588 mem module
+ support
+
+On RK3588 it's also possible to power down the memory used by the
+particular power domains via PMU_MEM_PWR_GATE_SFTCON. This adds
+support for this feature.
+
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
+Co-Developed-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230403193250.108693-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/soc/rockchip/pm_domains.c | 160 +++++++++++++++++++++++-------
+ 1 file changed, 125 insertions(+), 35 deletions(-)
+
+--- a/drivers/soc/rockchip/pm_domains.c
++++ b/drivers/soc/rockchip/pm_domains.c
+@@ -43,8 +43,10 @@ struct rockchip_domain_info {
+ 	bool active_wakeup;
+ 	int pwr_w_mask;
+ 	int req_w_mask;
++	int mem_status_mask;
+ 	int repair_status_mask;
+ 	u32 pwr_offset;
++	u32 mem_offset;
+ 	u32 req_offset;
+ };
+ 
+@@ -54,6 +56,9 @@ struct rockchip_pmu_info {
+ 	u32 req_offset;
+ 	u32 idle_offset;
+ 	u32 ack_offset;
++	u32 mem_pwr_offset;
++	u32 chain_status_offset;
++	u32 mem_status_offset;
+ 	u32 repair_status_offset;
+ 
+ 	u32 core_pwrcnt_offset;
+@@ -119,13 +124,15 @@ struct rockchip_pmu {
+ 	.active_wakeup = wakeup,			\
+ }
+ 
+-#define DOMAIN_M_O_R(_name, p_offset, pwr, status, r_status, r_offset, req, idle, ack, wakeup)	\
++#define DOMAIN_M_O_R(_name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, ack, wakeup)	\
+ {							\
+ 	.name = _name,					\
+ 	.pwr_offset = p_offset,				\
+ 	.pwr_w_mask = (pwr) << 16,			\
+ 	.pwr_mask = (pwr),				\
+ 	.status_mask = (status),			\
++	.mem_offset = m_offset,				\
++	.mem_status_mask = (m_status),			\
+ 	.repair_status_mask = (r_status),		\
+ 	.req_offset = r_offset,				\
+ 	.req_w_mask = (req) << 16,			\
+@@ -269,8 +276,8 @@ void rockchip_pmu_unblock(void)
+ }
+ EXPORT_SYMBOL_GPL(rockchip_pmu_unblock);
+ 
+-#define DOMAIN_RK3588(name, p_offset, pwr, status, r_status, r_offset, req, idle, wakeup)	\
+-	DOMAIN_M_O_R(name, p_offset, pwr, status, r_status, r_offset, req, idle, idle, wakeup)
++#define DOMAIN_RK3588(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, wakeup)	\
++	DOMAIN_M_O_R(name, p_offset, pwr, status, m_offset, m_status, r_status, r_offset, req, idle, idle, wakeup)
+ 
+ static bool rockchip_pmu_domain_is_idle(struct rockchip_pm_domain *pd)
+ {
+@@ -408,17 +415,92 @@ static bool rockchip_pmu_domain_is_on(st
+ 	return !(val & pd->info->status_mask);
+ }
+ 
++static bool rockchip_pmu_domain_is_mem_on(struct rockchip_pm_domain *pd)
++{
++	struct rockchip_pmu *pmu = pd->pmu;
++	unsigned int val;
++
++	regmap_read(pmu->regmap,
++		    pmu->info->mem_status_offset + pd->info->mem_offset, &val);
++
++	/* 1'b0: power on, 1'b1: power off */
++	return !(val & pd->info->mem_status_mask);
++}
++
++static bool rockchip_pmu_domain_is_chain_on(struct rockchip_pm_domain *pd)
++{
++	struct rockchip_pmu *pmu = pd->pmu;
++	unsigned int val;
++
++	regmap_read(pmu->regmap,
++		    pmu->info->chain_status_offset + pd->info->mem_offset, &val);
++
++	/* 1'b1: power on, 1'b0: power off */
++	return val & pd->info->mem_status_mask;
++}
++
++static int rockchip_pmu_domain_mem_reset(struct rockchip_pm_domain *pd)
++{
++	struct rockchip_pmu *pmu = pd->pmu;
++	struct generic_pm_domain *genpd = &pd->genpd;
++	bool is_on;
++	int ret = 0;
++
++	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_chain_on, pd, is_on,
++					is_on == true, 0, 10000);
++	if (ret) {
++		dev_err(pmu->dev,
++			"failed to get chain status '%s', target_on=1, val=%d\n",
++			genpd->name, is_on);
++		goto error;
++	}
++
++	udelay(20);
++
++	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
++		     (pd->info->pwr_mask | pd->info->pwr_w_mask));
++	wmb();
++
++	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
++					is_on == false, 0, 10000);
++	if (ret) {
++		dev_err(pmu->dev,
++			"failed to get mem status '%s', target_on=0, val=%d\n",
++			genpd->name, is_on);
++		goto error;
++	}
++
++	regmap_write(pmu->regmap, pmu->info->mem_pwr_offset + pd->info->pwr_offset,
++		     pd->info->pwr_w_mask);
++	wmb();
++
++	ret = readx_poll_timeout_atomic(rockchip_pmu_domain_is_mem_on, pd, is_on,
++					is_on == true, 0, 10000);
++	if (ret) {
++		dev_err(pmu->dev,
++			"failed to get mem status '%s', target_on=1, val=%d\n",
++			genpd->name, is_on);
++	}
++
++error:
++	return ret;
++}
++
+ static void rockchip_do_pmu_set_power_domain(struct rockchip_pm_domain *pd,
+ 					     bool on)
+ {
+ 	struct rockchip_pmu *pmu = pd->pmu;
+ 	struct generic_pm_domain *genpd = &pd->genpd;
+ 	u32 pd_pwr_offset = pd->info->pwr_offset;
+-	bool is_on;
++	bool is_on, is_mem_on = false;
+ 
+ 	if (pd->info->pwr_mask == 0)
+ 		return;
+-	else if (pd->info->pwr_w_mask)
++
++	if (on && pd->info->mem_status_mask)
++		is_mem_on = rockchip_pmu_domain_is_mem_on(pd);
++
++	if (pd->info->pwr_w_mask)
+ 		regmap_write(pmu->regmap, pmu->info->pwr_offset + pd_pwr_offset,
+ 			     on ? pd->info->pwr_w_mask :
+ 			     (pd->info->pwr_mask | pd->info->pwr_w_mask));
+@@ -428,6 +510,9 @@ static void rockchip_do_pmu_set_power_do
+ 
+ 	wmb();
+ 
++	if (is_mem_on && rockchip_pmu_domain_mem_reset(pd))
++		return;
++
+ 	if (readx_poll_timeout_atomic(rockchip_pmu_domain_is_on, pd, is_on,
+ 				      is_on == on, 0, 10000)) {
+ 		dev_err(pmu->dev,
+@@ -645,7 +730,9 @@ static int rockchip_pm_add_one_domain(st
+ 	pd->genpd.flags = GENPD_FLAG_PM_CLK;
+ 	if (pd_info->active_wakeup)
+ 		pd->genpd.flags |= GENPD_FLAG_ACTIVE_WAKEUP;
+-	pm_genpd_init(&pd->genpd, NULL, !rockchip_pmu_domain_is_on(pd));
++	pm_genpd_init(&pd->genpd, NULL,
++		      !rockchip_pmu_domain_is_on(pd) ||
++		      (pd->info->mem_status_mask && !rockchip_pmu_domain_is_mem_on(pd)));
+ 
+ 	pmu->genpd_data.domains[id] = &pd->genpd;
+ 	return 0;
+@@ -1024,35 +1111,35 @@ static const struct rockchip_domain_info
+ };
+ 
+ static const struct rockchip_domain_info rk3588_pm_domains[] = {
+-	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),
+-	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0,       0x0, 0,       0,       false),
+-	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0,       0x0, 0,       0,       false),
+-	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       BIT(2),  0x0, BIT(1),  BIT(1),  false),
+-	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       BIT(3),  0x0, BIT(2),  BIT(2),  false),
+-	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       BIT(4),  0x0, BIT(3),  BIT(3),  false),
+-	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       BIT(5),  0x0, BIT(4),  BIT(4),  false),
+-	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       BIT(6),  0x0, BIT(5),  BIT(5),  false),
+-	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       BIT(7),  0x0, BIT(6),  BIT(6),  false),
+-	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       BIT(8),  0x0, BIT(7),  BIT(7),  false),
+-	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       BIT(9),  0x0, BIT(8),  BIT(8),  false),
+-	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       BIT(10), 0x0, 0,       0,       false),
+-	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       BIT(11), 0x0, BIT(9),  BIT(9),  false),
+-	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       BIT(12), 0x0, BIT(10), BIT(10), false),
+-	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       BIT(13), 0x0, 0,       0,       false),
+-	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       BIT(14), 0x0, BIT(11), BIT(11), false),
+-	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       BIT(15), 0x0, BIT(12), BIT(12), false),
+-	[RK3588_PD_VOP]		= DOMAIN_RK3588("vop",     0x4, BIT(1),  0,       BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
+-	[RK3588_PD_VO0]		= DOMAIN_RK3588("vo0",     0x4, BIT(2),  0,       BIT(17), 0x0, BIT(15), BIT(15), false),
+-	[RK3588_PD_VO1]		= DOMAIN_RK3588("vo1",     0x4, BIT(3),  0,       BIT(18), 0x4, BIT(0),  BIT(16), false),
+-	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       BIT(19), 0x4, BIT(1),  BIT(17), false),
+-	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       BIT(20), 0x4, BIT(5),  BIT(21), false),
+-	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       BIT(21), 0x0, 0,       0,       false),
+-	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       BIT(22), 0x0, 0,       0,       true),
+-	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0,       0x4, BIT(2),  BIT(18), false),
+-	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       BIT(23), 0x0, 0,       0,       false),
+-	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       BIT(24), 0x4, BIT(3),  BIT(19), false),
+-	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       BIT(25), 0x4, BIT(4),  BIT(20), true),
+-	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       BIT(26), 0x0, 0,       0,       false),
++	[RK3588_PD_GPU]		= DOMAIN_RK3588("gpu",     0x0, BIT(0),  0,       0x0, 0,       BIT(1),  0x0, BIT(0),  BIT(0),  false),
++	[RK3588_PD_NPU]		= DOMAIN_RK3588("npu",     0x0, BIT(1),  BIT(1),  0x0, 0,       0,       0x0, 0,       0,       false),
++	[RK3588_PD_VCODEC]	= DOMAIN_RK3588("vcodec",  0x0, BIT(2),  BIT(2),  0x0, 0,       0,       0x0, 0,       0,       false),
++	[RK3588_PD_NPUTOP]	= DOMAIN_RK3588("nputop",  0x0, BIT(3),  0,       0x0, BIT(11), BIT(2),  0x0, BIT(1),  BIT(1),  false),
++	[RK3588_PD_NPU1]	= DOMAIN_RK3588("npu1",    0x0, BIT(4),  0,       0x0, BIT(12), BIT(3),  0x0, BIT(2),  BIT(2),  false),
++	[RK3588_PD_NPU2]	= DOMAIN_RK3588("npu2",    0x0, BIT(5),  0,       0x0, BIT(13), BIT(4),  0x0, BIT(3),  BIT(3),  false),
++	[RK3588_PD_VENC0]	= DOMAIN_RK3588("venc0",   0x0, BIT(6),  0,       0x0, BIT(14), BIT(5),  0x0, BIT(4),  BIT(4),  false),
++	[RK3588_PD_VENC1]	= DOMAIN_RK3588("venc1",   0x0, BIT(7),  0,       0x0, BIT(15), BIT(6),  0x0, BIT(5),  BIT(5),  false),
++	[RK3588_PD_RKVDEC0]	= DOMAIN_RK3588("rkvdec0", 0x0, BIT(8),  0,       0x0, BIT(16), BIT(7),  0x0, BIT(6),  BIT(6),  false),
++	[RK3588_PD_RKVDEC1]	= DOMAIN_RK3588("rkvdec1", 0x0, BIT(9),  0,       0x0, BIT(17), BIT(8),  0x0, BIT(7),  BIT(7),  false),
++	[RK3588_PD_VDPU]	= DOMAIN_RK3588("vdpu",    0x0, BIT(10), 0,       0x0, BIT(18), BIT(9),  0x0, BIT(8),  BIT(8),  false),
++	[RK3588_PD_RGA30]	= DOMAIN_RK3588("rga30",   0x0, BIT(11), 0,       0x0, BIT(19), BIT(10), 0x0, 0,       0,       false),
++	[RK3588_PD_AV1]		= DOMAIN_RK3588("av1",     0x0, BIT(12), 0,       0x0, BIT(20), BIT(11), 0x0, BIT(9),  BIT(9),  false),
++	[RK3588_PD_VI]		= DOMAIN_RK3588("vi",      0x0, BIT(13), 0,       0x0, BIT(21), BIT(12), 0x0, BIT(10), BIT(10), false),
++	[RK3588_PD_FEC]		= DOMAIN_RK3588("fec",     0x0, BIT(14), 0,       0x0, BIT(22), BIT(13), 0x0, 0,       0,       false),
++	[RK3588_PD_ISP1]	= DOMAIN_RK3588("isp1",    0x0, BIT(15), 0,       0x0, BIT(23), BIT(14), 0x0, BIT(11), BIT(11), false),
++	[RK3588_PD_RGA31]	= DOMAIN_RK3588("rga31",   0x4, BIT(0),  0,       0x0, BIT(24), BIT(15), 0x0, BIT(12), BIT(12), false),
++	[RK3588_PD_VOP]		= DOMAIN_RK3588("vop",     0x4, BIT(1),  0,       0x0, BIT(25), BIT(16), 0x0, BIT(13) | BIT(14), BIT(13) | BIT(14), false),
++	[RK3588_PD_VO0]		= DOMAIN_RK3588("vo0",     0x4, BIT(2),  0,       0x0, BIT(26), BIT(17), 0x0, BIT(15), BIT(15), false),
++	[RK3588_PD_VO1]		= DOMAIN_RK3588("vo1",     0x4, BIT(3),  0,       0x0, BIT(27), BIT(18), 0x4, BIT(0),  BIT(16), false),
++	[RK3588_PD_AUDIO]	= DOMAIN_RK3588("audio",   0x4, BIT(4),  0,       0x0, BIT(28), BIT(19), 0x4, BIT(1),  BIT(17), false),
++	[RK3588_PD_PHP]		= DOMAIN_RK3588("php",     0x4, BIT(5),  0,       0x0, BIT(29), BIT(20), 0x4, BIT(5),  BIT(21), false),
++	[RK3588_PD_GMAC]	= DOMAIN_RK3588("gmac",    0x4, BIT(6),  0,       0x0, BIT(30), BIT(21), 0x0, 0,       0,       false),
++	[RK3588_PD_PCIE]	= DOMAIN_RK3588("pcie",    0x4, BIT(7),  0,       0x0, BIT(31), BIT(22), 0x0, 0,       0,       true),
++	[RK3588_PD_NVM]		= DOMAIN_RK3588("nvm",     0x4, BIT(8),  BIT(24), 0x4, 0,       0,       0x4, BIT(2),  BIT(18), false),
++	[RK3588_PD_NVM0]	= DOMAIN_RK3588("nvm0",    0x4, BIT(9),  0,       0x4, BIT(1),  BIT(23), 0x0, 0,       0,       false),
++	[RK3588_PD_SDIO]	= DOMAIN_RK3588("sdio",    0x4, BIT(10), 0,       0x4, BIT(2),  BIT(24), 0x4, BIT(3),  BIT(19), false),
++	[RK3588_PD_USB]		= DOMAIN_RK3588("usb",     0x4, BIT(11), 0,       0x4, BIT(3),  BIT(25), 0x4, BIT(4),  BIT(20), true),
++	[RK3588_PD_SDMMC]	= DOMAIN_RK3588("sdmmc",   0x4, BIT(13), 0,       0x4, BIT(5),  BIT(26), 0x0, 0,       0,       false),
+ };
+ 
+ static const struct rockchip_pmu_info px30_pmu = {
+@@ -1207,6 +1294,9 @@ static const struct rockchip_pmu_info rk
+ 	.req_offset = 0x10c,
+ 	.idle_offset = 0x120,
+ 	.ack_offset = 0x118,
++	.mem_pwr_offset = 0x1a0,
++	.chain_status_offset = 0x1f0,
++	.mem_status_offset = 0x1f8,
+ 	.repair_status_offset = 0x290,
+ 
+ 	.num_domains = ARRAY_SIZE(rk3588_pm_domains),
diff --git a/target/linux/rockchip/patches-6.1/183-irqchip-gic-v3-Add-Rockchip-3588001-erratum-workarou.patch b/target/linux/rockchip/patches-6.1/183-irqchip-gic-v3-Add-Rockchip-3588001-erratum-workarou.patch
new file mode 100644
index 00000000000..1f08d96acfd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/183-irqchip-gic-v3-Add-Rockchip-3588001-erratum-workarou.patch
@@ -0,0 +1,154 @@
+From ec84008b72b43ad8ed6b1208d98bf22d945fcc27 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 18 Apr 2023 16:21:08 +0200
+Subject: [PATCH 183/383] irqchip/gic-v3: Add Rockchip 3588001 erratum
+ workaround
+
+Rockchip RK3588/RK3588s GIC600 integration does not support the
+sharability feature. Rockchip assigned Erratum ID #3588001 for this
+issue.
+
+Note, that the 0x0201743b ID is not Rockchip specific and thus
+there is an extra of_machine_is_compatible() check.
+
+The flags are named FORCE_NON_SHAREABLE to be vendor agnostic,
+since apparently similar integration design errors exist in other
+platforms and they can reuse the same flag.
+
+Co-developed-by: XiaoDong Huang <derrick.huang@rock-chips.com>
+Signed-off-by: XiaoDong Huang <derrick.huang@rock-chips.com>
+Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Co-developed-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marc Zyngier <maz@kernel.org>
+Link: https://lore.kernel.org/r/20230418142109.49762-2-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/arm64/silicon-errata.rst |  3 +++
+ arch/arm64/Kconfig                     | 10 ++++++++
+ drivers/irqchip/irq-gic-v3-its.c       | 35 ++++++++++++++++++++++++++
+ 3 files changed, 48 insertions(+)
+
+--- a/Documentation/arm64/silicon-errata.rst
++++ b/Documentation/arm64/silicon-errata.rst
+@@ -217,6 +217,9 @@ stable kernels.
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Qualcomm Tech. | Kryo4xx Gold    | N/A             | ARM64_ERRATUM_1286807       |
+ +----------------+-----------------+-----------------+-----------------------------+
+++----------------+-----------------+-----------------+-----------------------------+
++| Rockchip       | RK3588          | #3588001        | ROCKCHIP_ERRATUM_3588001    |
+++----------------+-----------------+-----------------+-----------------------------+
+ 
+ +----------------+-----------------+-----------------+-----------------------------+
+ | Fujitsu        | A64FX           | E#010001        | FUJITSU_ERRATUM_010001      |
+--- a/arch/arm64/Kconfig
++++ b/arch/arm64/Kconfig
+@@ -1160,6 +1160,16 @@ config NVIDIA_CARMEL_CNP_ERRATUM
+ 
+ 	  If unsure, say Y.
+ 
++config ROCKCHIP_ERRATUM_3588001
++	bool "Rockchip 3588001: GIC600 can not support shareability attributes"
++	default y
++	help
++	  The Rockchip RK3588 GIC600 SoC integration does not support ACE/ACE-lite.
++	  This means, that its sharability feature may not be used, even though it
++	  is supported by the IP itself.
++
++	  If unsure, say Y.
++
+ config SOCIONEXT_SYNQUACER_PREITS
+ 	bool "Socionext Synquacer: Workaround for GICv3 pre-ITS"
+ 	default y
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -42,9 +42,11 @@
+ #define ITS_FLAGS_CMDQ_NEEDS_FLUSHING		(1ULL << 0)
+ #define ITS_FLAGS_WORKAROUND_CAVIUM_22375	(1ULL << 1)
+ #define ITS_FLAGS_WORKAROUND_CAVIUM_23144	(1ULL << 2)
++#define ITS_FLAGS_FORCE_NON_SHAREABLE		(1ULL << 3)
+ 
+ #define RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING	(1 << 0)
+ #define RDIST_FLAGS_RD_TABLES_PREALLOCATED	(1 << 1)
++#define RDIST_FLAGS_FORCE_NON_SHAREABLE		(1 << 2)
+ 
+ #define RD_LOCAL_LPI_ENABLED                    BIT(0)
+ #define RD_LOCAL_PENDTABLE_PREALLOCATED         BIT(1)
+@@ -2384,6 +2386,9 @@ retry_baser:
+ 	its_write_baser(its, baser, val);
+ 	tmp = baser->val;
+ 
++	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
++		tmp &= ~GITS_BASER_SHAREABILITY_MASK;
++
+ 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
+ 		/*
+ 		 * Shareability didn't stick. Just use
+@@ -3121,6 +3126,9 @@ static void its_cpu_init_lpis(void)
+ 	gicr_write_propbaser(val, rbase + GICR_PROPBASER);
+ 	tmp = gicr_read_propbaser(rbase + GICR_PROPBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
++		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+ 			/*
+@@ -3145,6 +3153,9 @@ static void its_cpu_init_lpis(void)
+ 	gicr_write_pendbaser(val, rbase + GICR_PENDBASER);
+ 	tmp = gicr_read_pendbaser(rbase + GICR_PENDBASER);
+ 
++	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
++		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
++
+ 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 		/*
+ 		 * The HW reports non-shareable, we must remove the
+@@ -4727,6 +4738,19 @@ static bool __maybe_unused its_enable_qu
+ 	return true;
+ }
+ 
++static bool __maybe_unused its_enable_rk3588001(void *data)
++{
++	struct its_node *its = data;
++
++	if (!of_machine_is_compatible("rockchip,rk3588"))
++		return false;
++
++	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
++	gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE;
++
++	return true;
++}
++
+ static const struct gic_quirk its_quirks[] = {
+ #ifdef CONFIG_CAVIUM_ERRATUM_22375
+ 	{
+@@ -4773,6 +4797,14 @@ static const struct gic_quirk its_quirks
+ 		.init	= its_enable_quirk_hip07_161600802,
+ 	},
+ #endif
++#ifdef CONFIG_ROCKCHIP_ERRATUM_3588001
++	{
++		.desc   = "ITS: Rockchip erratum RK3588001",
++		.iidr   = 0x0201743b,
++		.mask   = 0xffffffff,
++		.init   = its_enable_rk3588001,
++	},
++#endif
+ 	{
+ 	}
+ };
+@@ -5112,6 +5144,9 @@ static int __init its_probe_one(struct r
+ 	gits_write_cbaser(baser, its->base + GITS_CBASER);
+ 	tmp = gits_read_cbaser(its->base + GITS_CBASER);
+ 
++	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
++		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+ 			/*
diff --git a/target/linux/rockchip/patches-6.1/184-dt-bindings-arm-rockchip-Add-pmu-compatible-for-rv11.patch b/target/linux/rockchip/patches-6.1/184-dt-bindings-arm-rockchip-Add-pmu-compatible-for-rv11.patch
new file mode 100644
index 00000000000..eaa023c332e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/184-dt-bindings-arm-rockchip-Add-pmu-compatible-for-rv11.patch
@@ -0,0 +1,35 @@
+From 4cbcb4ea61bc30275a4cf2154feaccf2d695f1e0 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 29 Nov 2022 13:24:17 +0530
+Subject: [PATCH 184/383] dt-bindings: arm: rockchip: Add pmu compatible for
+ rv1126
+
+Add PMU compatible string for rockchip rv1126.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20221129075424.189655-2-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip/pmu.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip/pmu.yaml
+@@ -27,6 +27,7 @@ select:
+           - rockchip,rk3399-pmu
+           - rockchip,rk3568-pmu
+           - rockchip,rk3588-pmu
++          - rockchip,rv1126-pmu
+ 
+   required:
+     - compatible
+@@ -43,6 +44,7 @@ properties:
+           - rockchip,rk3399-pmu
+           - rockchip,rk3568-pmu
+           - rockchip,rk3588-pmu
++          - rockchip,rv1126-pmu
+       - const: syscon
+       - const: simple-mfd
+ 
diff --git a/target/linux/rockchip/patches-6.1/185-dt-bindings-clock-add-rk3588-cru-bindings.patch b/target/linux/rockchip/patches-6.1/185-dt-bindings-clock-add-rk3588-cru-bindings.patch
new file mode 100644
index 00000000000..c87b7c2985c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/185-dt-bindings-clock-add-rk3588-cru-bindings.patch
@@ -0,0 +1,93 @@
+From 3330b6c24f398ae6cae0ab1ccd63ccb2bed23734 Mon Sep 17 00:00:00 2001
+From: Elaine Zhang <zhangqing@rock-chips.com>
+Date: Tue, 18 Oct 2022 17:14:01 +0200
+Subject: [PATCH 185/383] dt-bindings: clock: add rk3588 cru bindings
+
+Document the device tree bindings of the rockchip rk3588 SoC
+clock and reset unit.
+
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-4-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/clock/rockchip,rk3588-cru.yaml   | 71 +++++++++++++++++++
+ 1 file changed, 71 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/clock/rockchip,rk3588-cru.yaml
+@@ -0,0 +1,71 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/clock/rockchip,rk3588-cru.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip rk3588 Family Clock and Reset Control Module
++
++maintainers:
++  - Elaine Zhang <zhangqing@rock-chips.com>
++  - Heiko Stuebner <heiko@sntech.de>
++
++description: |
++  The RK3588 clock controller generates the clock and also implements a reset
++  controller for SoC peripherals. For example it provides SCLK_UART2 and
++  PCLK_UART2, as well as SRST_P_UART2 and SRST_S_UART2 for the second UART
++  module.
++  Each clock is assigned an identifier and client nodes can use this identifier
++  to specify the clock which they consume. All available clock and reset IDs
++  are defined as preprocessor macros in dt-binding headers.
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3588-cru
++
++  reg:
++    maxItems: 1
++
++  "#clock-cells":
++    const: 1
++
++  "#reset-cells":
++    const: 1
++
++  clocks:
++    minItems: 2
++    maxItems: 2
++
++  clock-names:
++    items:
++      - const: xin24m
++      - const: xin32k
++
++  assigned-clocks: true
++
++  assigned-clock-rates: true
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description: >
++      phandle to the syscon managing the "general register files". It is used
++      for GRF muxes, if missing any muxes present in the GRF will not be
++      available.
++
++required:
++  - compatible
++  - reg
++  - "#clock-cells"
++  - "#reset-cells"
++
++additionalProperties: false
++
++examples:
++  - |
++    cru: clock-controller@fd7c0000 {
++      compatible = "rockchip,rk3588-cru";
++      reg = <0xfd7c0000 0x5c000>;
++      #clock-cells = <1>;
++      #reset-cells = <1>;
++    };
diff --git a/target/linux/rockchip/patches-6.1/186-dt-bindings-display-rockchip-convert-rockchip-lvds.t.patch b/target/linux/rockchip/patches-6.1/186-dt-bindings-display-rockchip-convert-rockchip-lvds.t.patch
new file mode 100644
index 00000000000..c539a8fc967
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/186-dt-bindings-display-rockchip-convert-rockchip-lvds.t.patch
@@ -0,0 +1,292 @@
+From be15b9e321ec6bb0f63d8b3cf7afd6f6fd8f6aee Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:22:14 +0100
+Subject: [PATCH 186/383] dt-bindings: display: rockchip: convert
+ rockchip-lvds.txt to YAML
+
+Convert rockchip-lvds.txt to YAML.
+
+Changed:
+  Add power-domains property.
+  Requirements between PX30 and RK3288
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/67771143-fd83-383d-41b2-68e8707134e8@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../display/rockchip/rockchip,lvds.yaml       | 170 ++++++++++++++++++
+ .../display/rockchip/rockchip-lvds.txt        |  92 ----------
+ 2 files changed, 170 insertions(+), 92 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml
+ delete mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,lvds.yaml
+@@ -0,0 +1,170 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/rockchip/rockchip,lvds.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip low-voltage differential signal (LVDS) transmitter
++
++maintainers:
++  - Sandy Huang <hjc@rock-chips.com>
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,px30-lvds
++      - rockchip,rk3288-lvds
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    maxItems: 1
++
++  clock-names:
++    const: pclk_lvds
++
++  avdd1v0-supply:
++    description: 1.0V analog power.
++
++  avdd1v8-supply:
++    description: 1.8V analog power.
++
++  avdd3v3-supply:
++    description: 3.3V analog power.
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description: Phandle to the general register files syscon.
++
++  rockchip,output:
++    $ref: /schemas/types.yaml#/definitions/string
++    enum: [rgb, lvds, duallvds]
++    description: This describes the output interface.
++
++  phys:
++    maxItems: 1
++
++  phy-names:
++    const: dphy
++
++  pinctrl-names:
++    const: lcdc
++
++  pinctrl-0: true
++
++  power-domains:
++    maxItems: 1
++
++  ports:
++    $ref: /schemas/graph.yaml#/properties/ports
++
++    properties:
++      port@0:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Video port 0 for the VOP input.
++          The remote endpoint maybe vopb or vopl.
++
++      port@1:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Video port 1 for either a panel or subsequent encoder.
++
++    required:
++      - port@0
++      - port@1
++
++required:
++  - compatible
++  - rockchip,grf
++  - rockchip,output
++  - ports
++
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,px30-lvds
++
++    then:
++      properties:
++        reg: false
++        clocks: false
++        clock-names: false
++        avdd1v0-supply: false
++        avdd1v8-supply: false
++        avdd3v3-supply: false
++
++      required:
++        - phys
++        - phy-names
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,rk3288-lvds
++
++    then:
++      properties:
++        phys: false
++        phy-names: false
++
++      required:
++        - reg
++        - clocks
++        - clock-names
++        - avdd1v0-supply
++        - avdd1v8-supply
++        - avdd3v3-supply
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3288-cru.h>
++
++    lvds: lvds@ff96c000 {
++      compatible = "rockchip,rk3288-lvds";
++      reg = <0xff96c000 0x4000>;
++      clocks = <&cru PCLK_LVDS_PHY>;
++      clock-names = "pclk_lvds";
++      avdd1v0-supply = <&vdd10_lcd>;
++      avdd1v8-supply = <&vcc18_lcd>;
++      avdd3v3-supply = <&vcca_33>;
++      pinctrl-names = "lcdc";
++      pinctrl-0 = <&lcdc_ctl>;
++      rockchip,grf = <&grf>;
++      rockchip,output = "rgb";
++
++      ports {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        lvds_in: port@0 {
++          reg = <0>;
++          #address-cells = <1>;
++          #size-cells = <0>;
++
++          lvds_in_vopb: endpoint@0 {
++            reg = <0>;
++            remote-endpoint = <&vopb_out_lvds>;
++          };
++          lvds_in_vopl: endpoint@1 {
++            reg = <1>;
++            remote-endpoint = <&vopl_out_lvds>;
++          };
++        };
++
++        lvds_out: port@1 {
++          reg = <1>;
++
++          lvds_out_panel: endpoint {
++            remote-endpoint = <&panel_in_lvds>;
++          };
++        };
++      };
++    };
+--- a/Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
++++ /dev/null
+@@ -1,92 +0,0 @@
+-Rockchip RK3288 LVDS interface
+-================================
+-
+-Required properties:
+-- compatible: matching the soc type, one of
+-	- "rockchip,rk3288-lvds";
+-	- "rockchip,px30-lvds";
+-
+-- reg: physical base address of the controller and length
+-	of memory mapped region.
+-- clocks: must include clock specifiers corresponding to entries in the
+-	clock-names property.
+-- clock-names: must contain "pclk_lvds"
+-
+-- avdd1v0-supply: regulator phandle for 1.0V analog power
+-- avdd1v8-supply: regulator phandle for 1.8V analog power
+-- avdd3v3-supply: regulator phandle for 3.3V analog power
+-
+-- rockchip,grf: phandle to the general register files syscon
+-- rockchip,output: "rgb", "lvds" or "duallvds", This describes the output interface
+-
+-- phys: LVDS/DSI DPHY (px30 only)
+-- phy-names: name of the PHY, must be "dphy" (px30 only)
+-
+-Optional properties:
+-- pinctrl-names: must contain a "lcdc" entry.
+-- pinctrl-0: pin control group to be used for this controller.
+-
+-Required nodes:
+-
+-The lvds has two video ports as described by
+-	Documentation/devicetree/bindings/media/video-interfaces.txt
+-Their connections are modeled using the OF graph bindings specified in
+-	Documentation/devicetree/bindings/graph.txt.
+-
+-- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+-- video port 1 for either a panel or subsequent encoder
+-
+-Example:
+-
+-lvds_panel: lvds-panel {
+-	compatible = "auo,b101ean01";
+-	enable-gpios = <&gpio7 21 GPIO_ACTIVE_HIGH>;
+-	data-mapping = "jeida-24";
+-
+-	ports {
+-		panel_in_lvds: endpoint {
+-			remote-endpoint = <&lvds_out_panel>;
+-		};
+-	};
+-};
+-
+-For Rockchip RK3288:
+-
+-	lvds: lvds@ff96c000 {
+-		compatible = "rockchip,rk3288-lvds";
+-		rockchip,grf = <&grf>;
+-		reg = <0xff96c000 0x4000>;
+-		clocks = <&cru PCLK_LVDS_PHY>;
+-		clock-names = "pclk_lvds";
+-		pinctrl-names = "lcdc";
+-		pinctrl-0 = <&lcdc_ctl>;
+-		avdd1v0-supply = <&vdd10_lcd>;
+-		avdd1v8-supply = <&vcc18_lcd>;
+-		avdd3v3-supply = <&vcca_33>;
+-		rockchip,output = "rgb";
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			lvds_in: port@0 {
+-				reg = <0>;
+-
+-				lvds_in_vopb: endpoint@0 {
+-					reg = <0>;
+-					remote-endpoint = <&vopb_out_lvds>;
+-				};
+-				lvds_in_vopl: endpoint@1 {
+-					reg = <1>;
+-					remote-endpoint = <&vopl_out_lvds>;
+-				};
+-			};
+-
+-			lvds_out: port@1 {
+-				reg = <1>;
+-
+-				lvds_out_panel: endpoint {
+-					remote-endpoint = <&panel_in_lvds>;
+-				};
+-			};
+-		};
+-	};
diff --git a/target/linux/rockchip/patches-6.1/187-dt-bindings-display-rockchip-convert-dw_mipi_dsi_roc.patch b/target/linux/rockchip/patches-6.1/187-dt-bindings-display-rockchip-convert-dw_mipi_dsi_roc.patch
new file mode 100644
index 00000000000..4bd7bea0d81
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/187-dt-bindings-display-rockchip-convert-dw_mipi_dsi_roc.patch
@@ -0,0 +1,290 @@
+From e268e840d93b48076d717a92993f33705dac736f Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:26:28 +0100
+Subject: [PATCH 187/383] dt-bindings: display: rockchip: convert
+ dw_mipi_dsi_rockchip.txt to yaml
+
+Convert dw_mipi_dsi_rockchip.txt to yaml.
+
+Changed:
+  file name
+  requirements
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/d6dc8453-4807-0a5d-15bf-6dcf80dcd0fe@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../display/rockchip/dw_mipi_dsi_rockchip.txt |  94 ----------
+ .../rockchip/rockchip,dw-mipi-dsi.yaml        | 166 ++++++++++++++++++
+ 2 files changed, 166 insertions(+), 94 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
+ create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
+
+--- a/Documentation/devicetree/bindings/display/rockchip/dw_mipi_dsi_rockchip.txt
++++ /dev/null
+@@ -1,94 +0,0 @@
+-Rockchip specific extensions to the Synopsys Designware MIPI DSI
+-================================
+-
+-Required properties:
+-- #address-cells: Should be <1>.
+-- #size-cells: Should be <0>.
+-- compatible: one of
+-	"rockchip,px30-mipi-dsi", "snps,dw-mipi-dsi"
+-	"rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi"
+-	"rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi"
+-	"rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi"
+-- reg: Represent the physical address range of the controller.
+-- interrupts: Represent the controller's interrupt to the CPU(s).
+-- clocks, clock-names: Phandles to the controller's pll reference
+-  clock(ref) when using an internal dphy and APB clock(pclk).
+-  For RK3399, a phy config clock (phy_cfg) and a grf clock(grf)
+-  are required. As described in [1].
+-- rockchip,grf: this soc should set GRF regs to mux vopl/vopb.
+-- ports: contain a port node with endpoint definitions as defined in [2].
+-  For vopb,set the reg = <0> and set the reg = <1> for vopl.
+-- video port 0 for the VOP input, the remote endpoint maybe vopb or vopl
+-- video port 1 for either a panel or subsequent encoder
+-
+-Optional properties:
+-- phys: from general PHY binding: the phandle for the PHY device.
+-- phy-names: Should be "dphy" if phys references an external phy.
+-- #phy-cells: Defined when used as ISP phy, should be 0.
+-- power-domains: a phandle to mipi dsi power domain node.
+-- resets: list of phandle + reset specifier pairs, as described in [3].
+-- reset-names: string reset name, must be "apb".
+-
+-[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+-[2] Documentation/devicetree/bindings/media/video-interfaces.txt
+-[3] Documentation/devicetree/bindings/reset/reset.txt
+-
+-Example:
+-	mipi_dsi: mipi@ff960000 {
+-		#address-cells = <1>;
+-		#size-cells = <0>;
+-		compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
+-		reg = <0xff960000 0x4000>;
+-		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cru SCLK_MIPI_24M>, <&cru PCLK_MIPI_DSI0>;
+-		clock-names = "ref", "pclk";
+-		resets = <&cru SRST_MIPIDSI0>;
+-		reset-names = "apb";
+-		rockchip,grf = <&grf>;
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-
+-			mipi_in: port@0 {
+-				reg = <0>;
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				mipi_in_vopb: endpoint@0 {
+-					reg = <0>;
+-					remote-endpoint = <&vopb_out_mipi>;
+-				};
+-				mipi_in_vopl: endpoint@1 {
+-					reg = <1>;
+-					remote-endpoint = <&vopl_out_mipi>;
+-				};
+-			};
+-
+-			mipi_out: port@1 {
+-				reg = <1>;
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-
+-				mipi_out_panel: endpoint {
+-					remote-endpoint = <&panel_in_mipi>;
+-				};
+-			};
+-		};
+-
+-		panel {
+-			compatible ="boe,tv080wum-nl0";
+-			reg = <0>;
+-
+-			enable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
+-			pinctrl-names = "default";
+-			pinctrl-0 = <&lcd_en>;
+-			backlight = <&backlight>;
+-
+-			port {
+-				panel_in_mipi: endpoint {
+-					remote-endpoint = <&mipi_out_panel>;
+-				};
+-			};
+-		};
+-	};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml
+@@ -0,0 +1,166 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-mipi-dsi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip specific extensions to the Synopsys Designware MIPI DSI
++
++maintainers:
++  - Sandy Huang <hjc@rock-chips.com>
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    items:
++      - enum:
++          - rockchip,px30-mipi-dsi
++          - rockchip,rk3288-mipi-dsi
++          - rockchip,rk3399-mipi-dsi
++          - rockchip,rk3568-mipi-dsi
++      - const: snps,dw-mipi-dsi
++
++  interrupts:
++    maxItems: 1
++
++  clocks:
++    minItems: 1
++    maxItems: 4
++
++  clock-names:
++    oneOf:
++      - minItems: 2
++        items:
++          - const: ref
++          - const: pclk
++          - const: phy_cfg
++          - const: grf
++      - const: pclk
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      This SoC uses GRF regs to switch between vopl/vopb.
++
++  phys:
++    maxItems: 1
++
++  phy-names:
++    const: dphy
++
++  "#phy-cells":
++    const: 0
++    description:
++      Defined when in use as ISP phy.
++
++  power-domains:
++    maxItems: 1
++
++  "#address-cells":
++    const: 1
++
++  "#size-cells":
++    const: 0
++
++required:
++  - compatible
++  - clocks
++  - clock-names
++  - rockchip,grf
++
++allOf:
++  - $ref: /schemas/display/bridge/snps,dw-mipi-dsi.yaml#
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - rockchip,px30-mipi-dsi
++              - rockchip,rk3568-mipi-dsi
++
++    then:
++      properties:
++        clocks:
++          maxItems: 1
++
++        clock-names:
++          maxItems: 1
++
++      required:
++        - phys
++        - phy-names
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,rk3288-mipi-dsi
++
++    then:
++      properties:
++        clocks:
++          maxItems: 2
++
++        clock-names:
++          maxItems: 2
++
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,rk3399-mipi-dsi
++
++    then:
++      properties:
++        clocks:
++          minItems: 4
++
++        clock-names:
++          minItems: 4
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3288-cru.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++
++    mipi_dsi: dsi@ff960000 {
++      compatible = "rockchip,rk3288-mipi-dsi", "snps,dw-mipi-dsi";
++      reg = <0xff960000 0x4000>;
++      interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
++      clocks = <&cru SCLK_MIPIDSI_24M>, <&cru PCLK_MIPI_DSI0>;
++      clock-names = "ref", "pclk";
++      resets = <&cru SRST_MIPIDSI0>;
++      reset-names = "apb";
++      rockchip,grf = <&grf>;
++
++      ports {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        mipi_in: port@0 {
++          reg = <0>;
++          #address-cells = <1>;
++          #size-cells = <0>;
++
++          mipi_in_vopb: endpoint@0 {
++            reg = <0>;
++            remote-endpoint = <&vopb_out_mipi>;
++          };
++          mipi_in_vopl: endpoint@1 {
++            reg = <1>;
++            remote-endpoint = <&vopl_out_mipi>;
++          };
++        };
++
++        mipi_out: port@1 {
++          reg = <1>;
++
++          mipi_out_panel: endpoint {
++            remote-endpoint = <&panel_in_mipi>;
++          };
++        };
++      };
++    };
diff --git a/target/linux/rockchip/patches-6.1/188-dt-bindings-display-rockchip-convert-analogix_dp-roc.patch b/target/linux/rockchip/patches-6.1/188-dt-bindings-display-rockchip-convert-analogix_dp-roc.patch
new file mode 100644
index 00000000000..f56e527ac68
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/188-dt-bindings-display-rockchip-convert-analogix_dp-roc.patch
@@ -0,0 +1,231 @@
+From d3900411b446201a96e2063b4f0afbfda8a875c9 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:27:35 +0100
+Subject: [PATCH 188/383] dt-bindings: display: rockchip: convert
+ analogix_dp-rockchip.txt to yaml
+
+Convert analogix_dp-rockchip.txt to yaml.
+
+Changed:
+  Add power-domains property
+  File name
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/88a5a9e3-9bc8-5966-22ec-5bdb1fa7a5b1@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../display/rockchip/analogix_dp-rockchip.txt |  98 -----------------
+ .../rockchip/rockchip,analogix-dp.yaml        | 103 ++++++++++++++++++
+ 2 files changed, 103 insertions(+), 98 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+ create mode 100644 Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
+
+--- a/Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
++++ /dev/null
+@@ -1,98 +0,0 @@
+-Rockchip RK3288 specific extensions to the Analogix Display Port
+-================================
+-
+-Required properties:
+-- compatible: "rockchip,rk3288-dp",
+-	      "rockchip,rk3399-edp";
+-
+-- reg: physical base address of the controller and length
+-
+-- clocks: from common clock binding: handle to dp clock.
+-	  of memory mapped region.
+-
+-- clock-names: from common clock binding:
+-	       Required elements: "dp" "pclk"
+-
+-- resets: Must contain an entry for each entry in reset-names.
+-	  See ../reset/reset.txt for details.
+-
+-- pinctrl-names: Names corresponding to the chip hotplug pinctrl states.
+-- pinctrl-0: pin-control mode. should be <&edp_hpd>
+-
+-- reset-names: Must include the name "dp"
+-
+-- rockchip,grf: this soc should set GRF regs, so need get grf here.
+-
+-- ports: there are 2 port nodes with endpoint definitions as defined in
+-  Documentation/devicetree/bindings/media/video-interfaces.txt.
+-    Port 0: contained 2 endpoints, connecting to the output of vop.
+-    Port 1: contained 1 endpoint, connecting to the input of panel.
+-
+-Optional property for different chips:
+-- clocks: from common clock binding: handle to grf_vio clock.
+-
+-- clock-names: from common clock binding:
+-	       Required elements: "grf"
+-
+-For the below properties, please refer to Analogix DP binding document:
+- * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+-- phys (required)
+-- phy-names (required)
+-- hpd-gpios (optional)
+-- force-hpd (optional)
+--------------------------------------------------------------------------------
+-
+-Example:
+-	dp-controller: dp@ff970000 {
+-		compatible = "rockchip,rk3288-dp";
+-		reg = <0xff970000 0x4000>;
+-		interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
+-		clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
+-		clock-names = "dp", "pclk";
+-		phys = <&dp_phy>;
+-		phy-names = "dp";
+-
+-		rockchip,grf = <&grf>;
+-		resets = <&cru 111>;
+-		reset-names = "dp";
+-
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&edp_hpd>;
+-
+-
+-		ports {
+-			#address-cells = <1>;
+-			#size-cells = <0>;
+-			edp_in: port@0 {
+-				reg = <0>;
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-				edp_in_vopb: endpoint@0 {
+-					reg = <0>;
+-					remote-endpoint = <&vopb_out_edp>;
+-				};
+-				edp_in_vopl: endpoint@1 {
+-					reg = <1>;
+-					remote-endpoint = <&vopl_out_edp>;
+-				};
+-			};
+-
+-			edp_out: port@1 {
+-				reg = <1>;
+-				#address-cells = <1>;
+-				#size-cells = <0>;
+-				edp_out_panel: endpoint {
+-					reg = <0>;
+-					remote-endpoint = <&panel_in_edp>
+-				};
+-			};
+-		};
+-	};
+-
+-	pinctrl {
+-		edp {
+-			edp_hpd: edp-hpd {
+-				rockchip,pins = <7 11 RK_FUNC_2 &pcfg_pull_none>;
+-			};
+-		};
+-	};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,analogix-dp.yaml
+@@ -0,0 +1,103 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/rockchip/rockchip,analogix-dp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip specific extensions to the Analogix Display Port
++
++maintainers:
++  - Sandy Huang <hjc@rock-chips.com>
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3288-dp
++      - rockchip,rk3399-edp
++
++  clocks:
++    minItems: 2
++    maxItems: 3
++
++  clock-names:
++    minItems: 2
++    items:
++      - const: dp
++      - const: pclk
++      - const: grf
++
++  power-domains:
++    maxItems: 1
++
++  resets:
++    maxItems: 1
++
++  reset-names:
++    const: dp
++
++  rockchip,grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      This SoC makes use of GRF regs.
++
++required:
++  - compatible
++  - clocks
++  - clock-names
++  - resets
++  - reset-names
++  - rockchip,grf
++
++allOf:
++  - $ref: /schemas/display/bridge/analogix,dp.yaml#
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3288-cru.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++    dp@ff970000 {
++      compatible = "rockchip,rk3288-dp";
++      reg = <0xff970000 0x4000>;
++      interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
++      clocks = <&cru SCLK_EDP>, <&cru PCLK_EDP_CTRL>;
++      clock-names = "dp", "pclk";
++      phys = <&dp_phy>;
++      phy-names = "dp";
++      resets = <&cru 111>;
++      reset-names = "dp";
++      rockchip,grf = <&grf>;
++      pinctrl-0 = <&edp_hpd>;
++      pinctrl-names = "default";
++
++      ports {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        edp_in: port@0 {
++          reg = <0>;
++          #address-cells = <1>;
++          #size-cells = <0>;
++
++          edp_in_vopb: endpoint@0 {
++            reg = <0>;
++            remote-endpoint = <&vopb_out_edp>;
++          };
++          edp_in_vopl: endpoint@1 {
++            reg = <1>;
++            remote-endpoint = <&vopl_out_edp>;
++          };
++        };
++
++        edp_out: port@1 {
++          reg = <1>;
++
++          edp_out_panel: endpoint {
++            remote-endpoint = <&panel_in_edp>;
++          };
++        };
++      };
++    };
diff --git a/target/linux/rockchip/patches-6.1/189-dt-bindings-display-dsi-controller-move-clock-master.patch b/target/linux/rockchip/patches-6.1/189-dt-bindings-display-dsi-controller-move-clock-master.patch
new file mode 100644
index 00000000000..b91a759f19d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/189-dt-bindings-display-dsi-controller-move-clock-master.patch
@@ -0,0 +1,52 @@
+From b18322b37517cf18c412e8372edc73a20deae5d4 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:24:51 +0100
+Subject: [PATCH 189/383] dt-bindings: display: dsi-controller: move
+ clock-master property
+
+The clock-master property is used for the controller and not in the panel,
+so move it there.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/1c3b18ad-350f-e862-de98-a775e11e132c@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/display/dsi-controller.yaml       | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+--- a/Documentation/devicetree/bindings/display/dsi-controller.yaml
++++ b/Documentation/devicetree/bindings/display/dsi-controller.yaml
+@@ -30,6 +30,15 @@ properties:
+   $nodename:
+     pattern: "^dsi(@.*)?$"
+ 
++  clock-master:
++    type: boolean
++    description:
++      Should be enabled if the host is being used in conjunction with
++      another DSI host to drive the same peripheral. Hardware supporting
++      such a configuration generally requires the data on both the busses
++      to be driven by the same clock. Only the DSI host instance
++      controlling this clock should contain this property.
++
+   "#address-cells":
+     const: 1
+ 
+@@ -52,15 +61,6 @@ patternProperties:
+           case the reg property can take multiple entries, one for each virtual
+           channel that the peripheral responds to.
+ 
+-      clock-master:
+-        type: boolean
+-        description:
+-          Should be enabled if the host is being used in conjunction with
+-          another DSI host to drive the same peripheral. Hardware supporting
+-          such a configuration generally requires the data on both the busses
+-          to be driven by the same clock. Only the DSI host instance
+-          controlling this clock should contain this property.
+-
+       enforce-video-mode:
+         type: boolean
+         description:
diff --git a/target/linux/rockchip/patches-6.1/190-dt-bindings-display-bridge-snps-dw-mipi-dsi-fix-cloc.patch b/target/linux/rockchip/patches-6.1/190-dt-bindings-display-bridge-snps-dw-mipi-dsi-fix-cloc.patch
new file mode 100644
index 00000000000..eb97fc02848
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/190-dt-bindings-display-bridge-snps-dw-mipi-dsi-fix-cloc.patch
@@ -0,0 +1,42 @@
+From 325090fe4cd0232cdf0e0bb3fe2bfb16646439cf Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:25:44 +0100
+Subject: [PATCH 190/383] dt-bindings: display: bridge: snps,dw-mipi-dsi: fix
+ clock properties
+
+Fix clock properties from the common snps,dw-mipi-dsi.yaml file,
+as they don't match with what is used on the SoCs.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/78b4548e-dfe1-d0c6-f96c-5d40f28f8b2e@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../display/bridge/snps,dw-mipi-dsi.yaml         | 16 +++-------------
+ 1 file changed, 3 insertions(+), 13 deletions(-)
+
+--- a/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
++++ b/Documentation/devicetree/bindings/display/bridge/snps,dw-mipi-dsi.yaml
+@@ -26,19 +26,9 @@ properties:
+   reg:
+     maxItems: 1
+ 
+-  clocks:
+-    items:
+-      - description: Module clock
+-      - description: DSI bus clock for either AHB and APB
+-      - description: Pixel clock for the DPI/RGB input
+-    minItems: 2
++  clocks: true
+ 
+-  clock-names:
+-    items:
+-      - const: ref
+-      - const: pclk
+-      - const: px_clk
+-    minItems: 2
++  clock-names: true
+ 
+   resets:
+     maxItems: 1
diff --git a/target/linux/rockchip/patches-6.1/191-dt-bindings-display-bridge-convert-analogix_dp.txt-t.patch b/target/linux/rockchip/patches-6.1/191-dt-bindings-display-bridge-convert-analogix_dp.txt-t.patch
new file mode 100644
index 00000000000..d9e0e278950
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/191-dt-bindings-display-bridge-convert-analogix_dp.txt-t.patch
@@ -0,0 +1,155 @@
+From da32f359f8dbeb93b410f1d2d77dd88fd20ea297 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:26:57 +0100
+Subject: [PATCH 191/383] dt-bindings: display: bridge: convert analogix_dp.txt
+ to yaml
+
+Convert analogix_dp.txt to yaml for use as common document.
+
+Changed:
+  Relexed requirements
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/489e7bd3-fa26-885f-4104-8b0b29aa4f2b@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/display/bridge/analogix,dp.yaml  | 63 +++++++++++++++++++
+ .../bindings/display/bridge/analogix_dp.txt   | 51 ---------------
+ .../bindings/display/exynos/exynos_dp.txt     |  2 +-
+ 3 files changed, 64 insertions(+), 52 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
+ delete mode 100644 Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
+@@ -0,0 +1,63 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/display/bridge/analogix,dp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Analogix Display Port bridge
++
++maintainers:
++  - Rob Herring <robh@kernel.org>
++
++properties:
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  clocks: true
++
++  clock-names: true
++
++  phys: true
++
++  phy-names:
++    const: dp
++
++  force-hpd:
++    description:
++      Indicate driver need force hpd when hpd detect failed, this
++      is used for some eDP screen which don not have a hpd signal.
++
++  hpd-gpios:
++    description:
++      Hotplug detect GPIO.
++      Indicates which GPIO should be used for hotplug detection
++
++  ports:
++    $ref: /schemas/graph.yaml#/properties/ports
++
++    properties:
++      port@0:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Input node to receive pixel data.
++
++      port@1:
++        $ref: /schemas/graph.yaml#/properties/port
++        description:
++          Port node with one endpoint connected to a dp-connector node.
++
++    required:
++      - port@0
++      - port@1
++
++required:
++  - reg
++  - interrupts
++  - clock-names
++  - clocks
++  - ports
++
++additionalProperties: true
+--- a/Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
++++ /dev/null
+@@ -1,51 +0,0 @@
+-Analogix Display Port bridge bindings
+-
+-Required properties for dp-controller:
+-	-compatible:
+-		platform specific such as:
+-		 * "samsung,exynos5-dp"
+-		 * "rockchip,rk3288-dp"
+-		 * "rockchip,rk3399-edp"
+-	-reg:
+-		physical base address of the controller and length
+-		of memory mapped region.
+-	-interrupts:
+-		interrupt combiner values.
+-	-clocks:
+-		from common clock binding: handle to dp clock.
+-	-clock-names:
+-		from common clock binding: Shall be "dp".
+-	-phys:
+-		from general PHY binding: the phandle for the PHY device.
+-	-phy-names:
+-		from general PHY binding: Should be "dp".
+-
+-Optional properties for dp-controller:
+-	-force-hpd:
+-		Indicate driver need force hpd when hpd detect failed, this
+-		is used for some eDP screen which don't have hpd signal.
+-	-hpd-gpios:
+-		Hotplug detect GPIO.
+-		Indicates which GPIO should be used for hotplug detection
+-	-port@[X]: SoC specific port nodes with endpoint definitions as defined
+-		in Documentation/devicetree/bindings/media/video-interfaces.txt,
+-		please refer to the SoC specific binding document:
+-		* Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+-		* Documentation/devicetree/bindings/display/rockchip/analogix_dp-rockchip.txt
+-
+-[1]: Documentation/devicetree/bindings/media/video-interfaces.txt
+--------------------------------------------------------------------------------
+-
+-Example:
+-
+-	dp-controller {
+-		compatible = "samsung,exynos5-dp";
+-		reg = <0x145b0000 0x10000>;
+-		interrupts = <10 3>;
+-		interrupt-parent = <&combiner>;
+-		clocks = <&clock 342>;
+-		clock-names = "dp";
+-
+-		phys = <&dp_phy>;
+-		phy-names = "dp";
+-	};
+--- a/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
++++ b/Documentation/devicetree/bindings/display/exynos/exynos_dp.txt
+@@ -50,7 +50,7 @@ Optional properties for dp-controller:
+ 		Documentation/devicetree/bindings/display/panel/display-timing.txt
+ 
+ For the below properties, please refer to Analogix DP binding document:
+- * Documentation/devicetree/bindings/display/bridge/analogix_dp.txt
++ * Documentation/devicetree/bindings/display/bridge/analogix,dp.yaml
+ 	-phys (required)
+ 	-phy-names (required)
+ 	-hpd-gpios (optional)
diff --git a/target/linux/rockchip/patches-6.1/192-dt-bindings-mfd-Add-rk806-binding.patch b/target/linux/rockchip/patches-6.1/192-dt-bindings-mfd-Add-rk806-binding.patch
new file mode 100644
index 00000000000..9a56a5e6dce
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/192-dt-bindings-mfd-Add-rk806-binding.patch
@@ -0,0 +1,426 @@
+From 1f9b12b19fab56acdba865f511ee5ee40970a39e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:11 +0200
+Subject: [PATCH 192/383] dt-bindings: mfd: Add rk806 binding
+
+Add DT binding document for Rockchip's RK806 PMIC.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-8-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/mfd/rockchip,rk806.yaml          | 406 ++++++++++++++++++
+ 1 file changed, 406 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
+@@ -0,0 +1,406 @@
++# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/mfd/rockchip,rk806.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: RK806 Power Management Integrated Circuit
++
++maintainers:
++  - Sebastian Reichel <sebastian.reichel@collabora.com>
++
++description:
++  Rockchip RK806 series PMIC. This device consists of an spi or
++  i2c controlled MFD that includes multiple switchable regulators.
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk806
++
++  reg:
++    maxItems: 1
++
++  interrupts:
++    maxItems: 1
++
++  gpio-controller: true
++
++  '#gpio-cells':
++    const: 2
++
++  vcc1-supply:
++    description:
++      The input supply for dcdc-reg1.
++
++  vcc2-supply:
++    description:
++      The input supply for dcdc-reg2.
++
++  vcc3-supply:
++    description:
++      The input supply for dcdc-reg3.
++
++  vcc4-supply:
++    description:
++      The input supply for dcdc-reg4.
++
++  vcc5-supply:
++    description:
++      The input supply for dcdc-reg5.
++
++  vcc6-supply:
++    description:
++      The input supply for dcdc-reg6.
++
++  vcc7-supply:
++    description:
++      The input supply for dcdc-reg7.
++
++  vcc8-supply:
++    description:
++      The input supply for dcdc-reg8.
++
++  vcc9-supply:
++    description:
++      The input supply for dcdc-reg9.
++
++  vcc10-supply:
++    description:
++      The input supply for dcdc-reg10.
++
++  vcc11-supply:
++    description:
++      The input supply for pldo-reg1, pldo-reg2 and pldo-reg3.
++
++  vcc12-supply:
++    description:
++      The input supply for pldo-reg4 and pldo-reg5.
++
++  vcc13-supply:
++    description:
++      The input supply for nldo-reg1, nldo-reg2 and nldo-reg3.
++
++  vcc14-supply:
++    description:
++      The input supply for nldo-reg4 and nldo-reg5.
++
++  vcca-supply:
++    description:
++      The input supply for pldo-reg6.
++
++  regulators:
++    type: object
++    additionalProperties: false
++    patternProperties:
++      "^(dcdc-reg([1-9]|10)|pldo-reg[1-6]|nldo-reg[1-5])$":
++        type: object
++        $ref: /schemas/regulator/regulator.yaml#
++        unevaluatedProperties: false
++
++patternProperties:
++  '-pins$':
++    type: object
++    additionalProperties: false
++    $ref: /schemas/pinctrl/pinmux-node.yaml
++
++    properties:
++      function:
++        enum: [pin_fun0, pin_fun1, pin_fun2, pin_fun3, pin_fun4, pin_fun5]
++
++      pins:
++        $ref: /schemas/types.yaml#/definitions/string
++        enum: [gpio_pwrctrl1, gpio_pwrctrl2, gpio_pwrctrl3]
++
++allOf:
++  - $ref: /schemas/spi/spi-peripheral-props.yaml
++
++required:
++  - compatible
++  - reg
++  - interrupts
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/pinctrl/rockchip.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++    #include <dt-bindings/gpio/gpio.h>
++    spi {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        pmic@0 {
++            compatible = "rockchip,rk806";
++            reg = <0x0>;
++
++            interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++            vcc1-supply = <&vcc5v0_sys>;
++            vcc2-supply = <&vcc5v0_sys>;
++            vcc3-supply = <&vcc5v0_sys>;
++            vcc4-supply = <&vcc5v0_sys>;
++            vcc5-supply = <&vcc5v0_sys>;
++            vcc6-supply = <&vcc5v0_sys>;
++            vcc7-supply = <&vcc5v0_sys>;
++            vcc8-supply = <&vcc5v0_sys>;
++            vcc9-supply = <&vcc5v0_sys>;
++            vcc10-supply = <&vcc5v0_sys>;
++            vcc11-supply = <&vcc_2v0_pldo_s3>;
++            vcc12-supply = <&vcc5v0_sys>;
++            vcc13-supply = <&vcc5v0_sys>;
++            vcc14-supply = <&vcc_1v1_nldo_s3>;
++            vcca-supply = <&vcc5v0_sys>;
++
++            regulators {
++                vdd_gpu_s0: dcdc-reg1 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <550000>;
++                    regulator-max-microvolt = <950000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_gpu_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd_npu_s0: dcdc-reg2 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <550000>;
++                    regulator-max-microvolt = <950000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_npu_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd_log_s0: dcdc-reg3 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <750000>;
++                    regulator-max-microvolt = <750000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_log_s0";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <750000>;
++                    };
++                };
++
++                vdd_vdenc_s0: dcdc-reg4 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <550000>;
++                    regulator-max-microvolt = <950000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_vdenc_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd_gpu_mem_s0: dcdc-reg5 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <675000>;
++                    regulator-max-microvolt = <950000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_gpu_mem_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd_npu_mem_s0: dcdc-reg6 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <675000>;
++                    regulator-max-microvolt = <950000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_npu_mem_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vcc_2v0_pldo_s3: dcdc-reg7 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <2000000>;
++                    regulator-max-microvolt = <2000000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_2v0_pldo_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <2000000>;
++                    };
++                };
++
++                vdd_vdenc_mem_s0: dcdc-reg8 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <675000>;
++                    regulator-max-microvolt = <950000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_vdenc_mem_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd2_ddr_s3: dcdc-reg9 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-name = "vdd2_ddr_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                    };
++                };
++
++                vcc_1v1_nldo_s3: dcdc-reg10 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <1100000>;
++                    regulator-max-microvolt = <1100000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vcc_1v1_nldo_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <1100000>;
++                    };
++                };
++
++                avcc_1v8_s0: pldo-reg1 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <1800000>;
++                    regulator-max-microvolt = <1800000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "avcc_1v8_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd1_1v8_ddr_s3: pldo-reg2 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <1800000>;
++                    regulator-max-microvolt = <1800000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd1_1v8_ddr_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <1800000>;
++                    };
++                };
++
++                vcc_1v8_s3: pldo-reg3 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <1800000>;
++                    regulator-max-microvolt = <1800000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vcc_1v8_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <1800000>;
++                    };
++                };
++
++                vcc_3v3_s0: pldo-reg4 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <3300000>;
++                    regulator-max-microvolt = <3300000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vcc_3v3_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vccio_sd_s0: pldo-reg5 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <1800000>;
++                    regulator-max-microvolt = <3300000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vccio_sd_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                master_pldo6_s3: pldo-reg6 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <1800000>;
++                    regulator-max-microvolt = <1800000>;
++                    regulator-name = "master_pldo6_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <1800000>;
++                    };
++                };
++
++                vdd_0v75_s3: nldo-reg1 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <750000>;
++                    regulator-max-microvolt = <750000>;
++                    regulator-ramp-delay = <12500>;
++                    regulator-name = "vdd_0v75_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <750000>;
++                    };
++                };
++
++                vdd2l_0v9_ddr_s3: nldo-reg2 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <900000>;
++                    regulator-max-microvolt = <900000>;
++                    regulator-name = "vdd2l_0v9_ddr_s3";
++                    regulator-state-mem {
++                        regulator-on-in-suspend;
++                        regulator-suspend-microvolt = <900000>;
++                    };
++                };
++
++                master_nldo3: nldo-reg3 {
++                    regulator-name = "master_nldo3";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                avdd_0v75_s0: nldo-reg4 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <750000>;
++                    regulator-max-microvolt = <750000>;
++                    regulator-name = "avdd_0v75_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++
++                vdd_0v85_s0: nldo-reg5 {
++                    regulator-always-on;
++                    regulator-boot-on;
++                    regulator-min-microvolt = <850000>;
++                    regulator-max-microvolt = <850000>;
++                    regulator-name = "vdd_0v85_s0";
++                    regulator-state-mem {
++                        regulator-off-in-suspend;
++                    };
++                };
++            };
++        };
++    };
diff --git a/target/linux/rockchip/patches-6.1/193-dt-bindings-mmc-rockchip-dw-mshc-Add-power-domains-p.patch b/target/linux/rockchip/patches-6.1/193-dt-bindings-mmc-rockchip-dw-mshc-Add-power-domains-p.patch
new file mode 100644
index 00000000000..662a2259580
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/193-dt-bindings-mmc-rockchip-dw-mshc-Add-power-domains-p.patch
@@ -0,0 +1,31 @@
+From 753897a422de6bbb7d517fd479d3700408db8262 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 8 Nov 2022 09:43:52 +0530
+Subject: [PATCH 193/383] dt-bindings: mmc: rockchip-dw-mshc: Add power-domains
+ property
+
+Document power-domains property in rockchip dw controller.
+
+RV1126 is using eMMC and SDIO power domains but SDMMC is not.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221108041400.157052-3-jagan@edgeble.ai
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
++++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+@@ -71,6 +71,9 @@ properties:
+       to control the clock phases, "ciu-sample" is required for tuning
+       high speed modes.
+ 
++  power-domains:
++    maxItems: 1
++
+   rockchip,default-sample-phase:
+     $ref: /schemas/types.yaml#/definitions/uint32
+     minimum: 0
diff --git a/target/linux/rockchip/patches-6.1/194-dt-bindings-mmc-rockchip-dw-mshc-Add-RK3588-compatib.patch b/target/linux/rockchip/patches-6.1/194-dt-bindings-mmc-rockchip-dw-mshc-Add-RK3588-compatib.patch
new file mode 100644
index 00000000000..e46df7b31e1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/194-dt-bindings-mmc-rockchip-dw-mshc-Add-RK3588-compatib.patch
@@ -0,0 +1,30 @@
+From 3849da9dacffabef9e40d8fa2b6985d183b5a39b Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Mon, 13 Feb 2023 15:27:39 +0000
+Subject: [PATCH 194/383] dt-bindings: mmc: rockchip-dw-mshc: Add RK3588
+ compatible string
+
+Add RK3588 compatible string for SD interface.
+
+Co-developed-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20230213152740.359055-1-lucas.tanure@collabora.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
++++ b/Documentation/devicetree/bindings/mmc/rockchip-dw-mshc.yaml
+@@ -39,6 +39,7 @@ properties:
+               - rockchip,rk3368-dw-mshc
+               - rockchip,rk3399-dw-mshc
+               - rockchip,rk3568-dw-mshc
++              - rockchip,rk3588-dw-mshc
+               - rockchip,rv1108-dw-mshc
+               - rockchip,rv1126-dw-mshc
+           - const: rockchip,rk3288-dw-mshc
diff --git a/target/linux/rockchip/patches-6.1/195-dt-bindings-mtd-rockchip-add-rockchip-rk3128-nfc.patch b/target/linux/rockchip/patches-6.1/195-dt-bindings-mtd-rockchip-add-rockchip-rk3128-nfc.patch
new file mode 100644
index 00000000000..5382cc7069f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/195-dt-bindings-mtd-rockchip-add-rockchip-rk3128-nfc.patch
@@ -0,0 +1,29 @@
+From b370a3552b9ecaadb263cf20cf856df14d4699fb Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Sat, 10 Sep 2022 00:01:10 +0200
+Subject: [PATCH 195/383] dt-bindings: mtd: rockchip: add rockchip,rk3128-nfc
+
+Add rockchip,rk3128-nfc compatible string.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
+Link: https://lore.kernel.org/linux-mtd/f09665c1-9938-38c1-9a31-f196a3ef9cf0@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/mtd/rockchip,nand-controller.yaml     | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
++++ b/Documentation/devicetree/bindings/mtd/rockchip,nand-controller.yaml
+@@ -19,7 +19,9 @@ properties:
+       - const: rockchip,rk2928-nfc
+       - const: rockchip,rv1108-nfc
+       - items:
+-          - const: rockchip,rk3036-nfc
++          - enum:
++              - rockchip,rk3036-nfc
++              - rockchip,rk3128-nfc
+           - const: rockchip,rk2928-nfc
+       - items:
+           - const: rockchip,rk3308-nfc
diff --git a/target/linux/rockchip/patches-6.1/196-dt-bindings-PCI-Convert-Rockchip-RK3399-PCIe-to-DT-s.patch b/target/linux/rockchip/patches-6.1/196-dt-bindings-PCI-Convert-Rockchip-RK3399-PCIe-to-DT-s.patch
new file mode 100644
index 00000000000..0bc7ab0096b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/196-dt-bindings-PCI-Convert-Rockchip-RK3399-PCIe-to-DT-s.patch
@@ -0,0 +1,519 @@
+From 995238ee2a0734d47536b2d55834ec4eda322fc4 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Mon, 19 Dec 2022 13:12:08 -0600
+Subject: [PATCH 196/383] dt-bindings: PCI: Convert Rockchip RK3399 PCIe to DT
+ schema
+
+Convert the Rockchip RK3399 PCIe Host/Endpoint controller to DT schema
+format. Like most dual mode PCI controllers, we need to split the schema
+into common, host and endpoint schemas.
+
+Link: https://lore.kernel.org/r/20221219191209.1975834-1-robh@kernel.org
+Signed-off-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../pci/rockchip,rk3399-pcie-common.yaml      |  69 +++++++++
+ .../bindings/pci/rockchip,rk3399-pcie-ep.yaml |  68 +++++++++
+ .../bindings/pci/rockchip,rk3399-pcie.yaml    | 132 +++++++++++++++++
+ .../bindings/pci/rockchip-pcie-ep.txt         |  62 --------
+ .../bindings/pci/rockchip-pcie-host.txt       | 135 ------------------
+ MAINTAINERS                                   |   2 +-
+ 6 files changed, 270 insertions(+), 198 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml
+ create mode 100644 Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
+ create mode 100644 Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
+ delete mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
+ delete mode 100644 Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-common.yaml
+@@ -0,0 +1,69 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-common.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip AXI PCIe Bridge Common Properties
++
++maintainers:
++  - Shawn Lin <shawn.lin@rock-chips.com>
++
++properties:
++  reg:
++    maxItems: 2
++
++  clocks:
++    maxItems: 4
++
++  clock-names:
++    items:
++      - const: aclk
++      - const: aclk-perf
++      - const: hclk
++      - const: pm
++
++  num-lanes:
++    maximum: 4
++
++  phys:
++    oneOf:
++      - maxItems: 1
++      - maxItems: 4
++
++  phy-names:
++    oneOf:
++      - const: pcie-phy
++      - items:
++          - const: pcie-phy-0
++          - const: pcie-phy-1
++          - const: pcie-phy-2
++          - const: pcie-phy-3
++
++  resets:
++    maxItems: 7
++
++  reset-names:
++    items:
++      - const: core
++      - const: mgmt
++      - const: mgmt-sticky
++      - const: pipe
++      - const: pm
++      - const: pclk
++      - const: aclk
++
++required:
++  - compatible
++  - reg
++  - reg-names
++  - clocks
++  - clock-names
++  - phys
++  - phy-names
++  - resets
++  - reset-names
++
++additionalProperties: true
++
++...
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie-ep.yaml
+@@ -0,0 +1,68 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie-ep.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip AXI PCIe Endpoint
++
++maintainers:
++  - Shawn Lin <shawn.lin@rock-chips.com>
++
++allOf:
++  - $ref: /schemas/pci/pci-ep.yaml#
++  - $ref: rockchip,rk3399-pcie-common.yaml#
++
++properties:
++  compatible:
++    const: rockchip,rk3399-pcie-ep
++
++  reg: true
++
++  reg-names:
++    items:
++      - const: apb-base
++      - const: mem-base
++
++  rockchip,max-outbound-regions:
++    description: Maximum number of outbound regions
++    $ref: /schemas/types.yaml#/definitions/uint32
++    maximum: 32
++    default: 32
++
++required:
++  - rockchip,max-outbound-regions
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/gpio/gpio.h>
++    #include <dt-bindings/clock/rk3399-cru.h>
++
++    bus {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        pcie-ep@f8000000 {
++            compatible = "rockchip,rk3399-pcie-ep";
++            reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
++            reg-names = "apb-base", "mem-base";
++            clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
++              <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
++            clock-names = "aclk", "aclk-perf",
++                    "hclk", "pm";
++            max-functions = /bits/ 8 <8>;
++            num-lanes = <4>;
++            resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
++              <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
++              <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
++            reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
++                    "pm", "pclk", "aclk";
++            phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
++            phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
++            rockchip,max-outbound-regions = <16>;
++        };
++    };
++...
+--- /dev/null
++++ b/Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie.yaml
+@@ -0,0 +1,132 @@
++# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/pci/rockchip,rk3399-pcie.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip AXI PCIe Root Port Bridge Host
++
++maintainers:
++  - Shawn Lin <shawn.lin@rock-chips.com>
++
++allOf:
++  - $ref: /schemas/pci/pci-bus.yaml#
++  - $ref: rockchip,rk3399-pcie-common.yaml#
++
++properties:
++  compatible:
++    const: rockchip,rk3399-pcie
++
++  reg: true
++
++  reg-names:
++    items:
++      - const: axi-base
++      - const: apb-base
++
++  interrupts:
++    maxItems: 3
++
++  interrupt-names:
++    items:
++      - const: sys
++      - const: legacy
++      - const: client
++
++  aspm-no-l0s:
++    description: This property is needed if using 24MHz OSC for RC's PHY.
++
++  ep-gpios:
++    description: pre-reset GPIO
++
++  vpcie12v-supply:
++    description: The 12v regulator to use for PCIe.
++
++  vpcie3v3-supply:
++    description: The 3.3v regulator to use for PCIe.
++
++  vpcie1v8-supply:
++    description: The 1.8v regulator to use for PCIe.
++
++  vpcie0v9-supply:
++    description: The 0.9v regulator to use for PCIe.
++
++  interrupt-controller:
++    type: object
++    additionalProperties: false
++
++    properties:
++      '#address-cells':
++        const: 0
++
++      '#interrupt-cells':
++        const: 1
++
++      interrupt-controller: true
++
++required:
++  - ranges
++  - "#interrupt-cells"
++  - interrupts
++  - interrupt-controller
++  - interrupt-map
++  - interrupt-map-mask
++  - msi-map
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/gpio/gpio.h>
++    #include <dt-bindings/clock/rk3399-cru.h>
++
++    bus {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        pcie@f8000000 {
++            compatible = "rockchip,rk3399-pcie";
++            device_type = "pci";
++            #address-cells = <3>;
++            #size-cells = <2>;
++            clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
++              <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
++            clock-names = "aclk", "aclk-perf",
++                    "hclk", "pm";
++            interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
++                  <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
++                  <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
++            interrupt-names = "sys", "legacy", "client";
++            ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
++            ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
++                0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
++            num-lanes = <4>;
++            msi-map = <0x0 &its 0x0 0x1000>;
++            reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
++            reg-names = "axi-base", "apb-base";
++            resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
++              <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
++              <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
++            reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
++                    "pm", "pclk", "aclk";
++            /* deprecated legacy PHY model */
++            phys = <&pcie_phy>;
++            phy-names = "pcie-phy";
++            pinctrl-names = "default";
++            pinctrl-0 = <&pcie_clkreq>;
++            #interrupt-cells = <1>;
++            interrupt-map-mask = <0 0 0 7>;
++            interrupt-map = <0 0 0 1 &pcie0_intc 0>,
++                <0 0 0 2 &pcie0_intc 1>,
++                <0 0 0 3 &pcie0_intc 2>,
++                <0 0 0 4 &pcie0_intc 3>;
++
++            pcie0_intc: interrupt-controller {
++                interrupt-controller;
++                #address-cells = <0>;
++                #interrupt-cells = <1>;
++            };
++        };
++    };
++...
+--- a/Documentation/devicetree/bindings/pci/rockchip-pcie-ep.txt
++++ /dev/null
+@@ -1,62 +0,0 @@
+-* Rockchip AXI PCIe Endpoint Controller DT description
+-
+-Required properties:
+-- compatible: Should contain "rockchip,rk3399-pcie-ep"
+-- reg: Two register ranges as listed in the reg-names property
+-- reg-names: Must include the following names
+-	- "apb-base"
+-	- "mem-base"
+-- clocks: Must contain an entry for each entry in clock-names.
+-		See ../clocks/clock-bindings.txt for details.
+-- clock-names: Must include the following entries:
+-	- "aclk"
+-	- "aclk-perf"
+-	- "hclk"
+-	- "pm"
+-- resets: Must contain seven entries for each entry in reset-names.
+-	   See ../reset/reset.txt for details.
+-- reset-names: Must include the following names
+-	- "core"
+-	- "mgmt"
+-	- "mgmt-sticky"
+-	- "pipe"
+-	- "pm"
+-	- "aclk"
+-	- "pclk"
+-- pinctrl-names : The pin control state names
+-- pinctrl-0: The "default" pinctrl state
+-- phys: Must contain an phandle to a PHY for each entry in phy-names.
+-- phy-names: Must include 4 entries for all 4 lanes even if some of
+-  them won't be used for your cases. Entries are of the form "pcie-phy-N":
+-  where N ranges from 0 to 3.
+-  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+-  for changing the #phy-cells of phy node to support it)
+-- rockchip,max-outbound-regions: Maximum number of outbound regions
+-
+-Optional Property:
+-- num-lanes: number of lanes to use
+-- max-functions: Maximum number of functions that can be configured (default 1).
+-
+-pcie0-ep: pcie@f8000000 {
+-	compatible = "rockchip,rk3399-pcie-ep";
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-	rockchip,max-outbound-regions = <16>;
+-	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+-		 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+-	clock-names = "aclk", "aclk-perf",
+-		      "hclk", "pm";
+-	max-functions = /bits/ 8 <8>;
+-	num-lanes = <4>;
+-	reg = <0x0 0xfd000000 0x0 0x1000000>, <0x0 0x80000000 0x0 0x20000>;
+-	reg-names = "apb-base", "mem-base";
+-	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+-		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
+-		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
+-	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+-		      "pm", "pclk", "aclk";
+-	phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+-	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pcie_clkreq>;
+-};
+--- a/Documentation/devicetree/bindings/pci/rockchip-pcie-host.txt
++++ /dev/null
+@@ -1,135 +0,0 @@
+-* Rockchip AXI PCIe Root Port Bridge DT description
+-
+-Required properties:
+-- #address-cells: Address representation for root ports, set to <3>
+-- #size-cells: Size representation for root ports, set to <2>
+-- #interrupt-cells: specifies the number of cells needed to encode an
+-		interrupt source. The value must be 1.
+-- compatible: Should contain "rockchip,rk3399-pcie"
+-- reg: Two register ranges as listed in the reg-names property
+-- reg-names: Must include the following names
+-	- "axi-base"
+-	- "apb-base"
+-- clocks: Must contain an entry for each entry in clock-names.
+-		See ../clocks/clock-bindings.txt for details.
+-- clock-names: Must include the following entries:
+-	- "aclk"
+-	- "aclk-perf"
+-	- "hclk"
+-	- "pm"
+-- msi-map: Maps a Requester ID to an MSI controller and associated
+-	msi-specifier data. See ./pci-msi.txt
+-- interrupts: Three interrupt entries must be specified.
+-- interrupt-names: Must include the following names
+-	- "sys"
+-	- "legacy"
+-	- "client"
+-- resets: Must contain seven entries for each entry in reset-names.
+-	   See ../reset/reset.txt for details.
+-- reset-names: Must include the following names
+-	- "core"
+-	- "mgmt"
+-	- "mgmt-sticky"
+-	- "pipe"
+-	- "pm"
+-	- "aclk"
+-	- "pclk"
+-- pinctrl-names : The pin control state names
+-- pinctrl-0: The "default" pinctrl state
+-- #interrupt-cells: specifies the number of cells needed to encode an
+-	interrupt source. The value must be 1.
+-- interrupt-map-mask and interrupt-map: standard PCI properties
+-
+-Required properties for legacy PHY model (deprecated):
+-- phys: From PHY bindings: Phandle for the Generic PHY for PCIe.
+-- phy-names:  MUST be "pcie-phy".
+-
+-Required properties for per-lane PHY model (preferred):
+-- phys: Must contain an phandle to a PHY for each entry in phy-names.
+-- phy-names: Must include 4 entries for all 4 lanes even if some of
+-  them won't be used for your cases. Entries are of the form "pcie-phy-N":
+-  where N ranges from 0 to 3.
+-  (see example below and you MUST also refer to ../phy/rockchip-pcie-phy.txt
+-  for changing the #phy-cells of phy node to support it)
+-
+-Optional Property:
+-- aspm-no-l0s: RC won't support ASPM L0s. This property is needed if
+-	using 24MHz OSC for RC's PHY.
+-- ep-gpios: contain the entry for pre-reset GPIO
+-- num-lanes: number of lanes to use
+-- vpcie12v-supply: The phandle to the 12v regulator to use for PCIe.
+-- vpcie3v3-supply: The phandle to the 3.3v regulator to use for PCIe.
+-- vpcie1v8-supply: The phandle to the 1.8v regulator to use for PCIe.
+-- vpcie0v9-supply: The phandle to the 0.9v regulator to use for PCIe.
+-
+-*Interrupt controller child node*
+-The core controller provides a single interrupt for legacy INTx. The PCIe node
+-should contain an interrupt controller node as a target for the PCI
+-'interrupt-map' property. This node represents the domain at which the four
+-INTx interrupts are decoded and routed.
+-
+-
+-Required properties for Interrupt controller child node:
+-- interrupt-controller: identifies the node as an interrupt controller
+-- #address-cells: specifies the number of cells needed to encode an
+-	address. The value must be 0.
+-- #interrupt-cells: specifies the number of cells needed to encode an
+-	interrupt source. The value must be 1.
+-
+-Example:
+-
+-pcie0: pcie@f8000000 {
+-	compatible = "rockchip,rk3399-pcie";
+-	#address-cells = <3>;
+-	#size-cells = <2>;
+-	clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
+-		 <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
+-	clock-names = "aclk", "aclk-perf",
+-		      "hclk", "pm";
+-	bus-range = <0x0 0x1>;
+-	interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
+-		     <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
+-		     <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
+-	interrupt-names = "sys", "legacy", "client";
+-	assigned-clocks = <&cru SCLK_PCIEPHY_REF>;
+-	assigned-clock-parents = <&cru SCLK_PCIEPHY_REF100M>;
+-	assigned-clock-rates = <100000000>;
+-	ep-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>;
+-	ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x600000
+-		  0x81000000 0x0 0xfa600000 0x0 0xfa600000 0x0 0x100000>;
+-	num-lanes = <4>;
+-	msi-map = <0x0 &its 0x0 0x1000>;
+-	reg = <0x0 0xf8000000 0x0 0x2000000>, <0x0 0xfd000000 0x0 0x1000000>;
+-	reg-names = "axi-base", "apb-base";
+-	resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
+-		 <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE> ,
+-		 <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>, <&cru SRST_A_PCIE>;
+-	reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
+-		      "pm", "pclk", "aclk";
+-	/* deprecated legacy PHY model */
+-	phys = <&pcie_phy>;
+-	phy-names = "pcie-phy";
+-	pinctrl-names = "default";
+-	pinctrl-0 = <&pcie_clkreq>;
+-	#interrupt-cells = <1>;
+-	interrupt-map-mask = <0 0 0 7>;
+-	interrupt-map = <0 0 0 1 &pcie0_intc 0>,
+-			<0 0 0 2 &pcie0_intc 1>,
+-			<0 0 0 3 &pcie0_intc 2>,
+-			<0 0 0 4 &pcie0_intc 3>;
+-	pcie0_intc: interrupt-controller {
+-		interrupt-controller;
+-		#address-cells = <0>;
+-		#interrupt-cells = <1>;
+-	};
+-};
+-
+-pcie0: pcie@f8000000 {
+-	...
+-
+-	/* preferred per-lane PHY model */
+-	phys = <&pcie_phy 0>, <&pcie_phy 1>, <&pcie_phy 2>, <&pcie_phy 3>;
+-	phy-names = "pcie-phy-0", "pcie-phy-1", "pcie-phy-2", "pcie-phy-3";
+-
+-	...
+-};
+--- a/MAINTAINERS
++++ b/MAINTAINERS
+@@ -16092,7 +16092,7 @@ M:	Shawn Lin <shawn.lin@rock-chips.com>
+ L:	linux-pci@vger.kernel.org
+ L:	linux-rockchip@lists.infradead.org
+ S:	Maintained
+-F:	Documentation/devicetree/bindings/pci/rockchip-pcie*
++F:	Documentation/devicetree/bindings/pci/rockchip,rk3399-pcie*
+ F:	drivers/pci/controller/pcie-rockchip*
+ 
+ PCIE DRIVER FOR SOCIONEXT UNIPHIER
diff --git a/target/linux/rockchip/patches-6.1/197-dt-bindings-PCI-dwc-Apply-common-schema-to-Rockchip-.patch b/target/linux/rockchip/patches-6.1/197-dt-bindings-PCI-dwc-Apply-common-schema-to-Rockchip-.patch
new file mode 100644
index 00000000000..4d993c18d66
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/197-dt-bindings-PCI-dwc-Apply-common-schema-to-Rockchip-.patch
@@ -0,0 +1,36 @@
+From a5e0c66000dc56eecba2ffd45b8229bb687ed481 Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:54 +0300
+Subject: [PATCH 197/383] dt-bindings: PCI: dwc: Apply common schema to
+ Rockchip DW PCIe nodes
+
+As the DT-bindings description states the Rockchip PCIe controller is
+based on the DW PCIe RP IP-core thus its DT-nodes are supposed to be
+compatible with the common DW PCIe controller schema. Let's make sure they
+are evaluated against it by referring to the snps,dw-pcie.yaml schema in
+the allOf sub-schemas composition.
+
+Link: https://lore.kernel.org/r/20221113191301.5526-14-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -14,10 +14,10 @@ maintainers:
+ description: |+
+   RK3568 SoC PCIe host controller is based on the Synopsys DesignWare
+   PCIe IP and thus inherits all the common properties defined in
+-  designware-pcie.txt.
++  snps,dw-pcie.yaml.
+ 
+ allOf:
+-  - $ref: /schemas/pci/pci-bus.yaml#
++  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+ 
+ properties:
+   compatible:
diff --git a/target/linux/rockchip/patches-6.1/198-dt-bindings-PCI-dwc-Add-rk3588-compatible.patch b/target/linux/rockchip/patches-6.1/198-dt-bindings-PCI-dwc-Add-rk3588-compatible.patch
new file mode 100644
index 00000000000..841dd013974
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/198-dt-bindings-PCI-dwc-Add-rk3588-compatible.patch
@@ -0,0 +1,32 @@
+From ed34a35b864336153effbfc68d7be8f370adee2d Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 14 Mar 2023 13:55:53 +0000
+Subject: [PATCH 198/383] dt-bindings: PCI: dwc: Add rk3588 compatible
+
+PCIe for RK3588 is the same as RK3568.
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230314135555.44162-2-lucas.tanure@collabora.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 6 +++++-
+ 1 file changed, 5 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -21,8 +21,12 @@ allOf:
+ 
+ properties:
+   compatible:
+-    items:
++    oneOf:
+       - const: rockchip,rk3568-pcie
++      - items:
++          - enum:
++              - rockchip,rk3588-pcie
++          - const: rockchip,rk3568-pcie
+ 
+   reg:
+     items:
diff --git a/target/linux/rockchip/patches-6.1/199-dt-bindings-phy-rockchip-Add-rk3588-compatible.patch b/target/linux/rockchip/patches-6.1/199-dt-bindings-phy-rockchip-Add-rk3588-compatible.patch
new file mode 100644
index 00000000000..c073f2357bf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/199-dt-bindings-phy-rockchip-Add-rk3588-compatible.patch
@@ -0,0 +1,27 @@
+From 5db4e6060c4facd74448a7055459469c0cc210e3 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 14 Mar 2023 13:55:54 +0000
+Subject: [PATCH 199/383] dt-bindings: phy: rockchip: Add rk3588 compatible
+
+RK3568 Naneng Combo Phy driver can support RK3588 with the additional
+clocks and initial configuration, so add the compatible line.
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230314135555.44162-3-lucas.tanure@collabora.com
+Signed-off-by: Vinod Koul <vkoul@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml     | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
++++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+@@ -13,6 +13,7 @@ properties:
+   compatible:
+     enum:
+       - rockchip,rk3568-naneng-combphy
++      - rockchip,rk3588-naneng-combphy
+ 
+   reg:
+     maxItems: 1
diff --git a/target/linux/rockchip/patches-6.1/200-dt-bindings-pinctrl-rockchip-further-increase-max-am.patch b/target/linux/rockchip/patches-6.1/200-dt-bindings-pinctrl-rockchip-further-increase-max-am.patch
new file mode 100644
index 00000000000..f02b55a6635
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/200-dt-bindings-pinctrl-rockchip-further-increase-max-am.patch
@@ -0,0 +1,31 @@
+From 0b785974bb9f1cdf5e80059253d138756e64afee Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 21 Oct 2022 19:20:12 +0200
+Subject: [PATCH 200/383] dt-bindings: pinctrl: rockchip: further increase max
+ amount of device functions
+
+Apparently RK3588 pinctrl has 13 different device functions, but dt-validate
+only checks for pin configuration being referenced so I did not notice.
+
+Fixes: ed1f77b78322 ("dt-bindings: pinctrl: rockchip: increase max amount of device functions")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20221021172012.87954-1-sebastian.reichel@collabora.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
++++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+@@ -132,7 +132,7 @@ additionalProperties:
+               description:
+                 Pin bank index.
+             - minimum: 0
+-              maximum: 10
++              maximum: 13
+               description:
+                 Mux 0 means GPIO and mux 1 to N means
+                 the specific device function.
diff --git a/target/linux/rockchip/patches-6.1/201-dt-bindings-pinctrl-rockchip-pinctrl-mark-gpio-sub-n.patch b/target/linux/rockchip/patches-6.1/201-dt-bindings-pinctrl-rockchip-pinctrl-mark-gpio-sub-n.patch
new file mode 100644
index 00000000000..b6a83e17c81
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/201-dt-bindings-pinctrl-rockchip-pinctrl-mark-gpio-sub-n.patch
@@ -0,0 +1,40 @@
+From c0ec798a4d616eca4fb99f9c69315b98e6526b9f Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Sat, 21 Jan 2023 12:08:20 +0100
+Subject: [PATCH 201/383] dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub
+ nodes of pinctrl as deprecated
+
+Mark gpio sub nodes of pinctrl as deprecated.
+Gpio nodes are now placed in the root of the device tree.
+The relation to pinctrl is now described with the
+"gpio-ranges" property.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Link: https://lore.kernel.org/r/137b56f0-8e86-f705-4ba7-d5dfe3c0b477@gmail.com
+Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/pinctrl/rockchip,pinctrl.yaml         | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
++++ b/Documentation/devicetree/bindings/pinctrl/rockchip,pinctrl.yaml
+@@ -76,15 +76,13 @@ allOf:
+ required:
+   - compatible
+   - rockchip,grf
+-  - "#address-cells"
+-  - "#size-cells"
+-  - ranges
+ 
+ patternProperties:
+   "gpio@[0-9a-f]+$":
+     type: object
+ 
+     $ref: "/schemas/gpio/rockchip,gpio-bank.yaml#"
++    deprecated: true
+ 
+     unevaluatedProperties: false
+ 
diff --git a/target/linux/rockchip/patches-6.1/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch b/target/linux/rockchip/patches-6.1/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch
deleted file mode 100644
index 013e1498119..00000000000
--- a/target/linux/rockchip/patches-6.1/201-rockchip-rk3328-add-i2c0-controller-for-nanopi-r2s.patch
+++ /dev/null
@@ -1,22 +0,0 @@
-From 3b7eb946b1d640d684a921e53e1e50985ab7eb89 Mon Sep 17 00:00:00 2001
-From: QiuSimons <45143996+QiuSimons@users.noreply.github.com>
-Date: Tue, 4 Aug 2020 20:17:53 +0800
-Subject: [PATCH] rockchip: rk3328: add i2c0 controller for nanopi r2s
-
----
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 4 ++++
- 1 files changed, 4 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -173,6 +173,10 @@
- 	};
- };
- 
-+&i2c0 {
-+	status = "okay";
-+};
-+
- &i2c1 {
- 	status = "okay";
- 
diff --git a/target/linux/rockchip/patches-6.1/202-regulator-dt-bindings-Convert-Fairchild-FAN53555-to-.patch b/target/linux/rockchip/patches-6.1/202-regulator-dt-bindings-Convert-Fairchild-FAN53555-to-.patch
new file mode 100644
index 00000000000..81a79e9e693
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/202-regulator-dt-bindings-Convert-Fairchild-FAN53555-to-.patch
@@ -0,0 +1,118 @@
+From f50565b7b1d4866727087629bf701b6783303709 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Sun, 8 Jan 2023 18:46:56 -0600
+Subject: [PATCH 202/383] regulator: dt-bindings: Convert Fairchild FAN53555 to
+ DT schema
+
+Convert the Fairchild FAN53555 and compatible variants binding to DT
+schema format.
+
+Add the undocumented 'vsel-gpios' property used to control the VSEL pin.
+
+The example was missing 'reg', so add it.
+
+Signed-off-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230109004656.451231-1-robh@kernel.org
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/regulator/fan53555.txt           | 24 -------
+ .../bindings/regulator/fcs,fan53555.yaml      | 64 +++++++++++++++++++
+ 2 files changed, 64 insertions(+), 24 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/regulator/fan53555.txt
+ create mode 100644 Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml
+
+--- a/Documentation/devicetree/bindings/regulator/fan53555.txt
++++ /dev/null
+@@ -1,24 +0,0 @@
+-Binding for Fairchild FAN53555 regulators
+-
+-Required properties:
+-  - compatible: one of "fcs,fan53555", "fcs,fan53526", "silergy,syr827",
+-		"silergy,syr828" or "tcs,tcs4525".
+-  - reg: I2C address
+-
+-Optional properties:
+-  - fcs,suspend-voltage-selector: declare which of the two available
+-		voltage selector registers should be used for the suspend
+-		voltage. The other one is used for the runtime voltage setting
+-		Possible values are either <0> or <1>
+-  - vin-supply: regulator supplying the vin pin
+-
+-Example:
+-
+-	regulator@40 {
+-		compatible = "fcs,fan53555";
+-		regulator-name = "fan53555";
+-		regulator-min-microvolt = <1000000>;
+-		regulator-max-microvolt = <1800000>;
+-		vin-supply = <&parent_reg>;
+-		fcs,suspend-voltage-selector = <1>;
+-	};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml
+@@ -0,0 +1,64 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/regulator/fcs,fan53555.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Fairchild FAN53555 regulators
++
++maintainers:
++  - Heiko Stuebner <heiko@sntech.de>
++
++allOf:
++  - $ref: regulator.yaml#
++
++properties:
++  compatible:
++    enum:
++      - fcs,fan53555
++      - fcs,fan53526
++      - silergy,syr827
++      - silergy,syr828
++      - tcs,tcs4525
++
++  reg:
++    maxItems: 1
++
++  fcs,suspend-voltage-selector:
++    description: Declares which of the two available voltage selector
++      registers should be used for the suspend voltage. The other one is used
++      for the runtime voltage setting.
++    $ref: /schemas/types.yaml#/definitions/uint32
++    enum: [ 0, 1 ]
++
++  vin-supply:
++    description: Supply for the vin pin
++
++  vsel-gpios:
++    description: Voltage Select. When this pin is LOW, VOUT is set by the
++      VSEL0 register. When this pin is HIGH, VOUT is set by the VSEL1 register.
++    maxItems: 1
++
++required:
++  - compatible
++  - reg
++
++unevaluatedProperties: false
++
++examples:
++  - |
++    i2c {
++        #address-cells = <1>;
++        #size-cells = <0>;
++
++        regulator@40 {
++            compatible = "fcs,fan53555";
++            reg = <0x40>;
++            regulator-name = "fan53555";
++            regulator-min-microvolt = <1000000>;
++            regulator-max-microvolt = <1800000>;
++            vin-supply = <&parent_reg>;
++            fcs,suspend-voltage-selector = <1>;
++        };
++    };
++...
diff --git a/target/linux/rockchip/patches-6.1/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch b/target/linux/rockchip/patches-6.1/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch
deleted file mode 100644
index e1f441ba3de..00000000000
--- a/target/linux/rockchip/patches-6.1/202-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus.patch
+++ /dev/null
@@ -1,52 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -11,6 +11,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-od
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus.dts
-@@ -0,0 +1,39 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus";
-+	compatible = "xunlong,orangepi-r1-plus", "rockchip,rk3328";
-+};
-+
-+&lan_led {
-+	label = "orangepi-r1-plus:green:lan";
-+};
-+
-+&spi0 {
-+	max-freq = <48000000>;
-+	status = "okay";
-+
-+	flash@0 {
-+		compatible = "jedec,spi-nor";
-+		reg = <0>;
-+		spi-max-frequency = <10000000>;
-+	};
-+};
-+
-+&sys_led {
-+	gpios = <&gpio3 RK_PC5 GPIO_ACTIVE_HIGH>;
-+	label = "orangepi-r1-plus:red:sys";
-+};
-+
-+&sys_led_pin {
-+	rockchip,pins = <3 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
-+};
-+
-+&uart1 {
-+	status = "okay";
-+};
-+
-+&wan_led {
-+	label = "orangepi-r1-plus:green:wan";
-+};
diff --git a/target/linux/rockchip/patches-6.1/203-regulator-dt-bindings-fcs-fan53555-Add-support-for-R.patch b/target/linux/rockchip/patches-6.1/203-regulator-dt-bindings-fcs-fan53555-Add-support-for-R.patch
new file mode 100644
index 00000000000..7f55af26a59
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/203-regulator-dt-bindings-fcs-fan53555-Add-support-for-R.patch
@@ -0,0 +1,51 @@
+From 44cda43753bf2797bddedcf1ba04c522e2cbea3d Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 6 Apr 2023 22:41:51 +0300
+Subject: [PATCH 203/383] regulator: dt-bindings: fcs,fan53555: Add support for
+ RK860X
+
+Add compatibles to support Rockchip RK860X regulators.
+
+RK8600/RK8601 are pretty similar to the FAN53555 regulators, while
+RK8602/RK8603 are a bit different, having a wider voltage selection
+range.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230406194158.963352-2-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/regulator/fcs,fan53555.yaml      | 21 +++++++++++++------
+ 1 file changed, 15 insertions(+), 6 deletions(-)
+
+--- a/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml
++++ b/Documentation/devicetree/bindings/regulator/fcs,fan53555.yaml
+@@ -14,12 +14,21 @@ allOf:
+ 
+ properties:
+   compatible:
+-    enum:
+-      - fcs,fan53555
+-      - fcs,fan53526
+-      - silergy,syr827
+-      - silergy,syr828
+-      - tcs,tcs4525
++    oneOf:
++      - enum:
++          - fcs,fan53555
++          - fcs,fan53526
++          - rockchip,rk8600
++          - rockchip,rk8602
++          - silergy,syr827
++          - silergy,syr828
++          - tcs,tcs4525
++      - items:
++          - const: rockchip,rk8601
++          - const: rockchip,rk8600
++      - items:
++          - const: rockchip,rk8603
++          - const: rockchip,rk8602
+ 
+   reg:
+     maxItems: 1
diff --git a/target/linux/rockchip/patches-6.1/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch b/target/linux/rockchip/patches-6.1/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch
deleted file mode 100644
index f6547ceef15..00000000000
--- a/target/linux/rockchip/patches-6.1/203-rockchip-rk3328-Add-support-for-OrangePi-R1-Plus-LTS.patch
+++ /dev/null
@@ -1,79 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-orangepi-r1-plus-lts.dts
-@@ -0,0 +1,66 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2016 Xunlong Software. Co., Ltd.
-+ * (http://www.orangepi.org)
-+ *
-+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
-+ */
-+
-+#include "rk3328-orangepi-r1-plus.dts"
-+
-+/ {
-+	model = "Xunlong Orange Pi R1 Plus LTS";
-+	compatible = "xunlong,orangepi-r1-plus-lts", "rockchip,rk3328";
-+};
-+
-+&dmc_opp_table {
-+	opp-798000000 {
-+		status = "disabled";
-+	};
-+	opp-840000000 {
-+		status = "disabled";
-+	};
-+	opp-924000000 {
-+		status = "disabled";
-+	};
-+	opp-1056000000 {
-+		status = "disabled";
-+	};
-+};
-+
-+&gmac2io {
-+	phy-handle = <&yt8531c>;
-+	tx_delay = <0x19>;
-+	rx_delay = <0x05>;
-+
-+	mdio {
-+		/delete-node/ ethernet-phy@1;
-+
-+		yt8531c: ethernet-phy@0 {
-+			compatible = "ethernet-phy-id4f51.e91b",
-+				     "ethernet-phy-ieee802.3-c22";
-+			reg = <0>;
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <15000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
-+
-+&lan_led {
-+	label = "orangepi-r1-plus-lts:green:lan";
-+};
-+
-+&rtl8153 {
-+	realtek,led-data = <0x78>;
-+};
-+
-+&sys_led {
-+	label = "orangepi-r1-plus-lts:red:sys";
-+};
-+
-+&wan_led {
-+	label = "orangepi-r1-plus-lts:green:wan";
-+};
diff --git a/target/linux/rockchip/patches-6.1/204-dt-bindings-soc-rockchip-add-initial-rk3588-syscon-c.patch b/target/linux/rockchip/patches-6.1/204-dt-bindings-soc-rockchip-add-initial-rk3588-syscon-c.patch
new file mode 100644
index 00000000000..fa98b8dc360
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/204-dt-bindings-soc-rockchip-add-initial-rk3588-syscon-c.patch
@@ -0,0 +1,32 @@
+From b02173ba8e6f9f9843c4cad420b258a31db3d988 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 9 Jan 2023 16:57:55 +0100
+Subject: [PATCH 204/383] dt-bindings: soc: rockchip: add initial rk3588 syscon
+ compatibles
+
+Add IOC and PHP GRF syscon compatibles for RK3588.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Reviewed-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230109155801.51642-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -20,6 +20,11 @@ properties:
+               - rockchip,rk3568-pipe-grf
+               - rockchip,rk3568-pipe-phy-grf
+               - rockchip,rk3568-usb2phy-grf
++              - rockchip,rk3588-bigcore0-grf
++              - rockchip,rk3588-bigcore1-grf
++              - rockchip,rk3588-ioc
++              - rockchip,rk3588-php-grf
++              - rockchip,rk3588-sys-grf
+               - rockchip,rk3588-pcie3-phy-grf
+               - rockchip,rk3588-pcie3-pipe-grf
+               - rockchip,rv1108-usbgrf
diff --git a/target/linux/rockchip/patches-6.1/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch b/target/linux/rockchip/patches-6.1/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
deleted file mode 100644
index 02314136871..00000000000
--- a/target/linux/rockchip/patches-6.1/204-rockchip-rk3328-Add-support-for-FriendlyARM-NanoPi-R.patch
+++ /dev/null
@@ -1,68 +0,0 @@
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -10,6 +10,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3318-a9
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3326-odroid-go2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
---- /dev/null
-+++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2c.dts
-@@ -0,0 +1,55 @@
-+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-+/*
-+ * Copyright (c) 2021 FriendlyElec Computer Tech. Co., Ltd.
-+ * (http://www.friendlyarm.com)
-+ *
-+ * Copyright (c) 2021 Tianling Shen <cnsztl@immortalwrt.org>
-+ */
-+
-+/dts-v1/;
-+
-+#include "rk3328-nanopi-r2s.dts"
-+
-+/ {
-+	model = "FriendlyElec NanoPi R2C";
-+	compatible = "friendlyarm,nanopi-r2c", "rockchip,rk3328";
-+};
-+
-+&gmac2io {
-+	phy-handle = <&yt8521s>;
-+	tx_delay = <0x22>;
-+	rx_delay = <0x12>;
-+
-+	mdio {
-+		/delete-node/ ethernet-phy@1;
-+
-+		yt8521s: ethernet-phy@3 {
-+			compatible = "ethernet-phy-id0000.011a",
-+				     "ethernet-phy-ieee802.3-c22";
-+			reg = <3>;
-+			interrupt-parent = <&gpio2>;
-+			interrupts = <RK_PC4 IRQ_TYPE_EDGE_FALLING>;
-+			pinctrl-0 = <&eth_phy_reset_pin>;
-+			pinctrl-names = "default";
-+			reset-assert-us = <10000>;
-+			reset-deassert-us = <50000>;
-+			reset-gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>;
-+		};
-+	};
-+};
-+
-+&lan_led {
-+	label = "nanopi-r2c:green:lan";
-+};
-+
-+&rtl8153 {
-+	realtek,led-data = <0x78>;
-+};
-+
-+&sys_led {
-+	label = "nanopi-r2c:red:sys";
-+};
-+
-+&wan_led {
-+	label = "nanopi-r2c:green:wan";
-+};
diff --git a/target/linux/rockchip/patches-6.1/205-dt-bindings-soc-rockchip-grf-add-rockchip-rk3288-dp-.patch b/target/linux/rockchip/patches-6.1/205-dt-bindings-soc-rockchip-grf-add-rockchip-rk3288-dp-.patch
new file mode 100644
index 00000000000..21887aa5aa5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/205-dt-bindings-soc-rockchip-grf-add-rockchip-rk3288-dp-.patch
@@ -0,0 +1,32 @@
+From 075e506e9e274fb0ef7b7c5c6672ee8f904c0195 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 29 Dec 2022 10:45:16 +0100
+Subject: [PATCH 205/383] dt-bindings: soc: rockchip: grf: add
+ rockchip,rk3288-dp-phy.yaml
+
+Add new converted rockchip,rk3288-dp-phy.yaml to grf.yaml file.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+[dropped the unrelated blank line removals that didn't apply]
+Link: https://lore.kernel.org/r/5759c6e1-9c89-4cb2-dd57-83a8db09f547@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 5 +++--
+ 1 file changed, 3 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -97,8 +97,9 @@ allOf:
+     then:
+       properties:
+         edp-phy:
+-          description:
+-            Documentation/devicetree/bindings/phy/rockchip-dp-phy.txt
++          type: object
++          $ref: /schemas/phy/rockchip,rk3288-dp-phy.yaml#
++          unevaluatedProperties: false
+ 
+   - if:
+       properties:
diff --git a/target/linux/rockchip/patches-6.1/206-dt-bindings-phy-rename-phy-rockchip-inno-usb2.yaml.patch b/target/linux/rockchip/patches-6.1/206-dt-bindings-phy-rename-phy-rockchip-inno-usb2.yaml.patch
new file mode 100644
index 00000000000..6bf99b04976
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/206-dt-bindings-phy-rename-phy-rockchip-inno-usb2.yaml.patch
@@ -0,0 +1,413 @@
+From 268353bccdc7bbcdc2184dcad5f4d5d42852b121 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 29 Dec 2022 12:39:17 +0100
+Subject: [PATCH 206/383] dt-bindings: phy: rename phy-rockchip-inno-usb2.yaml
+
+Rename phy-rockchip-inno-usb2.yaml to a more common format of
+rockchip,inno-usb2phy.yaml
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Acked-By: Vinod Koul <vkoul@kernel.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/99794484-d67e-ee1f-4e76-200de20a879c@gmail.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../{phy-rockchip-inno-usb2.yaml => rockchip,inno-usb2phy.yaml} | 2 +-
+ Documentation/devicetree/bindings/soc/rockchip/grf.yaml         | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+ rename Documentation/devicetree/bindings/phy/{phy-rockchip-inno-usb2.yaml => rockchip,inno-usb2phy.yaml} (98%)
+
+--- a/Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
++++ /dev/null
+@@ -1,188 +0,0 @@
+-# SPDX-License-Identifier: GPL-2.0
+-%YAML 1.2
+----
+-$id: http://devicetree.org/schemas/phy/phy-rockchip-inno-usb2.yaml#
+-$schema: http://devicetree.org/meta-schemas/core.yaml#
+-
+-title: Rockchip USB2.0 phy with inno IP block
+-
+-maintainers:
+-  - Heiko Stuebner <heiko@sntech.de>
+-
+-properties:
+-  compatible:
+-    enum:
+-      - rockchip,px30-usb2phy
+-      - rockchip,rk3128-usb2phy
+-      - rockchip,rk3228-usb2phy
+-      - rockchip,rk3308-usb2phy
+-      - rockchip,rk3328-usb2phy
+-      - rockchip,rk3366-usb2phy
+-      - rockchip,rk3399-usb2phy
+-      - rockchip,rk3568-usb2phy
+-      - rockchip,rv1108-usb2phy
+-
+-  reg:
+-    maxItems: 1
+-
+-  clock-output-names:
+-    description:
+-      The usb 480m output clock name.
+-
+-  "#clock-cells":
+-    const: 0
+-
+-  clocks:
+-    maxItems: 1
+-
+-  clock-names:
+-    const: phyclk
+-
+-  assigned-clocks:
+-    description:
+-      Phandle of the usb 480m clock.
+-
+-  assigned-clock-parents:
+-    description:
+-      Parent of the usb 480m clock.
+-      Select between usb-phy output 480m and xin24m.
+-      Refer to clk/clock-bindings.txt for generic clock consumer properties.
+-
+-  extcon:
+-    description:
+-      Phandle to the extcon device providing the cable state for the otg phy.
+-
+-  interrupts:
+-    description: Muxed interrupt for both ports
+-    maxItems: 1
+-
+-  rockchip,usbgrf:
+-    $ref: /schemas/types.yaml#/definitions/phandle
+-    description:
+-      Phandle to the syscon managing the 'usb general register files'.
+-      When set the driver will request its phandle as one companion-grf
+-      for some special SoCs (e.g rv1108).
+-
+-  host-port:
+-    type: object
+-    additionalProperties: false
+-
+-    properties:
+-      "#phy-cells":
+-        const: 0
+-
+-      interrupts:
+-        description: host linestate interrupt
+-        maxItems: 1
+-
+-      interrupt-names:
+-        const: linestate
+-
+-      phy-supply:
+-        description:
+-          Phandle to a regulator that provides power to VBUS.
+-          See ./phy-bindings.txt for details.
+-
+-    required:
+-      - "#phy-cells"
+-
+-  otg-port:
+-    type: object
+-    additionalProperties: false
+-
+-    properties:
+-      "#phy-cells":
+-        const: 0
+-
+-      interrupts:
+-        minItems: 1
+-        maxItems: 3
+-
+-      interrupt-names:
+-        oneOf:
+-          - const: linestate
+-          - const: otg-mux
+-          - items:
+-              - const: otg-bvalid
+-              - const: otg-id
+-              - const: linestate
+-
+-      phy-supply:
+-        description:
+-          Phandle to a regulator that provides power to VBUS.
+-          See ./phy-bindings.txt for details.
+-
+-    required:
+-      - "#phy-cells"
+-
+-required:
+-  - compatible
+-  - reg
+-  - clock-output-names
+-  - "#clock-cells"
+-  - host-port
+-  - otg-port
+-
+-allOf:
+-  - if:
+-      properties:
+-        compatible:
+-          contains:
+-            const: rockchip,rk3568-usb2phy
+-
+-    then:
+-      properties:
+-        host-port:
+-          properties:
+-            interrupts: false
+-
+-        otg-port:
+-          properties:
+-            interrupts: false
+-
+-      required:
+-        - interrupts
+-
+-    else:
+-      properties:
+-        interrupts: false
+-
+-        host-port:
+-          required:
+-            - interrupts
+-            - interrupt-names
+-
+-        otg-port:
+-          required:
+-            - interrupts
+-            - interrupt-names
+-
+-additionalProperties: false
+-
+-examples:
+-  - |
+-    #include <dt-bindings/clock/rk3399-cru.h>
+-    #include <dt-bindings/interrupt-controller/arm-gic.h>
+-    #include <dt-bindings/interrupt-controller/irq.h>
+-    u2phy0: usb2phy@e450 {
+-      compatible = "rockchip,rk3399-usb2phy";
+-      reg = <0xe450 0x10>;
+-      clocks = <&cru SCLK_USB2PHY0_REF>;
+-      clock-names = "phyclk";
+-      clock-output-names = "clk_usbphy0_480m";
+-      #clock-cells = <0>;
+-
+-      u2phy0_host: host-port {
+-        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
+-        interrupt-names = "linestate";
+-        #phy-cells = <0>;
+-      };
+-
+-      u2phy0_otg: otg-port {
+-        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
+-                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
+-                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
+-        interrupt-names = "otg-bvalid", "otg-id", "linestate";
+-        #phy-cells = <0>;
+-      };
+-    };
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+@@ -0,0 +1,188 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/rockchip,inno-usb2phy.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip USB2.0 phy with inno IP block
++
++maintainers:
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,px30-usb2phy
++      - rockchip,rk3128-usb2phy
++      - rockchip,rk3228-usb2phy
++      - rockchip,rk3308-usb2phy
++      - rockchip,rk3328-usb2phy
++      - rockchip,rk3366-usb2phy
++      - rockchip,rk3399-usb2phy
++      - rockchip,rk3568-usb2phy
++      - rockchip,rv1108-usb2phy
++
++  reg:
++    maxItems: 1
++
++  clock-output-names:
++    description:
++      The usb 480m output clock name.
++
++  "#clock-cells":
++    const: 0
++
++  clocks:
++    maxItems: 1
++
++  clock-names:
++    const: phyclk
++
++  assigned-clocks:
++    description:
++      Phandle of the usb 480m clock.
++
++  assigned-clock-parents:
++    description:
++      Parent of the usb 480m clock.
++      Select between usb-phy output 480m and xin24m.
++      Refer to clk/clock-bindings.txt for generic clock consumer properties.
++
++  extcon:
++    description:
++      Phandle to the extcon device providing the cable state for the otg phy.
++
++  interrupts:
++    description: Muxed interrupt for both ports
++    maxItems: 1
++
++  rockchip,usbgrf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to the syscon managing the 'usb general register files'.
++      When set the driver will request its phandle as one companion-grf
++      for some special SoCs (e.g rv1108).
++
++  host-port:
++    type: object
++    additionalProperties: false
++
++    properties:
++      "#phy-cells":
++        const: 0
++
++      interrupts:
++        description: host linestate interrupt
++        maxItems: 1
++
++      interrupt-names:
++        const: linestate
++
++      phy-supply:
++        description:
++          Phandle to a regulator that provides power to VBUS.
++          See ./phy-bindings.txt for details.
++
++    required:
++      - "#phy-cells"
++
++  otg-port:
++    type: object
++    additionalProperties: false
++
++    properties:
++      "#phy-cells":
++        const: 0
++
++      interrupts:
++        minItems: 1
++        maxItems: 3
++
++      interrupt-names:
++        oneOf:
++          - const: linestate
++          - const: otg-mux
++          - items:
++              - const: otg-bvalid
++              - const: otg-id
++              - const: linestate
++
++      phy-supply:
++        description:
++          Phandle to a regulator that provides power to VBUS.
++          See ./phy-bindings.txt for details.
++
++    required:
++      - "#phy-cells"
++
++required:
++  - compatible
++  - reg
++  - clock-output-names
++  - "#clock-cells"
++  - host-port
++  - otg-port
++
++allOf:
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,rk3568-usb2phy
++
++    then:
++      properties:
++        host-port:
++          properties:
++            interrupts: false
++
++        otg-port:
++          properties:
++            interrupts: false
++
++      required:
++        - interrupts
++
++    else:
++      properties:
++        interrupts: false
++
++        host-port:
++          required:
++            - interrupts
++            - interrupt-names
++
++        otg-port:
++          required:
++            - interrupts
++            - interrupt-names
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3399-cru.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/interrupt-controller/irq.h>
++    u2phy0: usb2phy@e450 {
++      compatible = "rockchip,rk3399-usb2phy";
++      reg = <0xe450 0x10>;
++      clocks = <&cru SCLK_USB2PHY0_REF>;
++      clock-names = "phyclk";
++      clock-output-names = "clk_usbphy0_480m";
++      #clock-cells = <0>;
++
++      u2phy0_host: host-port {
++        interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
++        interrupt-names = "linestate";
++        #phy-cells = <0>;
++      };
++
++      u2phy0_otg: otg-port {
++        interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
++                     <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
++                     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
++        interrupt-names = "otg-bvalid", "otg-id", "linestate";
++        #phy-cells = <0>;
++      };
++    };
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -206,7 +206,7 @@ allOf:
+         "usb2phy@[0-9a-f]+$":
+           type: object
+ 
+-          $ref: "/schemas/phy/phy-rockchip-inno-usb2.yaml#"
++          $ref: /schemas/phy/rockchip,inno-usb2phy.yaml#
+ 
+           unevaluatedProperties: false
+ 
diff --git a/target/linux/rockchip/patches-6.1/207-dt-bindings-soc-rockchip-grf-add-rockchip-lvds.yaml.patch b/target/linux/rockchip/patches-6.1/207-dt-bindings-soc-rockchip-grf-add-rockchip-lvds.yaml.patch
new file mode 100644
index 00000000000..ecdeddeb586
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/207-dt-bindings-soc-rockchip-grf-add-rockchip-lvds.yaml.patch
@@ -0,0 +1,41 @@
+From 95da50be5d846250b94a472a8d9aa16f3f34b897 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Thu, 22 Dec 2022 15:24:15 +0100
+Subject: [PATCH 207/383] dt-bindings: soc: rockchip: grf: add
+ rockchip,lvds.yaml
+
+Add new converted rockchip,lvds.yaml to grf.yaml file.
+Prepare for more SoCs with lvds output.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://patchwork.freedesktop.org/patch/msgid/ff3644da-e5ae-f795-c7d9-454b8c8bdfe8@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/soc/rockchip/grf.yaml          | 10 +++++++---
+ 1 file changed, 7 insertions(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -80,13 +80,17 @@ allOf:
+       properties:
+         compatible:
+           contains:
+-            const: rockchip,px30-grf
++            enum:
++              - rockchip,px30-grf
+ 
+     then:
+       properties:
+         lvds:
+-          description:
+-            Documentation/devicetree/bindings/display/rockchip/rockchip-lvds.txt
++          type: object
++
++          $ref: /schemas/display/rockchip/rockchip,lvds.yaml#
++
++          unevaluatedProperties: false
+ 
+   - if:
+       properties:
diff --git a/target/linux/rockchip/patches-6.1/208-dt-bindings-soc-rockchip-add-rk3588-usb2phy-syscon.patch b/target/linux/rockchip/patches-6.1/208-dt-bindings-soc-rockchip-add-rk3588-usb2phy-syscon.patch
new file mode 100644
index 00000000000..ae239947981
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/208-dt-bindings-soc-rockchip-add-rk3588-usb2phy-syscon.patch
@@ -0,0 +1,35 @@
+From 6e33df31caaad43e25a4854f4cb62e241f45638f Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Apr 2023 22:23:01 +0200
+Subject: [PATCH 208/383] dt-bindings: soc: rockchip: add rk3588 usb2phy syscon
+
+The usb2phy is accessible via a syscon registers on RK3588, similar
+to rk3399.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230403202307.120562-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -52,6 +52,7 @@ properties:
+               - rockchip,rk3399-pmugrf
+               - rockchip,rk3568-grf
+               - rockchip,rk3568-pmugrf
++              - rockchip,rk3588-usb2phy-grf
+               - rockchip,rv1108-grf
+               - rockchip,rv1108-pmugrf
+               - rockchip,rv1126-grf
+@@ -199,6 +200,7 @@ allOf:
+               - rockchip,rk3308-usb2phy-grf
+               - rockchip,rk3328-usb2phy-grf
+               - rockchip,rk3399-grf
++              - rockchip,rk3588-usb2phy-grf
+               - rockchip,rv1108-grf
+ 
+     then:
diff --git a/target/linux/rockchip/patches-6.1/209-dt-bindings-rockchip-thermal-Support-the-RK3588-SoC-.patch b/target/linux/rockchip/patches-6.1/209-dt-bindings-rockchip-thermal-Support-the-RK3588-SoC-.patch
new file mode 100644
index 00000000000..ca6c947a00c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/209-dt-bindings-rockchip-thermal-Support-the-RK3588-SoC-.patch
@@ -0,0 +1,28 @@
+From acbd67c1682d4563e2c3778f021c321478aec6f7 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 8 Mar 2023 12:22:53 +0100
+Subject: [PATCH 209/383] dt-bindings: rockchip-thermal: Support the RK3588 SoC
+ compatible
+
+Add a new compatible for the thermal sensor device on RK3588 SoCs.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230308112253.15659-8-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
++++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml
+@@ -19,6 +19,7 @@ properties:
+       - rockchip,rk3368-tsadc
+       - rockchip,rk3399-tsadc
+       - rockchip,rk3568-tsadc
++      - rockchip,rk3588-tsadc
+       - rockchip,rv1108-tsadc
+ 
+   reg:
diff --git a/target/linux/rockchip/patches-6.1/210-dt-bindings-timer-rockchip-Add-rockchip-rk3128-timer.patch b/target/linux/rockchip/patches-6.1/210-dt-bindings-timer-rockchip-Add-rockchip-rk3128-timer.patch
new file mode 100644
index 00000000000..fb19661531c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/210-dt-bindings-timer-rockchip-Add-rockchip-rk3128-timer.patch
@@ -0,0 +1,28 @@
+From 289698c465f3351fa0b330f7ddf92e4ca5bfb854 Mon Sep 17 00:00:00 2001
+From: Johan Jonker <jbx6244@gmail.com>
+Date: Fri, 28 Oct 2022 16:41:30 +0200
+Subject: [PATCH 210/383] dt-bindings: timer: rockchip: Add
+ rockchip,rk3128-timer
+
+Add rockchip,rk3128-timer compatible string.
+
+Signed-off-by: Johan Jonker <jbx6244@gmail.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
+Link: https://lore.kernel.org/r/0e57f38f-bace-8556-7258-aa0b3c0ac103@gmail.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
++++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
+@@ -18,6 +18,7 @@ properties:
+           - enum:
+               - rockchip,rv1108-timer
+               - rockchip,rk3036-timer
++              - rockchip,rk3128-timer
+               - rockchip,rk3188-timer
+               - rockchip,rk3228-timer
+               - rockchip,rk3229-timer
diff --git a/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch
deleted file mode 100644
index 2373d5ab3bf..00000000000
--- a/target/linux/rockchip/patches-6.1/210-rockchip-rk356x-add-support-for-new-boards.patch
+++ /dev/null
@@ -1,57 +0,0 @@
-From 350a1a6557cd7425b6537dd4b226ba3009bee964 Mon Sep 17 00:00:00 2001
-From: =?UTF-8?q?=E4=BA=91=E5=B9=95?= <cancet@embedfire.com>
-Date: Mon, 26 Dec 2022 06:08:38 +0000
-Subject: [PATCH] wode
-
----
- arch/arm64/boot/dts/rockchip/Makefile | 6 ++++++
- 1 file changed, 6 insertions(+)
-
---- a/arch/arm64/boot/dts/rockchip/Makefile
-+++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -19,12 +19,14 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-ro
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock-pi-e.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-cc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-roc-pc.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-doornet1.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-evb-act8846.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-geekbox.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-lion-haikou.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-orion-r68-meta.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-px5-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3368-r88.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-eaidk-610.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-evb.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-ficus.dtb
-@@ -73,6 +75,12 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-qu
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-zero-n.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat1.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat1n.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat2.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat2n.dtb
-+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat2io.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
---- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
-@@ -1780,6 +1780,15 @@
- 		};
- 	};
- 
-+	rng: rng@fe388000 {
-+		compatible = "rockchip,rk3568-rng";
-+		reg = <0x0 0xfe388000 0x0 0x4000>;
-+		clocks = <&cru CLK_TRNG_NS>, <&cru HCLK_TRNG_NS>;
-+		clock-names = "trng_clk", "trng_hclk";
-+		resets = <&cru SRST_TRNG_NS>;
-+		reset-names = "reset";
-+	};
-+
- 	pinctrl: pinctrl {
- 		compatible = "rockchip,rk3568-pinctrl";
- 		rockchip,grf = <&grf>;
diff --git a/target/linux/rockchip/patches-6.1/211-dt-bindings-timer-rk-timer-Add-rktimer-for-rv1126.patch b/target/linux/rockchip/patches-6.1/211-dt-bindings-timer-rk-timer-Add-rktimer-for-rv1126.patch
new file mode 100644
index 00000000000..d30e2f38c8b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/211-dt-bindings-timer-rk-timer-Add-rktimer-for-rv1126.patch
@@ -0,0 +1,26 @@
+From e8cb207d78a65204ce7ba71af460dec49ee587bd Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Thu, 24 Nov 2022 00:01:18 +0530
+Subject: [PATCH 211/383] dt-bindings: timer: rk-timer: Add rktimer for rv1126
+
+Add rockchip timer compatible string for rockchip rv1126.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221123183124.6911-3-jagan@edgeble.ai
+Signed-off-by: Daniel Lezcano <daniel.lezcano@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
++++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
+@@ -17,6 +17,7 @@ properties:
+       - items:
+           - enum:
+               - rockchip,rv1108-timer
++              - rockchip,rv1126-timer
+               - rockchip,rk3036-timer
+               - rockchip,rk3128-timer
+               - rockchip,rk3188-timer
diff --git a/target/linux/rockchip/patches-6.1/212-dt-bindings-timer-rockchip-Drop-superfluous-rk3288-c.patch b/target/linux/rockchip/patches-6.1/212-dt-bindings-timer-rockchip-Drop-superfluous-rk3288-c.patch
new file mode 100644
index 00000000000..1e790c0466d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/212-dt-bindings-timer-rockchip-Drop-superfluous-rk3288-c.patch
@@ -0,0 +1,40 @@
+From 8595bd3140a00cdd20a43453199f3b4a1223ebae Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 19 Apr 2023 21:13:07 +0300
+Subject: [PATCH 212/383] dt-bindings: timer: rockchip: Drop superfluous rk3288
+ compatible
+
+The compatible string for Rockchip RK3288 is wrongly provided in the
+'enum' item, in addition to the subsequent 'const', which allows the
+usage of an incorrect specification:
+
+  compatible = "rockchip,rk3288-timer", "rockchip,rk3288-timer";
+
+As the rk3288 string is also specified in the top-most 'const' item, the
+binding already allows the usage of the correct variant:
+
+  compatible = "rockchip,rk3288-timer";
+
+Drop the unwanted rk3288 entry from the enum.
+
+Fixes: faa186adbd06 ("dt-bindings: timer: convert rockchip,rk-timer.txt to YAML")
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419181309.338354-2-cristian.ciocaltea@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
++++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
+@@ -23,7 +23,6 @@ properties:
+               - rockchip,rk3188-timer
+               - rockchip,rk3228-timer
+               - rockchip,rk3229-timer
+-              - rockchip,rk3288-timer
+               - rockchip,rk3368-timer
+               - rockchip,px30-timer
+           - const: rockchip,rk3288-timer
diff --git a/target/linux/rockchip/patches-6.1/213-dt-bindings-timer-rockchip-Add-rk3588-compatible.patch b/target/linux/rockchip/patches-6.1/213-dt-bindings-timer-rockchip-Add-rk3588-compatible.patch
new file mode 100644
index 00000000000..d1db22f58d5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/213-dt-bindings-timer-rockchip-Add-rk3588-compatible.patch
@@ -0,0 +1,27 @@
+From c59821c362910fc1f773a36577aec17c29f061dc Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 19 Apr 2023 21:13:08 +0300
+Subject: [PATCH 213/383] dt-bindings: timer: rockchip: Add rk3588 compatible
+
+Add compatible string for Rockchip RK3588 timer.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230419181309.338354-3-cristian.ciocaltea@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
++++ b/Documentation/devicetree/bindings/timer/rockchip,rk-timer.yaml
+@@ -24,6 +24,7 @@ properties:
+               - rockchip,rk3228-timer
+               - rockchip,rk3229-timer
+               - rockchip,rk3368-timer
++              - rockchip,rk3588-timer
+               - rockchip,px30-timer
+           - const: rockchip,rk3288-timer
+   reg:
diff --git a/target/linux/rockchip/patches-6.1/214-dt-bindings-usb-rockchip-dwc3-Move-RK3399-to-its-own.patch b/target/linux/rockchip/patches-6.1/214-dt-bindings-usb-rockchip-dwc3-Move-RK3399-to-its-own.patch
new file mode 100644
index 00000000000..63bfc502407
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/214-dt-bindings-usb-rockchip-dwc3-Move-RK3399-to-its-own.patch
@@ -0,0 +1,186 @@
+From 36e89e629736513666902e0a0e6a1c9d4eb54da1 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Mon, 23 Jan 2023 20:59:36 -0600
+Subject: [PATCH 214/383] dt-bindings: usb: rockchip,dwc3: Move RK3399 to its
+ own schema
+
+The rockchip,dwc3.yaml schema defines a single DWC3 node, but the RK3399
+uses the discouraged parent wrapper node and child 'generic' DWC3 node.
+The intent was to modify the RK3399 DTs to use a single node, but the DT
+changes were rejected for ABI reasons. However, the schema was accepted
+as-is.
+
+To fix this, we need to move the RK3399 binding to its own schema file.
+The RK3328 and RK3568 bindings are correct and use a single node.
+
+Cc: Johan Jonker <jbx6244@gmail.com>
+Signed-off-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230124025936.3256213-2-robh@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/usb/rockchip,dwc3.yaml           |  10 +-
+ .../bindings/usb/rockchip,rk3399-dwc3.yaml    | 115 ++++++++++++++++++
+ 2 files changed, 119 insertions(+), 6 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml
+
+--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
++++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+@@ -29,7 +29,6 @@ select:
+       contains:
+         enum:
+           - rockchip,rk3328-dwc3
+-          - rockchip,rk3399-dwc3
+           - rockchip,rk3568-dwc3
+   required:
+     - compatible
+@@ -39,7 +38,6 @@ properties:
+     items:
+       - enum:
+           - rockchip,rk3328-dwc3
+-          - rockchip,rk3399-dwc3
+           - rockchip,rk3568-dwc3
+       - const: snps,dwc3
+ 
+@@ -90,7 +88,7 @@ required:
+ 
+ examples:
+   - |
+-    #include <dt-bindings/clock/rk3399-cru.h>
++    #include <dt-bindings/clock/rk3328-cru.h>
+     #include <dt-bindings/interrupt-controller/arm-gic.h>
+ 
+     bus {
+@@ -98,11 +96,11 @@ examples:
+       #size-cells = <2>;
+ 
+       usbdrd3_0: usb@fe800000 {
+-        compatible = "rockchip,rk3399-dwc3", "snps,dwc3";
++        compatible = "rockchip,rk3328-dwc3", "snps,dwc3";
+         reg = <0x0 0xfe800000 0x0 0x100000>;
+         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
+-        clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
+-                 <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_GRF>;
++        clocks = <&cru SCLK_USB3OTG_REF>, <&cru SCLK_USB3OTG_SUSPEND>,
++                 <&cru ACLK_USB3OTG>;
+         clock-names = "ref_clk", "suspend_clk",
+                       "bus_clk", "grf_clk";
+         dr_mode = "otg";
+--- /dev/null
++++ b/Documentation/devicetree/bindings/usb/rockchip,rk3399-dwc3.yaml
+@@ -0,0 +1,115 @@
++# SPDX-License-Identifier: GPL-2.0
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/usb/rockchip,rk3399-dwc3.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip RK3399 SuperSpeed DWC3 USB SoC controller
++
++maintainers:
++  - Heiko Stuebner <heiko@sntech.de>
++
++properties:
++  compatible:
++    const: rockchip,rk3399-dwc3
++
++  '#address-cells':
++    const: 2
++
++  '#size-cells':
++    const: 2
++
++  ranges: true
++
++  clocks:
++    items:
++      - description:
++          Controller reference clock, must to be 24 MHz
++      - description:
++          Controller suspend clock, must to be 24 MHz or 32 KHz
++      - description:
++          Master/Core clock, must to be >= 62.5 MHz for SS
++          operation and >= 30MHz for HS operation
++      - description:
++          USB3 aclk peri
++      - description:
++          USB3 aclk
++      - description:
++          Controller grf clock
++
++  clock-names:
++    items:
++      - const: ref_clk
++      - const: suspend_clk
++      - const: bus_clk
++      - const: aclk_usb3_rksoc_axi_perf
++      - const: aclk_usb3
++      - const: grf_clk
++
++  resets:
++    maxItems: 1
++
++  reset-names:
++    const: usb3-otg
++
++patternProperties:
++  '^usb@':
++    $ref: snps,dwc3.yaml#
++
++additionalProperties: false
++
++required:
++  - compatible
++  - '#address-cells'
++  - '#size-cells'
++  - ranges
++  - clocks
++  - clock-names
++  - resets
++  - reset-names
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3399-cru.h>
++    #include <dt-bindings/power/rk3399-power.h>
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++
++    bus {
++        #address-cells = <2>;
++        #size-cells = <2>;
++
++        usb {
++            compatible = "rockchip,rk3399-dwc3";
++            #address-cells = <2>;
++            #size-cells = <2>;
++            ranges;
++            clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
++                     <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
++                     <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
++            clock-names = "ref_clk", "suspend_clk",
++                          "bus_clk", "aclk_usb3_rksoc_axi_perf",
++                          "aclk_usb3", "grf_clk";
++            resets = <&cru SRST_A_USB3_OTG0>;
++            reset-names = "usb3-otg";
++
++            usb@fe800000 {
++                compatible = "snps,dwc3";
++                reg = <0x0 0xfe800000 0x0 0x100000>;
++                interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
++                clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
++                         <&cru SCLK_USB3OTG0_SUSPEND>;
++                clock-names = "ref", "bus_early", "suspend";
++                dr_mode = "otg";
++                phys = <&u2phy0_otg>, <&tcphy0_usb3>;
++                phy-names = "usb2-phy", "usb3-phy";
++                phy_type = "utmi_wide";
++                snps,dis_enblslpm_quirk;
++                snps,dis-u2-freeclk-exists-quirk;
++                snps,dis_u2_susphy_quirk;
++                snps,dis-del-phy-power-chg-quirk;
++                snps,dis-tx-ipgap-linecheck-quirk;
++                power-domains = <&power RK3399_PD_USB3>;
++            };
++        };
++    };
++...
diff --git a/target/linux/rockchip/patches-6.1/215-clk-rockchip-add-register-offset-of-the-cores-select.patch b/target/linux/rockchip/patches-6.1/215-clk-rockchip-add-register-offset-of-the-cores-select.patch
new file mode 100644
index 00000000000..675540770fa
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/215-clk-rockchip-add-register-offset-of-the-cores-select.patch
@@ -0,0 +1,81 @@
+From 213cd57683805c67f3271263a034a3716afe0bfb Mon Sep 17 00:00:00 2001
+From: Elaine Zhang <zhangqing@rock-chips.com>
+Date: Tue, 18 Oct 2022 17:14:02 +0200
+Subject: [PATCH 215/383] clk: rockchip: add register offset of the cores
+ select parent
+
+The cores select parent register is special on RK3588.
+
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-5-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk-cpu.c | 28 ++++++++++++++++++++--------
+ drivers/clk/rockchip/clk.h     |  3 +++
+ 2 files changed, 23 insertions(+), 8 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-cpu.c
++++ b/drivers/clk/rockchip/clk-cpu.c
+@@ -166,10 +166,16 @@ static int rockchip_cpuclk_pre_rate_chan
+ 		}
+ 	}
+ 	/* select alternate parent */
+-	writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+-			     reg_data->mux_core_mask,
+-			     reg_data->mux_core_shift),
+-	       cpuclk->reg_base + reg_data->core_reg[0]);
++	if (reg_data->mux_core_reg)
++		writel(HIWORD_UPDATE(reg_data->mux_core_alt,
++				     reg_data->mux_core_mask,
++				     reg_data->mux_core_shift),
++		       cpuclk->reg_base + reg_data->mux_core_reg);
++	else
++		writel(HIWORD_UPDATE(reg_data->mux_core_alt,
++				     reg_data->mux_core_mask,
++				     reg_data->mux_core_shift),
++		       cpuclk->reg_base + reg_data->core_reg[0]);
+ 
+ 	spin_unlock_irqrestore(cpuclk->lock, flags);
+ 	return 0;
+@@ -202,10 +208,16 @@ static int rockchip_cpuclk_post_rate_cha
+ 	 * primary parent by the extra dividers that were needed for the alt.
+ 	 */
+ 
+-	writel(HIWORD_UPDATE(reg_data->mux_core_main,
+-			     reg_data->mux_core_mask,
+-			     reg_data->mux_core_shift),
+-	       cpuclk->reg_base + reg_data->core_reg[0]);
++	if (reg_data->mux_core_reg)
++		writel(HIWORD_UPDATE(reg_data->mux_core_main,
++				     reg_data->mux_core_mask,
++				     reg_data->mux_core_shift),
++		       cpuclk->reg_base + reg_data->mux_core_reg);
++	else
++		writel(HIWORD_UPDATE(reg_data->mux_core_main,
++				     reg_data->mux_core_mask,
++				     reg_data->mux_core_shift),
++		       cpuclk->reg_base + reg_data->core_reg[0]);
+ 
+ 	/* remove dividers */
+ 	for (i = 0; i < reg_data->num_cores; i++) {
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -389,6 +389,8 @@ struct rockchip_cpuclk_rate_table {
+  * @div_core_shift[]:	cores divider offset used to divide the pll value
+  * @div_core_mask[]:	cores divider mask
+  * @num_cores:	number of cpu cores
++ * @mux_core_reg:       register offset of the cores select parent
++ * @mux_core_alt:       mux value to select alternate parent
+  * @mux_core_main:	mux value to select main parent of core
+  * @mux_core_shift:	offset of the core multiplexer
+  * @mux_core_mask:	core multiplexer mask
+@@ -398,6 +400,7 @@ struct rockchip_cpuclk_reg_data {
+ 	u8	div_core_shift[ROCKCHIP_CPUCLK_MAX_CORES];
+ 	u32	div_core_mask[ROCKCHIP_CPUCLK_MAX_CORES];
+ 	int	num_cores;
++	int	mux_core_reg;
+ 	u8	mux_core_alt;
+ 	u8	mux_core_main;
+ 	u8	mux_core_shift;
diff --git a/target/linux/rockchip/patches-6.1/216-clk-rockchip-add-pll-type-for-RK3588.patch b/target/linux/rockchip/patches-6.1/216-clk-rockchip-add-pll-type-for-RK3588.patch
new file mode 100644
index 00000000000..a5566faa72f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/216-clk-rockchip-add-pll-type-for-RK3588.patch
@@ -0,0 +1,301 @@
+From e8e23381852477cef6c4c21772732b09604959c9 Mon Sep 17 00:00:00 2001
+From: Elaine Zhang <zhangqing@rock-chips.com>
+Date: Tue, 18 Oct 2022 17:14:03 +0200
+Subject: [PATCH 216/383] clk: rockchip: add pll type for RK3588
+
+Add RK3588 PLL support fully relying on lookup tables like
+the other upstream supported rockchip platforms.
+
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+[rebase and modify code to avoid PLL parameter calculation]
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-6-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk-pll.c | 218 ++++++++++++++++++++++++++++++++-
+ drivers/clk/rockchip/clk.h     |  18 +++
+ 2 files changed, 235 insertions(+), 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk-pll.c
++++ b/drivers/clk/rockchip/clk-pll.c
+@@ -843,6 +843,213 @@ static const struct clk_ops rockchip_rk3
+ };
+ 
+ /*
++ * PLL used in RK3588
++ */
++
++#define RK3588_PLLCON(i)               (i * 0x4)
++#define RK3588_PLLCON0_M_MASK          0x3ff
++#define RK3588_PLLCON0_M_SHIFT         0
++#define RK3588_PLLCON1_P_MASK          0x3f
++#define RK3588_PLLCON1_P_SHIFT         0
++#define RK3588_PLLCON1_S_MASK          0x7
++#define RK3588_PLLCON1_S_SHIFT         6
++#define RK3588_PLLCON2_K_MASK          0xffff
++#define RK3588_PLLCON2_K_SHIFT         0
++#define RK3588_PLLCON1_PWRDOWN         BIT(13)
++#define RK3588_PLLCON6_LOCK_STATUS     BIT(15)
++
++static int rockchip_rk3588_pll_wait_lock(struct rockchip_clk_pll *pll)
++{
++	u32 pllcon;
++	int ret;
++
++	/*
++	 * Lock time typical 250, max 500 input clock cycles @24MHz
++	 * So define a very safe maximum of 1000us, meaning 24000 cycles.
++	 */
++	ret = readl_relaxed_poll_timeout(pll->reg_base + RK3588_PLLCON(6),
++					 pllcon,
++					 pllcon & RK3588_PLLCON6_LOCK_STATUS,
++					 0, 1000);
++	if (ret)
++		pr_err("%s: timeout waiting for pll to lock\n", __func__);
++
++	return ret;
++}
++
++static void rockchip_rk3588_pll_get_params(struct rockchip_clk_pll *pll,
++					   struct rockchip_pll_rate_table *rate)
++{
++	u32 pllcon;
++
++	pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(0));
++	rate->m = ((pllcon >> RK3588_PLLCON0_M_SHIFT) & RK3588_PLLCON0_M_MASK);
++
++	pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(1));
++	rate->p = ((pllcon >> RK3588_PLLCON1_P_SHIFT) & RK3588_PLLCON1_P_MASK);
++	rate->s = ((pllcon >> RK3588_PLLCON1_S_SHIFT) & RK3588_PLLCON1_S_MASK);
++
++	pllcon = readl_relaxed(pll->reg_base + RK3588_PLLCON(2));
++	rate->k = ((pllcon >> RK3588_PLLCON2_K_SHIFT) & RK3588_PLLCON2_K_MASK);
++}
++
++static unsigned long rockchip_rk3588_pll_recalc_rate(struct clk_hw *hw, unsigned long prate)
++{
++	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
++	struct rockchip_pll_rate_table cur;
++	u64 rate64 = prate, postdiv;
++
++	rockchip_rk3588_pll_get_params(pll, &cur);
++
++	rate64 *= cur.m;
++	do_div(rate64, cur.p);
++
++	if (cur.k) {
++		/* fractional mode */
++		u64 frac_rate64 = prate * cur.k;
++
++		postdiv = cur.p * 65535;
++		do_div(frac_rate64, postdiv);
++		rate64 += frac_rate64;
++	}
++	rate64 = rate64 >> cur.s;
++
++	return (unsigned long)rate64;
++}
++
++static int rockchip_rk3588_pll_set_params(struct rockchip_clk_pll *pll,
++					  const struct rockchip_pll_rate_table *rate)
++{
++	const struct clk_ops *pll_mux_ops = pll->pll_mux_ops;
++	struct clk_mux *pll_mux = &pll->pll_mux;
++	struct rockchip_pll_rate_table cur;
++	int rate_change_remuxed = 0;
++	int cur_parent;
++	int ret;
++
++	pr_debug("%s: rate settings for %lu p: %d, m: %d, s: %d, k: %d\n",
++		 __func__, rate->rate, rate->p, rate->m, rate->s, rate->k);
++
++	rockchip_rk3588_pll_get_params(pll, &cur);
++	cur.rate = 0;
++
++	if (pll->type == pll_rk3588) {
++		cur_parent = pll_mux_ops->get_parent(&pll_mux->hw);
++		if (cur_parent == PLL_MODE_NORM) {
++			pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_SLOW);
++			rate_change_remuxed = 1;
++		}
++	}
++
++	/* set pll power down */
++	writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN,
++			     RK3588_PLLCON1_PWRDOWN, 0),
++	       pll->reg_base + RK3399_PLLCON(1));
++
++	/* update pll values */
++	writel_relaxed(HIWORD_UPDATE(rate->m, RK3588_PLLCON0_M_MASK, RK3588_PLLCON0_M_SHIFT),
++		       pll->reg_base + RK3399_PLLCON(0));
++
++	writel_relaxed(HIWORD_UPDATE(rate->p, RK3588_PLLCON1_P_MASK, RK3588_PLLCON1_P_SHIFT) |
++		       HIWORD_UPDATE(rate->s, RK3588_PLLCON1_S_MASK, RK3588_PLLCON1_S_SHIFT),
++		       pll->reg_base + RK3399_PLLCON(1));
++
++	writel_relaxed(HIWORD_UPDATE(rate->k, RK3588_PLLCON2_K_MASK, RK3588_PLLCON2_K_SHIFT),
++		       pll->reg_base + RK3399_PLLCON(2));
++
++	/* set pll power up */
++	writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
++	       pll->reg_base + RK3588_PLLCON(1));
++
++	/* wait for the pll to lock */
++	ret = rockchip_rk3588_pll_wait_lock(pll);
++	if (ret) {
++		pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
++			__func__);
++		rockchip_rk3588_pll_set_params(pll, &cur);
++	}
++
++	if ((pll->type == pll_rk3588) && rate_change_remuxed)
++		pll_mux_ops->set_parent(&pll_mux->hw, PLL_MODE_NORM);
++
++	return ret;
++}
++
++static int rockchip_rk3588_pll_set_rate(struct clk_hw *hw, unsigned long drate,
++					unsigned long prate)
++{
++	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
++	const struct rockchip_pll_rate_table *rate;
++
++	pr_debug("%s: changing %s to %lu with a parent rate of %lu\n",
++		 __func__, __clk_get_name(hw->clk), drate, prate);
++
++	/* Get required rate settings from table */
++	rate = rockchip_get_pll_settings(pll, drate);
++	if (!rate) {
++		pr_err("%s: Invalid rate : %lu for pll clk %s\n", __func__,
++			drate, __clk_get_name(hw->clk));
++		return -EINVAL;
++	}
++
++	return rockchip_rk3588_pll_set_params(pll, rate);
++}
++
++static int rockchip_rk3588_pll_enable(struct clk_hw *hw)
++{
++	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
++
++	writel(HIWORD_UPDATE(0, RK3588_PLLCON1_PWRDOWN, 0),
++	       pll->reg_base + RK3588_PLLCON(1));
++	rockchip_rk3588_pll_wait_lock(pll);
++
++	return 0;
++}
++
++static void rockchip_rk3588_pll_disable(struct clk_hw *hw)
++{
++	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
++
++	writel(HIWORD_UPDATE(RK3588_PLLCON1_PWRDOWN, RK3588_PLLCON1_PWRDOWN, 0),
++	       pll->reg_base + RK3588_PLLCON(1));
++}
++
++static int rockchip_rk3588_pll_is_enabled(struct clk_hw *hw)
++{
++	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
++	u32 pllcon = readl(pll->reg_base + RK3588_PLLCON(1));
++
++	return !(pllcon & RK3588_PLLCON1_PWRDOWN);
++}
++
++static int rockchip_rk3588_pll_init(struct clk_hw *hw)
++{
++	struct rockchip_clk_pll *pll = to_rockchip_clk_pll(hw);
++
++	if (!(pll->flags & ROCKCHIP_PLL_SYNC_RATE))
++		return 0;
++
++	return 0;
++}
++
++static const struct clk_ops rockchip_rk3588_pll_clk_norate_ops = {
++	.recalc_rate = rockchip_rk3588_pll_recalc_rate,
++	.enable = rockchip_rk3588_pll_enable,
++	.disable = rockchip_rk3588_pll_disable,
++	.is_enabled = rockchip_rk3588_pll_is_enabled,
++};
++
++static const struct clk_ops rockchip_rk3588_pll_clk_ops = {
++	.recalc_rate = rockchip_rk3588_pll_recalc_rate,
++	.round_rate = rockchip_pll_round_rate,
++	.set_rate = rockchip_rk3588_pll_set_rate,
++	.enable = rockchip_rk3588_pll_enable,
++	.disable = rockchip_rk3588_pll_disable,
++	.is_enabled = rockchip_rk3588_pll_is_enabled,
++	.init = rockchip_rk3588_pll_init,
++};
++
++/*
+  * Common registering of pll clocks
+  */
+ 
+@@ -890,7 +1097,8 @@ struct clk *rockchip_clk_register_pll(st
+ 	if (pll_type == pll_rk3036 ||
+ 	    pll_type == pll_rk3066 ||
+ 	    pll_type == pll_rk3328 ||
+-	    pll_type == pll_rk3399)
++	    pll_type == pll_rk3399 ||
++	    pll_type == pll_rk3588)
+ 		pll_mux->flags |= CLK_MUX_HIWORD_MASK;
+ 
+ 	/* the actual muxing is xin24m, pll-output, xin32k */
+@@ -957,6 +1165,14 @@ struct clk *rockchip_clk_register_pll(st
+ 		else
+ 			init.ops = &rockchip_rk3399_pll_clk_ops;
+ 		break;
++	case pll_rk3588:
++	case pll_rk3588_core:
++		if (!pll->rate_table)
++			init.ops = &rockchip_rk3588_pll_clk_norate_ops;
++		else
++			init.ops = &rockchip_rk3588_pll_clk_ops;
++		init.flags = flags;
++		break;
+ 	default:
+ 		pr_warn("%s: Unknown pll type for pll clk %s\n",
+ 			__func__, name);
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -240,6 +240,8 @@ enum rockchip_pll_type {
+ 	pll_rk3066,
+ 	pll_rk3328,
+ 	pll_rk3399,
++	pll_rk3588,
++	pll_rk3588_core,
+ };
+ 
+ #define RK3036_PLL_RATE(_rate, _refdiv, _fbdiv, _postdiv1,	\
+@@ -272,6 +274,15 @@ enum rockchip_pll_type {
+ 	.nb = _nb,						\
+ }
+ 
++#define RK3588_PLL_RATE(_rate, _p, _m, _s, _k)			\
++{								\
++	.rate   = _rate##U,					\
++	.p = _p,						\
++	.m = _m,						\
++	.s = _s,						\
++	.k = _k,						\
++}
++
+ /**
+  * struct rockchip_clk_provider - information about clock provider
+  * @reg_base: virtual address for the register base.
+@@ -307,6 +318,13 @@ struct rockchip_pll_rate_table {
+ 			unsigned int dsmpd;
+ 			unsigned int frac;
+ 		};
++		struct {
++			/* for RK3588 */
++			unsigned int m;
++			unsigned int p;
++			unsigned int s;
++			unsigned int k;
++		};
+ 	};
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/217-clk-rockchip-allow-additional-mux-options-for-cpu-cl.patch b/target/linux/rockchip/patches-6.1/217-clk-rockchip-allow-additional-mux-options-for-cpu-cl.patch
new file mode 100644
index 00000000000..5b349092573
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/217-clk-rockchip-allow-additional-mux-options-for-cpu-cl.patch
@@ -0,0 +1,123 @@
+From 7942aa7e188ebaa3bdb1677ef729969c9612e0e3 Mon Sep 17 00:00:00 2001
+From: Elaine Zhang <zhangqing@rock-chips.com>
+Date: Tue, 18 Oct 2022 17:14:04 +0200
+Subject: [PATCH 217/383] clk: rockchip: allow additional mux options for
+ cpu-clock frequency changes
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+In order to improve the main frequency of CPU, the clock path of CPU is
+simplified as follows:
+                         |--\
+                         |   \            |--\
+ --apll--|\              |    \           |   \
+         | |--apll_core--|     \          |    \
+ --24M---|/              |mux1 |--[gate]--|mux2|---clk_core
+                         |     /          |    /
+ --gpll--|\              |    /    |------|   /
+         | |--gpll_core--|   /     |      |--/
+ --24M---|/              |--/      |
+                                   |
+ -------apll_directly--------------|
+
+When the CPU requests high frequency, we want to use MUX2 select the
+"apll_directly".
+At low frequencies use MUX1 to select “apll_core" and then MUX2 to
+select "apll_core_gate".
+
+However, in this way, the CPU frequency conversion needs to be
+in the following order:
+1. MUX2 select to "apll_core_gate", MUX1 select "gpll_core"
+2. Apll sets slow_mode, sets APLL parameters, locks APLL, and then APLL
+sets normal_mode
+3. MUX1 select "apll_core", MUX2 select "apll_directly"
+
+So add pre_mux and post_mux options to cover this special requirements.
+
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+[rebase]
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-7-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk-cpu.c | 41 ++++++++++++++++++++++++++++++++++
+ drivers/clk/rockchip/clk.h     |  2 ++
+ 2 files changed, 43 insertions(+)
+
+--- a/drivers/clk/rockchip/clk-cpu.c
++++ b/drivers/clk/rockchip/clk-cpu.c
+@@ -113,6 +113,42 @@ static void rockchip_cpuclk_set_dividers
+ 	}
+ }
+ 
++static void rockchip_cpuclk_set_pre_muxs(struct rockchip_cpuclk *cpuclk,
++					 const struct rockchip_cpuclk_rate_table *rate)
++{
++	int i;
++
++	/* alternate parent is active now. set the pre_muxs */
++	for (i = 0; i < ARRAY_SIZE(rate->pre_muxs); i++) {
++		const struct rockchip_cpuclk_clksel *clksel = &rate->pre_muxs[i];
++
++		if (!clksel->reg)
++			break;
++
++		pr_debug("%s: setting reg 0x%x to 0x%x\n",
++			 __func__, clksel->reg, clksel->val);
++		writel(clksel->val, cpuclk->reg_base + clksel->reg);
++	}
++}
++
++static void rockchip_cpuclk_set_post_muxs(struct rockchip_cpuclk *cpuclk,
++					  const struct rockchip_cpuclk_rate_table *rate)
++{
++	int i;
++
++	/* alternate parent is active now. set the muxs */
++	for (i = 0; i < ARRAY_SIZE(rate->post_muxs); i++) {
++		const struct rockchip_cpuclk_clksel *clksel = &rate->post_muxs[i];
++
++		if (!clksel->reg)
++			break;
++
++		pr_debug("%s: setting reg 0x%x to 0x%x\n",
++			 __func__, clksel->reg, clksel->val);
++		writel(clksel->val, cpuclk->reg_base + clksel->reg);
++	}
++}
++
+ static int rockchip_cpuclk_pre_rate_change(struct rockchip_cpuclk *cpuclk,
+ 					   struct clk_notifier_data *ndata)
+ {
+@@ -165,6 +201,9 @@ static int rockchip_cpuclk_pre_rate_chan
+ 			       cpuclk->reg_base + reg_data->core_reg[i]);
+ 		}
+ 	}
++
++	rockchip_cpuclk_set_pre_muxs(cpuclk, rate);
++
+ 	/* select alternate parent */
+ 	if (reg_data->mux_core_reg)
+ 		writel(HIWORD_UPDATE(reg_data->mux_core_alt,
+@@ -219,6 +258,8 @@ static int rockchip_cpuclk_post_rate_cha
+ 				     reg_data->mux_core_shift),
+ 		       cpuclk->reg_base + reg_data->core_reg[0]);
+ 
++	rockchip_cpuclk_set_post_muxs(cpuclk, rate);
++
+ 	/* remove dividers */
+ 	for (i = 0; i < reg_data->num_cores; i++) {
+ 		writel(HIWORD_UPDATE(0, reg_data->div_core_mask[i],
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -399,6 +399,8 @@ struct rockchip_cpuclk_clksel {
+ struct rockchip_cpuclk_rate_table {
+ 	unsigned long prate;
+ 	struct rockchip_cpuclk_clksel divs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
++	struct rockchip_cpuclk_clksel pre_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
++	struct rockchip_cpuclk_clksel post_muxs[ROCKCHIP_CPUCLK_NUM_DIVIDERS];
+ };
+ 
+ /**
diff --git a/target/linux/rockchip/patches-6.1/218-clk-rockchip-simplify-rockchip_clk_add_lookup.patch b/target/linux/rockchip/patches-6.1/218-clk-rockchip-simplify-rockchip_clk_add_lookup.patch
new file mode 100644
index 00000000000..779aab6308c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/218-clk-rockchip-simplify-rockchip_clk_add_lookup.patch
@@ -0,0 +1,73 @@
+From 37bf5284d424b395e804f8a93ce4b262998966c6 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 18 Oct 2022 17:14:05 +0200
+Subject: [PATCH 218/383] clk: rockchip: simplify rockchip_clk_add_lookup
+
+rockchip_clk_add_lookup is only called from within the file,
+so it can be made static. The additional checks are removed
+with the following reasoning:
+
+1. The data structure is initialized by rockchip_clk_init(),
+   which is called by all rockchip platforms before the clocks
+   are registered. Not doing so would result in an incomplete
+   clock tree at the moment, which is a fatal error. In other
+   parts of the kernel these kind of checks are usually
+   omitted, so this was done here. The alternative is adding
+   a pr_err to inform the kernel programmer adding a new platform
+   about his incorrect code. Apart from that we are also not
+   checking if the clock id is within the array boundings.
+
+2. While not used so far by any rockchip platform, 0 is a valid
+   clock identifier. To align rockchip closer to other ARM
+   platforms we will start using it with rk3588.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-8-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk.c | 14 ++++++--------
+ drivers/clk/rockchip/clk.h |  2 --
+ 2 files changed, 6 insertions(+), 10 deletions(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -198,6 +198,12 @@ static void rockchip_fractional_approxim
+ 	clk_fractional_divider_general_approximation(hw, rate, parent_rate, m, n);
+ }
+ 
++static void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
++				    struct clk *clk, unsigned int id)
++{
++	ctx->clk_data.clks[id] = clk;
++}
++
+ static struct clk *rockchip_clk_register_frac_branch(
+ 		struct rockchip_clk_provider *ctx, const char *name,
+ 		const char *const *parent_names, u8 num_parents,
+@@ -401,14 +407,6 @@ void rockchip_clk_of_add_provider(struct
+ }
+ EXPORT_SYMBOL_GPL(rockchip_clk_of_add_provider);
+ 
+-void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
+-			     struct clk *clk, unsigned int id)
+-{
+-	if (ctx->clk_data.clks && id)
+-		ctx->clk_data.clks[id] = clk;
+-}
+-EXPORT_SYMBOL_GPL(rockchip_clk_add_lookup);
+-
+ void rockchip_clk_register_plls(struct rockchip_clk_provider *ctx,
+ 				struct rockchip_pll_clock *list,
+ 				unsigned int nr_pll, int grf_lock_offset)
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -928,8 +928,6 @@ struct rockchip_clk_provider *rockchip_c
+ 			void __iomem *base, unsigned long nr_clks);
+ void rockchip_clk_of_add_provider(struct device_node *np,
+ 				struct rockchip_clk_provider *ctx);
+-void rockchip_clk_add_lookup(struct rockchip_clk_provider *ctx,
+-			     struct clk *clk, unsigned int id);
+ void rockchip_clk_register_branches(struct rockchip_clk_provider *ctx,
+ 				    struct rockchip_clk_branch *list,
+ 				    unsigned int nr_clk);
diff --git a/target/linux/rockchip/patches-6.1/219-clk-rockchip-add-lookup-table-support.patch b/target/linux/rockchip/patches-6.1/219-clk-rockchip-add-lookup-table-support.patch
new file mode 100644
index 00000000000..4fc580ba203
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/219-clk-rockchip-add-lookup-table-support.patch
@@ -0,0 +1,131 @@
+From 4837f108f8c3a9a4a0c97b3b9a1988136012aba6 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 18 Oct 2022 17:14:06 +0200
+Subject: [PATCH 219/383] clk: rockchip: add lookup table support
+
+Add support for mapping reset IDs to register offsets
+to support gapless continous platform reset IDs.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-9-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk.h     | 21 +++++++++++++++------
+ drivers/clk/rockchip/softrst.c | 34 +++++++++++++++++++++++++---------
+ 2 files changed, 40 insertions(+), 15 deletions(-)
+
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -958,15 +958,24 @@ struct clk *rockchip_clk_register_halfdi
+ 					  spinlock_t *lock);
+ 
+ #ifdef CONFIG_RESET_CONTROLLER
+-void rockchip_register_softrst(struct device_node *np,
+-			       unsigned int num_regs,
+-			       void __iomem *base, u8 flags);
++void rockchip_register_softrst_lut(struct device_node *np,
++				   const int *lookup_table,
++				   unsigned int num_regs,
++				   void __iomem *base, u8 flags);
+ #else
+-static inline void rockchip_register_softrst(struct device_node *np,
+-			       unsigned int num_regs,
+-			       void __iomem *base, u8 flags)
++static inline void rockchip_register_softrst_lut(struct device_node *np,
++				   const int *lookup_table,
++				   unsigned int num_regs,
++				   void __iomem *base, u8 flags)
+ {
+ }
+ #endif
+ 
++static inline void rockchip_register_softrst(struct device_node *np,
++					     unsigned int num_regs,
++					     void __iomem *base, u8 flags)
++{
++	return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
++}
++
+ #endif
+--- a/drivers/clk/rockchip/softrst.c
++++ b/drivers/clk/rockchip/softrst.c
+@@ -12,6 +12,7 @@
+ 
+ struct rockchip_softrst {
+ 	struct reset_controller_dev	rcdev;
++	const int			*lut;
+ 	void __iomem			*reg_base;
+ 	int				num_regs;
+ 	int				num_per_reg;
+@@ -25,8 +26,13 @@ static int rockchip_softrst_assert(struc
+ 	struct rockchip_softrst *softrst = container_of(rcdev,
+ 						     struct rockchip_softrst,
+ 						     rcdev);
+-	int bank = id / softrst->num_per_reg;
+-	int offset = id % softrst->num_per_reg;
++	int bank, offset;
++
++	if (softrst->lut)
++		id = softrst->lut[id];
++
++	bank = id / softrst->num_per_reg;
++	offset = id % softrst->num_per_reg;
+ 
+ 	if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
+ 		writel(BIT(offset) | (BIT(offset) << 16),
+@@ -52,8 +58,13 @@ static int rockchip_softrst_deassert(str
+ 	struct rockchip_softrst *softrst = container_of(rcdev,
+ 						     struct rockchip_softrst,
+ 						     rcdev);
+-	int bank = id / softrst->num_per_reg;
+-	int offset = id % softrst->num_per_reg;
++	int bank, offset;
++
++	if (softrst->lut)
++		id = softrst->lut[id];
++
++	bank = id / softrst->num_per_reg;
++	offset = id % softrst->num_per_reg;
+ 
+ 	if (softrst->flags & ROCKCHIP_SOFTRST_HIWORD_MASK) {
+ 		writel((BIT(offset) << 16), softrst->reg_base + (bank * 4));
+@@ -77,9 +88,10 @@ static const struct reset_control_ops ro
+ 	.deassert	= rockchip_softrst_deassert,
+ };
+ 
+-void rockchip_register_softrst(struct device_node *np,
+-			       unsigned int num_regs,
+-			       void __iomem *base, u8 flags)
++void rockchip_register_softrst_lut(struct device_node *np,
++				   const int *lookup_table,
++				   unsigned int num_regs,
++				   void __iomem *base, u8 flags)
+ {
+ 	struct rockchip_softrst *softrst;
+ 	int ret;
+@@ -91,13 +103,17 @@ void rockchip_register_softrst(struct de
+ 	spin_lock_init(&softrst->lock);
+ 
+ 	softrst->reg_base = base;
++	softrst->lut = lookup_table;
+ 	softrst->flags = flags;
+ 	softrst->num_regs = num_regs;
+ 	softrst->num_per_reg = (flags & ROCKCHIP_SOFTRST_HIWORD_MASK) ? 16
+ 								      : 32;
+ 
+ 	softrst->rcdev.owner = THIS_MODULE;
+-	softrst->rcdev.nr_resets =  num_regs * softrst->num_per_reg;
++	if (lookup_table)
++		softrst->rcdev.nr_resets = num_regs;
++	else
++		softrst->rcdev.nr_resets = num_regs * softrst->num_per_reg;
+ 	softrst->rcdev.ops = &rockchip_softrst_ops;
+ 	softrst->rcdev.of_node = np;
+ 	ret = reset_controller_register(&softrst->rcdev);
+@@ -107,4 +123,4 @@ void rockchip_register_softrst(struct de
+ 		kfree(softrst);
+ 	}
+ };
+-EXPORT_SYMBOL_GPL(rockchip_register_softrst);
++EXPORT_SYMBOL_GPL(rockchip_register_softrst_lut);
diff --git a/target/linux/rockchip/patches-6.1/220-clk-rockchip-add-clock-controller-for-the-RK3588.patch b/target/linux/rockchip/patches-6.1/220-clk-rockchip-add-clock-controller-for-the-RK3588.patch
new file mode 100644
index 00000000000..272dba7c43d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/220-clk-rockchip-add-clock-controller-for-the-RK3588.patch
@@ -0,0 +1,3517 @@
+From 9a59eacce9db21cc2de1dd7c0267c170ec674f92 Mon Sep 17 00:00:00 2001
+From: Elaine Zhang <zhangqing@rock-chips.com>
+Date: Tue, 18 Oct 2022 17:14:07 +0200
+Subject: [PATCH 220/383] clk: rockchip: add clock controller for the RK3588
+
+Add full clock controller support RK3588.
+
+[rebase, integrate fixes from Wyon and Finley, add missing frequencies
+ to PLL lookup table, update commit message, add GATE_LINK clocks which
+ downstream handles in its own driver with one DT node per clock]
+
+Signed-off-by: Wyon Bi <bivvy.bi@rock-chips.com>
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-10-sebastian.reichel@collabora.com
+[dropped module stuff after talking to Sebastian]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/Kconfig      |    8 +
+ drivers/clk/rockchip/Makefile     |    1 +
+ drivers/clk/rockchip/clk-rk3588.c | 2533 +++++++++++++++++++++++++++++
+ drivers/clk/rockchip/clk.h        |   49 +-
+ drivers/clk/rockchip/rst-rk3588.c |  857 ++++++++++
+ 5 files changed, 3447 insertions(+), 1 deletion(-)
+ create mode 100644 drivers/clk/rockchip/clk-rk3588.c
+ create mode 100644 drivers/clk/rockchip/rst-rk3588.c
+
+--- a/drivers/clk/rockchip/Kconfig
++++ b/drivers/clk/rockchip/Kconfig
+@@ -99,4 +99,12 @@ config CLK_RK3568
+ 	default y
+ 	help
+ 	  Build the driver for RK3568 Clock Driver.
++
++config CLK_RK3588
++	bool "Rockchip RK3588 clock controller support"
++	depends on ARM64 || COMPILE_TEST
++	default y
++	help
++	  Build the driver for RK3588 Clock Driver.
++
+ endif
+--- a/drivers/clk/rockchip/Makefile
++++ b/drivers/clk/rockchip/Makefile
+@@ -28,3 +28,4 @@ obj-$(CONFIG_CLK_RK3328)        += clk-r
+ obj-$(CONFIG_CLK_RK3368)        += clk-rk3368.o
+ obj-$(CONFIG_CLK_RK3399)        += clk-rk3399.o
+ obj-$(CONFIG_CLK_RK3568)	+= clk-rk3568.o
++obj-$(CONFIG_CLK_RK3588)	+= clk-rk3588.o rst-rk3588.o
+--- /dev/null
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -0,0 +1,2533 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ * Author: Elaine Zhang <zhangqing@rock-chips.com>
++ */
++
++#include <linux/clk-provider.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++#include <linux/syscore_ops.h>
++#include <dt-bindings/clock/rockchip,rk3588-cru.h>
++#include "clk.h"
++
++/*
++ * GATE with additional linked clock. Downstream enables the linked clock
++ * (via runtime PM) whenever the gate is enabled. The downstream implementation
++ * does this via separate clock nodes for each of the linked gate clocks,
++ * which leaks parts of the clock tree into DT. It is unclear why this is
++ * actually needed and things work without it for simple use cases. Thus
++ * the linked clock is ignored for now.
++ */
++#define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
++	GATE(_id, cname, pname, f, o, b, gf)
++
++
++#define RK3588_GRF_SOC_STATUS0		0x600
++#define RK3588_PHYREF_ALT_GATE		0xc38
++
++enum rk3588_plls {
++	b0pll, b1pll, lpll, v0pll, aupll, cpll, gpll, npll, ppll,
++};
++
++static struct rockchip_pll_rate_table rk3588_pll_rates[] = {
++	/* _mhz, _p, _m, _s, _k */
++	RK3588_PLL_RATE(2520000000, 2, 210, 0, 0),
++	RK3588_PLL_RATE(2496000000, 2, 208, 0, 0),
++	RK3588_PLL_RATE(2472000000, 2, 206, 0, 0),
++	RK3588_PLL_RATE(2448000000, 2, 204, 0, 0),
++	RK3588_PLL_RATE(2424000000, 2, 202, 0, 0),
++	RK3588_PLL_RATE(2400000000, 2, 200, 0, 0),
++	RK3588_PLL_RATE(2376000000, 2, 198, 0, 0),
++	RK3588_PLL_RATE(2352000000, 2, 196, 0, 0),
++	RK3588_PLL_RATE(2328000000, 2, 194, 0, 0),
++	RK3588_PLL_RATE(2304000000, 2, 192, 0, 0),
++	RK3588_PLL_RATE(2280000000, 2, 190, 0, 0),
++	RK3588_PLL_RATE(2256000000, 2, 376, 1, 0),
++	RK3588_PLL_RATE(2232000000, 2, 372, 1, 0),
++	RK3588_PLL_RATE(2208000000, 2, 368, 1, 0),
++	RK3588_PLL_RATE(2184000000, 2, 364, 1, 0),
++	RK3588_PLL_RATE(2160000000, 2, 360, 1, 0),
++	RK3588_PLL_RATE(2136000000, 2, 356, 1, 0),
++	RK3588_PLL_RATE(2112000000, 2, 352, 1, 0),
++	RK3588_PLL_RATE(2088000000, 2, 348, 1, 0),
++	RK3588_PLL_RATE(2064000000, 2, 344, 1, 0),
++	RK3588_PLL_RATE(2040000000, 2, 340, 1, 0),
++	RK3588_PLL_RATE(2016000000, 2, 336, 1, 0),
++	RK3588_PLL_RATE(1992000000, 2, 332, 1, 0),
++	RK3588_PLL_RATE(1968000000, 2, 328, 1, 0),
++	RK3588_PLL_RATE(1944000000, 2, 324, 1, 0),
++	RK3588_PLL_RATE(1920000000, 2, 320, 1, 0),
++	RK3588_PLL_RATE(1896000000, 2, 316, 1, 0),
++	RK3588_PLL_RATE(1872000000, 2, 312, 1, 0),
++	RK3588_PLL_RATE(1848000000, 2, 308, 1, 0),
++	RK3588_PLL_RATE(1824000000, 2, 304, 1, 0),
++	RK3588_PLL_RATE(1800000000, 2, 300, 1, 0),
++	RK3588_PLL_RATE(1776000000, 2, 296, 1, 0),
++	RK3588_PLL_RATE(1752000000, 2, 292, 1, 0),
++	RK3588_PLL_RATE(1728000000, 2, 288, 1, 0),
++	RK3588_PLL_RATE(1704000000, 2, 284, 1, 0),
++	RK3588_PLL_RATE(1680000000, 2, 280, 1, 0),
++	RK3588_PLL_RATE(1656000000, 2, 276, 1, 0),
++	RK3588_PLL_RATE(1632000000, 2, 272, 1, 0),
++	RK3588_PLL_RATE(1608000000, 2, 268, 1, 0),
++	RK3588_PLL_RATE(1584000000, 2, 264, 1, 0),
++	RK3588_PLL_RATE(1560000000, 2, 260, 1, 0),
++	RK3588_PLL_RATE(1536000000, 2, 256, 1, 0),
++	RK3588_PLL_RATE(1512000000, 2, 252, 1, 0),
++	RK3588_PLL_RATE(1488000000, 2, 248, 1, 0),
++	RK3588_PLL_RATE(1464000000, 2, 244, 1, 0),
++	RK3588_PLL_RATE(1440000000, 2, 240, 1, 0),
++	RK3588_PLL_RATE(1416000000, 2, 236, 1, 0),
++	RK3588_PLL_RATE(1392000000, 2, 232, 1, 0),
++	RK3588_PLL_RATE(1320000000, 2, 220, 1, 0),
++	RK3588_PLL_RATE(1200000000, 2, 200, 1, 0),
++	RK3588_PLL_RATE(1188000000, 2, 198, 1, 0),
++	RK3588_PLL_RATE(1100000000, 3, 550, 2, 0),
++	RK3588_PLL_RATE(1008000000, 2, 336, 2, 0),
++	RK3588_PLL_RATE(1000000000, 3, 500, 2, 0),
++	RK3588_PLL_RATE(983040000, 4, 655, 2, 23592),
++	RK3588_PLL_RATE(955520000, 3, 477, 2, 49806),
++	RK3588_PLL_RATE(903168000, 6, 903, 2, 11009),
++	RK3588_PLL_RATE(900000000, 2, 300, 2, 0),
++	RK3588_PLL_RATE(850000000, 3, 425, 2, 0),
++	RK3588_PLL_RATE(816000000, 2, 272, 2, 0),
++	RK3588_PLL_RATE(786432000, 2, 262, 2, 9437),
++	RK3588_PLL_RATE(786000000, 1, 131, 2, 0),
++	RK3588_PLL_RATE(785560000, 3, 392, 2, 51117),
++	RK3588_PLL_RATE(722534400, 8, 963, 2, 24850),
++	RK3588_PLL_RATE(600000000, 2, 200, 2, 0),
++	RK3588_PLL_RATE(594000000, 2, 198, 2, 0),
++	RK3588_PLL_RATE(408000000, 2, 272, 3, 0),
++	RK3588_PLL_RATE(312000000, 2, 208, 3, 0),
++	RK3588_PLL_RATE(216000000, 2, 288, 4, 0),
++	RK3588_PLL_RATE(100000000, 3, 400, 5, 0),
++	RK3588_PLL_RATE(96000000, 2, 256, 5, 0),
++	{ /* sentinel */ },
++};
++
++#define RK3588_CLK_CORE_B0_SEL_CLEAN_MASK	0x3
++#define RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT	13
++#define RK3588_CLK_CORE_B1_SEL_CLEAN_MASK	0x3
++#define RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT	5
++#define RK3588_CLK_CORE_B0_GPLL_DIV_MASK	0x1f
++#define RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT	1
++#define RK3588_CLK_CORE_L_SEL_CLEAN_MASK	0x3
++#define RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT	12
++#define RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT	5
++#define RK3588_CLK_DSU_SEL_DF_MASK		0x1
++#define RK3588_CLK_DSU_SEL_DF_SHIFT		15
++#define RK3588_CLK_DSU_DF_SRC_MASK		0x3
++#define RK3588_CLK_DSU_DF_SRC_SHIFT		12
++#define RK3588_CLK_DSU_DF_DIV_MASK		0x1f
++#define RK3588_CLK_DSU_DF_DIV_SHIFT		7
++#define RK3588_ACLKM_DSU_DIV_MASK		0x1f
++#define RK3588_ACLKM_DSU_DIV_SHIFT		1
++#define RK3588_ACLKS_DSU_DIV_MASK		0x1f
++#define RK3588_ACLKS_DSU_DIV_SHIFT		6
++#define RK3588_ACLKMP_DSU_DIV_MASK		0x1f
++#define RK3588_ACLKMP_DSU_DIV_SHIFT		11
++#define RK3588_PERIPH_DSU_DIV_MASK		0x1f
++#define RK3588_PERIPH_DSU_DIV_SHIFT		0
++#define RK3588_ATCLK_DSU_DIV_MASK		0x1f
++#define RK3588_ATCLK_DSU_DIV_SHIFT		0
++#define RK3588_GICCLK_DSU_DIV_MASK		0x1f
++#define RK3588_GICCLK_DSU_DIV_SHIFT		5
++
++#define RK3588_CORE_B0_SEL(_apllcore)						\
++{										\
++	.reg = RK3588_BIGCORE0_CLKSEL_CON(0),					\
++	.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK,	\
++			RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) |			\
++		HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK,		\
++			RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT),			\
++}
++
++#define RK3588_CORE_B1_SEL(_apllcore)						\
++{										\
++	.reg = RK3588_BIGCORE0_CLKSEL_CON(1),					\
++	.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK,	\
++			RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT),			\
++}
++
++#define RK3588_CORE_B2_SEL(_apllcore)						\
++{										\
++	.reg = RK3588_BIGCORE1_CLKSEL_CON(0),					\
++	.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B0_SEL_CLEAN_MASK,	\
++			RK3588_CLK_CORE_B0_SEL_CLEAN_SHIFT) |			\
++		HIWORD_UPDATE(0, RK3588_CLK_CORE_B0_GPLL_DIV_MASK,		\
++			RK3588_CLK_CORE_B0_GPLL_DIV_SHIFT),			\
++}
++
++#define RK3588_CORE_B3_SEL(_apllcore)						\
++{										\
++	.reg = RK3588_BIGCORE1_CLKSEL_CON(1),					\
++	.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_B1_SEL_CLEAN_MASK,	\
++			RK3588_CLK_CORE_B1_SEL_CLEAN_SHIFT),			\
++}
++
++#define RK3588_CORE_L_SEL0(_offs, _apllcore)					\
++{										\
++	.reg = RK3588_DSU_CLKSEL_CON(6 + _offs),				\
++	.val = HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK,	\
++			RK3588_CLK_CORE_L0_SEL_CLEAN_SHIFT) |			\
++		HIWORD_UPDATE(_apllcore, RK3588_CLK_CORE_L_SEL_CLEAN_MASK,	\
++			RK3588_CLK_CORE_L1_SEL_CLEAN_SHIFT),			\
++}
++
++#define RK3588_CORE_L_SEL1(_seldsu, _divdsu)				\
++{									\
++	.reg = RK3588_DSU_CLKSEL_CON(0),				\
++	.val = HIWORD_UPDATE(_seldsu, RK3588_CLK_DSU_DF_SRC_MASK,	\
++			RK3588_CLK_DSU_DF_SRC_SHIFT) |			\
++		HIWORD_UPDATE(_divdsu - 1, RK3588_CLK_DSU_DF_DIV_MASK,	\
++			RK3588_CLK_DSU_DF_DIV_SHIFT),			\
++}
++
++#define RK3588_CORE_L_SEL2(_aclkm, _aclkmp, _aclks)			\
++{									\
++	.reg = RK3588_DSU_CLKSEL_CON(1),				\
++	.val = HIWORD_UPDATE(_aclkm - 1, RK3588_ACLKM_DSU_DIV_MASK,	\
++			RK3588_ACLKM_DSU_DIV_SHIFT) |			\
++		HIWORD_UPDATE(_aclkmp - 1, RK3588_ACLKMP_DSU_DIV_MASK,	\
++			RK3588_ACLKMP_DSU_DIV_SHIFT) |			\
++		HIWORD_UPDATE(_aclks - 1, RK3588_ACLKS_DSU_DIV_MASK,	\
++			RK3588_ACLKS_DSU_DIV_SHIFT),			\
++}
++
++#define RK3588_CORE_L_SEL3(_periph)					\
++{									\
++	.reg = RK3588_DSU_CLKSEL_CON(2),				\
++	.val = HIWORD_UPDATE(_periph - 1, RK3588_PERIPH_DSU_DIV_MASK,	\
++			RK3588_PERIPH_DSU_DIV_SHIFT),			\
++}
++
++#define RK3588_CORE_L_SEL4(_gicclk, _atclk)				\
++{									\
++	.reg = RK3588_DSU_CLKSEL_CON(3),				\
++	.val = HIWORD_UPDATE(_gicclk - 1, RK3588_GICCLK_DSU_DIV_MASK,	\
++			RK3588_GICCLK_DSU_DIV_SHIFT) |			\
++		HIWORD_UPDATE(_atclk - 1, RK3588_ATCLK_DSU_DIV_MASK,	\
++			RK3588_ATCLK_DSU_DIV_SHIFT),			\
++}
++
++#define RK3588_CPUB01CLK_RATE(_prate, _apllcore)		\
++{								\
++	.prate = _prate##U,					\
++	.pre_muxs = {						\
++		RK3588_CORE_B0_SEL(0),				\
++		RK3588_CORE_B1_SEL(0),				\
++	},							\
++	.post_muxs = {						\
++		RK3588_CORE_B0_SEL(_apllcore),			\
++		RK3588_CORE_B1_SEL(_apllcore),			\
++	},							\
++}
++
++#define RK3588_CPUB23CLK_RATE(_prate, _apllcore)		\
++{								\
++	.prate = _prate##U,					\
++	.pre_muxs = {						\
++		RK3588_CORE_B2_SEL(0),				\
++		RK3588_CORE_B3_SEL(0),				\
++	},							\
++	.post_muxs = {						\
++		RK3588_CORE_B2_SEL(_apllcore),			\
++		RK3588_CORE_B3_SEL(_apllcore),			\
++	},							\
++}
++
++#define RK3588_CPULCLK_RATE(_prate, _apllcore, _seldsu, _divdsu) \
++{								\
++	.prate = _prate##U,					\
++	.pre_muxs = {						\
++		RK3588_CORE_L_SEL0(0, 0),			\
++		RK3588_CORE_L_SEL0(1, 0),			\
++		RK3588_CORE_L_SEL1(3, 2),			\
++		RK3588_CORE_L_SEL2(2, 3, 3),			\
++		RK3588_CORE_L_SEL3(4),				\
++		RK3588_CORE_L_SEL4(4, 4),			\
++	},							\
++	.post_muxs = {						\
++		RK3588_CORE_L_SEL0(0, _apllcore),		\
++		RK3588_CORE_L_SEL0(1, _apllcore),		\
++		RK3588_CORE_L_SEL1(_seldsu, _divdsu),		\
++	},							\
++}
++
++static struct rockchip_cpuclk_rate_table rk3588_cpub0clk_rates[] __initdata = {
++	RK3588_CPUB01CLK_RATE(2496000000, 1),
++	RK3588_CPUB01CLK_RATE(2400000000, 1),
++	RK3588_CPUB01CLK_RATE(2304000000, 1),
++	RK3588_CPUB01CLK_RATE(2208000000, 1),
++	RK3588_CPUB01CLK_RATE(2184000000, 1),
++	RK3588_CPUB01CLK_RATE(2088000000, 1),
++	RK3588_CPUB01CLK_RATE(2040000000, 1),
++	RK3588_CPUB01CLK_RATE(2016000000, 1),
++	RK3588_CPUB01CLK_RATE(1992000000, 1),
++	RK3588_CPUB01CLK_RATE(1896000000, 1),
++	RK3588_CPUB01CLK_RATE(1800000000, 1),
++	RK3588_CPUB01CLK_RATE(1704000000, 0),
++	RK3588_CPUB01CLK_RATE(1608000000, 0),
++	RK3588_CPUB01CLK_RATE(1584000000, 0),
++	RK3588_CPUB01CLK_RATE(1560000000, 0),
++	RK3588_CPUB01CLK_RATE(1536000000, 0),
++	RK3588_CPUB01CLK_RATE(1512000000, 0),
++	RK3588_CPUB01CLK_RATE(1488000000, 0),
++	RK3588_CPUB01CLK_RATE(1464000000, 0),
++	RK3588_CPUB01CLK_RATE(1440000000, 0),
++	RK3588_CPUB01CLK_RATE(1416000000, 0),
++	RK3588_CPUB01CLK_RATE(1392000000, 0),
++	RK3588_CPUB01CLK_RATE(1368000000, 0),
++	RK3588_CPUB01CLK_RATE(1344000000, 0),
++	RK3588_CPUB01CLK_RATE(1320000000, 0),
++	RK3588_CPUB01CLK_RATE(1296000000, 0),
++	RK3588_CPUB01CLK_RATE(1272000000, 0),
++	RK3588_CPUB01CLK_RATE(1248000000, 0),
++	RK3588_CPUB01CLK_RATE(1224000000, 0),
++	RK3588_CPUB01CLK_RATE(1200000000, 0),
++	RK3588_CPUB01CLK_RATE(1104000000, 0),
++	RK3588_CPUB01CLK_RATE(1008000000, 0),
++	RK3588_CPUB01CLK_RATE(912000000, 0),
++	RK3588_CPUB01CLK_RATE(816000000, 0),
++	RK3588_CPUB01CLK_RATE(696000000, 0),
++	RK3588_CPUB01CLK_RATE(600000000, 0),
++	RK3588_CPUB01CLK_RATE(408000000, 0),
++	RK3588_CPUB01CLK_RATE(312000000, 0),
++	RK3588_CPUB01CLK_RATE(216000000, 0),
++	RK3588_CPUB01CLK_RATE(96000000, 0),
++};
++
++static const struct rockchip_cpuclk_reg_data rk3588_cpub0clk_data = {
++	.core_reg[0] = RK3588_BIGCORE0_CLKSEL_CON(0),
++	.div_core_shift[0] = 8,
++	.div_core_mask[0] = 0x1f,
++	.core_reg[1] = RK3588_BIGCORE0_CLKSEL_CON(1),
++	.div_core_shift[1] = 0,
++	.div_core_mask[1] = 0x1f,
++	.num_cores = 2,
++	.mux_core_alt = 1,
++	.mux_core_main = 2,
++	.mux_core_shift = 6,
++	.mux_core_mask = 0x3,
++};
++
++static struct rockchip_cpuclk_rate_table rk3588_cpub1clk_rates[] __initdata = {
++	RK3588_CPUB23CLK_RATE(2496000000, 1),
++	RK3588_CPUB23CLK_RATE(2400000000, 1),
++	RK3588_CPUB23CLK_RATE(2304000000, 1),
++	RK3588_CPUB23CLK_RATE(2208000000, 1),
++	RK3588_CPUB23CLK_RATE(2184000000, 1),
++	RK3588_CPUB23CLK_RATE(2088000000, 1),
++	RK3588_CPUB23CLK_RATE(2040000000, 1),
++	RK3588_CPUB23CLK_RATE(2016000000, 1),
++	RK3588_CPUB23CLK_RATE(1992000000, 1),
++	RK3588_CPUB23CLK_RATE(1896000000, 1),
++	RK3588_CPUB23CLK_RATE(1800000000, 1),
++	RK3588_CPUB23CLK_RATE(1704000000, 0),
++	RK3588_CPUB23CLK_RATE(1608000000, 0),
++	RK3588_CPUB23CLK_RATE(1584000000, 0),
++	RK3588_CPUB23CLK_RATE(1560000000, 0),
++	RK3588_CPUB23CLK_RATE(1536000000, 0),
++	RK3588_CPUB23CLK_RATE(1512000000, 0),
++	RK3588_CPUB23CLK_RATE(1488000000, 0),
++	RK3588_CPUB23CLK_RATE(1464000000, 0),
++	RK3588_CPUB23CLK_RATE(1440000000, 0),
++	RK3588_CPUB23CLK_RATE(1416000000, 0),
++	RK3588_CPUB23CLK_RATE(1392000000, 0),
++	RK3588_CPUB23CLK_RATE(1368000000, 0),
++	RK3588_CPUB23CLK_RATE(1344000000, 0),
++	RK3588_CPUB23CLK_RATE(1320000000, 0),
++	RK3588_CPUB23CLK_RATE(1296000000, 0),
++	RK3588_CPUB23CLK_RATE(1272000000, 0),
++	RK3588_CPUB23CLK_RATE(1248000000, 0),
++	RK3588_CPUB23CLK_RATE(1224000000, 0),
++	RK3588_CPUB23CLK_RATE(1200000000, 0),
++	RK3588_CPUB23CLK_RATE(1104000000, 0),
++	RK3588_CPUB23CLK_RATE(1008000000, 0),
++	RK3588_CPUB23CLK_RATE(912000000, 0),
++	RK3588_CPUB23CLK_RATE(816000000, 0),
++	RK3588_CPUB23CLK_RATE(696000000, 0),
++	RK3588_CPUB23CLK_RATE(600000000, 0),
++	RK3588_CPUB23CLK_RATE(408000000, 0),
++	RK3588_CPUB23CLK_RATE(312000000, 0),
++	RK3588_CPUB23CLK_RATE(216000000, 0),
++	RK3588_CPUB23CLK_RATE(96000000, 0),
++};
++
++static const struct rockchip_cpuclk_reg_data rk3588_cpub1clk_data = {
++	.core_reg[0] = RK3588_BIGCORE1_CLKSEL_CON(0),
++	.div_core_shift[0] = 8,
++	.div_core_mask[0] = 0x1f,
++	.core_reg[1] = RK3588_BIGCORE1_CLKSEL_CON(1),
++	.div_core_shift[1] = 0,
++	.div_core_mask[1] = 0x1f,
++	.num_cores = 2,
++	.mux_core_alt = 1,
++	.mux_core_main = 2,
++	.mux_core_shift = 6,
++	.mux_core_mask = 0x3,
++};
++
++static struct rockchip_cpuclk_rate_table rk3588_cpulclk_rates[] __initdata = {
++	RK3588_CPULCLK_RATE(2208000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(2184000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(2088000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(2040000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(2016000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(1992000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(1896000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(1800000000, 1, 3, 1),
++	RK3588_CPULCLK_RATE(1704000000, 0, 3, 1),
++	RK3588_CPULCLK_RATE(1608000000, 0, 3, 1),
++	RK3588_CPULCLK_RATE(1584000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1560000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1536000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1512000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1488000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1464000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1440000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1416000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1392000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1368000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1344000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1320000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1296000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1272000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1248000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1224000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1200000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1104000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(1008000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(912000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(816000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(696000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(600000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(408000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(312000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(216000000, 0, 2, 1),
++	RK3588_CPULCLK_RATE(96000000, 0, 2, 1),
++};
++
++static const struct rockchip_cpuclk_reg_data rk3588_cpulclk_data = {
++	.core_reg[0] = RK3588_DSU_CLKSEL_CON(6),
++	.div_core_shift[0] = 0,
++	.div_core_mask[0] = 0x1f,
++	.core_reg[1] = RK3588_DSU_CLKSEL_CON(6),
++	.div_core_shift[1] = 7,
++	.div_core_mask[1] = 0x1f,
++	.core_reg[2] = RK3588_DSU_CLKSEL_CON(7),
++	.div_core_shift[2] = 0,
++	.div_core_mask[2] = 0x1f,
++	.core_reg[3] = RK3588_DSU_CLKSEL_CON(7),
++	.div_core_shift[3] = 7,
++	.div_core_mask[3] = 0x1f,
++	.num_cores = 4,
++	.mux_core_reg = RK3588_DSU_CLKSEL_CON(5),
++	.mux_core_alt = 1,
++	.mux_core_main = 2,
++	.mux_core_shift = 14,
++	.mux_core_mask = 0x3,
++};
++
++PNAME(mux_pll_p)			= { "xin24m", "xin32k" };
++PNAME(mux_armclkl_p)			= { "xin24m", "gpll", "lpll" };
++PNAME(mux_armclkb01_p)			= { "xin24m", "gpll", "b0pll",};
++PNAME(mux_armclkb23_p)			= { "xin24m", "gpll", "b1pll",};
++PNAME(b0pll_b1pll_lpll_gpll_p)		= { "b0pll", "b1pll", "lpll", "gpll" };
++PNAME(gpll_24m_p)			= { "gpll", "xin24m" };
++PNAME(gpll_aupll_p)			= { "gpll", "aupll" };
++PNAME(gpll_lpll_p)			= { "gpll", "lpll" };
++PNAME(gpll_cpll_p)			= { "gpll", "cpll" };
++PNAME(gpll_spll_p)			= { "gpll", "spll" };
++PNAME(gpll_cpll_24m_p)			= { "gpll", "cpll", "xin24m"};
++PNAME(gpll_cpll_aupll_p)		= { "gpll", "cpll", "aupll"};
++PNAME(gpll_cpll_npll_p)			= { "gpll", "cpll", "npll"};
++PNAME(gpll_cpll_npll_v0pll_p)		= { "gpll", "cpll", "npll", "v0pll"};
++PNAME(gpll_cpll_24m_spll_p)		= { "gpll", "cpll", "xin24m", "spll" };
++PNAME(gpll_cpll_aupll_spll_p)		= { "gpll", "cpll", "aupll", "spll" };
++PNAME(gpll_cpll_aupll_npll_p)		= { "gpll", "cpll", "aupll", "npll" };
++PNAME(gpll_cpll_v0pll_aupll_p)		= { "gpll", "cpll", "v0pll", "aupll" };
++PNAME(gpll_cpll_v0pll_spll_p)		= { "gpll", "cpll", "v0pll", "spll" };
++PNAME(gpll_cpll_aupll_npll_spll_p)	= { "gpll", "cpll", "aupll", "npll", "spll" };
++PNAME(gpll_cpll_dmyaupll_npll_spll_p)	= { "gpll", "cpll", "dummy_aupll", "npll", "spll" };
++PNAME(gpll_cpll_npll_aupll_spll_p)	= { "gpll", "cpll", "npll", "aupll", "spll" };
++PNAME(gpll_cpll_npll_1000m_p)		= { "gpll", "cpll", "npll", "clk_1000m_src" };
++PNAME(mux_24m_spll_gpll_cpll_p)		= { "xin24m", "spll", "gpll", "cpll" };
++PNAME(mux_24m_32k_p)			= { "xin24m", "xin32k" };
++PNAME(mux_24m_100m_p)			= { "xin24m", "clk_100m_src" };
++PNAME(mux_200m_100m_p)			= { "clk_200m_src", "clk_100m_src" };
++PNAME(mux_100m_50m_24m_p)		= { "clk_100m_src", "clk_50m_src", "xin24m" };
++PNAME(mux_150m_50m_24m_p)		= { "clk_150m_src", "clk_50m_src", "xin24m" };
++PNAME(mux_150m_100m_24m_p)		= { "clk_150m_src", "clk_100m_src", "xin24m" };
++PNAME(mux_200m_150m_24m_p)		= { "clk_200m_src", "clk_150m_src", "xin24m" };
++PNAME(mux_150m_100m_50m_24m_p)		= { "clk_150m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
++PNAME(mux_200m_100m_50m_24m_p)		= { "clk_200m_src", "clk_100m_src", "clk_50m_src", "xin24m" };
++PNAME(mux_300m_200m_100m_24m_p)		= { "clk_300m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
++PNAME(mux_700m_400m_200m_24m_p)		= { "clk_700m_src", "clk_400m_src", "clk_200m_src", "xin24m" };
++PNAME(mux_500m_250m_100m_24m_p)		= { "clk_500m_src", "clk_250m_src", "clk_100m_src", "xin24m" };
++PNAME(mux_500m_300m_100m_24m_p)		= { "clk_500m_src", "clk_300m_src", "clk_100m_src", "xin24m" };
++PNAME(mux_400m_200m_100m_24m_p)		= { "clk_400m_src", "clk_200m_src", "clk_100m_src", "xin24m" };
++PNAME(clk_i2s2_2ch_p)			= { "clk_i2s2_2ch_src", "clk_i2s2_2ch_frac", "i2s2_mclkin", "xin12m" };
++PNAME(i2s2_2ch_mclkout_p)		= { "mclk_i2s2_2ch", "xin12m" };
++PNAME(clk_i2s3_2ch_p)			= { "clk_i2s3_2ch_src", "clk_i2s3_2ch_frac", "i2s3_mclkin", "xin12m" };
++PNAME(i2s3_2ch_mclkout_p)		= { "mclk_i2s3_2ch", "xin12m" };
++PNAME(clk_i2s0_8ch_tx_p)		= { "clk_i2s0_8ch_tx_src", "clk_i2s0_8ch_tx_frac", "i2s0_mclkin", "xin12m" };
++PNAME(clk_i2s0_8ch_rx_p)		= { "clk_i2s0_8ch_rx_src", "clk_i2s0_8ch_rx_frac", "i2s0_mclkin", "xin12m" };
++PNAME(i2s0_8ch_mclkout_p)		= { "mclk_i2s0_8ch_tx", "mclk_i2s0_8ch_rx", "xin12m" };
++PNAME(clk_i2s1_8ch_tx_p)		= { "clk_i2s1_8ch_tx_src", "clk_i2s1_8ch_tx_frac", "i2s1_mclkin", "xin12m" };
++PNAME(clk_i2s1_8ch_rx_p)		= { "clk_i2s1_8ch_rx_src", "clk_i2s1_8ch_rx_frac", "i2s1_mclkin", "xin12m" };
++PNAME(i2s1_8ch_mclkout_p)		= { "mclk_i2s1_8ch_tx", "mclk_i2s1_8ch_rx", "xin12m" };
++PNAME(clk_i2s4_8ch_tx_p)		= { "clk_i2s4_8ch_tx_src", "clk_i2s4_8ch_tx_frac", "i2s4_mclkin", "xin12m" };
++PNAME(clk_i2s5_8ch_tx_p)		= { "clk_i2s5_8ch_tx_src", "clk_i2s5_8ch_tx_frac", "i2s5_mclkin", "xin12m" };
++PNAME(clk_i2s6_8ch_tx_p)		= { "clk_i2s6_8ch_tx_src", "clk_i2s6_8ch_tx_frac", "i2s6_mclkin", "xin12m" };
++PNAME(clk_i2s6_8ch_rx_p)		= { "clk_i2s6_8ch_rx_src", "clk_i2s6_8ch_rx_frac", "i2s6_mclkin", "xin12m" };
++PNAME(i2s6_8ch_mclkout_p)		= { "mclk_i2s6_8ch_tx", "mclk_i2s6_8ch_rx", "xin12m" };
++PNAME(clk_i2s7_8ch_rx_p)		= { "clk_i2s7_8ch_rx_src", "clk_i2s7_8ch_rx_frac", "i2s7_mclkin", "xin12m" };
++PNAME(clk_i2s8_8ch_tx_p)		= { "clk_i2s8_8ch_tx_src", "clk_i2s8_8ch_tx_frac", "i2s8_mclkin", "xin12m" };
++PNAME(clk_i2s9_8ch_rx_p)		= { "clk_i2s9_8ch_rx_src", "clk_i2s9_8ch_rx_frac", "i2s9_mclkin", "xin12m" };
++PNAME(clk_i2s10_8ch_rx_p)		= { "clk_i2s10_8ch_rx_src", "clk_i2s10_8ch_rx_frac", "i2s10_mclkin", "xin12m" };
++PNAME(clk_spdif0_p)			= { "clk_spdif0_src", "clk_spdif0_frac", "xin12m" };
++PNAME(clk_spdif1_p)			= { "clk_spdif1_src", "clk_spdif1_frac", "xin12m" };
++PNAME(clk_spdif2_dp0_p)			= { "clk_spdif2_dp0_src", "clk_spdif2_dp0_frac", "xin12m" };
++PNAME(clk_spdif3_p)			= { "clk_spdif3_src", "clk_spdif3_frac", "xin12m" };
++PNAME(clk_spdif4_p)			= { "clk_spdif4_src", "clk_spdif4_frac", "xin12m" };
++PNAME(clk_spdif5_dp1_p)			= { "clk_spdif5_dp1_src", "clk_spdif5_dp1_frac", "xin12m" };
++PNAME(clk_uart0_p)			= { "clk_uart0_src", "clk_uart0_frac", "xin24m" };
++PNAME(clk_uart1_p)			= { "clk_uart1_src", "clk_uart1_frac", "xin24m" };
++PNAME(clk_uart2_p)			= { "clk_uart2_src", "clk_uart2_frac", "xin24m" };
++PNAME(clk_uart3_p)			= { "clk_uart3_src", "clk_uart3_frac", "xin24m" };
++PNAME(clk_uart4_p)			= { "clk_uart4_src", "clk_uart4_frac", "xin24m" };
++PNAME(clk_uart5_p)			= { "clk_uart5_src", "clk_uart5_frac", "xin24m" };
++PNAME(clk_uart6_p)			= { "clk_uart6_src", "clk_uart6_frac", "xin24m" };
++PNAME(clk_uart7_p)			= { "clk_uart7_src", "clk_uart7_frac", "xin24m" };
++PNAME(clk_uart8_p)			= { "clk_uart8_src", "clk_uart8_frac", "xin24m" };
++PNAME(clk_uart9_p)			= { "clk_uart9_src", "clk_uart9_frac", "xin24m" };
++PNAME(clk_gmac0_ptp_ref_p)		= { "cpll", "clk_gmac0_ptpref_io" };
++PNAME(clk_gmac1_ptp_ref_p)		= { "cpll", "clk_gmac1_ptpref_io" };
++PNAME(clk_hdmirx_aud_p)			= { "clk_hdmirx_aud_src", "clk_hdmirx_aud_frac" };
++PNAME(aclk_hdcp1_root_p)		= { "gpll", "cpll", "clk_hdmitrx_refsrc" };
++PNAME(aclk_vop_sub_src_p)		= { "aclk_vop_root", "aclk_vop_div2_src" };
++PNAME(dclk_vop0_p)			= { "dclk_vop0_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
++PNAME(dclk_vop1_p)			= { "dclk_vop1_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
++PNAME(dclk_vop2_p)			= { "dclk_vop2_src", "clk_hdmiphy_pixel0", "clk_hdmiphy_pixel1" };
++PNAME(pmu_200m_100m_p)			= { "clk_pmu1_200m_src", "clk_pmu1_100m_src" };
++PNAME(pmu_300m_24m_p)			= { "clk_300m_src", "xin24m" };
++PNAME(pmu_400m_24m_p)			= { "clk_400m_src", "xin24m" };
++PNAME(pmu_100m_50m_24m_src_p)		= { "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
++PNAME(pmu_24m_32k_100m_src_p)		= { "xin24m", "32k", "clk_pmu1_100m_src" };
++PNAME(hclk_pmu1_root_p)			= { "clk_pmu1_200m_src", "clk_pmu1_100m_src", "clk_pmu1_50m_src", "xin24m" };
++PNAME(hclk_pmu_cm0_root_p)		= { "clk_pmu1_400m_src", "clk_pmu1_200m_src", "clk_pmu1_100m_src", "xin24m" };
++PNAME(mclk_pdm0_p)			= { "clk_pmu1_300m_src", "clk_pmu1_200m_src" };
++PNAME(mux_24m_ppll_spll_p)		= { "xin24m", "ppll", "spll" };
++PNAME(mux_24m_ppll_p)			= { "xin24m", "ppll" };
++PNAME(clk_ref_pipe_phy0_p)		= { "clk_ref_pipe_phy0_osc_src", "clk_ref_pipe_phy0_pll_src" };
++PNAME(clk_ref_pipe_phy1_p)		= { "clk_ref_pipe_phy1_osc_src", "clk_ref_pipe_phy1_pll_src" };
++PNAME(clk_ref_pipe_phy2_p)		= { "clk_ref_pipe_phy2_osc_src", "clk_ref_pipe_phy2_pll_src" };
++
++#define MFLAGS CLK_MUX_HIWORD_MASK
++#define DFLAGS CLK_DIVIDER_HIWORD_MASK
++#define GFLAGS (CLK_GATE_HIWORD_MASK | CLK_GATE_SET_TO_DISABLE)
++
++static struct rockchip_clk_branch rk3588_i2s0_8ch_tx_fracmux __initdata =
++	MUX(CLK_I2S0_8CH_TX, "clk_i2s0_8ch_tx", clk_i2s0_8ch_tx_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(26), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s0_8ch_rx_fracmux __initdata =
++	MUX(CLK_I2S0_8CH_RX, "clk_i2s0_8ch_rx", clk_i2s0_8ch_rx_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(28), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s1_8ch_tx_fracmux __initdata =
++	MUX(CLK_I2S1_8CH_TX, "clk_i2s1_8ch_tx", clk_i2s1_8ch_tx_p, CLK_SET_RATE_PARENT,
++			 RK3588_PMU_CLKSEL_CON(7), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s1_8ch_rx_fracmux __initdata =
++	MUX(CLK_I2S1_8CH_RX, "clk_i2s1_8ch_rx", clk_i2s1_8ch_rx_p, CLK_SET_RATE_PARENT,
++			 RK3588_PMU_CLKSEL_CON(9), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s2_2ch_fracmux __initdata =
++	MUX(CLK_I2S2_2CH, "clk_i2s2_2ch", clk_i2s2_2ch_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(30), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s3_2ch_fracmux __initdata =
++	MUX(CLK_I2S3_2CH, "clk_i2s3_2ch", clk_i2s3_2ch_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(32), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s4_8ch_tx_fracmux __initdata =
++	MUX(CLK_I2S4_8CH_TX, "clk_i2s4_8ch_tx", clk_i2s4_8ch_tx_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(120), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s5_8ch_tx_fracmux __initdata =
++	MUX(CLK_I2S5_8CH_TX, "clk_i2s5_8ch_tx", clk_i2s5_8ch_tx_p, CLK_SET_RATE_PARENT,
++			 RK3588_CLKSEL_CON(142), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s6_8ch_tx_fracmux __initdata =
++	MUX(CLK_I2S6_8CH_TX, "clk_i2s6_8ch_tx", clk_i2s6_8ch_tx_p, CLK_SET_RATE_PARENT,
++			 RK3588_CLKSEL_CON(146), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s6_8ch_rx_fracmux __initdata =
++	MUX(CLK_I2S6_8CH_RX, "clk_i2s6_8ch_rx", clk_i2s6_8ch_rx_p, CLK_SET_RATE_PARENT,
++			 RK3588_CLKSEL_CON(148), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s7_8ch_rx_fracmux __initdata =
++	MUX(CLK_I2S7_8CH_RX, "clk_i2s7_8ch_rx", clk_i2s7_8ch_rx_p, CLK_SET_RATE_PARENT,
++			 RK3588_CLKSEL_CON(131), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s8_8ch_tx_fracmux __initdata =
++	MUX(CLK_I2S8_8CH_TX, "clk_i2s8_8ch_tx", clk_i2s8_8ch_tx_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(122), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s9_8ch_rx_fracmux __initdata =
++	MUX(CLK_I2S9_8CH_RX, "clk_i2s9_8ch_rx", clk_i2s9_8ch_rx_p, CLK_SET_RATE_PARENT,
++			 RK3588_CLKSEL_CON(155), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_i2s10_8ch_rx_fracmux __initdata =
++	MUX(CLK_I2S10_8CH_RX, "clk_i2s10_8ch_rx", clk_i2s10_8ch_rx_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(157), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_spdif0_fracmux __initdata =
++	MUX(CLK_SPDIF0, "clk_spdif0", clk_spdif0_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(34), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_spdif1_fracmux __initdata =
++	MUX(CLK_SPDIF1, "clk_spdif1", clk_spdif1_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(36), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_spdif2_dp0_fracmux __initdata =
++	MUX(CLK_SPDIF2_DP0, "clk_spdif2_dp0", clk_spdif2_dp0_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(124), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_spdif3_fracmux __initdata =
++	MUX(CLK_SPDIF3, "clk_spdif3", clk_spdif3_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(150), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_spdif4_fracmux __initdata =
++	MUX(CLK_SPDIF4, "clk_spdif4", clk_spdif4_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(152), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_spdif5_dp1_fracmux __initdata =
++	MUX(CLK_SPDIF5_DP1, "clk_spdif5_dp1", clk_spdif5_dp1_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(126), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart0_fracmux __initdata =
++	MUX(CLK_UART0, "clk_uart0", clk_uart0_p, CLK_SET_RATE_PARENT,
++			RK3588_PMU_CLKSEL_CON(5), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart1_fracmux __initdata =
++	MUX(CLK_UART1, "clk_uart1", clk_uart1_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(43), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart2_fracmux __initdata =
++	MUX(CLK_UART2, "clk_uart2", clk_uart2_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(45), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart3_fracmux __initdata =
++	MUX(CLK_UART3, "clk_uart3", clk_uart3_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(47), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart4_fracmux __initdata =
++	MUX(CLK_UART4, "clk_uart4", clk_uart4_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(49), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart5_fracmux __initdata =
++	MUX(CLK_UART5, "clk_uart5", clk_uart5_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(51), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart6_fracmux __initdata =
++	MUX(CLK_UART6, "clk_uart6", clk_uart6_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(53), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart7_fracmux __initdata =
++	MUX(CLK_UART7, "clk_uart7", clk_uart7_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(55), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart8_fracmux __initdata =
++	MUX(CLK_UART8, "clk_uart8", clk_uart8_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(57), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_uart9_fracmux __initdata =
++	MUX(CLK_UART9, "clk_uart9", clk_uart9_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(59), 0, 2, MFLAGS);
++
++static struct rockchip_clk_branch rk3588_hdmirx_aud_fracmux __initdata =
++	MUX(CLK_HDMIRX_AUD_P_MUX, "clk_hdmirx_aud_mux", clk_hdmirx_aud_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(140), 0, 1, MFLAGS);
++
++static struct rockchip_pll_clock rk3588_pll_clks[] __initdata = {
++	[b0pll] = PLL(pll_rk3588_core, PLL_B0PLL, "b0pll", mux_pll_p,
++		     CLK_IGNORE_UNUSED, RK3588_B0_PLL_CON(0),
++		     RK3588_B0_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
++	[b1pll] = PLL(pll_rk3588_core, PLL_B1PLL, "b1pll", mux_pll_p,
++		     CLK_IGNORE_UNUSED, RK3588_B1_PLL_CON(8),
++		     RK3588_B1_PLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
++	[lpll] = PLL(pll_rk3588_core, PLL_LPLL, "lpll", mux_pll_p,
++		     CLK_IGNORE_UNUSED, RK3588_LPLL_CON(16),
++		     RK3588_LPLL_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
++	[v0pll] = PLL(pll_rk3588, PLL_V0PLL, "v0pll", mux_pll_p,
++		     0, RK3588_PLL_CON(88),
++		     RK3588_MODE_CON0, 4, 15, 0, rk3588_pll_rates),
++	[aupll] = PLL(pll_rk3588, PLL_AUPLL, "aupll", mux_pll_p,
++		     0, RK3588_PLL_CON(96),
++		     RK3588_MODE_CON0, 6, 15, 0, rk3588_pll_rates),
++	[cpll] = PLL(pll_rk3588, PLL_CPLL, "cpll", mux_pll_p,
++		     CLK_IGNORE_UNUSED, RK3588_PLL_CON(104),
++		     RK3588_MODE_CON0, 8, 15, 0, rk3588_pll_rates),
++	[gpll] = PLL(pll_rk3588, PLL_GPLL, "gpll", mux_pll_p,
++		     CLK_IGNORE_UNUSED, RK3588_PLL_CON(112),
++		     RK3588_MODE_CON0, 2, 15, 0, rk3588_pll_rates),
++	[npll] = PLL(pll_rk3588, PLL_NPLL, "npll", mux_pll_p,
++		     0, RK3588_PLL_CON(120),
++		     RK3588_MODE_CON0, 0, 15, 0, rk3588_pll_rates),
++	[ppll] = PLL(pll_rk3588_core, PLL_PPLL, "ppll", mux_pll_p,
++		     CLK_IGNORE_UNUSED, RK3588_PMU_PLL_CON(128),
++		     RK3588_MODE_CON0, 10, 15, 0, rk3588_pll_rates),
++};
++
++static struct rockchip_clk_branch rk3588_clk_branches[] __initdata = {
++	/*
++	 * CRU Clock-Architecture
++	 */
++	/* fixed */
++	FACTOR(0, "xin12m", "xin24m", 0, 1, 2),
++
++	/* top */
++	COMPOSITE(CLK_50M_SRC, "clk_50m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(0), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 0, GFLAGS),
++	COMPOSITE(CLK_100M_SRC, "clk_100m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(0), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 1, GFLAGS),
++	COMPOSITE(CLK_150M_SRC, "clk_150m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 2, GFLAGS),
++	COMPOSITE(CLK_200M_SRC, "clk_200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(1), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 3, GFLAGS),
++	COMPOSITE(CLK_250M_SRC, "clk_250m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 4, GFLAGS),
++	COMPOSITE(CLK_300M_SRC, "clk_300m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(2), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 5, GFLAGS),
++	COMPOSITE(CLK_350M_SRC, "clk_350m_src", gpll_spll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(3), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 6, GFLAGS),
++	COMPOSITE(CLK_400M_SRC, "clk_400m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(3), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 7, GFLAGS),
++	COMPOSITE_HALFDIV(CLK_450M_SRC, "clk_450m_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(4), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 8, GFLAGS),
++	COMPOSITE(CLK_500M_SRC, "clk_500m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(4), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 9, GFLAGS),
++	COMPOSITE(CLK_600M_SRC, "clk_600m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(5), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 10, GFLAGS),
++	COMPOSITE(CLK_650M_SRC, "clk_650m_src", gpll_lpll_p, 0,
++			RK3588_CLKSEL_CON(5), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 11, GFLAGS),
++	COMPOSITE(CLK_700M_SRC, "clk_700m_src", gpll_spll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(6), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 12, GFLAGS),
++	COMPOSITE(CLK_800M_SRC, "clk_800m_src", gpll_aupll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(6), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 13, GFLAGS),
++	COMPOSITE_HALFDIV(CLK_1000M_SRC, "clk_1000m_src", gpll_cpll_npll_v0pll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(7), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 14, GFLAGS),
++	COMPOSITE(CLK_1200M_SRC, "clk_1200m_src", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(7), 12, 1, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(0), 15, GFLAGS),
++	COMPOSITE_NODIV(ACLK_TOP_M300_ROOT, "aclk_top_m300_root", mux_300m_200m_100m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(9), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(1), 10, GFLAGS),
++	COMPOSITE_NODIV(ACLK_TOP_M500_ROOT, "aclk_top_m500_root", mux_500m_300m_100m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(9), 2, 2, MFLAGS,
++			RK3588_CLKGATE_CON(1), 11, GFLAGS),
++	COMPOSITE_NODIV(ACLK_TOP_M400_ROOT, "aclk_top_m400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(9), 4, 2, MFLAGS,
++			RK3588_CLKGATE_CON(1), 12, GFLAGS),
++	COMPOSITE_NODIV(ACLK_TOP_S200_ROOT, "aclk_top_s200_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(9), 6, 2, MFLAGS,
++			RK3588_CLKGATE_CON(1), 13, GFLAGS),
++	COMPOSITE_NODIV(ACLK_TOP_S400_ROOT, "aclk_top_s400_root", mux_400m_200m_100m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(9), 8, 2, MFLAGS,
++			RK3588_CLKGATE_CON(1), 14, GFLAGS),
++	COMPOSITE(ACLK_TOP_ROOT, "aclk_top_root", gpll_cpll_aupll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(8), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(1), 0, GFLAGS),
++	COMPOSITE_NODIV(PCLK_TOP_ROOT, "pclk_top_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(8), 7, 2, MFLAGS,
++			RK3588_CLKGATE_CON(1), 1, GFLAGS),
++	COMPOSITE(ACLK_LOW_TOP_ROOT, "aclk_low_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(8), 14, 1, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(1), 2, GFLAGS),
++	COMPOSITE(CLK_MIPI_CAMARAOUT_M0, "clk_mipi_camaraout_m0", mux_24m_spll_gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(18), 8, 2, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(5), 9, GFLAGS),
++	COMPOSITE(CLK_MIPI_CAMARAOUT_M1, "clk_mipi_camaraout_m1", mux_24m_spll_gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(19), 8, 2, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(5), 10, GFLAGS),
++	COMPOSITE(CLK_MIPI_CAMARAOUT_M2, "clk_mipi_camaraout_m2", mux_24m_spll_gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(20), 8, 2, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(5), 11, GFLAGS),
++	COMPOSITE(CLK_MIPI_CAMARAOUT_M3, "clk_mipi_camaraout_m3", mux_24m_spll_gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(21), 8, 2, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(5), 12, GFLAGS),
++	COMPOSITE(CLK_MIPI_CAMARAOUT_M4, "clk_mipi_camaraout_m4", mux_24m_spll_gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(22), 8, 2, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(5), 13, GFLAGS),
++	COMPOSITE(MCLK_GMAC0_OUT, "mclk_gmac0_out", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(15), 7, 1, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(5), 3, GFLAGS),
++	COMPOSITE(REFCLKO25M_ETH0_OUT, "refclko25m_eth0_out", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(15), 15, 1, MFLAGS, 8, 7, DFLAGS,
++			RK3588_CLKGATE_CON(5), 4, GFLAGS),
++	COMPOSITE(REFCLKO25M_ETH1_OUT, "refclko25m_eth1_out", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(16), 7, 1, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(5), 5, GFLAGS),
++	COMPOSITE(CLK_CIFOUT_OUT, "clk_cifout_out", gpll_cpll_24m_spll_p, 0,
++			RK3588_CLKSEL_CON(17), 8, 2, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(5), 6, GFLAGS),
++	GATE(PCLK_MIPI_DCPHY0, "pclk_mipi_dcphy0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(3), 14, GFLAGS),
++	GATE(PCLK_MIPI_DCPHY1, "pclk_mipi_dcphy1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(4), 3, GFLAGS),
++	GATE(PCLK_CSIPHY0, "pclk_csiphy0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(1), 6, GFLAGS),
++	GATE(PCLK_CSIPHY1, "pclk_csiphy1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(1), 8, GFLAGS),
++	GATE(PCLK_CRU, "pclk_cru", "pclk_top_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(5), 0, GFLAGS),
++
++	/* bigcore0 */
++	COMPOSITE_NODIV(PCLK_BIGCORE0_ROOT, "pclk_bigcore0_root", mux_100m_50m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_BIGCORE0_CLKSEL_CON(2), 0, 2, MFLAGS,
++			RK3588_BIGCORE0_CLKGATE_CON(0), 14, GFLAGS),
++	GATE(PCLK_BIGCORE0_PVTM, "pclk_bigcore0_pvtm", "pclk_bigcore0_root", 0,
++			RK3588_BIGCORE0_CLKGATE_CON(1), 0, GFLAGS),
++	GATE(CLK_BIGCORE0_PVTM, "clk_bigcore0_pvtm", "xin24m", 0,
++			RK3588_BIGCORE0_CLKGATE_CON(0), 12, GFLAGS),
++	GATE(CLK_CORE_BIGCORE0_PVTM, "clk_core_bigcore0_pvtm", "armclk_b01", 0,
++			RK3588_BIGCORE0_CLKGATE_CON(0), 13, GFLAGS),
++
++	/* bigcore1 */
++	COMPOSITE_NODIV(PCLK_BIGCORE1_ROOT, "pclk_bigcore1_root", mux_100m_50m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_BIGCORE1_CLKSEL_CON(2), 0, 2, MFLAGS,
++			RK3588_BIGCORE1_CLKGATE_CON(0), 14, GFLAGS),
++	GATE(PCLK_BIGCORE1_PVTM, "pclk_bigcore1_pvtm", "pclk_bigcore1_root", 0,
++			RK3588_BIGCORE1_CLKGATE_CON(1), 0, GFLAGS),
++	GATE(CLK_BIGCORE1_PVTM, "clk_bigcore1_pvtm", "xin24m", 0,
++			RK3588_BIGCORE1_CLKGATE_CON(0), 12, GFLAGS),
++	GATE(CLK_CORE_BIGCORE1_PVTM, "clk_core_bigcore1_pvtm", "armclk_b23", 0,
++			RK3588_BIGCORE1_CLKGATE_CON(0), 13, GFLAGS),
++
++	/* dsu */
++	COMPOSITE(0, "sclk_dsu", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(0), 12, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_DSU_CLKGATE_CON(0), 4, GFLAGS),
++	COMPOSITE_NOMUX(0, "atclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(3), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(1), 0, GFLAGS),
++	COMPOSITE_NOMUX(0, "gicclk_dsu", "sclk_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(3), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(1), 1, GFLAGS),
++	COMPOSITE_NOMUX(0, "aclkmp_dsu", "sclk_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(1), 11, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(0), 12, GFLAGS),
++	COMPOSITE_NOMUX(0, "aclkm_dsu", "sclk_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(1), 1, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(0), 8, GFLAGS),
++	COMPOSITE_NOMUX(0, "aclks_dsu", "sclk_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(1), 6, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(0), 9, GFLAGS),
++	COMPOSITE_NOMUX(0, "periph_dsu", "sclk_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(2), 0, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(0), 13, GFLAGS),
++	COMPOSITE_NOMUX(0, "cntclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(2), 5, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(0), 14, GFLAGS),
++	COMPOSITE_NOMUX(0, "tsclk_dsu", "periph_dsu", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(2), 10, 5, DFLAGS | CLK_DIVIDER_READ_ONLY,
++			RK3588_DSU_CLKGATE_CON(0), 15, GFLAGS),
++	COMPOSITE_NODIV(PCLK_DSU_S_ROOT, "pclk_dsu_s_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(4), 11, 2, MFLAGS,
++			RK3588_DSU_CLKGATE_CON(2), 2, GFLAGS),
++	COMPOSITE(PCLK_DSU_ROOT, "pclk_dsu_root", b0pll_b1pll_lpll_gpll_p, CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(4), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_DSU_CLKGATE_CON(1), 3, GFLAGS),
++	COMPOSITE_NODIV(PCLK_DSU_NS_ROOT, "pclk_dsu_ns_root", mux_100m_50m_24m_p, CLK_IS_CRITICAL,
++			RK3588_DSU_CLKSEL_CON(4), 7, 2, MFLAGS,
++			RK3588_DSU_CLKGATE_CON(1), 4, GFLAGS),
++	GATE(PCLK_LITCORE_PVTM, "pclk_litcore_pvtm", "pclk_dsu_ns_root", 0,
++			RK3588_DSU_CLKGATE_CON(2), 6, GFLAGS),
++	GATE(PCLK_DBG, "pclk_dbg", "pclk_dsu_root", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKGATE_CON(1), 7, GFLAGS),
++	GATE(PCLK_DSU, "pclk_dsu", "pclk_dsu_root", CLK_IS_CRITICAL,
++			RK3588_DSU_CLKGATE_CON(1), 6, GFLAGS),
++	GATE(PCLK_S_DAPLITE, "pclk_s_daplite", "pclk_dsu_ns_root", CLK_IGNORE_UNUSED,
++			RK3588_DSU_CLKGATE_CON(1), 8, GFLAGS),
++	GATE(PCLK_M_DAPLITE, "pclk_m_daplite", "pclk_dsu_root", CLK_IGNORE_UNUSED,
++			RK3588_DSU_CLKGATE_CON(1), 9, GFLAGS),
++	GATE(CLK_LITCORE_PVTM, "clk_litcore_pvtm", "xin24m", 0,
++			RK3588_DSU_CLKGATE_CON(2), 0, GFLAGS),
++	GATE(CLK_CORE_LITCORE_PVTM, "clk_core_litcore_pvtm", "armclk_l", 0,
++			RK3588_DSU_CLKGATE_CON(2), 1, GFLAGS),
++
++	/* audio */
++	COMPOSITE_NODIV(HCLK_AUDIO_ROOT, "hclk_audio_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(24), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(7), 0, GFLAGS),
++	COMPOSITE_NODIV(PCLK_AUDIO_ROOT, "pclk_audio_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(24), 2, 2, MFLAGS,
++			RK3588_CLKGATE_CON(7), 1, GFLAGS),
++	GATE(HCLK_I2S2_2CH, "hclk_i2s2_2ch", "hclk_audio_root", 0,
++			RK3588_CLKGATE_CON(7), 12, GFLAGS),
++	GATE(HCLK_I2S3_2CH, "hclk_i2s3_2ch", "hclk_audio_root", 0,
++			RK3588_CLKGATE_CON(7), 13, GFLAGS),
++	COMPOSITE(CLK_I2S2_2CH_SRC, "clk_i2s2_2ch_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(28), 9, 1, MFLAGS, 4, 5, DFLAGS,
++			RK3588_CLKGATE_CON(7), 14, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S2_2CH_FRAC, "clk_i2s2_2ch_frac", "clk_i2s2_2ch_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(29), 0,
++			RK3588_CLKGATE_CON(7), 15, GFLAGS,
++			&rk3588_i2s2_2ch_fracmux),
++	GATE(MCLK_I2S2_2CH, "mclk_i2s2_2ch", "clk_i2s2_2ch", 0,
++			RK3588_CLKGATE_CON(8), 0, GFLAGS),
++	MUX(I2S2_2CH_MCLKOUT, "i2s2_2ch_mclkout", i2s2_2ch_mclkout_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(30), 2, 1, MFLAGS),
++
++	COMPOSITE(CLK_I2S3_2CH_SRC, "clk_i2s3_2ch_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(30), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(8), 1, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S3_2CH_FRAC, "clk_i2s3_2ch_frac", "clk_i2s3_2ch_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(31), 0,
++			RK3588_CLKGATE_CON(8), 2, GFLAGS,
++			&rk3588_i2s3_2ch_fracmux),
++	GATE(MCLK_I2S3_2CH, "mclk_i2s3_2ch", "clk_i2s3_2ch", 0,
++			RK3588_CLKGATE_CON(8), 3, GFLAGS),
++	GATE(CLK_DAC_ACDCDIG, "clk_dac_acdcdig", "mclk_i2s3_2ch", 0,
++			RK3588_CLKGATE_CON(8), 4, GFLAGS),
++	MUX(I2S3_2CH_MCLKOUT, "i2s3_2ch_mclkout", i2s3_2ch_mclkout_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(32), 2, 1, MFLAGS),
++	GATE(PCLK_ACDCDIG, "pclk_acdcdig", "pclk_audio_root", 0,
++			RK3588_CLKGATE_CON(7), 11, GFLAGS),
++	GATE(HCLK_I2S0_8CH, "hclk_i2s0_8ch", "hclk_audio_root", 0,
++			RK3588_CLKGATE_CON(7), 4, GFLAGS),
++
++	COMPOSITE(CLK_I2S0_8CH_TX_SRC, "clk_i2s0_8ch_tx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(24), 9, 1, MFLAGS, 4, 5, DFLAGS,
++			RK3588_CLKGATE_CON(7), 5, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S0_8CH_TX_FRAC, "clk_i2s0_8ch_tx_frac", "clk_i2s0_8ch_tx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(25), 0,
++			RK3588_CLKGATE_CON(7), 6, GFLAGS,
++			&rk3588_i2s0_8ch_tx_fracmux),
++	GATE(MCLK_I2S0_8CH_TX, "mclk_i2s0_8ch_tx", "clk_i2s0_8ch_tx", 0,
++			RK3588_CLKGATE_CON(7), 7, GFLAGS),
++
++	COMPOSITE(CLK_I2S0_8CH_RX_SRC, "clk_i2s0_8ch_rx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(26), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(7), 8, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S0_8CH_RX_FRAC, "clk_i2s0_8ch_rx_frac", "clk_i2s0_8ch_rx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(27), 0,
++			RK3588_CLKGATE_CON(7), 9, GFLAGS,
++			&rk3588_i2s0_8ch_rx_fracmux),
++	GATE(MCLK_I2S0_8CH_RX, "mclk_i2s0_8ch_rx", "clk_i2s0_8ch_rx", 0,
++			RK3588_CLKGATE_CON(7), 10, GFLAGS),
++	MUX(I2S0_8CH_MCLKOUT, "i2s0_8ch_mclkout", i2s0_8ch_mclkout_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(28), 2, 2, MFLAGS),
++
++	GATE(HCLK_PDM1, "hclk_pdm1", "hclk_audio_root", 0,
++			RK3588_CLKGATE_CON(9), 6, GFLAGS),
++	COMPOSITE(MCLK_PDM1, "mclk_pdm1", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(36), 7, 2, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(9), 7, GFLAGS),
++
++	GATE(HCLK_SPDIF0, "hclk_spdif0", "hclk_audio_root", 0,
++			RK3588_CLKGATE_CON(8), 14, GFLAGS),
++	COMPOSITE(CLK_SPDIF0_SRC, "clk_spdif0_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(32), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(8), 15, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_SPDIF0_FRAC, "clk_spdif0_frac", "clk_spdif0_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(33), 0,
++			RK3588_CLKGATE_CON(9), 0, GFLAGS,
++			&rk3588_spdif0_fracmux),
++	GATE(MCLK_SPDIF0, "mclk_spdif0", "clk_spdif0", 0,
++			RK3588_CLKGATE_CON(9), 1, GFLAGS),
++
++	GATE(HCLK_SPDIF1, "hclk_spdif1", "hclk_audio_root", 0,
++			RK3588_CLKGATE_CON(9), 2, GFLAGS),
++	COMPOSITE(CLK_SPDIF1_SRC, "clk_spdif1_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(34), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(9), 3, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_SPDIF1_FRAC, "clk_spdif1_frac", "clk_spdif1_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(35), 0,
++			RK3588_CLKGATE_CON(9), 4, GFLAGS,
++			&rk3588_spdif1_fracmux),
++	GATE(MCLK_SPDIF1, "mclk_spdif1", "clk_spdif1", 0,
++			RK3588_CLKGATE_CON(9), 5, GFLAGS),
++
++	COMPOSITE(ACLK_AV1_ROOT, "aclk_av1_root", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(163), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(68), 0, GFLAGS),
++	COMPOSITE_NODIV(PCLK_AV1_ROOT, "pclk_av1_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(163), 7, 2, MFLAGS,
++			RK3588_CLKGATE_CON(68), 3, GFLAGS),
++
++	/* bus */
++	COMPOSITE(ACLK_BUS_ROOT, "aclk_bus_root", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(38), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(10), 0, GFLAGS),
++
++	GATE(PCLK_MAILBOX0, "pclk_mailbox0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(16), 11, GFLAGS),
++	GATE(PCLK_MAILBOX1, "pclk_mailbox1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(16), 12, GFLAGS),
++	GATE(PCLK_MAILBOX2, "pclk_mailbox2", "pclk_top_root", 0,
++		RK3588_CLKGATE_CON(16), 13, GFLAGS),
++	GATE(PCLK_PMU2, "pclk_pmu2", "pclk_top_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(19), 3, GFLAGS),
++	GATE(PCLK_PMUCM0_INTMUX, "pclk_pmucm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(19), 4, GFLAGS),
++	GATE(PCLK_DDRCM0_INTMUX, "pclk_ddrcm0_intmux", "pclk_top_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(19), 5, GFLAGS),
++
++	GATE(PCLK_PWM1, "pclk_pwm1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(15), 3, GFLAGS),
++	COMPOSITE_NODIV(CLK_PWM1, "clk_pwm1", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 12, 2, MFLAGS,
++			RK3588_CLKGATE_CON(15), 4, GFLAGS),
++	GATE(CLK_PWM1_CAPTURE, "clk_pwm1_capture", "xin24m", 0,
++			RK3588_CLKGATE_CON(15), 5, GFLAGS),
++	GATE(PCLK_PWM2, "pclk_pwm2", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(15), 6, GFLAGS),
++	COMPOSITE_NODIV(CLK_PWM2, "clk_pwm2", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 14, 2, MFLAGS,
++			RK3588_CLKGATE_CON(15), 7, GFLAGS),
++	GATE(CLK_PWM2_CAPTURE, "clk_pwm2_capture", "xin24m", 0,
++			RK3588_CLKGATE_CON(15), 8, GFLAGS),
++	GATE(PCLK_PWM3, "pclk_pwm3", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(15), 9, GFLAGS),
++	COMPOSITE_NODIV(CLK_PWM3, "clk_pwm3", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(60), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(15), 10, GFLAGS),
++	GATE(CLK_PWM3_CAPTURE, "clk_pwm3_capture", "xin24m", 0,
++			RK3588_CLKGATE_CON(15), 11, GFLAGS),
++
++	GATE(PCLK_BUSTIMER0, "pclk_bustimer0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(15), 12, GFLAGS),
++	GATE(PCLK_BUSTIMER1, "pclk_bustimer1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(15), 13, GFLAGS),
++	COMPOSITE_NODIV(CLK_BUS_TIMER_ROOT, "clk_bus_timer_root", mux_24m_100m_p, 0,
++			RK3588_CLKSEL_CON(60), 2, 1, MFLAGS,
++			RK3588_CLKGATE_CON(15), 14, GFLAGS),
++	GATE(CLK_BUSTIMER0, "clk_bustimer0", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(15), 15, GFLAGS),
++	GATE(CLK_BUSTIMER1, "clk_bustimer1", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 0, GFLAGS),
++	GATE(CLK_BUSTIMER2, "clk_bustimer2", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 1, GFLAGS),
++	GATE(CLK_BUSTIMER3, "clk_bustimer3", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 2, GFLAGS),
++	GATE(CLK_BUSTIMER4, "clk_bustimer4", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 3, GFLAGS),
++	GATE(CLK_BUSTIMER5, "clk_bustimer5", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 4, GFLAGS),
++	GATE(CLK_BUSTIMER6, "clk_bustimer6", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 5, GFLAGS),
++	GATE(CLK_BUSTIMER7, "clk_bustimer7", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 6, GFLAGS),
++	GATE(CLK_BUSTIMER8, "clk_bustimer8", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 7, GFLAGS),
++	GATE(CLK_BUSTIMER9, "clk_bustimer9", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 8, GFLAGS),
++	GATE(CLK_BUSTIMER10, "clk_bustimer10", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 9, GFLAGS),
++	GATE(CLK_BUSTIMER11, "clk_bustimer11", "clk_bus_timer_root", 0,
++			RK3588_CLKGATE_CON(16), 10, GFLAGS),
++
++	GATE(PCLK_WDT0, "pclk_wdt0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(15), 0, GFLAGS),
++	GATE(TCLK_WDT0, "tclk_wdt0", "xin24m", 0,
++			RK3588_CLKGATE_CON(15), 1, GFLAGS),
++
++	GATE(PCLK_CAN0, "pclk_can0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(11), 8, GFLAGS),
++	COMPOSITE(CLK_CAN0, "clk_can0", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(39), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(11), 9, GFLAGS),
++	GATE(PCLK_CAN1, "pclk_can1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(11), 10, GFLAGS),
++	COMPOSITE(CLK_CAN1, "clk_can1", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(39), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(11), 11, GFLAGS),
++	GATE(PCLK_CAN2, "pclk_can2", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(11), 12, GFLAGS),
++	COMPOSITE(CLK_CAN2, "clk_can2", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(40), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(11), 13, GFLAGS),
++
++	GATE(ACLK_DECOM, "aclk_decom", "aclk_bus_root", 0,
++			RK3588_CLKGATE_CON(17), 6, GFLAGS),
++	GATE(PCLK_DECOM, "pclk_decom", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(17), 7, GFLAGS),
++	COMPOSITE(DCLK_DECOM, "dclk_decom", gpll_spll_p, 0,
++			RK3588_CLKSEL_CON(62), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(17), 8, GFLAGS),
++	GATE(ACLK_DMAC0, "aclk_dmac0", "aclk_bus_root", 0,
++			RK3588_CLKGATE_CON(10), 5, GFLAGS),
++	GATE(ACLK_DMAC1, "aclk_dmac1", "aclk_bus_root", 0,
++			RK3588_CLKGATE_CON(10), 6, GFLAGS),
++	GATE(ACLK_DMAC2, "aclk_dmac2", "aclk_bus_root", 0,
++			RK3588_CLKGATE_CON(10), 7, GFLAGS),
++	GATE(ACLK_GIC, "aclk_gic", "aclk_bus_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(10), 3, GFLAGS),
++
++	GATE(PCLK_GPIO1, "pclk_gpio1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(16), 14, GFLAGS),
++	COMPOSITE(DBCLK_GPIO1, "dbclk_gpio1", mux_24m_32k_p, 0,
++			RK3588_CLKSEL_CON(60), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(16), 15, GFLAGS),
++	GATE(PCLK_GPIO2, "pclk_gpio2", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(17), 0, GFLAGS),
++	COMPOSITE(DBCLK_GPIO2, "dbclk_gpio2", mux_24m_32k_p, 0,
++			RK3588_CLKSEL_CON(60), 14, 1, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(17), 1, GFLAGS),
++	GATE(PCLK_GPIO3, "pclk_gpio3", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(17), 2, GFLAGS),
++	COMPOSITE(DBCLK_GPIO3, "dbclk_gpio3", mux_24m_32k_p, 0,
++			RK3588_CLKSEL_CON(61), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(17), 3, GFLAGS),
++	GATE(PCLK_GPIO4, "pclk_gpio4", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(17), 4, GFLAGS),
++	COMPOSITE(DBCLK_GPIO4, "dbclk_gpio4", mux_24m_32k_p, 0,
++			RK3588_CLKSEL_CON(61), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(17), 5, GFLAGS),
++
++	GATE(PCLK_I2C1, "pclk_i2c1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 8, GFLAGS),
++	GATE(PCLK_I2C2, "pclk_i2c2", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 9, GFLAGS),
++	GATE(PCLK_I2C3, "pclk_i2c3", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 10, GFLAGS),
++	GATE(PCLK_I2C4, "pclk_i2c4", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 11, GFLAGS),
++	GATE(PCLK_I2C5, "pclk_i2c5", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 12, GFLAGS),
++	GATE(PCLK_I2C6, "pclk_i2c6", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 13, GFLAGS),
++	GATE(PCLK_I2C7, "pclk_i2c7", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 14, GFLAGS),
++	GATE(PCLK_I2C8, "pclk_i2c8", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(10), 15, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C1, "clk_i2c1", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 6, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 0, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C2, "clk_i2c2", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 7, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 1, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C3, "clk_i2c3", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 8, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 2, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C4, "clk_i2c4", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 9, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 3, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C5, "clk_i2c5", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 10, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 4, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C6, "clk_i2c6", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 11, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 5, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C7, "clk_i2c7", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 12, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 6, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C8, "clk_i2c8", mux_200m_100m_p, 0,
++			RK3588_CLKSEL_CON(38), 13, 1, MFLAGS,
++			RK3588_CLKGATE_CON(11), 7, GFLAGS),
++
++	GATE(PCLK_OTPC_NS, "pclk_otpc_ns", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(18), 9, GFLAGS),
++	GATE(CLK_OTPC_NS, "clk_otpc_ns", "xin24m", 0,
++			RK3588_CLKGATE_CON(18), 10, GFLAGS),
++	GATE(CLK_OTPC_ARB, "clk_otpc_arb", "xin24m", 0,
++			RK3588_CLKGATE_CON(18), 11, GFLAGS),
++	GATE(CLK_OTP_PHY_G, "clk_otp_phy_g", "xin24m", 0,
++			RK3588_CLKGATE_CON(18), 13, GFLAGS),
++	GATE(CLK_OTPC_AUTO_RD_G, "clk_otpc_auto_rd_g", "xin24m", 0,
++			RK3588_CLKGATE_CON(18), 12, GFLAGS),
++
++	GATE(PCLK_SARADC, "pclk_saradc", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(11), 14, GFLAGS),
++	COMPOSITE(CLK_SARADC, "clk_saradc", gpll_24m_p, 0,
++			RK3588_CLKSEL_CON(40), 14, 1, MFLAGS, 6, 8, DFLAGS,
++			RK3588_CLKGATE_CON(11), 15, GFLAGS),
++
++	GATE(PCLK_SPI0, "pclk_spi0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(14), 6, GFLAGS),
++	GATE(PCLK_SPI1, "pclk_spi1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(14), 7, GFLAGS),
++	GATE(PCLK_SPI2, "pclk_spi2", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(14), 8, GFLAGS),
++	GATE(PCLK_SPI3, "pclk_spi3", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(14), 9, GFLAGS),
++	GATE(PCLK_SPI4, "pclk_spi4", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(14), 10, GFLAGS),
++	COMPOSITE_NODIV(CLK_SPI0, "clk_spi0", mux_200m_150m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 2, 2, MFLAGS,
++			RK3588_CLKGATE_CON(14), 11, GFLAGS),
++	COMPOSITE_NODIV(CLK_SPI1, "clk_spi1", mux_200m_150m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 4, 2, MFLAGS,
++			RK3588_CLKGATE_CON(14), 12, GFLAGS),
++	COMPOSITE_NODIV(CLK_SPI2, "clk_spi2", mux_200m_150m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 6, 2, MFLAGS,
++			RK3588_CLKGATE_CON(14), 13, GFLAGS),
++	COMPOSITE_NODIV(CLK_SPI3, "clk_spi3", mux_200m_150m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 8, 2, MFLAGS,
++			RK3588_CLKGATE_CON(14), 14, GFLAGS),
++	COMPOSITE_NODIV(CLK_SPI4, "clk_spi4", mux_200m_150m_24m_p, 0,
++			RK3588_CLKSEL_CON(59), 10, 2, MFLAGS,
++			RK3588_CLKGATE_CON(14), 15, GFLAGS),
++
++	GATE(ACLK_SPINLOCK, "aclk_spinlock", "aclk_bus_root", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(18), 6, GFLAGS),
++	GATE(PCLK_TSADC, "pclk_tsadc", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 0, GFLAGS),
++	COMPOSITE(CLK_TSADC, "clk_tsadc", gpll_24m_p, 0,
++			RK3588_CLKSEL_CON(41), 8, 1, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(12), 1, GFLAGS),
++
++	GATE(PCLK_UART1, "pclk_uart1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 2, GFLAGS),
++	GATE(PCLK_UART2, "pclk_uart2", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 3, GFLAGS),
++	GATE(PCLK_UART3, "pclk_uart3", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 4, GFLAGS),
++	GATE(PCLK_UART4, "pclk_uart4", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 5, GFLAGS),
++	GATE(PCLK_UART5, "pclk_uart5", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 6, GFLAGS),
++	GATE(PCLK_UART6, "pclk_uart6", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 7, GFLAGS),
++	GATE(PCLK_UART7, "pclk_uart7", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 8, GFLAGS),
++	GATE(PCLK_UART8, "pclk_uart8", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 9, GFLAGS),
++	GATE(PCLK_UART9, "pclk_uart9", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(12), 10, GFLAGS),
++
++	COMPOSITE(CLK_UART1_SRC, "clk_uart1_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(41), 14, 1, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(12), 11, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART1_FRAC, "clk_uart1_frac", "clk_uart1_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(42), 0,
++			RK3588_CLKGATE_CON(12), 12, GFLAGS,
++			&rk3588_uart1_fracmux),
++	GATE(SCLK_UART1, "sclk_uart1", "clk_uart1", 0,
++			RK3588_CLKGATE_CON(12), 13, GFLAGS),
++	COMPOSITE(CLK_UART2_SRC, "clk_uart2_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(43), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(12), 14, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART2_FRAC, "clk_uart2_frac", "clk_uart2_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(44), 0,
++			RK3588_CLKGATE_CON(12), 15, GFLAGS,
++			&rk3588_uart2_fracmux),
++	GATE(SCLK_UART2, "sclk_uart2", "clk_uart2", 0,
++			RK3588_CLKGATE_CON(13), 0, GFLAGS),
++	COMPOSITE(CLK_UART3_SRC, "clk_uart3_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(45), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(13), 1, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART3_FRAC, "clk_uart3_frac", "clk_uart3_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(46), 0,
++			RK3588_CLKGATE_CON(13), 2, GFLAGS,
++			&rk3588_uart3_fracmux),
++	GATE(SCLK_UART3, "sclk_uart3", "clk_uart3", 0,
++			RK3588_CLKGATE_CON(13), 3, GFLAGS),
++	COMPOSITE(CLK_UART4_SRC, "clk_uart4_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(47), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(13), 4, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART4_FRAC, "clk_uart4_frac", "clk_uart4_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(48), 0,
++			RK3588_CLKGATE_CON(13), 5, GFLAGS,
++			&rk3588_uart4_fracmux),
++	GATE(SCLK_UART4, "sclk_uart4", "clk_uart4", 0,
++			RK3588_CLKGATE_CON(13), 6, GFLAGS),
++	COMPOSITE(CLK_UART5_SRC, "clk_uart5_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(49), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(13), 7, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART5_FRAC, "clk_uart5_frac", "clk_uart5_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(50), 0,
++			RK3588_CLKGATE_CON(13), 8, GFLAGS,
++			&rk3588_uart5_fracmux),
++	GATE(SCLK_UART5, "sclk_uart5", "clk_uart5", 0,
++			RK3588_CLKGATE_CON(13), 9, GFLAGS),
++	COMPOSITE(CLK_UART6_SRC, "clk_uart6_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(51), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(13), 10, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART6_FRAC, "clk_uart6_frac", "clk_uart6_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(52), 0,
++			RK3588_CLKGATE_CON(13), 11, GFLAGS,
++			&rk3588_uart6_fracmux),
++	GATE(SCLK_UART6, "sclk_uart6", "clk_uart6", 0,
++			RK3588_CLKGATE_CON(13), 12, GFLAGS),
++	COMPOSITE(CLK_UART7_SRC, "clk_uart7_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(53), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(13), 13, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART7_FRAC, "clk_uart7_frac", "clk_uart7_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(54), 0,
++			RK3588_CLKGATE_CON(13), 14, GFLAGS,
++			&rk3588_uart7_fracmux),
++	GATE(SCLK_UART7, "sclk_uart7", "clk_uart7", 0,
++			RK3588_CLKGATE_CON(13), 15, GFLAGS),
++	COMPOSITE(CLK_UART8_SRC, "clk_uart8_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(55), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(14), 0, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART8_FRAC, "clk_uart8_frac", "clk_uart8_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(56), 0,
++			RK3588_CLKGATE_CON(14), 1, GFLAGS,
++			&rk3588_uart8_fracmux),
++	GATE(SCLK_UART8, "sclk_uart8", "clk_uart8", 0,
++			RK3588_CLKGATE_CON(14), 2, GFLAGS),
++	COMPOSITE(CLK_UART9_SRC, "clk_uart9_src", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(57), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(14), 3, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART9_FRAC, "clk_uart9_frac", "clk_uart9_src", CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(58), 0,
++			RK3588_CLKGATE_CON(14), 4, GFLAGS,
++			&rk3588_uart9_fracmux),
++	GATE(SCLK_UART9, "sclk_uart9", "clk_uart9", 0,
++			RK3588_CLKGATE_CON(14), 5, GFLAGS),
++
++	/* center */
++	COMPOSITE_NODIV(ACLK_CENTER_ROOT, "aclk_center_root", mux_700m_400m_200m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(165), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(69), 0, GFLAGS),
++	COMPOSITE_NODIV(ACLK_CENTER_LOW_ROOT, "aclk_center_low_root", mux_500m_250m_100m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(165), 2, 2, MFLAGS,
++			RK3588_CLKGATE_CON(69), 1, GFLAGS),
++	COMPOSITE_NODIV(HCLK_CENTER_ROOT, "hclk_center_root", mux_400m_200m_100m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(165), 4, 2, MFLAGS,
++			RK3588_CLKGATE_CON(69), 2, GFLAGS),
++	COMPOSITE_NODIV(PCLK_CENTER_ROOT, "pclk_center_root", mux_200m_100m_50m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(165), 6, 2, MFLAGS | CLK_MUX_READ_ONLY,
++			RK3588_CLKGATE_CON(69), 3, GFLAGS),
++	GATE(ACLK_DMA2DDR, "aclk_dma2ddr", "aclk_center_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(69), 5, GFLAGS),
++	GATE(ACLK_DDR_SHAREMEM, "aclk_ddr_sharemem", "aclk_center_low_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(69), 6, GFLAGS),
++	COMPOSITE_NODIV(ACLK_CENTER_S200_ROOT, "aclk_center_s200_root", mux_200m_100m_50m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(165), 8, 2, MFLAGS,
++			RK3588_CLKGATE_CON(69), 8, GFLAGS),
++	COMPOSITE_NODIV(ACLK_CENTER_S400_ROOT, "aclk_center_s400_root", mux_400m_200m_100m_24m_p,
++			CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(165), 10, 2, MFLAGS,
++			RK3588_CLKGATE_CON(69), 9, GFLAGS),
++	GATE(FCLK_DDR_CM0_CORE, "fclk_ddr_cm0_core", "hclk_center_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(69), 14, GFLAGS),
++	COMPOSITE_NODIV(CLK_DDR_TIMER_ROOT, "clk_ddr_timer_root", mux_24m_100m_p, CLK_IGNORE_UNUSED,
++			RK3588_CLKSEL_CON(165), 12, 1, MFLAGS,
++			RK3588_CLKGATE_CON(69), 15, GFLAGS),
++	GATE(CLK_DDR_TIMER0, "clk_ddr_timer0", "clk_ddr_timer_root", 0,
++			RK3588_CLKGATE_CON(70), 0, GFLAGS),
++	GATE(CLK_DDR_TIMER1, "clk_ddr_timer1", "clk_ddr_timer_root", 0,
++			RK3588_CLKGATE_CON(70), 1, GFLAGS),
++	GATE(TCLK_WDT_DDR, "tclk_wdt_ddr", "xin24m", 0,
++			RK3588_CLKGATE_CON(70), 2, GFLAGS),
++	COMPOSITE(CLK_DDR_CM0_RTC, "clk_ddr_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(166), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(70), 4, GFLAGS),
++	GATE(PCLK_WDT, "pclk_wdt", "pclk_center_root", 0,
++			RK3588_CLKGATE_CON(70), 7, GFLAGS),
++	GATE(PCLK_TIMER, "pclk_timer", "pclk_center_root", 0,
++			RK3588_CLKGATE_CON(70), 8, GFLAGS),
++	GATE(PCLK_DMA2DDR, "pclk_dma2ddr", "pclk_center_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(70), 9, GFLAGS),
++	GATE(PCLK_SHAREMEM, "pclk_sharemem", "pclk_center_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(70), 10, GFLAGS),
++
++	/* gpu */
++	COMPOSITE(CLK_GPU_SRC, "clk_gpu_src", gpll_cpll_aupll_npll_spll_p, 0,
++			RK3588_CLKSEL_CON(158), 5, 3, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(66), 1, GFLAGS),
++	GATE(CLK_GPU, "clk_gpu", "clk_gpu_src", 0,
++			RK3588_CLKGATE_CON(66), 4, GFLAGS),
++	GATE(CLK_GPU_COREGROUP, "clk_gpu_coregroup", "clk_gpu_src", 0,
++			RK3588_CLKGATE_CON(66), 6, GFLAGS),
++	COMPOSITE_NOMUX(CLK_GPU_STACKS, "clk_gpu_stacks", "clk_gpu_src", 0,
++			RK3588_CLKSEL_CON(159), 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(66), 7, GFLAGS),
++	GATE(CLK_GPU_PVTM, "clk_gpu_pvtm", "xin24m", 0,
++			RK3588_CLKGATE_CON(67), 0, GFLAGS),
++	GATE(CLK_CORE_GPU_PVTM, "clk_core_gpu_pvtm", "clk_gpu_src", 0,
++			RK3588_CLKGATE_CON(67), 1, GFLAGS),
++
++	/* isp1 */
++	COMPOSITE(ACLK_ISP1_ROOT, "aclk_isp1_root", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(67), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(26), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_ISP1_ROOT, "hclk_isp1_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(67), 7, 2, MFLAGS,
++			RK3588_CLKGATE_CON(26), 1, GFLAGS),
++	COMPOSITE(CLK_ISP1_CORE, "clk_isp1_core", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(67), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(26), 2, GFLAGS),
++	GATE(CLK_ISP1_CORE_MARVIN, "clk_isp1_core_marvin", "clk_isp1_core", 0,
++			RK3588_CLKGATE_CON(26), 3, GFLAGS),
++	GATE(CLK_ISP1_CORE_VICAP, "clk_isp1_core_vicap", "clk_isp1_core", 0,
++			RK3588_CLKGATE_CON(26), 4, GFLAGS),
++
++	/* npu */
++	COMPOSITE_NODIV(HCLK_NPU_ROOT, "hclk_npu_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(73), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(29), 0, GFLAGS),
++	COMPOSITE(CLK_NPU_DSU0, "clk_npu_dsu0", gpll_cpll_aupll_npll_spll_p, 0,
++			RK3588_CLKSEL_CON(73), 7, 3, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(29), 1, GFLAGS),
++	COMPOSITE_NODIV(PCLK_NPU_ROOT, "pclk_npu_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(74), 1, 2, MFLAGS,
++			RK3588_CLKGATE_CON(29), 4, GFLAGS),
++	GATE(ACLK_NPU1, "aclk_npu1", "clk_npu_dsu0", 0,
++			RK3588_CLKGATE_CON(27), 0, GFLAGS),
++	GATE(HCLK_NPU1, "hclk_npu1", "hclk_npu_root", 0,
++			RK3588_CLKGATE_CON(27), 2, GFLAGS),
++	GATE(ACLK_NPU2, "aclk_npu2", "clk_npu_dsu0", 0,
++			RK3588_CLKGATE_CON(28), 0, GFLAGS),
++	GATE(HCLK_NPU2, "hclk_npu2", "hclk_npu_root", 0,
++			RK3588_CLKGATE_CON(28), 2, GFLAGS),
++	COMPOSITE_NODIV(HCLK_NPU_CM0_ROOT, "hclk_npu_cm0_root", mux_400m_200m_100m_24m_p, 0,
++			RK3588_CLKSEL_CON(74), 5, 2, MFLAGS,
++			RK3588_CLKGATE_CON(30), 1, GFLAGS),
++	GATE(FCLK_NPU_CM0_CORE, "fclk_npu_cm0_core", "hclk_npu_cm0_root", 0,
++			RK3588_CLKGATE_CON(30), 3, GFLAGS),
++	COMPOSITE(CLK_NPU_CM0_RTC, "clk_npu_cm0_rtc", mux_24m_32k_p, 0,
++			RK3588_CLKSEL_CON(74), 12, 1, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(30), 5, GFLAGS),
++	GATE(PCLK_NPU_PVTM, "pclk_npu_pvtm", "pclk_npu_root", 0,
++			RK3588_CLKGATE_CON(29), 12, GFLAGS),
++	GATE(PCLK_NPU_GRF, "pclk_npu_grf", "pclk_npu_root", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(29), 13, GFLAGS),
++	GATE(CLK_NPU_PVTM, "clk_npu_pvtm", "xin24m", 0,
++			RK3588_CLKGATE_CON(29), 14, GFLAGS),
++	GATE(CLK_CORE_NPU_PVTM, "clk_core_npu_pvtm", "clk_npu_dsu0", 0,
++			RK3588_CLKGATE_CON(29), 15, GFLAGS),
++	GATE(ACLK_NPU0, "aclk_npu0", "clk_npu_dsu0", 0,
++			RK3588_CLKGATE_CON(30), 6, GFLAGS),
++	GATE(HCLK_NPU0, "hclk_npu0", "hclk_npu_root", 0,
++			RK3588_CLKGATE_CON(30), 8, GFLAGS),
++	GATE(PCLK_NPU_TIMER, "pclk_npu_timer", "pclk_npu_root", 0,
++			RK3588_CLKGATE_CON(29), 6, GFLAGS),
++	COMPOSITE_NODIV(CLK_NPUTIMER_ROOT, "clk_nputimer_root", mux_24m_100m_p, 0,
++			RK3588_CLKSEL_CON(74), 3, 1, MFLAGS,
++			RK3588_CLKGATE_CON(29), 7, GFLAGS),
++	GATE(CLK_NPUTIMER0, "clk_nputimer0", "clk_nputimer_root", 0,
++			RK3588_CLKGATE_CON(29), 8, GFLAGS),
++	GATE(CLK_NPUTIMER1, "clk_nputimer1", "clk_nputimer_root", 0,
++			RK3588_CLKGATE_CON(29), 9, GFLAGS),
++	GATE(PCLK_NPU_WDT, "pclk_npu_wdt", "pclk_npu_root", 0,
++			RK3588_CLKGATE_CON(29), 10, GFLAGS),
++	GATE(TCLK_NPU_WDT, "tclk_npu_wdt", "xin24m", 0,
++			RK3588_CLKGATE_CON(29), 11, GFLAGS),
++
++	/* nvm */
++	COMPOSITE_NODIV(HCLK_NVM_ROOT,  "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(31), 0, GFLAGS),
++	COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(31), 1, GFLAGS),
++	GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
++			RK3588_CLKGATE_CON(31), 5, GFLAGS),
++	COMPOSITE(CCLK_EMMC, "cclk_emmc", gpll_cpll_24m_p, 0,
++			RK3588_CLKSEL_CON(77), 14, 2, MFLAGS, 8, 6, DFLAGS,
++			RK3588_CLKGATE_CON(31), 6, GFLAGS),
++	COMPOSITE(BCLK_EMMC, "bclk_emmc", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(78), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(31), 7, GFLAGS),
++	GATE(TMCLK_EMMC, "tmclk_emmc", "xin24m", 0,
++			RK3588_CLKGATE_CON(31), 8, GFLAGS),
++
++	COMPOSITE(SCLK_SFC, "sclk_sfc", gpll_cpll_24m_p, 0,
++			RK3588_CLKSEL_CON(78), 12, 2, MFLAGS, 6, 6, DFLAGS,
++			RK3588_CLKGATE_CON(31), 9, GFLAGS),
++
++	/* php */
++	COMPOSITE(CLK_GMAC0_PTP_REF, "clk_gmac0_ptp_ref", clk_gmac0_ptp_ref_p, 0,
++			RK3588_CLKSEL_CON(81), 6, 1, MFLAGS, 0, 6, DFLAGS,
++			RK3588_CLKGATE_CON(34), 10, GFLAGS),
++	COMPOSITE(CLK_GMAC1_PTP_REF, "clk_gmac1_ptp_ref", clk_gmac1_ptp_ref_p, 0,
++			RK3588_CLKSEL_CON(81), 13, 1, MFLAGS, 7, 6, DFLAGS,
++			RK3588_CLKGATE_CON(34), 11, GFLAGS),
++	COMPOSITE(CLK_GMAC_125M, "clk_gmac_125m", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(83), 15, 1, MFLAGS, 8, 7, DFLAGS,
++			RK3588_CLKGATE_CON(35), 5, GFLAGS),
++	COMPOSITE(CLK_GMAC_50M, "clk_gmac_50m", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(84), 7, 1, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(35), 6, GFLAGS),
++
++	COMPOSITE(ACLK_PCIE_ROOT, "aclk_pcie_root", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(80), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(32), 6, GFLAGS),
++	COMPOSITE(ACLK_PHP_ROOT, "aclk_php_root", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(80), 13, 1, MFLAGS, 8, 5, DFLAGS,
++			RK3588_CLKGATE_CON(32), 7, GFLAGS),
++	COMPOSITE_NODIV(PCLK_PHP_ROOT, "pclk_php_root", mux_150m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(80), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(32), 0, GFLAGS),
++	GATE(ACLK_PHP_GIC_ITS, "aclk_php_gic_its", "aclk_pcie_root", CLK_IS_CRITICAL,
++			RK3588_CLKGATE_CON(34), 6, GFLAGS),
++	GATE(ACLK_PCIE_BRIDGE, "aclk_pcie_bridge", "aclk_pcie_root", 0,
++			RK3588_CLKGATE_CON(32), 8, GFLAGS),
++	GATE(ACLK_MMU_PCIE, "aclk_mmu_pcie", "aclk_pcie_bridge", 0,
++			RK3588_CLKGATE_CON(34), 7, GFLAGS),
++	GATE(ACLK_MMU_PHP, "aclk_mmu_php", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(34), 8, GFLAGS),
++	GATE(ACLK_PCIE_4L_DBI, "aclk_pcie_4l_dbi", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(32), 13, GFLAGS),
++	GATE(ACLK_PCIE_2L_DBI, "aclk_pcie_2l_dbi", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(32), 14, GFLAGS),
++	GATE(ACLK_PCIE_1L0_DBI, "aclk_pcie_1l0_dbi", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(32), 15, GFLAGS),
++	GATE(ACLK_PCIE_1L1_DBI, "aclk_pcie_1l1_dbi", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 0, GFLAGS),
++	GATE(ACLK_PCIE_1L2_DBI, "aclk_pcie_1l2_dbi", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 1, GFLAGS),
++	GATE(ACLK_PCIE_4L_MSTR, "aclk_pcie_4l_mstr", "aclk_mmu_pcie", 0,
++			RK3588_CLKGATE_CON(33), 2, GFLAGS),
++	GATE(ACLK_PCIE_2L_MSTR, "aclk_pcie_2l_mstr", "aclk_mmu_pcie", 0,
++			RK3588_CLKGATE_CON(33), 3, GFLAGS),
++	GATE(ACLK_PCIE_1L0_MSTR, "aclk_pcie_1l0_mstr", "aclk_mmu_pcie", 0,
++			RK3588_CLKGATE_CON(33), 4, GFLAGS),
++	GATE(ACLK_PCIE_1L1_MSTR, "aclk_pcie_1l1_mstr", "aclk_mmu_pcie", 0,
++			RK3588_CLKGATE_CON(33), 5, GFLAGS),
++	GATE(ACLK_PCIE_1L2_MSTR, "aclk_pcie_1l2_mstr", "aclk_mmu_pcie", 0,
++			RK3588_CLKGATE_CON(33), 6, GFLAGS),
++	GATE(ACLK_PCIE_4L_SLV, "aclk_pcie_4l_slv", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 7, GFLAGS),
++	GATE(ACLK_PCIE_2L_SLV, "aclk_pcie_2l_slv", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 8, GFLAGS),
++	GATE(ACLK_PCIE_1L0_SLV, "aclk_pcie_1l0_slv", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 9, GFLAGS),
++	GATE(ACLK_PCIE_1L1_SLV, "aclk_pcie_1l1_slv", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 10, GFLAGS),
++	GATE(ACLK_PCIE_1L2_SLV, "aclk_pcie_1l2_slv", "aclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 11, GFLAGS),
++	GATE(PCLK_PCIE_4L, "pclk_pcie_4l", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 12, GFLAGS),
++	GATE(PCLK_PCIE_2L, "pclk_pcie_2l", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 13, GFLAGS),
++	GATE(PCLK_PCIE_1L0, "pclk_pcie_1l0", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 14, GFLAGS),
++	GATE(PCLK_PCIE_1L1, "pclk_pcie_1l1", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(33), 15, GFLAGS),
++	GATE(PCLK_PCIE_1L2, "pclk_pcie_1l2", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(34), 0, GFLAGS),
++	GATE(CLK_PCIE_AUX0, "clk_pcie_aux0", "xin24m", 0,
++			RK3588_CLKGATE_CON(34), 1, GFLAGS),
++	GATE(CLK_PCIE_AUX1, "clk_pcie_aux1", "xin24m", 0,
++			RK3588_CLKGATE_CON(34), 2, GFLAGS),
++	GATE(CLK_PCIE_AUX2, "clk_pcie_aux2", "xin24m", 0,
++			RK3588_CLKGATE_CON(34), 3, GFLAGS),
++	GATE(CLK_PCIE_AUX3, "clk_pcie_aux3", "xin24m", 0,
++			RK3588_CLKGATE_CON(34), 4, GFLAGS),
++	GATE(CLK_PCIE_AUX4, "clk_pcie_aux4", "xin24m", 0,
++			RK3588_CLKGATE_CON(34), 5, GFLAGS),
++	GATE(CLK_PIPEPHY0_REF, "clk_pipephy0_ref", "xin24m", 0,
++			RK3588_CLKGATE_CON(37), 0, GFLAGS),
++	GATE(CLK_PIPEPHY1_REF, "clk_pipephy1_ref", "xin24m", 0,
++			RK3588_CLKGATE_CON(37), 1, GFLAGS),
++	GATE(CLK_PIPEPHY2_REF, "clk_pipephy2_ref", "xin24m", 0,
++			RK3588_CLKGATE_CON(37), 2, GFLAGS),
++	GATE(PCLK_GMAC0, "pclk_gmac0", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(32), 3, GFLAGS),
++	GATE(PCLK_GMAC1, "pclk_gmac1", "pclk_php_root", 0,
++			RK3588_CLKGATE_CON(32), 4, GFLAGS),
++	GATE(ACLK_GMAC0, "aclk_gmac0", "aclk_mmu_php", 0,
++			RK3588_CLKGATE_CON(32), 10, GFLAGS),
++	GATE(ACLK_GMAC1, "aclk_gmac1", "aclk_mmu_php", 0,
++			RK3588_CLKGATE_CON(32), 11, GFLAGS),
++	GATE(CLK_PMALIVE0, "clk_pmalive0", "xin24m", 0,
++			RK3588_CLKGATE_CON(37), 4, GFLAGS),
++	GATE(CLK_PMALIVE1, "clk_pmalive1", "xin24m", 0,
++			RK3588_CLKGATE_CON(37), 5, GFLAGS),
++	GATE(CLK_PMALIVE2, "clk_pmalive2", "xin24m", 0,
++			RK3588_CLKGATE_CON(37), 6, GFLAGS),
++	GATE(ACLK_SATA0, "aclk_sata0", "aclk_mmu_php", 0,
++			RK3588_CLKGATE_CON(37), 7, GFLAGS),
++	GATE(ACLK_SATA1, "aclk_sata1", "aclk_mmu_php", 0,
++			RK3588_CLKGATE_CON(37), 8, GFLAGS),
++	GATE(ACLK_SATA2, "aclk_sata2", "aclk_mmu_php", 0,
++			RK3588_CLKGATE_CON(37), 9, GFLAGS),
++	COMPOSITE(CLK_RXOOB0, "clk_rxoob0", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(82), 7, 1, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(37), 10, GFLAGS),
++	COMPOSITE(CLK_RXOOB1, "clk_rxoob1", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(82), 15, 1, MFLAGS, 8, 7, DFLAGS,
++			RK3588_CLKGATE_CON(37), 11, GFLAGS),
++	COMPOSITE(CLK_RXOOB2, "clk_rxoob2", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(83), 7, 1, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(37), 12, GFLAGS),
++	GATE(ACLK_USB3OTG2, "aclk_usb3otg2", "aclk_mmu_php", 0,
++			RK3588_CLKGATE_CON(35), 7, GFLAGS),
++	GATE(SUSPEND_CLK_USB3OTG2, "suspend_clk_usb3otg2", "xin24m", 0,
++			RK3588_CLKGATE_CON(35), 8, GFLAGS),
++	GATE(REF_CLK_USB3OTG2, "ref_clk_usb3otg2", "xin24m", 0,
++			RK3588_CLKGATE_CON(35), 9, GFLAGS),
++	COMPOSITE(CLK_UTMI_OTG2, "clk_utmi_otg2", mux_150m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(84), 12, 2, MFLAGS, 8, 4, DFLAGS,
++			RK3588_CLKGATE_CON(35), 10, GFLAGS),
++	GATE(PCLK_PCIE_COMBO_PIPE_PHY0, "pclk_pcie_combo_pipe_phy0", "pclk_top_root", 0,
++			RK3588_PHP_CLKGATE_CON(0), 5, GFLAGS),
++	GATE(PCLK_PCIE_COMBO_PIPE_PHY1, "pclk_pcie_combo_pipe_phy1", "pclk_top_root", 0,
++			RK3588_PHP_CLKGATE_CON(0), 6, GFLAGS),
++	GATE(PCLK_PCIE_COMBO_PIPE_PHY2, "pclk_pcie_combo_pipe_phy2", "pclk_top_root", 0,
++			RK3588_PHP_CLKGATE_CON(0), 7, GFLAGS),
++	GATE(PCLK_PCIE_COMBO_PIPE_PHY, "pclk_pcie_combo_pipe_phy", "pclk_top_root", 0,
++			RK3588_PHP_CLKGATE_CON(0), 8, GFLAGS),
++
++	/* rga */
++	COMPOSITE(CLK_RGA3_1_CORE, "clk_rga3_1_core", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(174), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(76), 6, GFLAGS),
++	COMPOSITE(ACLK_RGA3_ROOT, "aclk_rga3_root", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(174), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(76), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_RGA3_ROOT, "hclk_rga3_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(174), 7, 2, MFLAGS,
++			RK3588_CLKGATE_CON(76), 1, GFLAGS),
++	GATE(HCLK_RGA3_1, "hclk_rga3_1", "hclk_rga3_root", 0,
++			RK3588_CLKGATE_CON(76), 4, GFLAGS),
++	GATE(ACLK_RGA3_1, "aclk_rga3_1", "aclk_rga3_root", 0,
++			RK3588_CLKGATE_CON(76), 5, GFLAGS),
++
++	/* vdec */
++	COMPOSITE_NODIV(0, "hclk_rkvdec0_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(89), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(40), 0, GFLAGS),
++	COMPOSITE(0, "aclk_rkvdec0_root", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(89), 7, 2, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(40), 1, GFLAGS),
++	COMPOSITE(ACLK_RKVDEC_CCU, "aclk_rkvdec_ccu", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(89), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(40), 2, GFLAGS),
++	COMPOSITE(CLK_RKVDEC0_CA, "clk_rkvdec0_ca", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(90), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(40), 7, GFLAGS),
++	COMPOSITE(CLK_RKVDEC0_HEVC_CA, "clk_rkvdec0_hevc_ca", gpll_cpll_npll_1000m_p, 0,
++			RK3588_CLKSEL_CON(90), 11, 2, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(40), 8, GFLAGS),
++	COMPOSITE(CLK_RKVDEC0_CORE, "clk_rkvdec0_core", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(91), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(40), 9, GFLAGS),
++	COMPOSITE_NODIV(0, "hclk_rkvdec1_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(93), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(41), 0, GFLAGS),
++	COMPOSITE(0, "aclk_rkvdec1_root", gpll_cpll_aupll_npll_p, 0,
++			RK3588_CLKSEL_CON(93), 7, 2, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(41), 1, GFLAGS),
++	COMPOSITE(CLK_RKVDEC1_CA, "clk_rkvdec1_ca", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(93), 14, 1, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(41), 6, GFLAGS),
++	COMPOSITE(CLK_RKVDEC1_HEVC_CA, "clk_rkvdec1_hevc_ca", gpll_cpll_npll_1000m_p, 0,
++			RK3588_CLKSEL_CON(94), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(41), 7, GFLAGS),
++	COMPOSITE(CLK_RKVDEC1_CORE, "clk_rkvdec1_core", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(94), 12, 1, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(41), 8, GFLAGS),
++
++	/* sdio */
++	COMPOSITE_NODIV(0, "hclk_sdio_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(172), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(75), 0, GFLAGS),
++	COMPOSITE(CCLK_SRC_SDIO, "cclk_src_sdio", gpll_cpll_24m_p, 0,
++			RK3588_CLKSEL_CON(172), 8, 2, MFLAGS, 2, 6, DFLAGS,
++			RK3588_CLKGATE_CON(75), 3, GFLAGS),
++	MMC(SCLK_SDIO_DRV, "sdio_drv", "cclk_src_sdio", RK3588_SDIO_CON0, 1),
++	MMC(SCLK_SDIO_SAMPLE, "sdio_sample", "cclk_src_sdio", RK3588_SDIO_CON1, 1),
++
++	/* usb */
++	COMPOSITE(ACLK_USB_ROOT, "aclk_usb_root", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(96), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(42), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_USB_ROOT, "hclk_usb_root", mux_150m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(96), 6, 2, MFLAGS,
++			RK3588_CLKGATE_CON(42), 1, GFLAGS),
++	GATE(SUSPEND_CLK_USB3OTG0, "suspend_clk_usb3otg0", "xin24m", 0,
++			RK3588_CLKGATE_CON(42), 5, GFLAGS),
++	GATE(REF_CLK_USB3OTG0, "ref_clk_usb3otg0", "xin24m", 0,
++			RK3588_CLKGATE_CON(42), 6, GFLAGS),
++	GATE(SUSPEND_CLK_USB3OTG1, "suspend_clk_usb3otg1", "xin24m", 0,
++			RK3588_CLKGATE_CON(42), 8, GFLAGS),
++	GATE(REF_CLK_USB3OTG1, "ref_clk_usb3otg1", "xin24m", 0,
++			RK3588_CLKGATE_CON(42), 9, GFLAGS),
++
++	/* vdpu */
++	COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(44), 0, GFLAGS),
++	COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
++			RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
++			RK3588_CLKGATE_CON(44), 1, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
++			RK3588_CLKGATE_CON(44), 2, GFLAGS),
++	COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(99), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(44), 3, GFLAGS),
++	GATE(HCLK_IEP2P0, "hclk_iep2p0", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 4, GFLAGS),
++	COMPOSITE(CLK_IEP2P0_CORE, "clk_iep2p0_core", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(99), 12, 1, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(45), 6, GFLAGS),
++	GATE(HCLK_JPEG_ENCODER0, "hclk_jpeg_encoder0", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(44), 11, GFLAGS),
++	GATE(HCLK_JPEG_ENCODER1, "hclk_jpeg_encoder1", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(44), 13, GFLAGS),
++	GATE(HCLK_JPEG_ENCODER2, "hclk_jpeg_encoder2", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(44), 15, GFLAGS),
++	GATE(HCLK_JPEG_ENCODER3, "hclk_jpeg_encoder3", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 1, GFLAGS),
++	GATE(HCLK_JPEG_DECODER, "hclk_jpeg_decoder", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 3, GFLAGS),
++	GATE(HCLK_RGA2, "hclk_rga2", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 7, GFLAGS),
++	GATE(ACLK_RGA2, "aclk_rga2", "aclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 8, GFLAGS),
++	COMPOSITE(CLK_RGA2_CORE, "clk_rga2_core", gpll_cpll_npll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(100), 5, 3, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(45), 9, GFLAGS),
++	GATE(HCLK_RGA3_0, "hclk_rga3_0", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 10, GFLAGS),
++	GATE(ACLK_RGA3_0, "aclk_rga3_0", "aclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(45), 11, GFLAGS),
++	COMPOSITE(CLK_RGA3_0_CORE, "clk_rga3_0_core", gpll_cpll_npll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(100), 13, 3, MFLAGS, 8, 5, DFLAGS,
++			RK3588_CLKGATE_CON(45), 12, GFLAGS),
++	GATE(HCLK_VPU, "hclk_vpu", "hclk_vdpu_root", 0,
++			RK3588_CLKGATE_CON(44), 9, GFLAGS),
++
++	/* venc */
++	COMPOSITE_NODIV(HCLK_RKVENC1_ROOT, "hclk_rkvenc1_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(104), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(48), 0, GFLAGS),
++	COMPOSITE(ACLK_RKVENC1_ROOT, "aclk_rkvenc1_root", gpll_cpll_npll_p, 0,
++			RK3588_CLKSEL_CON(104), 7, 2, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(48), 1, GFLAGS),
++	COMPOSITE_NODIV(HCLK_RKVENC0_ROOT, "hclk_rkvenc0_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(102), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(47), 0, GFLAGS),
++	COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
++			RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(47), 1, GFLAGS),
++	GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
++			RK3588_CLKGATE_CON(47), 4, GFLAGS),
++	GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
++			RK3588_CLKGATE_CON(47), 5, GFLAGS),
++	COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
++			RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(47), 6, GFLAGS),
++	COMPOSITE(CLK_RKVENC1_CORE, "clk_rkvenc1_core", gpll_cpll_aupll_npll_p, 0,
++			RK3588_CLKSEL_CON(104), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(48), 6, GFLAGS),
++
++	/* vi */
++	COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(49), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
++			RK3588_CLKGATE_CON(49), 1, GFLAGS),
++	COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(106), 10, 2, MFLAGS,
++			RK3588_CLKGATE_CON(49), 2, GFLAGS),
++	COMPOSITE_NODIV(ICLK_CSIHOST01, "iclk_csihost01", mux_400m_200m_100m_24m_p, 0,
++			RK3588_CLKSEL_CON(108), 14, 2, MFLAGS,
++			RK3588_CLKGATE_CON(51), 10, GFLAGS),
++	GATE(ICLK_CSIHOST0, "iclk_csihost0", "iclk_csihost01", 0,
++			RK3588_CLKGATE_CON(51), 11, GFLAGS),
++	GATE(ICLK_CSIHOST1, "iclk_csihost1", "iclk_csihost01", 0,
++			RK3588_CLKGATE_CON(51), 12, GFLAGS),
++	GATE(PCLK_CSI_HOST_0, "pclk_csi_host_0", "pclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 4, GFLAGS),
++	GATE(PCLK_CSI_HOST_1, "pclk_csi_host_1", "pclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 5, GFLAGS),
++	GATE(PCLK_CSI_HOST_2, "pclk_csi_host_2", "pclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 6, GFLAGS),
++	GATE(PCLK_CSI_HOST_3, "pclk_csi_host_3", "pclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 7, GFLAGS),
++	GATE(PCLK_CSI_HOST_4, "pclk_csi_host_4", "pclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 8, GFLAGS),
++	GATE(PCLK_CSI_HOST_5, "pclk_csi_host_5", "pclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 9, GFLAGS),
++	GATE(ACLK_FISHEYE0, "aclk_fisheye0", "aclk_vi_root", 0,
++			RK3588_CLKGATE_CON(49), 14, GFLAGS),
++	GATE(HCLK_FISHEYE0, "hclk_fisheye0", "hclk_vi_root", 0,
++			RK3588_CLKGATE_CON(49), 15, GFLAGS),
++	COMPOSITE(CLK_FISHEYE0_CORE, "clk_fisheye0_core", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(108), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(50), 0, GFLAGS),
++	GATE(ACLK_FISHEYE1, "aclk_fisheye1", "aclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 1, GFLAGS),
++	GATE(HCLK_FISHEYE1, "hclk_fisheye1", "hclk_vi_root", 0,
++			RK3588_CLKGATE_CON(50), 2, GFLAGS),
++	COMPOSITE(CLK_FISHEYE1_CORE, "clk_fisheye1_core", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(108), 12, 2, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(50), 3, GFLAGS),
++	COMPOSITE(CLK_ISP0_CORE, "clk_isp0_core", gpll_cpll_aupll_spll_p, 0,
++			RK3588_CLKSEL_CON(107), 11, 2, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(49), 9, GFLAGS),
++	GATE(CLK_ISP0_CORE_MARVIN, "clk_isp0_core_marvin", "clk_isp0_core", 0,
++			RK3588_CLKGATE_CON(49), 10, GFLAGS),
++	GATE(CLK_ISP0_CORE_VICAP, "clk_isp0_core_vicap", "clk_isp0_core", 0,
++			RK3588_CLKGATE_CON(49), 11, GFLAGS),
++	GATE(ACLK_ISP0, "aclk_isp0", "aclk_vi_root", 0,
++			RK3588_CLKGATE_CON(49), 12, GFLAGS),
++	GATE(HCLK_ISP0, "hclk_isp0", "hclk_vi_root", 0,
++			RK3588_CLKGATE_CON(49), 13, GFLAGS),
++	COMPOSITE(DCLK_VICAP, "dclk_vicap", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(107), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(49), 6, GFLAGS),
++	GATE(ACLK_VICAP, "aclk_vicap", "aclk_vi_root", 0,
++			RK3588_CLKGATE_CON(49), 7, GFLAGS),
++	GATE(HCLK_VICAP, "hclk_vicap", "hclk_vi_root", 0,
++			RK3588_CLKGATE_CON(49), 8, GFLAGS),
++
++	/* vo0 */
++	COMPOSITE(ACLK_VO0_ROOT, "aclk_vo0_root", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(116), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(55), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VO0_ROOT, "hclk_vo0_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(116), 6, 2, MFLAGS,
++			RK3588_CLKGATE_CON(55), 1, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VO0_S_ROOT, "hclk_vo0_s_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(116), 8, 2, MFLAGS,
++			RK3588_CLKGATE_CON(55), 2, GFLAGS),
++	COMPOSITE_NODIV(PCLK_VO0_ROOT, "pclk_vo0_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(116), 10, 2, MFLAGS,
++			RK3588_CLKGATE_CON(55), 3, GFLAGS),
++	COMPOSITE_NODIV(PCLK_VO0_S_ROOT, "pclk_vo0_s_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(116), 12, 2, MFLAGS,
++			RK3588_CLKGATE_CON(55), 4, GFLAGS),
++	GATE(PCLK_DP0, "pclk_dp0", "pclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(56), 4, GFLAGS),
++	GATE(PCLK_DP1, "pclk_dp1", "pclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(56), 5, GFLAGS),
++	GATE(PCLK_S_DP0, "pclk_s_dp0", "pclk_vo0_s_root", 0,
++			RK3588_CLKGATE_CON(56), 6, GFLAGS),
++	GATE(PCLK_S_DP1, "pclk_s_dp1", "pclk_vo0_s_root", 0,
++			RK3588_CLKGATE_CON(56), 7, GFLAGS),
++	GATE(CLK_DP0, "clk_dp0", "aclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(56), 8, GFLAGS),
++	GATE(CLK_DP1, "clk_dp1", "aclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(56), 9, GFLAGS),
++	GATE(HCLK_HDCP_KEY0, "hclk_hdcp_key0", "hclk_vo0_s_root", 0,
++			RK3588_CLKGATE_CON(55), 11, GFLAGS),
++	GATE(PCLK_HDCP0, "pclk_hdcp0", "pclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(55), 14, GFLAGS),
++	GATE(ACLK_TRNG0, "aclk_trng0", "aclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(56), 0, GFLAGS),
++	GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
++			RK3588_CLKGATE_CON(56), 1, GFLAGS),
++	GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(55), 10, GFLAGS),
++	COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(56), 11, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S4_8CH_TX_FRAC, "clk_i2s4_8ch_tx_frac", "clk_i2s4_8ch_tx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(119), 0,
++			RK3588_CLKGATE_CON(56), 12, GFLAGS,
++			&rk3588_i2s4_8ch_tx_fracmux),
++	GATE(MCLK_I2S4_8CH_TX, "mclk_i2s4_8ch_tx", "clk_i2s4_8ch_tx", 0,
++			RK3588_CLKGATE_CON(56), 13, GFLAGS),
++	COMPOSITE(CLK_I2S8_8CH_TX_SRC, "clk_i2s8_8ch_tx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(120), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(56), 15, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S8_8CH_TX_FRAC, "clk_i2s8_8ch_tx_frac", "clk_i2s8_8ch_tx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(121), 0,
++			RK3588_CLKGATE_CON(57), 0, GFLAGS,
++			&rk3588_i2s8_8ch_tx_fracmux),
++	GATE(MCLK_I2S8_8CH_TX, "mclk_i2s8_8ch_tx", "clk_i2s8_8ch_tx", 0,
++			RK3588_CLKGATE_CON(57), 1, GFLAGS),
++	COMPOSITE(CLK_SPDIF2_DP0_SRC, "clk_spdif2_dp0_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(122), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(57), 3, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_SPDIF2_DP0_FRAC, "clk_spdif2_dp0_frac", "clk_spdif2_dp0_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(123), 0,
++			RK3588_CLKGATE_CON(57), 4, GFLAGS,
++			&rk3588_spdif2_dp0_fracmux),
++	GATE(MCLK_SPDIF2_DP0, "mclk_spdif2_dp0", "clk_spdif2_dp0", 0,
++			RK3588_CLKGATE_CON(57), 5, GFLAGS),
++	GATE(MCLK_SPDIF2, "mclk_spdif2", "clk_spdif2_dp0", 0,
++			RK3588_CLKGATE_CON(57), 6, GFLAGS),
++	COMPOSITE(CLK_SPDIF5_DP1_SRC, "clk_spdif5_dp1_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(124), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(57), 8, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_SPDIF5_DP1_FRAC, "clk_spdif5_dp1_frac", "clk_spdif5_dp1_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(125), 0,
++			RK3588_CLKGATE_CON(57), 9, GFLAGS,
++			&rk3588_spdif5_dp1_fracmux),
++	GATE(MCLK_SPDIF5_DP1, "mclk_spdif5_dp1", "clk_spdif5_dp1", 0,
++			RK3588_CLKGATE_CON(57), 10, GFLAGS),
++	GATE(MCLK_SPDIF5, "mclk_spdif5", "clk_spdif5_dp1", 0,
++			RK3588_CLKGATE_CON(57), 11, GFLAGS),
++	COMPOSITE_NOMUX(CLK_AUX16M_0, "clk_aux16m_0", "gpll", 0,
++			RK3588_CLKSEL_CON(117), 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(56), 2, GFLAGS),
++	COMPOSITE_NOMUX(CLK_AUX16M_1, "clk_aux16m_1", "gpll", 0,
++			RK3588_CLKSEL_CON(117), 8, 8, DFLAGS,
++			RK3588_CLKGATE_CON(56), 3, GFLAGS),
++
++	/* vo1 */
++	COMPOSITE_HALFDIV(CLK_HDMITRX_REFSRC, "clk_hdmitrx_refsrc", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(157), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(65), 9, GFLAGS),
++	COMPOSITE(ACLK_HDCP1_ROOT, "aclk_hdcp1_root", aclk_hdcp1_root_p, 0,
++			RK3588_CLKSEL_CON(128), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(59), 0, GFLAGS),
++	COMPOSITE(ACLK_HDMIRX_ROOT, "aclk_hdmirx_root", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(128), 12, 1, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(59), 1, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VO1_ROOT, "hclk_vo1_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(128), 13, 2, MFLAGS,
++			RK3588_CLKGATE_CON(59), 2, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VO1_S_ROOT, "hclk_vo1_s_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(129), 0, 2, MFLAGS,
++			RK3588_CLKGATE_CON(59), 3, GFLAGS),
++	COMPOSITE_NODIV(PCLK_VO1_ROOT, "pclk_vo1_root", mux_150m_100m_24m_p, 0,
++			RK3588_CLKSEL_CON(129), 2, 2, MFLAGS,
++			RK3588_CLKGATE_CON(59), 4, GFLAGS),
++	COMPOSITE_NODIV(PCLK_VO1_S_ROOT, "pclk_vo1_s_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(129), 4, 2, MFLAGS,
++			RK3588_CLKGATE_CON(59), 5, GFLAGS),
++	COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
++			RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(52), 0, GFLAGS),
++	COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
++			RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
++			RK3588_CLKGATE_CON(52), 1, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
++			RK3588_CLKGATE_CON(52), 2, GFLAGS),
++	COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(110), 12, 2, MFLAGS,
++			RK3588_CLKGATE_CON(52), 3, GFLAGS),
++	COMPOSITE(ACLK_VO1USB_TOP_ROOT, "aclk_vo1usb_top_root", gpll_cpll_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(170), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(74), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_VO1USB_TOP_ROOT, "hclk_vo1usb_top_root", mux_200m_100m_50m_24m_p, CLK_IS_CRITICAL,
++			RK3588_CLKSEL_CON(170), 6, 2, MFLAGS,
++			RK3588_CLKGATE_CON(74), 2, GFLAGS),
++	MUX(ACLK_VOP_SUB_SRC, "aclk_vop_sub_src", aclk_vop_sub_src_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(115), 9, 1, MFLAGS),
++	GATE(PCLK_EDP0, "pclk_edp0", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(62), 0, GFLAGS),
++	GATE(CLK_EDP0_24M, "clk_edp0_24m", "xin24m", 0,
++			RK3588_CLKGATE_CON(62), 1, GFLAGS),
++	COMPOSITE_NODIV(CLK_EDP0_200M, "clk_edp0_200m", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(140), 1, 2, MFLAGS,
++			RK3588_CLKGATE_CON(62), 2, GFLAGS),
++	GATE(PCLK_EDP1, "pclk_edp1", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(62), 3, GFLAGS),
++	GATE(CLK_EDP1_24M, "clk_edp1_24m", "xin24m", 0,
++			RK3588_CLKGATE_CON(62), 4, GFLAGS),
++	COMPOSITE_NODIV(CLK_EDP1_200M, "clk_edp1_200m", mux_200m_100m_50m_24m_p, 0,
++			RK3588_CLKSEL_CON(140), 3, 2, MFLAGS,
++			RK3588_CLKGATE_CON(62), 5, GFLAGS),
++	GATE(HCLK_HDCP_KEY1, "hclk_hdcp_key1", "hclk_vo1_s_root", 0,
++			RK3588_CLKGATE_CON(60), 4, GFLAGS),
++	GATE(PCLK_HDCP1, "pclk_hdcp1", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(60), 7, GFLAGS),
++	GATE(ACLK_HDMIRX, "aclk_hdmirx", "aclk_hdmirx_root", 0,
++			RK3588_CLKGATE_CON(61), 9, GFLAGS),
++	GATE(PCLK_HDMIRX, "pclk_hdmirx", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(61), 10, GFLAGS),
++	GATE(CLK_HDMIRX_REF, "clk_hdmirx_ref", "aclk_hdcp1_root", 0,
++			RK3588_CLKGATE_CON(61), 11, GFLAGS),
++	COMPOSITE(CLK_HDMIRX_AUD_SRC, "clk_hdmirx_aud_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(138), 8, 1, MFLAGS, 0, 8, DFLAGS,
++			RK3588_CLKGATE_CON(61), 12, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_HDMIRX_AUD_FRAC, "clk_hdmirx_aud_frac", "clk_hdmirx_aud_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(139), 0,
++			RK3588_CLKGATE_CON(61), 13, GFLAGS,
++			&rk3588_hdmirx_aud_fracmux),
++	GATE(CLK_HDMIRX_AUD, "clk_hdmirx_aud", "clk_hdmirx_aud_mux", 0,
++			RK3588_CLKGATE_CON(61), 14, GFLAGS),
++	GATE(PCLK_HDMITX0, "pclk_hdmitx0", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(60), 11, GFLAGS),
++	COMPOSITE(CLK_HDMITX0_EARC, "clk_hdmitx0_earc", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(133), 6, 1, MFLAGS, 1, 5, DFLAGS,
++			RK3588_CLKGATE_CON(60), 15, GFLAGS),
++	GATE(CLK_HDMITX0_REF, "clk_hdmitx0_ref", "aclk_hdcp1_root", 0,
++			RK3588_CLKGATE_CON(61), 0, GFLAGS),
++	GATE(PCLK_HDMITX1, "pclk_hdmitx1", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(61), 2, GFLAGS),
++	COMPOSITE(CLK_HDMITX1_EARC, "clk_hdmitx1_earc", gpll_cpll_p, 0,
++			RK3588_CLKSEL_CON(136), 6, 1, MFLAGS, 1, 5, DFLAGS,
++			RK3588_CLKGATE_CON(61), 6, GFLAGS),
++	GATE(CLK_HDMITX1_REF, "clk_hdmitx1_ref", "aclk_hdcp1_root", 0,
++			RK3588_CLKGATE_CON(61), 7, GFLAGS),
++	GATE(ACLK_TRNG1, "aclk_trng1", "aclk_hdcp1_root", 0,
++			RK3588_CLKGATE_CON(60), 9, GFLAGS),
++	GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
++			RK3588_CLKGATE_CON(60), 10, GFLAGS),
++	GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(59), 12, GFLAGS),
++	GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
++			RK3588_CLKGATE_CON(59), 14, GFLAGS),
++	GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
++			RK3588_CLKGATE_CON(59), 15, GFLAGS),
++	GATE(PCLK_S_HDMIRX, "pclk_s_hdmirx", "pclk_vo1_s_root", 0,
++			RK3588_CLKGATE_CON(65), 8, GFLAGS),
++	COMPOSITE(CLK_I2S10_8CH_RX_SRC, "clk_i2s10_8ch_rx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(155), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(65), 5, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S10_8CH_RX_FRAC, "clk_i2s10_8ch_rx_frac", "clk_i2s10_8ch_rx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(156), 0,
++			RK3588_CLKGATE_CON(65), 6, GFLAGS,
++			&rk3588_i2s10_8ch_rx_fracmux),
++	GATE(MCLK_I2S10_8CH_RX, "mclk_i2s10_8ch_rx", "clk_i2s10_8ch_rx", 0,
++			RK3588_CLKGATE_CON(65), 7, GFLAGS),
++	COMPOSITE(CLK_I2S7_8CH_RX_SRC, "clk_i2s7_8ch_rx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(129), 11, 1, MFLAGS, 6, 5, DFLAGS,
++			RK3588_CLKGATE_CON(60), 1, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S7_8CH_RX_FRAC, "clk_i2s7_8ch_rx_frac", "clk_i2s7_8ch_rx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(130), 0,
++			RK3588_CLKGATE_CON(60), 2, GFLAGS,
++			&rk3588_i2s7_8ch_rx_fracmux),
++	GATE(MCLK_I2S7_8CH_RX, "mclk_i2s7_8ch_rx", "clk_i2s7_8ch_rx", 0,
++			RK3588_CLKGATE_CON(60), 3, GFLAGS),
++	COMPOSITE(CLK_I2S9_8CH_RX_SRC, "clk_i2s9_8ch_rx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(153), 12, 1, MFLAGS, 7, 5, DFLAGS,
++			RK3588_CLKGATE_CON(65), 1, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S9_8CH_RX_FRAC, "clk_i2s9_8ch_rx_frac", "clk_i2s9_8ch_rx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(154), 0,
++			RK3588_CLKGATE_CON(65), 2, GFLAGS,
++			&rk3588_i2s9_8ch_rx_fracmux),
++	GATE(MCLK_I2S9_8CH_RX, "mclk_i2s9_8ch_rx", "clk_i2s9_8ch_rx", 0,
++			RK3588_CLKGATE_CON(65), 3, GFLAGS),
++	COMPOSITE(CLK_I2S5_8CH_TX_SRC, "clk_i2s5_8ch_tx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(140), 10, 1, MFLAGS, 5, 5, DFLAGS,
++			RK3588_CLKGATE_CON(62), 6, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S5_8CH_TX_FRAC, "clk_i2s5_8ch_tx_frac", "clk_i2s5_8ch_tx_src", 0,
++			RK3588_CLKSEL_CON(141), 0,
++			RK3588_CLKGATE_CON(62), 7, GFLAGS,
++			&rk3588_i2s5_8ch_tx_fracmux),
++	GATE(MCLK_I2S5_8CH_TX, "mclk_i2s5_8ch_tx", "clk_i2s5_8ch_tx", 0,
++			RK3588_CLKGATE_CON(62), 8, GFLAGS),
++	COMPOSITE(CLK_I2S6_8CH_TX_SRC, "clk_i2s6_8ch_tx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(144), 8, 1, MFLAGS, 3, 5, DFLAGS,
++			RK3588_CLKGATE_CON(62), 13, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S6_8CH_TX_FRAC, "clk_i2s6_8ch_tx_frac", "clk_i2s6_8ch_tx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(145), 0,
++			RK3588_CLKGATE_CON(62), 14, GFLAGS,
++			&rk3588_i2s6_8ch_tx_fracmux),
++	GATE(MCLK_I2S6_8CH_TX, "mclk_i2s6_8ch_tx", "clk_i2s6_8ch_tx", 0,
++			RK3588_CLKGATE_CON(62), 15, GFLAGS),
++	COMPOSITE(CLK_I2S6_8CH_RX_SRC, "clk_i2s6_8ch_rx_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(146), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(63), 0, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S6_8CH_RX_FRAC, "clk_i2s6_8ch_rx_frac", "clk_i2s6_8ch_rx_src", 0,
++			RK3588_CLKSEL_CON(147), 0,
++			RK3588_CLKGATE_CON(63), 1, GFLAGS,
++			&rk3588_i2s6_8ch_rx_fracmux),
++	GATE(MCLK_I2S6_8CH_RX, "mclk_i2s6_8ch_rx", "clk_i2s6_8ch_rx", 0,
++			RK3588_CLKGATE_CON(63), 2, GFLAGS),
++	MUX(I2S6_8CH_MCLKOUT, "i2s6_8ch_mclkout", i2s6_8ch_mclkout_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(148), 2, 2, MFLAGS),
++	COMPOSITE(CLK_SPDIF3_SRC, "clk_spdif3_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(148), 9, 1, MFLAGS, 4, 5, DFLAGS,
++			RK3588_CLKGATE_CON(63), 5, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_SPDIF3_FRAC, "clk_spdif3_frac", "clk_spdif3_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(149), 0,
++			RK3588_CLKGATE_CON(63), 6, GFLAGS,
++			&rk3588_spdif3_fracmux),
++	GATE(MCLK_SPDIF3, "mclk_spdif3", "clk_spdif3", 0,
++			RK3588_CLKGATE_CON(63), 7, GFLAGS),
++	COMPOSITE(CLK_SPDIF4_SRC, "clk_spdif4_src", gpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(150), 7, 1, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(63), 9, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_SPDIF4_FRAC, "clk_spdif4_frac", "clk_spdif4_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(151), 0,
++			RK3588_CLKGATE_CON(63), 10, GFLAGS,
++			&rk3588_spdif4_fracmux),
++	GATE(MCLK_SPDIF4, "mclk_spdif4", "clk_spdif4", 0,
++			RK3588_CLKGATE_CON(63), 11, GFLAGS),
++	COMPOSITE(MCLK_SPDIFRX0, "mclk_spdifrx0", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(152), 7, 2, MFLAGS, 2, 5, DFLAGS,
++			RK3588_CLKGATE_CON(63), 13, GFLAGS),
++	COMPOSITE(MCLK_SPDIFRX1, "mclk_spdifrx1", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(152), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(63), 15, GFLAGS),
++	COMPOSITE(MCLK_SPDIFRX2, "mclk_spdifrx2", gpll_cpll_aupll_p, 0,
++			RK3588_CLKSEL_CON(153), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(64), 1, GFLAGS),
++	GATE(CLK_HDMIHDP0, "clk_hdmihdp0", "xin24m", 0,
++			RK3588_CLKGATE_CON(73), 12, GFLAGS),
++	GATE(CLK_HDMIHDP1, "clk_hdmihdp1", "xin24m", 0,
++			RK3588_CLKGATE_CON(73), 13, GFLAGS),
++	GATE(PCLK_HDPTX0, "pclk_hdptx0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(72), 5, GFLAGS),
++	GATE(PCLK_HDPTX1, "pclk_hdptx1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(72), 6, GFLAGS),
++	GATE(PCLK_USBDPPHY0, "pclk_usbdpphy0", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(72), 2, GFLAGS),
++	GATE(PCLK_USBDPPHY1, "pclk_usbdpphy1", "pclk_top_root", 0,
++			RK3588_CLKGATE_CON(72), 4, GFLAGS),
++	GATE(HCLK_VOP, "hclk_vop", "hclk_vop_root", 0,
++			RK3588_CLKGATE_CON(52), 8, GFLAGS),
++	GATE(ACLK_VOP, "aclk_vop", "aclk_vop_sub_src", 0,
++			RK3588_CLKGATE_CON(52), 9, GFLAGS),
++	COMPOSITE(DCLK_VOP0_SRC, "dclk_vop0_src", gpll_cpll_v0pll_aupll_p, 0,
++			RK3588_CLKSEL_CON(111), 7, 2, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(52), 10, GFLAGS),
++	COMPOSITE(DCLK_VOP1_SRC, "dclk_vop1_src", gpll_cpll_v0pll_aupll_p, 0,
++			RK3588_CLKSEL_CON(111), 14, 2, MFLAGS, 9, 5, DFLAGS,
++			RK3588_CLKGATE_CON(52), 11, GFLAGS),
++	COMPOSITE(DCLK_VOP2_SRC, "dclk_vop2_src", gpll_cpll_v0pll_aupll_p, CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3588_CLKSEL_CON(112), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_CLKGATE_CON(52), 12, GFLAGS),
++	COMPOSITE_NODIV(DCLK_VOP0, "dclk_vop0", dclk_vop0_p,
++			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3588_CLKSEL_CON(112), 7, 2, MFLAGS,
++			RK3588_CLKGATE_CON(52), 13, GFLAGS),
++	COMPOSITE_NODIV(DCLK_VOP1, "dclk_vop1", dclk_vop1_p,
++			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3588_CLKSEL_CON(112), 9, 2, MFLAGS,
++			RK3588_CLKGATE_CON(53), 0, GFLAGS),
++	COMPOSITE_NODIV(DCLK_VOP2, "dclk_vop2", dclk_vop2_p,
++			CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
++			RK3588_CLKSEL_CON(112), 11, 2, MFLAGS,
++			RK3588_CLKGATE_CON(53), 1, GFLAGS),
++	COMPOSITE(DCLK_VOP3, "dclk_vop3", gpll_cpll_v0pll_aupll_p, 0,
++			RK3588_CLKSEL_CON(113), 7, 2, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(53), 2, GFLAGS),
++	GATE(PCLK_DSIHOST0, "pclk_dsihost0", "pclk_vop_root", 0,
++			RK3588_CLKGATE_CON(53), 4, GFLAGS),
++	GATE(PCLK_DSIHOST1, "pclk_dsihost1", "pclk_vop_root", 0,
++			RK3588_CLKGATE_CON(53), 5, GFLAGS),
++	COMPOSITE(CLK_DSIHOST0, "clk_dsihost0", gpll_cpll_v0pll_spll_p, 0,
++			RK3588_CLKSEL_CON(114), 7, 2, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(53), 6, GFLAGS),
++	COMPOSITE(CLK_DSIHOST1, "clk_dsihost1", gpll_cpll_v0pll_spll_p, 0,
++			RK3588_CLKSEL_CON(115), 7, 2, MFLAGS, 0, 7, DFLAGS,
++			RK3588_CLKGATE_CON(53), 7, GFLAGS),
++	GATE(CLK_VOP_PMU, "clk_vop_pmu", "xin24m", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(53), 8, GFLAGS),
++	GATE(ACLK_VOP_DOBY, "aclk_vop_doby", "aclk_vop_root", 0,
++			RK3588_CLKGATE_CON(53), 10, GFLAGS),
++	GATE(CLK_USBDP_PHY0_IMMORTAL, "clk_usbdp_phy0_immortal", "xin24m", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(2), 8, GFLAGS),
++	GATE(CLK_USBDP_PHY1_IMMORTAL, "clk_usbdp_phy1_immortal", "xin24m", CLK_IGNORE_UNUSED,
++			RK3588_CLKGATE_CON(2), 15, GFLAGS),
++
++	GATE(CLK_REF_PIPE_PHY0_OSC_SRC, "clk_ref_pipe_phy0_osc_src", "xin24m", 0,
++			RK3588_CLKGATE_CON(77), 0, GFLAGS),
++	GATE(CLK_REF_PIPE_PHY1_OSC_SRC, "clk_ref_pipe_phy1_osc_src", "xin24m", 0,
++			RK3588_CLKGATE_CON(77), 1, GFLAGS),
++	GATE(CLK_REF_PIPE_PHY2_OSC_SRC, "clk_ref_pipe_phy2_osc_src", "xin24m", 0,
++			RK3588_CLKGATE_CON(77), 2, GFLAGS),
++	COMPOSITE_NOMUX(CLK_REF_PIPE_PHY0_PLL_SRC, "clk_ref_pipe_phy0_pll_src", "ppll", 0,
++			RK3588_CLKSEL_CON(176), 0, 6, DFLAGS,
++			RK3588_CLKGATE_CON(77), 3, GFLAGS),
++	COMPOSITE_NOMUX(CLK_REF_PIPE_PHY1_PLL_SRC, "clk_ref_pipe_phy1_pll_src", "ppll", 0,
++			RK3588_CLKSEL_CON(176), 6, 6, DFLAGS,
++			RK3588_CLKGATE_CON(77), 4, GFLAGS),
++	COMPOSITE_NOMUX(CLK_REF_PIPE_PHY2_PLL_SRC, "clk_ref_pipe_phy2_pll_src", "ppll", 0,
++			RK3588_CLKSEL_CON(177), 0, 6, DFLAGS,
++			RK3588_CLKGATE_CON(77), 5, GFLAGS),
++	MUX(CLK_REF_PIPE_PHY0, "clk_ref_pipe_phy0", clk_ref_pipe_phy0_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(177), 6, 1, MFLAGS),
++	MUX(CLK_REF_PIPE_PHY1, "clk_ref_pipe_phy1", clk_ref_pipe_phy1_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(177), 7, 1, MFLAGS),
++	MUX(CLK_REF_PIPE_PHY2, "clk_ref_pipe_phy2", clk_ref_pipe_phy2_p, CLK_SET_RATE_PARENT,
++			RK3588_CLKSEL_CON(177), 8, 1, MFLAGS),
++
++	/* pmu */
++	COMPOSITE(CLK_PMU1_300M_SRC, "clk_pmu1_300m_src", pmu_300m_24m_p, 0,
++			RK3588_PMU_CLKSEL_CON(0), 15, 1, MFLAGS, 10, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 3, GFLAGS),
++	COMPOSITE(CLK_PMU1_400M_SRC, "clk_pmu1_400m_src", pmu_400m_24m_p, 0,
++			RK3588_PMU_CLKSEL_CON(1), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 4, GFLAGS),
++	COMPOSITE_NOMUX(CLK_PMU1_50M_SRC, "clk_pmu1_50m_src", "clk_pmu1_400m_src", 0,
++			RK3588_PMU_CLKSEL_CON(0), 0, 4, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 0, GFLAGS),
++	COMPOSITE_NOMUX(CLK_PMU1_100M_SRC, "clk_pmu1_100m_src", "clk_pmu1_400m_src", 0,
++			RK3588_PMU_CLKSEL_CON(0), 4, 3, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 1, GFLAGS),
++	COMPOSITE_NOMUX(CLK_PMU1_200M_SRC, "clk_pmu1_200m_src", "clk_pmu1_400m_src", 0,
++			RK3588_PMU_CLKSEL_CON(0), 7, 3, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 2, GFLAGS),
++	COMPOSITE_NODIV(HCLK_PMU1_ROOT, "hclk_pmu1_root", hclk_pmu1_root_p, CLK_IS_CRITICAL,
++			RK3588_PMU_CLKSEL_CON(1), 6, 2, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 5, GFLAGS),
++	COMPOSITE_NODIV(PCLK_PMU1_ROOT, "pclk_pmu1_root", pmu_100m_50m_24m_src_p, CLK_IS_CRITICAL,
++			RK3588_PMU_CLKSEL_CON(1), 8, 2, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 7, GFLAGS),
++	GATE(PCLK_PMU0_ROOT, "pclk_pmu0_root", "pclk_pmu1_root", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(5), 0, GFLAGS),
++	COMPOSITE_NODIV(HCLK_PMU_CM0_ROOT, "hclk_pmu_cm0_root", hclk_pmu_cm0_root_p, CLK_IS_CRITICAL,
++			RK3588_PMU_CLKSEL_CON(1), 10, 2, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 8, GFLAGS),
++	GATE(CLK_PMU0, "clk_pmu0", "xin24m", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(5), 1, GFLAGS),
++	GATE(PCLK_PMU0, "pclk_pmu0", "pclk_pmu0_root", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(5), 2, GFLAGS),
++	GATE(PCLK_PMU0IOC, "pclk_pmu0ioc", "pclk_pmu0_root", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(5), 4, GFLAGS),
++	GATE(PCLK_GPIO0, "pclk_gpio0", "pclk_pmu0_root", 0,
++			RK3588_PMU_CLKGATE_CON(5), 5, GFLAGS),
++	COMPOSITE_NODIV(DBCLK_GPIO0, "dbclk_gpio0", mux_24m_32k_p, 0,
++			RK3588_PMU_CLKSEL_CON(17), 0, 1, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(5), 6, GFLAGS),
++	GATE(PCLK_I2C0, "pclk_i2c0", "pclk_pmu0_root", 0,
++			RK3588_PMU_CLKGATE_CON(2), 1, GFLAGS),
++	COMPOSITE_NODIV(CLK_I2C0, "clk_i2c0", pmu_200m_100m_p, 0,
++			RK3588_PMU_CLKSEL_CON(3), 6, 1, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(2), 2, GFLAGS),
++	GATE(HCLK_I2S1_8CH, "hclk_i2s1_8ch", "hclk_pmu1_root", 0,
++			RK3588_PMU_CLKGATE_CON(2), 7, GFLAGS),
++	COMPOSITE_NOMUX(CLK_I2S1_8CH_TX_SRC, "clk_i2s1_8ch_tx_src", "cpll", 0,
++			RK3588_PMU_CLKSEL_CON(5), 2, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(2), 8, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S1_8CH_TX_FRAC, "clk_i2s1_8ch_tx_frac", "clk_i2s1_8ch_tx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_PMU_CLKSEL_CON(6), 0,
++			RK3588_PMU_CLKGATE_CON(2), 9, GFLAGS,
++			&rk3588_i2s1_8ch_tx_fracmux),
++	GATE(MCLK_I2S1_8CH_TX, "mclk_i2s1_8ch_tx", "clk_i2s1_8ch_tx", 0,
++			RK3588_PMU_CLKGATE_CON(2), 10, GFLAGS),
++	COMPOSITE_NOMUX(CLK_I2S1_8CH_RX_SRC, "clk_i2s1_8ch_rx_src", "cpll", 0,
++			RK3588_PMU_CLKSEL_CON(7), 2, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(2), 11, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_I2S1_8CH_RX_FRAC, "clk_i2s1_8ch_rx_frac", "clk_i2s1_8ch_rx_src",
++			CLK_SET_RATE_PARENT,
++			RK3588_PMU_CLKSEL_CON(8), 0,
++			RK3588_PMU_CLKGATE_CON(2), 12, GFLAGS,
++			&rk3588_i2s1_8ch_rx_fracmux),
++	GATE(MCLK_I2S1_8CH_RX, "mclk_i2s1_8ch_rx", "clk_i2s1_8ch_rx", 0,
++			RK3588_PMU_CLKGATE_CON(2), 13, GFLAGS),
++	MUX(I2S1_8CH_MCLKOUT, "i2s1_8ch_mclkout", i2s1_8ch_mclkout_p, CLK_SET_RATE_PARENT,
++			RK3588_PMU_CLKSEL_CON(9), 2, 2, MFLAGS),
++	GATE(PCLK_PMU1, "pclk_pmu1", "pclk_pmu0_root", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(1), 0, GFLAGS),
++	GATE(CLK_DDR_FAIL_SAFE, "clk_ddr_fail_safe", "clk_pmu0", CLK_IGNORE_UNUSED,
++			RK3588_PMU_CLKGATE_CON(1), 1, GFLAGS),
++	GATE(CLK_PMU1, "clk_pmu1", "clk_pmu0", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(1), 3, GFLAGS),
++	GATE(HCLK_PDM0, "hclk_pdm0", "hclk_pmu1_root", 0,
++			RK3588_PMU_CLKGATE_CON(2), 14, GFLAGS),
++	COMPOSITE_NODIV(MCLK_PDM0, "mclk_pdm0", mclk_pdm0_p, 0,
++			RK3588_PMU_CLKSEL_CON(9), 4, 1, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(2), 15, GFLAGS),
++	GATE(HCLK_VAD, "hclk_vad", "hclk_pmu1_root", 0,
++			RK3588_PMU_CLKGATE_CON(3), 0, GFLAGS),
++	GATE(FCLK_PMU_CM0_CORE, "fclk_pmu_cm0_core", "hclk_pmu_cm0_root", CLK_IS_CRITICAL,
++			RK3588_PMU_CLKGATE_CON(0), 13, GFLAGS),
++	COMPOSITE(CLK_PMU_CM0_RTC, "clk_pmu_cm0_rtc", mux_24m_32k_p, CLK_IS_CRITICAL,
++			RK3588_PMU_CLKSEL_CON(2), 5, 1, MFLAGS, 0, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(0), 15, GFLAGS),
++	GATE(PCLK_PMU1_IOC, "pclk_pmu1_ioc", "pclk_pmu0_root", CLK_IGNORE_UNUSED,
++			RK3588_PMU_CLKGATE_CON(1), 5, GFLAGS),
++	GATE(PCLK_PMU1PWM, "pclk_pmu1pwm", "pclk_pmu0_root", 0,
++			RK3588_PMU_CLKGATE_CON(1), 12, GFLAGS),
++	COMPOSITE_NODIV(CLK_PMU1PWM, "clk_pmu1pwm", pmu_100m_50m_24m_src_p, 0,
++			RK3588_PMU_CLKSEL_CON(2), 9, 2, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(1), 13, GFLAGS),
++	GATE(CLK_PMU1PWM_CAPTURE, "clk_pmu1pwm_capture", "xin24m", 0,
++			RK3588_PMU_CLKGATE_CON(1), 14, GFLAGS),
++	GATE(PCLK_PMU1TIMER, "pclk_pmu1timer", "pclk_pmu0_root", 0,
++			RK3588_PMU_CLKGATE_CON(1), 8, GFLAGS),
++	COMPOSITE_NODIV(CLK_PMU1TIMER_ROOT, "clk_pmu1timer_root", pmu_24m_32k_100m_src_p, 0,
++			RK3588_PMU_CLKSEL_CON(2), 7, 2, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(1), 9, GFLAGS),
++	GATE(CLK_PMU1TIMER0, "clk_pmu1timer0", "clk_pmu1timer_root", 0,
++			RK3588_PMU_CLKGATE_CON(1), 10, GFLAGS),
++	GATE(CLK_PMU1TIMER1, "clk_pmu1timer1", "clk_pmu1timer_root", 0,
++			RK3588_PMU_CLKGATE_CON(1), 11, GFLAGS),
++	COMPOSITE_NOMUX(CLK_UART0_SRC, "clk_uart0_src", "cpll", 0,
++			RK3588_PMU_CLKSEL_CON(3), 7, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(2), 3, GFLAGS),
++	COMPOSITE_FRACMUX(CLK_UART0_FRAC, "clk_uart0_frac", "clk_uart0_src", CLK_SET_RATE_PARENT,
++			RK3588_PMU_CLKSEL_CON(4), 0,
++			RK3588_PMU_CLKGATE_CON(2), 4, GFLAGS,
++			&rk3588_uart0_fracmux),
++	GATE(SCLK_UART0, "sclk_uart0", "clk_uart0", 0,
++			RK3588_PMU_CLKGATE_CON(2), 5, GFLAGS),
++	GATE(PCLK_UART0, "pclk_uart0", "pclk_pmu0_root", 0,
++			RK3588_PMU_CLKGATE_CON(2), 6, GFLAGS),
++	GATE(PCLK_PMU1WDT, "pclk_pmu1wdt", "pclk_pmu0_root", 0,
++			RK3588_PMU_CLKGATE_CON(1), 6, GFLAGS),
++	COMPOSITE_NODIV(TCLK_PMU1WDT, "tclk_pmu1wdt", mux_24m_32k_p, 0,
++			RK3588_PMU_CLKSEL_CON(2), 6, 1, MFLAGS,
++			RK3588_PMU_CLKGATE_CON(1), 7, GFLAGS),
++	COMPOSITE(CLK_CR_PARA, "clk_cr_para", mux_24m_ppll_spll_p, 0,
++			RK3588_PMU_CLKSEL_CON(15), 5, 2, MFLAGS, 0, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(4), 11, GFLAGS),
++	COMPOSITE(CLK_USB2PHY_HDPTXRXPHY_REF, "clk_usb2phy_hdptxrxphy_ref", mux_24m_ppll_p,
++			CLK_IS_CRITICAL,
++			RK3588_PMU_CLKSEL_CON(14), 14, 1, MFLAGS, 9, 5, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(4), 7, GFLAGS),
++	COMPOSITE(CLK_USBDPPHY_MIPIDCPPHY_REF, "clk_usbdpphy_mipidcpphy_ref", mux_24m_ppll_spll_p,
++			CLK_IS_CRITICAL,
++			RK3588_PMU_CLKSEL_CON(14), 7, 2, MFLAGS, 0, 7, DFLAGS,
++			RK3588_PMU_CLKGATE_CON(4), 3, GFLAGS),
++
++	GATE(CLK_PHY0_REF_ALT_P, "clk_phy0_ref_alt_p", "ppll", 0,
++			RK3588_PHYREF_ALT_GATE, 0, GFLAGS),
++	GATE(CLK_PHY0_REF_ALT_M, "clk_phy0_ref_alt_m", "ppll", 0,
++			RK3588_PHYREF_ALT_GATE, 1, GFLAGS),
++	GATE(CLK_PHY1_REF_ALT_P, "clk_phy1_ref_alt_p", "ppll", 0,
++			RK3588_PHYREF_ALT_GATE, 2, GFLAGS),
++	GATE(CLK_PHY1_REF_ALT_M, "clk_phy1_ref_alt_m", "ppll", 0,
++			RK3588_PHYREF_ALT_GATE, 3, GFLAGS),
++
++	GATE(HCLK_SPDIFRX0, "hclk_spdifrx0", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(63), 12, GFLAGS),
++	GATE(HCLK_SPDIFRX1, "hclk_spdifrx1", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(63), 14, GFLAGS),
++	GATE(HCLK_SPDIFRX2, "hclk_spdifrx2", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(64), 0, GFLAGS),
++	GATE(HCLK_SPDIF4, "hclk_spdif4", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(63), 8, GFLAGS),
++	GATE(HCLK_SPDIF3, "hclk_spdif3", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(63), 4, GFLAGS),
++	GATE(HCLK_I2S6_8CH, "hclk_i2s6_8ch", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(63), 3, GFLAGS),
++	GATE(HCLK_I2S5_8CH, "hclk_i2s5_8ch", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(62), 12, GFLAGS),
++	GATE(HCLK_I2S9_8CH, "hclk_i2s9_8ch", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(65), 0, GFLAGS),
++	GATE(HCLK_I2S7_8CH, "hclk_i2s7_8ch", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(60), 0, GFLAGS),
++	GATE(HCLK_I2S10_8CH, "hclk_i2s10_8ch", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(65), 4, GFLAGS),
++	GATE(ACLK_HDCP1, "aclk_hdcp1", "aclk_hdcp1_pre", 0,
++			RK3588_CLKGATE_CON(60), 5, GFLAGS),
++	GATE(HCLK_HDCP1, "hclk_hdcp1", "hclk_vo1", 0,
++			RK3588_CLKGATE_CON(60), 6, GFLAGS),
++	GATE(HCLK_SPDIF5_DP1, "hclk_spdif5_dp1", "hclk_vo0", 0,
++			RK3588_CLKGATE_CON(57), 7, GFLAGS),
++	GATE(HCLK_SPDIF2_DP0, "hclk_spdif2_dp0", "hclk_vo0", 0,
++			RK3588_CLKGATE_CON(57), 2, GFLAGS),
++	GATE(HCLK_I2S8_8CH, "hclk_i2s8_8ch", "hclk_vo0", 0,
++			RK3588_CLKGATE_CON(56), 14, GFLAGS),
++	GATE(HCLK_I2S4_8CH, "hclk_i2s4_8ch", "hclk_vo0", 0,
++			RK3588_CLKGATE_CON(56), 10, GFLAGS),
++	GATE(ACLK_HDCP0, "aclk_hdcp0", "aclk_hdcp0_pre", 0,
++			RK3588_CLKGATE_CON(55), 12, GFLAGS),
++	GATE(HCLK_HDCP0, "hclk_hdcp0", "hclk_vo0", 0,
++			RK3588_CLKGATE_CON(55), 13, GFLAGS),
++	GATE(HCLK_RKVENC1, "hclk_rkvenc1", "hclk_rkvenc1_pre", 0,
++			RK3588_CLKGATE_CON(48), 4, GFLAGS),
++	GATE(ACLK_RKVENC1, "aclk_rkvenc1", "aclk_rkvenc1_pre", 0,
++			RK3588_CLKGATE_CON(48), 5, GFLAGS),
++	GATE(ACLK_VPU, "aclk_vpu", "aclk_vdpu_low_pre", 0,
++			RK3588_CLKGATE_CON(44), 8, GFLAGS),
++	GATE(ACLK_IEP2P0, "aclk_iep2p0", "aclk_vdpu_low_pre", 0,
++			RK3588_CLKGATE_CON(45), 5, GFLAGS),
++	GATE(ACLK_JPEG_ENCODER0, "aclk_jpeg_encoder0", "aclk_vdpu_low_pre", 0,
++			RK3588_CLKGATE_CON(44), 10, GFLAGS),
++	GATE(ACLK_JPEG_ENCODER1, "aclk_jpeg_encoder1", "aclk_vdpu_low_pre", 0,
++			RK3588_CLKGATE_CON(44), 12, GFLAGS),
++	GATE(ACLK_JPEG_ENCODER2, "aclk_jpeg_encoder2", "aclk_vdpu_low_pre", 0,
++			RK3588_CLKGATE_CON(44), 14, GFLAGS),
++	GATE(ACLK_JPEG_ENCODER3, "aclk_jpeg_encoder3", "aclk_vdpu_low_pre", 0,
++			RK3588_CLKGATE_CON(45), 0, GFLAGS),
++	GATE(ACLK_JPEG_DECODER, "aclk_jpeg_decoder", "aclk_jpeg_decoder_pre", 0,
++			RK3588_CLKGATE_CON(45), 2, GFLAGS),
++	GATE(ACLK_USB3OTG1, "aclk_usb3otg1", "aclk_usb", 0,
++			RK3588_CLKGATE_CON(42), 7, GFLAGS),
++	GATE(HCLK_HOST0, "hclk_host0", "hclk_usb", 0,
++			RK3588_CLKGATE_CON(42), 10, GFLAGS),
++	GATE(HCLK_HOST_ARB0, "hclk_host_arb0", "hclk_usb", 0,
++			RK3588_CLKGATE_CON(42), 11, GFLAGS),
++	GATE(HCLK_HOST1, "hclk_host1", "hclk_usb", 0,
++			RK3588_CLKGATE_CON(42), 12, GFLAGS),
++	GATE(HCLK_HOST_ARB1, "hclk_host_arb1", "hclk_usb", 0,
++			RK3588_CLKGATE_CON(42), 13, GFLAGS),
++	GATE(ACLK_USB3OTG0, "aclk_usb3otg0", "aclk_usb", 0,
++			RK3588_CLKGATE_CON(42), 4, GFLAGS),
++	MMC(SCLK_SDMMC_DRV, "sdmmc_drv", "scmi_cclk_sd", RK3588_SDMMC_CON0, 1),
++	MMC(SCLK_SDMMC_SAMPLE, "sdmmc_sample", "scmi_cclk_sd", RK3588_SDMMC_CON1, 1),
++	GATE(HCLK_SDIO, "hclk_sdio", "hclk_sdio_pre", 0,
++			RK3588_CLKGATE_CON(75), 2, GFLAGS),
++	GATE(HCLK_RKVDEC1, "hclk_rkvdec1", "hclk_rkvdec1_pre", 0,
++			RK3588_CLKGATE_CON(41), 2, GFLAGS),
++	GATE(ACLK_RKVDEC1, "aclk_rkvdec1", "aclk_rkvdec1_pre", 0,
++			RK3588_CLKGATE_CON(41), 3, GFLAGS),
++	GATE(HCLK_RKVDEC0, "hclk_rkvdec0", "hclk_rkvdec0_pre", 0,
++			RK3588_CLKGATE_CON(40), 3, GFLAGS),
++	GATE(ACLK_RKVDEC0, "aclk_rkvdec0", "aclk_rkvdec0_pre", 0,
++			RK3588_CLKGATE_CON(40), 4, GFLAGS),
++	GATE(CLK_PCIE4L_PIPE, "clk_pcie4l_pipe", "clk_pipe30phy_pipe0_i", 0,
++			RK3588_CLKGATE_CON(39), 0, GFLAGS),
++	GATE(CLK_PCIE2L_PIPE, "clk_pcie2l_pipe", "clk_pipe30phy_pipe2_i", 0,
++			RK3588_CLKGATE_CON(39), 1, GFLAGS),
++	GATE(CLK_PIPEPHY0_PIPE_G, "clk_pipephy0_pipe_g", "clk_pipephy0_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 3, GFLAGS),
++	GATE(CLK_PIPEPHY1_PIPE_G, "clk_pipephy1_pipe_g", "clk_pipephy1_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 4, GFLAGS),
++	GATE(CLK_PIPEPHY2_PIPE_G, "clk_pipephy2_pipe_g", "clk_pipephy2_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 5, GFLAGS),
++	GATE(CLK_PIPEPHY0_PIPE_ASIC_G, "clk_pipephy0_pipe_asic_g", "clk_pipephy0_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 6, GFLAGS),
++	GATE(CLK_PIPEPHY1_PIPE_ASIC_G, "clk_pipephy1_pipe_asic_g", "clk_pipephy1_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 7, GFLAGS),
++	GATE(CLK_PIPEPHY2_PIPE_ASIC_G, "clk_pipephy2_pipe_asic_g", "clk_pipephy2_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 8, GFLAGS),
++	GATE(CLK_PIPEPHY2_PIPE_U3_G, "clk_pipephy2_pipe_u3_g", "clk_pipephy2_pipe_i", 0,
++			RK3588_CLKGATE_CON(38), 9, GFLAGS),
++	GATE(CLK_PCIE1L2_PIPE, "clk_pcie1l2_pipe", "clk_pipephy0_pipe_g", 0,
++			RK3588_CLKGATE_CON(38), 13, GFLAGS),
++	GATE(CLK_PCIE1L0_PIPE, "clk_pcie1l0_pipe", "clk_pipephy1_pipe_g", 0,
++			RK3588_CLKGATE_CON(38), 14, GFLAGS),
++	GATE(CLK_PCIE1L1_PIPE, "clk_pcie1l1_pipe", "clk_pipephy2_pipe_g", 0,
++			RK3588_CLKGATE_CON(38), 15, GFLAGS),
++	GATE(HCLK_SFC, "hclk_sfc", "hclk_nvm", 0,
++			RK3588_CLKGATE_CON(31), 10, GFLAGS),
++	GATE(HCLK_SFC_XIP, "hclk_sfc_xip", "hclk_nvm", 0,
++			RK3588_CLKGATE_CON(31), 11, GFLAGS),
++	GATE(HCLK_EMMC, "hclk_emmc", "hclk_nvm", 0,
++			RK3588_CLKGATE_CON(31), 4, GFLAGS),
++	GATE(ACLK_ISP1, "aclk_isp1", "aclk_isp1_pre", 0,
++			RK3588_CLKGATE_CON(26), 5, GFLAGS),
++	GATE(HCLK_ISP1, "hclk_isp1", "hclk_isp1_pre", 0,
++			RK3588_CLKGATE_CON(26), 7, GFLAGS),
++	GATE(PCLK_AV1, "pclk_av1", "pclk_av1_pre", 0,
++			RK3588_CLKGATE_CON(68), 5, GFLAGS),
++	GATE(ACLK_AV1, "aclk_av1", "aclk_av1_pre", 0,
++			RK3588_CLKGATE_CON(68), 2, GFLAGS),
++
++	GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
++	GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
++	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
++	GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
++	GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
++	GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
++	GATE_LINK(ACLK_VDPU_LOW_PRE, "aclk_vdpu_low_pre", "aclk_vdpu_low_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 5, GFLAGS),
++	GATE_LINK(ACLK_RKVENC1_PRE, "aclk_rkvenc1_pre", "aclk_rkvenc1_root", "aclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 3, GFLAGS),
++	GATE_LINK(HCLK_RKVENC1_PRE, "hclk_rkvenc1_pre", "hclk_rkvenc1_root", "hclk_rkvenc0", 0, RK3588_CLKGATE_CON(48), 2, GFLAGS),
++	GATE_LINK(HCLK_RKVDEC0_PRE, "hclk_rkvdec0_pre", "hclk_rkvdec0_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 5, GFLAGS),
++	GATE_LINK(ACLK_RKVDEC0_PRE, "aclk_rkvdec0_pre", "aclk_rkvdec0_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(40), 6, GFLAGS),
++	GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
++	GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
++	GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
++	GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
++	GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
++	GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
++	GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
++	GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
++	GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
++};
++
++static void __init rk3588_clk_init(struct device_node *np)
++{
++	struct rockchip_clk_provider *ctx;
++	void __iomem *reg_base;
++
++	reg_base = of_iomap(np, 0);
++	if (!reg_base) {
++		pr_err("%s: could not map cru region\n", __func__);
++		return;
++	}
++
++	ctx = rockchip_clk_init(np, reg_base, CLK_NR_CLKS);
++	if (IS_ERR(ctx)) {
++		pr_err("%s: rockchip clk init failed\n", __func__);
++		iounmap(reg_base);
++		return;
++	}
++
++	rockchip_clk_register_plls(ctx, rk3588_pll_clks,
++				   ARRAY_SIZE(rk3588_pll_clks),
++				   RK3588_GRF_SOC_STATUS0);
++
++	rockchip_clk_register_armclk(ctx, ARMCLK_L, "armclk_l",
++			mux_armclkl_p, ARRAY_SIZE(mux_armclkl_p),
++			&rk3588_cpulclk_data, rk3588_cpulclk_rates,
++			ARRAY_SIZE(rk3588_cpulclk_rates));
++	rockchip_clk_register_armclk(ctx, ARMCLK_B01, "armclk_b01",
++			mux_armclkb01_p, ARRAY_SIZE(mux_armclkb01_p),
++			&rk3588_cpub0clk_data, rk3588_cpub0clk_rates,
++			ARRAY_SIZE(rk3588_cpub0clk_rates));
++	rockchip_clk_register_armclk(ctx, ARMCLK_B23, "armclk_b23",
++			mux_armclkb23_p, ARRAY_SIZE(mux_armclkb23_p),
++			&rk3588_cpub1clk_data, rk3588_cpub1clk_rates,
++			ARRAY_SIZE(rk3588_cpub1clk_rates));
++
++	rockchip_clk_register_branches(ctx, rk3588_clk_branches,
++				       ARRAY_SIZE(rk3588_clk_branches));
++
++	rk3588_rst_init(np, reg_base);
++
++	rockchip_register_restart_notifier(ctx, RK3588_GLB_SRST_FST, NULL);
++
++	rockchip_clk_of_add_provider(np, ctx);
++}
++
++CLK_OF_DECLARE(rk3588_cru, "rockchip,rk3588-cru", rk3588_clk_init);
++
++struct clk_rk3588_inits {
++	void (*inits)(struct device_node *np);
++};
++
++static const struct clk_rk3588_inits clk_3588_cru_init = {
++	.inits = rk3588_clk_init,
++};
++
++static const struct of_device_id clk_rk3588_match_table[] = {
++	{
++		.compatible = "rockchip,rk3588-cru",
++		.data = &clk_3588_cru_init,
++	},
++	{ }
++};
++
++static int __init clk_rk3588_probe(struct platform_device *pdev)
++{
++	const struct clk_rk3588_inits *init_data;
++	struct device *dev = &pdev->dev;
++
++	init_data = device_get_match_data(dev);
++	if (!init_data)
++		return -EINVAL;
++
++	if (init_data->inits)
++		init_data->inits(dev->of_node);
++
++	return 0;
++}
++
++static struct platform_driver clk_rk3588_driver = {
++	.driver		= {
++		.name	= "clk-rk3588",
++		.of_match_table = clk_rk3588_match_table,
++		.suppress_bind_attrs = true,
++	},
++};
++builtin_platform_driver_probe(clk_rk3588_driver, clk_rk3588_probe);
+--- a/drivers/clk/rockchip/clk.h
++++ b/drivers/clk/rockchip/clk.h
+@@ -235,6 +235,51 @@ struct clk;
+ #define RK3568_PMU_CLKGATE_CON(x)	((x) * 0x4 + 0x180)
+ #define RK3568_PMU_SOFTRST_CON(x)	((x) * 0x4 + 0x200)
+ 
++#define RK3588_PHP_CRU_BASE		0x8000
++#define RK3588_PMU_CRU_BASE		0x30000
++#define RK3588_BIGCORE0_CRU_BASE	0x50000
++#define RK3588_BIGCORE1_CRU_BASE	0x52000
++#define RK3588_DSU_CRU_BASE		0x58000
++
++#define RK3588_PLL_CON(x)		RK2928_PLL_CON(x)
++#define RK3588_MODE_CON0		0x280
++#define RK3588_B0_PLL_MODE_CON0		(RK3588_BIGCORE0_CRU_BASE + 0x280)
++#define RK3588_B1_PLL_MODE_CON0		(RK3588_BIGCORE1_CRU_BASE + 0x280)
++#define RK3588_LPLL_MODE_CON0		(RK3588_DSU_CRU_BASE + 0x280)
++#define RK3588_CLKSEL_CON(x)		((x) * 0x4 + 0x300)
++#define RK3588_CLKGATE_CON(x)		((x) * 0x4 + 0x800)
++#define RK3588_SOFTRST_CON(x)		((x) * 0x4 + 0xa00)
++#define RK3588_GLB_CNT_TH		0xc00
++#define RK3588_GLB_SRST_FST		0xc08
++#define RK3588_GLB_SRST_SND		0xc0c
++#define RK3588_GLB_RST_CON		0xc10
++#define RK3588_GLB_RST_ST		0xc04
++#define RK3588_SDIO_CON0		0xC24
++#define RK3588_SDIO_CON1		0xC28
++#define RK3588_SDMMC_CON0		0xC30
++#define RK3588_SDMMC_CON1		0xC34
++
++#define RK3588_PHP_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0x800)
++#define RK3588_PHP_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PHP_CRU_BASE + 0xa00)
++
++#define RK3588_PMU_PLL_CON(x)		((x) * 0x4 + RK3588_PHP_CRU_BASE)
++#define RK3588_PMU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x300)
++#define RK3588_PMU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0x800)
++#define RK3588_PMU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_PMU_CRU_BASE + 0xa00)
++
++#define RK3588_B0_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE)
++#define RK3588_BIGCORE0_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x300)
++#define RK3588_BIGCORE0_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0x800)
++#define RK3588_BIGCORE0_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE0_CRU_BASE + 0xa00)
++#define RK3588_B1_PLL_CON(x)		((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE)
++#define RK3588_BIGCORE1_CLKSEL_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x300)
++#define RK3588_BIGCORE1_CLKGATE_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0x800)
++#define RK3588_BIGCORE1_SOFTRST_CON(x)	((x) * 0x4 + RK3588_BIGCORE1_CRU_BASE + 0xa00)
++#define RK3588_LPLL_CON(x)		((x) * 0x4 + RK3588_DSU_CRU_BASE)
++#define RK3588_DSU_CLKSEL_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x300)
++#define RK3588_DSU_CLKGATE_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0x800)
++#define RK3588_DSU_SOFTRST_CON(x)	((x) * 0x4 + RK3588_DSU_CRU_BASE + 0xa00)
++
+ enum rockchip_pll_type {
+ 	pll_rk3036,
+ 	pll_rk3066,
+@@ -394,7 +439,7 @@ struct rockchip_cpuclk_clksel {
+ 	u32 val;
+ };
+ 
+-#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	5
++#define ROCKCHIP_CPUCLK_NUM_DIVIDERS	6
+ #define ROCKCHIP_CPUCLK_MAX_CORES	4
+ struct rockchip_cpuclk_rate_table {
+ 	unsigned long prate;
+@@ -978,4 +1023,6 @@ static inline void rockchip_register_sof
+ 	return rockchip_register_softrst_lut(np, NULL, num_regs, base, flags);
+ }
+ 
++void rk3588_rst_init(struct device_node *np, void __iomem *reg_base);
++
+ #endif
+--- /dev/null
++++ b/drivers/clk/rockchip/rst-rk3588.c
+@@ -0,0 +1,857 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2022 Collabora Ltd.
++ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
++ */
++
++#include <linux/module.h>
++#include <linux/of.h>
++#include <dt-bindings/reset/rockchip,rk3588-cru.h>
++#include "clk.h"
++
++/* 0xFD7C0000 + 0x0A00 */
++#define RK3588_CRU_RESET_OFFSET(id, reg, bit) [id] = (0 + reg * 16 + bit)
++
++/* 0xFD7C8000 + 0x0A00 */
++#define RK3588_PHPTOPCRU_RESET_OFFSET(id, reg, bit) [id] = (0x8000*4 + reg * 16 + bit)
++
++/* 0xFD7D0000 + 0x0A00 */
++#define RK3588_SECURECRU_RESET_OFFSET(id, reg, bit) [id] = (0x10000*4 + reg * 16 + bit)
++
++/* 0xFD7F0000 + 0x0A00 */
++#define RK3588_PMU1CRU_RESET_OFFSET(id, reg, bit) [id] = (0x30000*4 + reg * 16 + bit)
++
++/* mapping table for reset ID to register offset */
++static const int rk3588_register_offset[] = {
++	/* SOFTRST_CON01 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_BIU, 1, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_TOP_BIU, 1, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY0, 1, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIPHY0, 1, 7), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSIPHY1, 1, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIPHY1, 1, 9), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M500_BIU, 1, 15),
++
++	/* SOFTRST_CON02 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M400_BIU, 2, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S200_BIU, 2, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_S400_BIU, 2, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_TOP_M300_BIU, 2, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_INIT, 2, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_CMN, 2, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LANE, 2, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS, 2, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_INIT, 2, 15),
++
++	/* SOFTRST_CON03 */
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_CMN, 3, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LANE, 3, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS, 3, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_DCPHY0, 3, 11), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0, 3, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY0_GRF, 3, 15),
++
++	/* SOFTRST_CON04 */
++	RK3588_CRU_RESET_OFFSET(SRST_DCPHY1, 4, 0), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1, 4, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_MIPI_DCPHY1_GRF, 4, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CDPHY, 4, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CSIPHY, 4, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO3_5, 4, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_VCCIO6, 4, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_EMMCIO, 4, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_TOP, 4, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_IOC_RIGHT, 4, 11),
++
++	/* SOFTRST_CON05 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_CRU, 5, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2VO1USB, 5, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_CHANNEL_SECURE2CENTER, 5, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2VO1USB, 5, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_H_CHANNEL_SECURE2CENTER, 5, 15),
++
++	/* SOFTRST_CON06 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2VO1USB, 6, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CHANNEL_SECURE2CENTER, 6, 1),
++
++	/* SOFTRST_CON07 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_AUDIO_BIU, 7, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_AUDIO_BIU, 7, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S0_8CH, 7, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_TX, 7, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S0_8CH_RX, 7, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_ACDCDIG, 7, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S2_2CH, 7, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S3_2CH, 7, 13),
++
++	/* SOFTRST_CON08 */
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S2_2CH, 8, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S3_2CH, 8, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_DAC_ACDCDIG, 8, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF0, 8, 14),
++
++	/* SOFTRST_CON09 */
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF0, 9, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF1, 9, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF1, 9, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_H_PDM1, 9, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_PDM1, 9, 7),
++
++	/* SOFTRST_CON10 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_BUS_BIU, 10, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_BUS_BIU, 10, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_GIC, 10, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_A_GIC_DBG, 10, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DMAC0, 10, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DMAC1, 10, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DMAC2, 10, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C1, 10, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C2, 10, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C3, 10, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C4, 10, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C5, 10, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C6, 10, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C7, 10, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_I2C8, 10, 15),
++
++	/* SOFTRST_CON11 */
++	RK3588_CRU_RESET_OFFSET(SRST_I2C1, 11, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C2, 11, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C3, 11, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C4, 11, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C5, 11, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C6, 11, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C7, 11, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_I2C8, 11, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CAN0, 11, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_CAN0, 11, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CAN1, 11, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_CAN1, 11, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CAN2, 11, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_CAN2, 11, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SARADC, 11, 14),
++
++	/* SOFTRST_CON12 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_TSADC, 12, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_TSADC, 12, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART1, 12, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART2, 12, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART3, 12, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART4, 12, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART5, 12, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART6, 12, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART7, 12, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART8, 12, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_UART9, 12, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART1, 12, 13),
++
++	/* SOFTRST_CON13 */
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART2, 13, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART3, 13, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART4, 13, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART5, 13, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART6, 13, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART7, 13, 15),
++
++	/* SOFTRST_CON14 */
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART8, 14, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_S_UART9, 14, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SPI0, 14, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SPI1, 14, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SPI2, 14, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SPI3, 14, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SPI4, 14, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_SPI0, 14, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_SPI1, 14, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_SPI2, 14, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_SPI3, 14, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_SPI4, 14, 15),
++
++	/* SOFTRST_CON15 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_WDT0, 15, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_T_WDT0, 15, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SYS_GRF, 15, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PWM1, 15, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_PWM1, 15, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PWM2, 15, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_PWM2, 15, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PWM3, 15, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_PWM3, 15, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER0, 15, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_BUSTIMER1, 15, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER0, 15, 15),
++
++	/* SOFTRST_CON16 */
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER1, 16, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER2, 16, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER3, 16, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER4, 16, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER5, 16, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER6, 16, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER7, 16, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER8, 16, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER9, 16, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER10, 16, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_BUSTIMER11, 16, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX0, 16, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX1, 16, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_MAILBOX2, 16, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPIO1, 16, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_GPIO1, 16, 15),
++
++	/* SOFTRST_CON17 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPIO2, 17, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_GPIO2, 17, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPIO3, 17, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_GPIO3, 17, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPIO4, 17, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_GPIO4, 17, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DECOM, 17, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DECOM, 17, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_D_DECOM, 17, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_TOP, 17, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_A_GICADB_GIC2CORE_BUS, 17, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DFT2APB, 17, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_TOP, 17, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CDPHY, 17, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_BOT_RIGHT, 17, 15),
++
++	/* SOFTRST_CON18 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_TOP, 18, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_IOC_RIGHT, 18, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_CSIPHY, 18, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO3_5, 18, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_VCCIO6, 18, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_MST_EMMCIO, 18, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_SPINLOCK, 18, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_OTPC_NS, 18, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_OTPC_NS, 18, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_OTPC_ARB, 18, 11),
++
++	/* SOFTRST_CON19 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_BUSIOC, 19, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PMUCM0_INTMUX, 19, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDRCM0_INTMUX, 19, 5),
++
++	/* SOFTRST_CON20 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH0, 20, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH0, 20, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH0, 20, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH0, 20, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH0, 20, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH01, 20, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_DFI_CH0, 20, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_SBR_CH0, 20, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH0, 20, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH0, 20, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH0, 20, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH0, 20, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH0, 20, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH1, 20, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH1, 20, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH1, 20, 15),
++
++	/* SOFTRST_CON21 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH1, 21, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH1, 21, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_DFI_CH1, 21, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_SBR_CH1, 21, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH1, 21, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH1, 21, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH1, 21, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH1, 21, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH1, 21, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH0, 21, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH0, 21, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH0, 21, 15),
++
++	/* SOFTRST_CON22 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE0, 22, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE0, 22, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_MSCH1, 22, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_RS_MSCH1, 22, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_MSCH1, 22, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_SCRAMBLE1, 22, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR01_FRS_SCRAMBLE1, 22, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH0, 22, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR01_MSCH1, 22, 8),
++
++	/* SOFTRST_CON23 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH2, 23, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH2, 23, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH2, 23, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH2, 23, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH2, 23, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_GRF_CH23, 23, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_DFI_CH2, 23, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_SBR_CH2, 23, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH2, 23, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH2, 23, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH2, 23, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH2, 23, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH2, 23, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_DFICTL_CH3, 23, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_MON_CH3, 23, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_STANDBY_CH3, 23, 15),
++
++	/* SOFTRST_CON24 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR_UPCTL_CH3, 24, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_TM_DDR_MON_CH3, 24, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_DFI_CH3, 24, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_SBR_CH3, 24, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_UPCTL_CH3, 24, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_DFICTL_CH3, 24, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_MON_CH3, 24, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_STANDBY_CH3, 24, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_UPCTL_CH3, 24, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH2, 24, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH2, 24, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH2, 24, 15),
++
++	/* SOFTRST_CON25 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE2, 25, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE2, 25, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_MSCH3, 25, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_RS_MSCH3, 25, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_MSCH3, 25, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_SCRAMBLE3, 25, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR23_FRS_SCRAMBLE3, 25, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH2, 25, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DDR23_MSCH3, 25, 8),
++
++	/* SOFTRST_CON26 */
++	RK3588_CRU_RESET_OFFSET(SRST_ISP1, 26, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_ISP1_VICAP, 26, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_ISP1_BIU, 26, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_H_ISP1_BIU, 26, 8),
++
++	/* SOFTRST_CON27 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1, 27, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN1_BIU, 27, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1, 27, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKNN1_BIU, 27, 3),
++
++	/* SOFTRST_CON28 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2, 28, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN2_BIU, 28, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2, 28, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKNN2_BIU, 28, 3),
++
++	/* SOFTRST_CON29 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN_DSU0, 29, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_NPUTOP_BIU, 29, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_NPU_TIMER, 29, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER0, 29, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_NPUTIMER1, 29, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_NPU_WDT, 29, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_T_NPU_WDT, 29, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_NPU_PVTM, 29, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_NPU_GRF, 29, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTM, 29, 14),
++
++	/* SOFTRST_CON30 */
++	RK3588_CRU_RESET_OFFSET(SRST_NPU_PVTPLL, 30, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_H_NPU_CM0_BIU, 30, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_F_NPU_CM0_CORE, 30, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_T_NPU_CM0_JTAG, 30, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0, 30, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKNN0_BIU, 30, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0, 30, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKNN0_BIU, 30, 9),
++
++	/* SOFTRST_CON31 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_NVM_BIU, 31, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_NVM_BIU, 31, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_EMMC, 31, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_EMMC, 31, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_C_EMMC, 31, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_B_EMMC, 31, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_T_EMMC, 31, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_S_SFC, 31, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SFC, 31, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SFC_XIP, 31, 11),
++
++	/* SOFTRST_CON32 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_GRF, 32, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DEC_BIU, 32, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PHP_BIU, 32, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_GRIDGE, 32, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_PHP_BIU, 32, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_A_GMAC0, 32, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_A_GMAC1, 32, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_A_PCIE_BIU, 32, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_PCIE0_POWER_UP, 32, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_PCIE1_POWER_UP, 32, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_PCIE2_POWER_UP, 32, 15),
++
++	/* SOFTRST_CON33 */
++	RK3588_CRU_RESET_OFFSET(SRST_PCIE3_POWER_UP, 33, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_PCIE4_POWER_UP, 33, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PCIE0, 33, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PCIE1, 33, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PCIE2, 33, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_PCIE3, 33, 15),
++
++	/* SOFTRST_CON34 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_PCIE4, 34, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_A_PHP_GIC_ITS, 34, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PCIE, 34, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_MMU_PHP, 34, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_MMU_BIU, 34, 9),
++
++	/* SOFTRST_CON35 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG2, 35, 7),
++
++	/* SOFTRST_CON37 */
++	RK3588_CRU_RESET_OFFSET(SRST_PMALIVE0, 37, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_PMALIVE1, 37, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_PMALIVE2, 37, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_SATA0, 37, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_SATA1, 37, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_SATA2, 37, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_RXOOB0, 37, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_RXOOB1, 37, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_RXOOB2, 37, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_ASIC0, 37, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_ASIC1, 37, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_ASIC2, 37, 15),
++
++	/* SOFTRST_CON40 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC_CCU, 40, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0, 40, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0, 40, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC0_BIU, 40, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC0_BIU, 40, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CA, 40, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_HEVC_CA, 40, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC0_CORE, 40, 9),
++
++	/* SOFTRST_CON41 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1, 41, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1, 41, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVDEC1_BIU, 41, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVDEC1_BIU, 41, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CA, 41, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_HEVC_CA, 41, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVDEC1_CORE, 41, 8),
++
++	/* SOFTRST_CON42 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_USB_BIU, 42, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_H_USB_BIU, 42, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG0, 42, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_USB3OTG1, 42, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HOST0, 42, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB0, 42, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HOST1, 42, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HOST_ARB1, 42, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_A_USB_GRF, 42, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST0, 42, 15),
++
++	/* SOFTRST_CON43 */
++	RK3588_CRU_RESET_OFFSET(SRST_C_USB2P0_HOST1, 43, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI0, 43, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_HOST_UTMI1, 43, 2),
++
++	/* SOFTRST_CON44 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_BIU, 44, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_VDPU_LOW_BIU, 44, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VDPU_BIU, 44, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER_BIU, 44, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_VPU, 44, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VPU, 44, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER0, 44, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER0, 44, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER1, 44, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER1, 44, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER2, 44, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER2, 44, 15),
++
++	/* SOFTRST_CON45 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_ENCODER3, 45, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_ENCODER3, 45, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_A_JPEG_DECODER, 45, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_H_JPEG_DECODER, 45, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_IEP2P0, 45, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_IEP2P0, 45, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_IEP2P0_CORE, 45, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RGA2, 45, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RGA2, 45, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_RGA2_CORE, 45, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_0, 45, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_0, 45, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_RGA3_0_CORE, 45, 12),
++
++	/* SOFTRST_CON47 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0_BIU, 47, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0_BIU, 47, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC0, 47, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC0, 47, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVENC0_CORE, 47, 6),
++
++	/* SOFTRST_CON48 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1_BIU, 48, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1_BIU, 48, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RKVENC1, 48, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RKVENC1, 48, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_RKVENC1_CORE, 48, 6),
++
++	/* SOFTRST_CON49 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_VI_BIU, 49, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VI_BIU, 49, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VI_BIU, 49, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_D_VICAP, 49, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_VICAP, 49, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VICAP, 49, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_ISP0, 49, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_ISP0_VICAP, 49, 11),
++
++	/* SOFTRST_CON50 */
++	RK3588_CRU_RESET_OFFSET(SRST_FISHEYE0, 50, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_FISHEYE1, 50, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_0, 50, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_1, 50, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_2, 50, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_3, 50, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_4, 50, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CSI_HOST_5, 50, 9),
++
++	/* SOFTRST_CON51 */
++	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST0_VICAP, 51, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST1_VICAP, 51, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST2_VICAP, 51, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST3_VICAP, 51, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST4_VICAP, 51, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_CSIHOST5_VICAP, 51, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_CIFIN, 51, 13),
++
++	/* SOFTRST_CON52 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_VOP_BIU, 52, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_VOP_LOW_BIU, 52, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VOP_BIU, 52, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VOP_BIU, 52, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VOP, 52, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_VOP, 52, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_D_VOP0, 52, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE0, 52, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_D_VOP2HDMI_BRIDGE1, 52, 15),
++
++	/* SOFTRST_CON53 */
++	RK3588_CRU_RESET_OFFSET(SRST_D_VOP1, 53, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_D_VOP2, 53, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_D_VOP3, 53, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VOPGRF, 53, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST0, 53, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DSIHOST1, 53, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_DSIHOST0, 53, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_DSIHOST1, 53, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_VOP_PMU, 53, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VOP_CHANNEL_BIU, 53, 9),
++
++	/* SOFTRST_CON55 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_VO0_BIU, 55, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VO0_S_BIU, 55, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VO0_BIU, 55, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VO0_S_BIU, 55, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0_BIU, 55, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VO0GRF, 55, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY0, 55, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_A_HDCP0, 55, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HDCP0, 55, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_HDCP0, 55, 15),
++
++	/* SOFTRST_CON56 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_TRNG0, 56, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_DP0, 56, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_DP1, 56, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S4_8CH, 56, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S4_8CH_TX, 56, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S8_8CH, 56, 14),
++
++	/* SOFTRST_CON57 */
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S8_8CH_TX, 57, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF2_DP0, 57, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF2_DP0, 57, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF5_DP1, 57, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF5_DP1, 57, 11),
++
++	/* SOFTRST_CON59 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1_BIU, 59, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_VO1_BIU, 59, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_BIU, 59, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VOP1_S_BIU, 59, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VOP1_BIU, 59, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VO1GRF, 59, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_VO1_S_BIU, 59, 13),
++
++	/* SOFTRST_CON60 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S7_8CH, 60, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S7_8CH_RX, 60, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HDCP_KEY1, 60, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_HDCP1, 60, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_H_HDCP1, 60, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_HDCP1, 60, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_TRNG1, 60, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX0, 60, 11),
++
++	/* SOFTRST_CON61 */
++	RK3588_CRU_RESET_OFFSET(SRST_HDMITX0_REF, 61, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_HDMITX1, 61, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_HDMITX1_REF, 61, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_HDMIRX, 61, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_HDMIRX, 61, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_HDMIRX_REF, 61, 11),
++
++	/* SOFTRST_CON62 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_EDP0, 62, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_EDP0_24M, 62, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_EDP1, 62, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_EDP1_24M, 62, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S5_8CH_TX, 62, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S5_8CH, 62, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_TX, 62, 15),
++
++	/* SOFTRST_CON63 */
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S6_8CH_RX, 63, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S6_8CH, 63, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF3, 63, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF3, 63, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIF4, 63, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIF4, 63, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX0, 63, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX0, 63, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX1, 63, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX1, 63, 15),
++
++	/* SOFTRST_CON64 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_SPDIFRX2, 64, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_M_SPDIFRX2, 64, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY0, 64, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_LINKSYM_HDMITXPHY1, 64, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE0, 64, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_VO1_BRIDGE1, 64, 15),
++
++	/* SOFTRST_CON65 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S9_8CH, 65, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S9_8CH_RX, 65, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_I2S10_8CH, 65, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_M_I2S10_8CH_RX, 65, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_S_HDMIRX, 65, 8),
++
++	/* SOFTRST_CON66 */
++	RK3588_CRU_RESET_OFFSET(SRST_GPU, 66, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_SYS_GPU, 66, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_S_GPU_BIU, 66, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_A_M0_GPU_BIU, 66, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_A_M1_GPU_BIU, 66, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_A_M2_GPU_BIU, 66, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_A_M3_GPU_BIU, 66, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPU_BIU, 66, 14),
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPU_PVTM, 66, 15),
++
++	/* SOFTRST_CON67 */
++	RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTM, 67, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_P_GPU_GRF, 67, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_GPU_PVTPLL, 67, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_GPU_JTAG, 67, 4),
++
++	/* SOFTRST_CON68 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_AV1_BIU, 68, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_A_AV1, 68, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_AV1_BIU, 68, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_AV1, 68, 5),
++
++	/* SOFTRST_CON69 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_BIU, 69, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DMA2DDR, 69, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM, 69, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_A_DDR_SHAREMEM_BIU, 69, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S200_BIU, 69, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_A_CENTER_S400_BIU, 69, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_H_AHB2APB, 69, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_H_CENTER_BIU, 69, 13),
++	RK3588_CRU_RESET_OFFSET(SRST_F_DDR_CM0_CORE, 69, 14),
++
++	/* SOFTRST_CON70 */
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER0, 70, 0),
++	RK3588_CRU_RESET_OFFSET(SRST_DDR_TIMER1, 70, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_T_WDT_DDR, 70, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_T_DDR_CM0_JTAG, 70, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_GRF, 70, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_AHB2APB, 70, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_WDT, 70, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_TIMER, 70, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_DMA2DDR, 70, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_SHAREMEM, 70, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_BIU, 70, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_P_CENTER_CHANNEL_BIU, 70, 12),
++
++	/* SOFTRST_CON72 */
++	RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF0, 72, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY0, 72, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USBDPGRF1, 72, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USBDPPHY1, 72, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX0, 72, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_P_HDPTX1, 72, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_BOT_RIGHT, 72, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_0_GRF0, 72, 8),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U3_1_GRF0, 72, 9),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_0_GRF0, 72, 10),
++	RK3588_CRU_RESET_OFFSET(SRST_P_USB2PHY_U2_1_GRF0, 72, 11),
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_ROPLL, 72, 12), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_LCPLL, 72, 13), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX0, 72, 14), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_ROPLL, 72, 15), // missing in TRM
++
++	/* SOFTRST_CON73 */
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX1_LCPLL, 73, 0), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX1, 73, 1), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_HDPTX0_HDMIRXPHY_SET, 73, 2), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0, 73, 3), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_LCPLL, 73, 4), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_ROPLL, 73, 5), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY0_PCS_HS, 73, 6), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1, 73, 7), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_LCPLL, 73, 8), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_ROPLL, 73, 9), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_USBDP_COMBO_PHY1_PCS_HS, 73, 10), // missing in TRM
++	RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP0, 73, 12),
++	RK3588_CRU_RESET_OFFSET(SRST_HDMIHDP1, 73, 13),
++
++	/* SOFTRST_CON74 */
++	RK3588_CRU_RESET_OFFSET(SRST_A_VO1USB_TOP_BIU, 74, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_H_VO1USB_TOP_BIU, 74, 3),
++
++	/* SOFTRST_CON75 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_SDIO_BIU, 75, 1),
++	RK3588_CRU_RESET_OFFSET(SRST_H_SDIO, 75, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_SDIO, 75, 3),
++
++	/* SOFTRST_CON76 */
++	RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_BIU, 76, 2),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_BIU, 76, 3),
++	RK3588_CRU_RESET_OFFSET(SRST_H_RGA3_1, 76, 4),
++	RK3588_CRU_RESET_OFFSET(SRST_A_RGA3_1, 76, 5),
++	RK3588_CRU_RESET_OFFSET(SRST_RGA3_1_CORE, 76, 6),
++
++	/* SOFTRST_CON77 */
++	RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY0, 77, 6),
++	RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY1, 77, 7),
++	RK3588_CRU_RESET_OFFSET(SRST_REF_PIPE_PHY2, 77, 8),
++
++	/* PHPTOPCRU_SOFTRST_CON00 */
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PHPTOP_CRU, 0, 1),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF0, 0, 2),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF1, 0, 3),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_GRF2, 0, 4),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY0, 0, 5),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY1, 0, 6),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE2_PHY2, 0, 7),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_PCIE3_PHY, 0, 8),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_P_APB2ASB_SLV_CHIP_TOP, 0, 9),
++	RK3588_PHPTOPCRU_RESET_OFFSET(SRST_PCIE30_PHY, 0, 10),
++
++	/* PMU1CRU_SOFTRST_CON00 */
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU1_BIU, 0, 10),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_BIU, 0, 11),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PMU_CM0_BIU, 0, 12),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_F_PMU_CM0_CORE, 0, 13),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1_CM0_JTAG, 0, 14),
++
++	/* PMU1CRU_SOFTRST_CON01 */
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_DDR_FAIL_SAFE, 1, 1),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_CRU_PMU1, 1, 2),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_GRF, 1, 4),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1_IOC, 1, 5),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1WDT, 1, 6),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_T_PMU1WDT, 1, 7),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1TIMER, 1, 8),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER0, 1, 10),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1TIMER1, 1, 11),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU1PWM, 1, 12),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_PMU1PWM, 1, 13),
++
++	/* PMU1CRU_SOFTRST_CON02 */
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_I2C0, 2, 1),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_I2C0, 2, 2),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_S_UART0, 2, 5),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_UART0, 2, 6),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_I2S1_8CH, 2, 7),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_TX, 2, 10),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_M_I2S1_8CH_RX, 2, 13),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_PDM0, 2, 14),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_PDM0, 2, 15),
++
++	/* PMU1CRU_SOFTRST_CON03 */
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_H_VAD, 3, 0),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_INIT, 3, 11),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_CMN, 3, 12),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX0_LANE, 3, 13),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_INIT, 3, 15),
++
++	/* PMU1CRU_SOFTRST_CON04 */
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_CMN, 4, 0),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_HDPTX1_LANE, 4, 1),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY0, 4, 3),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY0, 4, 4),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_M_MIPI_DCPHY1, 4, 5),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_S_MIPI_DCPHY1, 4, 6),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_0, 4, 7),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U3_1, 4, 8),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_0, 4, 9),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_OTGPHY_U2_1, 4, 10),
++
++	/* PMU1CRU_SOFTRST_CON05 */
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0GRF, 5, 3),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_PMU0IOC, 5, 4),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_P_GPIO0, 5, 5),
++	RK3588_PMU1CRU_RESET_OFFSET(SRST_GPIO0, 5, 6),
++
++	/* SECURECRU_SOFTRST_CON00 */
++	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_NS_BIU, 0, 10),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_NS_BIU, 0, 11),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_A_SECURE_S_BIU, 0, 12),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SECURE_S_BIU, 0, 13),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_P_SECURE_S_BIU, 0, 14),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_CORE, 0, 15),
++
++	/* SECURECRU_SOFTRST_CON01 */
++	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_PKA, 1, 0),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_CRYPTO_RNG, 1, 1),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_A_CRYPTO, 1, 2),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_CRYPTO, 1, 3),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_CORE, 1, 9),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_KEYLADDER_RNG, 1, 10),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_A_KEYLADDER, 1, 11),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_KEYLADDER, 1, 12),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_P_OTPC_S, 1, 13),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_OTPC_S, 1, 14),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_WDT_S, 1, 15),
++
++	/* SECURECRU_SOFTRST_CON02 */
++	RK3588_SECURECRU_RESET_OFFSET(SRST_T_WDT_S, 2, 0),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM, 2, 1),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_A_DCF, 2, 2),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_P_DCF, 2, 3),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_BOOTROM_NS, 2, 5),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_P_KEYLADDER, 2, 14),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_S, 2, 15),
++
++	/* SECURECRU_SOFTRST_CON03 */
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_TRNG_NS, 3, 0),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_D_SDMMC_BUFFER, 3, 1),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC, 3, 2),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_H_SDMMC_BUFFER, 3, 3),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_SDMMC, 3, 4),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_P_TRNG_CHK, 3, 5),
++	RK3588_SECURECRU_RESET_OFFSET(SRST_TRNG_S, 3, 6),
++};
++
++void rk3588_rst_init(struct device_node *np, void __iomem *reg_base)
++{
++	rockchip_register_softrst_lut(np,
++				      rk3588_register_offset,
++				      ARRAY_SIZE(rk3588_register_offset),
++				      reg_base + RK3588_SOFTRST_CON(0),
++				      ROCKCHIP_SOFTRST_HIWORD_MASK);
++}
diff --git a/target/linux/rockchip/patches-6.1/221-clk-Remove-a-useless-include.patch b/target/linux/rockchip/patches-6.1/221-clk-Remove-a-useless-include.patch
new file mode 100644
index 00000000000..0ca940e8402
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/221-clk-Remove-a-useless-include.patch
@@ -0,0 +1,29 @@
+From 78b56785a0fa785077c8f2ec896140d2cba8cc8a Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sat, 12 Nov 2022 22:43:03 +0100
+Subject: [PATCH 221/383] clk: Remove a useless include
+
+<linux/rational.h> is not needed for these drivers. Remove the
+corresponding #include.
+
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Link: https://lore.kernel.org/r/12dd5cb49efa7714f8e0389e4c7b3bc829e8a90e.1668289299.git.christophe.jaillet@wanadoo.fr
+Acked-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Jerome Brunet <jbrunet@baylibre.com>
+Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -21,7 +21,6 @@
+ #include <linux/mfd/syscon.h>
+ #include <linux/regmap.h>
+ #include <linux/reboot.h>
+-#include <linux/rational.h>
+ 
+ #include "../clk-fractional-divider.h"
+ #include "clk.h"
diff --git a/target/linux/rockchip/patches-6.1/222-clk-rockchip-Remove-values-for-mmask-and-nmask-in-st.patch b/target/linux/rockchip/patches-6.1/222-clk-rockchip-Remove-values-for-mmask-and-nmask-in-st.patch
new file mode 100644
index 00000000000..a5b4811da91
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/222-clk-rockchip-Remove-values-for-mmask-and-nmask-in-st.patch
@@ -0,0 +1,31 @@
+From f16649f16a9c7321897bf4b11a6b3f78f97a76f8 Mon Sep 17 00:00:00 2001
+From: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Date: Sun, 2 Apr 2023 11:42:06 +0200
+Subject: [PATCH 222/383] clk: rockchip: Remove values for mmask and nmask in
+ struct clk_fractional_divider
+
+Now that fractional_divider clk computes mmask and nmask when needed, there
+is no more need to provide them explicitly anymore.
+
+Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
+Link: https://lore.kernel.org/r/58e1950566e40e2fbb31004baee57a164ca6a390.1680423909.git.christophe.jaillet@wanadoo.fr
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Stephen Boyd <sboyd@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/clk/rockchip/clk.c
++++ b/drivers/clk/rockchip/clk.c
+@@ -244,10 +244,8 @@ static struct clk *rockchip_clk_register
+ 	div->reg = base + muxdiv_offset;
+ 	div->mshift = 16;
+ 	div->mwidth = 16;
+-	div->mmask = GENMASK(div->mwidth - 1, 0) << div->mshift;
+ 	div->nshift = 0;
+ 	div->nwidth = 16;
+-	div->nmask = GENMASK(div->nwidth - 1, 0) << div->nshift;
+ 	div->lock = lock;
+ 	div->approximation = rockchip_fractional_approximation;
+ 	div_ops = &clk_fractional_divider_ops;
diff --git a/target/linux/rockchip/patches-6.1/223-clk-rockchip-rk3588-make-gate-linked-clocks-critical.patch b/target/linux/rockchip/patches-6.1/223-clk-rockchip-rk3588-make-gate-linked-clocks-critical.patch
new file mode 100644
index 00000000000..4b7f23ada16
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/223-clk-rockchip-rk3588-make-gate-linked-clocks-critical.patch
@@ -0,0 +1,150 @@
+From 08a92df3f5afe34c5115709fe3e77572989b5d93 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Apr 2023 21:32:49 +0200
+Subject: [PATCH 223/383] clk: rockchip: rk3588: make gate linked clocks
+ critical
+
+RK3588 has a couple of hardware blocks called Native Interface Unit
+(NIU) that gate the clocks to devices behind them. Effectively this
+means that some clocks require two parent clocks being enabled.
+Downstream implemented this by using a separate clock driver
+("clk-link") for them, which enables the second clock using PM
+framework.
+
+In the upstream kernel we are currently missing support for the second
+parent. The information about it is in the GATE_LINK() macro as
+linkname, but that is not used. Thus the second parent clock is not
+properly enabled. So far this did not really matter, since these clocks
+are mostly required for the more advanced IP blocks, that are not yet
+supported upstream. As this is about to change we need a fix. There
+are three options available:
+
+1. Properly implement support for having two parent clocks in the
+   clock framework.
+2. Mark the affected clocks CLK_IGNORE_UNUSED, so that they are not
+   disabled. This wastes some power, but keeps the hack contained
+   within the clock driver. Going from this to the first solution
+   is easy once that has been implemented.
+3. Enabling the extra clock in the consumer driver. This leaks some
+   implementation details into DT.
+
+This patch implements the second option as an intermediate solution
+until the first one is available. I used an alias for CLK_IS_CRITICAL,
+so that it's easy to see which clocks are not really critical once
+the clock framework supports a better way to implement this.
+
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230403193250.108693-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/rockchip/clk-rk3588.c | 42 +++++++++++++++++++------------
+ 1 file changed, 26 insertions(+), 16 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -13,15 +13,25 @@
+ #include "clk.h"
+ 
+ /*
+- * GATE with additional linked clock. Downstream enables the linked clock
+- * (via runtime PM) whenever the gate is enabled. The downstream implementation
+- * does this via separate clock nodes for each of the linked gate clocks,
+- * which leaks parts of the clock tree into DT. It is unclear why this is
+- * actually needed and things work without it for simple use cases. Thus
+- * the linked clock is ignored for now.
++ * Recent Rockchip SoCs have a new hardware block called Native Interface
++ * Unit (NIU), which gates clocks to devices behind them. These effectively
++ * need two parent clocks.
++ *
++ * Downstream enables the linked clock via runtime PM whenever the gate is
++ * enabled. This implementation uses separate clock nodes for each of the
++ * linked gate clocks, which leaks parts of the clock tree into DT.
++ *
++ * The GATE_LINK macro instead takes the second parent via 'linkname', but
++ * ignores the information. Once the clock framework is ready to handle it, the
++ * information should be passed on here. But since these clocks are required to
++ * access multiple relevant IP blocks, such as PCIe or USB, we mark all linked
++ * clocks critical until a better solution is available. This will waste some
++ * power, but avoids leaking implementation details into DT or hanging the
++ * system.
+  */
+ #define GATE_LINK(_id, cname, pname, linkname, f, o, b, gf) \
+ 	GATE(_id, cname, pname, f, o, b, gf)
++#define RK3588_LINKED_CLK		CLK_IS_CRITICAL
+ 
+ 
+ #define RK3588_GRF_SOC_STATUS0		0x600
+@@ -1446,7 +1456,7 @@ static struct rockchip_clk_branch rk3588
+ 	COMPOSITE_NODIV(HCLK_NVM_ROOT,  "hclk_nvm_root", mux_200m_100m_50m_24m_p, 0,
+ 			RK3588_CLKSEL_CON(77), 0, 2, MFLAGS,
+ 			RK3588_CLKGATE_CON(31), 0, GFLAGS),
+-	COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, 0,
++	COMPOSITE(ACLK_NVM_ROOT, "aclk_nvm_root", gpll_cpll_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(77), 7, 1, MFLAGS, 2, 5, DFLAGS,
+ 			RK3588_CLKGATE_CON(31), 1, GFLAGS),
+ 	GATE(ACLK_EMMC, "aclk_emmc", "aclk_nvm_root", 0,
+@@ -1675,13 +1685,13 @@ static struct rockchip_clk_branch rk3588
+ 			RK3588_CLKGATE_CON(42), 9, GFLAGS),
+ 
+ 	/* vdpu */
+-	COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, 0,
++	COMPOSITE(ACLK_VDPU_ROOT, "aclk_vdpu_root", gpll_cpll_aupll_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(98), 5, 2, MFLAGS, 0, 5, DFLAGS,
+ 			RK3588_CLKGATE_CON(44), 0, GFLAGS),
+ 	COMPOSITE_NODIV(ACLK_VDPU_LOW_ROOT, "aclk_vdpu_low_root", mux_400m_200m_100m_24m_p, 0,
+ 			RK3588_CLKSEL_CON(98), 7, 2, MFLAGS,
+ 			RK3588_CLKGATE_CON(44), 1, GFLAGS),
+-	COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, 0,
++	COMPOSITE_NODIV(HCLK_VDPU_ROOT, "hclk_vdpu_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(98), 9, 2, MFLAGS,
+ 			RK3588_CLKGATE_CON(44), 2, GFLAGS),
+ 	COMPOSITE(ACLK_JPEG_DECODER_ROOT, "aclk_jpeg_decoder_root", gpll_cpll_aupll_spll_p, 0,
+@@ -1732,9 +1742,9 @@ static struct rockchip_clk_branch rk3588
+ 	COMPOSITE(ACLK_RKVENC0_ROOT, "aclk_rkvenc0_root", gpll_cpll_npll_p, 0,
+ 			RK3588_CLKSEL_CON(102), 7, 2, MFLAGS, 2, 5, DFLAGS,
+ 			RK3588_CLKGATE_CON(47), 1, GFLAGS),
+-	GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", 0,
++	GATE(HCLK_RKVENC0, "hclk_rkvenc0", "hclk_rkvenc0_root", RK3588_LINKED_CLK,
+ 			RK3588_CLKGATE_CON(47), 4, GFLAGS),
+-	GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", 0,
++	GATE(ACLK_RKVENC0, "aclk_rkvenc0", "aclk_rkvenc0_root", RK3588_LINKED_CLK,
+ 			RK3588_CLKGATE_CON(47), 5, GFLAGS),
+ 	COMPOSITE(CLK_RKVENC0_CORE, "clk_rkvenc0_core", gpll_cpll_aupll_npll_p, 0,
+ 			RK3588_CLKSEL_CON(102), 14, 2, MFLAGS, 9, 5, DFLAGS,
+@@ -1744,10 +1754,10 @@ static struct rockchip_clk_branch rk3588
+ 			RK3588_CLKGATE_CON(48), 6, GFLAGS),
+ 
+ 	/* vi */
+-	COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, 0,
++	COMPOSITE(ACLK_VI_ROOT, "aclk_vi_root", gpll_cpll_npll_aupll_spll_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(106), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ 			RK3588_CLKGATE_CON(49), 0, GFLAGS),
+-	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, 0,
++	COMPOSITE_NODIV(HCLK_VI_ROOT, "hclk_vi_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(106), 8, 2, MFLAGS,
+ 			RK3588_CLKGATE_CON(49), 1, GFLAGS),
+ 	COMPOSITE_NODIV(PCLK_VI_ROOT, "pclk_vi_root", mux_100m_50m_24m_p, 0,
+@@ -1919,10 +1929,10 @@ static struct rockchip_clk_branch rk3588
+ 	COMPOSITE(ACLK_VOP_ROOT, "aclk_vop_root", gpll_cpll_dmyaupll_npll_spll_p, 0,
+ 			RK3588_CLKSEL_CON(110), 5, 3, MFLAGS, 0, 5, DFLAGS,
+ 			RK3588_CLKGATE_CON(52), 0, GFLAGS),
+-	COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, 0,
++	COMPOSITE_NODIV(ACLK_VOP_LOW_ROOT, "aclk_vop_low_root", mux_400m_200m_100m_24m_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(110), 8, 2, MFLAGS,
+ 			RK3588_CLKGATE_CON(52), 1, GFLAGS),
+-	COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, 0,
++	COMPOSITE_NODIV(HCLK_VOP_ROOT, "hclk_vop_root", mux_200m_100m_50m_24m_p, RK3588_LINKED_CLK,
+ 			RK3588_CLKSEL_CON(110), 10, 2, MFLAGS,
+ 			RK3588_CLKGATE_CON(52), 2, GFLAGS),
+ 	COMPOSITE_NODIV(PCLK_VOP_ROOT, "pclk_vop_root", mux_100m_50m_24m_p, 0,
+@@ -2425,7 +2435,7 @@ static struct rockchip_clk_branch rk3588
+ 
+ 	GATE_LINK(ACLK_ISP1_PRE, "aclk_isp1_pre", "aclk_isp1_root", "aclk_vi_root", 0, RK3588_CLKGATE_CON(26), 6, GFLAGS),
+ 	GATE_LINK(HCLK_ISP1_PRE, "hclk_isp1_pre", "hclk_isp1_root", "hclk_vi_root", 0, RK3588_CLKGATE_CON(26), 8, GFLAGS),
+-	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", 0, RK3588_CLKGATE_CON(31), 2, GFLAGS),
++	GATE_LINK(HCLK_NVM, "hclk_nvm", "hclk_nvm_root", "aclk_nvm_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(31), 2, GFLAGS),
+ 	GATE_LINK(ACLK_USB, "aclk_usb", "aclk_usb_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 2, GFLAGS),
+ 	GATE_LINK(HCLK_USB, "hclk_usb", "hclk_usb_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(42), 3, GFLAGS),
+ 	GATE_LINK(ACLK_JPEG_DECODER_PRE, "aclk_jpeg_decoder_pre", "aclk_jpeg_decoder_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(44), 7, GFLAGS),
diff --git a/target/linux/rockchip/patches-6.1/224-clk-RK808-Reduce-struct-rk808-usage.patch b/target/linux/rockchip/patches-6.1/224-clk-RK808-Reduce-struct-rk808-usage.patch
new file mode 100644
index 00000000000..a82b1864469
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/224-clk-RK808-Reduce-struct-rk808-usage.patch
@@ -0,0 +1,133 @@
+From 6e19b2ab9946f98ccc425dd102b7390cbfdd0ee2 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:05 +0200
+Subject: [PATCH 224/383] clk: RK808: Reduce 'struct rk808' usage
+
+Reduce usage of 'struct rk808' (driver data of the parent MFD), so
+that only the chip variant field is still being accessed directly.
+This allows restructuring the MFD driver to support SPI based
+PMICs.
+
+Acked-by: Stephen Boyd <sboyd@kernel.org>
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-2-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/clk-rk808.c | 34 ++++++++++++++++------------------
+ 1 file changed, 16 insertions(+), 18 deletions(-)
+
+--- a/drivers/clk/clk-rk808.c
++++ b/drivers/clk/clk-rk808.c
+@@ -12,10 +12,9 @@
+ #include <linux/slab.h>
+ #include <linux/platform_device.h>
+ #include <linux/mfd/rk808.h>
+-#include <linux/i2c.h>
+ 
+ struct rk808_clkout {
+-	struct rk808 *rk808;
++	struct regmap		*regmap;
+ 	struct clk_hw		clkout1_hw;
+ 	struct clk_hw		clkout2_hw;
+ };
+@@ -31,9 +30,8 @@ static int rk808_clkout2_enable(struct c
+ 	struct rk808_clkout *rk808_clkout = container_of(hw,
+ 							 struct rk808_clkout,
+ 							 clkout2_hw);
+-	struct rk808 *rk808 = rk808_clkout->rk808;
+ 
+-	return regmap_update_bits(rk808->regmap, RK808_CLK32OUT_REG,
++	return regmap_update_bits(rk808_clkout->regmap, RK808_CLK32OUT_REG,
+ 				  CLK32KOUT2_EN, enable ? CLK32KOUT2_EN : 0);
+ }
+ 
+@@ -52,10 +50,9 @@ static int rk808_clkout2_is_prepared(str
+ 	struct rk808_clkout *rk808_clkout = container_of(hw,
+ 							 struct rk808_clkout,
+ 							 clkout2_hw);
+-	struct rk808 *rk808 = rk808_clkout->rk808;
+ 	uint32_t val;
+ 
+-	int ret = regmap_read(rk808->regmap, RK808_CLK32OUT_REG, &val);
++	int ret = regmap_read(rk808_clkout->regmap, RK808_CLK32OUT_REG, &val);
+ 
+ 	if (ret < 0)
+ 		return ret;
+@@ -93,9 +90,8 @@ static int rk817_clkout2_enable(struct c
+ 	struct rk808_clkout *rk808_clkout = container_of(hw,
+ 							 struct rk808_clkout,
+ 							 clkout2_hw);
+-	struct rk808 *rk808 = rk808_clkout->rk808;
+ 
+-	return regmap_update_bits(rk808->regmap, RK817_SYS_CFG(1),
++	return regmap_update_bits(rk808_clkout->regmap, RK817_SYS_CFG(1),
+ 				  RK817_CLK32KOUT2_EN,
+ 				  enable ? RK817_CLK32KOUT2_EN : 0);
+ }
+@@ -115,10 +111,9 @@ static int rk817_clkout2_is_prepared(str
+ 	struct rk808_clkout *rk808_clkout = container_of(hw,
+ 							 struct rk808_clkout,
+ 							 clkout2_hw);
+-	struct rk808 *rk808 = rk808_clkout->rk808;
+ 	unsigned int val;
+ 
+-	int ret = regmap_read(rk808->regmap, RK817_SYS_CFG(1), &val);
++	int ret = regmap_read(rk808_clkout->regmap, RK817_SYS_CFG(1), &val);
+ 
+ 	if (ret < 0)
+ 		return 0;
+@@ -153,18 +148,21 @@ static const struct clk_ops *rkpmic_get_
+ static int rk808_clkout_probe(struct platform_device *pdev)
+ {
+ 	struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
+-	struct i2c_client *client = rk808->i2c;
+-	struct device_node *node = client->dev.of_node;
++	struct device *dev = &pdev->dev;
+ 	struct clk_init_data init = {};
+ 	struct rk808_clkout *rk808_clkout;
+ 	int ret;
+ 
+-	rk808_clkout = devm_kzalloc(&client->dev,
++	dev->of_node = pdev->dev.parent->of_node;
++
++	rk808_clkout = devm_kzalloc(dev,
+ 				    sizeof(*rk808_clkout), GFP_KERNEL);
+ 	if (!rk808_clkout)
+ 		return -ENOMEM;
+ 
+-	rk808_clkout->rk808 = rk808;
++	rk808_clkout->regmap = dev_get_regmap(pdev->dev.parent, NULL);
++	if (!rk808_clkout->regmap)
++		return -ENODEV;
+ 
+ 	init.parent_names = NULL;
+ 	init.num_parents = 0;
+@@ -173,10 +171,10 @@ static int rk808_clkout_probe(struct pla
+ 	rk808_clkout->clkout1_hw.init = &init;
+ 
+ 	/* optional override of the clockname */
+-	of_property_read_string_index(node, "clock-output-names",
++	of_property_read_string_index(dev->of_node, "clock-output-names",
+ 				      0, &init.name);
+ 
+-	ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout1_hw);
++	ret = devm_clk_hw_register(dev, &rk808_clkout->clkout1_hw);
+ 	if (ret)
+ 		return ret;
+ 
+@@ -185,10 +183,10 @@ static int rk808_clkout_probe(struct pla
+ 	rk808_clkout->clkout2_hw.init = &init;
+ 
+ 	/* optional override of the clockname */
+-	of_property_read_string_index(node, "clock-output-names",
++	of_property_read_string_index(dev->of_node, "clock-output-names",
+ 				      1, &init.name);
+ 
+-	ret = devm_clk_hw_register(&client->dev, &rk808_clkout->clkout2_hw);
++	ret = devm_clk_hw_register(dev, &rk808_clkout->clkout2_hw);
+ 	if (ret)
+ 		return ret;
+ 
diff --git a/target/linux/rockchip/patches-6.1/225-mfd-rk808-Convert-to-i2c-s-.probe_new.patch b/target/linux/rockchip/patches-6.1/225-mfd-rk808-Convert-to-i2c-s-.probe_new.patch
new file mode 100644
index 00000000000..f84c76ca1ec
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/225-mfd-rk808-Convert-to-i2c-s-.probe_new.patch
@@ -0,0 +1,40 @@
+From 9d6a187a4a0dc45d9eba7c35feb794f82506ae7b Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de>
+Date: Fri, 18 Nov 2022 23:43:07 +0100
+Subject: [PATCH 225/383] mfd: rk808: Convert to i2c's .probe_new()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The probe function doesn't make use of the i2c_device_id * parameter so it
+can be trivially converted.
+
+Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/20221118224540.619276-454-uwe@kleine-koenig.org
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk808.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/mfd/rk808.c
++++ b/drivers/mfd/rk808.c
+@@ -640,8 +640,7 @@ static const struct of_device_id rk808_o
+ };
+ MODULE_DEVICE_TABLE(of, rk808_of_match);
+ 
+-static int rk808_probe(struct i2c_client *client,
+-		       const struct i2c_device_id *id)
++static int rk808_probe(struct i2c_client *client)
+ {
+ 	struct device_node *np = client->dev.of_node;
+ 	struct rk808 *rk808;
+@@ -861,7 +860,7 @@ static struct i2c_driver rk808_i2c_drive
+ 		.of_match_table = rk808_of_match,
+ 		.pm = &rk8xx_pm_ops,
+ 	},
+-	.probe    = rk808_probe,
++	.probe_new = rk808_probe,
+ 	.remove   = rk808_remove,
+ 	.shutdown = rk8xx_shutdown,
+ };
diff --git a/target/linux/rockchip/patches-6.1/226-mfd-rk808-Permit-having-multiple-PMIC-instances.patch b/target/linux/rockchip/patches-6.1/226-mfd-rk808-Permit-having-multiple-PMIC-instances.patch
new file mode 100644
index 00000000000..2921e906ffb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/226-mfd-rk808-Permit-having-multiple-PMIC-instances.patch
@@ -0,0 +1,97 @@
+From 55bd7a34687b34eef66097db33015e65e2a00961 Mon Sep 17 00:00:00 2001
+From: Neil Armstrong <neil.armstrong@linaro.org>
+Date: Mon, 31 Oct 2022 17:05:07 +0100
+Subject: [PATCH 226/383] mfd: rk808: Permit having multiple PMIC instances
+
+This set each cells id to PLATFORM_DEVID_NONE to allow multiple
+instances of each cell in case multiple PMICs handled by the rk808
+driver are probed.
+
+This fixes probing a RK818 and a RK817 on the Odroid Go Ultra
+devices.
+
+Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/20221025-rk808-multi-v2-0-d292d51ada81@linaro.org
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk808.c | 26 ++++++++++++++++----------
+ 1 file changed, 16 insertions(+), 10 deletions(-)
+
+--- a/drivers/mfd/rk808.c
++++ b/drivers/mfd/rk808.c
+@@ -137,58 +137,64 @@ static const struct resource rk817_charg
+ };
+ 
+ static const struct mfd_cell rk805s[] = {
+-	{ .name = "rk808-clkout", },
+-	{ .name = "rk808-regulator", },
+-	{ .name = "rk805-pinctrl", },
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk808-rtc",
+ 		.num_resources = ARRAY_SIZE(rtc_resources),
+ 		.resources = &rtc_resources[0],
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+ 	{	.name = "rk805-pwrkey",
+ 		.num_resources = ARRAY_SIZE(rk805_key_resources),
+ 		.resources = &rk805_key_resources[0],
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+ };
+ 
+ static const struct mfd_cell rk808s[] = {
+-	{ .name = "rk808-clkout", },
+-	{ .name = "rk808-regulator", },
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk808-rtc",
+ 		.num_resources = ARRAY_SIZE(rtc_resources),
+ 		.resources = rtc_resources,
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+ };
+ 
+ static const struct mfd_cell rk817s[] = {
+-	{ .name = "rk808-clkout",},
+-	{ .name = "rk808-regulator",},
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk805-pwrkey",
+ 		.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
+ 		.resources = &rk817_pwrkey_resources[0],
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+ 	{
+ 		.name = "rk808-rtc",
+ 		.num_resources = ARRAY_SIZE(rk817_rtc_resources),
+ 		.resources = &rk817_rtc_resources[0],
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+-	{ .name = "rk817-codec",},
++	{ .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk817-charger",
+ 		.num_resources = ARRAY_SIZE(rk817_charger_resources),
+ 		.resources = &rk817_charger_resources[0],
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+ };
+ 
+ static const struct mfd_cell rk818s[] = {
+-	{ .name = "rk808-clkout", },
+-	{ .name = "rk808-regulator", },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk808-rtc",
+ 		.num_resources = ARRAY_SIZE(rtc_resources),
+ 		.resources = rtc_resources,
++		.id = PLATFORM_DEVID_NONE,
+ 	},
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/227-mfd-rk808-Re-add-rk808-clkout-to-RK818.patch b/target/linux/rockchip/patches-6.1/227-mfd-rk808-Re-add-rk808-clkout-to-RK818.patch
new file mode 100644
index 00000000000..e5c08f7eee9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/227-mfd-rk808-Re-add-rk808-clkout-to-RK818.patch
@@ -0,0 +1,32 @@
+From 89bee42c7d96dc87e65480e9c09502497e9b5ba4 Mon Sep 17 00:00:00 2001
+From: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+Date: Mon, 2 Jan 2023 22:11:47 +1100
+Subject: [PATCH 227/383] mfd: rk808: Re-add rk808-clkout to RK818
+
+Fixes RK818 (e.g. on Pinephone Pro) to register its clock, without which
+dependent devices (e.g. wifi/BT, via sdio-wifi-pwrseq) fail to probe.
+
+This line was removed in commit 3633daacea2e
+("mfd: rk808: Permit having multiple PMIC instances"), but only from RK818.
+
+Fixes: 3633daacea2e ("mfd: rk808: Permit having multiple PMIC instances")
+Signed-off-by: Tom Fitzhenry <tom@tom-fitzhenry.me.uk>
+Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
+Acked-by: Neil Armstrong <neil.armstrong@linaro.org>
+Signed-off-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/20230102111147.2580861-1-tom@tom-fitzhenry.me.uk
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk808.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mfd/rk808.c
++++ b/drivers/mfd/rk808.c
+@@ -189,6 +189,7 @@ static const struct mfd_cell rk817s[] =
+ };
+ 
+ static const struct mfd_cell rk818s[] = {
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+ 	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+ 	{
+ 		.name = "rk808-rtc",
diff --git a/target/linux/rockchip/patches-6.1/228-mfd-rk808-Convert-to-device-managed-resources.patch b/target/linux/rockchip/patches-6.1/228-mfd-rk808-Convert-to-device-managed-resources.patch
new file mode 100644
index 00000000000..f47a667114c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/228-mfd-rk808-Convert-to-device-managed-resources.patch
@@ -0,0 +1,152 @@
+From 26b0b32d2841305856fd7cdf7b6a96badf2c2599 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:06 +0200
+Subject: [PATCH 228/383] mfd: rk808: Convert to device managed resources
+
+Fully convert the driver to device managed resources.
+
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-3-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk808.c | 64 ++++++++++++++++-----------------------------
+ 1 file changed, 22 insertions(+), 42 deletions(-)
+
+--- a/drivers/mfd/rk808.c
++++ b/drivers/mfd/rk808.c
+@@ -548,13 +548,11 @@ static const struct regmap_irq_chip rk81
+ 	.init_ack_masked = true,
+ };
+ 
+-static struct i2c_client *rk808_i2c_client;
+-
+-static void rk808_pm_power_off(void)
++static int rk808_power_off(struct sys_off_data *data)
+ {
++	struct rk808 *rk808 = data->cb_data;
+ 	int ret;
+ 	unsigned int reg, bit;
+-	struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
+ 
+ 	switch (rk808->variant) {
+ 	case RK805_ID:
+@@ -575,16 +573,18 @@ static void rk808_pm_power_off(void)
+ 		bit = DEV_OFF;
+ 		break;
+ 	default:
+-		return;
++		return NOTIFY_DONE;
+ 	}
+ 	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
+ 	if (ret)
+-		dev_err(&rk808_i2c_client->dev, "Failed to shutdown device!\n");
++		dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n");
++
++	return NOTIFY_DONE;
+ }
+ 
+-static int rk808_restart_notify(struct notifier_block *this, unsigned long mode, void *cmd)
++static int rk808_restart(struct sys_off_data *data)
+ {
+-	struct rk808 *rk808 = i2c_get_clientdata(rk808_i2c_client);
++	struct rk808 *rk808 = data->cb_data;
+ 	unsigned int reg, bit;
+ 	int ret;
+ 
+@@ -600,16 +600,11 @@ static int rk808_restart_notify(struct n
+ 	}
+ 	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
+ 	if (ret)
+-		dev_err(&rk808_i2c_client->dev, "Failed to restart device!\n");
++		dev_err(&rk808->i2c->dev, "Failed to restart device!\n");
+ 
+ 	return NOTIFY_DONE;
+ }
+ 
+-static struct notifier_block rk808_restart_handler = {
+-	.notifier_call = rk808_restart_notify,
+-	.priority = 192,
+-};
+-
+ static void rk8xx_shutdown(struct i2c_client *client)
+ {
+ 	struct rk808 *rk808 = i2c_get_clientdata(client);
+@@ -745,9 +740,9 @@ static int rk808_probe(struct i2c_client
+ 		return -EINVAL;
+ 	}
+ 
+-	ret = regmap_add_irq_chip(rk808->regmap, client->irq,
+-				  IRQF_ONESHOT, -1,
+-				  rk808->regmap_irq_chip, &rk808->irq_data);
++	ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq,
++				       IRQF_ONESHOT, -1,
++				       rk808->regmap_irq_chip, &rk808->irq_data);
+ 	if (ret) {
+ 		dev_err(&client->dev, "Failed to add irq_chip %d\n", ret);
+ 		return ret;
+@@ -771,17 +766,23 @@ static int rk808_probe(struct i2c_client
+ 			      regmap_irq_get_domain(rk808->irq_data));
+ 	if (ret) {
+ 		dev_err(&client->dev, "failed to add MFD devices %d\n", ret);
+-		goto err_irq;
++		return ret;
+ 	}
+ 
+ 	if (of_property_read_bool(np, "rockchip,system-power-controller")) {
+-		rk808_i2c_client = client;
+-		pm_power_off = rk808_pm_power_off;
++		ret = devm_register_sys_off_handler(&client->dev,
++				    SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
++				    &rk808_power_off, rk808);
++		if (ret)
++			return dev_err_probe(&client->dev, ret,
++					     "failed to register poweroff handler\n");
+ 
+ 		switch (rk808->variant) {
+ 		case RK809_ID:
+ 		case RK817_ID:
+-			ret = register_restart_handler(&rk808_restart_handler);
++			ret = devm_register_sys_off_handler(&client->dev,
++							    SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
++							    &rk808_restart, rk808);
+ 			if (ret)
+ 				dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
+ 			break;
+@@ -792,26 +793,6 @@ static int rk808_probe(struct i2c_client
+ 	}
+ 
+ 	return 0;
+-
+-err_irq:
+-	regmap_del_irq_chip(client->irq, rk808->irq_data);
+-	return ret;
+-}
+-
+-static void rk808_remove(struct i2c_client *client)
+-{
+-	struct rk808 *rk808 = i2c_get_clientdata(client);
+-
+-	regmap_del_irq_chip(client->irq, rk808->irq_data);
+-
+-	/**
+-	 * pm_power_off may points to a function from another module.
+-	 * Check if the pointer is set by us and only then overwrite it.
+-	 */
+-	if (pm_power_off == rk808_pm_power_off)
+-		pm_power_off = NULL;
+-
+-	unregister_restart_handler(&rk808_restart_handler);
+ }
+ 
+ static int __maybe_unused rk8xx_suspend(struct device *dev)
+@@ -868,7 +849,6 @@ static struct i2c_driver rk808_i2c_drive
+ 		.pm = &rk8xx_pm_ops,
+ 	},
+ 	.probe_new = rk808_probe,
+-	.remove   = rk808_remove,
+ 	.shutdown = rk8xx_shutdown,
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/229-mfd-rk808-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/229-mfd-rk808-Use-dev_err_probe.patch
new file mode 100644
index 00000000000..9dcf7861c25
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/229-mfd-rk808-Use-dev_err_probe.patch
@@ -0,0 +1,104 @@
+From 3b3c8e38f04839777a073b8d049256993c91b469 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:07 +0200
+Subject: [PATCH 229/383] mfd: rk808: Use dev_err_probe
+
+Use dev_err_probe instead of dev_err in probe function,
+which simplifies code a little bit and prints the error
+code.
+
+Also drop possibly incorrect printing of chip id registers
+while touching the error message.
+
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-4-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk808.c | 48 +++++++++++++++------------------------------
+ 1 file changed, 16 insertions(+), 32 deletions(-)
+
+--- a/drivers/mfd/rk808.c
++++ b/drivers/mfd/rk808.c
+@@ -670,18 +670,12 @@ static int rk808_probe(struct i2c_client
+ 
+ 	/* Read chip variant */
+ 	msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
+-	if (msb < 0) {
+-		dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
+-			RK808_ID_MSB);
+-		return msb;
+-	}
++	if (msb < 0)
++		return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n");
+ 
+ 	lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
+-	if (lsb < 0) {
+-		dev_err(&client->dev, "failed to read the chip id at 0x%x\n",
+-			RK808_ID_LSB);
+-		return lsb;
+-	}
++	if (lsb < 0)
++		return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n");
+ 
+ 	rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
+ 	dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
+@@ -730,44 +724,34 @@ static int rk808_probe(struct i2c_client
+ 	i2c_set_clientdata(client, rk808);
+ 
+ 	rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
+-	if (IS_ERR(rk808->regmap)) {
+-		dev_err(&client->dev, "regmap initialization failed\n");
+-		return PTR_ERR(rk808->regmap);
+-	}
++	if (IS_ERR(rk808->regmap))
++		return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap),
++				     "regmap initialization failed\n");
+ 
+-	if (!client->irq) {
+-		dev_err(&client->dev, "No interrupt support, no core IRQ\n");
+-		return -EINVAL;
+-	}
++	if (!client->irq)
++		return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n");
+ 
+ 	ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq,
+ 				       IRQF_ONESHOT, -1,
+ 				       rk808->regmap_irq_chip, &rk808->irq_data);
+-	if (ret) {
+-		dev_err(&client->dev, "Failed to add irq_chip %d\n", ret);
+-		return ret;
+-	}
++	if (ret)
++		return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n");
+ 
+ 	for (i = 0; i < nr_pre_init_regs; i++) {
+ 		ret = regmap_update_bits(rk808->regmap,
+ 					pre_init_reg[i].addr,
+ 					pre_init_reg[i].mask,
+ 					pre_init_reg[i].value);
+-		if (ret) {
+-			dev_err(&client->dev,
+-				"0x%x write err\n",
+-				pre_init_reg[i].addr);
+-			return ret;
+-		}
++		if (ret)
++			return dev_err_probe(&client->dev, ret, "0x%x write err\n",
++					     pre_init_reg[i].addr);
+ 	}
+ 
+ 	ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
+ 			      cells, nr_cells, NULL, 0,
+ 			      regmap_irq_get_domain(rk808->irq_data));
+-	if (ret) {
+-		dev_err(&client->dev, "failed to add MFD devices %d\n", ret);
+-		return ret;
+-	}
++	if (ret)
++		return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n");
+ 
+ 	if (of_property_read_bool(np, "rockchip,system-power-controller")) {
+ 		ret = devm_register_sys_off_handler(&client->dev,
diff --git a/target/linux/rockchip/patches-6.1/230-mfd-rk808-Replace-struct-i2c_client-with-struct-devi.patch b/target/linux/rockchip/patches-6.1/230-mfd-rk808-Replace-struct-i2c_client-with-struct-devi.patch
new file mode 100644
index 00000000000..7ab8dfe1cf4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/230-mfd-rk808-Replace-struct-i2c_client-with-struct-devi.patch
@@ -0,0 +1,61 @@
+From 977a58c38c23b84f60eebc7141d03ab1464ad820 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:08 +0200
+Subject: [PATCH 230/383] mfd: rk808: Replace 'struct i2c_client' with 'struct
+ device'
+
+Put 'struct device' pointer into the MFD platform_data instead
+of the 'struct i2c_client' pointer. This simplifies the code
+and prepares the MFD for SPI support.
+
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-5-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk808.c       | 6 +++---
+ include/linux/mfd/rk808.h | 2 +-
+ 2 files changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/mfd/rk808.c
++++ b/drivers/mfd/rk808.c
+@@ -577,7 +577,7 @@ static int rk808_power_off(struct sys_of
+ 	}
+ 	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
+ 	if (ret)
+-		dev_err(&rk808->i2c->dev, "Failed to shutdown device!\n");
++		dev_err(rk808->dev, "Failed to shutdown device!\n");
+ 
+ 	return NOTIFY_DONE;
+ }
+@@ -600,7 +600,7 @@ static int rk808_restart(struct sys_off_
+ 	}
+ 	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
+ 	if (ret)
+-		dev_err(&rk808->i2c->dev, "Failed to restart device!\n");
++		dev_err(rk808->dev, "Failed to restart device!\n");
+ 
+ 	return NOTIFY_DONE;
+ }
+@@ -720,7 +720,7 @@ static int rk808_probe(struct i2c_client
+ 		return -EINVAL;
+ 	}
+ 
+-	rk808->i2c = client;
++	rk808->dev = &client->dev;
+ 	i2c_set_clientdata(client, rk808);
+ 
+ 	rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
+--- a/include/linux/mfd/rk808.h
++++ b/include/linux/mfd/rk808.h
+@@ -787,7 +787,7 @@ enum {
+ };
+ 
+ struct rk808 {
+-	struct i2c_client		*i2c;
++	struct device			*dev;
+ 	struct regmap_irq_chip_data	*irq_data;
+ 	struct regmap			*regmap;
+ 	long				variant;
diff --git a/target/linux/rockchip/patches-6.1/231-mfd-rk808-Split-into-core-and-i2c.patch b/target/linux/rockchip/patches-6.1/231-mfd-rk808-Split-into-core-and-i2c.patch
new file mode 100644
index 00000000000..5e6e5e65433
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/231-mfd-rk808-Split-into-core-and-i2c.patch
@@ -0,0 +1,1915 @@
+From 913d4f5a3492d221c52d40d7f6d85532cff29a25 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:09 +0200
+Subject: [PATCH 231/383] mfd: rk808: Split into core and i2c
+
+Split rk808 into a core and an i2c part in preparation for
+SPI support.
+
+Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com> # for RTC
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-6-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/Kconfig                   |   2 +-
+ drivers/input/misc/Kconfig            |   2 +-
+ drivers/mfd/Kconfig                   |   7 +-
+ drivers/mfd/Makefile                  |   3 +-
+ drivers/mfd/{rk808.c => rk8xx-core.c} | 209 +++++---------------------
+ drivers/mfd/rk8xx-i2c.c               | 200 ++++++++++++++++++++++++
+ drivers/pinctrl/Kconfig               |   2 +-
+ drivers/power/supply/Kconfig          |   2 +-
+ drivers/regulator/Kconfig             |   2 +-
+ drivers/rtc/Kconfig                   |   2 +-
+ include/linux/mfd/rk808.h             |   6 +
+ sound/soc/codecs/Kconfig              |   2 +-
+ 12 files changed, 256 insertions(+), 183 deletions(-)
+ rename drivers/mfd/{rk808.c => rk8xx-core.c} (76%)
+ create mode 100644 drivers/mfd/rk8xx-i2c.c
+
+--- a/drivers/clk/Kconfig
++++ b/drivers/clk/Kconfig
+@@ -83,7 +83,7 @@ config COMMON_CLK_MAX9485
+ 
+ config COMMON_CLK_RK808
+ 	tristate "Clock driver for RK805/RK808/RK809/RK817/RK818"
+-	depends on MFD_RK808
++	depends on MFD_RK8XX
+ 	help
+ 	  This driver supports RK805, RK809 and RK817, RK808 and RK818 crystal oscillator clock.
+ 	  These multi-function devices have two fixed-rate oscillators, clocked at 32KHz each.
+--- a/drivers/input/misc/Kconfig
++++ b/drivers/input/misc/Kconfig
+@@ -588,7 +588,7 @@ config INPUT_PWM_VIBRA
+ 
+ config INPUT_RK805_PWRKEY
+ 	tristate "Rockchip RK805 PMIC power key support"
+-	depends on MFD_RK808
++	depends on MFD_RK8XX
+ 	help
+ 	  Select this option to enable power key driver for RK805.
+ 
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -1202,12 +1202,17 @@ config MFD_RC5T583
+ 	  Additional drivers must be enabled in order to use the
+ 	  different functionality of the device.
+ 
+-config MFD_RK808
++config MFD_RK8XX
++	bool
++	select MFD_CORE
++
++config MFD_RK8XX_I2C
+ 	tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power Management Chip"
+ 	depends on I2C && OF
+ 	select MFD_CORE
+ 	select REGMAP_I2C
+ 	select REGMAP_IRQ
++	select MFD_RK8XX
+ 	help
+ 	  If you say yes here you get support for the RK805, RK808, RK809,
+ 	  RK817 and RK818 Power Management chips.
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -223,7 +223,8 @@ obj-$(CONFIG_MFD_PALMAS)	+= palmas.o
+ obj-$(CONFIG_MFD_VIPERBOARD)    += viperboard.o
+ obj-$(CONFIG_MFD_NTXEC)		+= ntxec.o
+ obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
+-obj-$(CONFIG_MFD_RK808)		+= rk808.o
++obj-$(CONFIG_MFD_RK8XX)		+= rk8xx-core.o
++obj-$(CONFIG_MFD_RK8XX_I2C)	+= rk8xx-i2c.o
+ obj-$(CONFIG_MFD_RN5T618)	+= rn5t618.o
+ obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
+ obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
+--- a/drivers/mfd/rk808.c
++++ /dev/null
+@@ -1,845 +0,0 @@
+-// SPDX-License-Identifier: GPL-2.0-only
+-/*
+- * MFD core driver for Rockchip RK808/RK818
+- *
+- * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
+- *
+- * Author: Chris Zhong <zyw@rock-chips.com>
+- * Author: Zhang Qing <zhangqing@rock-chips.com>
+- *
+- * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+- *
+- * Author: Wadim Egorov <w.egorov@phytec.de>
+- */
+-
+-#include <linux/i2c.h>
+-#include <linux/interrupt.h>
+-#include <linux/mfd/rk808.h>
+-#include <linux/mfd/core.h>
+-#include <linux/module.h>
+-#include <linux/of_device.h>
+-#include <linux/regmap.h>
+-#include <linux/reboot.h>
+-
+-struct rk808_reg_data {
+-	int addr;
+-	int mask;
+-	int value;
+-};
+-
+-static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
+-{
+-	/*
+-	 * Notes:
+-	 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
+-	 *   we don't use that feature.  It's better to cache.
+-	 * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
+-	 *   bits are cleared in case when we shutoff anyway, but better safe.
+-	 */
+-
+-	switch (reg) {
+-	case RK808_SECONDS_REG ... RK808_WEEKS_REG:
+-	case RK808_RTC_STATUS_REG:
+-	case RK808_VB_MON_REG:
+-	case RK808_THERMAL_REG:
+-	case RK808_DCDC_UV_STS_REG:
+-	case RK808_LDO_UV_STS_REG:
+-	case RK808_DCDC_PG_REG:
+-	case RK808_LDO_PG_REG:
+-	case RK808_DEVCTRL_REG:
+-	case RK808_INT_STS_REG1:
+-	case RK808_INT_STS_REG2:
+-		return true;
+-	}
+-
+-	return false;
+-}
+-
+-static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
+-{
+-	/*
+-	 * Notes:
+-	 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
+-	 *   we don't use that feature.  It's better to cache.
+-	 */
+-
+-	switch (reg) {
+-	case RK817_SECONDS_REG ... RK817_WEEKS_REG:
+-	case RK817_RTC_STATUS_REG:
+-	case RK817_CODEC_DTOP_LPT_SRST:
+-	case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0:
+-	case RK817_PMIC_CHRG_STS:
+-	case RK817_PMIC_CHRG_OUT:
+-	case RK817_PMIC_CHRG_IN:
+-	case RK817_INT_STS_REG0:
+-	case RK817_INT_STS_REG1:
+-	case RK817_INT_STS_REG2:
+-	case RK817_SYS_STS:
+-		return true;
+-	}
+-
+-	return false;
+-}
+-
+-static const struct regmap_config rk818_regmap_config = {
+-	.reg_bits = 8,
+-	.val_bits = 8,
+-	.max_register = RK818_USB_CTRL_REG,
+-	.cache_type = REGCACHE_RBTREE,
+-	.volatile_reg = rk808_is_volatile_reg,
+-};
+-
+-static const struct regmap_config rk805_regmap_config = {
+-	.reg_bits = 8,
+-	.val_bits = 8,
+-	.max_register = RK805_OFF_SOURCE_REG,
+-	.cache_type = REGCACHE_RBTREE,
+-	.volatile_reg = rk808_is_volatile_reg,
+-};
+-
+-static const struct regmap_config rk808_regmap_config = {
+-	.reg_bits = 8,
+-	.val_bits = 8,
+-	.max_register = RK808_IO_POL_REG,
+-	.cache_type = REGCACHE_RBTREE,
+-	.volatile_reg = rk808_is_volatile_reg,
+-};
+-
+-static const struct regmap_config rk817_regmap_config = {
+-	.reg_bits = 8,
+-	.val_bits = 8,
+-	.max_register = RK817_GPIO_INT_CFG,
+-	.cache_type = REGCACHE_NONE,
+-	.volatile_reg = rk817_is_volatile_reg,
+-};
+-
+-static const struct resource rtc_resources[] = {
+-	DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
+-};
+-
+-static const struct resource rk817_rtc_resources[] = {
+-	DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
+-};
+-
+-static const struct resource rk805_key_resources[] = {
+-	DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE),
+-	DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
+-};
+-
+-static const struct resource rk817_pwrkey_resources[] = {
+-	DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
+-	DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
+-};
+-
+-static const struct resource rk817_charger_resources[] = {
+-	DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN),
+-	DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT),
+-};
+-
+-static const struct mfd_cell rk805s[] = {
+-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+-	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
+-	{
+-		.name = "rk808-rtc",
+-		.num_resources = ARRAY_SIZE(rtc_resources),
+-		.resources = &rtc_resources[0],
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-	{	.name = "rk805-pwrkey",
+-		.num_resources = ARRAY_SIZE(rk805_key_resources),
+-		.resources = &rk805_key_resources[0],
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-};
+-
+-static const struct mfd_cell rk808s[] = {
+-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+-	{
+-		.name = "rk808-rtc",
+-		.num_resources = ARRAY_SIZE(rtc_resources),
+-		.resources = rtc_resources,
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-};
+-
+-static const struct mfd_cell rk817s[] = {
+-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+-	{
+-		.name = "rk805-pwrkey",
+-		.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
+-		.resources = &rk817_pwrkey_resources[0],
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-	{
+-		.name = "rk808-rtc",
+-		.num_resources = ARRAY_SIZE(rk817_rtc_resources),
+-		.resources = &rk817_rtc_resources[0],
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-	{ .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
+-	{
+-		.name = "rk817-charger",
+-		.num_resources = ARRAY_SIZE(rk817_charger_resources),
+-		.resources = &rk817_charger_resources[0],
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-};
+-
+-static const struct mfd_cell rk818s[] = {
+-	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+-	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+-	{
+-		.name = "rk808-rtc",
+-		.num_resources = ARRAY_SIZE(rtc_resources),
+-		.resources = rtc_resources,
+-		.id = PLATFORM_DEVID_NONE,
+-	},
+-};
+-
+-static const struct rk808_reg_data rk805_pre_init_reg[] = {
+-	{RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
+-				 RK805_BUCK1_2_ILMAX_4000MA},
+-	{RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
+-				 RK805_BUCK1_2_ILMAX_4000MA},
+-	{RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
+-				 RK805_BUCK3_ILMAX_3000MA},
+-	{RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
+-				 RK805_BUCK4_ILMAX_3500MA},
+-	{RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
+-	{RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
+-};
+-
+-static const struct rk808_reg_data rk808_pre_init_reg[] = {
+-	{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_150MA },
+-	{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_200MA },
+-	{ RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
+-	{ RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK,  BUCK_ILMIN_200MA },
+-	{ RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK,  BUCK_ILMIN_200MA },
+-	{ RK808_DCDC_UV_ACT_REG,  BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE},
+-	{ RK808_VB_MON_REG,       MASK_ALL,         VB_LO_ACT |
+-						    VB_LO_SEL_3500MV },
+-};
+-
+-static const struct rk808_reg_data rk817_pre_init_reg[] = {
+-	{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
+-	/* Codec specific registers */
+-	{ RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
+-	{ RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
+-	/* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
+-	{ RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
+-	{ RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
+-	/* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
+-	{ RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
+-	{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
+-	{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
+-	{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
+-	{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
+-	/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
+-	{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
+-	{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
+-	{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
+-	{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
+-	{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
+-	{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
+-	{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
+-	{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
+-	/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
+-	{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
+-	{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
+-	{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
+-	{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
+-	{ RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
+-	{ RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
+-	{ RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
+-	{ RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
+-	{ RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
+-	{ RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
+-	{ RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
+-	{ RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
+-	{ RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
+-	{ RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
+-	{ RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
+-	{ RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
+-	{ RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
+-	{ RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
+-	{ RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
+-	{ RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
+-	{RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
+-	{RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
+-					   RK817_HOTDIE_105 | RK817_TSD_140},
+-};
+-
+-static const struct rk808_reg_data rk818_pre_init_reg[] = {
+-	/* improve efficiency */
+-	{ RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK,  BUCK_ILMIN_250MA },
+-	{ RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_250MA },
+-	{ RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
+-	{ RK818_USB_CTRL_REG,	  RK818_USB_ILIM_SEL_MASK,
+-						    RK818_USB_ILMIN_2000MA },
+-	/* close charger when usb lower then 3.4V */
+-	{ RK818_USB_CTRL_REG,	  RK818_USB_CHG_SD_VSEL_MASK,
+-						    (0x7 << 4) },
+-	/* no action when vref */
+-	{ RK818_H5V_EN_REG,	  BIT(1),	    RK818_REF_RDY_CTRL },
+-	/* enable HDMI 5V */
+-	{ RK818_H5V_EN_REG,	  BIT(0),	    RK818_H5V_EN },
+-	{ RK808_VB_MON_REG,	  MASK_ALL,	    VB_LO_ACT |
+-						    VB_LO_SEL_3500MV },
+-};
+-
+-static const struct regmap_irq rk805_irqs[] = {
+-	[RK805_IRQ_PWRON_RISE] = {
+-		.mask = RK805_IRQ_PWRON_RISE_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_VB_LOW] = {
+-		.mask = RK805_IRQ_VB_LOW_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_PWRON] = {
+-		.mask = RK805_IRQ_PWRON_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_PWRON_LP] = {
+-		.mask = RK805_IRQ_PWRON_LP_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_HOTDIE] = {
+-		.mask = RK805_IRQ_HOTDIE_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_RTC_ALARM] = {
+-		.mask = RK805_IRQ_RTC_ALARM_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_RTC_PERIOD] = {
+-		.mask = RK805_IRQ_RTC_PERIOD_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK805_IRQ_PWRON_FALL] = {
+-		.mask = RK805_IRQ_PWRON_FALL_MSK,
+-		.reg_offset = 0,
+-	},
+-};
+-
+-static const struct regmap_irq rk808_irqs[] = {
+-	/* INT_STS */
+-	[RK808_IRQ_VOUT_LO] = {
+-		.mask = RK808_IRQ_VOUT_LO_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK808_IRQ_VB_LO] = {
+-		.mask = RK808_IRQ_VB_LO_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK808_IRQ_PWRON] = {
+-		.mask = RK808_IRQ_PWRON_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK808_IRQ_PWRON_LP] = {
+-		.mask = RK808_IRQ_PWRON_LP_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK808_IRQ_HOTDIE] = {
+-		.mask = RK808_IRQ_HOTDIE_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK808_IRQ_RTC_ALARM] = {
+-		.mask = RK808_IRQ_RTC_ALARM_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK808_IRQ_RTC_PERIOD] = {
+-		.mask = RK808_IRQ_RTC_PERIOD_MSK,
+-		.reg_offset = 0,
+-	},
+-
+-	/* INT_STS2 */
+-	[RK808_IRQ_PLUG_IN_INT] = {
+-		.mask = RK808_IRQ_PLUG_IN_INT_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK808_IRQ_PLUG_OUT_INT] = {
+-		.mask = RK808_IRQ_PLUG_OUT_INT_MSK,
+-		.reg_offset = 1,
+-	},
+-};
+-
+-static const struct regmap_irq rk818_irqs[] = {
+-	/* INT_STS */
+-	[RK818_IRQ_VOUT_LO] = {
+-		.mask = RK818_IRQ_VOUT_LO_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_VB_LO] = {
+-		.mask = RK818_IRQ_VB_LO_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_PWRON] = {
+-		.mask = RK818_IRQ_PWRON_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_PWRON_LP] = {
+-		.mask = RK818_IRQ_PWRON_LP_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_HOTDIE] = {
+-		.mask = RK818_IRQ_HOTDIE_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_RTC_ALARM] = {
+-		.mask = RK818_IRQ_RTC_ALARM_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_RTC_PERIOD] = {
+-		.mask = RK818_IRQ_RTC_PERIOD_MSK,
+-		.reg_offset = 0,
+-	},
+-	[RK818_IRQ_USB_OV] = {
+-		.mask = RK818_IRQ_USB_OV_MSK,
+-		.reg_offset = 0,
+-	},
+-
+-	/* INT_STS2 */
+-	[RK818_IRQ_PLUG_IN] = {
+-		.mask = RK818_IRQ_PLUG_IN_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_PLUG_OUT] = {
+-		.mask = RK818_IRQ_PLUG_OUT_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_CHG_OK] = {
+-		.mask = RK818_IRQ_CHG_OK_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_CHG_TE] = {
+-		.mask = RK818_IRQ_CHG_TE_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_CHG_TS1] = {
+-		.mask = RK818_IRQ_CHG_TS1_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_TS2] = {
+-		.mask = RK818_IRQ_TS2_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_CHG_CVTLIM] = {
+-		.mask = RK818_IRQ_CHG_CVTLIM_MSK,
+-		.reg_offset = 1,
+-	},
+-	[RK818_IRQ_DISCHG_ILIM] = {
+-		.mask = RK818_IRQ_DISCHG_ILIM_MSK,
+-		.reg_offset = 1,
+-	},
+-};
+-
+-static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = {
+-	REGMAP_IRQ_REG_LINE(0, 8),
+-	REGMAP_IRQ_REG_LINE(1, 8),
+-	REGMAP_IRQ_REG_LINE(2, 8),
+-	REGMAP_IRQ_REG_LINE(3, 8),
+-	REGMAP_IRQ_REG_LINE(4, 8),
+-	REGMAP_IRQ_REG_LINE(5, 8),
+-	REGMAP_IRQ_REG_LINE(6, 8),
+-	REGMAP_IRQ_REG_LINE(7, 8),
+-	REGMAP_IRQ_REG_LINE(8, 8),
+-	REGMAP_IRQ_REG_LINE(9, 8),
+-	REGMAP_IRQ_REG_LINE(10, 8),
+-	REGMAP_IRQ_REG_LINE(11, 8),
+-	REGMAP_IRQ_REG_LINE(12, 8),
+-	REGMAP_IRQ_REG_LINE(13, 8),
+-	REGMAP_IRQ_REG_LINE(14, 8),
+-	REGMAP_IRQ_REG_LINE(15, 8),
+-	REGMAP_IRQ_REG_LINE(16, 8),
+-	REGMAP_IRQ_REG_LINE(17, 8),
+-	REGMAP_IRQ_REG_LINE(18, 8),
+-	REGMAP_IRQ_REG_LINE(19, 8),
+-	REGMAP_IRQ_REG_LINE(20, 8),
+-	REGMAP_IRQ_REG_LINE(21, 8),
+-	REGMAP_IRQ_REG_LINE(22, 8),
+-	REGMAP_IRQ_REG_LINE(23, 8)
+-};
+-
+-static struct regmap_irq_chip rk805_irq_chip = {
+-	.name = "rk805",
+-	.irqs = rk805_irqs,
+-	.num_irqs = ARRAY_SIZE(rk805_irqs),
+-	.num_regs = 1,
+-	.status_base = RK805_INT_STS_REG,
+-	.mask_base = RK805_INT_STS_MSK_REG,
+-	.ack_base = RK805_INT_STS_REG,
+-	.init_ack_masked = true,
+-};
+-
+-static const struct regmap_irq_chip rk808_irq_chip = {
+-	.name = "rk808",
+-	.irqs = rk808_irqs,
+-	.num_irqs = ARRAY_SIZE(rk808_irqs),
+-	.num_regs = 2,
+-	.irq_reg_stride = 2,
+-	.status_base = RK808_INT_STS_REG1,
+-	.mask_base = RK808_INT_STS_MSK_REG1,
+-	.ack_base = RK808_INT_STS_REG1,
+-	.init_ack_masked = true,
+-};
+-
+-static struct regmap_irq_chip rk817_irq_chip = {
+-	.name = "rk817",
+-	.irqs = rk817_irqs,
+-	.num_irqs = ARRAY_SIZE(rk817_irqs),
+-	.num_regs = 3,
+-	.irq_reg_stride = 2,
+-	.status_base = RK817_INT_STS_REG0,
+-	.mask_base = RK817_INT_STS_MSK_REG0,
+-	.ack_base = RK817_INT_STS_REG0,
+-	.init_ack_masked = true,
+-};
+-
+-static const struct regmap_irq_chip rk818_irq_chip = {
+-	.name = "rk818",
+-	.irqs = rk818_irqs,
+-	.num_irqs = ARRAY_SIZE(rk818_irqs),
+-	.num_regs = 2,
+-	.irq_reg_stride = 2,
+-	.status_base = RK818_INT_STS_REG1,
+-	.mask_base = RK818_INT_STS_MSK_REG1,
+-	.ack_base = RK818_INT_STS_REG1,
+-	.init_ack_masked = true,
+-};
+-
+-static int rk808_power_off(struct sys_off_data *data)
+-{
+-	struct rk808 *rk808 = data->cb_data;
+-	int ret;
+-	unsigned int reg, bit;
+-
+-	switch (rk808->variant) {
+-	case RK805_ID:
+-		reg = RK805_DEV_CTRL_REG;
+-		bit = DEV_OFF;
+-		break;
+-	case RK808_ID:
+-		reg = RK808_DEVCTRL_REG,
+-		bit = DEV_OFF_RST;
+-		break;
+-	case RK809_ID:
+-	case RK817_ID:
+-		reg = RK817_SYS_CFG(3);
+-		bit = DEV_OFF;
+-		break;
+-	case RK818_ID:
+-		reg = RK818_DEVCTRL_REG;
+-		bit = DEV_OFF;
+-		break;
+-	default:
+-		return NOTIFY_DONE;
+-	}
+-	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
+-	if (ret)
+-		dev_err(rk808->dev, "Failed to shutdown device!\n");
+-
+-	return NOTIFY_DONE;
+-}
+-
+-static int rk808_restart(struct sys_off_data *data)
+-{
+-	struct rk808 *rk808 = data->cb_data;
+-	unsigned int reg, bit;
+-	int ret;
+-
+-	switch (rk808->variant) {
+-	case RK809_ID:
+-	case RK817_ID:
+-		reg = RK817_SYS_CFG(3);
+-		bit = DEV_RST;
+-		break;
+-
+-	default:
+-		return NOTIFY_DONE;
+-	}
+-	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
+-	if (ret)
+-		dev_err(rk808->dev, "Failed to restart device!\n");
+-
+-	return NOTIFY_DONE;
+-}
+-
+-static void rk8xx_shutdown(struct i2c_client *client)
+-{
+-	struct rk808 *rk808 = i2c_get_clientdata(client);
+-	int ret;
+-
+-	switch (rk808->variant) {
+-	case RK805_ID:
+-		ret = regmap_update_bits(rk808->regmap,
+-					 RK805_GPIO_IO_POL_REG,
+-					 SLP_SD_MSK,
+-					 SHUTDOWN_FUN);
+-		break;
+-	case RK809_ID:
+-	case RK817_ID:
+-		ret = regmap_update_bits(rk808->regmap,
+-					 RK817_SYS_CFG(3),
+-					 RK817_SLPPIN_FUNC_MSK,
+-					 SLPPIN_DN_FUN);
+-		break;
+-	default:
+-		return;
+-	}
+-	if (ret)
+-		dev_warn(&client->dev,
+-			 "Cannot switch to power down function\n");
+-}
+-
+-static const struct of_device_id rk808_of_match[] = {
+-	{ .compatible = "rockchip,rk805" },
+-	{ .compatible = "rockchip,rk808" },
+-	{ .compatible = "rockchip,rk809" },
+-	{ .compatible = "rockchip,rk817" },
+-	{ .compatible = "rockchip,rk818" },
+-	{ },
+-};
+-MODULE_DEVICE_TABLE(of, rk808_of_match);
+-
+-static int rk808_probe(struct i2c_client *client)
+-{
+-	struct device_node *np = client->dev.of_node;
+-	struct rk808 *rk808;
+-	const struct rk808_reg_data *pre_init_reg;
+-	const struct mfd_cell *cells;
+-	int nr_pre_init_regs;
+-	int nr_cells;
+-	int msb, lsb;
+-	unsigned char pmic_id_msb, pmic_id_lsb;
+-	int ret;
+-	int i;
+-
+-	rk808 = devm_kzalloc(&client->dev, sizeof(*rk808), GFP_KERNEL);
+-	if (!rk808)
+-		return -ENOMEM;
+-
+-	if (of_device_is_compatible(np, "rockchip,rk817") ||
+-	    of_device_is_compatible(np, "rockchip,rk809")) {
+-		pmic_id_msb = RK817_ID_MSB;
+-		pmic_id_lsb = RK817_ID_LSB;
+-	} else {
+-		pmic_id_msb = RK808_ID_MSB;
+-		pmic_id_lsb = RK808_ID_LSB;
+-	}
+-
+-	/* Read chip variant */
+-	msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
+-	if (msb < 0)
+-		return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n");
+-
+-	lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
+-	if (lsb < 0)
+-		return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n");
+-
+-	rk808->variant = ((msb << 8) | lsb) & RK8XX_ID_MSK;
+-	dev_info(&client->dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
+-
+-	switch (rk808->variant) {
+-	case RK805_ID:
+-		rk808->regmap_cfg = &rk805_regmap_config;
+-		rk808->regmap_irq_chip = &rk805_irq_chip;
+-		pre_init_reg = rk805_pre_init_reg;
+-		nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg);
+-		cells = rk805s;
+-		nr_cells = ARRAY_SIZE(rk805s);
+-		break;
+-	case RK808_ID:
+-		rk808->regmap_cfg = &rk808_regmap_config;
+-		rk808->regmap_irq_chip = &rk808_irq_chip;
+-		pre_init_reg = rk808_pre_init_reg;
+-		nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
+-		cells = rk808s;
+-		nr_cells = ARRAY_SIZE(rk808s);
+-		break;
+-	case RK818_ID:
+-		rk808->regmap_cfg = &rk818_regmap_config;
+-		rk808->regmap_irq_chip = &rk818_irq_chip;
+-		pre_init_reg = rk818_pre_init_reg;
+-		nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
+-		cells = rk818s;
+-		nr_cells = ARRAY_SIZE(rk818s);
+-		break;
+-	case RK809_ID:
+-	case RK817_ID:
+-		rk808->regmap_cfg = &rk817_regmap_config;
+-		rk808->regmap_irq_chip = &rk817_irq_chip;
+-		pre_init_reg = rk817_pre_init_reg;
+-		nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg);
+-		cells = rk817s;
+-		nr_cells = ARRAY_SIZE(rk817s);
+-		break;
+-	default:
+-		dev_err(&client->dev, "Unsupported RK8XX ID %lu\n",
+-			rk808->variant);
+-		return -EINVAL;
+-	}
+-
+-	rk808->dev = &client->dev;
+-	i2c_set_clientdata(client, rk808);
+-
+-	rk808->regmap = devm_regmap_init_i2c(client, rk808->regmap_cfg);
+-	if (IS_ERR(rk808->regmap))
+-		return dev_err_probe(&client->dev, PTR_ERR(rk808->regmap),
+-				     "regmap initialization failed\n");
+-
+-	if (!client->irq)
+-		return dev_err_probe(&client->dev, -EINVAL, "No interrupt support, no core IRQ\n");
+-
+-	ret = devm_regmap_add_irq_chip(&client->dev, rk808->regmap, client->irq,
+-				       IRQF_ONESHOT, -1,
+-				       rk808->regmap_irq_chip, &rk808->irq_data);
+-	if (ret)
+-		return dev_err_probe(&client->dev, ret, "Failed to add irq_chip\n");
+-
+-	for (i = 0; i < nr_pre_init_regs; i++) {
+-		ret = regmap_update_bits(rk808->regmap,
+-					pre_init_reg[i].addr,
+-					pre_init_reg[i].mask,
+-					pre_init_reg[i].value);
+-		if (ret)
+-			return dev_err_probe(&client->dev, ret, "0x%x write err\n",
+-					     pre_init_reg[i].addr);
+-	}
+-
+-	ret = devm_mfd_add_devices(&client->dev, PLATFORM_DEVID_NONE,
+-			      cells, nr_cells, NULL, 0,
+-			      regmap_irq_get_domain(rk808->irq_data));
+-	if (ret)
+-		return dev_err_probe(&client->dev, ret, "failed to add MFD devices\n");
+-
+-	if (of_property_read_bool(np, "rockchip,system-power-controller")) {
+-		ret = devm_register_sys_off_handler(&client->dev,
+-				    SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
+-				    &rk808_power_off, rk808);
+-		if (ret)
+-			return dev_err_probe(&client->dev, ret,
+-					     "failed to register poweroff handler\n");
+-
+-		switch (rk808->variant) {
+-		case RK809_ID:
+-		case RK817_ID:
+-			ret = devm_register_sys_off_handler(&client->dev,
+-							    SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
+-							    &rk808_restart, rk808);
+-			if (ret)
+-				dev_warn(&client->dev, "failed to register rst handler, %d\n", ret);
+-			break;
+-		default:
+-			dev_dbg(&client->dev, "pmic controlled board reset not supported\n");
+-			break;
+-		}
+-	}
+-
+-	return 0;
+-}
+-
+-static int __maybe_unused rk8xx_suspend(struct device *dev)
+-{
+-	struct rk808 *rk808 = i2c_get_clientdata(to_i2c_client(dev));
+-	int ret = 0;
+-
+-	switch (rk808->variant) {
+-	case RK805_ID:
+-		ret = regmap_update_bits(rk808->regmap,
+-					 RK805_GPIO_IO_POL_REG,
+-					 SLP_SD_MSK,
+-					 SLEEP_FUN);
+-		break;
+-	case RK809_ID:
+-	case RK817_ID:
+-		ret = regmap_update_bits(rk808->regmap,
+-					 RK817_SYS_CFG(3),
+-					 RK817_SLPPIN_FUNC_MSK,
+-					 SLPPIN_SLP_FUN);
+-		break;
+-	default:
+-		break;
+-	}
+-
+-	return ret;
+-}
+-
+-static int __maybe_unused rk8xx_resume(struct device *dev)
+-{
+-	struct rk808 *rk808 = i2c_get_clientdata(to_i2c_client(dev));
+-	int ret = 0;
+-
+-	switch (rk808->variant) {
+-	case RK809_ID:
+-	case RK817_ID:
+-		ret = regmap_update_bits(rk808->regmap,
+-					 RK817_SYS_CFG(3),
+-					 RK817_SLPPIN_FUNC_MSK,
+-					 SLPPIN_NULL_FUN);
+-		break;
+-	default:
+-		break;
+-	}
+-
+-	return ret;
+-}
+-static SIMPLE_DEV_PM_OPS(rk8xx_pm_ops, rk8xx_suspend, rk8xx_resume);
+-
+-static struct i2c_driver rk808_i2c_driver = {
+-	.driver = {
+-		.name = "rk808",
+-		.of_match_table = rk808_of_match,
+-		.pm = &rk8xx_pm_ops,
+-	},
+-	.probe_new = rk808_probe,
+-	.shutdown = rk8xx_shutdown,
+-};
+-
+-module_i2c_driver(rk808_i2c_driver);
+-
+-MODULE_LICENSE("GPL");
+-MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
+-MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
+-MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
+-MODULE_DESCRIPTION("RK808/RK818 PMIC driver");
+--- /dev/null
++++ b/drivers/mfd/rk8xx-core.c
+@@ -0,0 +1,706 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * MFD core driver for Rockchip RK8XX
++ *
++ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
++ *
++ * Author: Chris Zhong <zyw@rock-chips.com>
++ * Author: Zhang Qing <zhangqing@rock-chips.com>
++ * Author: Wadim Egorov <w.egorov@phytec.de>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/mfd/rk808.h>
++#include <linux/mfd/core.h>
++#include <linux/module.h>
++#include <linux/of_device.h>
++#include <linux/regmap.h>
++#include <linux/reboot.h>
++
++struct rk808_reg_data {
++	int addr;
++	int mask;
++	int value;
++};
++
++static const struct resource rtc_resources[] = {
++	DEFINE_RES_IRQ(RK808_IRQ_RTC_ALARM),
++};
++
++static const struct resource rk817_rtc_resources[] = {
++	DEFINE_RES_IRQ(RK817_IRQ_RTC_ALARM),
++};
++
++static const struct resource rk805_key_resources[] = {
++	DEFINE_RES_IRQ(RK805_IRQ_PWRON_RISE),
++	DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
++};
++
++static const struct resource rk817_pwrkey_resources[] = {
++	DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
++	DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
++};
++
++static const struct resource rk817_charger_resources[] = {
++	DEFINE_RES_IRQ(RK817_IRQ_PLUG_IN),
++	DEFINE_RES_IRQ(RK817_IRQ_PLUG_OUT),
++};
++
++static const struct mfd_cell rk805s[] = {
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_NONE, },
++	{
++		.name = "rk808-rtc",
++		.num_resources = ARRAY_SIZE(rtc_resources),
++		.resources = &rtc_resources[0],
++		.id = PLATFORM_DEVID_NONE,
++	},
++	{	.name = "rk805-pwrkey",
++		.num_resources = ARRAY_SIZE(rk805_key_resources),
++		.resources = &rk805_key_resources[0],
++		.id = PLATFORM_DEVID_NONE,
++	},
++};
++
++static const struct mfd_cell rk808s[] = {
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
++	{
++		.name = "rk808-rtc",
++		.num_resources = ARRAY_SIZE(rtc_resources),
++		.resources = rtc_resources,
++		.id = PLATFORM_DEVID_NONE,
++	},
++};
++
++static const struct mfd_cell rk817s[] = {
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
++	{
++		.name = "rk805-pwrkey",
++		.num_resources = ARRAY_SIZE(rk817_pwrkey_resources),
++		.resources = &rk817_pwrkey_resources[0],
++		.id = PLATFORM_DEVID_NONE,
++	},
++	{
++		.name = "rk808-rtc",
++		.num_resources = ARRAY_SIZE(rk817_rtc_resources),
++		.resources = &rk817_rtc_resources[0],
++		.id = PLATFORM_DEVID_NONE,
++	},
++	{ .name = "rk817-codec", .id = PLATFORM_DEVID_NONE, },
++	{
++		.name = "rk817-charger",
++		.num_resources = ARRAY_SIZE(rk817_charger_resources),
++		.resources = &rk817_charger_resources[0],
++		.id = PLATFORM_DEVID_NONE,
++	},
++};
++
++static const struct mfd_cell rk818s[] = {
++	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
++	{
++		.name = "rk808-rtc",
++		.num_resources = ARRAY_SIZE(rtc_resources),
++		.resources = rtc_resources,
++		.id = PLATFORM_DEVID_NONE,
++	},
++};
++
++static const struct rk808_reg_data rk805_pre_init_reg[] = {
++	{RK805_BUCK1_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
++				 RK805_BUCK1_2_ILMAX_4000MA},
++	{RK805_BUCK2_CONFIG_REG, RK805_BUCK1_2_ILMAX_MASK,
++				 RK805_BUCK1_2_ILMAX_4000MA},
++	{RK805_BUCK3_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
++				 RK805_BUCK3_ILMAX_3000MA},
++	{RK805_BUCK4_CONFIG_REG, RK805_BUCK3_4_ILMAX_MASK,
++				 RK805_BUCK4_ILMAX_3500MA},
++	{RK805_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK, BUCK_ILMIN_400MA},
++	{RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
++};
++
++static const struct rk808_reg_data rk808_pre_init_reg[] = {
++	{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_150MA },
++	{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_200MA },
++	{ RK808_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
++	{ RK808_BUCK1_CONFIG_REG, BUCK1_RATE_MASK,  BUCK_ILMIN_200MA },
++	{ RK808_BUCK2_CONFIG_REG, BUCK2_RATE_MASK,  BUCK_ILMIN_200MA },
++	{ RK808_DCDC_UV_ACT_REG,  BUCK_UV_ACT_MASK, BUCK_UV_ACT_DISABLE},
++	{ RK808_VB_MON_REG,       MASK_ALL,         VB_LO_ACT |
++						    VB_LO_SEL_3500MV },
++};
++
++static const struct rk808_reg_data rk817_pre_init_reg[] = {
++	{RK817_RTC_CTRL_REG, RTC_STOP, RTC_STOP},
++	/* Codec specific registers */
++	{ RK817_CODEC_DTOP_VUCTL, MASK_ALL, 0x03 },
++	{ RK817_CODEC_DTOP_VUCTIME, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DTOP_LPT_SRST, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DTOP_DIGEN_CLKE, MASK_ALL, 0x00 },
++	/* from vendor driver, CODEC_AREF_RTCFG0 not defined in data sheet */
++	{ RK817_CODEC_AREF_RTCFG0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_AREF_RTCFG1, MASK_ALL, 0x06 },
++	{ RK817_CODEC_AADC_CFG0, MASK_ALL, 0xc8 },
++	/* from vendor driver, CODEC_AADC_CFG1 not defined in data sheet */
++	{ RK817_CODEC_AADC_CFG1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_VOLL, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_VOLR, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_SR_ACL0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_ALC1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_ALC2, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_NG, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_HPF, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DADC_RVOLL, MASK_ALL, 0xff },
++	{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
++	{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
++	{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
++	{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
++	/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
++	{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
++	{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
++	{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
++	{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
++	{ RK817_CODEC_DADC_RVOLR, MASK_ALL, 0xff },
++	{ RK817_CODEC_AMIC_CFG0, MASK_ALL, 0x70 },
++	{ RK817_CODEC_AMIC_CFG1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_PGA_GAIN, MASK_ALL, 0x66 },
++	{ RK817_CODEC_DMIC_LMT1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_LMT2, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_NG1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DMIC_NG2, MASK_ALL, 0x00 },
++	/* from vendor driver, CODEC_ADAC_CFG0 not defined in data sheet */
++	{ RK817_CODEC_ADAC_CFG0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_ADAC_CFG1, MASK_ALL, 0x07 },
++	{ RK817_CODEC_DDAC_POPD_DACST, MASK_ALL, 0x82 },
++	{ RK817_CODEC_DDAC_VOLL, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_VOLR, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_SR_LMT0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_LMT1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_LMT2, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DDAC_MUTE_MIXCTL, MASK_ALL, 0xa0 },
++	{ RK817_CODEC_DDAC_RVOLL, MASK_ALL, 0xff },
++	{ RK817_CODEC_DDAC_RVOLR, MASK_ALL, 0xff },
++	{ RK817_CODEC_AHP_ANTI0, MASK_ALL, 0x00 },
++	{ RK817_CODEC_AHP_ANTI1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_AHP_CFG0, MASK_ALL, 0xe0 },
++	{ RK817_CODEC_AHP_CFG1, MASK_ALL, 0x1f },
++	{ RK817_CODEC_AHP_CP, MASK_ALL, 0x09 },
++	{ RK817_CODEC_ACLASSD_CFG1, MASK_ALL, 0x69 },
++	{ RK817_CODEC_ACLASSD_CFG2, MASK_ALL, 0x44 },
++	{ RK817_CODEC_APLL_CFG0, MASK_ALL, 0x04 },
++	{ RK817_CODEC_APLL_CFG1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_APLL_CFG2, MASK_ALL, 0x30 },
++	{ RK817_CODEC_APLL_CFG3, MASK_ALL, 0x19 },
++	{ RK817_CODEC_APLL_CFG4, MASK_ALL, 0x65 },
++	{ RK817_CODEC_APLL_CFG5, MASK_ALL, 0x01 },
++	{ RK817_CODEC_DI2S_CKM, MASK_ALL, 0x01 },
++	{ RK817_CODEC_DI2S_RSD, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DI2S_RXCR1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DI2S_RXCR2, MASK_ALL, 0x17 },
++	{ RK817_CODEC_DI2S_RXCMD_TSD, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DI2S_TXCR1, MASK_ALL, 0x00 },
++	{ RK817_CODEC_DI2S_TXCR2, MASK_ALL, 0x17 },
++	{ RK817_CODEC_DI2S_TXCR3_TXCMD, MASK_ALL, 0x00 },
++	{RK817_GPIO_INT_CFG, RK817_INT_POL_MSK, RK817_INT_POL_L},
++	{RK817_SYS_CFG(1), RK817_HOTDIE_TEMP_MSK | RK817_TSD_TEMP_MSK,
++					   RK817_HOTDIE_105 | RK817_TSD_140},
++};
++
++static const struct rk808_reg_data rk818_pre_init_reg[] = {
++	/* improve efficiency */
++	{ RK818_BUCK2_CONFIG_REG, BUCK2_RATE_MASK,  BUCK_ILMIN_250MA },
++	{ RK818_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_250MA },
++	{ RK818_BOOST_CONFIG_REG, BOOST_ILMIN_MASK, BOOST_ILMIN_100MA },
++	{ RK818_USB_CTRL_REG,	  RK818_USB_ILIM_SEL_MASK,
++						    RK818_USB_ILMIN_2000MA },
++	/* close charger when usb lower then 3.4V */
++	{ RK818_USB_CTRL_REG,	  RK818_USB_CHG_SD_VSEL_MASK,
++						    (0x7 << 4) },
++	/* no action when vref */
++	{ RK818_H5V_EN_REG,	  BIT(1),	    RK818_REF_RDY_CTRL },
++	/* enable HDMI 5V */
++	{ RK818_H5V_EN_REG,	  BIT(0),	    RK818_H5V_EN },
++	{ RK808_VB_MON_REG,	  MASK_ALL,	    VB_LO_ACT |
++						    VB_LO_SEL_3500MV },
++};
++
++static const struct regmap_irq rk805_irqs[] = {
++	[RK805_IRQ_PWRON_RISE] = {
++		.mask = RK805_IRQ_PWRON_RISE_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_VB_LOW] = {
++		.mask = RK805_IRQ_VB_LOW_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_PWRON] = {
++		.mask = RK805_IRQ_PWRON_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_PWRON_LP] = {
++		.mask = RK805_IRQ_PWRON_LP_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_HOTDIE] = {
++		.mask = RK805_IRQ_HOTDIE_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_RTC_ALARM] = {
++		.mask = RK805_IRQ_RTC_ALARM_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_RTC_PERIOD] = {
++		.mask = RK805_IRQ_RTC_PERIOD_MSK,
++		.reg_offset = 0,
++	},
++	[RK805_IRQ_PWRON_FALL] = {
++		.mask = RK805_IRQ_PWRON_FALL_MSK,
++		.reg_offset = 0,
++	},
++};
++
++static const struct regmap_irq rk808_irqs[] = {
++	/* INT_STS */
++	[RK808_IRQ_VOUT_LO] = {
++		.mask = RK808_IRQ_VOUT_LO_MSK,
++		.reg_offset = 0,
++	},
++	[RK808_IRQ_VB_LO] = {
++		.mask = RK808_IRQ_VB_LO_MSK,
++		.reg_offset = 0,
++	},
++	[RK808_IRQ_PWRON] = {
++		.mask = RK808_IRQ_PWRON_MSK,
++		.reg_offset = 0,
++	},
++	[RK808_IRQ_PWRON_LP] = {
++		.mask = RK808_IRQ_PWRON_LP_MSK,
++		.reg_offset = 0,
++	},
++	[RK808_IRQ_HOTDIE] = {
++		.mask = RK808_IRQ_HOTDIE_MSK,
++		.reg_offset = 0,
++	},
++	[RK808_IRQ_RTC_ALARM] = {
++		.mask = RK808_IRQ_RTC_ALARM_MSK,
++		.reg_offset = 0,
++	},
++	[RK808_IRQ_RTC_PERIOD] = {
++		.mask = RK808_IRQ_RTC_PERIOD_MSK,
++		.reg_offset = 0,
++	},
++
++	/* INT_STS2 */
++	[RK808_IRQ_PLUG_IN_INT] = {
++		.mask = RK808_IRQ_PLUG_IN_INT_MSK,
++		.reg_offset = 1,
++	},
++	[RK808_IRQ_PLUG_OUT_INT] = {
++		.mask = RK808_IRQ_PLUG_OUT_INT_MSK,
++		.reg_offset = 1,
++	},
++};
++
++static const struct regmap_irq rk818_irqs[] = {
++	/* INT_STS */
++	[RK818_IRQ_VOUT_LO] = {
++		.mask = RK818_IRQ_VOUT_LO_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_VB_LO] = {
++		.mask = RK818_IRQ_VB_LO_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_PWRON] = {
++		.mask = RK818_IRQ_PWRON_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_PWRON_LP] = {
++		.mask = RK818_IRQ_PWRON_LP_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_HOTDIE] = {
++		.mask = RK818_IRQ_HOTDIE_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_RTC_ALARM] = {
++		.mask = RK818_IRQ_RTC_ALARM_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_RTC_PERIOD] = {
++		.mask = RK818_IRQ_RTC_PERIOD_MSK,
++		.reg_offset = 0,
++	},
++	[RK818_IRQ_USB_OV] = {
++		.mask = RK818_IRQ_USB_OV_MSK,
++		.reg_offset = 0,
++	},
++
++	/* INT_STS2 */
++	[RK818_IRQ_PLUG_IN] = {
++		.mask = RK818_IRQ_PLUG_IN_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_PLUG_OUT] = {
++		.mask = RK818_IRQ_PLUG_OUT_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_CHG_OK] = {
++		.mask = RK818_IRQ_CHG_OK_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_CHG_TE] = {
++		.mask = RK818_IRQ_CHG_TE_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_CHG_TS1] = {
++		.mask = RK818_IRQ_CHG_TS1_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_TS2] = {
++		.mask = RK818_IRQ_TS2_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_CHG_CVTLIM] = {
++		.mask = RK818_IRQ_CHG_CVTLIM_MSK,
++		.reg_offset = 1,
++	},
++	[RK818_IRQ_DISCHG_ILIM] = {
++		.mask = RK818_IRQ_DISCHG_ILIM_MSK,
++		.reg_offset = 1,
++	},
++};
++
++static const struct regmap_irq rk817_irqs[RK817_IRQ_END] = {
++	REGMAP_IRQ_REG_LINE(0, 8),
++	REGMAP_IRQ_REG_LINE(1, 8),
++	REGMAP_IRQ_REG_LINE(2, 8),
++	REGMAP_IRQ_REG_LINE(3, 8),
++	REGMAP_IRQ_REG_LINE(4, 8),
++	REGMAP_IRQ_REG_LINE(5, 8),
++	REGMAP_IRQ_REG_LINE(6, 8),
++	REGMAP_IRQ_REG_LINE(7, 8),
++	REGMAP_IRQ_REG_LINE(8, 8),
++	REGMAP_IRQ_REG_LINE(9, 8),
++	REGMAP_IRQ_REG_LINE(10, 8),
++	REGMAP_IRQ_REG_LINE(11, 8),
++	REGMAP_IRQ_REG_LINE(12, 8),
++	REGMAP_IRQ_REG_LINE(13, 8),
++	REGMAP_IRQ_REG_LINE(14, 8),
++	REGMAP_IRQ_REG_LINE(15, 8),
++	REGMAP_IRQ_REG_LINE(16, 8),
++	REGMAP_IRQ_REG_LINE(17, 8),
++	REGMAP_IRQ_REG_LINE(18, 8),
++	REGMAP_IRQ_REG_LINE(19, 8),
++	REGMAP_IRQ_REG_LINE(20, 8),
++	REGMAP_IRQ_REG_LINE(21, 8),
++	REGMAP_IRQ_REG_LINE(22, 8),
++	REGMAP_IRQ_REG_LINE(23, 8)
++};
++
++static struct regmap_irq_chip rk805_irq_chip = {
++	.name = "rk805",
++	.irqs = rk805_irqs,
++	.num_irqs = ARRAY_SIZE(rk805_irqs),
++	.num_regs = 1,
++	.status_base = RK805_INT_STS_REG,
++	.mask_base = RK805_INT_STS_MSK_REG,
++	.ack_base = RK805_INT_STS_REG,
++	.init_ack_masked = true,
++};
++
++static const struct regmap_irq_chip rk808_irq_chip = {
++	.name = "rk808",
++	.irqs = rk808_irqs,
++	.num_irqs = ARRAY_SIZE(rk808_irqs),
++	.num_regs = 2,
++	.irq_reg_stride = 2,
++	.status_base = RK808_INT_STS_REG1,
++	.mask_base = RK808_INT_STS_MSK_REG1,
++	.ack_base = RK808_INT_STS_REG1,
++	.init_ack_masked = true,
++};
++
++static struct regmap_irq_chip rk817_irq_chip = {
++	.name = "rk817",
++	.irqs = rk817_irqs,
++	.num_irqs = ARRAY_SIZE(rk817_irqs),
++	.num_regs = 3,
++	.irq_reg_stride = 2,
++	.status_base = RK817_INT_STS_REG0,
++	.mask_base = RK817_INT_STS_MSK_REG0,
++	.ack_base = RK817_INT_STS_REG0,
++	.init_ack_masked = true,
++};
++
++static const struct regmap_irq_chip rk818_irq_chip = {
++	.name = "rk818",
++	.irqs = rk818_irqs,
++	.num_irqs = ARRAY_SIZE(rk818_irqs),
++	.num_regs = 2,
++	.irq_reg_stride = 2,
++	.status_base = RK818_INT_STS_REG1,
++	.mask_base = RK818_INT_STS_MSK_REG1,
++	.ack_base = RK818_INT_STS_REG1,
++	.init_ack_masked = true,
++};
++
++static int rk808_power_off(struct sys_off_data *data)
++{
++	struct rk808 *rk808 = data->cb_data;
++	int ret;
++	unsigned int reg, bit;
++
++	switch (rk808->variant) {
++	case RK805_ID:
++		reg = RK805_DEV_CTRL_REG;
++		bit = DEV_OFF;
++		break;
++	case RK808_ID:
++		reg = RK808_DEVCTRL_REG,
++		bit = DEV_OFF_RST;
++		break;
++	case RK809_ID:
++	case RK817_ID:
++		reg = RK817_SYS_CFG(3);
++		bit = DEV_OFF;
++		break;
++	case RK818_ID:
++		reg = RK818_DEVCTRL_REG;
++		bit = DEV_OFF;
++		break;
++	default:
++		return NOTIFY_DONE;
++	}
++	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
++	if (ret)
++		dev_err(rk808->dev, "Failed to shutdown device!\n");
++
++	return NOTIFY_DONE;
++}
++
++static int rk808_restart(struct sys_off_data *data)
++{
++	struct rk808 *rk808 = data->cb_data;
++	unsigned int reg, bit;
++	int ret;
++
++	switch (rk808->variant) {
++	case RK809_ID:
++	case RK817_ID:
++		reg = RK817_SYS_CFG(3);
++		bit = DEV_RST;
++		break;
++
++	default:
++		return NOTIFY_DONE;
++	}
++	ret = regmap_update_bits(rk808->regmap, reg, bit, bit);
++	if (ret)
++		dev_err(rk808->dev, "Failed to restart device!\n");
++
++	return NOTIFY_DONE;
++}
++
++void rk8xx_shutdown(struct device *dev)
++{
++	struct rk808 *rk808 = dev_get_drvdata(dev);
++	int ret;
++
++	switch (rk808->variant) {
++	case RK805_ID:
++		ret = regmap_update_bits(rk808->regmap,
++					 RK805_GPIO_IO_POL_REG,
++					 SLP_SD_MSK,
++					 SHUTDOWN_FUN);
++		break;
++	case RK809_ID:
++	case RK817_ID:
++		ret = regmap_update_bits(rk808->regmap,
++					 RK817_SYS_CFG(3),
++					 RK817_SLPPIN_FUNC_MSK,
++					 SLPPIN_DN_FUN);
++		break;
++	default:
++		return;
++	}
++	if (ret)
++		dev_warn(dev,
++			 "Cannot switch to power down function\n");
++}
++EXPORT_SYMBOL_GPL(rk8xx_shutdown);
++
++int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap)
++{
++	struct rk808 *rk808;
++	const struct rk808_reg_data *pre_init_reg;
++	const struct mfd_cell *cells;
++	int nr_pre_init_regs;
++	int nr_cells;
++	int ret;
++	int i;
++
++	rk808 = devm_kzalloc(dev, sizeof(*rk808), GFP_KERNEL);
++	if (!rk808)
++		return -ENOMEM;
++	rk808->dev = dev;
++	rk808->variant = variant;
++	rk808->regmap = regmap;
++	dev_set_drvdata(dev, rk808);
++
++	switch (rk808->variant) {
++	case RK805_ID:
++		rk808->regmap_irq_chip = &rk805_irq_chip;
++		pre_init_reg = rk805_pre_init_reg;
++		nr_pre_init_regs = ARRAY_SIZE(rk805_pre_init_reg);
++		cells = rk805s;
++		nr_cells = ARRAY_SIZE(rk805s);
++		break;
++	case RK808_ID:
++		rk808->regmap_irq_chip = &rk808_irq_chip;
++		pre_init_reg = rk808_pre_init_reg;
++		nr_pre_init_regs = ARRAY_SIZE(rk808_pre_init_reg);
++		cells = rk808s;
++		nr_cells = ARRAY_SIZE(rk808s);
++		break;
++	case RK818_ID:
++		rk808->regmap_irq_chip = &rk818_irq_chip;
++		pre_init_reg = rk818_pre_init_reg;
++		nr_pre_init_regs = ARRAY_SIZE(rk818_pre_init_reg);
++		cells = rk818s;
++		nr_cells = ARRAY_SIZE(rk818s);
++		break;
++	case RK809_ID:
++	case RK817_ID:
++		rk808->regmap_irq_chip = &rk817_irq_chip;
++		pre_init_reg = rk817_pre_init_reg;
++		nr_pre_init_regs = ARRAY_SIZE(rk817_pre_init_reg);
++		cells = rk817s;
++		nr_cells = ARRAY_SIZE(rk817s);
++		break;
++	default:
++		dev_err(dev, "Unsupported RK8XX ID %lu\n", rk808->variant);
++		return -EINVAL;
++	}
++
++	dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
++
++	if (!irq)
++		return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
++
++	ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq,
++				       IRQF_ONESHOT, -1,
++				       rk808->regmap_irq_chip, &rk808->irq_data);
++	if (ret)
++		return dev_err_probe(dev, ret, "Failed to add irq_chip\n");
++
++	for (i = 0; i < nr_pre_init_regs; i++) {
++		ret = regmap_update_bits(rk808->regmap,
++					pre_init_reg[i].addr,
++					pre_init_reg[i].mask,
++					pre_init_reg[i].value);
++		if (ret)
++			return dev_err_probe(dev, ret, "0x%x write err\n",
++					     pre_init_reg[i].addr);
++	}
++
++	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
++			      cells, nr_cells, NULL, 0,
++			      regmap_irq_get_domain(rk808->irq_data));
++	if (ret)
++		return dev_err_probe(dev, ret, "failed to add MFD devices\n");
++
++	if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
++		ret = devm_register_sys_off_handler(dev,
++				    SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
++				    &rk808_power_off, rk808);
++		if (ret)
++			return dev_err_probe(dev, ret,
++					     "failed to register poweroff handler\n");
++
++		switch (rk808->variant) {
++		case RK809_ID:
++		case RK817_ID:
++			ret = devm_register_sys_off_handler(dev,
++							    SYS_OFF_MODE_RESTART, SYS_OFF_PRIO_HIGH,
++							    &rk808_restart, rk808);
++			if (ret)
++				dev_warn(dev, "failed to register rst handler, %d\n", ret);
++			break;
++		default:
++			dev_dbg(dev, "pmic controlled board reset not supported\n");
++			break;
++		}
++	}
++
++	return 0;
++}
++EXPORT_SYMBOL_GPL(rk8xx_probe);
++
++int rk8xx_suspend(struct device *dev)
++{
++	struct rk808 *rk808 = dev_get_drvdata(dev);
++	int ret = 0;
++
++	switch (rk808->variant) {
++	case RK805_ID:
++		ret = regmap_update_bits(rk808->regmap,
++					 RK805_GPIO_IO_POL_REG,
++					 SLP_SD_MSK,
++					 SLEEP_FUN);
++		break;
++	case RK809_ID:
++	case RK817_ID:
++		ret = regmap_update_bits(rk808->regmap,
++					 RK817_SYS_CFG(3),
++					 RK817_SLPPIN_FUNC_MSK,
++					 SLPPIN_SLP_FUN);
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(rk8xx_suspend);
++
++int rk8xx_resume(struct device *dev)
++{
++	struct rk808 *rk808 = dev_get_drvdata(dev);
++	int ret = 0;
++
++	switch (rk808->variant) {
++	case RK809_ID:
++	case RK817_ID:
++		ret = regmap_update_bits(rk808->regmap,
++					 RK817_SYS_CFG(3),
++					 RK817_SLPPIN_FUNC_MSK,
++					 SLPPIN_NULL_FUN);
++		break;
++	default:
++		break;
++	}
++
++	return ret;
++}
++EXPORT_SYMBOL_GPL(rk8xx_resume);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
++MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
++MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
++MODULE_DESCRIPTION("RK8xx PMIC core");
+--- /dev/null
++++ b/drivers/mfd/rk8xx-i2c.c
+@@ -0,0 +1,200 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Rockchip RK808/RK818 Core (I2C) driver
++ *
++ * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (C) 2016 PHYTEC Messtechnik GmbH
++ *
++ * Author: Chris Zhong <zyw@rock-chips.com>
++ * Author: Zhang Qing <zhangqing@rock-chips.com>
++ * Author: Wadim Egorov <w.egorov@phytec.de>
++ */
++
++#include <linux/i2c.h>
++#include <linux/mfd/rk808.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/regmap.h>
++
++static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
++{
++	/*
++	 * Notes:
++	 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
++	 *   we don't use that feature.  It's better to cache.
++	 * - It's unlikely we care that RK808_DEVCTRL_REG is volatile since
++	 *   bits are cleared in case when we shutoff anyway, but better safe.
++	 */
++
++	switch (reg) {
++	case RK808_SECONDS_REG ... RK808_WEEKS_REG:
++	case RK808_RTC_STATUS_REG:
++	case RK808_VB_MON_REG:
++	case RK808_THERMAL_REG:
++	case RK808_DCDC_UV_STS_REG:
++	case RK808_LDO_UV_STS_REG:
++	case RK808_DCDC_PG_REG:
++	case RK808_LDO_PG_REG:
++	case RK808_DEVCTRL_REG:
++	case RK808_INT_STS_REG1:
++	case RK808_INT_STS_REG2:
++		return true;
++	}
++
++	return false;
++}
++
++static bool rk817_is_volatile_reg(struct device *dev, unsigned int reg)
++{
++	/*
++	 * Notes:
++	 * - Technically the ROUND_30s bit makes RTC_CTRL_REG volatile, but
++	 *   we don't use that feature.  It's better to cache.
++	 */
++
++	switch (reg) {
++	case RK817_SECONDS_REG ... RK817_WEEKS_REG:
++	case RK817_RTC_STATUS_REG:
++	case RK817_CODEC_DTOP_LPT_SRST:
++	case RK817_GAS_GAUGE_ADC_CONFIG0 ... RK817_GAS_GAUGE_CUR_ADC_K0:
++	case RK817_PMIC_CHRG_STS:
++	case RK817_PMIC_CHRG_OUT:
++	case RK817_PMIC_CHRG_IN:
++	case RK817_INT_STS_REG0:
++	case RK817_INT_STS_REG1:
++	case RK817_INT_STS_REG2:
++	case RK817_SYS_STS:
++		return true;
++	}
++
++	return false;
++}
++
++
++static const struct regmap_config rk818_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++	.max_register = RK818_USB_CTRL_REG,
++	.cache_type = REGCACHE_RBTREE,
++	.volatile_reg = rk808_is_volatile_reg,
++};
++
++static const struct regmap_config rk805_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++	.max_register = RK805_OFF_SOURCE_REG,
++	.cache_type = REGCACHE_RBTREE,
++	.volatile_reg = rk808_is_volatile_reg,
++};
++
++static const struct regmap_config rk808_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++	.max_register = RK808_IO_POL_REG,
++	.cache_type = REGCACHE_RBTREE,
++	.volatile_reg = rk808_is_volatile_reg,
++};
++
++static const struct regmap_config rk817_regmap_config = {
++	.reg_bits = 8,
++	.val_bits = 8,
++	.max_register = RK817_GPIO_INT_CFG,
++	.cache_type = REGCACHE_NONE,
++	.volatile_reg = rk817_is_volatile_reg,
++};
++
++static int rk8xx_i2c_get_variant(struct i2c_client *client)
++{
++	u8 pmic_id_msb, pmic_id_lsb;
++	int msb, lsb;
++
++	if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") ||
++	    of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) {
++		pmic_id_msb = RK817_ID_MSB;
++		pmic_id_lsb = RK817_ID_LSB;
++	} else {
++		pmic_id_msb = RK808_ID_MSB;
++		pmic_id_lsb = RK808_ID_LSB;
++	}
++
++	/* Read chip variant */
++	msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
++	if (msb < 0)
++		return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n");
++
++	lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
++	if (lsb < 0)
++		return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n");
++
++	return ((msb << 8) | lsb) & RK8XX_ID_MSK;
++}
++
++static int rk8xx_i2c_probe(struct i2c_client *client)
++{
++	const struct regmap_config *regmap_cfg;
++	struct regmap *regmap;
++	int variant;
++
++	variant = rk8xx_i2c_get_variant(client);
++	if (variant < 0)
++		return variant;
++
++	switch (variant) {
++	case RK805_ID:
++		regmap_cfg = &rk805_regmap_config;
++		break;
++	case RK808_ID:
++		regmap_cfg = &rk808_regmap_config;
++		break;
++	case RK818_ID:
++		regmap_cfg = &rk818_regmap_config;
++		break;
++	case RK809_ID:
++	case RK817_ID:
++		regmap_cfg = &rk817_regmap_config;
++		break;
++	default:
++		return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant);
++	}
++
++	regmap = devm_regmap_init_i2c(client, regmap_cfg);
++	if (IS_ERR(regmap))
++		return dev_err_probe(&client->dev, PTR_ERR(regmap),
++				     "regmap initialization failed\n");
++
++	return rk8xx_probe(&client->dev, variant, client->irq, regmap);
++}
++
++static void rk8xx_i2c_shutdown(struct i2c_client *client)
++{
++	rk8xx_shutdown(&client->dev);
++}
++
++static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume);
++
++static const struct of_device_id rk8xx_i2c_of_match[] = {
++	{ .compatible = "rockchip,rk805" },
++	{ .compatible = "rockchip,rk808" },
++	{ .compatible = "rockchip,rk809" },
++	{ .compatible = "rockchip,rk817" },
++	{ .compatible = "rockchip,rk818" },
++	{ },
++};
++MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match);
++
++static struct i2c_driver rk8xx_i2c_driver = {
++	.driver = {
++		.name = "rk8xx-i2c",
++		.of_match_table = rk8xx_i2c_of_match,
++		.pm = &rk8xx_i2c_pm_ops,
++	},
++	.probe_new = rk8xx_i2c_probe,
++	.shutdown  = rk8xx_i2c_shutdown,
++};
++module_i2c_driver(rk8xx_i2c_driver);
++
++MODULE_LICENSE("GPL");
++MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
++MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
++MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
++MODULE_DESCRIPTION("RK8xx I2C PMIC driver");
+--- a/drivers/pinctrl/Kconfig
++++ b/drivers/pinctrl/Kconfig
+@@ -396,7 +396,7 @@ config PINCTRL_PISTACHIO
+ 
+ config PINCTRL_RK805
+ 	tristate "Pinctrl and GPIO driver for RK805 PMIC"
+-	depends on MFD_RK808
++	depends on MFD_RK8XX
+ 	select GPIOLIB
+ 	select PINMUX
+ 	select GENERIC_PINCONF
+--- a/drivers/power/supply/Kconfig
++++ b/drivers/power/supply/Kconfig
+@@ -725,7 +725,7 @@ config CHARGER_BQ256XX
+ 
+ config CHARGER_RK817
+ 	tristate "Rockchip RK817 PMIC Battery Charger"
+-	depends on MFD_RK808
++	depends on MFD_RK8XX
+ 	help
+ 	  Say Y to include support for Rockchip RK817 Battery Charger.
+ 
+--- a/drivers/regulator/Kconfig
++++ b/drivers/regulator/Kconfig
+@@ -1039,7 +1039,7 @@ config REGULATOR_RC5T583
+ 
+ config REGULATOR_RK808
+ 	tristate "Rockchip RK805/RK808/RK809/RK817/RK818 Power regulators"
+-	depends on MFD_RK808
++	depends on MFD_RK8XX
+ 	help
+ 	  Select this option to enable the power regulator of ROCKCHIP
+ 	  PMIC RK805,RK809&RK817,RK808 and RK818.
+--- a/drivers/rtc/Kconfig
++++ b/drivers/rtc/Kconfig
+@@ -395,7 +395,7 @@ config RTC_DRV_NCT3018Y
+ 
+ config RTC_DRV_RK808
+ 	tristate "Rockchip RK805/RK808/RK809/RK817/RK818 RTC"
+-	depends on MFD_RK808
++	depends on MFD_RK8XX
+ 	help
+ 	  If you say yes here you will get support for the
+ 	  RTC of RK805, RK809 and RK817, RK808 and RK818 PMIC.
+--- a/include/linux/mfd/rk808.h
++++ b/include/linux/mfd/rk808.h
+@@ -794,4 +794,10 @@ struct rk808 {
+ 	const struct regmap_config	*regmap_cfg;
+ 	const struct regmap_irq_chip	*regmap_irq_chip;
+ };
++
++void rk8xx_shutdown(struct device *dev);
++int rk8xx_probe(struct device *dev, int variant, unsigned int irq, struct regmap *regmap);
++int rk8xx_suspend(struct device *dev);
++int rk8xx_resume(struct device *dev);
++
+ #endif /* __LINUX_REGULATOR_RK808_H */
+--- a/sound/soc/codecs/Kconfig
++++ b/sound/soc/codecs/Kconfig
+@@ -1211,7 +1211,7 @@ config SND_SOC_RK3328
+ 
+ config SND_SOC_RK817
+ 	tristate "Rockchip RK817 audio CODEC"
+-	depends on MFD_RK808 || COMPILE_TEST
++	depends on MFD_RK8XX || COMPILE_TEST
+ 
+ config SND_SOC_RL6231
+ 	tristate
diff --git a/target/linux/rockchip/patches-6.1/232-mfd-rk8xx-i2c-Use-device_get_match_data.patch b/target/linux/rockchip/patches-6.1/232-mfd-rk8xx-i2c-Use-device_get_match_data.patch
new file mode 100644
index 00000000000..15be1d7ebfc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/232-mfd-rk8xx-i2c-Use-device_get_match_data.patch
@@ -0,0 +1,159 @@
+From 4f4bccd6c5a165055daeeafe4a593845ddaca0d6 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:10 +0200
+Subject: [PATCH 232/383] mfd: rk8xx-i2c: Use device_get_match_data
+
+Simplify the device identification logic by supplying the relevant
+information via of_match_data. This also removes the dev_info()
+printing the chip version, since that's supplied by the match data
+now.
+
+Due to lack of hardware this change is compile-tested only.
+
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-7-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/rk8xx-core.c |  2 -
+ drivers/mfd/rk8xx-i2c.c  | 89 +++++++++++++++++-----------------------
+ 2 files changed, 37 insertions(+), 54 deletions(-)
+
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -597,8 +597,6 @@ int rk8xx_probe(struct device *dev, int
+ 		return -EINVAL;
+ 	}
+ 
+-	dev_info(dev, "chip id: 0x%x\n", (unsigned int)rk808->variant);
+-
+ 	if (!irq)
+ 		return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
+ 
+--- a/drivers/mfd/rk8xx-i2c.c
++++ b/drivers/mfd/rk8xx-i2c.c
+@@ -16,6 +16,11 @@
+ #include <linux/of.h>
+ #include <linux/regmap.h>
+ 
++struct rk8xx_i2c_platform_data {
++	const struct regmap_config *regmap_cfg;
++	int variant;
++};
++
+ static bool rk808_is_volatile_reg(struct device *dev, unsigned int reg)
+ {
+ 	/*
+@@ -103,66 +108,46 @@ static const struct regmap_config rk817_
+ 	.volatile_reg = rk817_is_volatile_reg,
+ };
+ 
+-static int rk8xx_i2c_get_variant(struct i2c_client *client)
+-{
+-	u8 pmic_id_msb, pmic_id_lsb;
+-	int msb, lsb;
++static const struct rk8xx_i2c_platform_data rk805_data = {
++	.regmap_cfg = &rk805_regmap_config,
++	.variant = RK805_ID,
++};
+ 
+-	if (of_device_is_compatible(client->dev.of_node, "rockchip,rk817") ||
+-	    of_device_is_compatible(client->dev.of_node, "rockchip,rk809")) {
+-		pmic_id_msb = RK817_ID_MSB;
+-		pmic_id_lsb = RK817_ID_LSB;
+-	} else {
+-		pmic_id_msb = RK808_ID_MSB;
+-		pmic_id_lsb = RK808_ID_LSB;
+-	}
++static const struct rk8xx_i2c_platform_data rk808_data = {
++	.regmap_cfg = &rk808_regmap_config,
++	.variant = RK808_ID,
++};
+ 
+-	/* Read chip variant */
+-	msb = i2c_smbus_read_byte_data(client, pmic_id_msb);
+-	if (msb < 0)
+-		return dev_err_probe(&client->dev, msb, "failed to read the chip id MSB\n");
+-
+-	lsb = i2c_smbus_read_byte_data(client, pmic_id_lsb);
+-	if (lsb < 0)
+-		return dev_err_probe(&client->dev, lsb, "failed to read the chip id LSB\n");
++static const struct rk8xx_i2c_platform_data rk809_data = {
++	.regmap_cfg = &rk817_regmap_config,
++	.variant = RK809_ID,
++};
+ 
+-	return ((msb << 8) | lsb) & RK8XX_ID_MSK;
+-}
++static const struct rk8xx_i2c_platform_data rk817_data = {
++	.regmap_cfg = &rk817_regmap_config,
++	.variant = RK817_ID,
++};
++
++static const struct rk8xx_i2c_platform_data rk818_data = {
++	.regmap_cfg = &rk818_regmap_config,
++	.variant = RK818_ID,
++};
+ 
+ static int rk8xx_i2c_probe(struct i2c_client *client)
+ {
+-	const struct regmap_config *regmap_cfg;
++	const struct rk8xx_i2c_platform_data *data;
+ 	struct regmap *regmap;
+-	int variant;
+ 
+-	variant = rk8xx_i2c_get_variant(client);
+-	if (variant < 0)
+-		return variant;
+-
+-	switch (variant) {
+-	case RK805_ID:
+-		regmap_cfg = &rk805_regmap_config;
+-		break;
+-	case RK808_ID:
+-		regmap_cfg = &rk808_regmap_config;
+-		break;
+-	case RK818_ID:
+-		regmap_cfg = &rk818_regmap_config;
+-		break;
+-	case RK809_ID:
+-	case RK817_ID:
+-		regmap_cfg = &rk817_regmap_config;
+-		break;
+-	default:
+-		return dev_err_probe(&client->dev, -EINVAL, "Unsupported RK8XX ID %x\n", variant);
+-	}
++	data = device_get_match_data(&client->dev);
++	if (!data)
++		return -ENODEV;
+ 
+-	regmap = devm_regmap_init_i2c(client, regmap_cfg);
++	regmap = devm_regmap_init_i2c(client, data->regmap_cfg);
+ 	if (IS_ERR(regmap))
+ 		return dev_err_probe(&client->dev, PTR_ERR(regmap),
+ 				     "regmap initialization failed\n");
+ 
+-	return rk8xx_probe(&client->dev, variant, client->irq, regmap);
++	return rk8xx_probe(&client->dev, data->variant, client->irq, regmap);
+ }
+ 
+ static void rk8xx_i2c_shutdown(struct i2c_client *client)
+@@ -173,11 +158,11 @@ static void rk8xx_i2c_shutdown(struct i2
+ static SIMPLE_DEV_PM_OPS(rk8xx_i2c_pm_ops, rk8xx_suspend, rk8xx_resume);
+ 
+ static const struct of_device_id rk8xx_i2c_of_match[] = {
+-	{ .compatible = "rockchip,rk805" },
+-	{ .compatible = "rockchip,rk808" },
+-	{ .compatible = "rockchip,rk809" },
+-	{ .compatible = "rockchip,rk817" },
+-	{ .compatible = "rockchip,rk818" },
++	{ .compatible = "rockchip,rk805", .data = &rk805_data },
++	{ .compatible = "rockchip,rk808", .data = &rk808_data },
++	{ .compatible = "rockchip,rk809", .data = &rk809_data },
++	{ .compatible = "rockchip,rk817", .data = &rk817_data },
++	{ .compatible = "rockchip,rk818", .data = &rk818_data },
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(of, rk8xx_i2c_of_match);
diff --git a/target/linux/rockchip/patches-6.1/233-mfd-rk8xx-Add-rk806-support.patch b/target/linux/rockchip/patches-6.1/233-mfd-rk8xx-Add-rk806-support.patch
new file mode 100644
index 00000000000..2a3453d24cc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/233-mfd-rk8xx-Add-rk806-support.patch
@@ -0,0 +1,744 @@
+From 015e9112f29888f35fbb01d7f416d56780f18f2b Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 19:36:12 +0200
+Subject: [PATCH 233/383] mfd: rk8xx: Add rk806 support
+
+Add support for SPI connected rk806, which is used by the RK3588
+evaluation boards. The PMIC is advertised to support I2C and SPI,
+but the evaluation boards all use SPI. Thus only SPI support is
+added here.
+
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20230504173618.142075-9-sebastian.reichel@collabora.com
+Signed-off-by: Lee Jones <lee@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mfd/Kconfig       |  14 ++
+ drivers/mfd/Makefile      |   1 +
+ drivers/mfd/rk8xx-core.c  |  69 ++++++-
+ drivers/mfd/rk8xx-spi.c   | 124 ++++++++++++
+ include/linux/mfd/rk808.h | 409 ++++++++++++++++++++++++++++++++++++++
+ 5 files changed, 614 insertions(+), 3 deletions(-)
+ create mode 100644 drivers/mfd/rk8xx-spi.c
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -1220,6 +1220,20 @@ config MFD_RK8XX_I2C
+ 	  through I2C interface. The device supports multiple sub-devices
+ 	  including interrupts, RTC, LDO & DCDC regulators, and onkey.
+ 
++config MFD_RK8XX_SPI
++	tristate "Rockchip RK806 Power Management Chip"
++	depends on SPI && OF
++	select MFD_CORE
++	select REGMAP_SPI
++	select REGMAP_IRQ
++	select MFD_RK8XX
++	help
++	  If you say yes here you get support for the RK806 Power Management
++	  chip.
++	  This driver provides common support for accessing the device
++	  through an SPI interface. The device supports multiple sub-devices
++	  including interrupts, LDO & DCDC regulators, and power on-key.
++
+ config MFD_RN5T618
+ 	tristate "Ricoh RN5T567/618 PMIC"
+ 	depends on I2C
+--- a/drivers/mfd/Makefile
++++ b/drivers/mfd/Makefile
+@@ -225,6 +225,7 @@ obj-$(CONFIG_MFD_NTXEC)		+= ntxec.o
+ obj-$(CONFIG_MFD_RC5T583)	+= rc5t583.o rc5t583-irq.o
+ obj-$(CONFIG_MFD_RK8XX)		+= rk8xx-core.o
+ obj-$(CONFIG_MFD_RK8XX_I2C)	+= rk8xx-i2c.o
++obj-$(CONFIG_MFD_RK8XX_SPI)	+= rk8xx-spi.o
+ obj-$(CONFIG_MFD_RN5T618)	+= rn5t618.o
+ obj-$(CONFIG_MFD_SEC_CORE)	+= sec-core.o sec-irq.o
+ obj-$(CONFIG_MFD_SYSCON)	+= syscon.o
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -37,6 +37,11 @@ static const struct resource rk805_key_r
+ 	DEFINE_RES_IRQ(RK805_IRQ_PWRON_FALL),
+ };
+ 
++static struct resource rk806_pwrkey_resources[] = {
++	DEFINE_RES_IRQ(RK806_IRQ_PWRON_FALL),
++	DEFINE_RES_IRQ(RK806_IRQ_PWRON_RISE),
++};
++
+ static const struct resource rk817_pwrkey_resources[] = {
+ 	DEFINE_RES_IRQ(RK817_IRQ_PWRON_RISE),
+ 	DEFINE_RES_IRQ(RK817_IRQ_PWRON_FALL),
+@@ -64,6 +69,17 @@ static const struct mfd_cell rk805s[] =
+ 	},
+ };
+ 
++static const struct mfd_cell rk806s[] = {
++	{ .name = "rk805-pinctrl", .id = PLATFORM_DEVID_AUTO, },
++	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_AUTO, },
++	{
++		.name = "rk805-pwrkey",
++		.resources = rk806_pwrkey_resources,
++		.num_resources = ARRAY_SIZE(rk806_pwrkey_resources),
++		.id = PLATFORM_DEVID_AUTO,
++	},
++};
++
+ static const struct mfd_cell rk808s[] = {
+ 	{ .name = "rk808-clkout", .id = PLATFORM_DEVID_NONE, },
+ 	{ .name = "rk808-regulator", .id = PLATFORM_DEVID_NONE, },
+@@ -123,6 +139,12 @@ static const struct rk808_reg_data rk805
+ 	{RK805_THERMAL_REG, TEMP_HOTDIE_MSK, TEMP115C},
+ };
+ 
++static const struct rk808_reg_data rk806_pre_init_reg[] = {
++	{ RK806_GPIO_INT_CONFIG, RK806_INT_POL_MSK, RK806_INT_POL_L },
++	{ RK806_SYS_CFG3, RK806_SLAVE_RESTART_FUN_MSK, RK806_SLAVE_RESTART_FUN_EN },
++	{ RK806_SYS_OPTION, RK806_SYS_ENB2_2M_MSK, RK806_SYS_ENB2_2M_EN },
++};
++
+ static const struct rk808_reg_data rk808_pre_init_reg[] = {
+ 	{ RK808_BUCK3_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_150MA },
+ 	{ RK808_BUCK4_CONFIG_REG, BUCK_ILMIN_MASK,  BUCK_ILMIN_200MA },
+@@ -273,6 +295,27 @@ static const struct regmap_irq rk805_irq
+ 	},
+ };
+ 
++static const struct regmap_irq rk806_irqs[] = {
++	/* INT_STS0 IRQs */
++	REGMAP_IRQ_REG(RK806_IRQ_PWRON_FALL, 0, RK806_INT_STS_PWRON_FALL),
++	REGMAP_IRQ_REG(RK806_IRQ_PWRON_RISE, 0, RK806_INT_STS_PWRON_RISE),
++	REGMAP_IRQ_REG(RK806_IRQ_PWRON, 0, RK806_INT_STS_PWRON),
++	REGMAP_IRQ_REG(RK806_IRQ_PWRON_LP, 0, RK806_INT_STS_PWRON_LP),
++	REGMAP_IRQ_REG(RK806_IRQ_HOTDIE, 0, RK806_INT_STS_HOTDIE),
++	REGMAP_IRQ_REG(RK806_IRQ_VDC_RISE, 0, RK806_INT_STS_VDC_RISE),
++	REGMAP_IRQ_REG(RK806_IRQ_VDC_FALL, 0, RK806_INT_STS_VDC_FALL),
++	REGMAP_IRQ_REG(RK806_IRQ_VB_LO, 0, RK806_INT_STS_VB_LO),
++	/* INT_STS1 IRQs */
++	REGMAP_IRQ_REG(RK806_IRQ_REV0, 1, RK806_INT_STS_REV0),
++	REGMAP_IRQ_REG(RK806_IRQ_REV1, 1, RK806_INT_STS_REV1),
++	REGMAP_IRQ_REG(RK806_IRQ_REV2, 1, RK806_INT_STS_REV2),
++	REGMAP_IRQ_REG(RK806_IRQ_CRC_ERROR, 1, RK806_INT_STS_CRC_ERROR),
++	REGMAP_IRQ_REG(RK806_IRQ_SLP3_GPIO, 1, RK806_INT_STS_SLP3_GPIO),
++	REGMAP_IRQ_REG(RK806_IRQ_SLP2_GPIO, 1, RK806_INT_STS_SLP2_GPIO),
++	REGMAP_IRQ_REG(RK806_IRQ_SLP1_GPIO, 1, RK806_INT_STS_SLP1_GPIO),
++	REGMAP_IRQ_REG(RK806_IRQ_WDT, 1, RK806_INT_STS_WDT),
++};
++
+ static const struct regmap_irq rk808_irqs[] = {
+ 	/* INT_STS */
+ 	[RK808_IRQ_VOUT_LO] = {
+@@ -423,6 +466,18 @@ static struct regmap_irq_chip rk805_irq_
+ 	.init_ack_masked = true,
+ };
+ 
++static struct regmap_irq_chip rk806_irq_chip = {
++	.name = "rk806",
++	.irqs = rk806_irqs,
++	.num_irqs = ARRAY_SIZE(rk806_irqs),
++	.num_regs = 2,
++	.irq_reg_stride = 2,
++	.mask_base = RK806_INT_MSK0,
++	.status_base = RK806_INT_STS0,
++	.ack_base = RK806_INT_STS0,
++	.init_ack_masked = true,
++};
++
+ static const struct regmap_irq_chip rk808_irq_chip = {
+ 	.name = "rk808",
+ 	.irqs = rk808_irqs,
+@@ -549,6 +604,7 @@ int rk8xx_probe(struct device *dev, int
+ 	struct rk808 *rk808;
+ 	const struct rk808_reg_data *pre_init_reg;
+ 	const struct mfd_cell *cells;
++	int dual_support = 0;
+ 	int nr_pre_init_regs;
+ 	int nr_cells;
+ 	int ret;
+@@ -570,6 +626,14 @@ int rk8xx_probe(struct device *dev, int
+ 		cells = rk805s;
+ 		nr_cells = ARRAY_SIZE(rk805s);
+ 		break;
++	case RK806_ID:
++		rk808->regmap_irq_chip = &rk806_irq_chip;
++		pre_init_reg = rk806_pre_init_reg;
++		nr_pre_init_regs = ARRAY_SIZE(rk806_pre_init_reg);
++		cells = rk806s;
++		nr_cells = ARRAY_SIZE(rk806s);
++		dual_support = IRQF_SHARED;
++		break;
+ 	case RK808_ID:
+ 		rk808->regmap_irq_chip = &rk808_irq_chip;
+ 		pre_init_reg = rk808_pre_init_reg;
+@@ -601,7 +665,7 @@ int rk8xx_probe(struct device *dev, int
+ 		return dev_err_probe(dev, -EINVAL, "No interrupt support, no core IRQ\n");
+ 
+ 	ret = devm_regmap_add_irq_chip(dev, rk808->regmap, irq,
+-				       IRQF_ONESHOT, -1,
++				       IRQF_ONESHOT | dual_support, -1,
+ 				       rk808->regmap_irq_chip, &rk808->irq_data);
+ 	if (ret)
+ 		return dev_err_probe(dev, ret, "Failed to add irq_chip\n");
+@@ -616,8 +680,7 @@ int rk8xx_probe(struct device *dev, int
+ 					     pre_init_reg[i].addr);
+ 	}
+ 
+-	ret = devm_mfd_add_devices(dev, PLATFORM_DEVID_NONE,
+-			      cells, nr_cells, NULL, 0,
++	ret = devm_mfd_add_devices(dev, 0, cells, nr_cells, NULL, 0,
+ 			      regmap_irq_get_domain(rk808->irq_data));
+ 	if (ret)
+ 		return dev_err_probe(dev, ret, "failed to add MFD devices\n");
+--- /dev/null
++++ b/drivers/mfd/rk8xx-spi.c
+@@ -0,0 +1,124 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Rockchip RK806 Core (SPI) driver
++ *
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ * Copyright (c) 2023 Collabora Ltd.
++ *
++ * Author: Xu Shengfei <xsf@rock-chips.com>
++ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
++ */
++
++#include <linux/interrupt.h>
++#include <linux/mfd/core.h>
++#include <linux/mfd/rk808.h>
++#include <linux/module.h>
++#include <linux/regmap.h>
++#include <linux/spi/spi.h>
++
++#define RK806_ADDR_SIZE 2
++#define RK806_CMD_WITH_SIZE(CMD, VALUE_BYTES) \
++	(RK806_CMD_##CMD | RK806_CMD_CRC_DIS | (VALUE_BYTES - 1))
++
++static const struct regmap_range rk806_volatile_ranges[] = {
++	regmap_reg_range(RK806_POWER_EN0, RK806_POWER_EN5),
++	regmap_reg_range(RK806_DVS_START_CTRL, RK806_INT_MSK1),
++};
++
++static const struct regmap_access_table rk806_volatile_table = {
++	.yes_ranges = rk806_volatile_ranges,
++	.n_yes_ranges = ARRAY_SIZE(rk806_volatile_ranges),
++};
++
++static const struct regmap_config rk806_regmap_config_spi = {
++	.reg_bits = 16,
++	.val_bits = 8,
++	.max_register = RK806_BUCK_RSERVE_REG5,
++	.cache_type = REGCACHE_RBTREE,
++	.volatile_table = &rk806_volatile_table,
++};
++
++static int rk806_spi_bus_write(void *context, const void *vdata, size_t count)
++{
++	struct device *dev = context;
++	struct spi_device *spi = to_spi_device(dev);
++	struct spi_transfer xfer[2] = { 0 };
++	/* data and thus count includes the register address */
++	size_t val_size = count - RK806_ADDR_SIZE;
++	char cmd;
++
++	if (val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1))
++		return -EINVAL;
++
++	cmd = RK806_CMD_WITH_SIZE(WRITE, val_size);
++
++	xfer[0].tx_buf = &cmd;
++	xfer[0].len = sizeof(cmd);
++	xfer[1].tx_buf = vdata;
++	xfer[1].len = count;
++
++	return spi_sync_transfer(spi, xfer, ARRAY_SIZE(xfer));
++}
++
++static int rk806_spi_bus_read(void *context, const void *vreg, size_t reg_size,
++			      void *val, size_t val_size)
++{
++	struct device *dev = context;
++	struct spi_device *spi = to_spi_device(dev);
++	char txbuf[3] = { 0 };
++
++	if (reg_size != RK806_ADDR_SIZE ||
++	    val_size < 1 || val_size > (RK806_CMD_LEN_MSK + 1))
++		return -EINVAL;
++
++	/* TX buffer contains command byte followed by two address bytes */
++	txbuf[0] = RK806_CMD_WITH_SIZE(READ, val_size);
++	memcpy(txbuf+1, vreg, reg_size);
++
++	return spi_write_then_read(spi, txbuf, sizeof(txbuf), val, val_size);
++}
++
++static const struct regmap_bus rk806_regmap_bus_spi = {
++	.write = rk806_spi_bus_write,
++	.read = rk806_spi_bus_read,
++	.reg_format_endian_default = REGMAP_ENDIAN_LITTLE,
++};
++
++static int rk8xx_spi_probe(struct spi_device *spi)
++{
++	struct regmap *regmap;
++
++	regmap = devm_regmap_init(&spi->dev, &rk806_regmap_bus_spi,
++				  &spi->dev, &rk806_regmap_config_spi);
++	if (IS_ERR(regmap))
++		return dev_err_probe(&spi->dev, PTR_ERR(regmap),
++				     "Failed to init regmap\n");
++
++	return rk8xx_probe(&spi->dev, RK806_ID, spi->irq, regmap);
++}
++
++static const struct of_device_id rk8xx_spi_of_match[] = {
++	{ .compatible = "rockchip,rk806", },
++	{ }
++};
++MODULE_DEVICE_TABLE(of, rk8xx_spi_of_match);
++
++static const struct spi_device_id rk8xx_spi_id_table[] = {
++	{ "rk806", 0 },
++	{ }
++};
++MODULE_DEVICE_TABLE(spi, rk8xx_spi_id_table);
++
++static struct spi_driver rk8xx_spi_driver = {
++	.driver		= {
++		.name	= "rk8xx-spi",
++		.of_match_table = rk8xx_spi_of_match,
++	},
++	.probe		= rk8xx_spi_probe,
++	.id_table	= rk8xx_spi_id_table,
++};
++module_spi_driver(rk8xx_spi_driver);
++
++MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
++MODULE_DESCRIPTION("RK8xx SPI PMIC driver");
++MODULE_LICENSE("GPL");
+--- a/include/linux/mfd/rk808.h
++++ b/include/linux/mfd/rk808.h
+@@ -289,6 +289,414 @@ enum rk805_reg {
+ #define RK805_INT_ALARM_EN		(1 << 3)
+ #define RK805_INT_TIMER_EN		(1 << 2)
+ 
++/* RK806 */
++#define RK806_POWER_EN0			0x0
++#define RK806_POWER_EN1			0x1
++#define RK806_POWER_EN2			0x2
++#define RK806_POWER_EN3			0x3
++#define RK806_POWER_EN4			0x4
++#define RK806_POWER_EN5			0x5
++#define RK806_POWER_SLP_EN0		0x6
++#define RK806_POWER_SLP_EN1		0x7
++#define RK806_POWER_SLP_EN2		0x8
++#define RK806_POWER_DISCHRG_EN0		0x9
++#define RK806_POWER_DISCHRG_EN1		0xA
++#define RK806_POWER_DISCHRG_EN2		0xB
++#define RK806_BUCK_FB_CONFIG		0xC
++#define RK806_SLP_LP_CONFIG		0xD
++#define RK806_POWER_FPWM_EN0		0xE
++#define RK806_POWER_FPWM_EN1		0xF
++#define RK806_BUCK1_CONFIG		0x10
++#define RK806_BUCK2_CONFIG		0x11
++#define RK806_BUCK3_CONFIG		0x12
++#define RK806_BUCK4_CONFIG		0x13
++#define RK806_BUCK5_CONFIG		0x14
++#define RK806_BUCK6_CONFIG		0x15
++#define RK806_BUCK7_CONFIG		0x16
++#define RK806_BUCK8_CONFIG		0x17
++#define RK806_BUCK9_CONFIG		0x18
++#define RK806_BUCK10_CONFIG		0x19
++#define RK806_BUCK1_ON_VSEL		0x1A
++#define RK806_BUCK2_ON_VSEL		0x1B
++#define RK806_BUCK3_ON_VSEL		0x1C
++#define RK806_BUCK4_ON_VSEL		0x1D
++#define RK806_BUCK5_ON_VSEL		0x1E
++#define RK806_BUCK6_ON_VSEL		0x1F
++#define RK806_BUCK7_ON_VSEL		0x20
++#define RK806_BUCK8_ON_VSEL		0x21
++#define RK806_BUCK9_ON_VSEL		0x22
++#define RK806_BUCK10_ON_VSEL		0x23
++#define RK806_BUCK1_SLP_VSEL		0x24
++#define RK806_BUCK2_SLP_VSEL		0x25
++#define RK806_BUCK3_SLP_VSEL		0x26
++#define RK806_BUCK4_SLP_VSEL		0x27
++#define RK806_BUCK5_SLP_VSEL		0x28
++#define RK806_BUCK6_SLP_VSEL		0x29
++#define RK806_BUCK7_SLP_VSEL		0x2A
++#define RK806_BUCK8_SLP_VSEL		0x2B
++#define RK806_BUCK9_SLP_VSEL		0x2D
++#define RK806_BUCK10_SLP_VSEL		0x2E
++#define RK806_BUCK_DEBUG1		0x30
++#define RK806_BUCK_DEBUG2		0x31
++#define RK806_BUCK_DEBUG3		0x32
++#define RK806_BUCK_DEBUG4		0x33
++#define RK806_BUCK_DEBUG5		0x34
++#define RK806_BUCK_DEBUG6		0x35
++#define RK806_BUCK_DEBUG7		0x36
++#define RK806_BUCK_DEBUG8		0x37
++#define RK806_BUCK_DEBUG9		0x38
++#define RK806_BUCK_DEBUG10		0x39
++#define RK806_BUCK_DEBUG11		0x3A
++#define RK806_BUCK_DEBUG12		0x3B
++#define RK806_BUCK_DEBUG13		0x3C
++#define RK806_BUCK_DEBUG14		0x3D
++#define RK806_BUCK_DEBUG15		0x3E
++#define RK806_BUCK_DEBUG16		0x3F
++#define RK806_BUCK_DEBUG17		0x40
++#define RK806_BUCK_DEBUG18		0x41
++#define RK806_NLDO_IMAX			0x42
++#define RK806_NLDO1_ON_VSEL		0x43
++#define RK806_NLDO2_ON_VSEL		0x44
++#define RK806_NLDO3_ON_VSEL		0x45
++#define RK806_NLDO4_ON_VSEL		0x46
++#define RK806_NLDO5_ON_VSEL		0x47
++#define RK806_NLDO1_SLP_VSEL		0x48
++#define RK806_NLDO2_SLP_VSEL		0x49
++#define RK806_NLDO3_SLP_VSEL		0x4A
++#define RK806_NLDO4_SLP_VSEL		0x4B
++#define RK806_NLDO5_SLP_VSEL		0x4C
++#define RK806_PLDO_IMAX			0x4D
++#define RK806_PLDO1_ON_VSEL		0x4E
++#define RK806_PLDO2_ON_VSEL		0x4F
++#define RK806_PLDO3_ON_VSEL		0x50
++#define RK806_PLDO4_ON_VSEL		0x51
++#define RK806_PLDO5_ON_VSEL		0x52
++#define RK806_PLDO6_ON_VSEL		0x53
++#define RK806_PLDO1_SLP_VSEL		0x54
++#define RK806_PLDO2_SLP_VSEL		0x55
++#define RK806_PLDO3_SLP_VSEL		0x56
++#define RK806_PLDO4_SLP_VSEL		0x57
++#define RK806_PLDO5_SLP_VSEL		0x58
++#define RK806_PLDO6_SLP_VSEL		0x59
++#define RK806_CHIP_NAME			0x5A
++#define RK806_CHIP_VER			0x5B
++#define RK806_OTP_VER			0x5C
++#define RK806_SYS_STS			0x5D
++#define RK806_SYS_CFG0			0x5E
++#define RK806_SYS_CFG1			0x5F
++#define RK806_SYS_OPTION		0x61
++#define RK806_SLEEP_CONFIG0		0x62
++#define RK806_SLEEP_CONFIG1		0x63
++#define RK806_SLEEP_CTR_SEL0		0x64
++#define RK806_SLEEP_CTR_SEL1		0x65
++#define RK806_SLEEP_CTR_SEL2		0x66
++#define RK806_SLEEP_CTR_SEL3		0x67
++#define RK806_SLEEP_CTR_SEL4		0x68
++#define RK806_SLEEP_CTR_SEL5		0x69
++#define RK806_DVS_CTRL_SEL0		0x6A
++#define RK806_DVS_CTRL_SEL1		0x6B
++#define RK806_DVS_CTRL_SEL2		0x6C
++#define RK806_DVS_CTRL_SEL3		0x6D
++#define RK806_DVS_CTRL_SEL4		0x6E
++#define RK806_DVS_CTRL_SEL5		0x6F
++#define RK806_DVS_START_CTRL		0x70
++#define RK806_SLEEP_GPIO		0x71
++#define RK806_SYS_CFG3			0x72
++#define RK806_ON_SOURCE			0x74
++#define RK806_OFF_SOURCE		0x75
++#define RK806_PWRON_KEY			0x76
++#define RK806_INT_STS0			0x77
++#define RK806_INT_MSK0			0x78
++#define RK806_INT_STS1			0x79
++#define RK806_INT_MSK1			0x7A
++#define RK806_GPIO_INT_CONFIG		0x7B
++#define RK806_DATA_REG0			0x7C
++#define RK806_DATA_REG1			0x7D
++#define RK806_DATA_REG2			0x7E
++#define RK806_DATA_REG3			0x7F
++#define RK806_DATA_REG4			0x80
++#define RK806_DATA_REG5			0x81
++#define RK806_DATA_REG6			0x82
++#define RK806_DATA_REG7			0x83
++#define RK806_DATA_REG8			0x84
++#define RK806_DATA_REG9			0x85
++#define RK806_DATA_REG10		0x86
++#define RK806_DATA_REG11		0x87
++#define RK806_DATA_REG12		0x88
++#define RK806_DATA_REG13		0x89
++#define RK806_DATA_REG14		0x8A
++#define RK806_DATA_REG15		0x8B
++#define RK806_TM_REG			0x8C
++#define RK806_OTP_EN_REG		0x8D
++#define RK806_FUNC_OTP_EN_REG		0x8E
++#define RK806_TEST_REG1			0x8F
++#define RK806_TEST_REG2			0x90
++#define RK806_TEST_REG3			0x91
++#define RK806_TEST_REG4			0x92
++#define RK806_TEST_REG5			0x93
++#define RK806_BUCK_VSEL_OTP_REG0	0x94
++#define RK806_BUCK_VSEL_OTP_REG1	0x95
++#define RK806_BUCK_VSEL_OTP_REG2	0x96
++#define RK806_BUCK_VSEL_OTP_REG3	0x97
++#define RK806_BUCK_VSEL_OTP_REG4	0x98
++#define RK806_BUCK_VSEL_OTP_REG5	0x99
++#define RK806_BUCK_VSEL_OTP_REG6	0x9A
++#define RK806_BUCK_VSEL_OTP_REG7	0x9B
++#define RK806_BUCK_VSEL_OTP_REG8	0x9C
++#define RK806_BUCK_VSEL_OTP_REG9	0x9D
++#define RK806_NLDO1_VSEL_OTP_REG0	0x9E
++#define RK806_NLDO1_VSEL_OTP_REG1	0x9F
++#define RK806_NLDO1_VSEL_OTP_REG2	0xA0
++#define RK806_NLDO1_VSEL_OTP_REG3	0xA1
++#define RK806_NLDO1_VSEL_OTP_REG4	0xA2
++#define RK806_PLDO_VSEL_OTP_REG0	0xA3
++#define RK806_PLDO_VSEL_OTP_REG1	0xA4
++#define RK806_PLDO_VSEL_OTP_REG2	0xA5
++#define RK806_PLDO_VSEL_OTP_REG3	0xA6
++#define RK806_PLDO_VSEL_OTP_REG4	0xA7
++#define RK806_PLDO_VSEL_OTP_REG5	0xA8
++#define RK806_BUCK_EN_OTP_REG1		0xA9
++#define RK806_NLDO_EN_OTP_REG1		0xAA
++#define RK806_PLDO_EN_OTP_REG1		0xAB
++#define RK806_BUCK_FB_RES_OTP_REG1	0xAC
++#define RK806_OTP_RESEV_REG0		0xAD
++#define RK806_OTP_RESEV_REG1		0xAE
++#define RK806_OTP_RESEV_REG2		0xAF
++#define RK806_OTP_RESEV_REG3		0xB0
++#define RK806_OTP_RESEV_REG4		0xB1
++#define RK806_BUCK_SEQ_REG0		0xB2
++#define RK806_BUCK_SEQ_REG1		0xB3
++#define RK806_BUCK_SEQ_REG2		0xB4
++#define RK806_BUCK_SEQ_REG3		0xB5
++#define RK806_BUCK_SEQ_REG4		0xB6
++#define RK806_BUCK_SEQ_REG5		0xB7
++#define RK806_BUCK_SEQ_REG6		0xB8
++#define RK806_BUCK_SEQ_REG7		0xB9
++#define RK806_BUCK_SEQ_REG8		0xBA
++#define RK806_BUCK_SEQ_REG9		0xBB
++#define RK806_BUCK_SEQ_REG10		0xBC
++#define RK806_BUCK_SEQ_REG11		0xBD
++#define RK806_BUCK_SEQ_REG12		0xBE
++#define RK806_BUCK_SEQ_REG13		0xBF
++#define RK806_BUCK_SEQ_REG14		0xC0
++#define RK806_BUCK_SEQ_REG15		0xC1
++#define RK806_BUCK_SEQ_REG16		0xC2
++#define RK806_BUCK_SEQ_REG17		0xC3
++#define RK806_HK_TRIM_REG1		0xC4
++#define RK806_HK_TRIM_REG2		0xC5
++#define RK806_BUCK_REF_TRIM_REG1	0xC6
++#define RK806_BUCK_REF_TRIM_REG2	0xC7
++#define RK806_BUCK_REF_TRIM_REG3	0xC8
++#define RK806_BUCK_REF_TRIM_REG4	0xC9
++#define RK806_BUCK_REF_TRIM_REG5	0xCA
++#define RK806_BUCK_OSC_TRIM_REG1	0xCB
++#define RK806_BUCK_OSC_TRIM_REG2	0xCC
++#define RK806_BUCK_OSC_TRIM_REG3	0xCD
++#define RK806_BUCK_OSC_TRIM_REG4	0xCE
++#define RK806_BUCK_OSC_TRIM_REG5	0xCF
++#define RK806_BUCK_TRIM_ZCDIOS_REG1	0xD0
++#define RK806_BUCK_TRIM_ZCDIOS_REG2	0xD1
++#define RK806_NLDO_TRIM_REG1		0xD2
++#define RK806_NLDO_TRIM_REG2		0xD3
++#define RK806_NLDO_TRIM_REG3		0xD4
++#define RK806_PLDO_TRIM_REG1		0xD5
++#define RK806_PLDO_TRIM_REG2		0xD6
++#define RK806_PLDO_TRIM_REG3		0xD7
++#define RK806_TRIM_ICOMP_REG1		0xD8
++#define RK806_TRIM_ICOMP_REG2		0xD9
++#define RK806_EFUSE_CONTROL_REGH	0xDA
++#define RK806_FUSE_PROG_REG		0xDB
++#define RK806_MAIN_FSM_STS_REG		0xDD
++#define RK806_FSM_REG			0xDE
++#define RK806_TOP_RESEV_OFFR		0xEC
++#define RK806_TOP_RESEV_POR		0xED
++#define RK806_BUCK_VRSN_REG1		0xEE
++#define RK806_BUCK_VRSN_REG2		0xEF
++#define RK806_NLDO_RLOAD_SEL_REG1	0xF0
++#define RK806_PLDO_RLOAD_SEL_REG1	0xF1
++#define RK806_PLDO_RLOAD_SEL_REG2	0xF2
++#define RK806_BUCK_CMIN_MX_REG1		0xF3
++#define RK806_BUCK_CMIN_MX_REG2		0xF4
++#define RK806_BUCK_FREQ_SET_REG1	0xF5
++#define RK806_BUCK_FREQ_SET_REG2	0xF6
++#define RK806_BUCK_RS_MEABS_REG1	0xF7
++#define RK806_BUCK_RS_MEABS_REG2	0xF8
++#define RK806_BUCK_RS_ZDLEB_REG1	0xF9
++#define RK806_BUCK_RS_ZDLEB_REG2	0xFA
++#define RK806_BUCK_RSERVE_REG1		0xFB
++#define RK806_BUCK_RSERVE_REG2		0xFC
++#define RK806_BUCK_RSERVE_REG3		0xFD
++#define RK806_BUCK_RSERVE_REG4		0xFE
++#define RK806_BUCK_RSERVE_REG5		0xFF
++
++/* INT_STS Register field definitions */
++#define RK806_INT_STS_PWRON_FALL	BIT(0)
++#define RK806_INT_STS_PWRON_RISE	BIT(1)
++#define RK806_INT_STS_PWRON		BIT(2)
++#define RK806_INT_STS_PWRON_LP		BIT(3)
++#define RK806_INT_STS_HOTDIE		BIT(4)
++#define RK806_INT_STS_VDC_RISE		BIT(5)
++#define RK806_INT_STS_VDC_FALL		BIT(6)
++#define RK806_INT_STS_VB_LO		BIT(7)
++#define RK806_INT_STS_REV0		BIT(0)
++#define RK806_INT_STS_REV1		BIT(1)
++#define RK806_INT_STS_REV2		BIT(2)
++#define RK806_INT_STS_CRC_ERROR		BIT(3)
++#define RK806_INT_STS_SLP3_GPIO		BIT(4)
++#define RK806_INT_STS_SLP2_GPIO		BIT(5)
++#define RK806_INT_STS_SLP1_GPIO		BIT(6)
++#define RK806_INT_STS_WDT		BIT(7)
++
++/* SPI command */
++#define RK806_CMD_READ			0
++#define RK806_CMD_WRITE			BIT(7)
++#define RK806_CMD_CRC_EN		BIT(6)
++#define RK806_CMD_CRC_DIS		0
++#define RK806_CMD_LEN_MSK		0x0f
++#define RK806_REG_H			0x00
++
++#define VERSION_AB		0x01
++
++enum rk806_reg_id {
++	RK806_ID_DCDC1 = 0,
++	RK806_ID_DCDC2,
++	RK806_ID_DCDC3,
++	RK806_ID_DCDC4,
++	RK806_ID_DCDC5,
++	RK806_ID_DCDC6,
++	RK806_ID_DCDC7,
++	RK806_ID_DCDC8,
++	RK806_ID_DCDC9,
++	RK806_ID_DCDC10,
++
++	RK806_ID_NLDO1,
++	RK806_ID_NLDO2,
++	RK806_ID_NLDO3,
++	RK806_ID_NLDO4,
++	RK806_ID_NLDO5,
++
++	RK806_ID_PLDO1,
++	RK806_ID_PLDO2,
++	RK806_ID_PLDO3,
++	RK806_ID_PLDO4,
++	RK806_ID_PLDO5,
++	RK806_ID_PLDO6,
++	RK806_ID_END,
++};
++
++/* Define the RK806 IRQ numbers */
++enum rk806_irqs {
++	/* INT_STS0 registers */
++	RK806_IRQ_PWRON_FALL,
++	RK806_IRQ_PWRON_RISE,
++	RK806_IRQ_PWRON,
++	RK806_IRQ_PWRON_LP,
++	RK806_IRQ_HOTDIE,
++	RK806_IRQ_VDC_RISE,
++	RK806_IRQ_VDC_FALL,
++	RK806_IRQ_VB_LO,
++
++	/* INT_STS0 registers */
++	RK806_IRQ_REV0,
++	RK806_IRQ_REV1,
++	RK806_IRQ_REV2,
++	RK806_IRQ_CRC_ERROR,
++	RK806_IRQ_SLP3_GPIO,
++	RK806_IRQ_SLP2_GPIO,
++	RK806_IRQ_SLP1_GPIO,
++	RK806_IRQ_WDT,
++};
++
++/* VCC1 Low Voltage Threshold */
++enum rk806_lv_sel {
++	VB_LO_SEL_2800,
++	VB_LO_SEL_2900,
++	VB_LO_SEL_3000,
++	VB_LO_SEL_3100,
++	VB_LO_SEL_3200,
++	VB_LO_SEL_3300,
++	VB_LO_SEL_3400,
++	VB_LO_SEL_3500,
++};
++
++/* System Shutdown Voltage Select */
++enum rk806_uv_sel {
++	VB_UV_SEL_2700,
++	VB_UV_SEL_2800,
++	VB_UV_SEL_2900,
++	VB_UV_SEL_3000,
++	VB_UV_SEL_3100,
++	VB_UV_SEL_3200,
++	VB_UV_SEL_3300,
++	VB_UV_SEL_3400,
++};
++
++/* Pin Function */
++enum rk806_pwrctrl_fun {
++	PWRCTRL_NULL_FUN,
++	PWRCTRL_SLP_FUN,
++	PWRCTRL_POWOFF_FUN,
++	PWRCTRL_RST_FUN,
++	PWRCTRL_DVS_FUN,
++	PWRCTRL_GPIO_FUN,
++};
++
++/* Pin Polarity */
++enum rk806_pin_level {
++	POL_LOW,
++	POL_HIGH,
++};
++
++enum rk806_vsel_ctr_sel {
++	CTR_BY_NO_EFFECT,
++	CTR_BY_PWRCTRL1,
++	CTR_BY_PWRCTRL2,
++	CTR_BY_PWRCTRL3,
++};
++
++enum rk806_dvs_ctr_sel {
++	CTR_SEL_NO_EFFECT,
++	CTR_SEL_DVS_START1,
++	CTR_SEL_DVS_START2,
++	CTR_SEL_DVS_START3,
++};
++
++enum rk806_pin_dr_sel {
++	RK806_PIN_INPUT,
++	RK806_PIN_OUTPUT,
++};
++
++#define RK806_INT_POL_MSK		BIT(1)
++#define RK806_INT_POL_H			BIT(1)
++#define RK806_INT_POL_L			0
++
++#define RK806_SLAVE_RESTART_FUN_MSK	BIT(1)
++#define RK806_SLAVE_RESTART_FUN_EN	BIT(1)
++#define RK806_SLAVE_RESTART_FUN_OFF	0
++
++#define RK806_SYS_ENB2_2M_MSK		BIT(1)
++#define RK806_SYS_ENB2_2M_EN		BIT(1)
++#define RK806_SYS_ENB2_2M_OFF		0
++
++enum rk806_int_fun {
++	RK806_INT_ONLY,
++	RK806_INT_ADN_WKUP,
++};
++
++enum rk806_dvs_mode {
++	RK806_DVS_NOT_SUPPORT,
++	RK806_DVS_START1,
++	RK806_DVS_START2,
++	RK806_DVS_START3,
++	RK806_DVS_PWRCTRL1,
++	RK806_DVS_PWRCTRL2,
++	RK806_DVS_PWRCTRL3,
++	RK806_DVS_START_PWRCTR1,
++	RK806_DVS_START_PWRCTR2,
++	RK806_DVS_START_PWRCTR3,
++	RK806_DVS_END,
++};
++
+ /* RK808 IRQ Definitions */
+ #define RK808_IRQ_VOUT_LO	0
+ #define RK808_IRQ_VB_LO		1
+@@ -780,6 +1188,7 @@ enum {
+ 
+ enum {
+ 	RK805_ID = 0x8050,
++	RK806_ID = 0x8060,
+ 	RK808_ID = 0x0000,
+ 	RK809_ID = 0x8090,
+ 	RK817_ID = 0x8170,
diff --git a/target/linux/rockchip/patches-6.1/234-regulator-rk808-reduce-struct-rk808-usage.patch b/target/linux/rockchip/patches-6.1/234-regulator-rk808-reduce-struct-rk808-usage.patch
new file mode 100644
index 00000000000..b6782f0487f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/234-regulator-rk808-reduce-struct-rk808-usage.patch
@@ -0,0 +1,83 @@
+From a4500ef729453d29aa91ff2ccbb838818ebb8a35 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Oct 2022 22:42:40 +0200
+Subject: [PATCH 234/383] regulator: rk808: reduce 'struct rk808' usage
+
+Reduce usage of 'struct rk808' (driver data of the parent MFD), so
+that only the chip variant field is still being accessed directly.
+This allows restructuring the MFD driver to support SPI based
+PMICs.
+
+Acked-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221020204251.108565-3-sebastian.reichel@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 20 ++++++++++++--------
+ 1 file changed, 12 insertions(+), 8 deletions(-)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -14,7 +14,6 @@
+ 
+ #include <linux/delay.h>
+ #include <linux/gpio.h>
+-#include <linux/i2c.h>
+ #include <linux/module.h>
+ #include <linux/of_device.h>
+ #include <linux/of_gpio.h>
+@@ -1286,19 +1285,23 @@ dt_parse_end:
+ static int rk808_regulator_probe(struct platform_device *pdev)
+ {
+ 	struct rk808 *rk808 = dev_get_drvdata(pdev->dev.parent);
+-	struct i2c_client *client = rk808->i2c;
+ 	struct regulator_config config = {};
+ 	struct regulator_dev *rk808_rdev;
+ 	struct rk808_regulator_data *pdata;
+ 	const struct regulator_desc *regulators;
++	struct regmap *regmap;
+ 	int ret, i, nregulators;
+ 
++	regmap = dev_get_regmap(pdev->dev.parent, NULL);
++	if (!regmap)
++		return -ENODEV;
++
+ 	pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
+ 	if (!pdata)
+ 		return -ENOMEM;
+ 
+-	ret = rk808_regulator_dt_parse_pdata(&pdev->dev, &client->dev,
+-					     rk808->regmap, pdata);
++	ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent,
++					     regmap, pdata);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1326,21 +1329,22 @@ static int rk808_regulator_probe(struct
+ 		nregulators = RK818_NUM_REGULATORS;
+ 		break;
+ 	default:
+-		dev_err(&client->dev, "unsupported RK8XX ID %lu\n",
++		dev_err(&pdev->dev, "unsupported RK8XX ID %lu\n",
+ 			rk808->variant);
+ 		return -EINVAL;
+ 	}
+ 
+-	config.dev = &client->dev;
++	config.dev = &pdev->dev;
++	config.dev->of_node = pdev->dev.parent->of_node;
+ 	config.driver_data = pdata;
+-	config.regmap = rk808->regmap;
++	config.regmap = regmap;
+ 
+ 	/* Instantiate the regulators */
+ 	for (i = 0; i < nregulators; i++) {
+ 		rk808_rdev = devm_regulator_register(&pdev->dev,
+ 						     &regulators[i], &config);
+ 		if (IS_ERR(rk808_rdev)) {
+-			dev_err(&client->dev,
++			dev_err(&pdev->dev,
+ 				"failed to register %d regulator\n", i);
+ 			return PTR_ERR(rk808_rdev);
+ 		}
diff --git a/target/linux/rockchip/patches-6.1/235-regulator-rk808-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/235-regulator-rk808-Use-dev_err_probe.patch
new file mode 100644
index 00000000000..469eb267ddf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/235-regulator-rk808-Use-dev_err_probe.patch
@@ -0,0 +1,35 @@
+From cfd259d1f7d6c8dbc15a68628d52657f0e1c0581 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Oct 2022 22:42:49 +0200
+Subject: [PATCH 235/383] regulator: rk808: Use dev_err_probe
+
+Print error message for potential EPROBE_DEFER error using
+dev_err_probe, which captures the reason in
+/sys/kernel/debug/devices_deferred and otherwise silences
+the message.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221020204251.108565-12-sebastian.reichel@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 8 +++-----
+ 1 file changed, 3 insertions(+), 5 deletions(-)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -1343,11 +1343,9 @@ static int rk808_regulator_probe(struct
+ 	for (i = 0; i < nregulators; i++) {
+ 		rk808_rdev = devm_regulator_register(&pdev->dev,
+ 						     &regulators[i], &config);
+-		if (IS_ERR(rk808_rdev)) {
+-			dev_err(&pdev->dev,
+-				"failed to register %d regulator\n", i);
+-			return PTR_ERR(rk808_rdev);
+-		}
++		if (IS_ERR(rk808_rdev))
++			return dev_err_probe(&pdev->dev, PTR_ERR(rk808_rdev),
++					     "failed to register %d regulator\n", i);
+ 	}
+ 
+ 	return 0;
diff --git a/target/linux/rockchip/patches-6.1/236-regulator-Set-PROBE_PREFER_ASYNCHRONOUS-for-drivers-.patch b/target/linux/rockchip/patches-6.1/236-regulator-Set-PROBE_PREFER_ASYNCHRONOUS-for-drivers-.patch
new file mode 100644
index 00000000000..92b2a237702
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/236-regulator-Set-PROBE_PREFER_ASYNCHRONOUS-for-drivers-.patch
@@ -0,0 +1,57 @@
+From 6b7b6e2e7d88a5471315b410e87fcd2dca87d464 Mon Sep 17 00:00:00 2001
+From: Douglas Anderson <dianders@chromium.org>
+Date: Thu, 16 Mar 2023 12:54:38 -0700
+Subject: [PATCH 236/383] regulator: Set PROBE_PREFER_ASYNCHRONOUS for drivers
+ that existed in 4.14
+
+Probing of regulators can be a slow operation and can contribute to
+slower boot times. This is especially true if a regulator is turned on
+at probe time (with regulator-boot-on or regulator-always-on) and the
+regulator requires delays (off-on-time, ramp time, etc).
+
+While the overall kernel is not ready to switch to async probe by
+default, as per the discussion on the mailing lists [1] it is believed
+that the regulator subsystem is in good shape and we can move
+regulator drivers over wholesale. There is no way to just magically
+opt in all regulators (regulators are just normal drivers like
+platform_driver), so we set PROBE_PREFER_ASYNCHRONOUS for all
+regulators found in 'drivers/regulator' individually.
+
+Given the number of drivers touched and the impossibility to test this
+ahead of time, it wouldn't be shocking at all if this caused a
+regression for someone. If there is a regression caused by this patch,
+it's likely to be one of the cases talked about in [1]. As a "quick
+fix", drivers involved in the regression could be fixed by changing
+them to PROBE_FORCE_SYNCHRONOUS. That being said, the correct fix
+would be to directly fix the problem that caused the issue with async
+probe.
+
+The approach here follows a similar approach that was used for the mmc
+subsystem several years ago [2]. In fact, I ran nearly the same python
+script to auto-generate the changes. The only thing I changed was to
+search for "i2c_driver", "spmi_driver", and "spi_driver" in addition
+to "platform_driver".
+
+[1] https://lore.kernel.org/r/06db017f-e985-4434-8d1d-02ca2100cca0@sirena.org.uk
+[2] https://lore.kernel.org/r/20200903232441.2694866-1-dianders@chromium.org/
+
+Signed-off-by: Douglas Anderson <dianders@chromium.org>
+Link: https://lore.kernel.org/r/20230316125351.1.I2a4677392a38db5758dee0788b2cea5872562a82@changeid
+Signed-off-by: Mark Brown <broonie@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -1354,7 +1354,8 @@ static int rk808_regulator_probe(struct
+ static struct platform_driver rk808_regulator_driver = {
+ 	.probe = rk808_regulator_probe,
+ 	.driver = {
+-		.name = "rk808-regulator"
++		.name = "rk808-regulator",
++		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
+ 	},
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/237-dt-bindings-usb-Add-H616-compatible-string.patch b/target/linux/rockchip/patches-6.1/237-dt-bindings-usb-Add-H616-compatible-string.patch
new file mode 100644
index 00000000000..391082eb7a6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/237-dt-bindings-usb-Add-H616-compatible-string.patch
@@ -0,0 +1,39 @@
+From 8cfb9b22a521a6aa2a39f3ca228540deda656cd4 Mon Sep 17 00:00:00 2001
+From: Andre Przywara <andre.przywara@arm.com>
+Date: Mon, 31 Oct 2022 11:13:52 +0000
+Subject: [PATCH 237/383] dt-bindings: usb: Add H616 compatible string
+
+The Allwinner H616 contains four fully OHCI/EHCI compatible USB host
+controllers, so just add their compatible strings to the list of
+generic OHCI/EHCI controllers.
+
+Signed-off-by: Andre Przywara <andre.przywara@arm.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20221031111358.3387297-2-andre.przywara@arm.com
+Signed-off-by: Jernej Skrabec <jernej.skrabec@gmail.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
+ Documentation/devicetree/bindings/usb/generic-ohci.yaml | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+@@ -30,6 +30,7 @@ properties:
+               - allwinner,sun4i-a10-ehci
+               - allwinner,sun50i-a64-ehci
+               - allwinner,sun50i-h6-ehci
++              - allwinner,sun50i-h616-ehci
+               - allwinner,sun5i-a13-ehci
+               - allwinner,sun6i-a31-ehci
+               - allwinner,sun7i-a20-ehci
+--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+@@ -20,6 +20,7 @@ properties:
+               - allwinner,sun4i-a10-ohci
+               - allwinner,sun50i-a64-ohci
+               - allwinner,sun50i-h6-ohci
++              - allwinner,sun50i-h616-ohci
+               - allwinner,sun5i-a13-ohci
+               - allwinner,sun6i-a31-ohci
+               - allwinner,sun7i-a20-ohci
diff --git a/target/linux/rockchip/patches-6.1/238-dt-bindings-usb-Convert-multiple-usb-ohci-bindings-t.patch b/target/linux/rockchip/patches-6.1/238-dt-bindings-usb-Convert-multiple-usb-ohci-bindings-t.patch
new file mode 100644
index 00000000000..97053aec054
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/238-dt-bindings-usb-Convert-multiple-usb-ohci-bindings-t.patch
@@ -0,0 +1,178 @@
+From fa350fa7a0dd8a4c7b8b303cc9d754f060f765ab Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Mon, 23 Jan 2023 21:05:16 -0600
+Subject: [PATCH 238/383] dt-bindings: usb: Convert multiple "usb-ohci"
+ bindings to DT schema
+
+"usb-ohci" is another "generic" OHCI controller compatible string used by
+several platforms. Add it to the generic-ohci.yaml schema and remove all
+the old binding docs.
+
+Marvell pxa-usb.txt has "usb-ohci" in the example, but actual users don't,
+so drop it.
+
+Signed-off-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230110-dt-usb-v3-2-5af0541fcf8c@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/powerpc/nintendo/wii.txt         | 10 ------
+ .../devicetree/bindings/usb/generic-ohci.yaml | 28 +++++++++++++--
+ .../devicetree/bindings/usb/ohci-nxp.txt      | 24 -------------
+ .../devicetree/bindings/usb/pxa-usb.txt       |  2 +-
+ .../devicetree/bindings/usb/spear-usb.txt     | 35 -------------------
+ 5 files changed, 26 insertions(+), 73 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/usb/ohci-nxp.txt
+ delete mode 100644 Documentation/devicetree/bindings/usb/spear-usb.txt
+
+--- a/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
++++ b/Documentation/devicetree/bindings/powerpc/nintendo/wii.txt
+@@ -97,16 +97,6 @@ Nintendo Wii device tree
+    - reg : should contain the EXI registers location and length
+    - interrupts : should contain the EXI interrupt
+ 
+-1.g) The Open Host Controller Interface (OHCI) nodes
+-
+-  Represent the USB 1.x Open Host Controller Interfaces.
+-
+-  Required properties:
+-
+-   - compatible : should be "nintendo,hollywood-usb-ohci","usb-ohci"
+-   - reg : should contain the OHCI registers location and length
+-   - interrupts : should contain the OHCI interrupt
+-
+ 1.h) The Enhanced Host Controller Interface (EHCI) node
+ 
+   Represents the USB 2.0 Enhanced Host Controller Interface.
+--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+@@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-sche
+ 
+ title: USB OHCI Controller
+ 
+-allOf:
+-  - $ref: "usb-hcd.yaml"
+-
+ maintainers:
+   - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+ 
+@@ -50,6 +47,13 @@ properties:
+               - snps,hsdk-v1.0-ohci
+           - const: generic-ohci
+       - const: generic-ohci
++      - items:
++          - enum:
++              - cavium,octeon-6335-ohci
++              - nintendo,hollywood-usb-ohci
++              - nxp,ohci-nxp
++              - st,spear600-ohci
++          - const: usb-ohci
+ 
+   reg:
+     maxItems: 1
+@@ -119,11 +123,29 @@ properties:
+       - host
+       - otg
+ 
++  transceiver:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      The associated ISP1301 device. Necessary for the UDC controller for
++      connecting to the USB physical layer.
++
+ required:
+   - compatible
+   - reg
+   - interrupts
+ 
++allOf:
++  - $ref: usb-hcd.yaml
++  - if:
++      not:
++        properties:
++          compatible:
++            contains:
++              const: nxp,ohci-nxp
++    then:
++      properties:
++        transceiver: false
++
+ additionalProperties: false
+ 
+ examples:
+--- a/Documentation/devicetree/bindings/usb/ohci-nxp.txt
++++ /dev/null
+@@ -1,24 +0,0 @@
+-* OHCI controller, NXP ohci-nxp variant
+-
+-Required properties:
+-- compatible: must be "nxp,ohci-nxp"
+-- reg: physical base address of the controller and length of memory mapped
+-  region.
+-- interrupts: The OHCI interrupt
+-- transceiver: phandle of the associated ISP1301 device - this is necessary for
+-               the UDC controller for connecting to the USB physical layer
+-
+-Example (LPC32xx):
+-
+-	isp1301: usb-transceiver@2c {
+-		compatible = "nxp,isp1301";
+-		reg = <0x2c>;
+-	};
+-
+-	ohci@31020000 {
+-		compatible = "nxp,ohci-nxp";
+-		reg = <0x31020000 0x300>;
+-		interrupt-parent = <&mic>;
+-		interrupts = <0x3b 0>;
+-		transceiver = <&isp1301>;
+-	};
+--- a/Documentation/devicetree/bindings/usb/pxa-usb.txt
++++ b/Documentation/devicetree/bindings/usb/pxa-usb.txt
+@@ -22,7 +22,7 @@ Optional properties:
+ Example:
+ 
+ 	usb0: ohci@4c000000 {
+-		compatible = "marvell,pxa-ohci", "usb-ohci";
++		compatible = "marvell,pxa-ohci";
+ 		reg = <0x4c000000 0x100000>;
+ 		interrupts = <18>;
+ 		marvell,enable-port1;
+--- a/Documentation/devicetree/bindings/usb/spear-usb.txt
++++ /dev/null
+@@ -1,35 +0,0 @@
+-ST SPEAr SoC USB controllers:
+------------------------------
+-
+-EHCI:
+------
+-
+-Required properties:
+-- compatible: "st,spear600-ehci"
+-- interrupts: Should contain the EHCI interrupt
+-
+-Example:
+-
+-	ehci@e1800000 {
+-		compatible = "st,spear600-ehci", "usb-ehci";
+-		reg = <0xe1800000 0x1000>;
+-		interrupt-parent = <&vic1>;
+-		interrupts = <27>;
+-	};
+-
+-
+-OHCI:
+------
+-
+-Required properties:
+-- compatible: "st,spear600-ohci"
+-- interrupts: Should contain the OHCI interrupt
+-
+-Example:
+-
+-	ohci@e1900000 {
+-		compatible = "st,spear600-ohci", "usb-ohci";
+-		reg = <0xe1800000 0x1000>;
+-		interrupt-parent = <&vic1>;
+-		interrupts = <26>;
+-	};
diff --git a/target/linux/rockchip/patches-6.1/239-dt-bindings-usb-Convert-OMAP-OHCI-EHCI-bindings-to-s.patch b/target/linux/rockchip/patches-6.1/239-dt-bindings-usb-Convert-OMAP-OHCI-EHCI-bindings-to-s.patch
new file mode 100644
index 00000000000..baa1969cfe0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/239-dt-bindings-usb-Convert-OMAP-OHCI-EHCI-bindings-to-s.patch
@@ -0,0 +1,132 @@
+From 9fa0037b606b7ee403ca098b12ea6dd5711b2c95 Mon Sep 17 00:00:00 2001
+From: Rob Herring <robh@kernel.org>
+Date: Mon, 23 Jan 2023 21:05:17 -0600
+Subject: [PATCH 239/383] dt-bindings: usb: Convert OMAP OHCI/EHCI bindings to
+ schema
+
+The OMAP OHCI and EHCI USB host bindings follow the generic binding, so
+add the compatibles and remove the old txt binding docs.
+
+The examples in omap-usb-host.txt don't match actual users, so update
+them dropping the fallback compatible.
+
+Signed-off-by: Rob Herring <robh@kernel.org>
+Acked-by: Lee Jones <lee@kernel.org>
+Link: https://lore.kernel.org/r/20230110-dt-usb-v3-3-5af0541fcf8c@kernel.org
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/mfd/omap-usb-host.txt |  8 ++---
+ .../devicetree/bindings/usb/ehci-omap.txt     | 31 -------------------
+ .../devicetree/bindings/usb/generic-ehci.yaml |  1 +
+ .../devicetree/bindings/usb/generic-ohci.yaml |  4 ++-
+ .../devicetree/bindings/usb/ohci-omap3.txt    | 15 ---------
+ 5 files changed, 8 insertions(+), 51 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/usb/ehci-omap.txt
+ delete mode 100644 Documentation/devicetree/bindings/usb/ohci-omap3.txt
+
+--- a/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
++++ b/Documentation/devicetree/bindings/mfd/omap-usb-host.txt
+@@ -64,8 +64,8 @@ Required properties if child node exists
+ Properties for children:
+ 
+ The OMAP HS USB Host subsystem contains EHCI and OHCI controllers.
+-See Documentation/devicetree/bindings/usb/ehci-omap.txt and
+-Documentation/devicetree/bindings/usb/ohci-omap3.txt.
++See Documentation/devicetree/bindings/usb/generic-ehci.yaml and
++Documentation/devicetree/bindings/usb/generic-ohci.yaml.
+ 
+ Example for OMAP4:
+ 
+@@ -78,14 +78,14 @@ usbhshost: usbhshost@4a064000 {
+ 	ranges;
+ 
+ 	usbhsohci: ohci@4a064800 {
+-		compatible = "ti,ohci-omap3", "usb-ohci";
++		compatible = "ti,ohci-omap3";
+ 		reg = <0x4a064800 0x400>;
+ 		interrupt-parent = <&gic>;
+ 		interrupts = <0 76 0x4>;
+ 	};
+ 
+ 	usbhsehci: ehci@4a064c00 {
+-		compatible = "ti,ehci-omap", "usb-ehci";
++		compatible = "ti,ehci-omap";
+ 		reg = <0x4a064c00 0x400>;
+ 		interrupt-parent = <&gic>;
+ 		interrupts = <0 77 0x4>;
+--- a/Documentation/devicetree/bindings/usb/ehci-omap.txt
++++ /dev/null
+@@ -1,31 +0,0 @@
+-OMAP HS USB EHCI controller
+-
+-This device is usually the child of the omap-usb-host
+-Documentation/devicetree/bindings/mfd/omap-usb-host.txt
+-
+-Required properties:
+-
+-- compatible: should be "ti,ehci-omap"
+-- reg: should contain one register range i.e. start and length
+-- interrupts: description of the interrupt line
+-
+-Optional properties:
+-
+-- phys: list of phandles to PHY nodes.
+-  This property is required if at least one of the ports are in
+-  PHY mode i.e. OMAP_EHCI_PORT_MODE_PHY
+-
+-To specify the port mode, see
+-Documentation/devicetree/bindings/mfd/omap-usb-host.txt
+-
+-Example for OMAP4:
+-
+-usbhsehci: ehci@4a064c00 {
+-	compatible = "ti,ehci-omap";
+-	reg = <0x4a064c00 0x400>;
+-	interrupts = <0 77 0x4>;
+-};
+-
+-&usbhsehci {
+-	phys = <&hsusb1_phy 0 &hsusb3_phy>;
+-};
+--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+@@ -74,6 +74,7 @@ properties:
+           - const: usb-ehci
+       - enum:
+           - generic-ehci
++          - ti,ehci-omap
+           - usb-ehci
+ 
+   reg:
+--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+@@ -46,7 +46,9 @@ properties:
+               - ingenic,jz4740-ohci
+               - snps,hsdk-v1.0-ohci
+           - const: generic-ohci
+-      - const: generic-ohci
++      - enum:
++          - generic-ohci
++          - ti,ohci-omap3
+       - items:
+           - enum:
+               - cavium,octeon-6335-ohci
+--- a/Documentation/devicetree/bindings/usb/ohci-omap3.txt
++++ /dev/null
+@@ -1,15 +0,0 @@
+-OMAP HS USB OHCI controller (OMAP3 and later)
+-
+-Required properties:
+-
+-- compatible: should be "ti,ohci-omap3"
+-- reg: should contain one register range i.e. start and length
+-- interrupts: description of the interrupt line
+-
+-Example for OMAP4:
+-
+-usbhsohci: ohci@4a064800 {
+-	compatible = "ti,ohci-omap3";
+-	reg = <0x4a064800 0x400>;
+-	interrupts = <0 76 0x4>;
+-};
diff --git a/target/linux/rockchip/patches-6.1/240-dt-bindings-usb-allow-evaluated-properties-in-OHCI-c.patch b/target/linux/rockchip/patches-6.1/240-dt-bindings-usb-allow-evaluated-properties-in-OHCI-c.patch
new file mode 100644
index 00000000000..6a546fced9d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/240-dt-bindings-usb-allow-evaluated-properties-in-OHCI-c.patch
@@ -0,0 +1,33 @@
+From af3c0f7f051205118c47f893e1e65e4b8b7fa120 Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Rafa=C5=82=20Mi=C5=82ecki?= <rafal@milecki.pl>
+Date: Tue, 28 Feb 2023 16:21:05 +0100
+Subject: [PATCH 240/383] dt-bindings: usb: allow evaluated properties in OHCI
+ controllers
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+This binding uses usb-hcd.yaml so replace additionalProperties with
+unevaluatedProperties to allow generic USB HCD properties. It's how EHCI
+and XHCI bindings work too.
+
+Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
+Acked-by: Rob Herring <robh@kernel.org>
+Link: https://lore.kernel.org/r/20230228152105.25358-1-zajec5@gmail.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/usb/generic-ohci.yaml | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+@@ -148,7 +148,7 @@ allOf:
+       properties:
+         transceiver: false
+ 
+-additionalProperties: false
++unevaluatedProperties: false
+ 
+ examples:
+   - |
diff --git a/target/linux/rockchip/patches-6.1/241-pinctrl-rk805-add-rk806-pinctrl-support.patch b/target/linux/rockchip/patches-6.1/241-pinctrl-rk805-add-rk806-pinctrl-support.patch
new file mode 100644
index 00000000000..522174b3bb1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/241-pinctrl-rk805-add-rk806-pinctrl-support.patch
@@ -0,0 +1,337 @@
+From a55798aaa672a9ea67bdd2c22ca922cff79b1fb4 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 4 Jul 2022 18:56:16 +0200
+Subject: [PATCH 241/383] pinctrl: rk805: add rk806 pinctrl support
+
+Add support for rk806 dvs pinctrl to the existing rk805
+driver.
+
+This has been implemented using shengfei Xu's rk806
+specific driver from the vendor tree as reference.
+
+Co-developed-by: shengfei Xu <xsf@rock-chips.com>
+Signed-off-by: shengfei Xu <xsf@rock-chips.com>
+Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
+Acked-by: Linus Walleij <linus.walleij@linaro.org>
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/pinctrl/pinctrl-rk805.c | 189 ++++++++++++++++++++++++++++----
+ 1 file changed, 168 insertions(+), 21 deletions(-)
+
+--- a/drivers/pinctrl/pinctrl-rk805.c
++++ b/drivers/pinctrl/pinctrl-rk805.c
+@@ -1,10 +1,12 @@
+ // SPDX-License-Identifier: GPL-2.0-or-later
+ /*
+- * Pinctrl driver for Rockchip RK805 PMIC
++ * Pinctrl driver for Rockchip RK805/RK806 PMIC
+  *
+  * Copyright (c) 2017, Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+  *
+  * Author: Joseph Chen <chenjh@rock-chips.com>
++ * Author: Xu Shengfei <xsf@rock-chips.com>
+  *
+  * Based on the pinctrl-as3722 driver
+  */
+@@ -44,6 +46,7 @@ struct rk805_pin_group {
+ 
+ /*
+  * @reg: gpio setting register;
++ * @fun_reg: functions select register;
+  * @fun_mask: functions select mask value, when set is gpio;
+  * @dir_mask: input or output mask value, when set is output, otherwise input;
+  * @val_mask: gpio set value, when set is level high, otherwise low;
+@@ -56,6 +59,7 @@ struct rk805_pin_group {
+  */
+ struct rk805_pin_config {
+ 	u8 reg;
++	u8 fun_reg;
+ 	u8 fun_msk;
+ 	u8 dir_msk;
+ 	u8 val_msk;
+@@ -80,22 +84,50 @@ enum rk805_pinmux_option {
+ 	RK805_PINMUX_GPIO,
+ };
+ 
++enum rk806_pinmux_option {
++	RK806_PINMUX_FUN0 = 0,
++	RK806_PINMUX_FUN1,
++	RK806_PINMUX_FUN2,
++	RK806_PINMUX_FUN3,
++	RK806_PINMUX_FUN4,
++	RK806_PINMUX_FUN5,
++};
++
+ enum {
+ 	RK805_GPIO0,
+ 	RK805_GPIO1,
+ };
+ 
++enum {
++	RK806_GPIO_DVS1,
++	RK806_GPIO_DVS2,
++	RK806_GPIO_DVS3
++};
++
+ static const char *const rk805_gpio_groups[] = {
+ 	"gpio0",
+ 	"gpio1",
+ };
+ 
++static const char *const rk806_gpio_groups[] = {
++	"gpio_pwrctrl1",
++	"gpio_pwrctrl2",
++	"gpio_pwrctrl3",
++};
++
+ /* RK805: 2 output only GPIOs */
+ static const struct pinctrl_pin_desc rk805_pins_desc[] = {
+ 	PINCTRL_PIN(RK805_GPIO0, "gpio0"),
+ 	PINCTRL_PIN(RK805_GPIO1, "gpio1"),
+ };
+ 
++/* RK806 */
++static const struct pinctrl_pin_desc rk806_pins_desc[] = {
++	PINCTRL_PIN(RK806_GPIO_DVS1, "gpio_pwrctrl1"),
++	PINCTRL_PIN(RK806_GPIO_DVS2, "gpio_pwrctrl2"),
++	PINCTRL_PIN(RK806_GPIO_DVS3, "gpio_pwrctrl3"),
++};
++
+ static const struct rk805_pin_function rk805_pin_functions[] = {
+ 	{
+ 		.name = "gpio",
+@@ -105,6 +137,45 @@ static const struct rk805_pin_function r
+ 	},
+ };
+ 
++static const struct rk805_pin_function rk806_pin_functions[] = {
++	{
++		.name = "pin_fun0",
++		.groups = rk806_gpio_groups,
++		.ngroups = ARRAY_SIZE(rk806_gpio_groups),
++		.mux_option = RK806_PINMUX_FUN0,
++	},
++	{
++		.name = "pin_fun1",
++		.groups = rk806_gpio_groups,
++		.ngroups = ARRAY_SIZE(rk806_gpio_groups),
++		.mux_option = RK806_PINMUX_FUN1,
++	},
++	{
++		.name = "pin_fun2",
++		.groups = rk806_gpio_groups,
++		.ngroups = ARRAY_SIZE(rk806_gpio_groups),
++		.mux_option = RK806_PINMUX_FUN2,
++	},
++	{
++		.name = "pin_fun3",
++		.groups = rk806_gpio_groups,
++		.ngroups = ARRAY_SIZE(rk806_gpio_groups),
++		.mux_option = RK806_PINMUX_FUN3,
++	},
++	{
++		.name = "pin_fun4",
++		.groups = rk806_gpio_groups,
++		.ngroups = ARRAY_SIZE(rk806_gpio_groups),
++		.mux_option = RK806_PINMUX_FUN4,
++	},
++	{
++		.name = "pin_fun5",
++		.groups = rk806_gpio_groups,
++		.ngroups = ARRAY_SIZE(rk806_gpio_groups),
++		.mux_option = RK806_PINMUX_FUN5,
++	},
++};
++
+ static const struct rk805_pin_group rk805_pin_groups[] = {
+ 	{
+ 		.name = "gpio0",
+@@ -118,6 +189,24 @@ static const struct rk805_pin_group rk80
+ 	},
+ };
+ 
++static const struct rk805_pin_group rk806_pin_groups[] = {
++	{
++		.name = "gpio_pwrctrl1",
++		.pins = { RK806_GPIO_DVS1 },
++		.npins = 1,
++	},
++	{
++		.name = "gpio_pwrctrl2",
++		.pins = { RK806_GPIO_DVS2 },
++		.npins = 1,
++	},
++	{
++		.name = "gpio_pwrctrl3",
++		.pins = { RK806_GPIO_DVS3 },
++		.npins = 1,
++	}
++};
++
+ #define RK805_GPIO0_VAL_MSK	BIT(0)
+ #define RK805_GPIO1_VAL_MSK	BIT(1)
+ 
+@@ -132,6 +221,40 @@ static const struct rk805_pin_config rk8
+ 	},
+ };
+ 
++#define RK806_PWRCTRL1_DR	BIT(0)
++#define RK806_PWRCTRL2_DR	BIT(1)
++#define RK806_PWRCTRL3_DR	BIT(2)
++#define RK806_PWRCTRL1_DATA	BIT(4)
++#define RK806_PWRCTRL2_DATA	BIT(5)
++#define RK806_PWRCTRL3_DATA	BIT(6)
++#define RK806_PWRCTRL1_FUN	GENMASK(2, 0)
++#define RK806_PWRCTRL2_FUN	GENMASK(6, 4)
++#define RK806_PWRCTRL3_FUN	GENMASK(2, 0)
++
++static struct rk805_pin_config rk806_gpio_cfgs[] = {
++	{
++		.fun_reg = RK806_SLEEP_CONFIG0,
++		.fun_msk = RK806_PWRCTRL1_FUN,
++		.reg = RK806_SLEEP_GPIO,
++		.val_msk = RK806_PWRCTRL1_DATA,
++		.dir_msk = RK806_PWRCTRL1_DR,
++	},
++	{
++		.fun_reg = RK806_SLEEP_CONFIG0,
++		.fun_msk = RK806_PWRCTRL2_FUN,
++		.reg = RK806_SLEEP_GPIO,
++		.val_msk = RK806_PWRCTRL2_DATA,
++		.dir_msk = RK806_PWRCTRL2_DR,
++	},
++	{
++		.fun_reg = RK806_SLEEP_CONFIG1,
++		.fun_msk = RK806_PWRCTRL3_FUN,
++		.reg = RK806_SLEEP_GPIO,
++		.val_msk = RK806_PWRCTRL3_DATA,
++		.dir_msk = RK806_PWRCTRL3_DR,
++	}
++};
++
+ /* generic gpio chip */
+ static int rk805_gpio_get(struct gpio_chip *chip, unsigned int offset)
+ {
+@@ -289,19 +412,13 @@ static int _rk805_pinctrl_set_mux(struct
+ 	if (!pci->pin_cfg[offset].fun_msk)
+ 		return 0;
+ 
+-	if (mux == RK805_PINMUX_GPIO) {
+-		ret = regmap_update_bits(pci->rk808->regmap,
+-					 pci->pin_cfg[offset].reg,
+-					 pci->pin_cfg[offset].fun_msk,
+-					 pci->pin_cfg[offset].fun_msk);
+-		if (ret) {
+-			dev_err(pci->dev, "set gpio%d GPIO failed\n", offset);
+-			return ret;
+-		}
+-	} else {
+-		dev_err(pci->dev, "Couldn't find function mux %d\n", mux);
+-		return -EINVAL;
+-	}
++	mux <<= ffs(pci->pin_cfg[offset].fun_msk) - 1;
++	ret = regmap_update_bits(pci->rk808->regmap,
++				 pci->pin_cfg[offset].fun_reg,
++				 pci->pin_cfg[offset].fun_msk, mux);
++
++	if (ret)
++		dev_err(pci->dev, "set gpio%d func%d failed\n", offset, mux);
+ 
+ 	return 0;
+ }
+@@ -317,6 +434,22 @@ static int rk805_pinctrl_set_mux(struct
+ 	return _rk805_pinctrl_set_mux(pctldev, offset, mux);
+ }
+ 
++static int rk805_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
++					     struct pinctrl_gpio_range *range,
++					     unsigned int offset)
++{
++	struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
++
++	switch (pci->rk808->variant) {
++	case RK805_ID:
++		return _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
++	case RK806_ID:
++		return _rk805_pinctrl_set_mux(pctldev, offset, RK806_PINMUX_FUN5);
++	}
++
++	return -ENOTSUPP;
++}
++
+ static int rk805_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
+ 					struct pinctrl_gpio_range *range,
+ 					unsigned int offset, bool input)
+@@ -324,13 +457,6 @@ static int rk805_pmx_gpio_set_direction(
+ 	struct rk805_pctrl_info *pci = pinctrl_dev_get_drvdata(pctldev);
+ 	int ret;
+ 
+-	/* switch to gpio function */
+-	ret = _rk805_pinctrl_set_mux(pctldev, offset, RK805_PINMUX_GPIO);
+-	if (ret) {
+-		dev_err(pci->dev, "set gpio%d mux failed\n", offset);
+-		return ret;
+-	}
+-
+ 	/* set direction */
+ 	if (!pci->pin_cfg[offset].dir_msk)
+ 		return 0;
+@@ -352,6 +478,7 @@ static const struct pinmux_ops rk805_pin
+ 	.get_function_name	= rk805_pinctrl_get_func_name,
+ 	.get_function_groups	= rk805_pinctrl_get_func_groups,
+ 	.set_mux		= rk805_pinctrl_set_mux,
++	.gpio_request_enable	= rk805_pinctrl_gpio_request_enable,
+ 	.gpio_set_direction	= rk805_pmx_gpio_set_direction,
+ };
+ 
+@@ -364,6 +491,7 @@ static int rk805_pinconf_get(struct pinc
+ 
+ 	switch (param) {
+ 	case PIN_CONFIG_OUTPUT:
++	case PIN_CONFIG_INPUT_ENABLE:
+ 		arg = rk805_gpio_get(&pci->gpio_chip, pin);
+ 		break;
+ 	default:
+@@ -393,6 +521,12 @@ static int rk805_pinconf_set(struct pinc
+ 			rk805_gpio_set(&pci->gpio_chip, pin, arg);
+ 			rk805_pmx_gpio_set_direction(pctldev, NULL, pin, false);
+ 			break;
++		case PIN_CONFIG_INPUT_ENABLE:
++			if (pci->rk808->variant != RK805_ID && arg) {
++				rk805_pmx_gpio_set_direction(pctldev, NULL, pin, true);
++				break;
++			}
++			fallthrough;
+ 		default:
+ 			dev_err(pci->dev, "Properties not supported\n");
+ 			return -ENOTSUPP;
+@@ -448,6 +582,18 @@ static int rk805_pinctrl_probe(struct pl
+ 		pci->pin_cfg = rk805_gpio_cfgs;
+ 		pci->gpio_chip.ngpio = ARRAY_SIZE(rk805_gpio_cfgs);
+ 		break;
++	case RK806_ID:
++		pci->pins = rk806_pins_desc;
++		pci->num_pins = ARRAY_SIZE(rk806_pins_desc);
++		pci->functions = rk806_pin_functions;
++		pci->num_functions = ARRAY_SIZE(rk806_pin_functions);
++		pci->groups = rk806_pin_groups;
++		pci->num_pin_groups = ARRAY_SIZE(rk806_pin_groups);
++		pci->pinctrl_desc.pins = rk806_pins_desc;
++		pci->pinctrl_desc.npins = ARRAY_SIZE(rk806_pins_desc);
++		pci->pin_cfg = rk806_gpio_cfgs;
++		pci->gpio_chip.ngpio = ARRAY_SIZE(rk806_gpio_cfgs);
++		break;
+ 	default:
+ 		dev_err(&pdev->dev, "unsupported RK805 ID %lu\n",
+ 			pci->rk808->variant);
+@@ -488,5 +634,6 @@ static struct platform_driver rk805_pinc
+ module_platform_driver(rk805_pinctrl_driver);
+ 
+ MODULE_DESCRIPTION("RK805 pin control and GPIO driver");
++MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
+ MODULE_AUTHOR("Joseph Chen <chenjh@rock-chips.com>");
+ MODULE_LICENSE("GPL v2");
diff --git a/target/linux/rockchip/patches-6.1/242-regulator-expose-regulator_find_closest_bigger.patch b/target/linux/rockchip/patches-6.1/242-regulator-expose-regulator_find_closest_bigger.patch
new file mode 100644
index 00000000000..72e2949a791
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/242-regulator-expose-regulator_find_closest_bigger.patch
@@ -0,0 +1,75 @@
+From b9129bbe59b3d53039c91b9daa908af84822b614 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 9 Sep 2022 18:24:43 +0200
+Subject: [PATCH 242/383] regulator: expose regulator_find_closest_bigger
+
+Expose and document the table lookup logic used by
+regulator_set_ramp_delay_regmap, so that it can be
+reused for devices that cannot be configured via
+regulator_set_ramp_delay_regmap.
+
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/helpers.c      | 22 ++++++++++++++++++----
+ include/linux/regulator/driver.h |  2 ++
+ 2 files changed, 20 insertions(+), 4 deletions(-)
+
+--- a/drivers/regulator/helpers.c
++++ b/drivers/regulator/helpers.c
+@@ -902,8 +902,21 @@ bool regulator_is_equal(struct regulator
+ }
+ EXPORT_SYMBOL_GPL(regulator_is_equal);
+ 
+-static int find_closest_bigger(unsigned int target, const unsigned int *table,
+-			       unsigned int num_sel, unsigned int *sel)
++/**
++ * regulator_find_closest_bigger - helper to find offset in ramp delay table
++ *
++ * @target: targeted ramp_delay
++ * @table: table with supported ramp delays
++ * @num_sel: number of entries in the table
++ * @sel: Pointer to store table offset
++ *
++ * This is the internal helper used by regulator_set_ramp_delay_regmap to
++ * map ramp delay to register value. It should only be used directly if
++ * regulator_set_ramp_delay_regmap cannot handle a specific device setup
++ * (e.g. because the value is split over multiple registers).
++ */
++int regulator_find_closest_bigger(unsigned int target, const unsigned int *table,
++				  unsigned int num_sel, unsigned int *sel)
+ {
+ 	unsigned int s, tmp, max, maxsel = 0;
+ 	bool found = false;
+@@ -933,6 +946,7 @@ static int find_closest_bigger(unsigned
+ 
+ 	return 0;
+ }
++EXPORT_SYMBOL_GPL(regulator_find_closest_bigger);
+ 
+ /**
+  * regulator_set_ramp_delay_regmap - set_ramp_delay() helper
+@@ -951,8 +965,8 @@ int regulator_set_ramp_delay_regmap(stru
+ 	if (WARN_ON(!rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table))
+ 		return -EINVAL;
+ 
+-	ret = find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table,
+-				  rdev->desc->n_ramp_values, &sel);
++	ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table,
++					    rdev->desc->n_ramp_values, &sel);
+ 
+ 	if (ret) {
+ 		dev_warn(rdev_get_dev(rdev),
+--- a/include/linux/regulator/driver.h
++++ b/include/linux/regulator/driver.h
+@@ -758,6 +758,8 @@ int regulator_set_current_limit_regmap(s
+ 				       int min_uA, int max_uA);
+ int regulator_get_current_limit_regmap(struct regulator_dev *rdev);
+ void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
++int regulator_find_closest_bigger(unsigned int target, const unsigned int *table,
++				  unsigned int num_sel, unsigned int *sel);
+ int regulator_set_ramp_delay_regmap(struct regulator_dev *rdev, int ramp_delay);
+ int regulator_sync_voltage_rdev(struct regulator_dev *rdev);
+ 
diff --git a/target/linux/rockchip/patches-6.1/243-regulator-rk808-fix-asynchronous-probing.patch b/target/linux/rockchip/patches-6.1/243-regulator-rk808-fix-asynchronous-probing.patch
new file mode 100644
index 00000000000..17f602951d1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/243-regulator-rk808-fix-asynchronous-probing.patch
@@ -0,0 +1,30 @@
+From 7cb5fe497fa7e15ae9d244da966f7931ad7a7136 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 3 May 2023 18:38:26 +0200
+Subject: [PATCH 243/383] regulator: rk808: fix asynchronous probing
+
+If the probe routine fails with -EPROBE_DEFER after taking over the
+OF node from its parent driver, reprobing triggers pinctrl_bind_pins()
+and that will fail. Fix this by setting of_node_reused, so that the
+device does not try to setup pin muxing.
+
+For me this always happens once the driver is marked to prefer async
+probing and never happens without that flag.
+
+Fixes: 259b93b21a9f ("regulator: Set PROBE_PREFER_ASYNCHRONOUS for drivers that existed in 4.14")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -1336,6 +1336,7 @@ static int rk808_regulator_probe(struct
+ 
+ 	config.dev = &pdev->dev;
+ 	config.dev->of_node = pdev->dev.parent->of_node;
++	config.dev->of_node_reused = true;
+ 	config.driver_data = pdata;
+ 	config.regmap = regmap;
+ 
diff --git a/target/linux/rockchip/patches-6.1/244-regulator-rk808-cleanup-parent-device-usage.patch b/target/linux/rockchip/patches-6.1/244-regulator-rk808-cleanup-parent-device-usage.patch
new file mode 100644
index 00000000000..0c6f55960d2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/244-regulator-rk808-cleanup-parent-device-usage.patch
@@ -0,0 +1,69 @@
+From f35a1161e73b4390bac1d5a86d46ae260743fe1e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 3 May 2023 19:19:42 +0200
+Subject: [PATCH 244/383] regulator: rk808: cleanup parent device usage
+
+By overridering the device's of_node a bit earlier we can
+get the GPIOs and any other DT properties from our own
+device instead of relying on the parent device.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -1245,20 +1245,19 @@ static const struct regulator_desc rk818
+ };
+ 
+ static int rk808_regulator_dt_parse_pdata(struct device *dev,
+-				   struct device *client_dev,
+ 				   struct regmap *map,
+ 				   struct rk808_regulator_data *pdata)
+ {
+ 	struct device_node *np;
+ 	int tmp, ret = 0, i;
+ 
+-	np = of_get_child_by_name(client_dev->of_node, "regulators");
++	np = of_get_child_by_name(dev->of_node, "regulators");
+ 	if (!np)
+ 		return -ENXIO;
+ 
+ 	for (i = 0; i < ARRAY_SIZE(pdata->dvs_gpio); i++) {
+ 		pdata->dvs_gpio[i] =
+-			devm_gpiod_get_index_optional(client_dev, "dvs", i,
++			devm_gpiod_get_index_optional(dev, "dvs", i,
+ 						      GPIOD_OUT_LOW);
+ 		if (IS_ERR(pdata->dvs_gpio[i])) {
+ 			ret = PTR_ERR(pdata->dvs_gpio[i]);
+@@ -1292,6 +1291,9 @@ static int rk808_regulator_probe(struct
+ 	struct regmap *regmap;
+ 	int ret, i, nregulators;
+ 
++	pdev->dev.of_node = pdev->dev.parent->of_node;
++	pdev->dev.of_node_reused = true;
++
+ 	regmap = dev_get_regmap(pdev->dev.parent, NULL);
+ 	if (!regmap)
+ 		return -ENODEV;
+@@ -1300,8 +1302,7 @@ static int rk808_regulator_probe(struct
+ 	if (!pdata)
+ 		return -ENOMEM;
+ 
+-	ret = rk808_regulator_dt_parse_pdata(&pdev->dev, pdev->dev.parent,
+-					     regmap, pdata);
++	ret = rk808_regulator_dt_parse_pdata(&pdev->dev, regmap, pdata);
+ 	if (ret < 0)
+ 		return ret;
+ 
+@@ -1335,8 +1336,6 @@ static int rk808_regulator_probe(struct
+ 	}
+ 
+ 	config.dev = &pdev->dev;
+-	config.dev->of_node = pdev->dev.parent->of_node;
+-	config.dev->of_node_reused = true;
+ 	config.driver_data = pdata;
+ 	config.regmap = regmap;
+ 
diff --git a/target/linux/rockchip/patches-6.1/245-regulator-rk808-revert-to-synchronous-probing.patch b/target/linux/rockchip/patches-6.1/245-regulator-rk808-revert-to-synchronous-probing.patch
new file mode 100644
index 00000000000..4e98ec2ccad
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/245-regulator-rk808-revert-to-synchronous-probing.patch
@@ -0,0 +1,39 @@
+From f28eadc90e6b85e0cce2ac937dcea39f998d0183 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 4 May 2023 16:11:48 +0200
+Subject: [PATCH 245/383] regulator: rk808: revert to synchronous probing
+
+The rk808 driver registers a bunch of regulator devices in a loop.
+If one of the later regulators fails to register (usually because
+its input supply is not yet available) everything will be unrolled
+(i.e. previously registered regulators will be unregistered). With
+asynchronous registration there might already be consumers, though.
+We do not have the necessary infrastructure to properly unregister
+the consumer device, so this scenario should be avoided.
+
+First checking all input supplies or disallowing usage of the regulators
+until all are registered does not work, since there can be
+self-references (e.g. DCDC channels providing the supply of LDOs).
+
+The only sensible solution I found is registering the regulator devices
+asynchronously, so that we do not have to unroll. Since this is a major
+rework let's revert back to synchronous probing for now to fix the issue
+at hand.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -1355,7 +1355,7 @@ static struct platform_driver rk808_regu
+ 	.probe = rk808_regulator_probe,
+ 	.driver = {
+ 		.name = "rk808-regulator",
+-		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
++		.probe_type = PROBE_FORCE_SYNCHRONOUS,
+ 	},
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/246-regulator-rk808-add-rk806-support.patch b/target/linux/rockchip/patches-6.1/246-regulator-rk808-add-rk806-support.patch
new file mode 100644
index 00000000000..3608921b832
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/246-regulator-rk808-add-rk806-support.patch
@@ -0,0 +1,481 @@
+From e2d9ac60fbb2b0c958bc6c2b2c112acfa7003834 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Oct 2022 22:08:09 +0200
+Subject: [PATCH 246/383] regulator: rk808: add rk806 support
+
+Add rk806 support to the existing rk808 regulator
+driver.
+
+This has been implemented using shengfei Xu's rk806
+specific driver from the vendor tree as reference.
+
+Co-developed-by: shengfei Xu <xsf@rock-chips.com>
+Signed-off-by: shengfei Xu <xsf@rock-chips.com>
+Reviewed-by: Matti Vaittinen <mazziesaccount@gmail.com>
+Tested-by: Diederik de Haas <didi.debian@cknow.org> # Rock64, Quartz64 Model A + B
+Tested-by: Vincent Legoll <vincent.legoll@gmail.com> # Pine64 QuartzPro64
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/regulator/rk808-regulator.c | 385 ++++++++++++++++++++++++++++
+ 1 file changed, 385 insertions(+)
+
+--- a/drivers/regulator/rk808-regulator.c
++++ b/drivers/regulator/rk808-regulator.c
+@@ -3,9 +3,11 @@
+  * Regulator driver for Rockchip RK805/RK808/RK818
+  *
+  * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
+  *
+  * Author: Chris Zhong <zyw@rock-chips.com>
+  * Author: Zhang Qing <zhangqing@rock-chips.com>
++ * Author: Xu Shengfei <xsf@rock-chips.com>
+  *
+  * Copyright (C) 2016 PHYTEC Messtechnik GmbH
+  *
+@@ -39,6 +41,13 @@
+ #define RK818_LDO3_ON_VSEL_MASK		0xf
+ #define RK818_BOOST_ON_VSEL_MASK	0xe0
+ 
++#define RK806_DCDC_SLP_REG_OFFSET	0x0A
++#define RK806_NLDO_SLP_REG_OFFSET	0x05
++#define RK806_PLDO_SLP_REG_OFFSET	0x06
++
++#define RK806_BUCK_SEL_CNT		0xff
++#define RK806_LDO_SEL_CNT		0xff
++
+ /* Ramp rate definitions for buck1 / buck2 only */
+ #define RK808_RAMP_RATE_OFFSET		3
+ #define RK808_RAMP_RATE_MASK		(3 << RK808_RAMP_RATE_OFFSET)
+@@ -117,6 +126,34 @@
+ 	RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg,	\
+ 	_vmask, _ereg, _emask, 0, 0, _etime, &rk805_reg_ops)
+ 
++#define RK806_REGULATOR(_name, _supply_name, _id, _ops,\
++			_n_voltages, _vr, _er, _lr, ctrl_bit,\
++			_rr, _rm, _rt)\
++[_id] = {\
++		.name = _name,\
++		.supply_name = _supply_name,\
++		.of_match = of_match_ptr(_name),\
++		.regulators_node = of_match_ptr("regulators"),\
++		.id = _id,\
++		.ops = &_ops,\
++		.type = REGULATOR_VOLTAGE,\
++		.n_voltages = _n_voltages,\
++		.linear_ranges = _lr,\
++		.n_linear_ranges = ARRAY_SIZE(_lr),\
++		.vsel_reg = _vr,\
++		.vsel_mask = 0xff,\
++		.enable_reg = _er,\
++		.enable_mask = ENABLE_MASK(ctrl_bit),\
++		.enable_val = ENABLE_MASK(ctrl_bit),\
++		.disable_val = DISABLE_VAL(ctrl_bit),\
++		.of_map_mode = rk8xx_regulator_of_map_mode,\
++		.ramp_reg = _rr,\
++		.ramp_mask = _rm,\
++		.ramp_delay_table = _rt, \
++		.n_ramp_values = ARRAY_SIZE(_rt), \
++		.owner = THIS_MODULE,\
++	}
++
+ #define RK8XX_DESC(_id, _match, _supply, _min, _max, _step, _vreg,	\
+ 	_vmask, _ereg, _emask, _etime)					\
+ 	RK8XX_DESC_COM(_id, _match, _supply, _min, _max, _step, _vreg,	\
+@@ -153,6 +190,17 @@
+ 	RKXX_DESC_SWITCH_COM(_id, _match, _supply, _ereg, _emask,	\
+ 	0, 0, &rk808_switch_ops)
+ 
++struct rk8xx_register_bit {
++	u8 reg;
++	u8 bit;
++};
++
++#define RK8XX_REG_BIT(_reg, _bit)					\
++	{								\
++		.reg = _reg,						\
++		.bit = BIT(_bit),						\
++	}
++
+ struct rk808_regulator_data {
+ 	struct gpio_desc *dvs_gpio[2];
+ };
+@@ -216,6 +264,133 @@ static const unsigned int rk817_buck1_4_
+ 	3000, 6300, 12500, 25000
+ };
+ 
++static int rk806_set_mode_dcdc(struct regulator_dev *rdev, unsigned int mode)
++{
++	int rid = rdev_get_id(rdev);
++	int ctr_bit, reg;
++
++	reg = RK806_POWER_FPWM_EN0 + rid / 8;
++	ctr_bit = rid % 8;
++
++	switch (mode) {
++	case REGULATOR_MODE_FAST:
++		return regmap_update_bits(rdev->regmap, reg,
++					  PWM_MODE_MSK << ctr_bit,
++					  FPWM_MODE << ctr_bit);
++	case REGULATOR_MODE_NORMAL:
++		return regmap_update_bits(rdev->regmap, reg,
++					  PWM_MODE_MSK << ctr_bit,
++					  AUTO_PWM_MODE << ctr_bit);
++	default:
++		dev_err(rdev_get_dev(rdev), "mode unsupported: %u\n", mode);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static unsigned int rk806_get_mode_dcdc(struct regulator_dev *rdev)
++{
++	int rid = rdev_get_id(rdev);
++	int ctr_bit, reg;
++	unsigned int val;
++	int err;
++
++	reg = RK806_POWER_FPWM_EN0 + rid / 8;
++	ctr_bit = rid % 8;
++
++	err = regmap_read(rdev->regmap, reg, &val);
++	if (err)
++		return err;
++
++	if ((val >> ctr_bit) & FPWM_MODE)
++		return REGULATOR_MODE_FAST;
++	else
++		return REGULATOR_MODE_NORMAL;
++}
++
++static const struct rk8xx_register_bit rk806_dcdc_rate2[] = {
++	RK8XX_REG_BIT(0xEB, 0),
++	RK8XX_REG_BIT(0xEB, 1),
++	RK8XX_REG_BIT(0xEB, 2),
++	RK8XX_REG_BIT(0xEB, 3),
++	RK8XX_REG_BIT(0xEB, 4),
++	RK8XX_REG_BIT(0xEB, 5),
++	RK8XX_REG_BIT(0xEB, 6),
++	RK8XX_REG_BIT(0xEB, 7),
++	RK8XX_REG_BIT(0xEA, 0),
++	RK8XX_REG_BIT(0xEA, 1),
++};
++
++static const unsigned int rk806_ramp_delay_table_dcdc[] = {
++	50000, 25000, 12500, 6250, 3125, 1560, 961, 390
++};
++
++static int rk806_set_ramp_delay_dcdc(struct regulator_dev *rdev, int ramp_delay)
++{
++	int rid = rdev_get_id(rdev);
++	int regval, ramp_value, ret;
++
++	ret = regulator_find_closest_bigger(ramp_delay, rdev->desc->ramp_delay_table,
++					    rdev->desc->n_ramp_values, &ramp_value);
++	if (ret) {
++		dev_warn(rdev_get_dev(rdev),
++			 "Can't set ramp-delay %u, setting %u\n", ramp_delay,
++			 rdev->desc->ramp_delay_table[ramp_value]);
++	}
++
++	regval = ramp_value << (ffs(rdev->desc->ramp_mask) - 1);
++
++	ret = regmap_update_bits(rdev->regmap, rdev->desc->ramp_reg,
++				 rdev->desc->ramp_mask, regval);
++	if (ret)
++		return ret;
++
++	/*
++	 * The above is effectively a copy of regulator_set_ramp_delay_regmap(),
++	 * but that only stores the lower 2 bits for rk806 DCDC ramp. The MSB must
++	 * be stored in a separate register, so this open codes the implementation
++	 * to have access to the ramp_value.
++	 */
++
++	regval = (ramp_value >> 2) & 0x1 ? rk806_dcdc_rate2[rid].bit : 0;
++	return regmap_update_bits(rdev->regmap, rk806_dcdc_rate2[rid].reg,
++				  rk806_dcdc_rate2[rid].bit,
++				  regval);
++}
++
++static const unsigned int rk806_ramp_delay_table_ldo[] = {
++	100000, 50000, 25000, 12500, 6280, 3120, 1900, 780
++};
++
++static int rk806_set_suspend_voltage_range(struct regulator_dev *rdev, int reg_offset, int uv)
++{
++	int sel = regulator_map_voltage_linear_range(rdev, uv, uv);
++	unsigned int reg;
++
++	if (sel < 0)
++		return -EINVAL;
++
++	reg = rdev->desc->vsel_reg + reg_offset;
++
++	return regmap_update_bits(rdev->regmap, reg, rdev->desc->vsel_mask, sel);
++}
++
++static int rk806_set_suspend_voltage_range_dcdc(struct regulator_dev *rdev, int uv)
++{
++	return rk806_set_suspend_voltage_range(rdev, RK806_DCDC_SLP_REG_OFFSET, uv);
++}
++
++static int rk806_set_suspend_voltage_range_nldo(struct regulator_dev *rdev, int uv)
++{
++	return rk806_set_suspend_voltage_range(rdev, RK806_NLDO_SLP_REG_OFFSET, uv);
++}
++
++static int rk806_set_suspend_voltage_range_pldo(struct regulator_dev *rdev, int uv)
++{
++	return rk806_set_suspend_voltage_range(rdev, RK806_PLDO_SLP_REG_OFFSET, uv);
++}
++
+ static int rk808_buck1_2_get_voltage_sel_regmap(struct regulator_dev *rdev)
+ {
+ 	struct rk808_regulator_data *pdata = rdev_get_drvdata(rdev);
+@@ -393,6 +568,47 @@ static int rk805_set_suspend_disable(str
+ 				  0);
+ }
+ 
++static const struct rk8xx_register_bit rk806_suspend_bits[] = {
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 0),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 1),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 2),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 3),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 4),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 5),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 6),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN0, 7),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 6),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 7),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 0),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 1),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 2),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 3),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN1, 4),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 1),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 2),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 3),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 4),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 5),
++	RK8XX_REG_BIT(RK806_POWER_SLP_EN2, 0),
++};
++
++static int rk806_set_suspend_enable(struct regulator_dev *rdev)
++{
++	int rid = rdev_get_id(rdev);
++
++	return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg,
++				  rk806_suspend_bits[rid].bit,
++				  rk806_suspend_bits[rid].bit);
++}
++
++static int rk806_set_suspend_disable(struct regulator_dev *rdev)
++{
++	int rid = rdev_get_id(rdev);
++
++	return regmap_update_bits(rdev->regmap, rk806_suspend_bits[rid].reg,
++				  rk806_suspend_bits[rid].bit, 0);
++}
++
+ static int rk808_set_suspend_enable(struct regulator_dev *rdev)
+ {
+ 	unsigned int reg;
+@@ -561,6 +777,64 @@ static const struct regulator_ops rk805_
+ 	.set_suspend_disable    = rk805_set_suspend_disable,
+ };
+ 
++static const struct regulator_ops rk806_ops_dcdc = {
++	.list_voltage		= regulator_list_voltage_linear_range,
++	.map_voltage		= regulator_map_voltage_linear_range,
++	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
++	.set_voltage_sel        = regulator_set_voltage_sel_regmap,
++	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
++	.set_mode		= rk806_set_mode_dcdc,
++	.get_mode		= rk806_get_mode_dcdc,
++
++	.enable			= regulator_enable_regmap,
++	.disable		= regulator_disable_regmap,
++	.is_enabled		= rk8xx_is_enabled_wmsk_regmap,
++
++	.set_suspend_mode	= rk806_set_mode_dcdc,
++	.set_ramp_delay		= rk806_set_ramp_delay_dcdc,
++
++	.set_suspend_voltage	= rk806_set_suspend_voltage_range_dcdc,
++	.set_suspend_enable	= rk806_set_suspend_enable,
++	.set_suspend_disable	= rk806_set_suspend_disable,
++};
++
++static const struct regulator_ops rk806_ops_nldo = {
++	.list_voltage		= regulator_list_voltage_linear_range,
++	.map_voltage		= regulator_map_voltage_linear_range,
++	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
++	.set_voltage_sel        = regulator_set_voltage_sel_regmap,
++	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
++
++	.enable			= regulator_enable_regmap,
++	.disable		= regulator_disable_regmap,
++	.is_enabled		= regulator_is_enabled_regmap,
++
++	.set_ramp_delay		= regulator_set_ramp_delay_regmap,
++
++	.set_suspend_voltage	= rk806_set_suspend_voltage_range_nldo,
++	.set_suspend_enable	= rk806_set_suspend_enable,
++	.set_suspend_disable	= rk806_set_suspend_disable,
++};
++
++static const struct regulator_ops rk806_ops_pldo = {
++	.list_voltage		= regulator_list_voltage_linear_range,
++	.map_voltage		= regulator_map_voltage_linear_range,
++
++	.get_voltage_sel	= regulator_get_voltage_sel_regmap,
++	.set_voltage_sel        = regulator_set_voltage_sel_regmap,
++	.set_voltage_time_sel	= regulator_set_voltage_time_sel,
++
++	.enable			= regulator_enable_regmap,
++	.disable		= regulator_disable_regmap,
++	.is_enabled		= regulator_is_enabled_regmap,
++
++	.set_ramp_delay		= regulator_set_ramp_delay_regmap,
++
++	.set_suspend_voltage	= rk806_set_suspend_voltage_range_pldo,
++	.set_suspend_enable	= rk806_set_suspend_enable,
++	.set_suspend_disable	= rk806_set_suspend_disable,
++};
++
+ static const struct regulator_ops rk808_buck1_2_ops = {
+ 	.list_voltage		= regulator_list_voltage_linear,
+ 	.map_voltage		= regulator_map_voltage_linear,
+@@ -743,6 +1017,112 @@ static const struct regulator_desc rk805
+ 		BIT(2), 400),
+ };
+ 
++static const struct linear_range rk806_buck_voltage_ranges[] = {
++	REGULATOR_LINEAR_RANGE(500000, 0, 160, 6250), /* 500mV ~ 1500mV */
++	REGULATOR_LINEAR_RANGE(1500000, 161, 237, 25000), /* 1500mV ~ 3400mV */
++	REGULATOR_LINEAR_RANGE(3400000, 238, 255, 0),
++};
++
++static const struct linear_range rk806_ldo_voltage_ranges[] = {
++	REGULATOR_LINEAR_RANGE(500000, 0, 232, 12500), /* 500mV ~ 3400mV */
++	REGULATOR_LINEAR_RANGE(3400000, 233, 255, 0), /* 500mV ~ 3400mV */
++};
++
++static const struct regulator_desc rk806_reg[] = {
++	RK806_REGULATOR("dcdc-reg1", "vcc1", RK806_ID_DCDC1, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK1_ON_VSEL,
++			RK806_POWER_EN0, rk806_buck_voltage_ranges, 0,
++			RK806_BUCK1_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg2", "vcc2", RK806_ID_DCDC2, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK2_ON_VSEL,
++			RK806_POWER_EN0, rk806_buck_voltage_ranges, 1,
++			RK806_BUCK2_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg3", "vcc3", RK806_ID_DCDC3, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK3_ON_VSEL,
++			RK806_POWER_EN0, rk806_buck_voltage_ranges, 2,
++			RK806_BUCK3_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg4", "vcc4", RK806_ID_DCDC4, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK4_ON_VSEL,
++			RK806_POWER_EN0, rk806_buck_voltage_ranges, 3,
++			RK806_BUCK4_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++
++	RK806_REGULATOR("dcdc-reg5", "vcc5", RK806_ID_DCDC5, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK5_ON_VSEL,
++			RK806_POWER_EN1, rk806_buck_voltage_ranges, 0,
++			RK806_BUCK5_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg6", "vcc6", RK806_ID_DCDC6, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK6_ON_VSEL,
++			RK806_POWER_EN1, rk806_buck_voltage_ranges, 1,
++			RK806_BUCK6_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg7", "vcc7", RK806_ID_DCDC7, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK7_ON_VSEL,
++			RK806_POWER_EN1, rk806_buck_voltage_ranges, 2,
++			RK806_BUCK7_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg8", "vcc8", RK806_ID_DCDC8, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK8_ON_VSEL,
++			RK806_POWER_EN1, rk806_buck_voltage_ranges, 3,
++			RK806_BUCK8_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++
++	RK806_REGULATOR("dcdc-reg9", "vcc9", RK806_ID_DCDC9, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK9_ON_VSEL,
++			RK806_POWER_EN2, rk806_buck_voltage_ranges, 0,
++			RK806_BUCK9_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++	RK806_REGULATOR("dcdc-reg10", "vcc10", RK806_ID_DCDC10, rk806_ops_dcdc,
++			RK806_BUCK_SEL_CNT, RK806_BUCK10_ON_VSEL,
++			RK806_POWER_EN2, rk806_buck_voltage_ranges, 1,
++			RK806_BUCK10_CONFIG, 0xc0, rk806_ramp_delay_table_dcdc),
++
++	RK806_REGULATOR("nldo-reg1", "vcc13", RK806_ID_NLDO1, rk806_ops_nldo,
++			RK806_LDO_SEL_CNT, RK806_NLDO1_ON_VSEL,
++			RK806_POWER_EN3, rk806_ldo_voltage_ranges, 0,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++	RK806_REGULATOR("nldo-reg2", "vcc13", RK806_ID_NLDO2, rk806_ops_nldo,
++			RK806_LDO_SEL_CNT, RK806_NLDO2_ON_VSEL,
++			RK806_POWER_EN3, rk806_ldo_voltage_ranges, 1,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++	RK806_REGULATOR("nldo-reg3", "vcc13", RK806_ID_NLDO3, rk806_ops_nldo,
++			RK806_LDO_SEL_CNT, RK806_NLDO3_ON_VSEL,
++			RK806_POWER_EN3, rk806_ldo_voltage_ranges, 2,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++	RK806_REGULATOR("nldo-reg4", "vcc14", RK806_ID_NLDO4, rk806_ops_nldo,
++			RK806_LDO_SEL_CNT, RK806_NLDO4_ON_VSEL,
++			RK806_POWER_EN3, rk806_ldo_voltage_ranges, 3,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++
++	RK806_REGULATOR("nldo-reg5", "vcc14", RK806_ID_NLDO5, rk806_ops_nldo,
++			RK806_LDO_SEL_CNT, RK806_NLDO5_ON_VSEL,
++			RK806_POWER_EN5, rk806_ldo_voltage_ranges, 2,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++
++	RK806_REGULATOR("pldo-reg1", "vcc11", RK806_ID_PLDO1, rk806_ops_pldo,
++			RK806_LDO_SEL_CNT, RK806_PLDO1_ON_VSEL,
++			RK806_POWER_EN4, rk806_ldo_voltage_ranges, 1,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++	RK806_REGULATOR("pldo-reg2", "vcc11", RK806_ID_PLDO2, rk806_ops_pldo,
++			RK806_LDO_SEL_CNT, RK806_PLDO2_ON_VSEL,
++			RK806_POWER_EN4, rk806_ldo_voltage_ranges, 2,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++	RK806_REGULATOR("pldo-reg3", "vcc11", RK806_ID_PLDO3, rk806_ops_pldo,
++			RK806_LDO_SEL_CNT, RK806_PLDO3_ON_VSEL,
++			RK806_POWER_EN4, rk806_ldo_voltage_ranges, 3,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++
++	RK806_REGULATOR("pldo-reg4", "vcc12", RK806_ID_PLDO4, rk806_ops_pldo,
++			RK806_LDO_SEL_CNT, RK806_PLDO4_ON_VSEL,
++			RK806_POWER_EN5, rk806_ldo_voltage_ranges, 0,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++	RK806_REGULATOR("pldo-reg5", "vcc12", RK806_ID_PLDO5, rk806_ops_pldo,
++			RK806_LDO_SEL_CNT, RK806_PLDO5_ON_VSEL,
++			RK806_POWER_EN5, rk806_ldo_voltage_ranges, 1,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++
++	RK806_REGULATOR("pldo-reg6", "vcca", RK806_ID_PLDO6, rk806_ops_pldo,
++			RK806_LDO_SEL_CNT, RK806_PLDO6_ON_VSEL,
++			RK806_POWER_EN4, rk806_ldo_voltage_ranges, 0,
++			0xEA, 0x38, rk806_ramp_delay_table_ldo),
++};
++
++
+ static const struct regulator_desc rk808_reg[] = {
+ 	{
+ 		.name = "DCDC_REG1",
+@@ -1313,6 +1693,10 @@ static int rk808_regulator_probe(struct
+ 		regulators = rk805_reg;
+ 		nregulators = RK805_NUM_REGULATORS;
+ 		break;
++	case RK806_ID:
++		regulators = rk806_reg;
++		nregulators = ARRAY_SIZE(rk806_reg);
++		break;
+ 	case RK808_ID:
+ 		regulators = rk808_reg;
+ 		nregulators = RK808_NUM_REGULATORS;
+@@ -1366,5 +1750,6 @@ MODULE_AUTHOR("Tony xie <tony.xie@rock-c
+ MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
+ MODULE_AUTHOR("Zhang Qing <zhangqing@rock-chips.com>");
+ MODULE_AUTHOR("Wadim Egorov <w.egorov@phytec.de>");
++MODULE_AUTHOR("Xu Shengfei <xsf@rock-chips.com>");
+ MODULE_LICENSE("GPL");
+ MODULE_ALIAS("platform:rk808-regulator");
diff --git a/target/linux/rockchip/patches-6.1/247-arm64-defconfig-update-RK8XX-MFD-config.patch b/target/linux/rockchip/patches-6.1/247-arm64-defconfig-update-RK8XX-MFD-config.patch
new file mode 100644
index 00000000000..5f2a7639b39
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/247-arm64-defconfig-update-RK8XX-MFD-config.patch
@@ -0,0 +1,26 @@
+From ec0248b3d14b51734d055bdd0b5f10236595d830 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 7 Feb 2023 18:02:45 +0100
+Subject: [PATCH 247/383] arm64: defconfig: update RK8XX MFD config
+
+Update the defconfig for the new RK8XX MFD config name,
+which got split to add SPI support.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/configs/defconfig | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -650,7 +650,8 @@ CONFIG_MFD_MAX77620=y
+ CONFIG_MFD_MT6360=y
+ CONFIG_MFD_MT6397=y
+ CONFIG_MFD_SPMI_PMIC=y
+-CONFIG_MFD_RK808=y
++CONFIG_MFD_RK8XX_I2C=y
++CONFIG_MFD_RK8XX_SPI=y
+ CONFIG_MFD_SEC_CORE=y
+ CONFIG_MFD_SL28CPLD=y
+ CONFIG_MFD_ROHM_BD718XX=y
diff --git a/target/linux/rockchip/patches-6.1/248-arm64-dts-rockchip-rk3588-evb1-add-pmic.patch b/target/linux/rockchip/patches-6.1/248-arm64-dts-rockchip-rk3588-evb1-add-pmic.patch
new file mode 100644
index 00000000000..2dee0dae435
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/248-arm64-dts-rockchip-rk3588-evb1-add-pmic.patch
@@ -0,0 +1,764 @@
+From 16062a2547d5c82671b59290b824750b311e1b32 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 12 Jul 2022 15:17:33 +0200
+Subject: [PATCH 248/383] arm64: dts: rockchip: rk3588-evb1: add pmic
+
+This adds PMIC support for the RK3588 EVB.
+
+Signed-off-by: shengfei Xu <xsf@rock-chips.com>
+Co-developed-by: shengfei Xu <xsf@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 740 ++++++++++++++++++
+ 1 file changed, 740 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -123,6 +123,746 @@
+ 	status = "okay";
+ };
+ 
++&spi2 {
++	status = "okay";
++	assigned-clocks = <&cru CLK_SPI2>;
++	assigned-clock-rates = <200000000>;
++	num-cs = <2>;
++
++	pmic@0 {
++		compatible = "rockchip,rk806";
++		spi-max-frequency = <1000000>;
++		reg = <0x0>;
++
++		interrupt-parent = <&gpio0>;
++		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++		pinctrl-names = "default", "pmic-power-off";
++		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++		pinctrl-1 = <&rk806_dvs1_pwrdn>;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc5v0_sys>;
++		vcc6-supply = <&vcc5v0_sys>;
++		vcc7-supply = <&vcc5v0_sys>;
++		vcc8-supply = <&vcc5v0_sys>;
++		vcc9-supply = <&vcc5v0_sys>;
++		vcc10-supply = <&vcc5v0_sys>;
++		vcc11-supply = <&vcc_2v0_pldo_s3>;
++		vcc12-supply = <&vcc5v0_sys>;
++		vcc13-supply = <&vcc5v0_sys>;
++		vcc14-supply = <&vcc_1v1_nldo_s3>;
++		vcca-supply = <&vcc5v0_sys>;
++
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		rk806_dvs1_null: dvs1-null-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs1_slp: dvs1-slp-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs1_rst: dvs1-rst-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs2_null: dvs2-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs2_slp: dvs2-slp-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs2_rst: dvs2-rst-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs2_dvs: dvs2-dvs-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun4";
++		};
++
++		rk806_dvs2_gpio: dvs2-gpio-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun5";
++		};
++
++		rk806_dvs3_null: dvs3-null-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs3_slp: dvs3-slp-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs3_rst: dvs3-rst-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs3_dvs: dvs3-dvs-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun4";
++		};
++
++		rk806_dvs3_gpio: dvs3-gpio-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun5";
++		};
++
++		regulators {
++			vdd_gpu_s0: dcdc-reg1 {
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_gpu_s0";
++				regulator-enable-ramp-delay = <400>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_npu_s0: dcdc-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_npu_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_log_s0: dcdc-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <750000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_log_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <750000>;
++				};
++			};
++
++			vdd_vdenc_s0: dcdc-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_vdenc_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++
++			};
++
++			vdd_gpu_mem_s0: dcdc-reg5 {
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-enable-ramp-delay = <400>;
++				regulator-name = "vdd_gpu_mem_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++
++			};
++
++			vdd_npu_mem_s0: dcdc-reg6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_npu_mem_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++
++			};
++
++			vcc_2v0_pldo_s3: dcdc-reg7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2000000>;
++				regulator-max-microvolt = <2000000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_2v0_pldo_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <2000000>;
++				};
++			};
++
++			vdd_vdenc_mem_s0: dcdc-reg8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_vdenc_mem_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd2_ddr_s3: dcdc-reg9 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vdd2_ddr_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_1v1_nldo_s3: dcdc-reg10 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1100000>;
++				regulator-max-microvolt = <1100000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_1v1_nldo_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1100000>;
++				};
++			};
++
++			avcc_1v8_s0: pldo-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "avcc_1v8_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd1_1v8_ddr_s3: pldo-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd1_1v8_ddr_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			avcc_1v8_codec_s0: pldo-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "avcc_1v8_codec_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3_s3: pldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_3v3_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vccio_sd_s0: pldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vccio_sd_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_1v8_s3: pldo-reg6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vccio_1v8_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_0v75_s3: nldo-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_0v75_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <750000>;
++				};
++			};
++
++			vdd2l_0v9_ddr_s3: nldo-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <900000>;
++				regulator-max-microvolt = <900000>;
++				regulator-name = "vdd2l_0v9_ddr_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <900000>;
++				};
++			};
++
++			vdd_0v75_hdmi_edp_s0: nldo-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++				regulator-name = "vdd_0v75_hdmi_edp_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			avdd_0v75_s0: nldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++				regulator-name = "avdd_0v75_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_0v85_s0: nldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <850000>;
++				regulator-max-microvolt = <850000>;
++				regulator-name = "vdd_0v85_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++
++	pmic@1 {
++		compatible = "rockchip,rk806";
++		spi-max-frequency = <1000000>;
++		reg = <0x01>;
++
++		interrupt-parent = <&gpio0>;
++		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++		pinctrl-names = "default", "pmic-sleep";
++		pinctrl-0 = <&rk806_slave_dvs1_null>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
++		pinctrl-1 = <&rk806_slave_dvs1_slp>, <&rk806_slave_dvs2_null>, <&rk806_slave_dvs3_null>;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc5v0_sys>;
++		vcc6-supply = <&vcc5v0_sys>;
++		vcc7-supply = <&vcc5v0_sys>;
++		vcc8-supply = <&vcc5v0_sys>;
++		vcc9-supply = <&vcc5v0_sys>;
++		vcc10-supply = <&vcc5v0_sys>;
++		vcc11-supply = <&vcc_2v0_pldo_s3>;
++		vcc12-supply = <&vcc5v0_sys>;
++		vcc13-supply = <&vcc_1v1_nldo_s3>;
++		vcc14-supply = <&vcc_2v0_pldo_s3>;
++		vcca-supply = <&vcc5v0_sys>;
++
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		rk806_slave_dvs1_null: dvs1-null-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun0";
++		};
++
++		rk806_slave_dvs1_slp: dvs1-slp-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun1";
++		};
++
++		rk806_slave_dvs1_pwrdn: dvs1-pwrdn-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun2";
++		};
++
++		rk806_slave_dvs1_rst: dvs1-rst-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun3";
++		};
++
++		rk806_slave_dvs2_null: dvs2-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_slave_dvs2_slp: dvs2-slp-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun1";
++		};
++
++		rk806_slave_dvs2_pwrdn: dvs2-pwrdn-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun2";
++		};
++
++		rk806_slave_dvs2_rst: dvs2-rst-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun3";
++		};
++
++		rk806_slave_dvs2_dvs: dvs2-dvs-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun4";
++		};
++
++		rk806_slave_dvs2_gpio: dvs2-gpio-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun5";
++		};
++
++		rk806_slave_dvs3_null: dvs3-null-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun0";
++		};
++
++		rk806_slave_dvs3_slp: dvs3-slp-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun1";
++		};
++
++		rk806_slave_dvs3_pwrdn: dvs3-pwrdn-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun2";
++		};
++
++		rk806_slave_dvs3_rst: dvs3-rst-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun3";
++		};
++
++		rk806_slave_dvs3_dvs: dvs3-dvs-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun4";
++		};
++
++		rk806_slave_dvs3_gpio: dvs3-gpio-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun5";
++		};
++
++		regulators {
++			vdd_cpu_big1_s0: dcdc-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <1050000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_big1_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_big0_s0: dcdc-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <1050000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_big0_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_lit_s0: dcdc-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_lit_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3_s0: dcdc-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_3v3_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_big1_mem_s0: dcdc-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <1050000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_big1_mem_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++
++			vdd_cpu_big0_mem_s0: dcdc-reg6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <1050000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_big0_mem_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8_s0: dcdc-reg7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_1v8_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_lit_mem_s0: dcdc-reg8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_lit_mem_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vddq_ddr_s0: dcdc-reg9 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-name = "vddq_ddr_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_ddr_s0: dcdc-reg10 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <900000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_ddr_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8_cam_s0: pldo-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_1v8_cam_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			avdd1v8_ddr_pll_s0: pldo-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "avdd1v8_ddr_pll_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_1v8_pll_s0: pldo-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_1v8_pll_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3_sd_s0: pldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_3v3_sd_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_2v8_cam_s0: pldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2800000>;
++				regulator-max-microvolt = <2800000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_2v8_cam_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			pldo6_s3: pldo-reg6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++				regulator-name = "pldo6_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_0v75_pll_s0: nldo-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_0v75_pll_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_ddr_pll_s0: nldo-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <850000>;
++				regulator-max-microvolt = <850000>;
++				regulator-name = "vdd_ddr_pll_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			avdd_0v85_s0: nldo-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <850000>;
++				regulator-max-microvolt = <850000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "avdd_0v85_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			avdd_1v2_cam_s0: nldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "avdd_1v2_cam_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			avdd_1v2_s0: nldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "avdd_1v2_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
+ &uart2 {
+ 	pinctrl-0 = <&uart2m0_xfer>;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/249-cpufreq-rockchip-Introduce-driver-for-rk3588.patch b/target/linux/rockchip/patches-6.1/249-cpufreq-rockchip-Introduce-driver-for-rk3588.patch
new file mode 100644
index 00000000000..9372c931bcc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/249-cpufreq-rockchip-Introduce-driver-for-rk3588.patch
@@ -0,0 +1,708 @@
+From 66ae7200b69720abd1ce6c9db7c4d50357fc5761 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 18 Aug 2022 14:21:30 +0200
+Subject: [PATCH 249/383] cpufreq: rockchip: Introduce driver for rk3588
+
+This is a heavily modified port from the downstream driver.
+Downstream used it for multiple rockchip generations, while
+upstream just used the generic cpufreq-dt driver so far. For
+rk3588 this is no longer good enough, since two regulators
+need to be controlled.
+
+Also during shutdown the correct frequency needs to be configured
+for the big CPU cores to avoid a system hang when firmware tries
+to bring them up at reboot time.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/cpufreq/Kconfig.arm          |  10 +
+ drivers/cpufreq/Makefile             |   1 +
+ drivers/cpufreq/cpufreq-dt-platdev.c |   2 +
+ drivers/cpufreq/rockchip-cpufreq.c   | 640 +++++++++++++++++++++++++++
+ 4 files changed, 653 insertions(+)
+ create mode 100644 drivers/cpufreq/rockchip-cpufreq.c
+
+--- a/drivers/cpufreq/Kconfig.arm
++++ b/drivers/cpufreq/Kconfig.arm
+@@ -180,6 +180,16 @@ config ARM_RASPBERRYPI_CPUFREQ
+ 
+ 	  If in doubt, say N.
+ 
++config ARM_ROCKCHIP_CPUFREQ
++	tristate "Rockchip CPUfreq driver"
++	depends on ARCH_ROCKCHIP && CPUFREQ_DT
++	select PM_OPP
++	help
++	  This adds the CPUFreq driver support for Rockchip SoCs,
++	  based on cpufreq-dt.
++
++	  If in doubt, say N.
++
+ config ARM_S3C_CPUFREQ
+ 	bool
+ 	help
+--- a/drivers/cpufreq/Makefile
++++ b/drivers/cpufreq/Makefile
+@@ -70,6 +70,7 @@ obj-$(CONFIG_PXA3xx)			+= pxa3xx-cpufreq
+ obj-$(CONFIG_ARM_QCOM_CPUFREQ_HW)	+= qcom-cpufreq-hw.o
+ obj-$(CONFIG_ARM_QCOM_CPUFREQ_NVMEM)	+= qcom-cpufreq-nvmem.o
+ obj-$(CONFIG_ARM_RASPBERRYPI_CPUFREQ) 	+= raspberrypi-cpufreq.o
++obj-$(CONFIG_ARM_ROCKCHIP_CPUFREQ)	+= rockchip-cpufreq.o
+ obj-$(CONFIG_ARM_S3C2410_CPUFREQ)	+= s3c2410-cpufreq.o
+ obj-$(CONFIG_ARM_S3C2412_CPUFREQ)	+= s3c2412-cpufreq.o
+ obj-$(CONFIG_ARM_S3C2416_CPUFREQ)	+= s3c2416-cpufreq.o
+--- a/drivers/cpufreq/cpufreq-dt-platdev.c
++++ b/drivers/cpufreq/cpufreq-dt-platdev.c
+@@ -154,6 +154,8 @@ static const struct of_device_id blockli
+ 	{ .compatible = "qcom,sm8250", },
+ 	{ .compatible = "qcom,sm8350", },
+ 
++	{ .compatible = "rockchip,rk3588", },
++
+ 	{ .compatible = "st,stih407", },
+ 	{ .compatible = "st,stih410", },
+ 	{ .compatible = "st,stih418", },
+--- /dev/null
++++ b/drivers/cpufreq/rockchip-cpufreq.c
+@@ -0,0 +1,640 @@
++// SPDX-License-Identifier: GPL-2.0-only
++/*
++ * Rockchip CPUFreq Driver. This is similar to the generic DT
++ * cpufreq driver, but handles the following platform specific
++ * quirks:
++ *
++ *  * support for two regulators - one for the CPU core and one
++ *    for the memory interface
++ *  * reboot handler to setup the reboot frequency
++ *  * handling of read margin registers
++ *
++ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co., Ltd
++ * Copyright (C) 2023 Collabora Ltd.
++ */
++
++#include <linux/cpu.h>
++#include <linux/cpufreq.h>
++#include <linux/err.h>
++#include <linux/init.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/platform_device.h>
++#include <linux/pm_opp.h>
++#include <linux/slab.h>
++#include <linux/reboot.h>
++#include <linux/regmap.h>
++#include <linux/regulator/consumer.h>
++
++#include "cpufreq-dt.h"
++
++#define RK3588_MEMCFG_HSSPRF_LOW	0x20
++#define RK3588_MEMCFG_HSDPRF_LOW	0x28
++#define RK3588_MEMCFG_HSDPRF_HIGH	0x2c
++#define RK3588_CPU_CTRL			0x30
++
++#define VOLT_RM_TABLE_END		~1
++
++static struct platform_device *cpufreq_pdev;
++static LIST_HEAD(priv_list);
++
++struct volt_rm_table {
++	uint32_t volt;
++	uint32_t rm;
++};
++
++struct rockchip_opp_info {
++	const struct rockchip_opp_data *data;
++	struct volt_rm_table *volt_rm_tbl;
++	struct regmap *grf;
++	u32 current_rm;
++	u32 reboot_freq;
++};
++
++struct private_data {
++	struct list_head node;
++
++	cpumask_var_t cpus;
++	struct device *cpu_dev;
++	struct cpufreq_frequency_table *freq_table;
++};
++
++struct rockchip_opp_data {
++	int (*set_read_margin)(struct device *dev, struct rockchip_opp_info *opp_info,
++			       unsigned long volt);
++};
++
++struct cluster_info {
++	struct list_head list_head;
++	struct rockchip_opp_info opp_info;
++	cpumask_t cpus;
++};
++static LIST_HEAD(cluster_info_list);
++
++static int rk3588_cpu_set_read_margin(struct device *dev, struct rockchip_opp_info *opp_info,
++				      unsigned long volt)
++{
++	bool is_found = false;
++	u32 rm;
++	int i;
++
++	if (!opp_info->volt_rm_tbl)
++		return 0;
++
++	for (i = 0; opp_info->volt_rm_tbl[i].rm != VOLT_RM_TABLE_END; i++) {
++		if (volt >= opp_info->volt_rm_tbl[i].volt) {
++			rm = opp_info->volt_rm_tbl[i].rm;
++			is_found = true;
++			break;
++		}
++	}
++
++	if (!is_found)
++		return 0;
++	if (rm == opp_info->current_rm)
++		return 0;
++	if (!opp_info->grf)
++		return 0;
++
++	dev_dbg(dev, "set rm to %d\n", rm);
++	regmap_write(opp_info->grf, RK3588_MEMCFG_HSSPRF_LOW, 0x001c0000 | (rm << 2));
++	regmap_write(opp_info->grf, RK3588_MEMCFG_HSDPRF_LOW, 0x003c0000 | (rm << 2));
++	regmap_write(opp_info->grf, RK3588_MEMCFG_HSDPRF_HIGH, 0x003c0000 | (rm << 2));
++	regmap_write(opp_info->grf, RK3588_CPU_CTRL, 0x00200020);
++	udelay(1);
++	regmap_write(opp_info->grf, RK3588_CPU_CTRL, 0x00200000);
++
++	opp_info->current_rm = rm;
++
++	return 0;
++}
++
++static const struct rockchip_opp_data rk3588_cpu_opp_data = {
++	.set_read_margin = rk3588_cpu_set_read_margin,
++};
++
++static const struct of_device_id rockchip_cpufreq_of_match[] = {
++	{
++		.compatible = "rockchip,rk3588",
++		.data = (void *)&rk3588_cpu_opp_data,
++	},
++	{},
++};
++
++static struct cluster_info *rockchip_cluster_info_lookup(int cpu)
++{
++	struct cluster_info *cluster;
++
++	list_for_each_entry(cluster, &cluster_info_list, list_head) {
++		if (cpumask_test_cpu(cpu, &cluster->cpus))
++			return cluster;
++	}
++
++	return NULL;
++}
++
++static int rockchip_cpufreq_set_volt(struct device *dev,
++				     struct regulator *reg,
++				     struct dev_pm_opp_supply *supply)
++{
++	int ret;
++
++	ret = regulator_set_voltage_triplet(reg, supply->u_volt_min,
++					    supply->u_volt, supply->u_volt_max);
++	if (ret)
++		dev_err(dev, "%s: failed to set voltage (%lu %lu %lu uV): %d\n",
++			__func__, supply->u_volt_min, supply->u_volt,
++			supply->u_volt_max, ret);
++
++	return ret;
++}
++
++static int rockchip_cpufreq_set_read_margin(struct device *dev,
++					    struct rockchip_opp_info *opp_info,
++					    unsigned long volt)
++{
++	if (opp_info->data && opp_info->data->set_read_margin) {
++		opp_info->data->set_read_margin(dev, opp_info, volt);
++	}
++
++	return 0;
++}
++
++static int rk_opp_config_regulators(struct device *dev,
++				    struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp,
++				    struct regulator **regulators, unsigned int count)
++{
++	struct dev_pm_opp_supply old_supplies[2];
++	struct dev_pm_opp_supply new_supplies[2];
++	struct regulator *vdd_reg = regulators[0];
++	struct regulator *mem_reg = regulators[1];
++	struct rockchip_opp_info *opp_info;
++	struct cluster_info *cluster;
++	int ret = 0;
++	unsigned long old_freq = dev_pm_opp_get_freq(old_opp);
++	unsigned long new_freq = dev_pm_opp_get_freq(new_opp);
++
++	/* We must have two regulators here */
++	WARN_ON(count != 2);
++
++	ret = dev_pm_opp_get_supplies(old_opp, old_supplies);
++	if (ret)
++		return ret;
++
++	ret = dev_pm_opp_get_supplies(new_opp, new_supplies);
++	if (ret)
++		return ret;
++
++	cluster = rockchip_cluster_info_lookup(dev->id);
++	if (!cluster)
++		return -EINVAL;
++	opp_info = &cluster->opp_info;
++
++	if (new_freq >= old_freq) {
++		ret = rockchip_cpufreq_set_volt(dev, mem_reg, &new_supplies[1]);
++		if (ret)
++			goto error;
++		ret = rockchip_cpufreq_set_volt(dev, vdd_reg, &new_supplies[0]);
++		if (ret)
++			goto error;
++		rockchip_cpufreq_set_read_margin(dev, opp_info, new_supplies[0].u_volt);
++	} else {
++		rockchip_cpufreq_set_read_margin(dev, opp_info, new_supplies[0].u_volt);
++		ret = rockchip_cpufreq_set_volt(dev, vdd_reg, &new_supplies[0]);
++		if (ret)
++			goto error;
++		ret = rockchip_cpufreq_set_volt(dev, mem_reg, &new_supplies[1]);
++		if (ret)
++			goto error;
++	}
++
++	return 0;
++
++error:
++	rockchip_cpufreq_set_read_margin(dev, opp_info, old_supplies[0].u_volt);
++	rockchip_cpufreq_set_volt(dev, mem_reg, &old_supplies[1]);
++	rockchip_cpufreq_set_volt(dev, vdd_reg, &old_supplies[0]);
++	return ret;
++}
++
++static void rockchip_get_opp_data(const struct of_device_id *matches,
++				  struct rockchip_opp_info *info)
++{
++	const struct of_device_id *match;
++	struct device_node *node;
++
++	node = of_find_node_by_path("/");
++	match = of_match_node(matches, node);
++	if (match && match->data)
++		info->data = match->data;
++	of_node_put(node);
++}
++
++static int rockchip_get_volt_rm_table(struct device *dev, struct device_node *np,
++				      char *porp_name, struct volt_rm_table **table)
++{
++	struct volt_rm_table *rm_table;
++	const struct property *prop;
++	int count, i;
++
++	prop = of_find_property(np, porp_name, NULL);
++	if (!prop)
++		return -EINVAL;
++
++	if (!prop->value)
++		return -ENODATA;
++
++	count = of_property_count_u32_elems(np, porp_name);
++	if (count < 0)
++		return -EINVAL;
++
++	if (count % 2)
++		return -EINVAL;
++
++	rm_table = devm_kzalloc(dev, sizeof(*rm_table) * (count / 2 + 1),
++				GFP_KERNEL);
++	if (!rm_table)
++		return -ENOMEM;
++
++	for (i = 0; i < count / 2; i++) {
++		of_property_read_u32_index(np, porp_name, 2 * i,
++					   &rm_table[i].volt);
++		of_property_read_u32_index(np, porp_name, 2 * i + 1,
++					   &rm_table[i].rm);
++	}
++
++	rm_table[i].volt = 0;
++	rm_table[i].rm = VOLT_RM_TABLE_END;
++
++	*table = rm_table;
++
++	return 0;
++}
++
++static int rockchip_cpufreq_reboot(struct notifier_block *notifier, unsigned long event, void *cmd)
++{
++	struct cluster_info *cluster;
++	struct device *dev;
++	int freq, ret, cpu;
++
++	if (event != SYS_RESTART)
++		return NOTIFY_DONE;
++
++	for_each_possible_cpu(cpu) {
++		cluster = rockchip_cluster_info_lookup(cpu);
++		if (!cluster)
++			continue;
++
++		dev = get_cpu_device(cpu);
++		if (!dev)
++			continue;
++
++		freq = cluster->opp_info.reboot_freq;
++
++		if (freq) {
++			ret = dev_pm_opp_set_rate(dev, freq);
++			if (ret)
++				dev_err(dev, "Failed setting reboot freq for cpu %d to %d: %d\n",
++					cpu, freq, ret);
++			dev_pm_opp_remove_table(dev);
++		}
++	}
++
++	return NOTIFY_DONE;
++}
++
++static int rockchip_cpufreq_cluster_init(int cpu, struct cluster_info *cluster)
++{
++	struct rockchip_opp_info *opp_info = &cluster->opp_info;
++	int reg_table_token = -EINVAL;
++	int opp_table_token = -EINVAL;
++	struct device_node *np;
++	struct device *dev;
++	const char * const reg_names[] = { "cpu", "mem", NULL };
++	int ret = 0;
++
++	dev = get_cpu_device(cpu);
++	if (!dev)
++		return -ENODEV;
++
++	if (!of_find_property(dev->of_node, "cpu-supply", NULL))
++		return -ENOENT;
++
++	np = of_parse_phandle(dev->of_node, "operating-points-v2", 0);
++	if (!np) {
++		dev_warn(dev, "OPP-v2 not supported\n");
++		return -ENOENT;
++	}
++
++	reg_table_token = dev_pm_opp_set_regulators(dev, reg_names);
++	if (reg_table_token < 0) {
++		ret = reg_table_token;
++		dev_err_probe(dev, ret, "Failed to set opp regulators\n");
++		goto np_err;
++	}
++
++	ret = dev_pm_opp_of_get_sharing_cpus(dev, &cluster->cpus);
++	if (ret) {
++		dev_err_probe(dev, ret, "Failed to get sharing cpus\n");
++		goto np_err;
++	}
++
++	rockchip_get_opp_data(rockchip_cpufreq_of_match, opp_info);
++	if (opp_info->data && opp_info->data->set_read_margin) {
++		opp_info->current_rm = UINT_MAX;
++		opp_info->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
++		if (IS_ERR(opp_info->grf))
++			opp_info->grf = NULL;
++		rockchip_get_volt_rm_table(dev, np, "rockchip,volt-mem-read-margin", &opp_info->volt_rm_tbl);
++
++		of_property_read_u32(np, "rockchip,reboot-freq", &opp_info->reboot_freq);
++	}
++
++	opp_table_token = dev_pm_opp_set_config_regulators(dev, rk_opp_config_regulators);
++	if (opp_table_token < 0) {
++		ret = opp_table_token;
++		dev_err(dev, "Failed to set opp config regulators\n");
++		goto reg_opp_table;
++	}
++
++	of_node_put(np);
++
++	return 0;
++
++reg_opp_table:
++	if (reg_table_token >= 0)
++		dev_pm_opp_put_regulators(reg_table_token);
++np_err:
++	of_node_put(np);
++
++	return ret;
++}
++
++static struct notifier_block rockchip_cpufreq_reboot_notifier = {
++	.notifier_call = rockchip_cpufreq_reboot,
++	.priority = 0,
++};
++
++static struct freq_attr *cpufreq_rockchip_attr[] = {
++	&cpufreq_freq_attr_scaling_available_freqs,
++	NULL,
++};
++
++static int cpufreq_online(struct cpufreq_policy *policy)
++{
++	/* We did light-weight tear down earlier, nothing to do here */
++	return 0;
++}
++
++static int cpufreq_offline(struct cpufreq_policy *policy)
++{
++	/*
++	 * Preserve policy->driver_data and don't free resources on light-weight
++	 * tear down.
++	 */
++	return 0;
++}
++
++static struct private_data *rockchip_cpufreq_find_data(int cpu)
++{
++	struct private_data *priv;
++
++	list_for_each_entry(priv, &priv_list, node) {
++		if (cpumask_test_cpu(cpu, priv->cpus))
++			return priv;
++	}
++
++	return NULL;
++}
++
++static int cpufreq_init(struct cpufreq_policy *policy)
++{
++	struct private_data *priv;
++	struct device *cpu_dev;
++	struct clk *cpu_clk;
++	unsigned int transition_latency;
++	int ret;
++
++	priv = rockchip_cpufreq_find_data(policy->cpu);
++	if (!priv) {
++		pr_err("failed to find data for cpu%d\n", policy->cpu);
++		return -ENODEV;
++	}
++	cpu_dev = priv->cpu_dev;
++
++	cpu_clk = clk_get(cpu_dev, NULL);
++	if (IS_ERR(cpu_clk)) {
++		ret = PTR_ERR(cpu_clk);
++		dev_err(cpu_dev, "%s: failed to get clk: %d\n", __func__, ret);
++		return ret;
++	}
++
++	transition_latency = dev_pm_opp_get_max_transition_latency(cpu_dev);
++	if (!transition_latency)
++		transition_latency = CPUFREQ_ETERNAL;
++
++	cpumask_copy(policy->cpus, priv->cpus);
++	policy->driver_data = priv;
++	policy->clk = cpu_clk;
++	policy->freq_table = priv->freq_table;
++	policy->suspend_freq = dev_pm_opp_get_suspend_opp_freq(cpu_dev) / 1000;
++	policy->cpuinfo.transition_latency = transition_latency;
++	policy->dvfs_possible_from_any_cpu = true;
++
++	return 0;
++}
++
++static int cpufreq_exit(struct cpufreq_policy *policy)
++{
++	clk_put(policy->clk);
++	return 0;
++}
++
++static int set_target(struct cpufreq_policy *policy, unsigned int index)
++{
++	struct private_data *priv = policy->driver_data;
++	unsigned long freq = policy->freq_table[index].frequency;
++
++	return dev_pm_opp_set_rate(priv->cpu_dev, freq * 1000);
++}
++
++static struct cpufreq_driver rockchip_cpufreq_driver = {
++	.flags = CPUFREQ_NEED_INITIAL_FREQ_CHECK |
++		 CPUFREQ_IS_COOLING_DEV |
++		 CPUFREQ_HAVE_GOVERNOR_PER_POLICY,
++	.verify = cpufreq_generic_frequency_table_verify,
++	.target_index = set_target,
++	.get = cpufreq_generic_get,
++	.init = cpufreq_init,
++	.exit = cpufreq_exit,
++	.online = cpufreq_online,
++	.offline = cpufreq_offline,
++	.register_em = cpufreq_register_em_with_opp,
++	.name = "rockchip-cpufreq",
++	.attr = cpufreq_rockchip_attr,
++	.suspend = cpufreq_generic_suspend,
++};
++
++static int rockchip_cpufreq_init(struct device *dev, int cpu)
++{
++	struct private_data *priv;
++	struct device *cpu_dev;
++	int ret;
++
++	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
++	if (!priv)
++		return -ENOMEM;
++
++	if (!alloc_cpumask_var(&priv->cpus, GFP_KERNEL))
++		return -ENOMEM;
++
++	cpumask_set_cpu(cpu, priv->cpus);
++
++	cpu_dev = get_cpu_device(cpu);
++	if (!cpu_dev)
++		return -EPROBE_DEFER;
++	priv->cpu_dev = cpu_dev;
++
++	ret = dev_pm_opp_of_get_sharing_cpus(cpu_dev, priv->cpus);
++	if (ret)
++		return ret;
++
++	ret = dev_pm_opp_of_cpumask_add_table(priv->cpus);
++	if (ret)
++		return ret;
++
++	ret = dev_pm_opp_get_opp_count(cpu_dev);
++	if (ret <= 0)
++		return dev_err_probe(cpu_dev, -ENODEV, "OPP table can't be empty\n");
++
++	ret = dev_pm_opp_init_cpufreq_table(cpu_dev, &priv->freq_table);
++	if (ret)
++		return dev_err_probe(cpu_dev, ret, "failed to init cpufreq table\n");
++
++	list_add(&priv->node, &priv_list);
++
++	return 0;
++}
++
++static void rockchip_cpufreq_free_list(void *data)
++{
++	struct cluster_info *cluster, *pos;
++
++	list_for_each_entry_safe(cluster, pos, &cluster_info_list, list_head) {
++		list_del(&cluster->list_head);
++	}
++}
++
++static int rockchip_cpufreq_init_list(struct device *dev)
++{
++	struct cluster_info *cluster;
++	int cpu, ret;
++
++	for_each_possible_cpu(cpu) {
++		cluster = rockchip_cluster_info_lookup(cpu);
++		if (cluster)
++			continue;
++
++		cluster = devm_kzalloc(dev, sizeof(*cluster), GFP_KERNEL);
++		if (!cluster) {
++			ret = -ENOMEM;
++			goto release_cluster_info;
++		}
++
++		ret = rockchip_cpufreq_cluster_init(cpu, cluster);
++		if (ret) {
++			dev_err_probe(dev, ret, "Failed to initialize dvfs info cpu%d\n", cpu);
++			goto release_cluster_info;
++		}
++		list_add(&cluster->list_head, &cluster_info_list);
++	}
++
++	return 0;
++
++release_cluster_info:
++	rockchip_cpufreq_free_list(NULL);
++	return ret;
++}
++
++static void rockchip_cpufreq_unregister(void *data)
++{
++	cpufreq_unregister_driver(&rockchip_cpufreq_driver);
++}
++
++static int rockchip_cpufreq_probe(struct platform_device *pdev)
++{
++	int ret, cpu;
++
++	ret = rockchip_cpufreq_init_list(&pdev->dev);
++	if (ret)
++		return ret;
++
++	ret = devm_add_action_or_reset(&pdev->dev, rockchip_cpufreq_free_list, NULL);
++	if (ret)
++		return ret;
++
++	ret = devm_register_reboot_notifier(&pdev->dev, &rockchip_cpufreq_reboot_notifier);
++	if (ret)
++		return dev_err_probe(&pdev->dev, ret, "Failed to register reboot handler\n");
++
++	for_each_possible_cpu(cpu) {
++		ret = rockchip_cpufreq_init(&pdev->dev, cpu);
++		if (ret)
++			return ret;
++	}
++
++	ret = cpufreq_register_driver(&rockchip_cpufreq_driver);
++	if (ret)
++		return dev_err_probe(&pdev->dev, ret, "failed register driver\n");
++
++	ret = devm_add_action_or_reset(&pdev->dev, rockchip_cpufreq_unregister, NULL);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static struct platform_driver rockchip_cpufreq_platdrv = {
++	.driver = {
++		.name	= "rockchip-cpufreq",
++	},
++	.probe		= rockchip_cpufreq_probe,
++};
++
++static int __init rockchip_cpufreq_driver_init(void)
++{
++	int ret;
++
++	ret = platform_driver_register(&rockchip_cpufreq_platdrv);
++	if (ret)
++		return ret;
++
++	cpufreq_pdev = platform_device_register_data(NULL, "rockchip-cpufreq", -1,
++						     NULL, 0);
++	if (IS_ERR(cpufreq_pdev)) {
++		pr_err("failed to register rockchip-cpufreq platform device\n");
++		ret = PTR_ERR(cpufreq_pdev);
++		goto unregister_platform_driver;
++	}
++
++	return 0;
++
++unregister_platform_driver:
++	platform_driver_unregister(&rockchip_cpufreq_platdrv);
++	return ret;
++}
++module_init(rockchip_cpufreq_driver_init);
++
++static void __exit rockchip_cpufreq_driver_exit(void)
++{
++	platform_device_unregister(cpufreq_pdev);
++	platform_driver_unregister(&rockchip_cpufreq_platdrv);
++}
++module_exit(rockchip_cpufreq_driver_exit)
++
++MODULE_AUTHOR("Finley Xiao <finley.xiao@rock-chips.com>");
++MODULE_DESCRIPTION("Rockchip cpufreq driver");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/rockchip/patches-6.1/250-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling-.patch b/target/linux/rockchip/patches-6.1/250-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling-.patch
new file mode 100644
index 00000000000..c78d615b03d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/250-arm64-dts-rockchip-rk3588-add-cpu-frequency-scaling-.patch
@@ -0,0 +1,556 @@
+From cce542d393d7e0ab3268eb75b4c028550425f91b Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 4 Apr 2023 17:30:46 +0200
+Subject: [PATCH 250/383] arm64: dts: rockchip: rk3588: add cpu frequency
+ scaling support
+
+Add required bits for CPU frequency scaling to the Rockchip 3588
+devicetree. This is missing the 2.4 GHz operating point for the
+big cpu clusters, since that does not work well on all SoCs.
+Downstream has a driver for PVTM, which reduces the requested
+frequencies based on (among other things) silicon quality.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 452 ++++++++++++++++++++++
+ 1 file changed, 452 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -8,6 +8,7 @@
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	compatible = "rockchip,rk3588";
+@@ -16,6 +17,215 @@
+ 	#address-cells = <2>;
+ 	#size-cells = <2>;
+ 
++	cluster0_opp_table: opp-table-cluster0 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		opp-408000000 {
++			opp-hz = /bits/ 64 <408000000>;
++			opp-microvolt = <750000 750000 950000>,
++					<750000 750000 950000>;
++			clock-latency-ns = <40000>;
++			opp-suspend;
++		};
++		opp-600000000 {
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt = <750000 750000 950000>,
++					<750000 750000 950000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-816000000 {
++			opp-hz = /bits/ 64 <816000000>;
++			opp-microvolt = <750000 750000 950000>,
++					<750000 750000 950000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt = <750000 750000 950000>,
++					<750000 750000 950000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <775000 775000 950000>,
++					<775000 775000 950000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1416000000 {
++			opp-hz = /bits/ 64 <1416000000>;
++			opp-microvolt = <825000 825000 950000>,
++					<825000 825000 950000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <875000 875000 950000>,
++					<875000 875000 950000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <950000 950000 950000>,
++					<950000 950000 950000>;
++			clock-latency-ns = <40000>;
++		};
++	};
++
++	cluster1_opp_table: opp-table-cluster1 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		rockchip,grf = <&bigcore0_grf>;
++		rockchip,volt-mem-read-margin = <
++			855000	1
++			765000	2
++			675000	3
++			495000	4
++		>;
++
++		rockchip,reboot-freq = <1800000000>;
++
++		opp-408000000 {
++			opp-hz = /bits/ 64 <408000000>;
++			opp-microvolt = <600000 600000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++			opp-suspend;
++		};
++		opp-600000000 {
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt = <600000 600000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-816000000 {
++			opp-hz = /bits/ 64 <816000000>;
++			opp-microvolt = <600000 600000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt = <625000 625000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <650000 650000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1416000000 {
++			opp-hz = /bits/ 64 <1416000000>;
++			opp-microvolt = <675000 675000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <700000 700000 1000000>,
++					<700000 700000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <775000 775000 1000000>,
++					<775000 775000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-2016000000 {
++			opp-hz = /bits/ 64 <2016000000>;
++			opp-microvolt = <850000 850000 1000000>,
++					<850000 850000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-2208000000 {
++			opp-hz = /bits/ 64 <2208000000>;
++			opp-microvolt = <925000 925000 1000000>,
++					<925000 925000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++	};
++
++	cluster2_opp_table: opp-table-cluster2 {
++		compatible = "operating-points-v2";
++		opp-shared;
++
++		rockchip,grf = <&bigcore1_grf>;
++		rockchip,volt-mem-read-margin = <
++			855000	1
++			765000	2
++			675000	3
++			495000	4
++		>;
++
++		rockchip,reboot-freq = <1800000000>;
++
++		opp-408000000 {
++			opp-hz = /bits/ 64 <408000000>;
++			opp-microvolt = <600000 600000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++			opp-suspend;
++		};
++		opp-600000000 {
++			opp-hz = /bits/ 64 <600000000>;
++			opp-microvolt = <600000 600000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-816000000 {
++			opp-hz = /bits/ 64 <816000000>;
++			opp-microvolt = <600000 600000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1008000000 {
++			opp-hz = /bits/ 64 <1008000000>;
++			opp-microvolt = <625000 625000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1200000000 {
++			opp-hz = /bits/ 64 <1200000000>;
++			opp-microvolt = <650000 650000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1416000000 {
++			opp-hz = /bits/ 64 <1416000000>;
++			opp-microvolt = <675000 675000 1000000>,
++					<675000 675000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1608000000 {
++			opp-hz = /bits/ 64 <1608000000>;
++			opp-microvolt = <700000 700000 1000000>,
++					<700000 700000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-1800000000 {
++			opp-hz = /bits/ 64 <1800000000>;
++			opp-microvolt = <775000 775000 1000000>,
++					<775000 775000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-2016000000 {
++			opp-hz = /bits/ 64 <2016000000>;
++			opp-microvolt = <850000 850000 1000000>,
++					<850000 850000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++		opp-2208000000 {
++			opp-hz = /bits/ 64 <2208000000>;
++			opp-microvolt = <925000 925000 1000000>,
++					<925000 925000 1000000>;
++			clock-latency-ns = <40000>;
++		};
++	};
++
+ 	cpus {
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -62,6 +272,7 @@
+ 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ 			assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>;
+ 			assigned-clock-rates = <816000000>;
++			operating-points-v2 = <&cluster0_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <32768>;
+ 			i-cache-line-size = <64>;
+@@ -81,6 +292,7 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <530>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			operating-points-v2 = <&cluster0_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <32768>;
+ 			i-cache-line-size = <64>;
+@@ -100,6 +312,7 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <530>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			operating-points-v2 = <&cluster0_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <32768>;
+ 			i-cache-line-size = <64>;
+@@ -119,6 +332,7 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <530>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUL>;
++			operating-points-v2 = <&cluster0_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <32768>;
+ 			i-cache-line-size = <64>;
+@@ -140,6 +354,7 @@
+ 			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ 			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>;
+ 			assigned-clock-rates = <816000000>;
++			operating-points-v2 = <&cluster1_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <65536>;
+ 			i-cache-line-size = <64>;
+@@ -159,6 +374,7 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <1024>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUB01>;
++			operating-points-v2 = <&cluster1_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <65536>;
+ 			i-cache-line-size = <64>;
+@@ -180,6 +396,7 @@
+ 			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ 			assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>;
+ 			assigned-clock-rates = <816000000>;
++			operating-points-v2 = <&cluster2_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <65536>;
+ 			i-cache-line-size = <64>;
+@@ -199,6 +416,7 @@
+ 			enable-method = "psci";
+ 			capacity-dmips-mhz = <1024>;
+ 			clocks = <&scmi_clk SCMI_CLK_CPUB23>;
++			operating-points-v2 = <&cluster2_opp_table>;
+ 			cpu-idle-states = <&CPU_SLEEP>;
+ 			i-cache-size = <65536>;
+ 			i-cache-line-size = <64>;
+@@ -360,6 +578,230 @@
+ 		#clock-cells = <0>;
+ 	};
+ 
++	thermal_zones: thermal-zones {
++		soc_thermal: soc-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			sustainable-power = <2100>; /* milliwatts */
++
++			thermal-sensors = <&tsadc 0>;
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				soc_target: trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&soc_target>;
++					cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <1024>;
++				};
++			};
++		};
++
++		bigcore0_thermal: bigcore0-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			thermal-sensors = <&tsadc 1>;
++
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				b0_target: trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&b0_target>;
++					cooling-device = <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <1024>;
++				};
++			};
++		};
++
++		bigcore1_thermal: bigcore1-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			thermal-sensors = <&tsadc 2>;
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				b1_target: trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&b1_target>;
++					cooling-device = <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <1024>;
++				};
++			};
++		};
++
++		little_core_thermal: littlecore-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			thermal-sensors = <&tsadc 3>;
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				l0_target: trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++
++			cooling-maps {
++				map0 {
++					trip = <&l0_target>;
++					cooling-device = <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
++							 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
++					contribution = <1024>;
++				};
++			};
++		};
++
++		center_thermal: center-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			thermal-sensors = <&tsadc 4>;
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++
++		gpu_thermal: gpu-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			thermal-sensors = <&tsadc 5>;
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++
++		npu_thermal: npu-thermal {
++			polling-delay-passive = <20>; /* milliseconds */
++			polling-delay = <1000>; /* milliseconds */
++			thermal-sensors = <&tsadc 6>;
++			trips {
++				trip-point-0 {
++					temperature = <75000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-1 {
++					temperature = <85000>;
++					hysteresis = <2000>;
++					type = "passive";
++				};
++				trip-point-2 {
++					/* millicelsius */
++					temperature = <115000>;
++					/* millicelsius */
++					hysteresis = <2000>;
++					type = "critical";
++				};
++			};
++		};
++	};
++
+ 	timer {
+ 		compatible = "arm,armv8-timer";
+ 		interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+@@ -402,6 +844,16 @@
+ 		reg = <0x0 0xfd58c000 0x0 0x1000>;
+ 	};
+ 
++	bigcore0_grf: syscon@fd590000 {
++		compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
++		reg = <0x0 0xfd590000 0x0 0x100>;
++	};
++
++	bigcore1_grf: syscon@fd592000 {
++		compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
++		reg = <0x0 0xfd592000 0x0 0x100>;
++	};
++
+ 	php_grf: syscon@fd5b0000 {
+ 		compatible = "rockchip,rk3588-php-grf", "syscon";
+ 		reg = <0x0 0xfd5b0000 0x0 0x1000>;
diff --git a/target/linux/rockchip/patches-6.1/251-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-inf.patch b/target/linux/rockchip/patches-6.1/251-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-inf.patch
new file mode 100644
index 00000000000..fffbb9dd19e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/251-arm64-dts-rockchip-rk3588-evb1-add-cpu-regulator-inf.patch
@@ -0,0 +1,50 @@
+From 0391014ac6b5e7304c274f11720990c3f517eb8b Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 18 Aug 2022 14:35:46 +0200
+Subject: [PATCH 251/383] arm64: dts: rockchip: rk3588-evb1: add cpu regulator
+ info
+
+Add regulator information for the CPU and enable the thermal sensor
+to have working cpu frequency scaling.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 19 +++++++++++++++++++
+ 1 file changed, 19 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -49,6 +49,21 @@
+ 	};
+ };
+ 
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++	mem-supply = <&vdd_cpu_lit_mem_s0>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_big0_s0>;
++	mem-supply = <&vdd_cpu_big0_mem_s0>;
++};
++
++&cpu_b2 {
++	cpu-supply = <&vdd_cpu_big1_s0>;
++	mem-supply = <&vdd_cpu_big1_mem_s0>;
++};
++
+ &gmac0 {
+ 	clock_in_out = "output";
+ 	phy-handle = <&rgmii_phy>;
+@@ -863,6 +878,10 @@
+ 	};
+ };
+ 
++&tsadc {
++	status = "okay";
++};
++
+ &uart2 {
+ 	pinctrl-0 = <&uart2m0_xfer>;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/252-dt-bindings-usb-Add-RK3588-OHCI.patch b/target/linux/rockchip/patches-6.1/252-dt-bindings-usb-Add-RK3588-OHCI.patch
new file mode 100644
index 00000000000..c828d818f2a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/252-dt-bindings-usb-Add-RK3588-OHCI.patch
@@ -0,0 +1,55 @@
+From 5b5dce2b195fbdfd126a06304fc37f0c93cb1752 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 30 Mar 2023 16:31:18 +0200
+Subject: [PATCH 252/383] dt-bindings: usb: Add RK3588 OHCI
+
+Add compatible for RK3588 OHCI. As far as I know it's fully
+compatible with generic-ohci.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/usb/generic-ohci.yaml   | 17 ++++++++++++++++-
+ 1 file changed, 16 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/usb/generic-ohci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ohci.yaml
+@@ -44,6 +44,7 @@ properties:
+               - hpe,gxp-ohci
+               - ibm,476gtr-ohci
+               - ingenic,jz4740-ohci
++              - rockchip,rk3588-ohci
+               - snps,hsdk-v1.0-ohci
+           - const: generic-ohci
+       - enum:
+@@ -69,7 +70,7 @@ properties:
+ 
+   clocks:
+     minItems: 1
+-    maxItems: 3
++    maxItems: 4
+     description: |
+       In case the Renesas R-Car Gen3 SoCs:
+         - if a host only channel: first clock should be host.
+@@ -147,6 +148,20 @@ allOf:
+     then:
+       properties:
+         transceiver: false
++  - if:
++      properties:
++        compatible:
++          contains:
++            const: rockchip,rk3588-ohci
++    then:
++      properties:
++        clocks:
++          minItems: 4
++    else:
++      properties:
++        clocks:
++          minItems: 1
++          maxItems: 3
+ 
+ unevaluatedProperties: false
+ 
diff --git a/target/linux/rockchip/patches-6.1/253-dt-bindings-usb-Add-RK3588-EHCI.patch b/target/linux/rockchip/patches-6.1/253-dt-bindings-usb-Add-RK3588-EHCI.patch
new file mode 100644
index 00000000000..378aed7d820
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/253-dt-bindings-usb-Add-RK3588-EHCI.patch
@@ -0,0 +1,26 @@
+From 42fc4ed4b445af9300c8b96a20dcc3c39b347ce6 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 4 Apr 2023 15:32:54 +0200
+Subject: [PATCH 253/383] dt-bindings: usb: Add RK3588 EHCI
+
+Add compatible for RK3588 EHCI. As far as I know it's fully
+compatible with generic-ehci.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/usb/generic-ehci.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/usb/generic-ehci.yaml
++++ b/Documentation/devicetree/bindings/usb/generic-ehci.yaml
+@@ -61,6 +61,7 @@ properties:
+               - ibm,476gtr-ehci
+               - nxp,lpc1850-ehci
+               - qca,ar7100-ehci
++              - rockchip,rk3588-ehci
+               - snps,hsdk-v1.0-ehci
+               - socionext,uniphier-ehci
+           - const: generic-ehci
diff --git a/target/linux/rockchip/patches-6.1/254-usb-host-ohci-platform-increase-max-clock-number-to-.patch b/target/linux/rockchip/patches-6.1/254-usb-host-ohci-platform-increase-max-clock-number-to-.patch
new file mode 100644
index 00000000000..a7d00f3ec00
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/254-usb-host-ohci-platform-increase-max-clock-number-to-.patch
@@ -0,0 +1,26 @@
+From af8418372ced7a8362dd0770e662312f43581a07 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 29 Mar 2023 18:54:49 +0200
+Subject: [PATCH 254/383] usb: host: ohci-platform: increase max clock number
+ to 4
+
+Rockchip RK3588 OHCI requires 4 clocks to be enabled.
+
+Acked-by: Alan Stern <stern@rowland.harvard.edu>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/usb/host/ohci-platform.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/usb/host/ohci-platform.c
++++ b/drivers/usb/host/ohci-platform.c
+@@ -33,7 +33,7 @@
+ #include "ohci.h"
+ 
+ #define DRIVER_DESC "OHCI generic platform driver"
+-#define OHCI_MAX_CLKS 3
++#define OHCI_MAX_CLKS 4
+ #define hcd_to_ohci_priv(h) ((struct ohci_platform_priv *)hcd_to_ohci(h)->priv)
+ 
+ struct ohci_platform_priv {
diff --git a/target/linux/rockchip/patches-6.1/255-dt-bindings-phy-rockchip-inno-usb2phy-add-rk3588.patch b/target/linux/rockchip/patches-6.1/255-dt-bindings-phy-rockchip-inno-usb2phy-add-rk3588.patch
new file mode 100644
index 00000000000..ed6bcb30599
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/255-dt-bindings-phy-rockchip-inno-usb2phy-add-rk3588.patch
@@ -0,0 +1,64 @@
+From fe0ff33f83bc59d7e12efe997922e93fe2e25fae Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 30 Mar 2023 16:25:20 +0200
+Subject: [PATCH 255/383] dt-bindings: phy: rockchip,inno-usb2phy: add rk3588
+
+Add compatible for the USB2 phy in the Rockchip RK3588 SoC.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/phy/rockchip,inno-usb2phy.yaml   | 21 ++++++++++++++++---
+ 1 file changed, 18 insertions(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
++++ b/Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+@@ -20,6 +20,7 @@ properties:
+       - rockchip,rk3366-usb2phy
+       - rockchip,rk3399-usb2phy
+       - rockchip,rk3568-usb2phy
++      - rockchip,rk3588-usb2phy
+       - rockchip,rv1108-usb2phy
+ 
+   reg:
+@@ -56,6 +57,14 @@ properties:
+     description: Muxed interrupt for both ports
+     maxItems: 1
+ 
++  resets:
++    maxItems: 2
++
++  reset-names:
++    items:
++      - const: phy
++      - const: apb
++
+   rockchip,usbgrf:
+     $ref: /schemas/types.yaml#/definitions/phandle
+     description:
+@@ -120,15 +129,21 @@ required:
+   - reg
+   - clock-output-names
+   - "#clock-cells"
+-  - host-port
+-  - otg-port
++
++anyOf:
++  - required:
++      - otg-port
++  - required:
++      - host-port
+ 
+ allOf:
+   - if:
+       properties:
+         compatible:
+           contains:
+-            const: rockchip,rk3568-usb2phy
++            enum:
++              - rockchip,rk3568-usb2phy
++              - rockchip,rk3588-usb2phy
+ 
+     then:
+       properties:
diff --git a/target/linux/rockchip/patches-6.1/256-phy-phy-rockchip-inno-usb2-add-rk3588-support.patch b/target/linux/rockchip/patches-6.1/256-phy-phy-rockchip-inno-usb2-add-rk3588-support.patch
new file mode 100644
index 00000000000..22bde63f616
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/256-phy-phy-rockchip-inno-usb2-add-rk3588-support.patch
@@ -0,0 +1,350 @@
+From dffcf64f750d5853835324a6c122f1a5ccfe1db7 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 12 Jan 2023 19:15:52 +0100
+Subject: [PATCH 256/383] phy: phy-rockchip-inno-usb2: add rk3588 support
+
+Add basic support for the USB2 PHY found in the Rockchip RK3588.
+
+Co-developed-by: William Wu <william.wu@rock-chips.com>
+Signed-off-by: William Wu <william.wu@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 226 ++++++++++++++++--
+ 1 file changed, 211 insertions(+), 15 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -116,6 +116,12 @@ struct rockchip_chg_det_reg {
+  * @bvalid_det_en: vbus valid rise detection enable register.
+  * @bvalid_det_st: vbus valid rise detection status register.
+  * @bvalid_det_clr: vbus valid rise detection clear register.
++ * @disfall_en: host disconnect fall edge detection enable.
++ * @disfall_st: host disconnect fall edge detection state.
++ * @disfall_clr: host disconnect fall edge detection clear.
++ * @disrise_en: host disconnect rise edge detection enable.
++ * @disrise_st: host disconnect rise edge detection state.
++ * @disrise_clr: host disconnect rise edge detection clear.
+  * @id_det_en: id detection enable register.
+  * @id_det_st: id detection state register.
+  * @id_det_clr: id detection clear register.
+@@ -133,6 +139,12 @@ struct rockchip_usb2phy_port_cfg {
+ 	struct usb2phy_reg	bvalid_det_en;
+ 	struct usb2phy_reg	bvalid_det_st;
+ 	struct usb2phy_reg	bvalid_det_clr;
++	struct usb2phy_reg      disfall_en;
++	struct usb2phy_reg      disfall_st;
++	struct usb2phy_reg      disfall_clr;
++	struct usb2phy_reg      disrise_en;
++	struct usb2phy_reg      disrise_st;
++	struct usb2phy_reg      disrise_clr;
+ 	struct usb2phy_reg	id_det_en;
+ 	struct usb2phy_reg	id_det_st;
+ 	struct usb2phy_reg	id_det_clr;
+@@ -168,6 +180,7 @@ struct rockchip_usb2phy_cfg {
+  * @port_id: flag for otg port or host port.
+  * @suspended: phy suspended flag.
+  * @vbus_attached: otg device vbus status.
++ * @host_disconnect: usb host disconnect status.
+  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
+  * @id_irq: IRQ number assigned for ID pin detection.
+  * @ls_irq: IRQ number assigned for linestate detection.
+@@ -187,6 +200,7 @@ struct rockchip_usb2phy_port {
+ 	unsigned int	port_id;
+ 	bool		suspended;
+ 	bool		vbus_attached;
++	bool            host_disconnect;
+ 	int		bvalid_irq;
+ 	int		id_irq;
+ 	int		ls_irq;
+@@ -405,6 +419,27 @@ static int rockchip_usb2phy_extcon_regis
+ 	return 0;
+ }
+ 
++static int rockchip_usb2phy_enable_host_disc_irq(struct rockchip_usb2phy *rphy,
++						 struct rockchip_usb2phy_port *rport,
++						 bool en)
++{
++	int ret;
++
++	ret = property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
++	if (ret)
++		return ret;
++
++	ret = property_enable(rphy->grf, &rport->port_cfg->disfall_en, en);
++	if (ret)
++		return ret;
++
++	ret = property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
++	if (ret)
++		return ret;
++
++	return property_enable(rphy->grf, &rport->port_cfg->disrise_en, en);
++}
++
+ static int rockchip_usb2phy_init(struct phy *phy)
+ {
+ 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
+@@ -449,6 +484,15 @@ static int rockchip_usb2phy_init(struct
+ 			dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
+ 		}
+ 	} else if (rport->port_id == USB2PHY_PORT_HOST) {
++		if (rport->port_cfg->disfall_en.offset) {
++			rport->host_disconnect = true;
++			ret = rockchip_usb2phy_enable_host_disc_irq(rphy, rport, true);
++			if (ret) {
++				dev_err(rphy->dev, "failed to enable disconnect irq\n");
++				goto out;
++			}
++		}
++
+ 		/* clear linestate and enable linestate detect irq */
+ 		ret = property_enable(rphy->grf,
+ 				      &rport->port_cfg->ls_det_clr, true);
+@@ -810,9 +854,7 @@ static void rockchip_usb2phy_sm_work(str
+ 	struct rockchip_usb2phy_port *rport =
+ 		container_of(work, struct rockchip_usb2phy_port, sm_work.work);
+ 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
+-	unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
+-			  rport->port_cfg->utmi_hstdet.bitstart + 1;
+-	unsigned int ul, uhd, state;
++	unsigned int sh, ul, uhd, state;
+ 	unsigned int ul_mask, uhd_mask;
+ 	int ret;
+ 
+@@ -822,18 +864,26 @@ static void rockchip_usb2phy_sm_work(str
+ 	if (ret < 0)
+ 		goto next_schedule;
+ 
+-	ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
+-	if (ret < 0)
+-		goto next_schedule;
+-
+-	uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
+-			   rport->port_cfg->utmi_hstdet.bitstart);
+ 	ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
+ 			  rport->port_cfg->utmi_ls.bitstart);
+ 
+-	/* stitch on utmi_ls and utmi_hstdet as phy state */
+-	state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
+-		(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
++	if (rport->port_cfg->utmi_hstdet.offset) {
++		ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
++		if (ret < 0)
++			goto next_schedule;
++
++		uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
++				   rport->port_cfg->utmi_hstdet.bitstart);
++
++		sh = rport->port_cfg->utmi_hstdet.bitend -
++		     rport->port_cfg->utmi_hstdet.bitstart + 1;
++		/* stitch on utmi_ls and utmi_hstdet as phy state */
++		state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
++			(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
++	} else {
++		state = ((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << 1 |
++			rport->host_disconnect;
++	}
+ 
+ 	switch (state) {
+ 	case PHY_STATE_HS_ONLINE:
+@@ -966,6 +1016,31 @@ static irqreturn_t rockchip_usb2phy_otg_
+ 	return ret;
+ }
+ 
++static irqreturn_t rockchip_usb2phy_host_disc_irq(int irq, void *data)
++{
++	struct rockchip_usb2phy_port *rport = data;
++	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
++
++	if (!property_enabled(rphy->grf, &rport->port_cfg->disfall_st) &&
++	    !property_enabled(rphy->grf, &rport->port_cfg->disrise_st))
++		return IRQ_NONE;
++
++	mutex_lock(&rport->mutex);
++
++	/* clear disconnect fall or rise detect irq pending status */
++	if (property_enabled(rphy->grf, &rport->port_cfg->disfall_st)) {
++		property_enable(rphy->grf, &rport->port_cfg->disfall_clr, true);
++		rport->host_disconnect = false;
++	} else if (property_enabled(rphy->grf, &rport->port_cfg->disrise_st)) {
++		property_enable(rphy->grf, &rport->port_cfg->disrise_clr, true);
++		rport->host_disconnect = true;
++	}
++
++	mutex_unlock(&rport->mutex);
++
++	return IRQ_HANDLED;
++}
++
+ static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
+ {
+ 	struct rockchip_usb2phy *rphy = data;
+@@ -978,6 +1053,10 @@ static irqreturn_t rockchip_usb2phy_irq(
+ 		if (!rport->phy)
+ 			continue;
+ 
++		if (rport->port_id == USB2PHY_PORT_HOST &&
++		    rport->port_cfg->disfall_en.offset)
++			ret |= rockchip_usb2phy_host_disc_irq(irq, rport);
++
+ 		switch (rport->port_id) {
+ 		case USB2PHY_PORT_OTG:
+ 			if (rport->mode != USB_DR_MODE_HOST &&
+@@ -1233,7 +1312,7 @@ static int rockchip_usb2phy_probe(struct
+ 	}
+ 
+ 	/* support address_cells=2 */
+-	if (reg == 0) {
++	if (of_property_count_u32_elems(np, "reg") > 2 && reg == 0) {
+ 		if (of_property_read_u32_index(np, "reg", 1, &reg)) {
+ 			dev_err(dev, "the reg property is not assigned in %pOFn node\n",
+ 				np);
+@@ -1254,14 +1333,14 @@ static int rockchip_usb2phy_probe(struct
+ 
+ 	/* find out a proper config which can be matched with dt. */
+ 	index = 0;
+-	while (phy_cfgs[index].reg) {
++	do {
+ 		if (phy_cfgs[index].reg == reg) {
+ 			rphy->phy_cfg = &phy_cfgs[index];
+ 			break;
+ 		}
+ 
+ 		++index;
+-	}
++	} while (phy_cfgs[index].reg);
+ 
+ 	if (!rphy->phy_cfg) {
+ 		dev_err(dev, "no phy-config can be matched with %pOFn node\n",
+@@ -1664,6 +1743,122 @@ static const struct rockchip_usb2phy_cfg
+ 	{ /* sentinel */ }
+ };
+ 
++static const struct rockchip_usb2phy_cfg rk3588_phy_cfgs[] = {
++	{
++		.reg = 0x0000,
++		.num_ports	= 1,
++		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
++		.port_cfgs	= {
++			[USB2PHY_PORT_OTG] = {
++				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
++				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
++				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
++				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
++				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
++				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
++				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
++				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
++				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
++				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
++				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
++				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
++				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
++				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
++				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
++				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
++			}
++		},
++		.chg_det = {
++			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
++			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
++			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
++			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
++			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
++			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
++			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
++			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
++			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
++		},
++	},
++	{
++		.reg = 0x4000,
++		.num_ports	= 1,
++		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
++		.port_cfgs	= {
++			[USB2PHY_PORT_OTG] = {
++				.phy_sus	= { 0x000c, 11, 11, 0, 1 },
++				.bvalid_det_en	= { 0x0080, 1, 1, 0, 1 },
++				.bvalid_det_st	= { 0x0084, 1, 1, 0, 1 },
++				.bvalid_det_clr = { 0x0088, 1, 1, 0, 1 },
++				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
++				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
++				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
++				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
++				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
++				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
++				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
++				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
++				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
++				.utmi_avalid	= { 0x00c0, 7, 7, 0, 1 },
++				.utmi_bvalid	= { 0x00c0, 6, 6, 0, 1 },
++				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
++			}
++		},
++		.chg_det = {
++			.cp_det		= { 0x00c0, 0, 0, 0, 1 },
++			.dcp_det	= { 0x00c0, 0, 0, 0, 1 },
++			.dp_det		= { 0x00c0, 1, 1, 1, 0 },
++			.idm_sink_en	= { 0x0008, 5, 5, 1, 0 },
++			.idp_sink_en	= { 0x0008, 5, 5, 0, 1 },
++			.idp_src_en	= { 0x0008, 14, 14, 0, 1 },
++			.rdm_pdwn_en	= { 0x0008, 14, 14, 0, 1 },
++			.vdm_src_en	= { 0x0008, 7, 6, 0, 3 },
++			.vdp_src_en	= { 0x0008, 7, 6, 0, 3 },
++		},
++	},
++	{
++		.reg = 0x8000,
++		.num_ports	= 1,
++		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
++		.port_cfgs	= {
++			[USB2PHY_PORT_HOST] = {
++				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
++				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
++				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
++				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
++				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
++				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
++				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
++				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
++				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
++				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
++				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
++			}
++		},
++	},
++	{
++		.reg = 0xc000,
++		.num_ports	= 1,
++		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
++		.port_cfgs	= {
++			[USB2PHY_PORT_HOST] = {
++				.phy_sus	= { 0x0008, 2, 2, 0, 1 },
++				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
++				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
++				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
++				.disfall_en	= { 0x0080, 6, 6, 0, 1 },
++				.disfall_st	= { 0x0084, 6, 6, 0, 1 },
++				.disfall_clr	= { 0x0088, 6, 6, 0, 1 },
++				.disrise_en	= { 0x0080, 5, 5, 0, 1 },
++				.disrise_st	= { 0x0084, 5, 5, 0, 1 },
++				.disrise_clr	= { 0x0088, 5, 5, 0, 1 },
++				.utmi_ls	= { 0x00c0, 10, 9, 0, 1 },
++			}
++		},
++	},
++	{ /* sentinel */ }
++};
++
+ static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
+ 	{
+ 		.reg = 0x100,
+@@ -1714,6 +1909,7 @@ static const struct of_device_id rockchi
+ 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
+ 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
+ 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
++	{ .compatible = "rockchip,rk3588-usb2phy", .data = &rk3588_phy_cfgs },
+ 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
+ 	{}
+ };
diff --git a/target/linux/rockchip/patches-6.1/257-phy-phy-rockchip-inno-usb2-add-reset-support.patch b/target/linux/rockchip/patches-6.1/257-phy-phy-rockchip-inno-usb2-add-reset-support.patch
new file mode 100644
index 00000000000..6c6930070ac
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/257-phy-phy-rockchip-inno-usb2-add-reset-support.patch
@@ -0,0 +1,96 @@
+From 6a4a6ef3b1d5217de9d9b51ae92008b0f628f165 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Apr 2023 20:23:14 +0200
+Subject: [PATCH 257/383] phy: phy-rockchip-inno-usb2: add reset support
+
+Add reset handling support, which is needed for proper
+operation with RK3588.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 38 +++++++++++++++++++
+ 1 file changed, 38 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -24,6 +24,7 @@
+ #include <linux/platform_device.h>
+ #include <linux/power_supply.h>
+ #include <linux/regmap.h>
++#include <linux/reset.h>
+ #include <linux/mfd/syscon.h>
+ #include <linux/usb/of.h>
+ #include <linux/usb/otg.h>
+@@ -223,6 +224,7 @@ struct rockchip_usb2phy_port {
+  * @clk: clock struct of phy input clk.
+  * @clk480m: clock struct of phy output clk.
+  * @clk480m_hw: clock struct of phy output clk management.
++ * @phy_reset: phy reset control.
+  * @chg_state: states involved in USB charger detection.
+  * @chg_type: USB charger types.
+  * @dcd_retries: The retry count used to track Data contact
+@@ -239,6 +241,7 @@ struct rockchip_usb2phy {
+ 	struct clk	*clk;
+ 	struct clk	*clk480m;
+ 	struct clk_hw	clk480m_hw;
++	struct reset_control	*phy_reset;
+ 	enum usb_chg_state	chg_state;
+ 	enum power_supply_type	chg_type;
+ 	u8			dcd_retries;
+@@ -280,6 +283,25 @@ static inline bool property_enabled(stru
+ 	return tmp != reg->disable;
+ }
+ 
++static int rockchip_usb2phy_reset(struct rockchip_usb2phy *rphy)
++{
++	int ret;
++
++	ret = reset_control_assert(rphy->phy_reset);
++	if (ret)
++		return ret;
++
++	udelay(10);
++
++	ret = reset_control_deassert(rphy->phy_reset);
++	if (ret)
++		return ret;
++
++	usleep_range(100, 200);
++
++	return 0;
++}
++
+ static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
+ {
+ 	struct rockchip_usb2phy *rphy =
+@@ -534,6 +556,18 @@ static int rockchip_usb2phy_power_on(str
+ 		return ret;
+ 	}
+ 
++	/*
++	 * For rk3588, it needs to reset phy when exit from
++	 * suspend mode with common_on_n 1'b1(aka REFCLK_LOGIC,
++	 * Bias, and PLL blocks are powered down) for lower
++	 * power consumption. If you don't want to reset phy,
++	 * please keep the common_on_n 1'b0 to set these blocks
++	 * remain powered.
++	 */
++	ret = rockchip_usb2phy_reset(rphy);
++	if (ret)
++		return ret;
++
+ 	/* waiting for the utmi_clk to become stable */
+ 	usleep_range(1500, 2000);
+ 
+@@ -1348,6 +1382,10 @@ static int rockchip_usb2phy_probe(struct
+ 		return -EINVAL;
+ 	}
+ 
++	rphy->phy_reset = devm_reset_control_get_optional(dev, "phy");
++	if (IS_ERR(rphy->phy_reset))
++		return PTR_ERR(rphy->phy_reset);
++
+ 	rphy->clk = of_clk_get_by_name(np, "phyclk");
+ 	if (!IS_ERR(rphy->clk)) {
+ 		clk_prepare_enable(rphy->clk);
diff --git a/target/linux/rockchip/patches-6.1/258-phy-phy-rockchip-inno-usb2-add-rk3588-phy-tuning-sup.patch b/target/linux/rockchip/patches-6.1/258-phy-phy-rockchip-inno-usb2-add-rk3588-phy-tuning-sup.patch
new file mode 100644
index 00000000000..fb62ef2c9ec
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/258-phy-phy-rockchip-inno-usb2-add-rk3588-phy-tuning-sup.patch
@@ -0,0 +1,148 @@
+From 63b3d76a9aebdcb0b09a446f4cbb2606050e2ecf Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Apr 2023 20:24:06 +0200
+Subject: [PATCH 258/383] phy: phy-rockchip-inno-usb2: add rk3588 phy tuning
+ support
+
+On RK3588 some registers need to be tweaked to support waking up from
+suspend when a USB device is plugged into a port from a suspended PHY.
+Without this change USB devices only work when they are plugged at
+boot time.
+
+Apart from that it optimizes settings to avoid devices toggling
+between fullspeed and highspeed mode.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 63 +++++++++++++++++++
+ 1 file changed, 63 insertions(+)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -33,6 +33,8 @@
+ #define SCHEDULE_DELAY		(60 * HZ)
+ #define OTG_SCHEDULE_DELAY	(2 * HZ)
+ 
++struct rockchip_usb2phy;
++
+ enum rockchip_usb2phy_port_id {
+ 	USB2PHY_PORT_OTG,
+ 	USB2PHY_PORT_HOST,
+@@ -163,6 +165,7 @@ struct rockchip_usb2phy_port_cfg {
+  * struct rockchip_usb2phy_cfg - usb-phy configuration.
+  * @reg: the address offset of grf for usb-phy config.
+  * @num_ports: specify how many ports that the phy has.
++ * @phy_tuning: phy default parameters tuning.
+  * @clkout_ctl: keep on/turn off output clk of phy.
+  * @port_cfgs: usb-phy port configurations.
+  * @chg_det: charger detection registers.
+@@ -170,6 +173,7 @@ struct rockchip_usb2phy_port_cfg {
+ struct rockchip_usb2phy_cfg {
+ 	unsigned int	reg;
+ 	unsigned int	num_ports;
++	int (*phy_tuning)(struct rockchip_usb2phy *rphy);
+ 	struct usb2phy_reg	clkout_ctl;
+ 	const struct rockchip_usb2phy_port_cfg	port_cfgs[USB2PHY_NUM_PORTS];
+ 	const struct rockchip_chg_det_reg	chg_det;
+@@ -1400,6 +1404,12 @@ static int rockchip_usb2phy_probe(struct
+ 		goto disable_clks;
+ 	}
+ 
++	if (rphy->phy_cfg->phy_tuning) {
++		ret = rphy->phy_cfg->phy_tuning(rphy);
++		if (ret)
++			goto disable_clks;
++	}
++
+ 	index = 0;
+ 	for_each_available_child_of_node(np, child_np) {
+ 		struct rockchip_usb2phy_port *rport = &rphy->ports[index];
+@@ -1468,6 +1478,55 @@ disable_clks:
+ 	return ret;
+ }
+ 
++static int rk3588_usb2phy_tuning(struct rockchip_usb2phy *rphy)
++{
++	int ret = 0;
++	bool usb3otg = false;
++	/*
++	 * utmi_termselect = 1'b1 (en FS terminations)
++	 * utmi_xcvrselect = 2'b01 (FS transceiver)
++	 */
++	int suspend_cfg = 0x14;
++
++	if (rphy->phy_cfg->reg == 0x0000 || rphy->phy_cfg->reg == 0x4000) {
++		/* USB2 config for USB3_0 and USB3_1 */
++		suspend_cfg |= 0x01; /* utmi_opmode = 2'b01 (no-driving) */
++		usb3otg = true;
++	} else if (rphy->phy_cfg->reg == 0x8000 || rphy->phy_cfg->reg == 0xc000) {
++		/* USB2 config for USB2_0 and USB2_1 */
++		suspend_cfg |= 0x00; /* utmi_opmode = 2'b00 (normal) */
++	} else {
++		return -EINVAL;
++	}
++
++	/* Deassert SIDDQ to power on analog block */
++	ret = regmap_write(rphy->grf, 0x0008, GENMASK(29, 29) | 0x0000);
++	if (ret)
++		return ret;
++
++	/* Do reset after exit IDDQ mode */
++	ret = rockchip_usb2phy_reset(rphy);
++	if (ret)
++		return ret;
++
++	/* suspend configuration */
++	ret |= regmap_write(rphy->grf, 0x000c, GENMASK(20, 16) | suspend_cfg);
++
++	/* HS DC Voltage Level Adjustment 4'b1001 : +5.89% */
++	ret |= regmap_write(rphy->grf, 0x0004, GENMASK(27, 24) | 0x0900);
++
++	/* HS Transmitter Pre-Emphasis Current Control 2'b10 : 2x */
++	ret |= regmap_write(rphy->grf, 0x0008, GENMASK(20, 19) | 0x0010);
++
++	if (!usb3otg)
++		return ret;
++
++	/* Pullup iddig pin for USB3_0 OTG mode */
++	ret |= regmap_write(rphy->grf, 0x0010, GENMASK(17, 16) | 0x0003);
++
++	return ret;
++}
++
+ static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
+ 	{
+ 		.reg = 0x760,
+@@ -1785,6 +1844,7 @@ static const struct rockchip_usb2phy_cfg
+ 	{
+ 		.reg = 0x0000,
+ 		.num_ports	= 1,
++		.phy_tuning	= rk3588_usb2phy_tuning,
+ 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+@@ -1821,6 +1881,7 @@ static const struct rockchip_usb2phy_cfg
+ 	{
+ 		.reg = 0x4000,
+ 		.num_ports	= 1,
++		.phy_tuning	= rk3588_usb2phy_tuning,
+ 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_OTG] = {
+@@ -1857,6 +1918,7 @@ static const struct rockchip_usb2phy_cfg
+ 	{
+ 		.reg = 0x8000,
+ 		.num_ports	= 1,
++		.phy_tuning	= rk3588_usb2phy_tuning,
+ 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_HOST] = {
+@@ -1877,6 +1939,7 @@ static const struct rockchip_usb2phy_cfg
+ 	{
+ 		.reg = 0xc000,
+ 		.num_ports	= 1,
++		.phy_tuning	= rk3588_usb2phy_tuning,
+ 		.clkout_ctl	= { 0x0000, 0, 0, 1, 0 },
+ 		.port_cfgs	= {
+ 			[USB2PHY_PORT_HOST] = {
diff --git a/target/linux/rockchip/patches-6.1/259-phy-phy-rockchip-inno-usb2-simplify-phy-clock-handli.patch b/target/linux/rockchip/patches-6.1/259-phy-phy-rockchip-inno-usb2-simplify-phy-clock-handli.patch
new file mode 100644
index 00000000000..a51ff74aaea
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/259-phy-phy-rockchip-inno-usb2-simplify-phy-clock-handli.patch
@@ -0,0 +1,61 @@
+From 8b4337415d34e2f6c46460b13bc38b97c09646fb Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Apr 2023 21:49:58 +0200
+Subject: [PATCH 259/383] phy: phy-rockchip-inno-usb2: simplify phy clock
+ handling
+
+Simplify phyclk handling by using devm_clk_get_optional_enabled to
+acquire and enable the optional clock. This also fixes a resource
+leak in driver remove path and adds proper error handling.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 19 ++++++-------------
+ 1 file changed, 6 insertions(+), 13 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1390,24 +1390,22 @@ static int rockchip_usb2phy_probe(struct
+ 	if (IS_ERR(rphy->phy_reset))
+ 		return PTR_ERR(rphy->phy_reset);
+ 
+-	rphy->clk = of_clk_get_by_name(np, "phyclk");
+-	if (!IS_ERR(rphy->clk)) {
+-		clk_prepare_enable(rphy->clk);
+-	} else {
+-		dev_info(&pdev->dev, "no phyclk specified\n");
+-		rphy->clk = NULL;
++	rphy->clk = devm_clk_get_optional_enabled(dev, "phyclk");
++	if (IS_ERR(rphy->clk)) {
++		return dev_err_probe(&pdev->dev, PTR_ERR(rphy->clk),
++				     "failed to get phyclk\n");
+ 	}
+ 
+ 	ret = rockchip_usb2phy_clk480m_register(rphy);
+ 	if (ret) {
+ 		dev_err(dev, "failed to register 480m output clock\n");
+-		goto disable_clks;
++		return ret;
+ 	}
+ 
+ 	if (rphy->phy_cfg->phy_tuning) {
+ 		ret = rphy->phy_cfg->phy_tuning(rphy);
+ 		if (ret)
+-			goto disable_clks;
++			return ret;
+ 	}
+ 
+ 	index = 0;
+@@ -1470,11 +1468,6 @@ next_child:
+ 
+ put_child:
+ 	of_node_put(child_np);
+-disable_clks:
+-	if (rphy->clk) {
+-		clk_disable_unprepare(rphy->clk);
+-		clk_put(rphy->clk);
+-	}
+ 	return ret;
+ }
+ 
diff --git a/target/linux/rockchip/patches-6.1/260-phy-phy-rockchip-inno-usb2-simplify-getting-match-da.patch b/target/linux/rockchip/patches-6.1/260-phy-phy-rockchip-inno-usb2-simplify-getting-match-da.patch
new file mode 100644
index 00000000000..3c8168ff0a5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/260-phy-phy-rockchip-inno-usb2-simplify-getting-match-da.patch
@@ -0,0 +1,55 @@
+From 03ca99979b142af0dcfbe07437bef37a81aff554 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Apr 2023 22:01:14 +0200
+Subject: [PATCH 260/383] phy: phy-rockchip-inno-usb2: simplify getting match
+ data
+
+Simplify the code by directly getting the match data via
+device_get_match_data() instead of open coding its functionality.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 12 ++++--------
+ 1 file changed, 4 insertions(+), 8 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1305,7 +1305,6 @@ static int rockchip_usb2phy_probe(struct
+ 	struct phy_provider *provider;
+ 	struct rockchip_usb2phy *rphy;
+ 	const struct rockchip_usb2phy_cfg *phy_cfgs;
+-	const struct of_device_id *match;
+ 	unsigned int reg;
+ 	int index, ret;
+ 
+@@ -1313,12 +1312,6 @@ static int rockchip_usb2phy_probe(struct
+ 	if (!rphy)
+ 		return -ENOMEM;
+ 
+-	match = of_match_device(dev->driver->of_match_table, dev);
+-	if (!match || !match->data) {
+-		dev_err(dev, "phy configs are not assigned!\n");
+-		return -EINVAL;
+-	}
+-
+ 	if (!dev->parent || !dev->parent->of_node) {
+ 		rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
+ 		if (IS_ERR(rphy->grf)) {
+@@ -1359,12 +1352,15 @@ static int rockchip_usb2phy_probe(struct
+ 	}
+ 
+ 	rphy->dev = dev;
+-	phy_cfgs = match->data;
++	phy_cfgs = device_get_match_data(dev);
+ 	rphy->chg_state = USB_CHG_STATE_UNDEFINED;
+ 	rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
+ 	rphy->irq = platform_get_irq_optional(pdev, 0);
+ 	platform_set_drvdata(pdev, rphy);
+ 
++	if (!phy_cfgs)
++		return dev_err_probe(dev, -EINVAL, "phy configs are not assigned!\n");
++
+ 	ret = rockchip_usb2phy_extcon_register(rphy);
+ 	if (ret)
+ 		return ret;
diff --git a/target/linux/rockchip/patches-6.1/261-phy-phy-rockchip-inno-usb2-improve-error-message.patch b/target/linux/rockchip/patches-6.1/261-phy-phy-rockchip-inno-usb2-improve-error-message.patch
new file mode 100644
index 00000000000..97c8388f633
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/261-phy-phy-rockchip-inno-usb2-improve-error-message.patch
@@ -0,0 +1,27 @@
+From 664873357f522876d1f821309ea2685786cb9c07 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 15 May 2023 18:40:42 +0200
+Subject: [PATCH 261/383] phy: phy-rockchip-inno-usb2: improve error message
+
+Printing the OF node is not useful, since we get the same information
+from the device context. Instead print the reg address, that could
+not be found.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/phy-rockchip-inno-usb2.c | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c
+@@ -1377,8 +1377,7 @@ static int rockchip_usb2phy_probe(struct
+ 	} while (phy_cfgs[index].reg);
+ 
+ 	if (!rphy->phy_cfg) {
+-		dev_err(dev, "no phy-config can be matched with %pOFn node\n",
+-			np);
++		dev_err(dev, "could not find phy config for reg=0x%08x\n", reg);
+ 		return -EINVAL;
+ 	}
+ 
diff --git a/target/linux/rockchip/patches-6.1/262-arm64-dts-rockchip-rk3588-add-USB2-support.patch b/target/linux/rockchip/patches-6.1/262-arm64-dts-rockchip-rk3588-add-USB2-support.patch
new file mode 100644
index 00000000000..a5184047efb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/262-arm64-dts-rockchip-rk3588-add-USB2-support.patch
@@ -0,0 +1,122 @@
+From c60f1b73585df7675e85454e151cd356b21fbfb1 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 12 Jan 2023 19:20:37 +0100
+Subject: [PATCH 262/383] arm64: dts: rockchip: rk3588: add USB2 support
+
+This adds USB2 (EHCI & OHCI) ports including the related PHYs
+and GRF modules to the rk3588(s) device tree.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 94 +++++++++++++++++++++++
+ 1 file changed, 94 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -839,11 +839,105 @@
+ 		};
+ 	};
+ 
++	usb_host0_ehci: usb@fc800000 {
++		compatible = "rockchip,rk3588-ehci", "generic-ehci";
++		reg = <0x0 0xfc800000 0x0 0x40000>;
++		interrupts = <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
++		phys = <&u2phy2_host>;
++		phy-names = "usb";
++		power-domains = <&power RK3588_PD_USB>;
++		status = "disabled";
++	};
++
++	usb_host0_ohci: usb@fc840000 {
++		compatible = "rockchip,rk3588-ohci", "generic-ohci";
++		reg = <0x0 0xfc840000 0x0 0x40000>;
++		interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST_ARB0>, <&cru ACLK_USB>, <&u2phy2>;
++		phys = <&u2phy2_host>;
++		phy-names = "usb";
++		power-domains = <&power RK3588_PD_USB>;
++		status = "disabled";
++	};
++
++	usb_host1_ehci: usb@fc880000 {
++		compatible = "rockchip,rk3588-ehci", "generic-ehci";
++		reg = <0x0 0xfc880000 0x0 0x40000>;
++		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
++		phys = <&u2phy3_host>;
++		phy-names = "usb";
++		power-domains = <&power RK3588_PD_USB>;
++		status = "disabled";
++	};
++
++	usb_host1_ohci: usb@fc8c0000 {
++		compatible = "rockchip,rk3588-ohci", "generic-ohci";
++		reg = <0x0 0xfc8c0000 0x0 0x40000>;
++		interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST_ARB1>, <&cru ACLK_USB>, <&u2phy3>;
++		phys = <&u2phy3_host>;
++		phy-names = "usb";
++		power-domains = <&power RK3588_PD_USB>;
++		status = "disabled";
++	};
++
+ 	sys_grf: syscon@fd58c000 {
+ 		compatible = "rockchip,rk3588-sys-grf", "syscon";
+ 		reg = <0x0 0xfd58c000 0x0 0x1000>;
+ 	};
+ 
++	usb2phy2_grf: syscon@fd5d8000 {
++		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
++		reg = <0x0 0xfd5d8000 0x0 0x4000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		u2phy2: usb2-phy@8000 {
++			compatible = "rockchip,rk3588-usb2phy";
++			reg = <0x8000 0x10>;
++			interrupts = <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH 0>;
++			resets = <&cru SRST_OTGPHY_U2_0>, <&cru SRST_P_USB2PHY_U2_0_GRF0>;
++			reset-names = "phy", "apb";
++			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
++			clock-names = "phyclk";
++			clock-output-names = "usb480m_phy2";
++			#clock-cells = <0>;
++			status = "disabled";
++
++			u2phy2_host: host-port {
++				#phy-cells = <0>;
++				status = "disabled";
++			};
++		};
++	};
++
++	usb2phy3_grf: syscon@fd5dc000 {
++		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
++		reg = <0x0 0xfd5dc000 0x0 0x4000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		u2phy3: usb2-phy@c000 {
++			compatible = "rockchip,rk3588-usb2phy";
++			reg = <0xc000 0x10>;
++			interrupts = <GIC_SPI 392 IRQ_TYPE_LEVEL_HIGH 0>;
++			resets = <&cru SRST_OTGPHY_U2_1>, <&cru SRST_P_USB2PHY_U2_1_GRF0>;
++			reset-names = "phy", "apb";
++			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
++			clock-names = "phyclk";
++			clock-output-names = "usb480m_phy3";
++			#clock-cells = <0>;
++			status = "disabled";
++
++			u2phy3_host: host-port {
++				#phy-cells = <0>;
++				status = "disabled";
++			};
++		};
++	};
++
+ 	bigcore0_grf: syscon@fd590000 {
+ 		compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
+ 		reg = <0x0 0xfd590000 0x0 0x100>;
diff --git a/target/linux/rockchip/patches-6.1/263-arm64-dts-rockchip-rk3588-evb1-add-USB2.patch b/target/linux/rockchip/patches-6.1/263-arm64-dts-rockchip-rk3588-evb1-add-USB2.patch
new file mode 100644
index 00000000000..8b6af30a486
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/263-arm64-dts-rockchip-rk3588-evb1-add-USB2.patch
@@ -0,0 +1,109 @@
+From dbb2f12cd75aaed870c4ba01b76e83bd3b9e992f Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 12 Jan 2023 19:23:27 +0100
+Subject: [PATCH 263/383] arm64: dts: rockchip: rk3588-evb1: add USB2
+
+Enable USB2 (EHCI and OCHI mode) support for the Rockchip RK3588 EVB1.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 76 +++++++++++++++++++
+ 1 file changed, 76 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -47,6 +47,40 @@
+ 		regulator-max-microvolt = <5000000>;
+ 		vin-supply = <&vcc12v_dcin>;
+ 	};
++
++	vcc5v0_usbdcin: vcc5v0-usbdcin {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usbdcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc12v_dcin>;
++	};
++
++	vcc5v0_usb: vcc5v0-usb {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usbdcin>;
++	};
++
++	vcc5v0_host: vcc5v0-host {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_host";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++		vin-supply = <&vcc5v0_usb>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++	};
+ };
+ 
+ &cpu_l0 {
+@@ -64,6 +98,40 @@
+ 	mem-supply = <&vdd_cpu_big1_mem_s0>;
+ };
+ 
++&u2phy2 {
++	status = "okay";
++};
++
++&u2phy3 {
++	status = "okay";
++};
++
++&u2phy2_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&u2phy3_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
+ &gmac0 {
+ 	clock_in_out = "output";
+ 	phy-handle = <&rgmii_phy>;
+@@ -886,3 +954,11 @@
+ 	pinctrl-0 = <&uart2m0_xfer>;
+ 	status = "okay";
+ };
++
++&pinctrl {
++	usb {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/264-arm64-dts-rockchip-rk3588-rock5b-add-USB2.patch b/target/linux/rockchip/patches-6.1/264-arm64-dts-rockchip-rk3588-rock5b-add-USB2.patch
new file mode 100644
index 00000000000..55e42e975f5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/264-arm64-dts-rockchip-rk3588-rock5b-add-USB2.patch
@@ -0,0 +1,96 @@
+From e8facd99ce2cbab3e91e236a662b567016630c28 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 30 Mar 2023 15:44:36 +0200
+Subject: [PATCH 264/383] arm64: dts: rockchip: rk3588-rock5b: add USB2
+
+Enable USB2 (EHCI and OCHI mode) support for the Radxa ROCK 5 Model B.
+This adds USB support on the M.2 Key E, both USB2 ports and USB2 mode
+for the upper USB3 port (the one further away from the PCB).
+
+The lower USB3 (closer to the PCB) and the USB-C ports use the RK3588
+USB TypeC host controller, which is not yet supported upstream.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 58 +++++++++++++++++++
+ 1 file changed, 58 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -3,6 +3,7 @@
+ /dts-v1/;
+ 
+ #include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
+ #include "rk3588.dtsi"
+ 
+ / {
+@@ -51,6 +52,20 @@
+ 		regulator-min-microvolt = <5000000>;
+ 		regulator-max-microvolt = <5000000>;
+ 	};
++
++	vcc5v0_host: vcc5v0-host-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_host";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		enable-active-high;
++		gpio = <&gpio4 RK_PB0 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host_en>;
++		vin-supply = <&vcc5v0_sys>;
++	};
+ };
+ 
+ &cpu_b0 {
+@@ -194,3 +209,46 @@
+ 	pinctrl-0 = <&uart2m0_xfer>;
+ 	status = "okay";
+ };
++
++&u2phy2_host {
++	/* connected to USB hub, which is powered by vcc5v0_sys */
++	phy-supply = <&vcc5v0_sys>;
++	status = "okay";
++};
++
++&u2phy3_host {
++	phy-supply = <&vcc5v0_host>;
++	status = "okay";
++};
++
++&u2phy2 {
++	status = "okay";
++};
++
++&u2phy3 {
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&pinctrl {
++	usb {
++		vcc5v0_host_en: vcc5v0-host-en {
++			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/265-dt-bindings-soc-rockchip-add-rk3588-pipe-phy-syscon.patch b/target/linux/rockchip/patches-6.1/265-dt-bindings-soc-rockchip-add-rk3588-pipe-phy-syscon.patch
new file mode 100644
index 00000000000..9649737ecc8
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/265-dt-bindings-soc-rockchip-add-rk3588-pipe-phy-syscon.patch
@@ -0,0 +1,26 @@
+From 4223f34930303bdc69366e3d5eea19b1eafa92cb Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 6 Apr 2023 16:41:49 +0200
+Subject: [PATCH 265/383] dt-bindings: soc: rockchip: add rk3588 pipe-phy
+ syscon
+
+The pipe-phy syscon is used by rockchip,rk3588-naneng-combphy,
+which in turn is the PHY for USB3, PCIe and SATA.
+
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/soc/rockchip/grf.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -24,6 +24,7 @@ properties:
+               - rockchip,rk3588-bigcore1-grf
+               - rockchip,rk3588-ioc
+               - rockchip,rk3588-php-grf
++              - rockchip,rk3588-pipe-phy-grf
+               - rockchip,rk3588-sys-grf
+               - rockchip,rk3588-pcie3-phy-grf
+               - rockchip,rk3588-pcie3-pipe-grf
diff --git a/target/linux/rockchip/patches-6.1/266-dt-bindings-ata-ahci-add-RK3588-AHCI-controller.patch b/target/linux/rockchip/patches-6.1/266-dt-bindings-ata-ahci-add-RK3588-AHCI-controller.patch
new file mode 100644
index 00000000000..8b169874dd6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/266-dt-bindings-ata-ahci-add-RK3588-AHCI-controller.patch
@@ -0,0 +1,57 @@
+From 05b552f4e516f259288f8948a7fe59c366cff95c Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 6 Apr 2023 17:13:12 +0200
+Subject: [PATCH 266/383] dt-bindings: ata: ahci: add RK3588 AHCI controller
+
+Just like RK3568, the RK3588 has a DWC based AHCI controller.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/ata/snps,dwc-ahci-common.yaml     | 8 ++++++--
+ Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml  | 6 ++++--
+ 2 files changed, 10 insertions(+), 4 deletions(-)
+
+--- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
++++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci-common.yaml
+@@ -31,11 +31,11 @@ properties:
+       PM-alive clock, RxOOB detection clock, embedded PHYs reference (Rx/Tx)
+       clock, etc.
+     minItems: 1
+-    maxItems: 4
++    maxItems: 6
+ 
+   clock-names:
+     minItems: 1
+-    maxItems: 4
++    maxItems: 6
+     items:
+       oneOf:
+         - description: Application APB/AHB/AXI BIU clock
+@@ -48,6 +48,10 @@ properties:
+           const: pmalive
+         - description: RxOOB detection clock
+           const: rxoob
++        - description: PHY Transmit Clock
++          const: asic
++        - description: PHY Receive Clock
++          const: rbc
+         - description: SATA Ports reference clock
+           const: ref
+ 
+--- a/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
++++ b/Documentation/devicetree/bindings/ata/snps,dwc-ahci.yaml
+@@ -23,9 +23,11 @@ properties:
+         const: snps,dwc-ahci
+       - description: SPEAr1340 AHCI SATA device
+         const: snps,spear-ahci
+-      - description: Rockhip RK3568 AHCI controller
++      - description: Rockhip AHCI controller
+         items:
+-          - const: rockchip,rk3568-dwc-ahci
++          - enum:
++              - rockchip,rk3568-dwc-ahci
++              - rockchip,rk3588-dwc-ahci
+           - const: snps,dwc-ahci
+ 
+ patternProperties:
diff --git a/target/linux/rockchip/patches-6.1/267-dt-bindings-phy-rockchip-rk3588-has-two-reset-lines.patch b/target/linux/rockchip/patches-6.1/267-dt-bindings-phy-rockchip-rk3588-has-two-reset-lines.patch
new file mode 100644
index 00000000000..0945fd041f6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/267-dt-bindings-phy-rockchip-rk3588-has-two-reset-lines.patch
@@ -0,0 +1,33 @@
+From ab488b7528353b9ae68d3d8d15d9d25636db0c39 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 6 Apr 2023 19:09:53 +0200
+Subject: [PATCH 267/383] dt-bindings: phy: rockchip: rk3588 has two reset
+ lines
+
+The RK3588 has two reset lines for the combphy. One for the
+APB interface and one for the actual PHY.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/phy/phy-rockchip-naneng-combphy.yaml         | 8 +++++++-
+ 1 file changed, 7 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
++++ b/Documentation/devicetree/bindings/phy/phy-rockchip-naneng-combphy.yaml
+@@ -31,8 +31,14 @@ properties:
+       - const: pipe
+ 
+   resets:
++    minItems: 1
++    maxItems: 2
++
++  reset-names:
++    minItems: 1
+     items:
+-      - description: exclusive PHY reset line
++      - const: phy
++      - const: apb
+ 
+   rockchip,enable-ssc:
+     type: boolean
diff --git a/target/linux/rockchip/patches-6.1/268-arm64-dts-rockchip-rk3588-add-combo-PHYs.patch b/target/linux/rockchip/patches-6.1/268-arm64-dts-rockchip-rk3588-add-combo-PHYs.patch
new file mode 100644
index 00000000000..8ffc1d9d07f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/268-arm64-dts-rockchip-rk3588-add-combo-PHYs.patch
@@ -0,0 +1,108 @@
+From c61ff1ea4f7533d6cc14f62e71ac5d4c7105c879 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 6 Apr 2023 16:54:11 +0200
+Subject: [PATCH 268/383] arm64: dts: rockchip: rk3588: add combo PHYs
+
+Add all 3 combo PHYs that can be found in RK3588.
+They are used for SATA, PCIe or USB3.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 21 ++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 42 +++++++++++++++++++++++
+ 2 files changed, 63 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -7,6 +7,11 @@
+ #include "rk3588-pinctrl.dtsi"
+ 
+ / {
++	pipe_phy1_grf: syscon@fd5c0000 {
++		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
++		reg = <0x0 0xfd5c0000 0x0 0x100>;
++	};
++
+ 	i2s8_8ch: i2s@fddc8000 {
+ 		compatible = "rockchip,rk3588-i2s-tdm";
+ 		reg = <0x0 0xfddc8000 0x0 0x1000>;
+@@ -123,4 +128,20 @@
+ 			queue1 {};
+ 		};
+ 	};
++
++	combphy1_ps: phy@fee10000 {
++		compatible = "rockchip,rk3588-naneng-combphy";
++		reg = <0x0 0xfee10000 0x0 0x100>;
++		#phy-cells = <1>;
++		clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
++			 <&cru PCLK_PHP_ROOT>;
++		clock-names = "ref", "apb", "pipe";
++		assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
++		assigned-clock-rates = <100000000>;
++		resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
++		reset-names = "phy", "apb";
++		rockchip,pipe-grf = <&php_grf>;
++		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
++		status = "disabled";
++	};
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -953,6 +953,16 @@
+ 		reg = <0x0 0xfd5b0000 0x0 0x1000>;
+ 	};
+ 
++	pipe_phy0_grf: syscon@fd5bc000 {
++		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
++		reg = <0x0 0xfd5bc000 0x0 0x100>;
++	};
++
++	pipe_phy2_grf: syscon@fd5c4000 {
++		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
++		reg = <0x0 0xfd5c4000 0x0 0x100>;
++	};
++
+ 	ioc: syscon@fd5f0000 {
+ 		compatible = "rockchip,rk3588-ioc", "syscon";
+ 		reg = <0x0 0xfd5f0000 0x0 0x10000>;
+@@ -2459,6 +2469,38 @@
+ 		#dma-cells = <1>;
+ 	};
+ 
++	combphy0_ps: phy@fee00000 {
++		compatible = "rockchip,rk3588-naneng-combphy";
++		reg = <0x0 0xfee00000 0x0 0x100>;
++		#phy-cells = <1>;
++		clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
++			 <&cru PCLK_PHP_ROOT>;
++		clock-names = "ref", "apb", "pipe";
++		assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
++		assigned-clock-rates = <100000000>;
++		resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
++		reset-names = "phy", "apb";
++		rockchip,pipe-grf = <&php_grf>;
++		rockchip,pipe-phy-grf = <&pipe_phy0_grf>;
++		status = "disabled";
++	};
++
++	combphy2_psu: phy@fee20000 {
++		compatible = "rockchip,rk3588-naneng-combphy";
++		reg = <0x0 0xfee20000 0x0 0x100>;
++		#phy-cells = <1>;
++		clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
++			 <&cru PCLK_PHP_ROOT>;
++		clock-names = "ref", "apb", "pipe";
++		assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
++		assigned-clock-rates = <100000000>;
++		resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
++		reset-names = "phy", "apb";
++		rockchip,pipe-grf = <&php_grf>;
++		rockchip,pipe-phy-grf = <&pipe_phy2_grf>;
++		status = "disabled";
++	};
++
+ 	system_sram2: sram@ff001000 {
+ 		compatible = "mmio-sram";
+ 		reg = <0x0 0xff001000 0x0 0xef000>;
diff --git a/target/linux/rockchip/patches-6.1/269-arm64-dts-rockchip-rk3588-add-SATA-support.patch b/target/linux/rockchip/patches-6.1/269-arm64-dts-rockchip-rk3588-add-SATA-support.patch
new file mode 100644
index 00000000000..dac991ac0f4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/269-arm64-dts-rockchip-rk3588-add-SATA-support.patch
@@ -0,0 +1,110 @@
+From 9db7df910c791511e3f4f1dd3d484fef41bc1e9b Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 6 Apr 2023 17:14:19 +0200
+Subject: [PATCH 269/383] arm64: dts: rockchip: rk3588: add SATA support
+
+Add all three SATA IP blocks to the RK3588 DT.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 23 +++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 48 +++++++++++++++++++++++
+ 2 files changed, 71 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -129,6 +129,29 @@
+ 		};
+ 	};
+ 
++	sata1: sata@fe220000 {
++		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
++		reg = <0 0xfe220000 0 0x1000>;
++		clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
++			 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
++			 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
++		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
++		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
++		ports-implemented = <0x1>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++
++		sata-port@0 {
++			reg = <0>;
++			hba-port-cap = <HBA_PORT_FBSCP>;
++			phys = <&combphy1_ps PHY_TYPE_SATA>;
++			phy-names = "sata-phy";
++			snps,rx-ts-max = <32>;
++			snps,tx-ts-max = <32>;
++		};
++	};
++
+ 	combphy1_ps: phy@fee10000 {
+ 		compatible = "rockchip,rk3588-naneng-combphy";
+ 		reg = <0x0 0xfee10000 0x0 0x100>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -9,6 +9,8 @@
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+ #include <dt-bindings/thermal/thermal.h>
++#include <dt-bindings/phy/phy.h>
++#include <dt-bindings/ata/ahci.h>
+ 
+ / {
+ 	compatible = "rockchip,rk3588";
+@@ -1726,6 +1728,52 @@
+ 		};
+ 	};
+ 
++	sata0: sata@fe210000 {
++		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
++		reg = <0 0xfe210000 0 0x1000>;
++		clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
++			 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
++			 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
++		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
++		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
++		ports-implemented = <0x1>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++
++		sata-port@0 {
++			reg = <0>;
++			hba-port-cap = <HBA_PORT_FBSCP>;
++			phys = <&combphy0_ps PHY_TYPE_SATA>;
++			phy-names = "sata-phy";
++			snps,rx-ts-max = <32>;
++			snps,tx-ts-max = <32>;
++		};
++	};
++
++	sata2: sata@fe230000 {
++		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
++		reg = <0 0xfe230000 0 0x1000>;
++		clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
++			 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
++			 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
++		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
++		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
++		ports-implemented = <0x1>;
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++
++		sata-port@0 {
++			reg = <0>;
++			hba-port-cap = <HBA_PORT_FBSCP>;
++			phys = <&combphy2_psu PHY_TYPE_SATA>;
++			phy-names = "sata-phy";
++			snps,rx-ts-max = <32>;
++			snps,tx-ts-max = <32>;
++		};
++	};
++
+ 	sdmmc: mmc@fe2c0000 {
+ 		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ 		reg = <0x0 0xfe2c0000 0x0 0x4000>;
diff --git a/target/linux/rockchip/patches-6.1/270-arm64-dts-rockchip-rk3588-evb1-add-SATA.patch b/target/linux/rockchip/patches-6.1/270-arm64-dts-rockchip-rk3588-evb1-add-SATA.patch
new file mode 100644
index 00000000000..fb14aed5fb5
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/270-arm64-dts-rockchip-rk3588-evb1-add-SATA.patch
@@ -0,0 +1,32 @@
+From af5ae0a087642e245546854cafda974a546def92 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 6 Apr 2023 17:32:02 +0200
+Subject: [PATCH 270/383] arm64: dts: rockchip: rk3588-evb1: add SATA
+
+Add support for the SATA0_0 port found on the RK3588 EVB1. The
+second port (SATA0_1) does not work, which matches the downstream
+behaviour.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts | 8 ++++++++
+ 1 file changed, 8 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -946,6 +946,14 @@
+ 	};
+ };
+ 
++&combphy0_ps {
++	status = "okay";
++};
++
++&sata0 {
++	status = "okay";
++};
++
+ &tsadc {
+ 	status = "okay";
+ };
diff --git a/target/linux/rockchip/patches-6.1/271-arm64-dts-rockchip-rk3588-add-PCIe2-support.patch b/target/linux/rockchip/patches-6.1/271-arm64-dts-rockchip-rk3588-add-PCIe2-support.patch
new file mode 100644
index 00000000000..238b9bfd1af
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/271-arm64-dts-rockchip-rk3588-add-PCIe2-support.patch
@@ -0,0 +1,201 @@
+From 1d0351c583664fa2a4fa34077ccdf3aa74645762 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 17 Apr 2023 20:03:08 +0200
+Subject: [PATCH 271/383] arm64: dts: rockchip: rk3588: add PCIe2 support
+
+Add all three PCIe2 IP blocks to the RK3588 DT. Note, that RK3588
+also has two PCIe3 IP blocks, that will be handled separately.
+
+TODO: FIXME: this is not compliant with the DT binding. There is
+one additional clock ("pipe"), one additional reset line, the
+interrupt-names do not match
+
+Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
+Co-developed-by: Kever Yang <kever.yang@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  |  54 +++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 108 ++++++++++++++++++++++
+ 2 files changed, 162 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -80,6 +80,60 @@
+ 		status = "disabled";
+ 	};
+ 
++	pcie2x1l0: pcie@fe170000 {
++		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		bus-range = <0x20 0x2f>;
++		clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
++			 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
++			 <&cru CLK_PCIE_AUX2>, <&cru CLK_PCIE1L0_PIPE>;
++		clock-names = "aclk_mst", "aclk_slv",
++			      "aclk_dbi", "pclk",
++			      "aux", "pipe";
++		device_type = "pci";
++		interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie2x1l0_intc 0>,
++				<0 0 0 2 &pcie2x1l0_intc 1>,
++				<0 0 0 3 &pcie2x1l0_intc 2>,
++				<0 0 0 4 &pcie2x1l0_intc 3>;
++		linux,pci-domain = <2>;
++		num-ib-windows = <8>;
++		num-ob-windows = <8>;
++		num-viewport = <4>;
++		max-link-speed = <2>;
++		msi-map = <0x2000 &its0 0x2000 0x1000>;
++		num-lanes = <1>;
++		phys = <&combphy1_ps PHY_TYPE_PCIE>;
++		phy-names = "pcie-phy";
++		power-domains = <&power RK3588_PD_PCIE>;
++		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
++			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
++			 <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
++		reg = <0xa 0x40800000 0x0 0x00400000>,
++		      <0x0 0xfe170000 0x0 0x00010000>,
++		      <0x0 0xf2000000 0x0 0x00100000>;
++		reg-names = "dbi", "apb", "config";
++		resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
++		reset-names = "pwr", "pipe";
++		status = "disabled";
++
++		pcie2x1l0_intc: legacy-interrupt-controller {
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
++		};
++	};
++
+ 	gmac0: ethernet@fe1b0000 {
+ 		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ 		reg = <0x0 0xfe1b0000 0x0 0x10000>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1679,6 +1679,114 @@
+ 		reg = <0x0 0xfdf82200 0x0 0x20>;
+ 	};
+ 
++	pcie2x1l1: pcie@fe180000 {
++		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		bus-range = <0x30 0x3f>;
++		clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
++			 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
++			 <&cru CLK_PCIE_AUX3>, <&cru CLK_PCIE1L1_PIPE>;
++		clock-names = "aclk_mst", "aclk_slv",
++			      "aclk_dbi", "pclk",
++			      "aux", "pipe";
++		device_type = "pci";
++		interrupts = <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie2x1l1_intc 0>,
++				<0 0 0 2 &pcie2x1l1_intc 1>,
++				<0 0 0 3 &pcie2x1l1_intc 2>,
++				<0 0 0 4 &pcie2x1l1_intc 3>;
++		linux,pci-domain = <3>;
++		num-ib-windows = <8>;
++		num-ob-windows = <8>;
++		num-viewport = <4>;
++		max-link-speed = <2>;
++		msi-map = <0x3000 &its0 0x3000 0x1000>;
++		num-lanes = <1>;
++		phys = <&combphy2_psu PHY_TYPE_PCIE>;
++		phy-names = "pcie-phy";
++		power-domains = <&power RK3588_PD_PCIE>;
++		ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
++			 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
++			 <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
++		reg = <0xa 0x40c00000 0x0 0x00400000>,
++		      <0x0 0xfe180000 0x0 0x00010000>,
++		      <0x0 0xf3000000 0x0 0x00100000>;
++		reg-names = "dbi", "apb", "config";
++		resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
++		reset-names = "pwr", "pipe";
++		status = "disabled";
++
++		pcie2x1l1_intc: legacy-interrupt-controller {
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 245 IRQ_TYPE_EDGE_RISING 0>;
++		};
++	};
++
++	pcie2x1l2: pcie@fe190000 {
++		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		bus-range = <0x40 0x4f>;
++		clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
++			 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
++			 <&cru CLK_PCIE_AUX4>, <&cru CLK_PCIE1L2_PIPE>;
++		clock-names = "aclk_mst", "aclk_slv",
++			      "aclk_dbi", "pclk",
++			      "aux", "pipe";
++		device_type = "pci";
++		interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie2x1l2_intc 0>,
++				<0 0 0 2 &pcie2x1l2_intc 1>,
++				<0 0 0 3 &pcie2x1l2_intc 2>,
++				<0 0 0 4 &pcie2x1l2_intc 3>;
++		linux,pci-domain = <4>;
++		num-ib-windows = <8>;
++		num-ob-windows = <8>;
++		num-viewport = <4>;
++		max-link-speed = <2>;
++		msi-map = <0x4000 &its0 0x4000 0x1000>;
++		num-lanes = <1>;
++		phys = <&combphy0_ps PHY_TYPE_PCIE>;
++		phy-names = "pcie-phy";
++		power-domains = <&power RK3588_PD_PCIE>;
++		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
++			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
++			 <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
++		reg = <0xa 0x41000000 0x0 0x00400000>,
++		      <0x0 0xfe190000 0x0 0x00010000>,
++		      <0x0 0xf4000000 0x0 0x00100000>;
++		reg-names = "dbi", "apb", "config";
++		resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
++		reset-names = "pwr", "pipe";
++		status = "disabled";
++
++		pcie2x1l2_intc: legacy-interrupt-controller {
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING 0>;
++		};
++	};
++
+ 	gmac1: ethernet@fe1c0000 {
+ 		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ 		reg = <0x0 0xfe1c0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-6.1/272-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-support.patch b/target/linux/rockchip/patches-6.1/272-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-support.patch
new file mode 100644
index 00000000000..4333bf6f0d9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/272-arm64-dts-rockchip-rk3588-evb1-add-PCIe2-support.patch
@@ -0,0 +1,74 @@
+From 97313a7cb397325c08f2a3f065094c7f84402084 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 17 Apr 2023 21:13:03 +0200
+Subject: [PATCH 272/383] arm64: dts: rockchip: rk3588-evb1: add PCIe2 support
+
+The RK3588 EVB1 has a second network card, which is connected
+via a PCIe2 block. This adds support for that.
+
+The patch also enables the first PCIe2 block. I did not test
+its functionality, but the board boots up properly.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-evb1-v10.dts     | 37 +++++++++++++++++++
+ 1 file changed, 37 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-evb1-v10.dts
+@@ -81,6 +81,26 @@
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&vcc5v0_host_en>;
+ 	};
++
++	pcie20_avdd0v85: pcie20-avdd0v85 {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie20_avdd0v85";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <850000>;
++		regulator-max-microvolt = <850000>;
++		vin-supply = <&avdd_0v85_s0>;
++	};
++
++	pcie20_avdd1v8: pcie20-avdd1v8 {
++		compatible = "regulator-fixed";
++		regulator-name = "pcie20_avdd1v8";
++		regulator-boot-on;
++		regulator-always-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		vin-supply = <&avcc_1v8_s0>;
++	};
+ };
+ 
+ &cpu_l0 {
+@@ -963,10 +983,27 @@
+ 	status = "okay";
+ };
+ 
++&pcie2x1l1 {
++	reset-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&rtl8111_isolate>;
++	status = "okay";
++};
++
+ &pinctrl {
++	rtl8111 {
++		rtl8111_isolate: rtl8111-isolate {
++			rockchip,pins = <1 RK_PA4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
+ 	usb {
+ 		vcc5v0_host_en: vcc5v0-host-en {
+ 			rockchip,pins = <4 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 	};
+ };
++
++&combphy2_psu {
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/273-arm64-dts-rockchip-Add-RK806-regulator-config.patch b/target/linux/rockchip/patches-6.1/273-arm64-dts-rockchip-Add-RK806-regulator-config.patch
new file mode 100644
index 00000000000..37c9c7ca6e7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/273-arm64-dts-rockchip-Add-RK806-regulator-config.patch
@@ -0,0 +1,197 @@
+From 17e58cbb2ad5d95f5d4c060e3e248287ecf83180 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Mon, 9 Jan 2023 16:37:23 +0000
+Subject: [PATCH 273/383] arm64: dts: rockchip: Add RK806 regulator config
+
+Add support for rk806 single configuration PMIC in Rock Pi 5A and 5B.
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3588-rk806-single.dtsi     | 179 ++++++++++++++++++
+ 1 file changed, 179 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rk806-single.dtsi
+@@ -0,0 +1,179 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ *
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++
++&spi2 {
++	status = "okay";
++	assigned-clocks = <&cru CLK_SPI2>;
++	assigned-clock-rates = <200000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++	num-cs = <1>;
++
++	rk806single: rk806single@0 {
++		compatible = "rockchip,rk806";
++		spi-max-frequency = <1000000>;
++		reg = <0x0>;
++
++		interrupt-parent = <&gpio0>;
++		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc5v0_sys>;
++		vcc6-supply = <&vcc5v0_sys>;
++		vcc7-supply = <&vcc5v0_sys>;
++		vcc8-supply = <&vcc5v0_sys>;
++		vcc9-supply = <&vcc5v0_sys>;
++		vcc10-supply = <&vcc5v0_sys>;
++		vcc11-supply = <&vcc_2v0_pldo_s3>;
++		vcc12-supply = <&vcc5v0_sys>;
++		vcc13-supply = <&vcc_1v1_nldo_s3>;
++		vcc14-supply = <&vcc_1v1_nldo_s3>;
++		vcca-supply = <&vcc5v0_sys>;
++
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		rk806_dvs1_null: dvs1-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs1_slp: dvs1-slp-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs1_rst: dvs1-rst-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs2_null: dvs2-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs2_slp: dvs2-slp-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs2_rst: dvs2-rst-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs2_dvs: dvs2-dvs-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun4";
++		};
++
++		rk806_dvs2_gpio: dvs2-gpio-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun5";
++		};
++
++		rk806_dvs3_null: dvs3-null-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs3_slp: dvs3-slp-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs3_rst: dvs3-rst-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs3_dvs: dvs3-dvs-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun4";
++		};
++
++		rk806_dvs3_gpio: dvs3-gpio-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun5";
++		};
++
++		regulators {
++			vcc_2v0_pldo_s3: dcdc-reg7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2000000>;
++				regulator-max-microvolt = <2000000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_2v0_pldo_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <2000000>;
++				};
++			};
++
++			vcc_3v3_s3: dcdc-reg8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc_3v3_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_3v3_s0: pldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_3v3_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd_s0: pldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vccio_sd_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/274-arm64-dts-rockchip-rock-5a-Add-SD-card-support.patch b/target/linux/rockchip/patches-6.1/274-arm64-dts-rockchip-rock-5a-Add-SD-card-support.patch
new file mode 100644
index 00000000000..6a930ac93b4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/274-arm64-dts-rockchip-rock-5a-Add-SD-card-support.patch
@@ -0,0 +1,80 @@
+From 32abca3fb87cf855d924680093e263dd5f173a61 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 13 Dec 2022 09:30:20 +0000
+Subject: [PATCH 274/383] arm64: dts: rockchip: rock-5a: Add SD card support
+
+Add sdmmc support for Rock Pi 5A board.
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588s-rock-5a.dts     | 46 +++++++++++++++++++
+ 1 file changed, 46 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-rock-5a.dts
+@@ -5,6 +5,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include "rk3588s.dtsi"
++#include "rk3588-rk806-single.dtsi"
+ 
+ / {
+ 	model = "Radxa ROCK 5 Model A";
+@@ -18,6 +19,35 @@
+ 	chosen {
+ 		stdout-path = "serial2:1500000n8";
+ 	};
++
++	vcc12v_dcin: vcc12v-dcin {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc12v_dcin>;
++	};
++
++	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v1_nldo_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
+ };
+ 
+ &gmac1 {
+@@ -71,3 +101,19 @@
+ 	pinctrl-0 = <&uart2m0_xfer>;
+ 	status = "okay";
+ };
++
++&sdmmc {
++	max-frequency = <150000000>;
++	no-sdio;
++	no-mmc;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3_s0>;
++	vqmmc-supply = <&vccio_sd_s0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/275-arm64-dts-rockchip-rock-5b-Add-SD-card-support.patch b/target/linux/rockchip/patches-6.1/275-arm64-dts-rockchip-rock-5b-Add-SD-card-support.patch
new file mode 100644
index 00000000000..f81956cc20f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/275-arm64-dts-rockchip-rock-5b-Add-SD-card-support.patch
@@ -0,0 +1,64 @@
+From 63b730d81733ad2643580ac1c2c7f238a53edf31 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 21 Feb 2023 16:17:19 +0000
+Subject: [PATCH 275/383] arm64: dts: rockchip: rock-5b: Add SD card support
+
+Add sdmmc node and it's regulators for sd card support
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 27 +++++++++++++++++++
+ 1 file changed, 27 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -5,6 +5,7 @@
+ #include <dt-bindings/gpio/gpio.h>
+ #include <dt-bindings/pinctrl/rockchip.h>
+ #include "rk3588.dtsi"
++#include "rk3588-rk806-single.dtsi"
+ 
+ / {
+ 	model = "Radxa ROCK 5 Model B";
+@@ -66,6 +67,16 @@
+ 		pinctrl-0 = <&vcc5v0_host_en>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
++	
++	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v1_nldo_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
+ };
+ 
+ &cpu_b0 {
+@@ -205,6 +216,22 @@
+ 	status = "okay";
+ };
+ 
++&sdmmc {
++	max-frequency = <200000000>;
++	no-sdio;
++	no-mmc;
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3_s3>;
++	vqmmc-supply = <&vccio_sd_s0>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
++	status = "okay";
++};
++
+ &uart2 {
+ 	pinctrl-0 = <&uart2m0_xfer>;
+ 	status = "okay";
diff --git a/target/linux/rockchip/patches-6.1/276-arm64-dts-rockchip-rk3588-Add-I2S-nodes.patch b/target/linux/rockchip/patches-6.1/276-arm64-dts-rockchip-rk3588-Add-I2S-nodes.patch
new file mode 100644
index 00000000000..1cc2c2d5991
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/276-arm64-dts-rockchip-rk3588-Add-I2S-nodes.patch
@@ -0,0 +1,27 @@
+From a45f75760dff9339819078d32fd76bc091df0a24 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Mon, 13 Mar 2023 11:53:05 +0200
+Subject: [PATCH 276/383] arm64: dts: rockchip: rk3588: Add I2S nodes
+
+In addition to the five I2S/PCM/TDM controllers and the two I2S/PCM
+controllers shared between the RK3588 and RK3588S SoCs, RK3588 contains
+another four I2S/PCM/TDM controllers.
+
+Add the DT nodes corresponding to the additional controllers.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -132,6 +132,7 @@
+ 			interrupt-parent = <&gic>;
+ 			interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
+ 		};
++
+ 	};
+ 
+ 	gmac0: ethernet@fe1b0000 {
diff --git a/target/linux/rockchip/patches-6.1/277-arm64-dts-rockchip-RK3588s-Enable-PCIE2.0x1-fe190000.patch b/target/linux/rockchip/patches-6.1/277-arm64-dts-rockchip-RK3588s-Enable-PCIE2.0x1-fe190000.patch
new file mode 100644
index 00000000000..ae109f35600
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/277-arm64-dts-rockchip-RK3588s-Enable-PCIE2.0x1-fe190000.patch
@@ -0,0 +1,48 @@
+From 2ac45c4f5a98cb76d6be3c8ddb872c99e4f5d4d9 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Tue, 28 Feb 2023 14:40:59 +0000
+Subject: [PATCH 277/383] arm64: dts: rockchip: RK3588s: Enable PCIE2.0x1
+ @fe190000
+
+Enable PCIE2.0x1 @fe190000 for RTL8125 network controller in
+Rock 5B board.
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3588-rock-5b.dts      | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts
+@@ -77,6 +77,15 @@
+ 		regulator-max-microvolt = <1100000>;
+ 		vin-supply = <&vcc5v0_sys>;
+ 	};
++
++	vcc3v3_pcie2x1l2: vcc3v3-pcie2x1l2 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc3v3_pcie2x1l2";
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		startup-delay-us = <5000>;
++		vin-supply = <&vcc_3v3_s3>;
++	};
+ };
+ 
+ &cpu_b0 {
+@@ -279,3 +288,14 @@
+ 		};
+ 	};
+ };
++
++&combphy0_ps {
++	status = "okay";
++};
++
++&pcie2x1l2 {
++	reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie2x1l2>;
++	status = "okay";
++
++};
diff --git a/target/linux/rockchip/patches-6.1/278-dt-bindings-PCI-tegra234-Add-ECAM-support.patch b/target/linux/rockchip/patches-6.1/278-dt-bindings-PCI-tegra234-Add-ECAM-support.patch
new file mode 100644
index 00000000000..9904dc9288f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/278-dt-bindings-PCI-tegra234-Add-ECAM-support.patch
@@ -0,0 +1,30 @@
+From f6147442e9cdd52d86a3d90ec22acc7b6ac45607 Mon Sep 17 00:00:00 2001
+From: Vidya Sagar <vidyas@nvidia.com>
+Date: Mon, 14 Nov 2022 15:53:32 +0000
+Subject: [PATCH 278/383] dt-bindings: PCI: tegra234: Add ECAM support
+
+Add support for ECAM aperture that is only supported for Tegra234
+devices.
+
+Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
+Co-developed-by: Jon Hunter <jonathanh@nvidia.com>
+Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
+Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Thierry Reding <treding@nvidia.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -35,7 +35,7 @@ properties:
+     maxItems: 5
+     items:
+       enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
+-              parf, cfg, link, ulreg, smu, mpu, apb, phy ]
++              parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
+ 
+   num-lanes:
+     description: |
diff --git a/target/linux/rockchip/patches-6.1/279-dt-bindings-PCI-dwc-Detach-common-RP-EP-DT-bindings.patch b/target/linux/rockchip/patches-6.1/279-dt-bindings-PCI-dwc-Detach-common-RP-EP-DT-bindings.patch
new file mode 100644
index 00000000000..410082c4592
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/279-dt-bindings-PCI-dwc-Detach-common-RP-EP-DT-bindings.patch
@@ -0,0 +1,82 @@
+From faee1117423b08c5dd21b4c53240363633b3a6ea Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:44 +0300
+Subject: [PATCH 279/383] dt-bindings: PCI: dwc: Detach common RP/EP DT
+ bindings
+
+Currently both DW PCIe Root Port and End-point DT bindings are defined as
+separate schemas. Carefully looking at them, at the hardware reference
+manuals and seeing there is a generic part of the driver used by the both
+RP and EP drivers we can greatly simplify the DW PCIe controller bindings
+by moving some of the properties into the common DT schema. It concerns
+the PERST GPIO control, number of lanes, number of iATU windows and CDM
+check properties. They will be defined in the snps,dw-pcie-common.yaml
+schema which will be referenced in the DW PCIe Root Port and End-point DT
+bindings in order to evaluate the common for both of these controllers
+properties. The rest of properties like reg{,-names}, clock{s,-names},
+reset{s,-names}, etc will be consolidate there in one of the next commits.
+
+Link: https://lore.kernel.org/r/20221113191301.5526-4-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 33 +------------------
+ 1 file changed, 1 insertion(+), 32 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -15,6 +15,7 @@ description: |
+ 
+ allOf:
+   - $ref: /schemas/pci/pci-bus.yaml#
++  - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
+ 
+ properties:
+   compatible:
+@@ -37,44 +38,12 @@ properties:
+       enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
+               parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
+ 
+-  num-lanes:
+-    description: |
+-      number of lanes to use (this property should be specified unless
+-      the link is brought already up in firmware)
+-    maximum: 16
+-
+-  reset-gpio:
+-    description: GPIO pin number of PERST# signal
+-    maxItems: 1
+-    deprecated: true
+-
+-  reset-gpios:
+-    description: GPIO controlled connection to PERST# signal
+-    maxItems: 1
+-
+   interrupts: true
+ 
+   interrupt-names: true
+ 
+   clocks: true
+ 
+-  snps,enable-cdm-check:
+-    type: boolean
+-    description: |
+-      This is a boolean property and if present enables
+-      automatic checking of CDM (Configuration Dependent Module) registers
+-      for data corruption. CDM registers include standard PCIe configuration
+-      space registers, Port Logic registers, DMA and iATU (internal Address
+-      Translation Unit) registers.
+-
+-  num-viewport:
+-    $ref: /schemas/types.yaml#/definitions/uint32
+-    maximum: 256
+-    description: |
+-      number of view ports configured in hardware. If a platform
+-      does not specify it, the driver autodetects it.
+-    deprecated: true
+-
+ additionalProperties: true
+ 
+ required:
diff --git a/target/linux/rockchip/patches-6.1/280-dt-bindings-PCI-dwc-Remove-bus-node-from-the-example.patch b/target/linux/rockchip/patches-6.1/280-dt-bindings-PCI-dwc-Remove-bus-node-from-the-example.patch
new file mode 100644
index 00000000000..ee2eba53965
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/280-dt-bindings-PCI-dwc-Remove-bus-node-from-the-example.patch
@@ -0,0 +1,60 @@
+From af471adc15b9bbd98a0ed7e005c920f55681bb80 Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:45 +0300
+Subject: [PATCH 280/383] dt-bindings: PCI: dwc: Remove bus node from the
+ examples
+
+It's absolutely redundant seeing by default each node is embedded into its
+own example-X node with address and size cells set to 1.
+
+Link: https://lore.kernel.org/r/20221113191301.5526-5-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 35 ++++++++++---------
+ 1 file changed, 18 insertions(+), 17 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -53,21 +53,22 @@ required:
+ 
+ examples:
+   - |
+-    bus {
+-      #address-cells = <1>;
+-      #size-cells = <1>;
+-      pcie@dfc00000 {
+-        device_type = "pci";
+-        compatible = "snps,dw-pcie";
+-        reg = <0xdfc00000 0x0001000>, /* IP registers */
+-              <0xd0000000 0x0002000>; /* Configuration space */
+-        reg-names = "dbi", "config";
+-        #address-cells = <3>;
+-        #size-cells = <2>;
+-        ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
+-                 <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
+-        interrupts = <25>, <24>;
+-        #interrupt-cells = <1>;
+-        num-lanes = <1>;
+-      };
++    pcie@dfc00000 {
++      compatible = "snps,dw-pcie";
++      device_type = "pci";
++      reg = <0xdfc00000 0x0001000>, /* IP registers */
++            <0xd0000000 0x0002000>; /* Configuration space */
++      reg-names = "dbi", "config";
++      #address-cells = <3>;
++      #size-cells = <2>;
++      ranges = <0x81000000 0 0x00000000 0xde000000 0 0x00010000>,
++               <0x82000000 0 0xd0400000 0xd0400000 0 0x0d000000>;
++      bus-range = <0x0 0xff>;
++
++      interrupts = <25>, <24>;
++      #interrupt-cells = <1>;
++
++      reset-gpios = <&port0 0 1>;
++
++      num-lanes = <1>;
+     };
diff --git a/target/linux/rockchip/patches-6.1/281-dt-bindings-PCI-dwc-Add-phys-phy-names-common-proper.patch b/target/linux/rockchip/patches-6.1/281-dt-bindings-PCI-dwc-Add-phys-phy-names-common-proper.patch
new file mode 100644
index 00000000000..07229d4e81d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/281-dt-bindings-PCI-dwc-Add-phys-phy-names-common-proper.patch
@@ -0,0 +1,37 @@
+From 8a436f7c0b87149e9fe16a10c3f7362afe9fd9d7 Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:46 +0300
+Subject: [PATCH 281/383] dt-bindings: PCI: dwc: Add phys/phy-names common
+ properties
+
+It's normal to have the DW PCIe RP/EP DT-nodes equipped with the explicit
+PHY phandle references. There can be up to 16 PHYs attach in accordance
+with the maximum number of supported PCIe lanes. Let's extend the common
+DW PCIe controller schema with the 'phys' and 'phy-names' properties
+definition. There two types PHY names are defined: preferred generic names
+'^pcie[0-9]+$' and non-preferred vendor-specific names
+'^pcie([0-9]+|-?phy[0-9]*)?$' so to match the names currently supported by
+the DW PCIe platform drivers ("pcie": meson; "pciephy": qcom, imx6;
+"pcie-phy": uniphier, rockchip, spear13xx; "pcie": intel-gw; "pcie-phy%d":
+keystone, dra7xx; "pcie": histb, etc).
+
+Link: https://lore.kernel.org/r/20221113191301.5526-6-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -70,5 +70,8 @@ examples:
+ 
+       reset-gpios = <&port0 0 1>;
+ 
++      phys = <&pcie_phy>;
++      phy-names = "pcie";
++
+       num-lanes = <1>;
+     };
diff --git a/target/linux/rockchip/patches-6.1/282-dt-bindings-PCI-dwc-Add-max-link-speed-common-proper.patch b/target/linux/rockchip/patches-6.1/282-dt-bindings-PCI-dwc-Add-max-link-speed-common-proper.patch
new file mode 100644
index 00000000000..761b49957e9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/282-dt-bindings-PCI-dwc-Add-max-link-speed-common-proper.patch
@@ -0,0 +1,31 @@
+From 13570bd7d59d75142960e6a6ded90f316e3ffd82 Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:47 +0300
+Subject: [PATCH 282/383] dt-bindings: PCI: dwc: Add max-link-speed common
+ property
+
+In accordance with [1] DW PCIe controllers support up to Gen5 link speed.
+Let's add the max-link-speed property upper bound to 5 then. The DT
+bindings of the particular devices are expected to setup more strict
+constraint on that parameter.
+
+[1] Synopsys DesignWare Cores PCI Express Controller Databook, Version
+5.40a, March 2019, p. 27
+
+Link: https://lore.kernel.org/r/20221113191301.5526-7-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -74,4 +74,5 @@ examples:
+       phy-names = "pcie";
+ 
+       num-lanes = <1>;
++      max-link-speed = <3>;
+     };
diff --git a/target/linux/rockchip/patches-6.1/283-dt-bindings-PCI-dwc-Apply-generic-schema-for-generic.patch b/target/linux/rockchip/patches-6.1/283-dt-bindings-PCI-dwc-Apply-generic-schema-for-generic.patch
new file mode 100644
index 00000000000..7fc6597a481
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/283-dt-bindings-PCI-dwc-Apply-generic-schema-for-generic.patch
@@ -0,0 +1,67 @@
+From f57d13d916a8665f03c62d053292870734912317 Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:48 +0300
+Subject: [PATCH 283/383] dt-bindings: PCI: dwc: Apply generic schema for
+ generic device only
+
+Having the generic compatible strings constraints with the 'any'+'generic
+string' semantic implicitly encourages either to add new DW PCIe-based
+DT-bindings with the generic compatible string attached or just forget
+about adding new DT-bindings since the corresponding DT-node will be
+evaluated anyway. Moreover having that semantic implemented in the
+generic DT-schema causes the DT-validation tool to apply the schema twice:
+first by implicit compatible-string-based selection and second by means of
+the 'allOf: [ $ref ]' statement. Let's fix all of that by dropping the
+compatible property constraints and selecting the generic DT-schema only
+for the purely generic DW PCIe DT-nodes. The later is required since there
+is a driver for such devices. (Though there are no such DT-nodes currently
+defined in the kernel DT sources.)
+
+Link: https://lore.kernel.org/r/20221113191301.5526-8-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml    | 16 ++++++++++------
+ 1 file changed, 10 insertions(+), 6 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -13,16 +13,20 @@ maintainers:
+ description: |
+   Synopsys DesignWare PCIe host controller
+ 
++# Please create a separate DT-schema for your DWC PCIe Root Port controller
++# and make sure it's assigned with the vendor-specific compatible string.
++select:
++  properties:
++    compatible:
++      const: snps,dw-pcie
++  required:
++    - compatible
++
+ allOf:
+   - $ref: /schemas/pci/pci-bus.yaml#
+   - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
+ 
+ properties:
+-  compatible:
+-    anyOf:
+-      - {}
+-      - const: snps,dw-pcie
+-
+   reg:
+     description: |
+       It should contain Data Bus Interface (dbi) and config registers for all
+@@ -47,9 +51,9 @@ properties:
+ additionalProperties: true
+ 
+ required:
++  - compatible
+   - reg
+   - reg-names
+-  - compatible
+ 
+ examples:
+   - |
diff --git a/target/linux/rockchip/patches-6.1/284-dt-bindings-PCI-dwc-Add-interrupts-interrupt-names-c.patch b/target/linux/rockchip/patches-6.1/284-dt-bindings-PCI-dwc-Add-interrupts-interrupt-names-c.patch
new file mode 100644
index 00000000000..cadddc7495e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/284-dt-bindings-PCI-dwc-Add-interrupts-interrupt-names-c.patch
@@ -0,0 +1,138 @@
+From ccd02ddfabc49a9c2e4979235c63323d878a9a8b Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:50 +0300
+Subject: [PATCH 284/383] dt-bindings: PCI: dwc: Add interrupts/interrupt-names
+ common properties
+
+Currently the 'interrupts' and 'interrupt-names' properties are defined
+being too generic to really describe any actual IRQ interface. Moreover
+the DW PCIe End-point devices are left with no IRQ signals. All of that
+can be fixed by adding the IRQ-related properties to the common DW PCIe
+DT-schemas in accordance with the hardware reference manual. The DW PCIe
+common DT-schema will contain the generic properties definitions with just
+a number of entries per property, while the DW PCIe RP/EP-specific schemas
+will have the particular number of items and the generic resource names
+listed.
+
+Note since there are DW PCI-based vendor-specific DT-bindings with the
+custom names assigned to the same IRQ resources we have no much choice but
+to add them to the generic DT-schemas in order to have the schemas being
+applicable for such devices. These names are marked as vendor-specific and
+should be avoided being used in new bindings in favor of the generic
+names.
+
+Link: https://lore.kernel.org/r/20221113191301.5526-10-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 90 ++++++++++++++++++-
+ 1 file changed, 87 insertions(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -42,9 +42,92 @@ properties:
+       enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
+               parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
+ 
+-  interrupts: true
+-
+-  interrupt-names: true
++  interrupts:
++    description:
++      DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
++      signal is supposed to be specified for the host controller.
++    minItems: 1
++    maxItems: 26
++
++  interrupt-names:
++    minItems: 1
++    maxItems: 26
++    items:
++      oneOf:
++        - description:
++            Controller request to read or write virtual product data
++            from/to the VPD capability registers.
++          const: vpd
++        - description:
++            Link Equalization Request flag is set in the Link Status 2
++            register (applicable if the corresponding IRQ is enabled in
++            the Link Control 3 register).
++          const: l_eq
++        - description:
++            Indicates that the eDMA Tx/Rx transfer is complete or that an
++            error has occurred on the corresponding channel. eDMA can have
++            eight Tx (Write) and Rx (Read) eDMA channels thus supporting up
++            to 16 IRQ signals all together. Write eDMA channels shall go
++            first in the ordered row as per default edma_int[*] bus setup.
++          pattern: '^dma([0-9]|1[0-5])?$'
++        - description:
++            PCIe protocol correctable error or a Data Path protection
++            correctable error is detected by the automotive/safety
++            feature.
++          const: sft_ce
++        - description:
++            Indicates that the internal safety mechanism has detected an
++            uncorrectable error.
++          const: sft_ue
++        - description:
++            Application-specific IRQ raised depending on the vendor-specific
++            events basis.
++          const: app
++        - description:
++            DSP AXI MSI Interrupt detected. It gets de-asserted when there is
++            no more MSI interrupt pending. The interrupt is relevant to the
++            iMSI-RX - Integrated MSI Receiver (AXI bridge).
++          const: msi
++        - description:
++            Legacy A/B/C/D interrupt signal. Basically it's triggered by
++            receiving a Assert_INT{A,B,C,D}/Desassert_INT{A,B,C,D} message
++            from the downstream device.
++          pattern: "^int(a|b|c|d)$"
++        - description:
++            Error condition detected and a flag is set in the Root Error Status
++            register of the AER capability. It's asserted when the RC
++            internally generated an error or an error message is received by
++            the RC.
++          const: aer
++        - description:
++            PME message is received by the port. That means having the PME
++            status bit set in the Root Status register (the event is
++            supposed to be unmasked in the Root Control register).
++          const: pme
++        - description:
++            Hot-plug event is detected. That is a bit has been set in the
++            Slot Status register and the corresponding event is enabled in
++            the Slot Control register.
++          const: hp
++        - description:
++            Link Autonomous Bandwidth Status flag has been set in the Link
++            Status register (the event is supposed to be unmasked in the
++            Link Control register).
++          const: bw_au
++        - description:
++            Bandwidth Management Status flag has been set in the Link
++            Status register (the event is supposed to be unmasked in the
++            Link Control register).
++          const: bw_mg
++        - description:
++            Vendor-specific IRQ names. Consider using the generic names above
++            for new bindings.
++          oneOf:
++            - description: See native "app" IRQ for details
++              enum: [ intr ]
++    allOf:
++      - contains:
++          const: msi
+ 
+   clocks: true
+ 
+@@ -70,6 +153,7 @@ examples:
+       bus-range = <0x0 0xff>;
+ 
+       interrupts = <25>, <24>;
++      interrupt-names = "msi", "hp";
+       #interrupt-cells = <1>;
+ 
+       reset-gpios = <&port0 0 1>;
diff --git a/target/linux/rockchip/patches-6.1/285-dt-bindings-PCI-dwc-Add-reg-reg-names-common-propert.patch b/target/linux/rockchip/patches-6.1/285-dt-bindings-PCI-dwc-Add-reg-reg-names-common-propert.patch
new file mode 100644
index 00000000000..0188eb7f3cc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/285-dt-bindings-PCI-dwc-Add-reg-reg-names-common-propert.patch
@@ -0,0 +1,132 @@
+From 792f6eade6f3baa914cc3c4f0beccaff16cb6bb5 Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:51 +0300
+Subject: [PATCH 285/383] dt-bindings: PCI: dwc: Add reg/reg-names common
+ properties
+
+Even though there is a more-or-less limited set of the CSR spaces can be
+defined for each DW PCIe controller the generic DT-schema currently
+doesn't specify much limitations on the reg-space names used for one or
+another range. In order to prevent the vendor-specific controller schemas
+further deviation from the generic interface let's fix that by introducing
+the reg-names definition in the common DW PCIe DT-schemas and preserving
+the generic "reg" and "reg-names" properties in there. New DW PCIe device
+DT-bindings are encouraged to use the generic set of the CSR spaces
+defined in the generic DW PCIe RP/EP DT-bindings, while the already
+available vendor-specific DT-bindings can still apple the common
+DT-schemas.
+
+Note the number of reg/reg-names items need to be changed in the DW PCIe
+EP DT-schema since aside with the "dbi" CSRs space these arrays can have
+"dbi2", "addr_space", "atu", etc ranges.
+
+Also note since there are DW PCIe-based vendor-specific DT-bindings with
+the custom names assigned to the same CSR resources we have no much choice
+but to add them to the generic DT-schemas in order to have the schemas
+being applicable for such devices. These names are marked as
+vendor-specific and should be avoided being used in new bindings in favor
+of the generic names.
+
+Link: https://lore.kernel.org/r/20221113191301.5526-11-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml | 78 +++++++++++++++++--
+ 1 file changed, 72 insertions(+), 6 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -28,10 +28,10 @@ allOf:
+ 
+ properties:
+   reg:
+-    description: |
+-      It should contain Data Bus Interface (dbi) and config registers for all
+-      versions.
+-      For designware core version >= 4.80, it may contain ATU address space.
++    description:
++      At least DBI reg-space and peripheral devices CFG-space outbound window
++      are required for the normal controller work. iATU memory IO region is
++      also required if the space is unrolled (IP-core version >= 4.80a).
+     minItems: 2
+     maxItems: 5
+ 
+@@ -39,8 +39,74 @@ properties:
+     minItems: 2
+     maxItems: 5
+     items:
+-      enum: [ dbi, dbi2, config, atu, atu_dma, app, appl, elbi, mgmt, ctrl,
+-              parf, cfg, link, ulreg, smu, mpu, apb, phy, ecam ]
++      oneOf:
++        - description:
++            Basic DWC PCIe controller configuration-space accessible over
++            the DBI interface. This memory space is either activated with
++            CDM/ELBI = 0 and CS2 = 0 or is a contiguous memory region
++            with all spaces. Note iATU/eDMA CSRs are indirectly accessible
++            via the PL viewports on the DWC PCIe controllers older than
++            v4.80a.
++          const: dbi
++        - description:
++            Shadow DWC PCIe config-space registers. This space is selected
++            by setting CDM/ELBI = 0 and CS2 = 1. This is an intermix of
++            the PCI-SIG PCIe CFG-space with the shadow registers for some
++            PCI Header space, PCI Standard and Extended Structures. It's
++            mainly relevant for the end-point controller configuration,
++            but still there are some shadow registers available for the
++            Root Port mode too.
++          const: dbi2
++        - description:
++            External Local Bus registers. It's an application-dependent
++            registers normally defined by the platform engineers. The space
++            can be selected by setting CDM/ELBI = 1 and CS2 = 0 wires or can
++            be accessed over some platform-specific means (for instance
++            as a part of a system controller).
++          enum: [ elbi, app ]
++        - description:
++            iATU/eDMA registers common for all device functions. It's an
++            unrolled memory space with the internal Address Translation
++            Unit and Enhanced DMA, which is selected by setting CDM/ELBI = 1
++            and CS2 = 1. For IP-core releases prior v4.80a, these registers
++            have been programmed via an indirect addressing scheme using a
++            set of viewport CSRs mapped into the PL space. Note iATU is
++            normally mapped to the 0x0 address of this region, while eDMA
++            is available at 0x80000 base address.
++          const: atu
++        - description:
++            Platform-specific eDMA registers. Some platforms may have eDMA
++            CSRs mapped in a non-standard base address. The registers offset
++            can be changed or the MS/LS-bits of the address can be attached
++            in an additional RTL block before the MEM-IO transactions reach
++            the DW PCIe slave interface.
++          const: dma
++        - description:
++            PHY/PCS configuration registers. Some platforms can have the
++            PCS and PHY CSRs accessible over a dedicated memory mapped
++            region, but mainly these registers are indirectly accessible
++            either by means of the embedded PHY viewport schema or by some
++            platform-specific method.
++          const: phy
++        - description:
++            Outbound iATU-capable memory-region which will be used to access
++            the peripheral PCIe devices configuration space.
++          const: config
++        - description:
++            Vendor-specific CSR names. Consider using the generic names above
++            for new bindings.
++          oneOf:
++            - description: See native 'elbi/app' CSR region for details.
++              enum: [ apb, mgmt, link, ulreg, appl ]
++            - description: See native 'atu' CSR region for details.
++              enum: [ atu_dma ]
++            - description: Syscon-related CSR regions.
++              enum: [ smu, mpu ]
++    allOf:
++      - contains:
++          const: dbi
++      - contains:
++          const: config
+ 
+   interrupts:
+     description:
diff --git a/target/linux/rockchip/patches-6.1/286-dt-bindings-PCI-dwc-Add-clocks-resets-common-propert.patch b/target/linux/rockchip/patches-6.1/286-dt-bindings-PCI-dwc-Add-clocks-resets-common-propert.patch
new file mode 100644
index 00000000000..e1fd4655843
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/286-dt-bindings-PCI-dwc-Add-clocks-resets-common-propert.patch
@@ -0,0 +1,44 @@
+From 20fe75b3d5c10e48181257b6d86506a375fce5dc Mon Sep 17 00:00:00 2001
+From: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Date: Sun, 13 Nov 2022 22:12:52 +0300
+Subject: [PATCH 286/383] dt-bindings: PCI: dwc: Add clocks/resets common
+ properties
+
+DW PCIe RP/EP reference manuals explicit define all the clocks and reset
+requirements in [1] and [2]. Seeing the DW PCIe vendor-specific
+DT-bindings have already started assigning random names to the same set of
+the clocks and resets lines, let's define a generic names sets and add
+them to the DW PCIe common DT-schema.
+
+Note since there are DW PCI-based vendor-specific DT-bindings with the
+custom names assigned to the same clocks and resets resources we have no
+much choice but to add them to the generic DT-schemas in order to have the
+schemas being applicable for such devices. These names are marked as
+vendor-specific and should be avoided being used in new bindings in favor
+of the generic names.
+
+[1] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
+Root Port, Version 5.40a, March 2019, p.55 - 78.
+[2] Synopsys DesignWare Cores PCI Express Controller Databook - DWC PCIe
+Endpoint, Version 5.40a, March 2019, p.58 - 81.
+
+Link: https://lore.kernel.org/r/20221113191301.5526-12-Sergey.Semin@baikalelectronics.ru
+Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
+Signed-off-by: Lorenzo Pieralisi <lpieralisi@kernel.org>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -195,8 +195,6 @@ properties:
+       - contains:
+           const: msi
+ 
+-  clocks: true
+-
+ additionalProperties: true
+ 
+ required:
diff --git a/target/linux/rockchip/patches-6.1/287-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch b/target/linux/rockchip/patches-6.1/287-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch
new file mode 100644
index 00000000000..25f0fd73543
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/287-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch
@@ -0,0 +1,90 @@
+From 0fd0248e890af947cc41be8e147278b28825014b Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 19 Apr 2023 14:57:14 +0200
+Subject: [PATCH 287/383] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names
+ issue
+
+The RK356x (and RK3588) have 5 ganged interrupts. For example the
+"legacy" interrupt combines "inta/intb/intc/intd" with a register
+providing the details.
+
+Currently the binding is not specifying these interrupts resulting
+in a bunch of errors for all rk356x boards using PCIe.
+
+Fix this by specifying the interrupts and add them to the example
+to prevent regressions.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/pci/rockchip-dw-pcie.yaml         | 18 ++++++++++++++++++
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml  | 15 ++++++++++++++-
+ 2 files changed, 32 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -56,6 +56,17 @@ properties:
+       - const: pclk
+       - const: aux
+ 
++  interrupts:
++    maxItems: 5
++
++  interrupt-names:
++    items:
++      - const: sys
++      - const: pmc
++      - const: msg
++      - const: legacy
++      - const: err
++
+   msi-map: true
+ 
+   num-lanes: true
+@@ -98,6 +109,7 @@ unevaluatedProperties: false
+ 
+ examples:
+   - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
+ 
+     bus {
+         #address-cells = <2>;
+@@ -117,6 +129,12 @@ examples:
+                           "aclk_dbi", "pclk",
+                           "aux";
+             device_type = "pci";
++            interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
++                         <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>,
++                         <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
++                         <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>,
++                         <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
++            interrupt-names = "sys", "pmc", "msg", "legacy", "err";
+             linux,pci-domain = <2>;
+             max-link-speed = <2>;
+             msi-map = <0x2000 &its 0x2000 0x1000>;
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -191,9 +191,22 @@ properties:
+           oneOf:
+             - description: See native "app" IRQ for details
+               enum: [ intr ]
++        - description: Combined Legacy A/B/C/D interrupt signal.
++          const: legacy
++        - description: Combined System interrupt signal.
++          const: sys
++        - description: Combined Power Management interrupt signal.
++          const: pmc
++        - description: Combined Message Received interrupt signal.
++          const: msg
++        - description: Combined Error interrupt signal.
++          const: err
++
+     allOf:
+       - contains:
+-          const: msi
++          enum:
++            - msi
++            - msg
+ 
+ additionalProperties: true
+ 
diff --git a/target/linux/rockchip/patches-6.1/288-dt-bindings-PCI-dwc-rockchip-Add-missing-legacy-inte.patch b/target/linux/rockchip/patches-6.1/288-dt-bindings-PCI-dwc-rockchip-Add-missing-legacy-inte.patch
new file mode 100644
index 00000000000..4cb7aeff8d7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/288-dt-bindings-PCI-dwc-rockchip-Add-missing-legacy-inte.patch
@@ -0,0 +1,58 @@
+From 167e9d4eb601b8e9423c505f23639e56098a329c Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 19 Apr 2023 18:27:12 +0200
+Subject: [PATCH 288/383] dt-bindings: PCI: dwc: rockchip: Add missing
+ legacy-interrupt-controller
+
+Rockchip RK356x and RK3588 handle legacy interrupts via a ganged
+interrupts. The RK356x DT implements this via a sub-node named
+"legacy-interrupt-controller", just like a couple of other PCIe
+implementations. This adds proper documentation for this and updates
+the example to avoid regressions.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/pci/rockchip-dw-pcie.yaml        | 24 +++++++++++++++++++
+ 1 file changed, 24 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -67,6 +67,22 @@ properties:
+       - const: legacy
+       - const: err
+ 
++  legacy-interrupt-controller:
++    description: Interrupt controller node for handling legacy PCI interrupts.
++    type: object
++    properties:
++      "#address-cells":
++        const: 0
++
++      "#interrupt-cells":
++        const: 1
++
++      "interrupt-controller": true
++
++      interrupts:
++        items:
++          - description: combined legacy interrupt
++
+   msi-map: true
+ 
+   num-lanes: true
+@@ -148,6 +164,14 @@ examples:
+             reset-names = "pipe";
+             #address-cells = <3>;
+             #size-cells = <2>;
++
++            legacy-interrupt-controller {
++                interrupt-controller;
++                #address-cells = <0>;
++                #interrupt-cells = <1>;
++                interrupt-parent = <&gic>;
++                interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
++            };
+         };
+     };
+ ...
diff --git a/target/linux/rockchip/patches-6.1/289-dt-bindings-PCI-dwc-rockchip-Update-for-RK3588.patch b/target/linux/rockchip/patches-6.1/289-dt-bindings-PCI-dwc-rockchip-Update-for-RK3588.patch
new file mode 100644
index 00000000000..3cc7833eda8
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/289-dt-bindings-PCI-dwc-rockchip-Update-for-RK3588.patch
@@ -0,0 +1,64 @@
+From c45b5461951611521cf20008d0ae57b4ece400c3 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 19 Apr 2023 20:49:46 +0200
+Subject: [PATCH 289/383] dt-bindings: PCI: dwc: rockchip: Update for RK3588
+
+The PCIe 2.0 controllers on RK3588 need one additional clock,
+one additional reset line and one for ranges entry.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/pci/rockchip-dw-pcie.yaml           | 16 +++++++++++++---
+ 1 file changed, 13 insertions(+), 3 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -41,20 +41,24 @@ properties:
+       - const: config
+ 
+   clocks:
++    minItems: 5
+     items:
+       - description: AHB clock for PCIe master
+       - description: AHB clock for PCIe slave
+       - description: AHB clock for PCIe dbi
+       - description: APB clock for PCIe
+       - description: Auxiliary clock for PCIe
++      - description: PIPE clock
+ 
+   clock-names:
++    minItems: 5
+     items:
+       - const: aclk_mst
+       - const: aclk_slv
+       - const: aclk_dbi
+       - const: pclk
+       - const: aux
++      - const: pipe
+ 
+   interrupts:
+     maxItems: 5
+@@ -97,13 +101,19 @@ properties:
+     maxItems: 1
+ 
+   ranges:
+-    maxItems: 2
++    minItems: 2
++    maxItems: 3
+ 
+   resets:
+-    maxItems: 1
++    minItems: 1
++    maxItems: 2
+ 
+   reset-names:
+-    const: pipe
++    oneOf:
++      - const: pipe
++      - items:
++          - const: pwr
++          - const: pipe
+ 
+   vpcie3v3-supply: true
+ 
diff --git a/target/linux/rockchip/patches-6.1/290-arm64-defconfig-Enable-ethernet-for-Rock-5B.patch b/target/linux/rockchip/patches-6.1/290-arm64-defconfig-Enable-ethernet-for-Rock-5B.patch
new file mode 100644
index 00000000000..4154d6a64a7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/290-arm64-defconfig-Enable-ethernet-for-Rock-5B.patch
@@ -0,0 +1,29 @@
+From f00922dce0f289208c65e175c8c47e1ceb5b3216 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Thu, 23 Mar 2023 12:27:19 +0000
+Subject: [PATCH 290/383] arm64: defconfig: Enable ethernet for Rock 5B
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -230,6 +230,7 @@ CONFIG_PCIE_ALTERA=y
+ CONFIG_PCIE_ALTERA_MSI=y
+ CONFIG_PCI_HOST_THUNDER_PEM=y
+ CONFIG_PCI_HOST_THUNDER_ECAM=y
++CONFIG_PCIE_ROCKCHIP_DW_HOST=y
+ CONFIG_PCIE_ROCKCHIP_HOST=m
+ CONFIG_PCIE_BRCMSTB=m
+ CONFIG_PCI_IMX6=y
+@@ -1243,6 +1244,7 @@ CONFIG_PHY_RCAR_GEN3_PCIE=y
+ CONFIG_PHY_RCAR_GEN3_USB2=y
+ CONFIG_PHY_RCAR_GEN3_USB3=m
+ CONFIG_PHY_ROCKCHIP_EMMC=y
++CONFIG_PHY_ROCKCHIP_NANENG_COMBO_PHY=y
+ CONFIG_PHY_ROCKCHIP_INNO_HDMI=m
+ CONFIG_PHY_ROCKCHIP_INNO_USB2=y
+ CONFIG_PHY_ROCKCHIP_INNO_DSIDPHY=m
diff --git a/target/linux/rockchip/patches-6.1/291-arm64-defconfig-Enable-Sound-Card-for-Rock-5B.patch b/target/linux/rockchip/patches-6.1/291-arm64-defconfig-Enable-Sound-Card-for-Rock-5B.patch
new file mode 100644
index 00000000000..180a6b2847f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/291-arm64-defconfig-Enable-Sound-Card-for-Rock-5B.patch
@@ -0,0 +1,29 @@
+From 55166fa47b3cc85efecbebe7b078eb4752467ad5 Mon Sep 17 00:00:00 2001
+From: Lucas Tanure <lucas.tanure@collabora.com>
+Date: Thu, 23 Mar 2023 12:37:12 +0000
+Subject: [PATCH 291/383] arm64: defconfig: Enable Sound Card for Rock 5B
+
+Signed-off-by: Lucas Tanure <lucas.tanure@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/configs/defconfig | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -813,6 +813,7 @@ CONFIG_SND_SOC_SM8250=m
+ CONFIG_SND_SOC_SC7180=m
+ CONFIG_SND_SOC_SC7280=m
+ CONFIG_SND_SOC_ROCKCHIP=m
++CONFIG_SND_SOC_ROCKCHIP_I2S_TDM=m
+ CONFIG_SND_SOC_ROCKCHIP_SPDIF=m
+ CONFIG_SND_SOC_ROCKCHIP_RT5645=m
+ CONFIG_SND_SOC_RK3399_GRU_SOUND=m
+@@ -841,6 +842,7 @@ CONFIG_SND_SOC_TEGRA_AUDIO_GRAPH_CARD=m
+ CONFIG_SND_SOC_AK4613=m
+ CONFIG_SND_SOC_ES7134=m
+ CONFIG_SND_SOC_ES7241=m
++CONFIG_SND_SOC_ES8316=m
+ CONFIG_SND_SOC_GTM601=m
+ CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m
+ CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m
diff --git a/target/linux/rockchip/patches-6.1/292-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch b/target/linux/rockchip/patches-6.1/292-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch
new file mode 100644
index 00000000000..8d0d6973477
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/292-arm64-dts-rockchip-rk3588s-Add-USBDP-phy-nodes.patch
@@ -0,0 +1,197 @@
+From 8c0b8cebeff2773880e5e5fae175ed300e7cc031 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 25 Apr 2023 17:49:04 +0200
+Subject: [PATCH 292/383] arm64: dts: rockchip: rk3588s: Add USBDP phy nodes
+
+Add both USB3-Displayport PHYs from RK3588.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 63 +++++++++++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 74 +++++++++++++++++++++++
+ 2 files changed, 137 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -12,6 +12,38 @@
+ 		reg = <0x0 0xfd5c0000 0x0 0x100>;
+ 	};
+ 
++	usbdpphy1_grf: syscon@fd5cc000 {
++		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
++		reg = <0x0 0xfd5cc000 0x0 0x4000>;
++	};
++
++	usb2phy1_grf: syscon@fd5d4000 {
++		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
++			     "simple-mfd";
++		reg = <0x0 0xfd5d4000 0x0 0x4000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		u2phy1: usb2-phy@4000 {
++			compatible = "rockchip,rk3588-usb2phy";
++			reg = <0x4000 0x10>;
++			interrupts = <GIC_SPI 394 IRQ_TYPE_LEVEL_HIGH 0>;
++			resets = <&cru SRST_OTGPHY_U3_1>, <&cru SRST_P_USB2PHY_U3_1_GRF0>;
++			reset-names = "phy", "apb";
++			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
++			clock-names = "phyclk";
++			clock-output-names = "usb480m_phy1";
++			#clock-cells = <0>;
++			rockchip,usbctrl-grf = <&usb_grf>;
++			status = "disabled";
++
++			u2phy1_otg: otg-port {
++				#phy-cells = <0>;
++				status = "disabled";
++			};
++		};
++	};
++
+ 	i2s8_8ch: i2s@fddc8000 {
+ 		compatible = "rockchip,rk3588-i2s-tdm";
+ 		reg = <0x0 0xfddc8000 0x0 0x1000>;
+@@ -207,6 +239,37 @@
+ 		};
+ 	};
+ 
++	usbdp_phy1: phy@fed90000 {
++		compatible = "rockchip,rk3588-usbdp-phy";
++		reg = <0x0 0xfed90000 0x0 0x10000>;
++		rockchip,u2phy-grf = <&usb2phy1_grf>;
++		rockchip,usb-grf = <&usb_grf>;
++		rockchip,usbdpphy-grf = <&usbdpphy1_grf>;
++		rockchip,vo-grf = <&vo0_grf>;
++		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
++			 <&cru CLK_USBDP_PHY1_IMMORTAL>,
++			 <&cru PCLK_USBDPPHY1>,
++			 <&u2phy1>;
++		clock-names = "refclk", "immortal", "pclk", "utmi";
++		resets = <&cru SRST_USBDP_COMBO_PHY1_INIT>,
++			 <&cru SRST_USBDP_COMBO_PHY1_CMN>,
++			 <&cru SRST_USBDP_COMBO_PHY1_LANE>,
++			 <&cru SRST_USBDP_COMBO_PHY1_PCS>,
++			 <&cru SRST_P_USBDPPHY1>;
++		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
++		status = "disabled";
++
++		usbdp_phy1_dp: dp-port {
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
++		usbdp_phy1_u3: usb3-port {
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++	};
++
+ 	combphy1_ps: phy@fee10000 {
+ 		compatible = "rockchip,rk3588-naneng-combphy";
+ 		reg = <0x0 0xfee10000 0x0 0x100>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -890,6 +890,33 @@
+ 		reg = <0x0 0xfd58c000 0x0 0x1000>;
+ 	};
+ 
++	usb2phy0_grf: syscon@fd5d0000 {
++		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
++			     "simple-mfd";
++		reg = <0x0 0xfd5d0000 0x0 0x4000>;
++		#address-cells = <1>;
++		#size-cells = <1>;
++
++		u2phy0: usb2-phy@0 {
++			compatible = "rockchip,rk3588-usb2phy";
++			reg = <0x0 0x10>;
++			interrupts = <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH 0>;
++			resets = <&cru SRST_OTGPHY_U3_0>, <&cru SRST_P_USB2PHY_U3_0_GRF0>;
++			reset-names = "phy", "apb";
++			clocks = <&cru CLK_USB2PHY_HDPTXRXPHY_REF>;
++			clock-names = "phyclk";
++			clock-output-names = "usb480m_phy0";
++			#clock-cells = <0>;
++			rockchip,usbctrl-grf = <&usb_grf>;
++			status = "disabled";
++
++			u2phy0_otg: otg-port {
++				#phy-cells = <0>;
++				status = "disabled";
++			};
++		};
++	};
++
+ 	usb2phy2_grf: syscon@fd5d8000 {
+ 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ 		reg = <0x0 0xfd5d8000 0x0 0x4000>;
+@@ -915,6 +942,17 @@
+ 		};
+ 	};
+ 
++	vo0_grf: syscon@fd5a6000 {
++		compatible = "rockchip,rk3588-vo-grf", "syscon";
++		reg = <0x0 0xfd5a6000 0x0 0x2000>;
++		clocks = <&cru PCLK_VO0GRF>;
++	};
++
++	usb_grf: syscon@fd5ac000 {
++		compatible = "rockchip,rk3588-usb-grf", "syscon";
++		reg = <0x0 0xfd5ac000 0x0 0x4000>;
++	};
++
+ 	usb2phy3_grf: syscon@fd5dc000 {
+ 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon", "simple-mfd";
+ 		reg = <0x0 0xfd5dc000 0x0 0x4000>;
+@@ -965,6 +1003,11 @@
+ 		reg = <0x0 0xfd5c4000 0x0 0x100>;
+ 	};
+ 
++	usbdpphy0_grf: syscon@fd5c8000 {
++		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
++		reg = <0x0 0xfd5c8000 0x0 0x4000>;
++	};
++
+ 	ioc: syscon@fd5f0000 {
+ 		compatible = "rockchip,rk3588-ioc", "syscon";
+ 		reg = <0x0 0xfd5f0000 0x0 0x10000>;
+@@ -2625,6 +2668,37 @@
+ 		#dma-cells = <1>;
+ 	};
+ 
++	usbdp_phy0: phy@fed80000 {
++		compatible = "rockchip,rk3588-usbdp-phy";
++		reg = <0x0 0xfed80000 0x0 0x10000>;
++		rockchip,u2phy-grf = <&usb2phy0_grf>;
++		rockchip,usb-grf = <&usb_grf>;
++		rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
++		rockchip,vo-grf = <&vo0_grf>;
++		clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
++			 <&cru CLK_USBDP_PHY0_IMMORTAL>,
++			 <&cru PCLK_USBDPPHY0>,
++			 <&u2phy0>;
++		clock-names = "refclk", "immortal", "pclk", "utmi";
++		resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
++			 <&cru SRST_USBDP_COMBO_PHY0_CMN>,
++			 <&cru SRST_USBDP_COMBO_PHY0_LANE>,
++			 <&cru SRST_USBDP_COMBO_PHY0_PCS>,
++			 <&cru SRST_P_USBDPPHY0>;
++		reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
++		status = "disabled";
++
++		usbdp_phy0_dp: dp-port {
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++
++		usbdp_phy0_u3: usb3-port {
++			#phy-cells = <0>;
++			status = "disabled";
++		};
++	};
++
+ 	combphy0_ps: phy@fee00000 {
+ 		compatible = "rockchip,rk3588-naneng-combphy";
+ 		reg = <0x0 0xfee00000 0x0 0x100>;
diff --git a/target/linux/rockchip/patches-6.1/293-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch b/target/linux/rockchip/patches-6.1/293-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch
new file mode 100644
index 00000000000..e33225d5375
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/293-arm64-dts-rockchip-rk3588s-Add-USB3-controllers.patch
@@ -0,0 +1,130 @@
+From e80e8b243a895dee41b5159752c9e2a9d196247e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 25 Apr 2023 18:17:19 +0200
+Subject: [PATCH 293/383] arm64: dts: rockchip: rk3588s: Add USB3 controllers
+
+Add all USB3 controllers.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 29 +++++++++++
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 62 +++++++++++++++++++++++
+ 2 files changed, 91 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -7,6 +7,35 @@
+ #include "rk3588-pinctrl.dtsi"
+ 
+ / {
++	usbdrd3_1: usbdrd3_1 {
++		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
++		clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
++			 <&cru ACLK_USB3OTG1>;
++		clock-names = "ref", "suspend", "bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		status = "disabled";
++
++		usbdrd_dwc3_1: usb@fc400000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0xfc400000 0x0 0x400000>;
++			interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
++			power-domains = <&power RK3588_PD_USB>;
++			resets = <&cru SRST_A_USB3OTG1>;
++			reset-names = "usb3-otg";
++			dr_mode = "host";
++			phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
++			phy-names = "usb2-phy", "usb3-phy";
++			phy_type = "utmi_wide";
++			snps,dis_enblslpm_quirk;
++			snps,dis-u2-freeclk-exists-quirk;
++			snps,dis-del-phy-power-chg-quirk;
++			snps,dis-tx-ipgap-linecheck-quirk;
++			status = "disabled";
++		};
++	};
++
+ 	pipe_phy1_grf: syscon@fd5c0000 {
+ 		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ 		reg = <0x0 0xfd5c0000 0x0 0x100>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -841,6 +841,38 @@
+ 		};
+ 	};
+ 
++	usbdrd3_0: usbdrd3_0 {
++		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
++		clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
++			 <&cru ACLK_USB3OTG0>;
++		clock-names = "ref", "suspend", "bus";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		status = "disabled";
++
++		usbdrd_dwc3_0: usb@fc000000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0xfc000000 0x0 0x400000>;
++			interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
++			power-domains = <&power RK3588_PD_USB>;
++			resets = <&cru SRST_A_USB3OTG0>;
++			reset-names = "usb3-otg";
++			dr_mode = "otg";
++			phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
++			phy-names = "usb2-phy", "usb3-phy";
++			phy_type = "utmi_wide";
++			snps,dis_enblslpm_quirk;
++			snps,dis-u1-entry-quirk;
++			snps,dis-u2-entry-quirk;
++			snps,dis-u2-freeclk-exists-quirk;
++			snps,dis-del-phy-power-chg-quirk;
++			snps,dis-tx-ipgap-linecheck-quirk;
++			quirk-skip-phy-init;
++			status = "disabled";
++		};
++	};
++
+ 	usb_host0_ehci: usb@fc800000 {
+ 		compatible = "rockchip,rk3588-ehci", "generic-ehci";
+ 		reg = <0x0 0xfc800000 0x0 0x40000>;
+@@ -885,6 +917,36 @@
+ 		status = "disabled";
+ 	};
+ 
++	usbhost3_0: usbhost3_0 {
++		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
++		clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
++			 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
++			 <&cru PCLK_PHP_ROOT>, <&cru CLK_PIPEPHY2_PIPE_U3_G>;
++		clock-names = "ref", "suspend", "bus", "utmi", "php", "pipe";
++		#address-cells = <2>;
++		#size-cells = <2>;
++		ranges;
++		status = "disabled";
++
++		usbhost_dwc3_0: usb@fcd00000 {
++			compatible = "snps,dwc3";
++			reg = <0x0 0xfcd00000 0x0 0x400000>;
++			interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
++			resets = <&cru SRST_A_USB3OTG2>;
++			reset-names = "usb3-host";
++			dr_mode = "host";
++			phys = <&combphy2_psu PHY_TYPE_USB3>;
++			phy-names = "usb3-phy";
++			phy_type = "utmi_wide";
++			snps,dis_enblslpm_quirk;
++			snps,dis-u2-freeclk-exists-quirk;
++			snps,dis-del-phy-power-chg-quirk;
++			snps,dis-tx-ipgap-linecheck-quirk;
++			snps,dis_rxdet_inp3_quirk;
++			status = "disabled";
++		};
++	};
++
+ 	sys_grf: syscon@fd58c000 {
+ 		compatible = "rockchip,rk3588-sys-grf", "syscon";
+ 		reg = <0x0 0xfd58c000 0x0 0x1000>;
diff --git a/target/linux/rockchip/patches-6.1/294-fix-USB3-do-not-disable-sub-nodes.patch b/target/linux/rockchip/patches-6.1/294-fix-USB3-do-not-disable-sub-nodes.patch
new file mode 100644
index 00000000000..29656d1d9f6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/294-fix-USB3-do-not-disable-sub-nodes.patch
@@ -0,0 +1,39 @@
+From ac17358d5ed73d379ce873a7fc3d35f92bdaad83 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 26 Apr 2023 15:01:10 +0200
+Subject: [PATCH 294/383] fix USB3: do not disable sub-nodes
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 1 -
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 2 --
+ 2 files changed, 3 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -32,7 +32,6 @@
+ 			snps,dis-u2-freeclk-exists-quirk;
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
+-			status = "disabled";
+ 		};
+ 	};
+ 
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -869,7 +869,6 @@
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
+ 			quirk-skip-phy-init;
+-			status = "disabled";
+ 		};
+ 	};
+ 
+@@ -943,7 +942,6 @@
+ 			snps,dis-del-phy-power-chg-quirk;
+ 			snps,dis-tx-ipgap-linecheck-quirk;
+ 			snps,dis_rxdet_inp3_quirk;
+-			status = "disabled";
+ 		};
+ 	};
+ 
diff --git a/target/linux/rockchip/patches-6.1/295-phy-rockchip-add-usbdp-combo-phy-driver.patch b/target/linux/rockchip/patches-6.1/295-phy-rockchip-add-usbdp-combo-phy-driver.patch
new file mode 100644
index 00000000000..f6556cde657
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/295-phy-rockchip-add-usbdp-combo-phy-driver.patch
@@ -0,0 +1,1780 @@
+From b881d0c0e83b98ccdb7e091d16ab31c2495da721 Mon Sep 17 00:00:00 2001
+From: Frank Wang <frank.wang@rock-chips.com>
+Date: Tue, 25 Apr 2023 15:55:54 +0200
+Subject: [PATCH 295/383] phy: rockchip: add usbdp combo phy driver
+
+This adds a new USBDP combo PHY with Samsung IP block driver.
+
+The driver get lane mux and mapping info in 2 ways, supporting
+DisplayPort alternate mode or parsing from DT. When parsing from DT,
+the property "rockchip,dp-lane-mux" provide the DP mux and mapping info.
+
+When do DP link training, need to set lane number, link rate, swing, and
+pre-emphasis via PHY configure interface.
+
+Co-Developed-by: Zhang Yubing <yubing.zhang@rock-chips.com>
+Signed-off-by: Zhang Yubing <yubing.zhang@rock-chips.com>
+Co-Developed-by: Frank Wang <frank.wang@rock-chips.com>
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/phy/rockchip/Kconfig              |    9 +
+ drivers/phy/rockchip/Makefile             |    1 +
+ drivers/phy/rockchip/phy-rockchip-usbdp.c | 1728 +++++++++++++++++++++
+ 3 files changed, 1738 insertions(+)
+ create mode 100644 drivers/phy/rockchip/phy-rockchip-usbdp.c
+
+--- a/drivers/phy/rockchip/Kconfig
++++ b/drivers/phy/rockchip/Kconfig
+@@ -107,3 +107,12 @@ config PHY_ROCKCHIP_USB
+ 	select GENERIC_PHY
+ 	help
+ 	  Enable this to support the Rockchip USB 2.0 PHY.
++
++config PHY_ROCKCHIP_USBDP
++	tristate "Rockchip USBDP COMBO PHY Driver"
++	depends on ARCH_ROCKCHIP && OF
++	select GENERIC_PHY
++	select TYPEC
++	help
++	  Enable this to support the Rockchip USB3.0/DP
++	  combo PHY with Samsung IP block.
+--- a/drivers/phy/rockchip/Makefile
++++ b/drivers/phy/rockchip/Makefile
+@@ -11,3 +11,4 @@ obj-$(CONFIG_PHY_ROCKCHIP_PCIE)		+= phy-
+ obj-$(CONFIG_PHY_ROCKCHIP_SNPS_PCIE3)	+= phy-rockchip-snps-pcie3.o
+ obj-$(CONFIG_PHY_ROCKCHIP_TYPEC)	+= phy-rockchip-typec.o
+ obj-$(CONFIG_PHY_ROCKCHIP_USB)		+= phy-rockchip-usb.o
++obj-$(CONFIG_PHY_ROCKCHIP_USBDP)	+= phy-rockchip-usbdp.o
+--- /dev/null
++++ b/drivers/phy/rockchip/phy-rockchip-usbdp.c
+@@ -0,0 +1,1728 @@
++// SPDX-License-Identifier: GPL-2.0-or-later
++/*
++ * Rockchip USBDP Combo PHY with Samsung IP block driver
++ *
++ * Copyright (C) 2021 Rockchip Electronics Co., Ltd
++ */
++
++#include <linux/bitfield.h>
++#include <linux/bits.h>
++#include <linux/clk.h>
++#include <linux/clk-provider.h>
++#include <linux/delay.h>
++#include <linux/gpio.h>
++#include <linux/io.h>
++#include <linux/iopoll.h>
++#include <linux/kernel.h>
++#include <linux/mfd/syscon.h>
++#include <linux/module.h>
++#include <linux/mutex.h>
++#include <linux/of.h>
++#include <linux/of_address.h>
++#include <linux/of_platform.h>
++#include <linux/phy/phy.h>
++#include <linux/platform_device.h>
++#include <linux/regmap.h>
++#include <linux/reset.h>
++#include <linux/usb/ch9.h>
++#include <linux/usb/typec_dp.h>
++#include <linux/usb/typec_mux.h>
++
++/* RK3588 USBDP PHY Register Definitions */
++
++#define UDPHY_PCS				0x4000
++#define UDPHY_PMA				0x8000
++
++/* VO0 GRF Registers */
++#define RK3588_GRF_VO0_CON0			0x0000
++#define RK3588_GRF_VO0_CON2			0x0008
++#define DP_SINK_HPD_CFG				BIT(11)
++#define DP_SINK_HPD_SEL				BIT(10)
++#define DP_AUX_DIN_SEL				BIT(9)
++#define DP_AUX_DOUT_SEL				BIT(8)
++#define DP_LANE_SEL_N(n)			GENMASK(2 * (n) + 1, 2 * (n))
++#define DP_LANE_SEL_ALL				GENMASK(7, 0)
++#define PHY_AUX_DP_DATA_POL_NORMAL		0
++#define PHY_AUX_DP_DATA_POL_INVERT		1
++
++/* PMA CMN Registers */
++#define CMN_LANE_MUX_AND_EN_OFFSET		0x0288	/* cmn_reg00A2 */
++#define CMN_DP_LANE_MUX_N(n)			BIT((n) + 4)
++#define CMN_DP_LANE_EN_N(n)			BIT(n)
++#define CMN_DP_LANE_MUX_ALL			GENMASK(7, 4)
++#define CMN_DP_LANE_EN_ALL			GENMASK(3, 0)
++#define PHY_LANE_MUX_USB			0
++#define PHY_LANE_MUX_DP				1
++
++#define CMN_DP_LINK_OFFSET			0x28c	/*cmn_reg00A3 */
++#define CMN_DP_TX_LINK_BW			GENMASK(6, 5)
++#define CMN_DP_TX_LANE_SWAP_EN			BIT(2)
++
++#define CMN_SSC_EN_OFFSET			0x2d0	/* cmn_reg00B4 */
++#define CMN_ROPLL_SSC_EN			BIT(1)
++#define CMN_LCPLL_SSC_EN			BIT(0)
++
++#define CMN_ANA_LCPLL_DONE_OFFSET		0x0350	/* cmn_reg00D4 */
++#define CMN_ANA_LCPLL_LOCK_DONE			BIT(7)
++#define CMN_ANA_LCPLL_AFC_DONE			BIT(6)
++
++#define CMN_ANA_ROPLL_DONE_OFFSET		0x0354	/* cmn_reg00D5 */
++#define CMN_ANA_ROPLL_LOCK_DONE			BIT(1)
++#define CMN_ANA_ROPLL_AFC_DONE			BIT(0)
++
++#define CMN_DP_RSTN_OFFSET			0x038c	/* cmn_reg00E3 */
++#define CMN_DP_INIT_RSTN			BIT(3)
++#define CMN_DP_CMN_RSTN				BIT(2)
++#define CMN_CDR_WTCHDG_EN			BIT(1)
++#define CMN_CDR_WTCHDG_MSK_CDR_EN		BIT(0)
++
++#define TRSV_ANA_TX_CLK_OFFSET_N(n)		(0x854 + (n) * 0x800)	/* trsv_reg0215 */
++#define LN_ANA_TX_SER_TXCLK_INV			BIT(1)
++
++#define TRSV_LN0_MON_RX_CDR_DONE_OFFSET		0x0b84	/* trsv_reg02E1 */
++#define TRSV_LN0_MON_RX_CDR_LOCK_DONE		BIT(0)
++
++#define TRSV_LN2_MON_RX_CDR_DONE_OFFSET		0x1b84	/* trsv_reg06E1 */
++#define TRSV_LN2_MON_RX_CDR_LOCK_DONE		BIT(0)
++
++
++#define BIT_WRITEABLE_SHIFT	16
++
++enum {
++	DP_BW_RBR,
++	DP_BW_HBR,
++	DP_BW_HBR2,
++	DP_BW_HBR3,
++};
++
++enum {
++	UDPHY_MODE_NONE		= 0,
++	UDPHY_MODE_USB		= BIT(0),
++	UDPHY_MODE_DP		= BIT(1),
++	UDPHY_MODE_DP_USB	= BIT(1) | BIT(0),
++};
++
++struct udphy_grf_reg {
++	unsigned int	offset;
++	unsigned int	bitend;
++	unsigned int	bitstart;
++	unsigned int	disable;
++	unsigned int	enable;
++};
++
++struct udphy_grf_cfg {
++	/* u2phy-grf */
++	struct udphy_grf_reg	bvalid_phy_con;
++	struct udphy_grf_reg	bvalid_grf_con;
++
++	/* usb-grf */
++	struct udphy_grf_reg	usb3otg0_cfg;
++	struct udphy_grf_reg	usb3otg1_cfg;
++
++	/* usbdpphy-grf */
++	struct udphy_grf_reg	low_pwrn;
++	struct udphy_grf_reg	rx_lfps;
++};
++
++struct udphy_vogrf_cfg {
++	/* vo-grf */
++	struct udphy_grf_reg hpd_trigger;
++};
++
++struct dp_tx_drv_ctrl {
++	u32 trsv_reg0204;
++	u32 trsv_reg0205;
++	u32 trsv_reg0206;
++	u32 trsv_reg0207;
++};
++
++struct rockchip_udphy;
++
++struct rockchip_udphy_cfg {
++	/* resets to be requested */
++	const char * const *rst_list;
++	int num_rsts;
++
++	struct udphy_grf_cfg grfcfg;
++	struct udphy_vogrf_cfg vogrfcfg[2];
++	const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg[4])[4];
++	const struct dp_tx_drv_ctrl (*dp_tx_ctrl_cfg_typec[4])[4];
++	int (*combophy_init)(struct rockchip_udphy *udphy);
++	int (*dp_phy_set_rate)(struct rockchip_udphy *udphy,
++			       struct phy_configure_opts_dp *dp);
++	int (*dp_phy_set_voltages)(struct rockchip_udphy *udphy,
++				   struct phy_configure_opts_dp *dp);
++	int (*hpd_event_trigger)(struct rockchip_udphy *udphy, bool hpd);
++	int (*dplane_enable)(struct rockchip_udphy *udphy, int dp_lanes);
++	int (*dplane_select)(struct rockchip_udphy *udphy);
++};
++
++struct rockchip_udphy {
++	struct device *dev;
++	struct regmap *pma_regmap;
++	struct regmap *u2phygrf;
++	struct regmap *udphygrf;
++	struct regmap *usbgrf;
++	struct regmap *vogrf;
++	struct typec_switch_dev *sw;
++	struct typec_mux_dev *mux;
++	struct mutex mutex; /* mutex to protect access to individual PHYs */
++
++	/* clocks and rests */
++	int num_clks;
++	struct clk_bulk_data *clks;
++	struct clk *refclk;
++	struct reset_control **rsts;
++
++	/* PHY status management */
++	bool flip;
++	bool mode_change;
++	u8 mode;
++	u8 status;
++
++	/* utilized for USB */
++	bool hs; /* flag for high-speed */
++
++	/* utilized for DP */
++	struct gpio_desc *sbu1_dc_gpio;
++	struct gpio_desc *sbu2_dc_gpio;
++	u32 lane_mux_sel[4];
++	u32 dp_lane_sel[4];
++	u32 dp_aux_dout_sel;
++	u32 dp_aux_din_sel;
++	bool dp_sink_hpd_sel;
++	bool dp_sink_hpd_cfg;
++	u8 bw;
++	int id;
++
++	/* PHY const config */
++	const struct rockchip_udphy_cfg *cfgs;
++};
++
++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr[4][4] = {
++	/* voltage swing 0, pre-emphasis 0->3 */
++	{
++		{ 0x20, 0x10, 0x42, 0xe5 },
++		{ 0x26, 0x14, 0x42, 0xe5 },
++		{ 0x29, 0x18, 0x42, 0xe5 },
++		{ 0x2b, 0x1c, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 1, pre-emphasis 0->2 */
++	{
++		{ 0x23, 0x10, 0x42, 0xe7 },
++		{ 0x2a, 0x17, 0x43, 0xe7 },
++		{ 0x2b, 0x1a, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 2, pre-emphasis 0->1 */
++	{
++		{ 0x27, 0x10, 0x42, 0xe7 },
++		{ 0x2b, 0x17, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 3, pre-emphasis 0 */
++	{
++		{ 0x29, 0x10, 0x43, 0xe7 },
++	},
++};
++
++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_rbr_hbr_typec[4][4] = {
++	/* voltage swing 0, pre-emphasis 0->3 */
++	{
++		{ 0x20, 0x10, 0x42, 0xe5 },
++		{ 0x26, 0x14, 0x42, 0xe5 },
++		{ 0x29, 0x18, 0x42, 0xe5 },
++		{ 0x2b, 0x1c, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 1, pre-emphasis 0->2 */
++	{
++		{ 0x23, 0x10, 0x42, 0xe7 },
++		{ 0x2a, 0x17, 0x43, 0xe7 },
++		{ 0x2b, 0x1a, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 2, pre-emphasis 0->1 */
++	{
++		{ 0x27, 0x10, 0x43, 0x67 },
++		{ 0x2b, 0x17, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 3, pre-emphasis 0 */
++	{
++		{ 0x29, 0x10, 0x43, 0xe7 },
++	},
++};
++
++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr2[4][4] = {
++	/* voltage swing 0, pre-emphasis 0->3 */
++	{
++		{ 0x21, 0x10, 0x42, 0xe5 },
++		{ 0x26, 0x14, 0x42, 0xe5 },
++		{ 0x26, 0x16, 0x43, 0xe5 },
++		{ 0x2a, 0x19, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 1, pre-emphasis 0->2 */
++	{
++		{ 0x24, 0x10, 0x42, 0xe7 },
++		{ 0x2a, 0x17, 0x43, 0xe7 },
++		{ 0x2b, 0x1a, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 2, pre-emphasis 0->1 */
++	{
++		{ 0x28, 0x10, 0x42, 0xe7 },
++		{ 0x2b, 0x17, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 3, pre-emphasis 0 */
++	{
++		{ 0x28, 0x10, 0x43, 0xe7 },
++	},
++};
++
++static const struct dp_tx_drv_ctrl rk3588_dp_tx_drv_ctrl_hbr3[4][4] = {
++	/* voltage swing 0, pre-emphasis 0->3 */
++	{
++		{ 0x21, 0x10, 0x42, 0xe5 },
++		{ 0x26, 0x14, 0x42, 0xe5 },
++		{ 0x26, 0x16, 0x43, 0xe5 },
++		{ 0x29, 0x18, 0x43, 0xe7 },
++	},
++
++	/* voltage swing 1, pre-emphasis 0->2 */
++	{
++		{ 0x24, 0x10, 0x42, 0xe7 },
++		{ 0x2a, 0x18, 0x43, 0xe7 },
++		{ 0x2b, 0x1b, 0x43, 0xe7 }
++	},
++
++	/* voltage swing 2, pre-emphasis 0->1 */
++	{
++		{ 0x27, 0x10, 0x42, 0xe7 },
++		{ 0x2b, 0x18, 0x43, 0xe7 }
++	},
++
++	/* voltage swing 3, pre-emphasis 0 */
++	{
++		{ 0x28, 0x10, 0x43, 0xe7 },
++	},
++};
++
++static const struct reg_sequence rk3588_udphy_24m_refclk_cfg[] = {
++	{0x0090, 0x68}, {0x0094, 0x68},
++	{0x0128, 0x24}, {0x012c, 0x44},
++	{0x0130, 0x3f}, {0x0134, 0x44},
++	{0x015c, 0xa9}, {0x0160, 0x71},
++	{0x0164, 0x71}, {0x0168, 0xa9},
++	{0x0174, 0xa9}, {0x0178, 0x71},
++	{0x017c, 0x71}, {0x0180, 0xa9},
++	{0x018c, 0x41}, {0x0190, 0x00},
++	{0x0194, 0x05}, {0x01ac, 0x2a},
++	{0x01b0, 0x17}, {0x01b4, 0x17},
++	{0x01b8, 0x2a}, {0x01c8, 0x04},
++	{0x01cc, 0x08}, {0x01d0, 0x08},
++	{0x01d4, 0x04}, {0x01d8, 0x20},
++	{0x01dc, 0x01}, {0x01e0, 0x09},
++	{0x01e4, 0x03}, {0x01f0, 0x29},
++	{0x01f4, 0x02}, {0x01f8, 0x02},
++	{0x01fc, 0x29}, {0x0208, 0x2a},
++	{0x020c, 0x17}, {0x0210, 0x17},
++	{0x0214, 0x2a}, {0x0224, 0x20},
++	{0x03f0, 0x0a}, {0x03f4, 0x07},
++	{0x03f8, 0x07}, {0x03fc, 0x0c},
++	{0x0404, 0x12}, {0x0408, 0x1a},
++	{0x040c, 0x1a}, {0x0410, 0x3f},
++	{0x0ce0, 0x68}, {0x0ce8, 0xd0},
++	{0x0cf0, 0x87}, {0x0cf8, 0x70},
++	{0x0d00, 0x70}, {0x0d08, 0xa9},
++	{0x1ce0, 0x68}, {0x1ce8, 0xd0},
++	{0x1cf0, 0x87}, {0x1cf8, 0x70},
++	{0x1d00, 0x70}, {0x1d08, 0xa9},
++	{0x0a3c, 0xd0}, {0x0a44, 0xd0},
++	{0x0a48, 0x01}, {0x0a4c, 0x0d},
++	{0x0a54, 0xe0}, {0x0a5c, 0xe0},
++	{0x0a64, 0xa8}, {0x1a3c, 0xd0},
++	{0x1a44, 0xd0}, {0x1a48, 0x01},
++	{0x1a4c, 0x0d}, {0x1a54, 0xe0},
++	{0x1a5c, 0xe0}, {0x1a64, 0xa8}
++};
++
++static const struct reg_sequence rk3588_udphy_26m_refclk_cfg[] = {
++	{0x0830, 0x07}, {0x085c, 0x80},
++	{0x1030, 0x07}, {0x105c, 0x80},
++	{0x1830, 0x07}, {0x185c, 0x80},
++	{0x2030, 0x07}, {0x205c, 0x80},
++	{0x0228, 0x38}, {0x0104, 0x44},
++	{0x0248, 0x44}, {0x038C, 0x02},
++	{0x0878, 0x04}, {0x1878, 0x04},
++	{0x0898, 0x77}, {0x1898, 0x77},
++	{0x0054, 0x01}, {0x00e0, 0x38},
++	{0x0060, 0x24}, {0x0064, 0x77},
++	{0x0070, 0x76}, {0x0234, 0xE8},
++	{0x0AF4, 0x15}, {0x1AF4, 0x15},
++	{0x081C, 0xE5}, {0x181C, 0xE5},
++	{0x099C, 0x48}, {0x199C, 0x48},
++	{0x09A4, 0x07}, {0x09A8, 0x22},
++	{0x19A4, 0x07}, {0x19A8, 0x22},
++	{0x09B8, 0x3E}, {0x19B8, 0x3E},
++	{0x09E4, 0x02}, {0x19E4, 0x02},
++	{0x0A34, 0x1E}, {0x1A34, 0x1E},
++	{0x0A98, 0x2F}, {0x1A98, 0x2F},
++	{0x0c30, 0x0E}, {0x0C48, 0x06},
++	{0x1C30, 0x0E}, {0x1C48, 0x06},
++	{0x028C, 0x18}, {0x0AF0, 0x00},
++	{0x1AF0, 0x00}
++};
++
++static const struct reg_sequence rk3588_udphy_init_sequence[] = {
++	{0x0104, 0x44}, {0x0234, 0xE8},
++	{0x0248, 0x44}, {0x028C, 0x18},
++	{0x081C, 0xE5}, {0x0878, 0x00},
++	{0x0994, 0x1C}, {0x0AF0, 0x00},
++	{0x181C, 0xE5}, {0x1878, 0x00},
++	{0x1994, 0x1C}, {0x1AF0, 0x00},
++	{0x0428, 0x60}, {0x0D58, 0x33},
++	{0x1D58, 0x33}, {0x0990, 0x74},
++	{0x0D64, 0x17}, {0x08C8, 0x13},
++	{0x1990, 0x74}, {0x1D64, 0x17},
++	{0x18C8, 0x13}, {0x0D90, 0x40},
++	{0x0DA8, 0x40}, {0x0DC0, 0x40},
++	{0x0DD8, 0x40}, {0x1D90, 0x40},
++	{0x1DA8, 0x40}, {0x1DC0, 0x40},
++	{0x1DD8, 0x40}, {0x03C0, 0x30},
++	{0x03C4, 0x06}, {0x0E10, 0x00},
++	{0x1E10, 0x00}, {0x043C, 0x0F},
++	{0x0D2C, 0xFF}, {0x1D2C, 0xFF},
++	{0x0D34, 0x0F}, {0x1D34, 0x0F},
++	{0x08FC, 0x2A}, {0x0914, 0x28},
++	{0x0A30, 0x03}, {0x0E38, 0x05},
++	{0x0ECC, 0x27}, {0x0ED0, 0x22},
++	{0x0ED4, 0x26}, {0x18FC, 0x2A},
++	{0x1914, 0x28}, {0x1A30, 0x03},
++	{0x1E38, 0x05}, {0x1ECC, 0x27},
++	{0x1ED0, 0x22}, {0x1ED4, 0x26},
++	{0x0048, 0x0F}, {0x0060, 0x3C},
++	{0x0064, 0xF7}, {0x006C, 0x20},
++	{0x0070, 0x7D}, {0x0074, 0x68},
++	{0x0AF4, 0x1A}, {0x1AF4, 0x1A},
++	{0x0440, 0x3F}, {0x10D4, 0x08},
++	{0x20D4, 0x08}, {0x00D4, 0x30},
++	{0x0024, 0x6e},
++};
++
++static inline int grfreg_write(struct regmap *base,
++			       const struct udphy_grf_reg *reg, bool en)
++{
++	u32 val, mask, tmp;
++
++	tmp = en ? reg->enable : reg->disable;
++	mask = GENMASK(reg->bitend, reg->bitstart);
++	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
++
++	return regmap_write(base, reg->offset, val);
++}
++
++static int udphy_clk_init(struct rockchip_udphy *udphy, struct device *dev)
++{
++	int i;
++
++	udphy->num_clks = devm_clk_bulk_get_all(dev, &udphy->clks);
++	if (udphy->num_clks < 1)
++		return -ENODEV;
++
++	/* used for configure phy reference clock frequency */
++	for (i = 0; i < udphy->num_clks; i++) {
++		if (!strncmp(udphy->clks[i].id, "refclk", 6)) {
++			udphy->refclk = udphy->clks[i].clk;
++			break;
++		}
++	}
++
++	if (!udphy->refclk)
++		dev_warn(udphy->dev, "no refclk found\n");
++
++	return 0;
++}
++
++static int udphy_reset_init(struct rockchip_udphy *udphy, struct device *dev)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int idx;
++
++	udphy->rsts = devm_kcalloc(dev, cfg->num_rsts,
++				   sizeof(*udphy->rsts), GFP_KERNEL);
++	if (!udphy->rsts)
++		return -ENOMEM;
++
++	for (idx = 0; idx < cfg->num_rsts; idx++) {
++		struct reset_control *rst;
++		const char *name = cfg->rst_list[idx];
++
++		rst = devm_reset_control_get(dev, name);
++		if (IS_ERR(rst)) {
++			dev_err(dev, "failed to get %s reset\n", name);
++			devm_kfree(dev, (void *)udphy->rsts);
++			return PTR_ERR(rst);
++		}
++
++		udphy->rsts[idx] = rst;
++	}
++
++	return 0;
++}
++
++static int udphy_get_rst_idx(const char * const *list, int num, char *name)
++{
++	int idx;
++
++	for (idx = 0; idx < num; idx++) {
++		if (!strcmp(list[idx], name))
++			return idx;
++	}
++
++	return -EINVAL;
++}
++
++static int udphy_reset_assert(struct rockchip_udphy *udphy, char *name)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int idx;
++
++	idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
++	if (idx < 0)
++		return idx;
++
++	return reset_control_assert(udphy->rsts[idx]);
++}
++
++static int udphy_reset_deassert(struct rockchip_udphy *udphy, char *name)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int idx;
++
++	idx = udphy_get_rst_idx(cfg->rst_list, cfg->num_rsts, name);
++	if (idx < 0)
++		return idx;
++
++	return reset_control_deassert(udphy->rsts[idx]);
++}
++
++static void udphy_u3_port_disable(struct rockchip_udphy *udphy, u8 disable)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	const struct udphy_grf_reg *preg;
++
++	preg = udphy->id ? &cfg->grfcfg.usb3otg1_cfg : &cfg->grfcfg.usb3otg0_cfg;
++	grfreg_write(udphy->usbgrf, preg, disable);
++}
++
++static void udphy_usb_bvalid_enable(struct rockchip_udphy *udphy, u8 enable)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++
++	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_phy_con, enable);
++	grfreg_write(udphy->u2phygrf, &cfg->grfcfg.bvalid_grf_con, enable);
++}
++
++/*
++ * In usb/dp combo phy driver, here are 2 ways to mapping lanes.
++ *
++ * 1 Type-C Mapping table (DP_Alt_Mode V1.0b remove ABF pin mapping)
++ * ---------------------------------------------------------------------------
++ * Type-C Pin   B11-B10       A2-A3       A11-A10       B2-B3
++ * PHY Pad      ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
++ * C/E(Normal)  dpln3         dpln2       dpln0         dpln1
++ * C/E(Flip  )  dpln0         dpln1       dpln3         dpln2
++ * D/F(Normal)  usbrx         usbtx       dpln0         dpln1
++ * D/F(Flip  )  dpln0         dpln1       usbrx         usbtx
++ * A(Normal  )  dpln3         dpln1       dpln2         dpln0
++ * A(Flip    )  dpln2         dpln0       dpln3         dpln1
++ * B(Normal  )  usbrx         usbtx       dpln1         dpln0
++ * B(Flip    )  dpln1         dpln0       usbrx         usbtx
++ * ---------------------------------------------------------------------------
++ *
++ * 2 Mapping the lanes in dtsi
++ * if all 4 lane assignment for dp function, define rockchip,dp-lane-mux = <x x x x>;
++ * sample as follow:
++ * ---------------------------------------------------------------------------
++ *                        B11-B10       A2-A3       A11-A10       B2-B3
++ * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
++ * <0 1 2 3>              dpln0         dpln1       dpln2         dpln3
++ * <2 3 0 1>              dpln2         dpln3       dpln0         dpln1
++ * ---------------------------------------------------------------------------
++ * if 2 lane for dp function, 2 lane for usb function, define rockchip,dp-lane-mux = <x x>;
++ * sample as follow:
++ * ---------------------------------------------------------------------------
++ *                        B11-B10       A2-A3       A11-A10       B2-B3
++ * rockchip,dp-lane-mux   ln0(tx/rx)    ln1(tx)     ln2(tx/rx)    ln3(tx)
++ * <0 1>                  dpln0         dpln1       usbrx         usbtx
++ * <2 3>                  usbrx         usbtx       dpln0         dpln1
++ * ---------------------------------------------------------------------------
++ */
++
++static int udphy_dplane_select(struct rockchip_udphy *udphy)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++
++	if (cfg->dplane_select)
++		return cfg->dplane_select(udphy);
++
++	return 0;
++}
++
++static int udphy_dplane_get(struct rockchip_udphy *udphy)
++{
++	int dp_lanes;
++
++	switch (udphy->mode) {
++	case UDPHY_MODE_DP:
++		dp_lanes = 4;
++		break;
++	case UDPHY_MODE_DP_USB:
++		dp_lanes = 2;
++		break;
++	case UDPHY_MODE_USB:
++		fallthrough;
++	default:
++		dp_lanes = 0;
++		break;
++	}
++
++	return dp_lanes;
++}
++
++static int udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int ret = 0;
++
++	if (cfg->dplane_enable)
++		ret = cfg->dplane_enable(udphy, dp_lanes);
++
++	return ret;
++}
++
++static int upphy_set_typec_default_mapping(struct rockchip_udphy *udphy)
++{
++	if (udphy->flip) {
++		udphy->dp_lane_sel[0] = 0;
++		udphy->dp_lane_sel[1] = 1;
++		udphy->dp_lane_sel[2] = 3;
++		udphy->dp_lane_sel[3] = 2;
++		udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
++		udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
++		udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
++		udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
++		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_INVERT;
++		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_INVERT;
++		gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 1);
++		gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
++	} else {
++		udphy->dp_lane_sel[0] = 2;
++		udphy->dp_lane_sel[1] = 3;
++		udphy->dp_lane_sel[2] = 1;
++		udphy->dp_lane_sel[3] = 0;
++		udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
++		udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
++		udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
++		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
++		udphy->dp_aux_dout_sel = PHY_AUX_DP_DATA_POL_NORMAL;
++		udphy->dp_aux_din_sel = PHY_AUX_DP_DATA_POL_NORMAL;
++		gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
++		gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 1);
++	}
++
++	udphy->mode = UDPHY_MODE_DP_USB;
++
++	return 0;
++}
++
++static int udphy_orien_sw_set(struct typec_switch_dev *sw,
++			      enum typec_orientation orien)
++{
++	struct rockchip_udphy *udphy = typec_switch_get_drvdata(sw);
++
++	mutex_lock(&udphy->mutex);
++
++	if (orien == TYPEC_ORIENTATION_NONE) {
++		gpiod_set_value_cansleep(udphy->sbu1_dc_gpio, 0);
++		gpiod_set_value_cansleep(udphy->sbu2_dc_gpio, 0);
++		/* unattached */
++		udphy_usb_bvalid_enable(udphy, false);
++		goto unlock_ret;
++	}
++
++	udphy->flip = (orien == TYPEC_ORIENTATION_REVERSE) ? true : false;
++	upphy_set_typec_default_mapping(udphy);
++	udphy_usb_bvalid_enable(udphy, true);
++
++unlock_ret:
++	mutex_unlock(&udphy->mutex);
++	return 0;
++}
++
++static int udphy_setup_orien_switch(struct rockchip_udphy *udphy)
++{
++	struct typec_switch_desc sw_desc = { };
++
++	sw_desc.drvdata = udphy;
++	sw_desc.fwnode = dev_fwnode(udphy->dev);
++	sw_desc.set = udphy_orien_sw_set;
++
++	udphy->sw = typec_switch_register(udphy->dev, &sw_desc);
++	if (IS_ERR(udphy->sw)) {
++		dev_err(udphy->dev, "Error register typec orientation switch: %ld\n",
++			PTR_ERR(udphy->sw));
++		return PTR_ERR(udphy->sw);
++	}
++
++	return 0;
++}
++
++static void udphy_orien_switch_unregister(void *data)
++{
++	struct rockchip_udphy *udphy = data;
++
++	typec_switch_unregister(udphy->sw);
++}
++
++static int udphy_setup(struct rockchip_udphy *udphy)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int ret = 0;
++
++	ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
++	if (ret) {
++		dev_err(udphy->dev, "failed to enable clk\n");
++		return ret;
++	}
++
++	if (cfg->combophy_init) {
++		ret = cfg->combophy_init(udphy);
++		if (ret) {
++			dev_err(udphy->dev, "failed to init combophy\n");
++			clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static int udphy_disable(struct rockchip_udphy *udphy)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int i;
++
++	clk_bulk_disable_unprepare(udphy->num_clks, udphy->clks);
++
++	for (i = 0; i < cfg->num_rsts; i++)
++		reset_control_assert(udphy->rsts[i]);
++
++	return 0;
++}
++
++static int udphy_parse_lane_mux_data(struct rockchip_udphy *udphy, struct device_node *np)
++{
++	struct property *prop;
++	int ret, i, len, num_lanes;
++
++	prop = of_find_property(np, "rockchip,dp-lane-mux", &len);
++	if (!prop) {
++		dev_dbg(udphy->dev, "failed to find dp lane mux, following dp alt mode\n");
++		udphy->mode = UDPHY_MODE_USB;
++		return 0;
++	}
++
++	num_lanes = len / sizeof(u32);
++
++	if (num_lanes != 2 && num_lanes != 4) {
++		dev_err(udphy->dev, "invalid number of lane mux\n");
++		return -EINVAL;
++	}
++
++	ret = of_property_read_u32_array(np, "rockchip,dp-lane-mux", udphy->dp_lane_sel, num_lanes);
++	if (ret) {
++		dev_err(udphy->dev, "get dp lane mux failed\n");
++		return -EINVAL;
++	}
++
++	for (i = 0; i < num_lanes; i++) {
++		int j;
++
++		if (udphy->dp_lane_sel[i] > 3) {
++			dev_err(udphy->dev, "lane mux between 0 and 3, exceeding the range\n");
++			return -EINVAL;
++		}
++
++		udphy->lane_mux_sel[udphy->dp_lane_sel[i]] = PHY_LANE_MUX_DP;
++
++		for (j = i + 1; j < num_lanes; j++) {
++			if (udphy->dp_lane_sel[i] == udphy->dp_lane_sel[j]) {
++				dev_err(udphy->dev, "set repeat lane mux value\n");
++				return -EINVAL;
++			}
++		}
++	}
++
++	udphy->mode = UDPHY_MODE_DP;
++	if (num_lanes == 2)
++		udphy->mode |= UDPHY_MODE_USB;
++
++	return 0;
++}
++
++static int udphy_get_initial_status(struct rockchip_udphy *udphy)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int ret, i;
++	u32 value;
++
++	ret = clk_bulk_prepare_enable(udphy->num_clks, udphy->clks);
++	if (ret) {
++		dev_err(udphy->dev, "failed to enable clk\n");
++		return ret;
++	}
++
++	for (i = 0; i < cfg->num_rsts; i++)
++		reset_control_deassert(udphy->rsts[i]);
++
++	regmap_read(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, &value);
++	if (FIELD_GET(CMN_DP_LANE_MUX_ALL, value) && FIELD_GET(CMN_DP_LANE_EN_ALL, value))
++		udphy->status = UDPHY_MODE_DP;
++	else
++		udphy_disable(udphy);
++
++	return 0;
++}
++
++static int udphy_parse_dt(struct rockchip_udphy *udphy, struct device *dev)
++{
++	struct device_node *np = dev->of_node;
++	enum usb_device_speed maximum_speed;
++	int ret;
++
++	udphy->u2phygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,u2phy-grf");
++	if (IS_ERR(udphy->u2phygrf)) {
++		if (PTR_ERR(udphy->u2phygrf) == -ENODEV) {
++			dev_warn(dev, "missing u2phy-grf dt node\n");
++			udphy->u2phygrf = NULL;
++		} else {
++			return PTR_ERR(udphy->u2phygrf);
++		}
++	}
++
++	udphy->udphygrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbdpphy-grf");
++	if (IS_ERR(udphy->udphygrf)) {
++		if (PTR_ERR(udphy->udphygrf) == -ENODEV) {
++			dev_warn(dev, "missing usbdpphy-grf dt node\n");
++			udphy->udphygrf = NULL;
++		} else {
++			return PTR_ERR(udphy->udphygrf);
++		}
++	}
++
++	udphy->usbgrf = syscon_regmap_lookup_by_phandle(np, "rockchip,usb-grf");
++	if (IS_ERR(udphy->usbgrf)) {
++		if (PTR_ERR(udphy->usbgrf) == -ENODEV) {
++			dev_warn(dev, "missing usb-grf dt node\n");
++			udphy->usbgrf = NULL;
++		} else {
++			return PTR_ERR(udphy->usbgrf);
++		}
++	}
++
++	udphy->vogrf = syscon_regmap_lookup_by_phandle(np, "rockchip,vo-grf");
++	if (IS_ERR(udphy->vogrf)) {
++		if (PTR_ERR(udphy->vogrf) == -ENODEV) {
++			dev_warn(dev, "missing vo-grf dt node\n");
++			udphy->vogrf = NULL;
++		} else {
++			return PTR_ERR(udphy->vogrf);
++		}
++	}
++
++	ret = udphy_parse_lane_mux_data(udphy, np);
++	if (ret)
++		return ret;
++
++	udphy->sbu1_dc_gpio = devm_gpiod_get_optional(dev, "sbu1-dc", GPIOD_OUT_LOW);
++	if (IS_ERR(udphy->sbu1_dc_gpio))
++		return PTR_ERR(udphy->sbu1_dc_gpio);
++
++	udphy->sbu2_dc_gpio = devm_gpiod_get_optional(dev, "sbu2-dc", GPIOD_OUT_LOW);
++	if (IS_ERR(udphy->sbu2_dc_gpio))
++		return PTR_ERR(udphy->sbu2_dc_gpio);
++
++	if (device_property_present(dev, "maximum-speed")) {
++		maximum_speed = usb_get_maximum_speed(dev);
++		udphy->hs = maximum_speed <= USB_SPEED_HIGH ? true : false;
++	}
++
++	ret = udphy_clk_init(udphy, dev);
++	if (ret)
++		return ret;
++
++	ret = udphy_reset_init(udphy, dev);
++	if (ret)
++		return ret;
++
++	return 0;
++}
++
++static int udphy_power_on(struct rockchip_udphy *udphy, u8 mode)
++{
++	int ret;
++
++	if (!(udphy->mode & mode)) {
++		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
++		return 0;
++	}
++
++	if (udphy->status == UDPHY_MODE_NONE) {
++		udphy->mode_change = false;
++		ret = udphy_setup(udphy);
++		if (ret)
++			return ret;
++
++		if (udphy->mode & UDPHY_MODE_USB)
++			udphy_u3_port_disable(udphy, false);
++	} else if (udphy->mode_change) {
++		udphy->mode_change = false;
++		udphy->status = UDPHY_MODE_NONE;
++		if (udphy->mode == UDPHY_MODE_DP)
++			udphy_u3_port_disable(udphy, true);
++
++		ret = udphy_disable(udphy);
++		if (ret)
++			return ret;
++		ret = udphy_setup(udphy);
++		if (ret)
++			return ret;
++	}
++
++	udphy->status |= mode;
++
++	return 0;
++}
++
++static int udphy_power_off(struct rockchip_udphy *udphy, u8 mode)
++{
++	int ret;
++
++	if (!(udphy->mode & mode)) {
++		dev_info(udphy->dev, "mode 0x%02x is not support\n", mode);
++		return 0;
++	}
++
++	if (!udphy->status)
++		return 0;
++
++	udphy->status &= ~mode;
++
++	if (udphy->status == UDPHY_MODE_NONE) {
++		ret = udphy_disable(udphy);
++		if (ret)
++			return ret;
++	}
++
++	return 0;
++}
++
++static int rockchip_dp_phy_power_on(struct phy *phy)
++{
++	struct rockchip_udphy *udphy = phy_get_drvdata(phy);
++	int ret, dp_lanes;
++
++	mutex_lock(&udphy->mutex);
++
++	dp_lanes = udphy_dplane_get(udphy);
++	phy_set_bus_width(phy, dp_lanes);
++
++	ret = udphy_power_on(udphy, UDPHY_MODE_DP);
++	if (ret)
++		goto unlock;
++
++	ret = udphy_dplane_enable(udphy, dp_lanes);
++	if (ret)
++		goto unlock;
++
++	ret = udphy_dplane_select(udphy);
++
++unlock:
++	mutex_unlock(&udphy->mutex);
++	/*
++	 * If data send by aux channel too fast after phy power on,
++	 * the aux may be not ready which will cause aux error. Adding
++	 * delay to avoid this issue.
++	 */
++	usleep_range(10000, 11000);
++	return ret;
++}
++
++static int rockchip_dp_phy_power_off(struct phy *phy)
++{
++	struct rockchip_udphy *udphy = phy_get_drvdata(phy);
++	int ret;
++
++	mutex_lock(&udphy->mutex);
++	ret = udphy_dplane_enable(udphy, 0);
++	if (ret)
++		goto unlock;
++
++	ret = udphy_power_off(udphy, UDPHY_MODE_DP);
++
++unlock:
++	mutex_unlock(&udphy->mutex);
++	return ret;
++}
++
++static int rockchip_dp_phy_verify_link_rate(unsigned int link_rate)
++{
++	switch (link_rate) {
++	case 1620:
++	case 2700:
++	case 5400:
++	case 8100:
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int rockchip_dp_phy_verify_config(struct rockchip_udphy *udphy,
++					 struct phy_configure_opts_dp *dp)
++{
++	int i, ret;
++
++	/* If changing link rate was required, verify it's supported. */
++	ret = rockchip_dp_phy_verify_link_rate(dp->link_rate);
++	if (ret)
++		return ret;
++
++	/* Verify lane count. */
++	switch (dp->lanes) {
++	case 1:
++	case 2:
++	case 4:
++		/* valid lane count. */
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	/*
++	 * If changing voltages is required, check swing and pre-emphasis
++	 * levels, per-lane.
++	 */
++	if (dp->set_voltages) {
++		/* Lane count verified previously. */
++		for (i = 0; i < dp->lanes; i++) {
++			if (dp->voltage[i] > 3 || dp->pre[i] > 3)
++				return -EINVAL;
++
++			/*
++			 * Sum of voltage swing and pre-emphasis levels cannot
++			 * exceed 3.
++			 */
++			if (dp->voltage[i] + dp->pre[i] > 3)
++				return -EINVAL;
++		}
++	}
++
++	return 0;
++}
++
++static int rockchip_dp_phy_configure(struct phy *phy,
++				     union phy_configure_opts *opts)
++{
++	struct rockchip_udphy *udphy = phy_get_drvdata(phy);
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int ret;
++
++	ret = rockchip_dp_phy_verify_config(udphy, &opts->dp);
++	if (ret)
++		return ret;
++
++	if (opts->dp.set_rate && cfg->dp_phy_set_rate) {
++		ret = cfg->dp_phy_set_rate(udphy, &opts->dp);
++		if (ret) {
++			dev_err(udphy->dev,
++				"rockchip_hdptx_phy_set_rate failed\n");
++			return ret;
++		}
++	}
++
++	if (opts->dp.set_voltages && cfg->dp_phy_set_voltages) {
++		ret = cfg->dp_phy_set_voltages(udphy, &opts->dp);
++		if (ret) {
++			dev_err(udphy->dev,
++				"rockchip_dp_phy_set_voltages failed\n");
++			return ret;
++		}
++	}
++
++	return 0;
++}
++
++static const struct phy_ops rockchip_dp_phy_ops = {
++	.power_on	= rockchip_dp_phy_power_on,
++	.power_off	= rockchip_dp_phy_power_off,
++	.configure	= rockchip_dp_phy_configure,
++	.owner		= THIS_MODULE,
++};
++
++static int rockchip_u3phy_init(struct phy *phy)
++{
++	struct rockchip_udphy *udphy = phy_get_drvdata(phy);
++	int ret = 0;
++
++	mutex_lock(&udphy->mutex);
++	/* DP only or high-speed, disable U3 port */
++	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs) {
++		udphy_u3_port_disable(udphy, true);
++		goto unlock;
++	}
++
++	ret = udphy_power_on(udphy, UDPHY_MODE_USB);
++
++unlock:
++	mutex_unlock(&udphy->mutex);
++	return ret;
++}
++
++static int rockchip_u3phy_exit(struct phy *phy)
++{
++	struct rockchip_udphy *udphy = phy_get_drvdata(phy);
++	int ret = 0;
++
++	mutex_lock(&udphy->mutex);
++	/* DP only or high-speed */
++	if (!(udphy->mode & UDPHY_MODE_USB) || udphy->hs)
++		goto unlock;
++
++	ret = udphy_power_off(udphy, UDPHY_MODE_USB);
++
++unlock:
++	mutex_unlock(&udphy->mutex);
++	return ret;
++}
++
++static const struct phy_ops rockchip_u3phy_ops = {
++	.init		= rockchip_u3phy_init,
++	.exit		= rockchip_u3phy_exit,
++	.owner		= THIS_MODULE,
++};
++
++static int usbdp_typec_mux_set(struct typec_mux_dev *mux,
++			       struct typec_mux_state *state)
++{
++	struct rockchip_udphy *udphy = typec_mux_get_drvdata(mux);
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	u8 mode;
++
++	mutex_lock(&udphy->mutex);
++
++	switch (state->mode) {
++	case TYPEC_DP_STATE_C:
++		fallthrough;
++	case TYPEC_DP_STATE_E:
++		udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
++		udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
++		udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
++		udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
++		mode = UDPHY_MODE_DP;
++		break;
++	case TYPEC_DP_STATE_D:
++		fallthrough;
++	default:
++		if (udphy->flip) {
++			udphy->lane_mux_sel[0] = PHY_LANE_MUX_DP;
++			udphy->lane_mux_sel[1] = PHY_LANE_MUX_DP;
++			udphy->lane_mux_sel[2] = PHY_LANE_MUX_USB;
++			udphy->lane_mux_sel[3] = PHY_LANE_MUX_USB;
++		} else {
++			udphy->lane_mux_sel[0] = PHY_LANE_MUX_USB;
++			udphy->lane_mux_sel[1] = PHY_LANE_MUX_USB;
++			udphy->lane_mux_sel[2] = PHY_LANE_MUX_DP;
++			udphy->lane_mux_sel[3] = PHY_LANE_MUX_DP;
++		}
++		mode = UDPHY_MODE_DP_USB;
++		break;
++	}
++
++	if (state->alt && state->alt->svid == USB_TYPEC_DP_SID) {
++		struct typec_displayport_data *data = state->data;
++
++		if (!data) {
++			if (cfg->hpd_event_trigger)
++				cfg->hpd_event_trigger(udphy, false);
++		} else if (data->status & DP_STATUS_IRQ_HPD) {
++			if (cfg->hpd_event_trigger) {
++				cfg->hpd_event_trigger(udphy, false);
++				usleep_range(750, 800);
++				cfg->hpd_event_trigger(udphy, true);
++			}
++		} else if (data->status & DP_STATUS_HPD_STATE) {
++			if (udphy->mode != mode) {
++				udphy->mode = mode;
++				udphy->mode_change = true;
++			}
++			if (cfg->hpd_event_trigger)
++				cfg->hpd_event_trigger(udphy, true);
++		} else {
++			if (cfg->hpd_event_trigger)
++				cfg->hpd_event_trigger(udphy, false);
++		}
++	}
++
++	mutex_unlock(&udphy->mutex);
++	return 0;
++}
++
++static int udphy_setup_typec_mux(struct rockchip_udphy *udphy)
++{
++	struct typec_mux_desc mux_desc = {};
++
++	mux_desc.drvdata = udphy;
++	mux_desc.fwnode = dev_fwnode(udphy->dev);
++	mux_desc.set = usbdp_typec_mux_set;
++
++	udphy->mux = typec_mux_register(udphy->dev, &mux_desc);
++	if (IS_ERR(udphy->mux)) {
++		dev_err(udphy->dev, "Error register typec mux: %ld\n",
++			PTR_ERR(udphy->mux));
++		return PTR_ERR(udphy->mux);
++	}
++
++	return 0;
++}
++
++static void udphy_typec_mux_unregister(void *data)
++{
++	struct rockchip_udphy *udphy = data;
++
++	typec_mux_unregister(udphy->mux);
++}
++
++static u32 udphy_dp_get_max_link_rate(struct rockchip_udphy *udphy, struct device_node *np)
++{
++	u32 max_link_rate;
++	int ret;
++
++	ret = of_property_read_u32(np, "max-link-rate", &max_link_rate);
++	if (ret)
++		return 8100;
++
++	ret = rockchip_dp_phy_verify_link_rate(max_link_rate);
++	if (ret) {
++		dev_warn(udphy->dev, "invalid max-link-rate value:%d\n", max_link_rate);
++		max_link_rate = 8100;
++	}
++
++	return max_link_rate;
++}
++
++static const struct regmap_config rockchip_udphy_pma_regmap_cfg = {
++	.reg_bits = 32,
++	.reg_stride = 4,
++	.val_bits = 32,
++	.fast_io = true,
++	.max_register = 0x20dc,
++};
++
++static int rockchip_udphy_probe(struct platform_device *pdev)
++{
++	struct device *dev = &pdev->dev;
++	struct device_node *np = dev->of_node;
++	struct device_node *child_np;
++	struct phy_provider *phy_provider;
++	struct resource *res;
++	struct rockchip_udphy *udphy;
++	const struct rockchip_udphy_cfg *phy_cfgs;
++	void __iomem *base;
++	int id, ret;
++
++	udphy = devm_kzalloc(dev, sizeof(*udphy), GFP_KERNEL);
++	if (!udphy)
++		return -ENOMEM;
++
++	id = of_alias_get_id(dev->of_node, "usbdp");
++	if (id < 0)
++		id = 0;
++	udphy->id = id;
++
++	phy_cfgs = of_device_get_match_data(dev);
++	if (!phy_cfgs) {
++		dev_err(dev, "no OF data can be matched with %p node\n", np);
++		return -EINVAL;
++	}
++
++	udphy->cfgs = phy_cfgs;
++
++	base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
++	if (IS_ERR(base))
++		return PTR_ERR(base);
++
++	udphy->pma_regmap = devm_regmap_init_mmio(dev, base + UDPHY_PMA,
++						  &rockchip_udphy_pma_regmap_cfg);
++	if (IS_ERR(udphy->pma_regmap))
++		return PTR_ERR(udphy->pma_regmap);
++
++	ret = udphy_parse_dt(udphy, dev);
++	if (ret)
++		return ret;
++
++	ret = udphy_get_initial_status(udphy);
++	if (ret)
++		return ret;
++
++	mutex_init(&udphy->mutex);
++	udphy->dev = dev;
++	platform_set_drvdata(pdev, udphy);
++
++	if (device_property_present(dev, "orientation-switch")) {
++		ret = udphy_setup_orien_switch(udphy);
++		if (ret)
++			return ret;
++
++		ret = devm_add_action_or_reset(dev, udphy_orien_switch_unregister, udphy);
++		if (ret)
++			return ret;
++	}
++
++	if (device_property_present(dev, "svid")) {
++		ret = udphy_setup_typec_mux(udphy);
++		if (ret)
++			return ret;
++
++		ret = devm_add_action_or_reset(dev, udphy_typec_mux_unregister, udphy);
++		if (ret)
++			return ret;
++	}
++
++	for_each_available_child_of_node(np, child_np) {
++		struct phy *phy;
++
++		if (of_node_name_eq(child_np, "dp-port")) {
++			phy = devm_phy_create(dev, child_np, &rockchip_dp_phy_ops);
++			if (IS_ERR(phy)) {
++				dev_err(dev, "failed to create dp phy: %pOFn\n", child_np);
++				goto put_child;
++			}
++
++			phy_set_bus_width(phy, udphy_dplane_get(udphy));
++			phy->attrs.max_link_rate = udphy_dp_get_max_link_rate(udphy, child_np);
++		} else if (of_node_name_eq(child_np, "usb3-port")) {
++			phy = devm_phy_create(dev, child_np, &rockchip_u3phy_ops);
++			if (IS_ERR(phy)) {
++				dev_err(dev, "failed to create usb phy: %pOFn\n", child_np);
++				goto put_child;
++			}
++		} else
++			continue;
++
++		phy_set_drvdata(phy, udphy);
++	}
++
++	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
++	if (IS_ERR(phy_provider)) {
++		dev_err(dev, "failed to register phy provider\n");
++		goto put_child;
++	}
++
++	return 0;
++
++put_child:
++	of_node_put(child_np);
++	return ret;
++}
++
++static int rk3588_udphy_refclk_set(struct rockchip_udphy *udphy)
++{
++	unsigned long rate;
++	int ret;
++
++	/* configure phy reference clock */
++	rate = clk_get_rate(udphy->refclk);
++	dev_dbg(udphy->dev, "refclk freq %ld\n", rate);
++
++	switch (rate) {
++	case 24000000:
++		ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_24m_refclk_cfg,
++					     ARRAY_SIZE(rk3588_udphy_24m_refclk_cfg));
++		if (ret)
++			return ret;
++		break;
++	case 26000000:
++		/* register default is 26MHz */
++		ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_26m_refclk_cfg,
++					     ARRAY_SIZE(rk3588_udphy_26m_refclk_cfg));
++		if (ret)
++			return ret;
++		break;
++	default:
++		dev_err(udphy->dev, "unsupported refclk freq %ld\n", rate);
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static int rk3588_udphy_status_check(struct rockchip_udphy *udphy)
++{
++	unsigned int val;
++	int ret;
++
++	/* LCPLL check */
++	if (udphy->mode & UDPHY_MODE_USB) {
++		ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_LCPLL_DONE_OFFSET,
++					       val, (val & CMN_ANA_LCPLL_AFC_DONE) &&
++					       (val & CMN_ANA_LCPLL_LOCK_DONE), 200, 100000);
++		if (ret) {
++			dev_err(udphy->dev, "cmn ana lcpll lock timeout\n");
++			return ret;
++		}
++	}
++
++	if (udphy->mode & UDPHY_MODE_USB) {
++		if (!udphy->flip) {
++			ret = regmap_read_poll_timeout(udphy->pma_regmap,
++						       TRSV_LN0_MON_RX_CDR_DONE_OFFSET, val,
++						       val & TRSV_LN0_MON_RX_CDR_LOCK_DONE,
++						       200, 100000);
++			if (ret)
++				dev_err(udphy->dev, "trsv ln0 mon rx cdr lock timeout\n");
++		} else {
++			ret = regmap_read_poll_timeout(udphy->pma_regmap,
++						       TRSV_LN2_MON_RX_CDR_DONE_OFFSET, val,
++						       val & TRSV_LN2_MON_RX_CDR_LOCK_DONE,
++						       200, 100000);
++			if (ret)
++				dev_err(udphy->dev, "trsv ln2 mon rx cdr lock timeout\n");
++		}
++	}
++
++	return 0;
++}
++
++static int rk3588_udphy_init(struct rockchip_udphy *udphy)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	int ret;
++
++	/* enable rx lfps for usb */
++	if (udphy->mode & UDPHY_MODE_USB)
++		grfreg_write(udphy->udphygrf, &cfg->grfcfg.rx_lfps, true);
++
++	/* Step 1: power on pma and deassert apb rstn */
++	grfreg_write(udphy->udphygrf, &cfg->grfcfg.low_pwrn, true);
++
++	udphy_reset_deassert(udphy, "pma_apb");
++	udphy_reset_deassert(udphy, "pcs_apb");
++
++	/* Step 2: set init sequence and phy refclk */
++	ret = regmap_multi_reg_write(udphy->pma_regmap, rk3588_udphy_init_sequence,
++				     ARRAY_SIZE(rk3588_udphy_init_sequence));
++	if (ret) {
++		dev_err(udphy->dev, "init sequence set error %d\n", ret);
++		goto assert_apb;
++	}
++
++	ret = rk3588_udphy_refclk_set(udphy);
++	if (ret) {
++		dev_err(udphy->dev, "refclk set error %d\n", ret);
++		goto assert_apb;
++	}
++
++	/* Step 3: configure lane mux */
++	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET,
++			   CMN_DP_LANE_MUX_ALL | CMN_DP_LANE_EN_ALL,
++			   FIELD_PREP(CMN_DP_LANE_MUX_N(3), udphy->lane_mux_sel[3]) |
++			   FIELD_PREP(CMN_DP_LANE_MUX_N(2), udphy->lane_mux_sel[2]) |
++			   FIELD_PREP(CMN_DP_LANE_MUX_N(1), udphy->lane_mux_sel[1]) |
++			   FIELD_PREP(CMN_DP_LANE_MUX_N(0), udphy->lane_mux_sel[0]) |
++			   FIELD_PREP(CMN_DP_LANE_EN_ALL, 0));
++
++	/* Step 4: deassert init rstn and wait for 200ns from datasheet */
++	if (udphy->mode & UDPHY_MODE_USB)
++		udphy_reset_deassert(udphy, "init");
++
++	if (udphy->mode & UDPHY_MODE_DP) {
++		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
++				   CMN_DP_INIT_RSTN,
++				   FIELD_PREP(CMN_DP_INIT_RSTN, 0x1));
++	}
++
++	udelay(1);
++
++	/*  Step 5: deassert cmn/lane rstn */
++	if (udphy->mode & UDPHY_MODE_USB) {
++		udphy_reset_deassert(udphy, "cmn");
++		udphy_reset_deassert(udphy, "lane");
++	}
++
++	/*  Step 6: wait for lock done of pll */
++	ret = rk3588_udphy_status_check(udphy);
++	if (ret)
++		goto assert_phy;
++
++	return 0;
++
++assert_phy:
++	udphy_reset_assert(udphy, "init");
++	udphy_reset_assert(udphy, "cmn");
++	udphy_reset_assert(udphy, "lane");
++
++assert_apb:
++	udphy_reset_assert(udphy, "pma_apb");
++	udphy_reset_assert(udphy, "pcs_apb");
++	return ret;
++}
++
++static int rk3588_udphy_hpd_event_trigger(struct rockchip_udphy *udphy, bool hpd)
++{
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++
++	udphy->dp_sink_hpd_sel = true;
++	udphy->dp_sink_hpd_cfg = hpd;
++
++	grfreg_write(udphy->vogrf, &cfg->vogrfcfg[udphy->id].hpd_trigger, hpd);
++
++	return 0;
++}
++
++static int rk3588_udphy_dplane_enable(struct rockchip_udphy *udphy, int dp_lanes)
++{
++	int i;
++	u32 val = 0;
++
++	for (i = 0; i < dp_lanes; i++)
++		val |= BIT(udphy->dp_lane_sel[i]);
++
++	regmap_update_bits(udphy->pma_regmap, CMN_LANE_MUX_AND_EN_OFFSET, CMN_DP_LANE_EN_ALL,
++			   FIELD_PREP(CMN_DP_LANE_EN_ALL, val));
++
++	if (!dp_lanes)
++		regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
++				   CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
++
++	return 0;
++}
++
++static int rk3588_udphy_dplane_select(struct rockchip_udphy *udphy)
++{
++	u32 value = 0;
++
++	switch (udphy->mode) {
++	case UDPHY_MODE_DP:
++		value |= 2 << udphy->dp_lane_sel[2] * 2;
++		value |= 3 << udphy->dp_lane_sel[3] * 2;
++		fallthrough;
++	case UDPHY_MODE_DP_USB:
++		value |= 0 << udphy->dp_lane_sel[0] * 2;
++		value |= 1 << udphy->dp_lane_sel[1] * 2;
++		break;
++	case UDPHY_MODE_USB:
++		break;
++	default:
++		break;
++	}
++
++	regmap_write(udphy->vogrf, udphy->id ? RK3588_GRF_VO0_CON2 : RK3588_GRF_VO0_CON0,
++		     ((DP_AUX_DIN_SEL | DP_AUX_DOUT_SEL | DP_LANE_SEL_ALL) << 16) |
++		     FIELD_PREP(DP_AUX_DIN_SEL, udphy->dp_aux_din_sel) |
++		     FIELD_PREP(DP_AUX_DOUT_SEL, udphy->dp_aux_dout_sel) | value);
++
++	return 0;
++}
++
++static int rk3588_dp_phy_set_rate(struct rockchip_udphy *udphy,
++				  struct phy_configure_opts_dp *dp)
++{
++	u32 val;
++	int ret;
++
++	regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET,
++			   CMN_DP_CMN_RSTN, FIELD_PREP(CMN_DP_CMN_RSTN, 0x0));
++
++	switch (dp->link_rate) {
++	case 1620:
++		udphy->bw = DP_BW_RBR;
++		break;
++	case 2700:
++		udphy->bw = DP_BW_HBR;
++		break;
++	case 5400:
++		udphy->bw = DP_BW_HBR2;
++		break;
++	case 8100:
++		udphy->bw = DP_BW_HBR3;
++		break;
++	default:
++		return -EINVAL;
++	}
++
++	regmap_update_bits(udphy->pma_regmap, CMN_DP_LINK_OFFSET, CMN_DP_TX_LINK_BW,
++			   FIELD_PREP(CMN_DP_TX_LINK_BW, udphy->bw));
++	regmap_update_bits(udphy->pma_regmap, CMN_SSC_EN_OFFSET, CMN_ROPLL_SSC_EN,
++			   FIELD_PREP(CMN_ROPLL_SSC_EN, dp->ssc));
++	regmap_update_bits(udphy->pma_regmap, CMN_DP_RSTN_OFFSET, CMN_DP_CMN_RSTN,
++			   FIELD_PREP(CMN_DP_CMN_RSTN, 0x1));
++
++	ret = regmap_read_poll_timeout(udphy->pma_regmap, CMN_ANA_ROPLL_DONE_OFFSET, val,
++				       FIELD_GET(CMN_ANA_ROPLL_LOCK_DONE, val) &&
++				       FIELD_GET(CMN_ANA_ROPLL_AFC_DONE, val),
++				       0, 1000);
++	if (ret) {
++		dev_err(udphy->dev, "ROPLL is not lock\n");
++		return ret;
++	}
++
++	return 0;
++}
++
++static void rk3588_dp_phy_set_voltage(struct rockchip_udphy *udphy, u8 bw,
++				      u32 voltage, u32 pre, u32 lane)
++{
++	u32 offset = 0x800 * lane;
++	u32 val;
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++	const struct dp_tx_drv_ctrl (*dp_ctrl)[4];
++
++	dp_ctrl = udphy->mux ? cfg->dp_tx_ctrl_cfg_typec[bw] : cfg->dp_tx_ctrl_cfg[bw];
++	val = dp_ctrl[voltage][pre].trsv_reg0204;
++	regmap_write(udphy->pma_regmap, 0x0810 + offset, val);
++
++	val = dp_ctrl[voltage][pre].trsv_reg0205;
++	regmap_write(udphy->pma_regmap, 0x0814 + offset, val);
++
++	val = dp_ctrl[voltage][pre].trsv_reg0206;
++	regmap_write(udphy->pma_regmap, 0x0818 + offset, val);
++
++	val = dp_ctrl[voltage][pre].trsv_reg0207;
++	regmap_write(udphy->pma_regmap, 0x081c + offset, val);
++}
++
++static int rk3588_dp_phy_set_voltages(struct rockchip_udphy *udphy,
++				      struct phy_configure_opts_dp *dp)
++{
++	u32 i, lane;
++
++	for (i = 0; i < dp->lanes; i++) {
++		lane = udphy->dp_lane_sel[i];
++		switch (dp->link_rate) {
++		case 1620:
++		case 2700:
++			regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
++					   LN_ANA_TX_SER_TXCLK_INV,
++					   FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV,
++					   udphy->lane_mux_sel[lane]));
++			break;
++		case 5400:
++		case 8100:
++			regmap_update_bits(udphy->pma_regmap, TRSV_ANA_TX_CLK_OFFSET_N(lane),
++					   LN_ANA_TX_SER_TXCLK_INV,
++					   FIELD_PREP(LN_ANA_TX_SER_TXCLK_INV, 0x0));
++			break;
++		}
++
++		rk3588_dp_phy_set_voltage(udphy, udphy->bw, dp->voltage[i], dp->pre[i], lane);
++	}
++
++	return 0;
++}
++
++static int __maybe_unused udphy_resume(struct device *dev)
++{
++	struct rockchip_udphy *udphy = dev_get_drvdata(dev);
++	const struct rockchip_udphy_cfg *cfg = udphy->cfgs;
++
++	if (udphy->dp_sink_hpd_sel)
++		cfg->hpd_event_trigger(udphy, udphy->dp_sink_hpd_cfg);
++
++	return 0;
++}
++
++static const struct dev_pm_ops udphy_pm_ops = {
++	SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, udphy_resume)
++};
++
++static const char * const rk3588_udphy_rst_l[] = {
++	"init", "cmn", "lane", "pcs_apb", "pma_apb"
++};
++
++static const struct rockchip_udphy_cfg rk3588_udphy_cfgs = {
++	.num_rsts = ARRAY_SIZE(rk3588_udphy_rst_l),
++	.rst_list = rk3588_udphy_rst_l,
++	.grfcfg	= {
++		/* u2phy-grf */
++		.bvalid_phy_con		= { 0x0008, 1, 0, 0x2, 0x3 },
++		.bvalid_grf_con		= { 0x0010, 3, 2, 0x2, 0x3 },
++
++		/* usb-grf */
++		.usb3otg0_cfg		= { 0x001c, 15, 0, 0x1100, 0x0188 },
++		.usb3otg1_cfg		= { 0x0034, 15, 0, 0x1100, 0x0188 },
++
++		/* usbdpphy-grf */
++		.low_pwrn		= { 0x0004, 13, 13, 0, 1 },
++		.rx_lfps		= { 0x0004, 14, 14, 0, 1 },
++	},
++	.vogrfcfg = {
++		{
++			.hpd_trigger	= { 0x0000, 11, 10, 1, 3 },
++		},
++		{
++			.hpd_trigger	= { 0x0008, 11, 10, 1, 3 },
++		},
++	},
++	.dp_tx_ctrl_cfg = {
++		rk3588_dp_tx_drv_ctrl_rbr_hbr,
++		rk3588_dp_tx_drv_ctrl_rbr_hbr,
++		rk3588_dp_tx_drv_ctrl_hbr2,
++		rk3588_dp_tx_drv_ctrl_hbr3,
++	},
++	.dp_tx_ctrl_cfg_typec = {
++		rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++		rk3588_dp_tx_drv_ctrl_rbr_hbr_typec,
++		rk3588_dp_tx_drv_ctrl_hbr2,
++		rk3588_dp_tx_drv_ctrl_hbr3,
++	},
++	.combophy_init = rk3588_udphy_init,
++	.dp_phy_set_rate = rk3588_dp_phy_set_rate,
++	.dp_phy_set_voltages = rk3588_dp_phy_set_voltages,
++	.hpd_event_trigger = rk3588_udphy_hpd_event_trigger,
++	.dplane_enable = rk3588_udphy_dplane_enable,
++	.dplane_select = rk3588_udphy_dplane_select,
++};
++
++static const struct of_device_id rockchip_udphy_dt_match[] = {
++	{
++		.compatible = "rockchip,rk3588-usbdp-phy",
++		.data = &rk3588_udphy_cfgs
++	},
++	{ /* sentinel */ }
++};
++
++MODULE_DEVICE_TABLE(of, rockchip_udphy_dt_match);
++
++static struct platform_driver rockchip_udphy_driver = {
++	.probe		= rockchip_udphy_probe,
++	.driver		= {
++		.name	= "rockchip-usbdp-phy",
++		.of_match_table = rockchip_udphy_dt_match,
++		.pm = &udphy_pm_ops,
++	},
++};
++
++module_platform_driver(rockchip_udphy_driver);
++
++MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
++MODULE_AUTHOR("Zhang Yubing <yubing.zhang@rock-chips.com>");
++MODULE_DESCRIPTION("Rockchip USBDP Combo PHY driver");
++MODULE_LICENSE("GPL v2");
diff --git a/target/linux/rockchip/patches-6.1/296-dt-bindings-phy-add-rockchip-usbdp-combo-phy-documen.patch b/target/linux/rockchip/patches-6.1/296-dt-bindings-phy-add-rockchip-usbdp-combo-phy-documen.patch
new file mode 100644
index 00000000000..e21f899adfd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/296-dt-bindings-phy-add-rockchip-usbdp-combo-phy-documen.patch
@@ -0,0 +1,166 @@
+From 6a6b43f1246a756b6f6270e73f706c374a108e29 Mon Sep 17 00:00:00 2001
+From: Frank Wang <frank.wang@rock-chips.com>
+Date: Tue, 25 Apr 2023 17:38:57 +0200
+Subject: [PATCH 296/383] dt-bindings: phy: add rockchip usbdp combo phy
+ document
+
+Add device tree binding document for Rockchip USBDP Combo PHY
+with Samsung IP block.
+
+Signed-off-by: Frank Wang <frank.wang@rock-chips.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../bindings/phy/phy-rockchip-usbdp.yaml      | 146 ++++++++++++++++++
+ 1 file changed, 146 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/phy/phy-rockchip-usbdp.yaml
+@@ -0,0 +1,146 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/phy/phy-rockchip-usbdp.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip USBDP Combo PHY with Samsung IP block
++
++maintainers:
++  - Frank Wang <frank.wang@rock-chips.com>
++  - Zhang Yubing <yubing.zhang@rock-chips.com>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3588-usbdp-phy
++
++  reg:
++    maxItems: 1
++
++  clocks:
++    items:
++      - description: phy ref clock.
++      - description: phy pcs immortal clock.
++      - description: phy peripheral clock.
++
++  clock-names:
++    items:
++      - const: refclk
++      - const: immortal
++      - const: pclk
++
++  resets:
++      - description: phy init reset.
++      - description: phy cmn reset.
++      - description: phy lane reset.
++      - description: phy pcs apb reset.
++      - description: phy pma apb reset.
++
++  reset-names:
++      - const: init
++      - const: cmn
++      - const: lane
++      - const: pcs_apb
++      - const: pma_apb
++
++  rockchip,dp-lane-mux:
++    minItems: 2
++    maxItems: 4
++    description:
++      An array of physical Tyep-C lanes indexes. Position of an entry determines
++      the dp lane index, while the value of an entry indicater physical Type-C lane.
++      The support dp lanes number are 2 or 4. e.g. for 2 lanes dp lanes map, we could
++      have "rockchip,dp-lane-mux = <2, 3>;", assuming dp lane0 on Type-C phy lane2,
++      dp lane1 on Type-C phy lane3. For 4 lanes dp lanes map, we could have
++      "rockchip,dp-lane-mux = <0, 1, 2, 3>;", assuming dp lane0 on Type-C phy lane0,
++      dp lane1 on Type-C phy lane1, dp lane2 on Type-C phy lane2, dp lane3 on Type-C
++      phy lane3. If dp lane map by DisplayPort Alt mode, this property is not need.
++
++  rockchip,u2phy-grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to the syscon managing the 'usb2 phy general register files'.
++
++  rockchip,usb-grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to the syscon managing the 'usb general register files'.
++
++  rockchip,usbdpphy-grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to the syscon managing the 'usbdp phy general register files'.
++
++  rockchip,vo-grf:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to the syscon managing the 'video output general register files'.
++      When select the dp lane mapping will request its phandle.
++
++  dp-port:
++    type: object
++    additionalProperties: false
++
++    properties:
++      "#phy-cells":
++        const: 0
++
++    required:
++      - "#phy-cells"
++
++  usb3-port:
++    type: object
++    additionalProperties: false
++
++    properties:
++      "#phy-cells":
++        const: 0
++
++    required:
++      - "#phy-cells"
++
++required:
++  - compatible
++  - reg
++  - clocks
++  - clock-names
++  - resets
++  - reset-names
++  - dp-port
++  - usb3-port
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/clock/rk3588-cru.h>
++
++    usbdp_phy0: phy@fed80000 {
++      compatible = "rockchip,rk3588-usbdp-phy";
++      reg = <0x0 0xfed80000 0x0 0x10000>;
++      rockchip,u2phy-grf = <&usb2phy0_grf>;
++      rockchip,usb-grf = <&usb_grf>;
++      rockchip,usbdpphy-grf = <&usbdpphy0_grf>;
++      rockchip,vo-grf = <&vo0_grf>;
++      clocks = <&cru CLK_USBDPPHY_MIPIDCPPHY_REF>,
++               <&cru CLK_USBDP_PHY0_IMMORTAL>,
++               <&cru PCLK_USBDPPHY0>;
++      clock-names = "refclk", "immortal", "pclk";
++      resets = <&cru SRST_USBDP_COMBO_PHY0_INIT>,
++               <&cru SRST_USBDP_COMBO_PHY0_CMN>,
++               <&cru SRST_USBDP_COMBO_PHY0_LANE>,
++               <&cru SRST_USBDP_COMBO_PHY0_PCS>,
++               <&cru SRST_P_USBDPPHY0>;
++      reset-names = "init", "cmn", "lane", "pcs_apb", "pma_apb";
++      status = "disabled";
++
++      usbdp_phy0_dp: dp-port {
++        #phy-cells = <0>;
++        status = "disabled";
++      };
++
++      usbdp_phy0_u3: usb3-port {
++        #phy-cells = <0>;
++        status = "disabled";
++    };
diff --git a/target/linux/rockchip/patches-6.1/167-crypto-rockchip-use-dev_err-for-error-message-about-.patch b/target/linux/rockchip/patches-6.1/297-crypto-rockchip-use-dev_err-for-error-message-about-.patch
similarity index 80%
rename from target/linux/rockchip/patches-6.1/167-crypto-rockchip-use-dev_err-for-error-message-about-.patch
rename to target/linux/rockchip/patches-6.1/297-crypto-rockchip-use-dev_err-for-error-message-about-.patch
index 8f60539397d..cf0ab145480 100644
--- a/target/linux/rockchip/patches-6.1/167-crypto-rockchip-use-dev_err-for-error-message-about-.patch
+++ b/target/linux/rockchip/patches-6.1/297-crypto-rockchip-use-dev_err-for-error-message-about-.patch
@@ -1,13 +1,14 @@
-From 5b85875f5b63720c85f525a0b94054041ca2a118 Mon Sep 17 00:00:00 2001
+From c0f99b22e8c9b5595650726747c76f2f692dba9e Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:39 +0000
-Subject: [PATCH 17/49] crypto: rockchip: use dev_err for error message about
+Subject: [PATCH 297/383] crypto: rockchip: use dev_err for error message about
  interrupt
 
 Interrupt is mandatory so the message should be printed as error.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 3 +--
  1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/168-crypto-rockchip-do-not-use-uninitialized-variable.patch b/target/linux/rockchip/patches-6.1/298-crypto-rockchip-do-not-use-uninitialized-variable.patch
similarity index 78%
rename from target/linux/rockchip/patches-6.1/168-crypto-rockchip-do-not-use-uninitialized-variable.patch
rename to target/linux/rockchip/patches-6.1/298-crypto-rockchip-do-not-use-uninitialized-variable.patch
index e487746a76c..045c35cc3c1 100644
--- a/target/linux/rockchip/patches-6.1/168-crypto-rockchip-do-not-use-uninitialized-variable.patch
+++ b/target/linux/rockchip/patches-6.1/298-crypto-rockchip-do-not-use-uninitialized-variable.patch
@@ -1,12 +1,13 @@
-From ccd6a7fd0b6afdfa47d3b4f6b850127031effc1f Mon Sep 17 00:00:00 2001
+From 122c64319bce419be4b041b2213995854669d3fc Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:40 +0000
-Subject: [PATCH 18/49] crypto: rockchip: do not use uninitialized variable
+Subject: [PATCH 298/383] crypto: rockchip: do not use uninitialized variable
 
 crypto_info->dev is not yet set, so use pdev->dev instead.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/linux/rockchip/patches-6.1/170-crypto-rockchip-fix-privete-private-typo.patch b/target/linux/rockchip/patches-6.1/299-crypto-rockchip-fix-privete-private-typo.patch
similarity index 79%
rename from target/linux/rockchip/patches-6.1/170-crypto-rockchip-fix-privete-private-typo.patch
rename to target/linux/rockchip/patches-6.1/299-crypto-rockchip-fix-privete-private-typo.patch
index e32a6e57c40..67de6b76942 100644
--- a/target/linux/rockchip/patches-6.1/170-crypto-rockchip-fix-privete-private-typo.patch
+++ b/target/linux/rockchip/patches-6.1/299-crypto-rockchip-fix-privete-private-typo.patch
@@ -1,12 +1,13 @@
-From 7ea605d0e8b85ffac2bf152be86d010d9eac0193 Mon Sep 17 00:00:00 2001
+From 6cc93254c411d5c17f706f75a9f315d9bf76d30d Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:42 +0000
-Subject: [PATCH 20/49] crypto: rockchip: fix privete/private typo
+Subject: [PATCH 299/383] crypto: rockchip: fix privete/private typo
 
 This fix a simple typo on private word.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.h | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/linux/rockchip/patches-6.1/177-crypto-rockchip-rewrite-type.patch b/target/linux/rockchip/patches-6.1/300-crypto-rockchip-rewrite-type.patch
similarity index 97%
rename from target/linux/rockchip/patches-6.1/177-crypto-rockchip-rewrite-type.patch
rename to target/linux/rockchip/patches-6.1/300-crypto-rockchip-rewrite-type.patch
index 032310fb6d9..92f3451d73c 100644
--- a/target/linux/rockchip/patches-6.1/177-crypto-rockchip-rewrite-type.patch
+++ b/target/linux/rockchip/patches-6.1/300-crypto-rockchip-rewrite-type.patch
@@ -1,7 +1,7 @@
-From b9d97d2708d9ae617a3bb7bbb91ca543c486f337 Mon Sep 17 00:00:00 2001
+From 7df633086eca7e9a080b3c31edca9c7485ef288a Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:49 +0000
-Subject: [PATCH 27/49] crypto: rockchip: rewrite type
+Subject: [PATCH 300/383] crypto: rockchip: rewrite type
 
 Instead of using a custom type for classify algorithms, let's just use
 already defined ones.
@@ -9,6 +9,7 @@ And let's made a bit more verbose about what is registered.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c       | 26 +++++++++++++------
  drivers/crypto/rockchip/rk3288_crypto.h       |  7 +----
diff --git a/target/linux/rockchip/patches-6.1/178-crypto-rockchip-add-debugfs.patch b/target/linux/rockchip/patches-6.1/301-crypto-rockchip-add-debugfs.patch
similarity index 97%
rename from target/linux/rockchip/patches-6.1/178-crypto-rockchip-add-debugfs.patch
rename to target/linux/rockchip/patches-6.1/301-crypto-rockchip-add-debugfs.patch
index 0ff54cc53a1..bade36d4d79 100644
--- a/target/linux/rockchip/patches-6.1/178-crypto-rockchip-add-debugfs.patch
+++ b/target/linux/rockchip/patches-6.1/301-crypto-rockchip-add-debugfs.patch
@@ -1,12 +1,13 @@
-From ca19c52753332836704019bc5f423b054ea2616b Mon Sep 17 00:00:00 2001
+From cf79ab946d3cf92b907135d9651829bf6b99e2c3 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:50 +0000
-Subject: [PATCH 28/49] crypto: rockchip: add debugfs
+Subject: [PATCH 301/383] crypto: rockchip: add debugfs
 
 This patch enable to access usage stats for each algorithm.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/Kconfig                        | 10 ++++
  drivers/crypto/rockchip/rk3288_crypto.c       | 47 +++++++++++++++++++
diff --git a/target/linux/rockchip/patches-6.1/179-crypto-rockchip-introduce-PM.patch b/target/linux/rockchip/patches-6.1/302-crypto-rockchip-introduce-PM.patch
similarity index 96%
rename from target/linux/rockchip/patches-6.1/179-crypto-rockchip-introduce-PM.patch
rename to target/linux/rockchip/patches-6.1/302-crypto-rockchip-introduce-PM.patch
index afe2a9a68c5..398cfaa1d3a 100644
--- a/target/linux/rockchip/patches-6.1/179-crypto-rockchip-introduce-PM.patch
+++ b/target/linux/rockchip/patches-6.1/302-crypto-rockchip-introduce-PM.patch
@@ -1,12 +1,13 @@
-From a8a988a5e67068b554f92418775f274771cfb068 Mon Sep 17 00:00:00 2001
+From e99e91bc798c892fb202087a7667c6d4240306a4 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:51 +0000
-Subject: [PATCH 29/49] crypto: rockchip: introduce PM
+Subject: [PATCH 302/383] crypto: rockchip: introduce PM
 
 Add runtime PM support for rockchip crypto.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c       | 51 ++++++++++++++++++-
  drivers/crypto/rockchip/rk3288_crypto.h       |  1 +
diff --git a/target/linux/rockchip/patches-6.1/180-crypto-rockchip-handle-reset-also-in-PM.patch b/target/linux/rockchip/patches-6.1/303-crypto-rockchip-handle-reset-also-in-PM.patch
similarity index 90%
rename from target/linux/rockchip/patches-6.1/180-crypto-rockchip-handle-reset-also-in-PM.patch
rename to target/linux/rockchip/patches-6.1/303-crypto-rockchip-handle-reset-also-in-PM.patch
index 5c7e6953f1b..ade056ee2d7 100644
--- a/target/linux/rockchip/patches-6.1/180-crypto-rockchip-handle-reset-also-in-PM.patch
+++ b/target/linux/rockchip/patches-6.1/303-crypto-rockchip-handle-reset-also-in-PM.patch
@@ -1,13 +1,14 @@
-From e1d7ad70ff4447218815f3b9427ee7cd8cc6836b Mon Sep 17 00:00:00 2001
+From 4f92fd4d67460f440bbace248c00edd5dc0fd580 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:52 +0000
-Subject: [PATCH 30/49] crypto: rockchip: handle reset also in PM
+Subject: [PATCH 303/383] crypto: rockchip: handle reset also in PM
 
 reset could be handled by PM functions.
 We keep the initial reset pulse to be sure the hw is a know device state
 after probe.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 22 ++++++++++------------
  1 file changed, 10 insertions(+), 12 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/181-crypto-rockchip-use-clk_bulk-to-simplify-clock-manag.patch b/target/linux/rockchip/patches-6.1/304-crypto-rockchip-use-clk_bulk-to-simplify-clock-manag.patch
similarity index 94%
rename from target/linux/rockchip/patches-6.1/181-crypto-rockchip-use-clk_bulk-to-simplify-clock-manag.patch
rename to target/linux/rockchip/patches-6.1/304-crypto-rockchip-use-clk_bulk-to-simplify-clock-manag.patch
index 2caf7f6c84f..c5b193b5732 100644
--- a/target/linux/rockchip/patches-6.1/181-crypto-rockchip-use-clk_bulk-to-simplify-clock-manag.patch
+++ b/target/linux/rockchip/patches-6.1/304-crypto-rockchip-use-clk_bulk-to-simplify-clock-manag.patch
@@ -1,7 +1,7 @@
-From b388e1b6a75d477735f7e2b90130169638b72c37 Mon Sep 17 00:00:00 2001
+From 0a685107d61d6e4e2d5251f43a0a430bb75b00c3 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:53 +0000
-Subject: [PATCH 31/49] crypto: rockchip: use clk_bulk to simplify clock
+Subject: [PATCH 304/383] crypto: rockchip: use clk_bulk to simplify clock
  management
 
 rk3328 does not have the same clock names than rk3288, instead of using a complex
@@ -9,6 +9,7 @@ clock management, let's use clk_bulk to simplify their handling.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 66 ++++---------------------
  drivers/crypto/rockchip/rk3288_crypto.h |  6 +--
diff --git a/target/linux/rockchip/patches-6.1/182-crypto-rockchip-add-myself-as-maintainer.patch b/target/linux/rockchip/patches-6.1/305-crypto-rockchip-add-myself-as-maintainer.patch
similarity index 76%
rename from target/linux/rockchip/patches-6.1/182-crypto-rockchip-add-myself-as-maintainer.patch
rename to target/linux/rockchip/patches-6.1/305-crypto-rockchip-add-myself-as-maintainer.patch
index d36e8024999..3dbb1c86454 100644
--- a/target/linux/rockchip/patches-6.1/182-crypto-rockchip-add-myself-as-maintainer.patch
+++ b/target/linux/rockchip/patches-6.1/305-crypto-rockchip-add-myself-as-maintainer.patch
@@ -1,20 +1,21 @@
-From 771d6ebe99b61c1b143feab92e896fecc6ba16d0 Mon Sep 17 00:00:00 2001
+From 6d5b834b49c996c71bed2d005fefc48813931e75 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:54 +0000
-Subject: [PATCH 32/49] crypto: rockchip: add myself as maintainer
+Subject: [PATCH 305/383] crypto: rockchip: add myself as maintainer
 
 Nobody is set as maintainer of rockchip crypto, I propose to do it as I
 have already reworked lot of this code.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  MAINTAINERS | 7 +++++++
  1 file changed, 7 insertions(+)
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17797,6 +17797,13 @@ F:	Documentation/ABI/*/sysfs-driver-hid-
+@@ -17799,6 +17799,13 @@ F:	Documentation/ABI/*/sysfs-driver-hid-
  F:	drivers/hid/hid-roccat*
  F:	include/linux/hid-roccat*
  
diff --git a/target/linux/rockchip/patches-6.1/183-crypto-rockchip-use-read_poll_timeout.patch b/target/linux/rockchip/patches-6.1/306-crypto-rockchip-use-read_poll_timeout.patch
similarity index 90%
rename from target/linux/rockchip/patches-6.1/183-crypto-rockchip-use-read_poll_timeout.patch
rename to target/linux/rockchip/patches-6.1/306-crypto-rockchip-use-read_poll_timeout.patch
index b1ae94d2e44..42d8027b64f 100644
--- a/target/linux/rockchip/patches-6.1/183-crypto-rockchip-use-read_poll_timeout.patch
+++ b/target/linux/rockchip/patches-6.1/306-crypto-rockchip-use-read_poll_timeout.patch
@@ -1,13 +1,14 @@
-From f7d1ea66d097a14e2c8dd312f2360db746db055f Mon Sep 17 00:00:00 2001
+From 2ca8e662ea1e7dabc54fd143846024e095671f9e Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:55 +0000
-Subject: [PATCH 33/49] crypto: rockchip: use read_poll_timeout
+Subject: [PATCH 306/383] crypto: rockchip: use read_poll_timeout
 
 Use read_poll_timeout instead of open coding it.
 In the same time, fix indentation of related comment.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto_ahash.c | 24 +++++++++----------
  1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/184-crypto-rockchip-fix-style-issue.patch b/target/linux/rockchip/patches-6.1/307-crypto-rockchip-fix-style-issue.patch
similarity index 89%
rename from target/linux/rockchip/patches-6.1/184-crypto-rockchip-fix-style-issue.patch
rename to target/linux/rockchip/patches-6.1/307-crypto-rockchip-fix-style-issue.patch
index 4c6d89be1d1..edd7de69f01 100644
--- a/target/linux/rockchip/patches-6.1/184-crypto-rockchip-fix-style-issue.patch
+++ b/target/linux/rockchip/patches-6.1/307-crypto-rockchip-fix-style-issue.patch
@@ -1,12 +1,13 @@
-From ce5aef761e09d6f17ed8f3e0dae3bf90fb06a838 Mon Sep 17 00:00:00 2001
+From 73aba3ceda56054ee3570c4ad60ddf20c43392e2 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:56 +0000
-Subject: [PATCH 34/49] crypto: rockchip: fix style issue
+Subject: [PATCH 307/383] crypto: rockchip: fix style issue
 
 This patch fixes some warning reported by checkpatch
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto_ahash.c | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/185-crypto-rockchip-add-support-for-rk3328.patch b/target/linux/rockchip/patches-6.1/308-crypto-rockchip-add-support-for-rk3328.patch
similarity index 79%
rename from target/linux/rockchip/patches-6.1/185-crypto-rockchip-add-support-for-rk3328.patch
rename to target/linux/rockchip/patches-6.1/308-crypto-rockchip-add-support-for-rk3328.patch
index 7319de60382..4f226720f6e 100644
--- a/target/linux/rockchip/patches-6.1/185-crypto-rockchip-add-support-for-rk3328.patch
+++ b/target/linux/rockchip/patches-6.1/308-crypto-rockchip-add-support-for-rk3328.patch
@@ -1,12 +1,13 @@
-From 50f01f648e6cc3d2b20674b50b662290c98e9041 Mon Sep 17 00:00:00 2001
+From 08598edd4feb6ae049077dc10d2e26cf570ce9f3 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:57 +0000
-Subject: [PATCH 35/49] crypto: rockchip: add support for rk3328
+Subject: [PATCH 308/383] crypto: rockchip: add support for rk3328
 
 The rk3328 could be used as-is by the rockchip driver.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 1 +
  1 file changed, 1 insertion(+)
diff --git a/target/linux/rockchip/patches-6.1/186-crypto-rockchip-rename-ablk-functions-to-cipher.patch b/target/linux/rockchip/patches-6.1/309-crypto-rockchip-rename-ablk-functions-to-cipher.patch
similarity index 95%
rename from target/linux/rockchip/patches-6.1/186-crypto-rockchip-rename-ablk-functions-to-cipher.patch
rename to target/linux/rockchip/patches-6.1/309-crypto-rockchip-rename-ablk-functions-to-cipher.patch
index bc63375698a..30de2b61fca 100644
--- a/target/linux/rockchip/patches-6.1/186-crypto-rockchip-rename-ablk-functions-to-cipher.patch
+++ b/target/linux/rockchip/patches-6.1/309-crypto-rockchip-rename-ablk-functions-to-cipher.patch
@@ -1,7 +1,7 @@
-From d6996995f04ac2be833d87b94e78aa532ed9ee16 Mon Sep 17 00:00:00 2001
+From 1db8d3dda917510fdda9c63b5c11a782994994b3 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:58 +0000
-Subject: [PATCH 36/49] crypto: rockchip: rename ablk functions to cipher
+Subject: [PATCH 309/383] crypto: rockchip: rename ablk functions to cipher
 
 Some functions have still ablk in their name even if there are
 not handling ablk_cipher anymore.
@@ -9,6 +9,7 @@ So let's rename them.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  .../crypto/rockchip/rk3288_crypto_skcipher.c  | 32 +++++++++----------
  1 file changed, 16 insertions(+), 16 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/187-crypto-rockchip-rework-rk_handle_req-function.patch b/target/linux/rockchip/patches-6.1/310-crypto-rockchip-rework-rk_handle_req-function.patch
similarity index 97%
rename from target/linux/rockchip/patches-6.1/187-crypto-rockchip-rework-rk_handle_req-function.patch
rename to target/linux/rockchip/patches-6.1/310-crypto-rockchip-rework-rk_handle_req-function.patch
index 136423a6663..2bd171d8e07 100644
--- a/target/linux/rockchip/patches-6.1/187-crypto-rockchip-rework-rk_handle_req-function.patch
+++ b/target/linux/rockchip/patches-6.1/310-crypto-rockchip-rework-rk_handle_req-function.patch
@@ -1,13 +1,14 @@
-From d294827ca9bf9c9a893ea0b70f5cec93a3248706 Mon Sep 17 00:00:00 2001
+From 92ec7b16d9ab4b37af4cccabb5278b7d307a20ad Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:54:59 +0000
-Subject: [PATCH 37/49] crypto: rockchip: rework rk_handle_req function
+Subject: [PATCH 310/383] crypto: rockchip: rework rk_handle_req function
 
 This patch rework the rk_handle_req(), simply removing the
 rk_crypto_info parameter.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  .../crypto/rockchip/rk3288_crypto_skcipher.c  | 68 +++++--------------
  1 file changed, 17 insertions(+), 51 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/188-crypto-rockchip-use-a-rk_crypto_info-variable-instea.patch b/target/linux/rockchip/patches-6.1/311-crypto-rockchip-use-a-rk_crypto_info-variable-instea.patch
similarity index 96%
rename from target/linux/rockchip/patches-6.1/188-crypto-rockchip-use-a-rk_crypto_info-variable-instea.patch
rename to target/linux/rockchip/patches-6.1/311-crypto-rockchip-use-a-rk_crypto_info-variable-instea.patch
index b663638df3a..c0b49c14f09 100644
--- a/target/linux/rockchip/patches-6.1/188-crypto-rockchip-use-a-rk_crypto_info-variable-instea.patch
+++ b/target/linux/rockchip/patches-6.1/311-crypto-rockchip-use-a-rk_crypto_info-variable-instea.patch
@@ -1,8 +1,8 @@
-From b792b8f33d2c772cab201a068884feb0c10c1533 Mon Sep 17 00:00:00 2001
+From 251ef5a41fa0ff4d061ee7f1928a4c639a925e45 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:00 +0000
-Subject: [PATCH 38/49] crypto: rockchip: use a rk_crypto_info variable instead
- of lot of indirection
+Subject: [PATCH 311/383] crypto: rockchip: use a rk_crypto_info variable
+ instead of lot of indirection
 
 Instead of using lot of ctx->dev->xx indirections, use an intermediate
 variable for rk_crypto_info.
@@ -10,6 +10,7 @@ This will help later, when 2 different rk_crypto_info would be used.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto_ahash.c | 23 +++++++-----
  .../crypto/rockchip/rk3288_crypto_skcipher.c  | 37 ++++++++++---------
diff --git a/target/linux/rockchip/patches-6.1/189-crypto-rockchip-use-the-rk_crypto_info-given-as-para.patch b/target/linux/rockchip/patches-6.1/312-crypto-rockchip-use-the-rk_crypto_info-given-as-para.patch
similarity index 87%
rename from target/linux/rockchip/patches-6.1/189-crypto-rockchip-use-the-rk_crypto_info-given-as-para.patch
rename to target/linux/rockchip/patches-6.1/312-crypto-rockchip-use-the-rk_crypto_info-given-as-para.patch
index d5d582fd28b..4fc86a084d9 100644
--- a/target/linux/rockchip/patches-6.1/189-crypto-rockchip-use-the-rk_crypto_info-given-as-para.patch
+++ b/target/linux/rockchip/patches-6.1/312-crypto-rockchip-use-the-rk_crypto_info-given-as-para.patch
@@ -1,13 +1,14 @@
-From 9cbaeb79b6353f2b13c592754739d33f027e6662 Mon Sep 17 00:00:00 2001
+From 70e0fa5dc17aac682ebbfe293d15506e3d24f444 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:01 +0000
-Subject: [PATCH 39/49] crypto: rockchip: use the rk_crypto_info given as
+Subject: [PATCH 312/383] crypto: rockchip: use the rk_crypto_info given as
  parameter
 
 Instead of using the crypto_info from TFM ctx, use the one given as parameter.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto_skcipher.c | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/190-dt-bindings-crypto-convert-rockchip-crypto-to-YAML.patch b/target/linux/rockchip/patches-6.1/313-dt-bindings-crypto-convert-rockchip-crypto-to-YAML.patch
similarity index 94%
rename from target/linux/rockchip/patches-6.1/190-dt-bindings-crypto-convert-rockchip-crypto-to-YAML.patch
rename to target/linux/rockchip/patches-6.1/313-dt-bindings-crypto-convert-rockchip-crypto-to-YAML.patch
index 6d41f1a0157..134b4889a07 100644
--- a/target/linux/rockchip/patches-6.1/190-dt-bindings-crypto-convert-rockchip-crypto-to-YAML.patch
+++ b/target/linux/rockchip/patches-6.1/313-dt-bindings-crypto-convert-rockchip-crypto-to-YAML.patch
@@ -1,13 +1,14 @@
-From b4f63ecb0942ead52697ef3790c79546804fe478 Mon Sep 17 00:00:00 2001
+From 7e66f7d31afe27c521b84bb88509dd1966a85a56 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:02 +0000
-Subject: [PATCH 40/49] dt-bindings: crypto: convert rockchip-crypto to YAML
+Subject: [PATCH 313/383] dt-bindings: crypto: convert rockchip-crypto to YAML
 
 Convert rockchip-crypto to YAML.
 
 Reviewed-by: John Keeping <john@metanate.com>
 Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  .../crypto/rockchip,rk3288-crypto.yaml        | 64 +++++++++++++++++++
  .../bindings/crypto/rockchip-crypto.txt       | 28 --------
diff --git a/target/linux/rockchip/patches-6.1/191-dt-bindings-crypto-rockchip-add-new-compatible.patch b/target/linux/rockchip/patches-6.1/314-dt-bindings-crypto-rockchip-add-new-compatible.patch
similarity index 92%
rename from target/linux/rockchip/patches-6.1/191-dt-bindings-crypto-rockchip-add-new-compatible.patch
rename to target/linux/rockchip/patches-6.1/314-dt-bindings-crypto-rockchip-add-new-compatible.patch
index dfe6203a027..fa0fdc1c9fd 100644
--- a/target/linux/rockchip/patches-6.1/191-dt-bindings-crypto-rockchip-add-new-compatible.patch
+++ b/target/linux/rockchip/patches-6.1/314-dt-bindings-crypto-rockchip-add-new-compatible.patch
@@ -1,11 +1,12 @@
-From a20c32bcc5b5067368adc5ae47c467e32ffc0994 Mon Sep 17 00:00:00 2001
+From 8d344cf7eeaf9f2a9efdabd16b4932e8a6f11adc Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:03 +0000
-Subject: [PATCH 41/49] dt-bindings: crypto: rockchip: add new compatible
+Subject: [PATCH 314/383] dt-bindings: crypto: rockchip: add new compatible
 
 Since driver support new compatible, we need to update the driver bindings.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  .../crypto/rockchip,rk3288-crypto.yaml        | 79 +++++++++++++++++--
  1 file changed, 71 insertions(+), 8 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/192-clk-rk3399-use-proper-crypto0-name.patch b/target/linux/rockchip/patches-6.1/315-clk-rk3399-use-proper-crypto0-name.patch
similarity index 86%
rename from target/linux/rockchip/patches-6.1/192-clk-rk3399-use-proper-crypto0-name.patch
rename to target/linux/rockchip/patches-6.1/315-clk-rk3399-use-proper-crypto0-name.patch
index 6c2d5eb4cc4..608c2d098c0 100644
--- a/target/linux/rockchip/patches-6.1/192-clk-rk3399-use-proper-crypto0-name.patch
+++ b/target/linux/rockchip/patches-6.1/315-clk-rk3399-use-proper-crypto0-name.patch
@@ -1,7 +1,7 @@
-From b55b62250202a6d95872e367963190aaad6f9f08 Mon Sep 17 00:00:00 2001
+From 9ab9fe74997223d977e008e2426e3ba585586dcf Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:04 +0000
-Subject: [PATCH 42/49] clk: rk3399: use proper crypto0 name
+Subject: [PATCH 315/383] clk: rk3399: use proper crypto0 name
 
 RK3399 has 2 crypto instance, named crypto0 and crypto1 in the TRM.
 Only reset for crypto1 is correctly named, but crypto0 is not.
@@ -9,6 +9,7 @@ Since nobody use them , add a 0 to be consistent with the TRM and crypto1 entrie
 
 Acked-by: Rob Herring <robh@kernel.org>
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  include/dt-bindings/clock/rk3399-cru.h | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/195-crypto-rockchip-store-crypto_info-in-request-context.patch b/target/linux/rockchip/patches-6.1/316-crypto-rockchip-store-crypto_info-in-request-context.patch
similarity index 95%
rename from target/linux/rockchip/patches-6.1/195-crypto-rockchip-store-crypto_info-in-request-context.patch
rename to target/linux/rockchip/patches-6.1/316-crypto-rockchip-store-crypto_info-in-request-context.patch
index d8c4d173e02..6634944f3b6 100644
--- a/target/linux/rockchip/patches-6.1/195-crypto-rockchip-store-crypto_info-in-request-context.patch
+++ b/target/linux/rockchip/patches-6.1/316-crypto-rockchip-store-crypto_info-in-request-context.patch
@@ -1,12 +1,14 @@
-From 61900b43baea9ed606aacb824b761feca7511eaa Mon Sep 17 00:00:00 2001
+From 773b418cb58372831f1fe508fea1308bf1e8c67f Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:07 +0000
-Subject: [PATCH 45/49] crypto: rockchip: store crypto_info in request context
+Subject: [PATCH 316/383] crypto: rockchip: store crypto_info in request
+ context
 
 The crypto_info to use must be stored in the request context.
 This will help when 2 crypto_info will be available on rk3399.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.h          |  2 ++
  drivers/crypto/rockchip/rk3288_crypto_ahash.c    | 14 ++++++--------
diff --git a/target/linux/rockchip/patches-6.1/196-crypto-rockchip-Check-for-clocks-numbers-and-their-f.patch b/target/linux/rockchip/patches-6.1/317-crypto-rockchip-Check-for-clocks-numbers-and-their-f.patch
similarity index 95%
rename from target/linux/rockchip/patches-6.1/196-crypto-rockchip-Check-for-clocks-numbers-and-their-f.patch
rename to target/linux/rockchip/patches-6.1/317-crypto-rockchip-Check-for-clocks-numbers-and-their-f.patch
index 5cebb131e3e..aeb93cdfd21 100644
--- a/target/linux/rockchip/patches-6.1/196-crypto-rockchip-Check-for-clocks-numbers-and-their-f.patch
+++ b/target/linux/rockchip/patches-6.1/317-crypto-rockchip-Check-for-clocks-numbers-and-their-f.patch
@@ -1,7 +1,7 @@
-From 5301685e031d21df2b2a2d5959805f3292f3d481 Mon Sep 17 00:00:00 2001
+From 9c918c5eec0f61f820d282b7d10c1cce585f5ad1 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:08 +0000
-Subject: [PATCH 46/49] crypto: rockchip: Check for clocks numbers and their
+Subject: [PATCH 317/383] crypto: rockchip: Check for clocks numbers and their
  frequencies
 
 Add the number of clocks needed for each compatible.
@@ -10,6 +10,7 @@ checks for verifying they are within limits. Let's start with rk3288 for
 clock frequency check, other will came later.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 75 +++++++++++++++++++++----
  drivers/crypto/rockchip/rk3288_crypto.h | 16 +++++-
diff --git a/target/linux/rockchip/patches-6.1/197-crypto-rockchip-rk_ahash_reg_init-use-crypto_info-fr.patch b/target/linux/rockchip/patches-6.1/318-crypto-rockchip-rk_ahash_reg_init-use-crypto_info-fr.patch
similarity index 86%
rename from target/linux/rockchip/patches-6.1/197-crypto-rockchip-rk_ahash_reg_init-use-crypto_info-fr.patch
rename to target/linux/rockchip/patches-6.1/318-crypto-rockchip-rk_ahash_reg_init-use-crypto_info-fr.patch
index bb6b4f256c3..8e591bb15bc 100644
--- a/target/linux/rockchip/patches-6.1/197-crypto-rockchip-rk_ahash_reg_init-use-crypto_info-fr.patch
+++ b/target/linux/rockchip/patches-6.1/318-crypto-rockchip-rk_ahash_reg_init-use-crypto_info-fr.patch
@@ -1,13 +1,14 @@
-From 566cce03ee27f1288a4a029f5c7d437cc2e11eac Mon Sep 17 00:00:00 2001
+From f9354c6a535347932a8e15f30a40edc46e8f7b0e Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:09 +0000
-Subject: [PATCH 47/49] crypto: rockchip: rk_ahash_reg_init use crypto_info
+Subject: [PATCH 318/383] crypto: rockchip: rk_ahash_reg_init use crypto_info
  from parameter
 
 rk_ahash_reg_init() use crypto_info from TFM context, since we will
 remove it, let's take if from parameters.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto_ahash.c | 8 +++-----
  1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/198-crypto-rockchip-permit-to-have-more-than-one-reset.patch b/target/linux/rockchip/patches-6.1/319-crypto-rockchip-permit-to-have-more-than-one-reset.patch
similarity index 80%
rename from target/linux/rockchip/patches-6.1/198-crypto-rockchip-permit-to-have-more-than-one-reset.patch
rename to target/linux/rockchip/patches-6.1/319-crypto-rockchip-permit-to-have-more-than-one-reset.patch
index a56241149eb..b1e7c107420 100644
--- a/target/linux/rockchip/patches-6.1/198-crypto-rockchip-permit-to-have-more-than-one-reset.patch
+++ b/target/linux/rockchip/patches-6.1/319-crypto-rockchip-permit-to-have-more-than-one-reset.patch
@@ -1,12 +1,13 @@
-From 5a73176384bd62a9ac4300805d243592e93fe5d4 Mon Sep 17 00:00:00 2001
+From bedc4f455e3049653fbf82fd557fd69ee1a6d560 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:10 +0000
-Subject: [PATCH 48/49] crypto: rockchip: permit to have more than one reset
+Subject: [PATCH 319/383] crypto: rockchip: permit to have more than one reset
 
 The RK3399 has 3 resets, so the driver to handle multiple resets.
 This is done by using devm_reset_control_array_get_exclusive().
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/linux/rockchip/patches-6.1/199-crypto-rockchip-Add-support-for-RK3399.patch b/target/linux/rockchip/patches-6.1/320-crypto-rockchip-Add-support-for-RK3399.patch
similarity index 98%
rename from target/linux/rockchip/patches-6.1/199-crypto-rockchip-Add-support-for-RK3399.patch
rename to target/linux/rockchip/patches-6.1/320-crypto-rockchip-Add-support-for-RK3399.patch
index 7c5902ff517..9ff1d41e7d8 100644
--- a/target/linux/rockchip/patches-6.1/199-crypto-rockchip-Add-support-for-RK3399.patch
+++ b/target/linux/rockchip/patches-6.1/320-crypto-rockchip-Add-support-for-RK3399.patch
@@ -1,7 +1,7 @@
-From 5a0b753155b5d3cbba77ecd6a017e6f3733e344e Mon Sep 17 00:00:00 2001
+From 4d4aecbfbcf56cd82685593bb3e6abd6f49411d0 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 07:55:11 +0000
-Subject: [PATCH 49/49] crypto: rockchip: Add support for RK3399
+Subject: [PATCH 320/383] crypto: rockchip: Add support for RK3399
 
 The RK3399 has 2 rk3288 compatible crypto device named crypto0 and
 crypto1. The only difference is lack of RSA in crypto1.
@@ -13,6 +13,7 @@ Then the driver will round robin each request on each device.
 For avoiding complexity (device bringup after a TFM is created), PM is
 modified to be handled per request.
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/rk3288_crypto.c       | 92 +++++++++++++++----
  drivers/crypto/rockchip/rk3288_crypto.h       | 25 +++--
diff --git a/target/linux/rockchip/patches-6.1/213-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch b/target/linux/rockchip/patches-6.1/321-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch
similarity index 94%
rename from target/linux/rockchip/patches-6.1/213-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch
rename to target/linux/rockchip/patches-6.1/321-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch
index 903789cc4de..848c77ebd6c 100644
--- a/target/linux/rockchip/patches-6.1/213-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch
+++ b/target/linux/rockchip/patches-6.1/321-crypto-rockchip-move-kconfig-to-its-dedicated-direct.patch
@@ -1,11 +1,13 @@
-From e8749922cdcddc6e3d3df6a94c530df863073353 Mon Sep 17 00:00:00 2001
+From b480879eeb810bed35d467f41650a90df83124c7 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 08:00:44 +0000
-Subject: [PATCH 1/5] crypto: rockchip: move kconfig to its dedicated directory
+Subject: [PATCH 321/383] crypto: rockchip: move kconfig to its dedicated
+ directory
 
 Move all rockchip kconfig in its own subdirectory.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/Kconfig          | 32 ++------------------------------
  drivers/crypto/Makefile         |  2 +-
diff --git a/target/linux/rockchip/patches-6.1/214-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch b/target/linux/rockchip/patches-6.1/322-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch
similarity index 92%
rename from target/linux/rockchip/patches-6.1/214-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch
rename to target/linux/rockchip/patches-6.1/322-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch
index aa9e35d316f..a72c220b617 100644
--- a/target/linux/rockchip/patches-6.1/214-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch
+++ b/target/linux/rockchip/patches-6.1/322-dt-bindings-crypto-add-support-for-rockchip-crypto-r.patch
@@ -1,13 +1,14 @@
-From 03c8a180b9ba57a1bcf658c25a725b063bbade96 Mon Sep 17 00:00:00 2001
+From f17c012755ee45fd3657ed9f1103120bd18edad2 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 08:00:45 +0000
-Subject: [PATCH 2/5] dt-bindings: crypto: add support for
+Subject: [PATCH 322/383] dt-bindings: crypto: add support for
  rockchip,crypto-rk3588
 
 Add device tree binding documentation for the Rockchip cryptographic
 offloader V2.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  .../crypto/rockchip,rk3588-crypto.yaml        | 71 +++++++++++++++++++
  1 file changed, 71 insertions(+)
diff --git a/target/linux/rockchip/patches-6.1/215-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch b/target/linux/rockchip/patches-6.1/323-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch
similarity index 67%
rename from target/linux/rockchip/patches-6.1/215-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch
rename to target/linux/rockchip/patches-6.1/323-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch
index bba0a083526..46c9e5ae7f1 100644
--- a/target/linux/rockchip/patches-6.1/215-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch
+++ b/target/linux/rockchip/patches-6.1/323-MAINTAINERS-add-new-dt-binding-doc-to-the-right-entr.patch
@@ -1,18 +1,20 @@
-From a091cb568872e3ef2e6a5c6e28e4f43465d46ca2 Mon Sep 17 00:00:00 2001
+From 0f612f7920922d78f2e0aea6a8d0fe11bebf0653 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 08:00:46 +0000
-Subject: [PATCH 3/5] MAINTAINERS: add new dt-binding doc to the right entry
+Subject: [PATCH 323/383] MAINTAINERS: add new dt-binding doc to the right
+ entry
 
 Rockchip crypto driver have a new file to be added.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  MAINTAINERS | 1 +
  1 file changed, 1 insertion(+)
 
 --- a/MAINTAINERS
 +++ b/MAINTAINERS
-@@ -17802,6 +17802,7 @@ M:	Corentin Labbe <clabbe@baylibre.com>
+@@ -17804,6 +17804,7 @@ M:	Corentin Labbe <clabbe@baylibre.com>
  L:	linux-crypto@vger.kernel.org
  S:	Maintained
  F:	Documentation/devicetree/bindings/crypto/rockchip,rk3288-crypto.yaml
diff --git a/target/linux/rockchip/patches-6.1/216-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch b/target/linux/rockchip/patches-6.1/324-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch
similarity index 99%
rename from target/linux/rockchip/patches-6.1/216-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch
rename to target/linux/rockchip/patches-6.1/324-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch
index ecef871076c..7fe0f331d9c 100644
--- a/target/linux/rockchip/patches-6.1/216-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch
+++ b/target/linux/rockchip/patches-6.1/324-crypto-rockchip-support-the-new-crypto-IP-for-rk3568.patch
@@ -1,13 +1,14 @@
-From 06ecfb2f7b3277c4ed1bf0172b14ae7bc0c2d4aa Mon Sep 17 00:00:00 2001
+From aaff60293f2a9456aa4a1ad195abf6038af61cdd Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 08:00:47 +0000
-Subject: [PATCH 4/5] crypto: rockchip: support the new crypto IP for
+Subject: [PATCH 324/383] crypto: rockchip: support the new crypto IP for
  rk3568/rk3588
 
 Rockchip rk3568 and rk3588 have a common crypto offloader IP.
 This driver adds support for it.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/crypto/rockchip/Kconfig               |  28 +
  drivers/crypto/rockchip/Makefile              |   5 +
diff --git a/target/linux/rockchip/patches-6.1/217-ARM64-dts-rk3568-add-crypto-node.patch b/target/linux/rockchip/patches-6.1/325-ARM64-dts-rk3568-add-crypto-node.patch
similarity index 86%
rename from target/linux/rockchip/patches-6.1/217-ARM64-dts-rk3568-add-crypto-node.patch
rename to target/linux/rockchip/patches-6.1/325-ARM64-dts-rk3568-add-crypto-node.patch
index 2a8a24d0e61..0442240d305 100644
--- a/target/linux/rockchip/patches-6.1/217-ARM64-dts-rk3568-add-crypto-node.patch
+++ b/target/linux/rockchip/patches-6.1/325-ARM64-dts-rk3568-add-crypto-node.patch
@@ -1,12 +1,13 @@
-From 5055f9e39713f9e5303bbcdc3712909a462dd3c2 Mon Sep 17 00:00:00 2001
+From 2bfe81b49f613340025a0f3a19a8989159923034 Mon Sep 17 00:00:00 2001
 From: Corentin Labbe <clabbe@baylibre.com>
 Date: Tue, 27 Sep 2022 08:00:48 +0000
-Subject: [PATCH 5/5] ARM64: dts: rk3568: add crypto node
+Subject: [PATCH 325/383] ARM64: dts: rk3568: add crypto node
 
 The rk3568 has a crypto IP handled by the rk3588 crypto driver so adds a
 node for it.
 
 Signed-off-by: Corentin Labbe <clabbe@baylibre.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk3568.dtsi | 14 ++++++++++++++
  1 file changed, 14 insertions(+)
diff --git a/target/linux/rockchip/patches-6.1/218-fix-build-crypto.patch b/target/linux/rockchip/patches-6.1/326-drivers-crypto-rockchip-fix-openwrt-build.patch
similarity index 61%
rename from target/linux/rockchip/patches-6.1/218-fix-build-crypto.patch
rename to target/linux/rockchip/patches-6.1/326-drivers-crypto-rockchip-fix-openwrt-build.patch
index 234e69b5655..4755a8c67cb 100644
--- a/target/linux/rockchip/patches-6.1/218-fix-build-crypto.patch
+++ b/target/linux/rockchip/patches-6.1/326-drivers-crypto-rockchip-fix-openwrt-build.patch
@@ -1,3 +1,13 @@
+From baba923180a89d14ed312642355c5328c21ad29e Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Thu, 29 Sep 2022 18:44:42 -0400
+Subject: [PATCH 326/383] drivers: crypto-rockchip fix openwrt build
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/crypto/rockchip/rk3288_crypto.c | 12 ------------
+ 1 file changed, 12 deletions(-)
+
 --- a/drivers/crypto/rockchip/rk3288_crypto.c
 +++ b/drivers/crypto/rockchip/rk3288_crypto.c
 @@ -24,18 +24,6 @@ static struct rockchip_ip rocklist = {
diff --git a/target/linux/rockchip/patches-6.1/219-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch b/target/linux/rockchip/patches-6.1/327-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
similarity index 98%
rename from target/linux/rockchip/patches-6.1/219-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
rename to target/linux/rockchip/patches-6.1/327-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
index 62e84a55d6d..cc9a0340a68 100644
--- a/target/linux/rockchip/patches-6.1/219-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
+++ b/target/linux/rockchip/patches-6.1/327-PCI-Add-ROCKCHIP-PCIe-ASPM-interface.patch
@@ -1,10 +1,11 @@
-From d591c3f6efef5f50fc970aeeedbf9e03b7bd5d21 Mon Sep 17 00:00:00 2001
+From 75d32727b1cbbeb33ecee0a8bd9fc1d484762717 Mon Sep 17 00:00:00 2001
 From: Jon Lin <jon.lin@rock-chips.com>
 Date: Fri, 17 Jun 2022 10:38:30 +0800
-Subject: [PATCH] PCI: Add ROCKCHIP PCIe ASPM interface
+Subject: [PATCH 327/383] PCI: Add ROCKCHIP PCIe ASPM interface
 
 Change-Id: I1156bd10e352145d745899067bf43afda92d5a30
 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/pci/pcie/Kconfig    |   6 +
  drivers/pci/pcie/Makefile   |   1 +
diff --git a/target/linux/rockchip/patches-6.1/220-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch b/target/linux/rockchip/patches-6.1/328-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
similarity index 80%
rename from target/linux/rockchip/patches-6.1/220-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
rename to target/linux/rockchip/patches-6.1/328-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
index 990bf194afb..84fd2b51665 100644
--- a/target/linux/rockchip/patches-6.1/220-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
+++ b/target/linux/rockchip/patches-6.1/328-PCI-aspm_ext-Re-enable-LRT-for-L1SS-after-power-loss.patch
@@ -1,10 +1,12 @@
-From a6c71606de486944c5fb028f47604fb22292312b Mon Sep 17 00:00:00 2001
+From 8233ef929824976915dd99328f1b0347ded24e45 Mon Sep 17 00:00:00 2001
 From: Jon Lin <jon.lin@rock-chips.com>
 Date: Fri, 24 Jun 2022 21:32:11 +0800
-Subject: [PATCH] PCI: aspm_ext: Re-enable LRT for L1SS after power loss
+Subject: [PATCH 328/383] PCI: aspm_ext: Re-enable LRT for L1SS after power
+ loss
 
 Change-Id: Iedb72ee74660a8f11f38895e06766c3b77728ba3
 Signed-off-by: Jon Lin <jon.lin@rock-chips.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/pci/pcie/aspm_ext.c | 4 ++++
  1 file changed, 4 insertions(+)
diff --git a/target/linux/rockchip/patches-6.1/221-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch b/target/linux/rockchip/patches-6.1/329-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
similarity index 85%
rename from target/linux/rockchip/patches-6.1/221-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
rename to target/linux/rockchip/patches-6.1/329-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
index 3bf9e9a5d3f..651cc27968b 100644
--- a/target/linux/rockchip/patches-6.1/221-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
+++ b/target/linux/rockchip/patches-6.1/329-PCI-aspm_ext-Fix-Add-missing-MODULE_LICENSE.patch
@@ -1,12 +1,13 @@
-From cf03561e5ec9f2f8b41a992f3b8ca19b9c3b9e47 Mon Sep 17 00:00:00 2001
+From c5efbe8d0a1349f29668555019541c1b6d612d7a Mon Sep 17 00:00:00 2001
 From: Tao Huang <huangtao@rock-chips.com>
 Date: Fri, 15 Jul 2022 20:56:15 +0800
-Subject: [PATCH] PCI: aspm_ext: Fix Add missing MODULE_LICENSE()
+Subject: [PATCH 329/383] PCI: aspm_ext: Fix Add missing MODULE_LICENSE()
 
 ERROR: modpost: missing MODULE_LICENSE() in drivers/pci/pcie/aspm_ext.o
 
 Signed-off-by: Tao Huang <huangtao@rock-chips.com>
 Change-Id: Id365aba7a73f02cc2c61882b46937250e64af01c
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/pci/pcie/aspm_ext.c | 5 ++++-
  1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/linux/rockchip/patches-6.1/330-mmc-sdhci-of-dwcmshc-enable-host-V4-support-for-Blue.patch b/target/linux/rockchip/patches-6.1/330-mmc-sdhci-of-dwcmshc-enable-host-V4-support-for-Blue.patch
new file mode 100644
index 00000000000..9af3ba21f37
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/330-mmc-sdhci-of-dwcmshc-enable-host-V4-support-for-Blue.patch
@@ -0,0 +1,33 @@
+From fb85457dc9dc26083167e3e960a919559cee53de Mon Sep 17 00:00:00 2001
+From: Liming Sun <limings@nvidia.com>
+Date: Wed, 11 Jan 2023 13:14:58 -0500
+Subject: [PATCH 330/383] mmc: sdhci-of-dwcmshc: enable host V4 support for
+ BlueField-3 SoC
+
+This commit enables SDHCI Host V4 support on Bluefield-3 SoC to be
+consistent with the default setting in firmware(UEFI).
+
+Reviewed-by: David Woods <davwoods@nvidia.com>
+Signed-off-by: Liming Sun <limings@nvidia.com>
+Acked-by: Adrian Hunter <adrian.hunter@intel.com>
+Link: https://lore.kernel.org/r/990885f566c32ac8e6888ad6b434fb70d1a5d7af.1673460632.git.limings@nvidia.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -528,6 +528,11 @@ static int dwcmshc_probe(struct platform
+ 			goto err_clk;
+ 	}
+ 
++#ifdef CONFIG_ACPI
++	if (pltfm_data == &sdhci_dwcmshc_bf3_pdata)
++		sdhci_enable_v4_mode(host);
++#endif
++
+ 	host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
+ 
+ 	err = sdhci_setup_host(host);
diff --git a/target/linux/rockchip/patches-6.1/019-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre.patch b/target/linux/rockchip/patches-6.1/331-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay.patch
similarity index 91%
rename from target/linux/rockchip/patches-6.1/019-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre.patch
rename to target/linux/rockchip/patches-6.1/331-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay.patch
index 2bb542be369..173a6b60e4f 100644
--- a/target/linux/rockchip/patches-6.1/019-v6.3-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre.patch
+++ b/target/linux/rockchip/patches-6.1/331-mmc-sdhci-of-dwcmshc-Update-DLL-and-pre-change-delay.patch
@@ -1,8 +1,8 @@
-From b75a52b0dda353aeefb4830a320589a363f49579 Mon Sep 17 00:00:00 2001
+From d6458f453d0f843ad03c6a674cc1ffa701b1d664 Mon Sep 17 00:00:00 2001
 From: Shawn Lin <shawn.lin@rock-chips.com>
 Date: Thu, 2 Feb 2023 08:35:16 +0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: Update DLL and pre-change delay for
- rockchip platform
+Subject: [PATCH 331/383] mmc: sdhci-of-dwcmshc: Update DLL and pre-change
+ delay for rockchip platform
 
 For Rockchip platform, DLL bypass bit and start bit need to be set if
 DLL is not locked. And adjust pre-change delay to 0x3 for better signal
@@ -11,6 +11,7 @@ test result.
 Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
 Link: https://lore.kernel.org/r/1675298118-64243-2-git-send-email-shawn.lin@rock-chips.com
 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/mmc/host/sdhci-of-dwcmshc.c | 13 +++++++++----
  1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/target/linux/rockchip/patches-6.1/332-mmc-sdhci-of-dwcmshc-add-the-missing-device-table-ID.patch b/target/linux/rockchip/patches-6.1/332-mmc-sdhci-of-dwcmshc-add-the-missing-device-table-ID.patch
new file mode 100644
index 00000000000..dc8088e8118
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/332-mmc-sdhci-of-dwcmshc-add-the-missing-device-table-ID.patch
@@ -0,0 +1,28 @@
+From 8af7b973bbdd7fe934438914fc36d34c52885166 Mon Sep 17 00:00:00 2001
+From: Liming Sun <limings@nvidia.com>
+Date: Thu, 2 Feb 2023 10:29:15 -0500
+Subject: [PATCH 332/383] mmc: sdhci-of-dwcmshc: add the missing device table
+ IDs for acpi
+
+This commit adds the missing MODULE_DEVICE_TABLE for acpi, or else
+it won't be loaded automatically when compiled as a kernel module.
+
+Reviewed-by: David Thompson <davthompson@nvidia.com>
+Signed-off-by: Liming Sun <limings@nvidia.com>
+Link: https://lore.kernel.org/r/f57ad0f8fdf663465bca74467c344dfa305a3199.1675305696.git.limings@nvidia.com
+Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/mmc/host/sdhci-of-dwcmshc.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/drivers/mmc/host/sdhci-of-dwcmshc.c
++++ b/drivers/mmc/host/sdhci-of-dwcmshc.c
+@@ -451,6 +451,7 @@ static const struct acpi_device_id sdhci
+ 	},
+ 	{}
+ };
++MODULE_DEVICE_TABLE(acpi, sdhci_dwcmshc_acpi_ids);
+ #endif
+ 
+ static int dwcmshc_probe(struct platform_device *pdev)
diff --git a/target/linux/rockchip/patches-6.1/020-v6.4-mmc-sdhci-of-dwcmshc-properly-determine.patch b/target/linux/rockchip/patches-6.1/333-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch
similarity index 90%
rename from target/linux/rockchip/patches-6.1/020-v6.4-mmc-sdhci-of-dwcmshc-properly-determine.patch
rename to target/linux/rockchip/patches-6.1/333-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch
index 9d9c1b5c1c2..f5f3a24e41c 100644
--- a/target/linux/rockchip/patches-6.1/020-v6.4-mmc-sdhci-of-dwcmshc-properly-determine.patch
+++ b/target/linux/rockchip/patches-6.1/333-mmc-sdhci-of-dwcmshc-properly-determine-max-clock-on.patch
@@ -1,8 +1,8 @@
-From 49502408007b77ff290ce62e6218cefaeedcb31a Mon Sep 17 00:00:00 2001
+From 4823aef067e0e33b0e9c5ee658d3e16e190fb462 Mon Sep 17 00:00:00 2001
 From: Vasily Khoruzhick <anarsoul@gmail.com>
 Date: Thu, 9 Mar 2023 17:03:49 -0800
-Subject: [PATCH] mmc: sdhci-of-dwcmshc: properly determine max clock on
- Rockchip
+Subject: [PATCH 333/383] mmc: sdhci-of-dwcmshc: properly determine max clock
+ on Rockchip
 
 Currently .get_max_clock returns the current clock rate for cclk_emmc
 on rk35xx, thus max clock gets set to whatever bootloader set it to.
@@ -21,6 +21,7 @@ Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
 Acked-by: Adrian Hunter <adrian.hunter@intel.com>
 Link: https://lore.kernel.org/r/20230310010349.509132-1-anarsoul@gmail.com
 Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  drivers/mmc/host/sdhci-of-dwcmshc.c | 9 ++++++++-
  1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/linux/rockchip/patches-6.1/334-dt-bindings-reset-add-rk3588-reset-definitions.patch b/target/linux/rockchip/patches-6.1/334-dt-bindings-reset-add-rk3588-reset-definitions.patch
new file mode 100644
index 00000000000..278428101dc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/334-dt-bindings-reset-add-rk3588-reset-definitions.patch
@@ -0,0 +1,782 @@
+From 8812d1166868437b6d5161f3e97e139b78c139b6 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 18 Oct 2022 17:14:00 +0200
+Subject: [PATCH 334/383] dt-bindings: reset: add rk3588 reset definitions
+
+Add reset ID defines for rk3588.
+
+Compared to the downstream bindings and previous rockchip
+generations this uses continous gapless reset IDs starting
+at 0 instead of register offsets as IDs. Thus all numbers
+are different between upstream and downstream, but I kept
+the names exactly the same.
+
+Co-Developed-by: Elaine Zhang <zhangqing@rock-chips.com>
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dt-bindings/reset/rockchip,rk3588-cru.h   | 754 ++++++++++++++++++
+ 1 file changed, 754 insertions(+)
+ create mode 100644 include/dt-bindings/reset/rockchip,rk3588-cru.h
+
+--- /dev/null
++++ b/include/dt-bindings/reset/rockchip,rk3588-cru.h
+@@ -0,0 +1,754 @@
++/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ * Copyright (c) 2022 Collabora Ltd.
++ *
++ * Author: Elaine Zhang <zhangqing@rock-chips.com>
++ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
++ */
++
++#ifndef _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
++#define _DT_BINDINGS_RESET_ROCKCHIP_RK3588_H
++
++#define SRST_A_TOP_BIU			0
++#define SRST_P_TOP_BIU			1
++#define SRST_P_CSIPHY0			2
++#define SRST_CSIPHY0			3
++#define SRST_P_CSIPHY1			4
++#define SRST_CSIPHY1			5
++#define SRST_A_TOP_M500_BIU		6
++
++#define SRST_A_TOP_M400_BIU		7
++#define SRST_A_TOP_S200_BIU		8
++#define SRST_A_TOP_S400_BIU		9
++#define SRST_A_TOP_M300_BIU		10
++#define SRST_USBDP_COMBO_PHY0_INIT	11
++#define SRST_USBDP_COMBO_PHY0_CMN	12
++#define SRST_USBDP_COMBO_PHY0_LANE	13
++#define SRST_USBDP_COMBO_PHY0_PCS	14
++#define SRST_USBDP_COMBO_PHY1_INIT	15
++
++#define SRST_USBDP_COMBO_PHY1_CMN	16
++#define SRST_USBDP_COMBO_PHY1_LANE	17
++#define SRST_USBDP_COMBO_PHY1_PCS	18
++#define SRST_DCPHY0			19
++#define SRST_P_MIPI_DCPHY0		20
++#define SRST_P_MIPI_DCPHY0_GRF		21
++
++#define SRST_DCPHY1			22
++#define SRST_P_MIPI_DCPHY1		23
++#define SRST_P_MIPI_DCPHY1_GRF		24
++#define SRST_P_APB2ASB_SLV_CDPHY	25
++#define SRST_P_APB2ASB_SLV_CSIPHY	26
++#define SRST_P_APB2ASB_SLV_VCCIO3_5	27
++#define SRST_P_APB2ASB_SLV_VCCIO6	28
++#define SRST_P_APB2ASB_SLV_EMMCIO	29
++#define SRST_P_APB2ASB_SLV_IOC_TOP	30
++#define SRST_P_APB2ASB_SLV_IOC_RIGHT	31
++
++#define SRST_P_CRU			32
++#define SRST_A_CHANNEL_SECURE2VO1USB	33
++#define SRST_A_CHANNEL_SECURE2CENTER	34
++#define SRST_H_CHANNEL_SECURE2VO1USB	35
++#define SRST_H_CHANNEL_SECURE2CENTER	36
++
++#define SRST_P_CHANNEL_SECURE2VO1USB	37
++#define SRST_P_CHANNEL_SECURE2CENTER	38
++
++#define SRST_H_AUDIO_BIU		39
++#define SRST_P_AUDIO_BIU		40
++#define SRST_H_I2S0_8CH			41
++#define SRST_M_I2S0_8CH_TX		42
++#define SRST_M_I2S0_8CH_RX		43
++#define SRST_P_ACDCDIG			44
++#define SRST_H_I2S2_2CH			45
++#define SRST_H_I2S3_2CH			46
++
++#define SRST_M_I2S2_2CH			47
++#define SRST_M_I2S3_2CH			48
++#define SRST_DAC_ACDCDIG		49
++#define SRST_H_SPDIF0			50
++
++#define SRST_M_SPDIF0			51
++#define SRST_H_SPDIF1			52
++#define SRST_M_SPDIF1			53
++#define SRST_H_PDM1			54
++#define SRST_PDM1			55
++
++#define SRST_A_BUS_BIU			56
++#define SRST_P_BUS_BIU			57
++#define SRST_A_GIC			58
++#define SRST_A_GIC_DBG			59
++#define SRST_A_DMAC0			60
++#define SRST_A_DMAC1			61
++#define SRST_A_DMAC2			62
++#define SRST_P_I2C1			63
++#define SRST_P_I2C2			64
++#define SRST_P_I2C3			65
++#define SRST_P_I2C4			66
++#define SRST_P_I2C5			67
++#define SRST_P_I2C6			68
++#define SRST_P_I2C7			69
++#define SRST_P_I2C8			70
++
++#define SRST_I2C1			71
++#define SRST_I2C2			72
++#define SRST_I2C3			73
++#define SRST_I2C4			74
++#define SRST_I2C5			75
++#define SRST_I2C6			76
++#define SRST_I2C7			77
++#define SRST_I2C8			78
++#define SRST_P_CAN0			79
++#define SRST_CAN0			80
++#define SRST_P_CAN1			81
++#define SRST_CAN1			82
++#define SRST_P_CAN2			83
++#define SRST_CAN2			84
++#define SRST_P_SARADC			85
++
++#define SRST_P_TSADC			86
++#define SRST_TSADC			87
++#define SRST_P_UART1			88
++#define SRST_P_UART2			89
++#define SRST_P_UART3			90
++#define SRST_P_UART4			91
++#define SRST_P_UART5			92
++#define SRST_P_UART6			93
++#define SRST_P_UART7			94
++#define SRST_P_UART8			95
++#define SRST_P_UART9			96
++#define SRST_S_UART1			97
++
++#define SRST_S_UART2			98
++#define SRST_S_UART3			99
++#define SRST_S_UART4			100
++#define SRST_S_UART5			101
++#define SRST_S_UART6			102
++#define SRST_S_UART7			103
++
++#define SRST_S_UART8			104
++#define SRST_S_UART9			105
++#define SRST_P_SPI0			106
++#define SRST_P_SPI1			107
++#define SRST_P_SPI2			108
++#define SRST_P_SPI3			109
++#define SRST_P_SPI4			110
++#define SRST_SPI0			111
++#define SRST_SPI1			112
++#define SRST_SPI2			113
++#define SRST_SPI3			114
++#define SRST_SPI4			115
++
++#define SRST_P_WDT0			116
++#define SRST_T_WDT0			117
++#define SRST_P_SYS_GRF			118
++#define SRST_P_PWM1			119
++#define SRST_PWM1			120
++#define SRST_P_PWM2			121
++#define SRST_PWM2			122
++#define SRST_P_PWM3			123
++#define SRST_PWM3			124
++#define SRST_P_BUSTIMER0		125
++#define SRST_P_BUSTIMER1		126
++#define SRST_BUSTIMER0			127
++
++#define SRST_BUSTIMER1			128
++#define SRST_BUSTIMER2			129
++#define SRST_BUSTIMER3			130
++#define SRST_BUSTIMER4			131
++#define SRST_BUSTIMER5			132
++#define SRST_BUSTIMER6			133
++#define SRST_BUSTIMER7			134
++#define SRST_BUSTIMER8			135
++#define SRST_BUSTIMER9			136
++#define SRST_BUSTIMER10			137
++#define SRST_BUSTIMER11			138
++#define SRST_P_MAILBOX0			139
++#define SRST_P_MAILBOX1			140
++#define SRST_P_MAILBOX2			141
++#define SRST_P_GPIO1			142
++#define SRST_GPIO1			143
++
++#define SRST_P_GPIO2			144
++#define SRST_GPIO2			145
++#define SRST_P_GPIO3			146
++#define SRST_GPIO3			147
++#define SRST_P_GPIO4			148
++#define SRST_GPIO4			149
++#define SRST_A_DECOM			150
++#define SRST_P_DECOM			151
++#define SRST_D_DECOM			152
++#define SRST_P_TOP			153
++#define SRST_A_GICADB_GIC2CORE_BUS	154
++#define SRST_P_DFT2APB			155
++#define SRST_P_APB2ASB_MST_TOP		156
++#define SRST_P_APB2ASB_MST_CDPHY	157
++#define SRST_P_APB2ASB_MST_BOT_RIGHT	158
++
++#define SRST_P_APB2ASB_MST_IOC_TOP	159
++#define SRST_P_APB2ASB_MST_IOC_RIGHT	160
++#define SRST_P_APB2ASB_MST_CSIPHY	161
++#define SRST_P_APB2ASB_MST_VCCIO3_5	162
++#define SRST_P_APB2ASB_MST_VCCIO6	163
++#define SRST_P_APB2ASB_MST_EMMCIO	164
++#define SRST_A_SPINLOCK			165
++#define SRST_P_OTPC_NS			166
++#define SRST_OTPC_NS			167
++#define SRST_OTPC_ARB			168
++
++#define SRST_P_BUSIOC			169
++#define SRST_P_PMUCM0_INTMUX		170
++#define SRST_P_DDRCM0_INTMUX		171
++
++#define SRST_P_DDR_DFICTL_CH0		172
++#define SRST_P_DDR_MON_CH0		173
++#define SRST_P_DDR_STANDBY_CH0		174
++#define SRST_P_DDR_UPCTL_CH0		175
++#define SRST_TM_DDR_MON_CH0		176
++#define SRST_P_DDR_GRF_CH01		177
++#define SRST_DFI_CH0			178
++#define SRST_SBR_CH0			179
++#define SRST_DDR_UPCTL_CH0		180
++#define SRST_DDR_DFICTL_CH0		181
++#define SRST_DDR_MON_CH0		182
++#define SRST_DDR_STANDBY_CH0		183
++#define SRST_A_DDR_UPCTL_CH0		184
++#define SRST_P_DDR_DFICTL_CH1		185
++#define SRST_P_DDR_MON_CH1		186
++#define SRST_P_DDR_STANDBY_CH1		187
++
++#define SRST_P_DDR_UPCTL_CH1		188
++#define SRST_TM_DDR_MON_CH1		189
++#define SRST_DFI_CH1			190
++#define SRST_SBR_CH1			191
++#define SRST_DDR_UPCTL_CH1		192
++#define SRST_DDR_DFICTL_CH1		193
++#define SRST_DDR_MON_CH1		194
++#define SRST_DDR_STANDBY_CH1		195
++#define SRST_A_DDR_UPCTL_CH1		196
++#define SRST_A_DDR01_MSCH0		197
++#define SRST_A_DDR01_RS_MSCH0		198
++#define SRST_A_DDR01_FRS_MSCH0		199
++
++#define SRST_A_DDR01_SCRAMBLE0		200
++#define SRST_A_DDR01_FRS_SCRAMBLE0	201
++#define SRST_A_DDR01_MSCH1		202
++#define SRST_A_DDR01_RS_MSCH1		203
++#define SRST_A_DDR01_FRS_MSCH1		204
++#define SRST_A_DDR01_SCRAMBLE1		205
++#define SRST_A_DDR01_FRS_SCRAMBLE1	206
++#define SRST_P_DDR01_MSCH0		207
++#define SRST_P_DDR01_MSCH1		208
++
++#define SRST_P_DDR_DFICTL_CH2		209
++#define SRST_P_DDR_MON_CH2		210
++#define SRST_P_DDR_STANDBY_CH2		211
++#define SRST_P_DDR_UPCTL_CH2		212
++#define SRST_TM_DDR_MON_CH2		213
++#define SRST_P_DDR_GRF_CH23		214
++#define SRST_DFI_CH2			215
++#define SRST_SBR_CH2			216
++#define SRST_DDR_UPCTL_CH2		217
++#define SRST_DDR_DFICTL_CH2		218
++#define SRST_DDR_MON_CH2		219
++#define SRST_DDR_STANDBY_CH2		220
++#define SRST_A_DDR_UPCTL_CH2		221
++#define SRST_P_DDR_DFICTL_CH3		222
++#define SRST_P_DDR_MON_CH3		223
++#define SRST_P_DDR_STANDBY_CH3		224
++
++#define SRST_P_DDR_UPCTL_CH3		225
++#define SRST_TM_DDR_MON_CH3		226
++#define SRST_DFI_CH3			227
++#define SRST_SBR_CH3			228
++#define SRST_DDR_UPCTL_CH3		229
++#define SRST_DDR_DFICTL_CH3		230
++#define SRST_DDR_MON_CH3		231
++#define SRST_DDR_STANDBY_CH3		232
++#define SRST_A_DDR_UPCTL_CH3		233
++#define SRST_A_DDR23_MSCH2		234
++#define SRST_A_DDR23_RS_MSCH2		235
++#define SRST_A_DDR23_FRS_MSCH2		236
++
++#define SRST_A_DDR23_SCRAMBLE2		237
++#define SRST_A_DDR23_FRS_SCRAMBLE2	238
++#define SRST_A_DDR23_MSCH3		239
++#define SRST_A_DDR23_RS_MSCH3		240
++#define SRST_A_DDR23_FRS_MSCH3		241
++#define SRST_A_DDR23_SCRAMBLE3		242
++#define SRST_A_DDR23_FRS_SCRAMBLE3	243
++#define SRST_P_DDR23_MSCH2		244
++#define SRST_P_DDR23_MSCH3		245
++
++#define SRST_ISP1			246
++#define SRST_ISP1_VICAP			247
++#define SRST_A_ISP1_BIU			248
++#define SRST_H_ISP1_BIU			249
++
++#define SRST_A_RKNN1			250
++#define SRST_A_RKNN1_BIU		251
++#define SRST_H_RKNN1			252
++#define SRST_H_RKNN1_BIU		253
++
++#define SRST_A_RKNN2			254
++#define SRST_A_RKNN2_BIU		255
++#define SRST_H_RKNN2			256
++#define SRST_H_RKNN2_BIU		257
++
++#define SRST_A_RKNN_DSU0		258
++#define SRST_P_NPUTOP_BIU		259
++#define SRST_P_NPU_TIMER		260
++#define SRST_NPUTIMER0			261
++#define SRST_NPUTIMER1			262
++#define SRST_P_NPU_WDT			263
++#define SRST_T_NPU_WDT			264
++#define SRST_P_NPU_PVTM			265
++#define SRST_P_NPU_GRF			266
++#define SRST_NPU_PVTM			267
++
++#define SRST_NPU_PVTPLL			268
++#define SRST_H_NPU_CM0_BIU		269
++#define SRST_F_NPU_CM0_CORE		270
++#define SRST_T_NPU_CM0_JTAG		271
++#define SRST_A_RKNN0			272
++#define SRST_A_RKNN0_BIU		273
++#define SRST_H_RKNN0			274
++#define SRST_H_RKNN0_BIU		275
++
++#define SRST_H_NVM_BIU			276
++#define SRST_A_NVM_BIU			277
++#define SRST_H_EMMC			278
++#define SRST_A_EMMC			279
++#define SRST_C_EMMC			280
++#define SRST_B_EMMC			281
++#define SRST_T_EMMC			282
++#define SRST_S_SFC			283
++#define SRST_H_SFC			284
++#define SRST_H_SFC_XIP			285
++
++#define SRST_P_GRF			286
++#define SRST_P_DEC_BIU			287
++#define SRST_P_PHP_BIU			288
++#define SRST_A_PCIE_GRIDGE		289
++#define SRST_A_PHP_BIU			290
++#define SRST_A_GMAC0			291
++#define SRST_A_GMAC1			292
++#define SRST_A_PCIE_BIU			293
++#define SRST_PCIE0_POWER_UP		294
++#define SRST_PCIE1_POWER_UP		295
++#define SRST_PCIE2_POWER_UP		296
++
++#define SRST_PCIE3_POWER_UP		297
++#define SRST_PCIE4_POWER_UP		298
++#define SRST_P_PCIE0			299
++#define SRST_P_PCIE1			300
++#define SRST_P_PCIE2			301
++#define SRST_P_PCIE3			302
++
++#define SRST_P_PCIE4			303
++#define SRST_A_PHP_GIC_ITS		304
++#define SRST_A_MMU_PCIE			305
++#define SRST_A_MMU_PHP			306
++#define SRST_A_MMU_BIU			307
++
++#define SRST_A_USB3OTG2			308
++
++#define SRST_PMALIVE0			309
++#define SRST_PMALIVE1			310
++#define SRST_PMALIVE2			311
++#define SRST_A_SATA0			312
++#define SRST_A_SATA1			313
++#define SRST_A_SATA2			314
++#define SRST_RXOOB0			315
++#define SRST_RXOOB1			316
++#define SRST_RXOOB2			317
++#define SRST_ASIC0			318
++#define SRST_ASIC1			319
++#define SRST_ASIC2			320
++
++#define SRST_A_RKVDEC_CCU		321
++#define SRST_H_RKVDEC0			322
++#define SRST_A_RKVDEC0			323
++#define SRST_H_RKVDEC0_BIU		324
++#define SRST_A_RKVDEC0_BIU		325
++#define SRST_RKVDEC0_CA			326
++#define SRST_RKVDEC0_HEVC_CA		327
++#define SRST_RKVDEC0_CORE		328
++
++#define SRST_H_RKVDEC1			329
++#define SRST_A_RKVDEC1			330
++#define SRST_H_RKVDEC1_BIU		331
++#define SRST_A_RKVDEC1_BIU		332
++#define SRST_RKVDEC1_CA			333
++#define SRST_RKVDEC1_HEVC_CA		334
++#define SRST_RKVDEC1_CORE		335
++
++#define SRST_A_USB_BIU			336
++#define SRST_H_USB_BIU			337
++#define SRST_A_USB3OTG0			338
++#define SRST_A_USB3OTG1			339
++#define SRST_H_HOST0			340
++#define SRST_H_HOST_ARB0		341
++#define SRST_H_HOST1			342
++#define SRST_H_HOST_ARB1		343
++#define SRST_A_USB_GRF			344
++#define SRST_C_USB2P0_HOST0		345
++
++#define SRST_C_USB2P0_HOST1		346
++#define SRST_HOST_UTMI0			347
++#define SRST_HOST_UTMI1			348
++
++#define SRST_A_VDPU_BIU			349
++#define SRST_A_VDPU_LOW_BIU		350
++#define SRST_H_VDPU_BIU			351
++#define SRST_A_JPEG_DECODER_BIU		352
++#define SRST_A_VPU			353
++#define SRST_H_VPU			354
++#define SRST_A_JPEG_ENCODER0		355
++#define SRST_H_JPEG_ENCODER0		356
++#define SRST_A_JPEG_ENCODER1		357
++#define SRST_H_JPEG_ENCODER1		358
++#define SRST_A_JPEG_ENCODER2		359
++#define SRST_H_JPEG_ENCODER2		360
++
++#define SRST_A_JPEG_ENCODER3		361
++#define SRST_H_JPEG_ENCODER3		362
++#define SRST_A_JPEG_DECODER		363
++#define SRST_H_JPEG_DECODER		364
++#define SRST_H_IEP2P0			365
++#define SRST_A_IEP2P0			366
++#define SRST_IEP2P0_CORE		367
++#define SRST_H_RGA2			368
++#define SRST_A_RGA2			369
++#define SRST_RGA2_CORE			370
++#define SRST_H_RGA3_0			371
++#define SRST_A_RGA3_0			372
++#define SRST_RGA3_0_CORE		373
++
++#define SRST_H_RKVENC0_BIU		374
++#define SRST_A_RKVENC0_BIU		375
++#define SRST_H_RKVENC0			376
++#define SRST_A_RKVENC0			377
++#define SRST_RKVENC0_CORE		378
++
++#define SRST_H_RKVENC1_BIU		379
++#define SRST_A_RKVENC1_BIU		380
++#define SRST_H_RKVENC1			381
++#define SRST_A_RKVENC1			382
++#define SRST_RKVENC1_CORE		383
++
++#define SRST_A_VI_BIU			384
++#define SRST_H_VI_BIU			385
++#define SRST_P_VI_BIU			386
++#define SRST_D_VICAP			387
++#define SRST_A_VICAP			388
++#define SRST_H_VICAP			389
++#define SRST_ISP0			390
++#define SRST_ISP0_VICAP			391
++
++#define SRST_FISHEYE0			392
++#define SRST_FISHEYE1			393
++#define SRST_P_CSI_HOST_0		394
++#define SRST_P_CSI_HOST_1		395
++#define SRST_P_CSI_HOST_2		396
++#define SRST_P_CSI_HOST_3		397
++#define SRST_P_CSI_HOST_4		398
++#define SRST_P_CSI_HOST_5		399
++
++#define SRST_CSIHOST0_VICAP		400
++#define SRST_CSIHOST1_VICAP		401
++#define SRST_CSIHOST2_VICAP		402
++#define SRST_CSIHOST3_VICAP		403
++#define SRST_CSIHOST4_VICAP		404
++#define SRST_CSIHOST5_VICAP		405
++#define SRST_CIFIN			406
++
++#define SRST_A_VOP_BIU			407
++#define SRST_A_VOP_LOW_BIU		408
++#define SRST_H_VOP_BIU			409
++#define SRST_P_VOP_BIU			410
++#define SRST_H_VOP			411
++#define SRST_A_VOP			412
++#define SRST_D_VOP0			413
++#define SRST_D_VOP2HDMI_BRIDGE0		414
++#define SRST_D_VOP2HDMI_BRIDGE1		415
++
++#define SRST_D_VOP1			416
++#define SRST_D_VOP2			417
++#define SRST_D_VOP3			418
++#define SRST_P_VOPGRF			419
++#define SRST_P_DSIHOST0			420
++#define SRST_P_DSIHOST1			421
++#define SRST_DSIHOST0			422
++#define SRST_DSIHOST1			423
++#define SRST_VOP_PMU			424
++#define SRST_P_VOP_CHANNEL_BIU		425
++
++#define SRST_H_VO0_BIU			426
++#define SRST_H_VO0_S_BIU		427
++#define SRST_P_VO0_BIU			428
++#define SRST_P_VO0_S_BIU		429
++#define SRST_A_HDCP0_BIU		430
++#define SRST_P_VO0GRF			431
++#define SRST_H_HDCP_KEY0		432
++#define SRST_A_HDCP0			433
++#define SRST_H_HDCP0			434
++#define SRST_HDCP0			435
++
++#define SRST_P_TRNG0			436
++#define SRST_DP0			437
++#define SRST_DP1			438
++#define SRST_H_I2S4_8CH			439
++#define SRST_M_I2S4_8CH_TX		440
++#define SRST_H_I2S8_8CH			441
++
++#define SRST_M_I2S8_8CH_TX		442
++#define SRST_H_SPDIF2_DP0		443
++#define SRST_M_SPDIF2_DP0		444
++#define SRST_H_SPDIF5_DP1		445
++#define SRST_M_SPDIF5_DP1		446
++
++#define SRST_A_HDCP1_BIU		447
++#define SRST_A_VO1_BIU			448
++#define SRST_H_VOP1_BIU			449
++#define SRST_H_VOP1_S_BIU		450
++#define SRST_P_VOP1_BIU			451
++#define SRST_P_VO1GRF			452
++#define SRST_P_VO1_S_BIU		453
++
++#define SRST_H_I2S7_8CH			454
++#define SRST_M_I2S7_8CH_RX		455
++#define SRST_H_HDCP_KEY1		456
++#define SRST_A_HDCP1			457
++#define SRST_H_HDCP1			458
++#define SRST_HDCP1			459
++#define SRST_P_TRNG1			460
++#define SRST_P_HDMITX0			461
++
++#define SRST_HDMITX0_REF		462
++#define SRST_P_HDMITX1			463
++#define SRST_HDMITX1_REF		464
++#define SRST_A_HDMIRX			465
++#define SRST_P_HDMIRX			466
++#define SRST_HDMIRX_REF			467
++
++#define SRST_P_EDP0			468
++#define SRST_EDP0_24M			469
++#define SRST_P_EDP1			470
++#define SRST_EDP1_24M			471
++#define SRST_M_I2S5_8CH_TX		472
++#define SRST_H_I2S5_8CH			473
++#define SRST_M_I2S6_8CH_TX		474
++
++#define SRST_M_I2S6_8CH_RX		475
++#define SRST_H_I2S6_8CH			476
++#define SRST_H_SPDIF3			477
++#define SRST_M_SPDIF3			478
++#define SRST_H_SPDIF4			479
++#define SRST_M_SPDIF4			480
++#define SRST_H_SPDIFRX0			481
++#define SRST_M_SPDIFRX0			482
++#define SRST_H_SPDIFRX1			483
++#define SRST_M_SPDIFRX1			484
++
++#define SRST_H_SPDIFRX2			485
++#define SRST_M_SPDIFRX2			486
++#define SRST_LINKSYM_HDMITXPHY0		487
++#define SRST_LINKSYM_HDMITXPHY1		488
++#define SRST_VO1_BRIDGE0		489
++#define SRST_VO1_BRIDGE1		490
++
++#define SRST_H_I2S9_8CH			491
++#define SRST_M_I2S9_8CH_RX		492
++#define SRST_H_I2S10_8CH		493
++#define SRST_M_I2S10_8CH_RX		494
++#define SRST_P_S_HDMIRX			495
++
++#define SRST_GPU			496
++#define SRST_SYS_GPU			497
++#define SRST_A_S_GPU_BIU		498
++#define SRST_A_M0_GPU_BIU		499
++#define SRST_A_M1_GPU_BIU		500
++#define SRST_A_M2_GPU_BIU		501
++#define SRST_A_M3_GPU_BIU		502
++#define SRST_P_GPU_BIU			503
++#define SRST_P_GPU_PVTM			504
++
++#define SRST_GPU_PVTM			505
++#define SRST_P_GPU_GRF			506
++#define SRST_GPU_PVTPLL			507
++#define SRST_GPU_JTAG			508
++
++#define SRST_A_AV1_BIU			509
++#define SRST_A_AV1			510
++#define SRST_P_AV1_BIU			511
++#define SRST_P_AV1			512
++
++#define SRST_A_DDR_BIU			513
++#define SRST_A_DMA2DDR			514
++#define SRST_A_DDR_SHAREMEM		515
++#define SRST_A_DDR_SHAREMEM_BIU		516
++#define SRST_A_CENTER_S200_BIU		517
++#define SRST_A_CENTER_S400_BIU		518
++#define SRST_H_AHB2APB			519
++#define SRST_H_CENTER_BIU		520
++#define SRST_F_DDR_CM0_CORE		521
++
++#define SRST_DDR_TIMER0			522
++#define SRST_DDR_TIMER1			523
++#define SRST_T_WDT_DDR			524
++#define SRST_T_DDR_CM0_JTAG		525
++#define SRST_P_CENTER_GRF		526
++#define SRST_P_AHB2APB			527
++#define SRST_P_WDT			528
++#define SRST_P_TIMER			529
++#define SRST_P_DMA2DDR			530
++#define SRST_P_SHAREMEM			531
++#define SRST_P_CENTER_BIU		532
++#define SRST_P_CENTER_CHANNEL_BIU	533
++
++#define SRST_P_USBDPGRF0		534
++#define SRST_P_USBDPPHY0		535
++#define SRST_P_USBDPGRF1		536
++#define SRST_P_USBDPPHY1		537
++#define SRST_P_HDPTX0			538
++#define SRST_P_HDPTX1			539
++#define SRST_P_APB2ASB_SLV_BOT_RIGHT	540
++#define SRST_P_USB2PHY_U3_0_GRF0	541
++#define SRST_P_USB2PHY_U3_1_GRF0	542
++#define SRST_P_USB2PHY_U2_0_GRF0	543
++#define SRST_P_USB2PHY_U2_1_GRF0	544
++#define SRST_HDPTX0_ROPLL		545
++#define SRST_HDPTX0_LCPLL		546
++#define SRST_HDPTX0			547
++#define SRST_HDPTX1_ROPLL		548
++
++#define SRST_HDPTX1_LCPLL		549
++#define SRST_HDPTX1			550
++#define SRST_HDPTX0_HDMIRXPHY_SET	551
++#define SRST_USBDP_COMBO_PHY0		552
++#define SRST_USBDP_COMBO_PHY0_LCPLL	553
++#define SRST_USBDP_COMBO_PHY0_ROPLL	554
++#define SRST_USBDP_COMBO_PHY0_PCS_HS	555
++#define SRST_USBDP_COMBO_PHY1		556
++#define SRST_USBDP_COMBO_PHY1_LCPLL	557
++#define SRST_USBDP_COMBO_PHY1_ROPLL	558
++#define SRST_USBDP_COMBO_PHY1_PCS_HS	559
++#define SRST_HDMIHDP0			560
++#define SRST_HDMIHDP1			561
++
++#define SRST_A_VO1USB_TOP_BIU		562
++#define SRST_H_VO1USB_TOP_BIU		563
++
++#define SRST_H_SDIO_BIU			564
++#define SRST_H_SDIO			565
++#define SRST_SDIO			566
++
++#define SRST_H_RGA3_BIU			567
++#define SRST_A_RGA3_BIU			568
++#define SRST_H_RGA3_1			569
++#define SRST_A_RGA3_1			570
++#define SRST_RGA3_1_CORE		571
++
++#define SRST_REF_PIPE_PHY0		572
++#define SRST_REF_PIPE_PHY1		573
++#define SRST_REF_PIPE_PHY2		574
++
++#define SRST_P_PHPTOP_CRU		575
++#define SRST_P_PCIE2_GRF0		576
++#define SRST_P_PCIE2_GRF1		577
++#define SRST_P_PCIE2_GRF2		578
++#define SRST_P_PCIE2_PHY0		579
++#define SRST_P_PCIE2_PHY1		580
++#define SRST_P_PCIE2_PHY2		581
++#define SRST_P_PCIE3_PHY		582
++#define SRST_P_APB2ASB_SLV_CHIP_TOP	583
++#define SRST_PCIE30_PHY			584
++
++#define SRST_H_PMU1_BIU			585
++#define SRST_P_PMU1_BIU			586
++#define SRST_H_PMU_CM0_BIU		587
++#define SRST_F_PMU_CM0_CORE		588
++#define SRST_T_PMU1_CM0_JTAG		589
++
++#define SRST_DDR_FAIL_SAFE		590
++#define SRST_P_CRU_PMU1			591
++#define SRST_P_PMU1_GRF			592
++#define SRST_P_PMU1_IOC			593
++#define SRST_P_PMU1WDT			594
++#define SRST_T_PMU1WDT			595
++#define SRST_P_PMU1TIMER		596
++#define SRST_PMU1TIMER0			597
++#define SRST_PMU1TIMER1			598
++#define SRST_P_PMU1PWM			599
++#define SRST_PMU1PWM			600
++
++#define SRST_P_I2C0			601
++#define SRST_I2C0			602
++#define SRST_S_UART0			603
++#define SRST_P_UART0			604
++#define SRST_H_I2S1_8CH			605
++#define SRST_M_I2S1_8CH_TX		606
++#define SRST_M_I2S1_8CH_RX		607
++#define SRST_H_PDM0			608
++#define SRST_PDM0			609
++
++#define SRST_H_VAD			610
++#define SRST_HDPTX0_INIT		611
++#define SRST_HDPTX0_CMN			612
++#define SRST_HDPTX0_LANE		613
++#define SRST_HDPTX1_INIT		614
++
++#define SRST_HDPTX1_CMN			615
++#define SRST_HDPTX1_LANE		616
++#define SRST_M_MIPI_DCPHY0		617
++#define SRST_S_MIPI_DCPHY0		618
++#define SRST_M_MIPI_DCPHY1		619
++#define SRST_S_MIPI_DCPHY1		620
++#define SRST_OTGPHY_U3_0		621
++#define SRST_OTGPHY_U3_1		622
++#define SRST_OTGPHY_U2_0		623
++#define SRST_OTGPHY_U2_1		624
++
++#define SRST_P_PMU0GRF			625
++#define SRST_P_PMU0IOC			626
++#define SRST_P_GPIO0			627
++#define SRST_GPIO0			628
++
++#define SRST_A_SECURE_NS_BIU		629
++#define SRST_H_SECURE_NS_BIU		630
++#define SRST_A_SECURE_S_BIU		631
++#define SRST_H_SECURE_S_BIU		632
++#define SRST_P_SECURE_S_BIU		633
++#define SRST_CRYPTO_CORE		634
++
++#define SRST_CRYPTO_PKA			635
++#define SRST_CRYPTO_RNG			636
++#define SRST_A_CRYPTO			637
++#define SRST_H_CRYPTO			638
++#define SRST_KEYLADDER_CORE		639
++#define SRST_KEYLADDER_RNG		640
++#define SRST_A_KEYLADDER		641
++#define SRST_H_KEYLADDER		642
++#define SRST_P_OTPC_S			643
++#define SRST_OTPC_S			644
++#define SRST_WDT_S			645
++
++#define SRST_T_WDT_S			646
++#define SRST_H_BOOTROM			647
++#define SRST_A_DCF			648
++#define SRST_P_DCF			649
++#define SRST_H_BOOTROM_NS		650
++#define SRST_P_KEYLADDER		651
++#define SRST_H_TRNG_S			652
++
++#define SRST_H_TRNG_NS			653
++#define SRST_D_SDMMC_BUFFER		654
++#define SRST_H_SDMMC			655
++#define SRST_H_SDMMC_BUFFER		656
++#define SRST_SDMMC			657
++#define SRST_P_TRNG_CHK			658
++#define SRST_TRNG_S			659
++
++#endif
diff --git a/target/linux/rockchip/patches-6.1/335-rtc-rk808-reduce-struct-rk808-usage.patch b/target/linux/rockchip/patches-6.1/335-rtc-rk808-reduce-struct-rk808-usage.patch
new file mode 100644
index 00000000000..21e67828267
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/335-rtc-rk808-reduce-struct-rk808-usage.patch
@@ -0,0 +1,216 @@
+From 65caf6731af81513a229157fa2fd6d469099375d Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Oct 2022 22:42:41 +0200
+Subject: [PATCH 335/383] rtc: rk808: reduce 'struct rk808' usage
+
+Reduce usage of 'struct rk808' (driver data of the parent MFD), so
+that only the chip variant field is still being accessed directly.
+This allows restructuring the MFD driver to support SPI based
+PMICs.
+
+Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221020204251.108565-4-sebastian.reichel@collabora.com
+Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/rtc/rtc-rk808.c | 47 ++++++++++++++++++-----------------------
+ 1 file changed, 20 insertions(+), 27 deletions(-)
+
+--- a/drivers/rtc/rtc-rk808.c
++++ b/drivers/rtc/rtc-rk808.c
+@@ -14,7 +14,6 @@
+ #include <linux/bcd.h>
+ #include <linux/mfd/rk808.h>
+ #include <linux/platform_device.h>
+-#include <linux/i2c.h>
+ 
+ /* RTC_CTRL_REG bitfields */
+ #define BIT_RTC_CTRL_REG_STOP_RTC_M		BIT(0)
+@@ -51,7 +50,7 @@ struct rk_rtc_compat_reg {
+ };
+ 
+ struct rk808_rtc {
+-	struct rk808 *rk808;
++	struct regmap *regmap;
+ 	struct rtc_device *rtc;
+ 	struct rk_rtc_compat_reg *creg;
+ 	int irq;
+@@ -97,12 +96,11 @@ static void gregorian_to_rockchip(struct
+ static int rk808_rtc_readtime(struct device *dev, struct rtc_time *tm)
+ {
+ 	struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+ 	u8 rtc_data[NUM_TIME_REGS];
+ 	int ret;
+ 
+ 	/* Force an update of the shadowed registers right now */
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
+ 				 BIT_RTC_CTRL_REG_RTC_GET_TIME,
+ 				 BIT_RTC_CTRL_REG_RTC_GET_TIME);
+ 	if (ret) {
+@@ -116,7 +114,7 @@ static int rk808_rtc_readtime(struct dev
+ 	 * 32khz. If we clear the GET_TIME bit here, the time of i2c transfer
+ 	 * certainly more than 31.25us: 16 * 2.5us at 400kHz bus frequency.
+ 	 */
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
+ 				 BIT_RTC_CTRL_REG_RTC_GET_TIME,
+ 				 0);
+ 	if (ret) {
+@@ -124,7 +122,7 @@ static int rk808_rtc_readtime(struct dev
+ 		return ret;
+ 	}
+ 
+-	ret = regmap_bulk_read(rk808->regmap, rk808_rtc->creg->seconds_reg,
++	ret = regmap_bulk_read(rk808_rtc->regmap, rk808_rtc->creg->seconds_reg,
+ 			       rtc_data, NUM_TIME_REGS);
+ 	if (ret) {
+ 		dev_err(dev, "Failed to bulk read rtc_data: %d\n", ret);
+@@ -148,7 +146,6 @@ static int rk808_rtc_readtime(struct dev
+ static int rk808_rtc_set_time(struct device *dev, struct rtc_time *tm)
+ {
+ 	struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+ 	u8 rtc_data[NUM_TIME_REGS];
+ 	int ret;
+ 
+@@ -163,7 +160,7 @@ static int rk808_rtc_set_time(struct dev
+ 	rtc_data[6] = bin2bcd(tm->tm_wday);
+ 
+ 	/* Stop RTC while updating the RTC registers */
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
+ 				 BIT_RTC_CTRL_REG_STOP_RTC_M,
+ 				 BIT_RTC_CTRL_REG_STOP_RTC_M);
+ 	if (ret) {
+@@ -171,14 +168,14 @@ static int rk808_rtc_set_time(struct dev
+ 		return ret;
+ 	}
+ 
+-	ret = regmap_bulk_write(rk808->regmap, rk808_rtc->creg->seconds_reg,
++	ret = regmap_bulk_write(rk808_rtc->regmap, rk808_rtc->creg->seconds_reg,
+ 				rtc_data, NUM_TIME_REGS);
+ 	if (ret) {
+ 		dev_err(dev, "Failed to bull write rtc_data: %d\n", ret);
+ 		return ret;
+ 	}
+ 	/* Start RTC again */
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
+ 				 BIT_RTC_CTRL_REG_STOP_RTC_M, 0);
+ 	if (ret) {
+ 		dev_err(dev, "Failed to update RTC control: %d\n", ret);
+@@ -191,12 +188,11 @@ static int rk808_rtc_set_time(struct dev
+ static int rk808_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+ 	struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+ 	u8 alrm_data[NUM_ALARM_REGS];
+ 	uint32_t int_reg;
+ 	int ret;
+ 
+-	ret = regmap_bulk_read(rk808->regmap,
++	ret = regmap_bulk_read(rk808_rtc->regmap,
+ 			       rk808_rtc->creg->alarm_seconds_reg,
+ 			       alrm_data, NUM_ALARM_REGS);
+ 	if (ret) {
+@@ -212,7 +208,7 @@ static int rk808_rtc_readalarm(struct de
+ 	alrm->time.tm_year = (bcd2bin(alrm_data[5] & YEARS_REG_MSK)) + 100;
+ 	rockchip_to_gregorian(&alrm->time);
+ 
+-	ret = regmap_read(rk808->regmap, rk808_rtc->creg->int_reg, &int_reg);
++	ret = regmap_read(rk808_rtc->regmap, rk808_rtc->creg->int_reg, &int_reg);
+ 	if (ret) {
+ 		dev_err(dev, "Failed to read RTC INT REG: %d\n", ret);
+ 		return ret;
+@@ -228,10 +224,9 @@ static int rk808_rtc_readalarm(struct de
+ 
+ static int rk808_rtc_stop_alarm(struct rk808_rtc *rk808_rtc)
+ {
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+ 	int ret;
+ 
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->int_reg,
+ 				 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M, 0);
+ 
+ 	return ret;
+@@ -239,10 +234,9 @@ static int rk808_rtc_stop_alarm(struct r
+ 
+ static int rk808_rtc_start_alarm(struct rk808_rtc *rk808_rtc)
+ {
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+ 	int ret;
+ 
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->int_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->int_reg,
+ 				 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M,
+ 				 BIT_RTC_INTERRUPTS_REG_IT_ALARM_M);
+ 
+@@ -252,7 +246,6 @@ static int rk808_rtc_start_alarm(struct
+ static int rk808_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
+ {
+ 	struct rk808_rtc *rk808_rtc = dev_get_drvdata(dev);
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+ 	u8 alrm_data[NUM_ALARM_REGS];
+ 	int ret;
+ 
+@@ -272,7 +265,7 @@ static int rk808_rtc_setalarm(struct dev
+ 	alrm_data[4] = bin2bcd(alrm->time.tm_mon + 1);
+ 	alrm_data[5] = bin2bcd(alrm->time.tm_year - 100);
+ 
+-	ret = regmap_bulk_write(rk808->regmap,
++	ret = regmap_bulk_write(rk808_rtc->regmap,
+ 				rk808_rtc->creg->alarm_seconds_reg,
+ 				alrm_data, NUM_ALARM_REGS);
+ 	if (ret) {
+@@ -313,20 +306,18 @@ static int rk808_rtc_alarm_irq_enable(st
+ static irqreturn_t rk808_alarm_irq(int irq, void *data)
+ {
+ 	struct rk808_rtc *rk808_rtc = data;
+-	struct rk808 *rk808 = rk808_rtc->rk808;
+-	struct i2c_client *client = rk808->i2c;
+ 	int ret;
+ 
+-	ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg,
++	ret = regmap_write(rk808_rtc->regmap, rk808_rtc->creg->status_reg,
+ 			   RTC_STATUS_MASK);
+ 	if (ret) {
+-		dev_err(&client->dev,
++		dev_err(&rk808_rtc->rtc->dev,
+ 			"%s:Failed to update RTC status: %d\n", __func__, ret);
+ 		return ret;
+ 	}
+ 
+ 	rtc_update_irq(rk808_rtc->rtc, 1, RTC_IRQF | RTC_AF);
+-	dev_dbg(&client->dev,
++	dev_dbg(&rk808_rtc->rtc->dev,
+ 		 "%s:irq=%d\n", __func__, irq);
+ 	return IRQ_HANDLED;
+ }
+@@ -404,10 +395,12 @@ static int rk808_rtc_probe(struct platfo
+ 		break;
+ 	}
+ 	platform_set_drvdata(pdev, rk808_rtc);
+-	rk808_rtc->rk808 = rk808;
++	rk808_rtc->regmap = dev_get_regmap(pdev->dev.parent, NULL);
++	if (!rk808_rtc->regmap)
++		return -ENODEV;
+ 
+ 	/* start rtc running by default, and use shadowed timer. */
+-	ret = regmap_update_bits(rk808->regmap, rk808_rtc->creg->ctrl_reg,
++	ret = regmap_update_bits(rk808_rtc->regmap, rk808_rtc->creg->ctrl_reg,
+ 				 BIT_RTC_CTRL_REG_STOP_RTC_M |
+ 				 BIT_RTC_CTRL_REG_RTC_READSEL_M,
+ 				 BIT_RTC_CTRL_REG_RTC_READSEL_M);
+@@ -417,7 +410,7 @@ static int rk808_rtc_probe(struct platfo
+ 		return ret;
+ 	}
+ 
+-	ret = regmap_write(rk808->regmap, rk808_rtc->creg->status_reg,
++	ret = regmap_write(rk808_rtc->regmap, rk808_rtc->creg->status_reg,
+ 			   RTC_STATUS_MASK);
+ 	if (ret) {
+ 		dev_err(&pdev->dev,
diff --git a/target/linux/rockchip/patches-6.1/336-dt-bindings-clock-add-rk3588-clock-definitions.patch b/target/linux/rockchip/patches-6.1/336-dt-bindings-clock-add-rk3588-clock-definitions.patch
new file mode 100644
index 00000000000..11a16bb52d0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/336-dt-bindings-clock-add-rk3588-clock-definitions.patch
@@ -0,0 +1,793 @@
+From 80be6056185f51cfa7092608e2176c72a4d1573e Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 18 Oct 2022 17:13:59 +0200
+Subject: [PATCH 336/383] dt-bindings: clock: add rk3588 clock definitions
+
+Add clock ID defines for rk3588.
+
+Compared to the downstream bindings written by Elaine, this uses
+continous gapless clock IDs starting at 0. Thus all numbers are
+different between downstream and upstream, but I kept exactly the
+same names.
+
+Co-Developed-by: Elaine Zhang <zhangqing@rock-chips.com>
+Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Link: https://lore.kernel.org/r/20221018151407.63395-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dt-bindings/clock/rockchip,rk3588-cru.h   | 766 ++++++++++++++++++
+ 1 file changed, 766 insertions(+)
+ create mode 100644 include/dt-bindings/clock/rockchip,rk3588-cru.h
+
+--- /dev/null
++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
+@@ -0,0 +1,766 @@
++/* SPDX-License-Identifier: (GPL-2.0 or MIT) */
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co. Ltd.
++ * Copyright (c) 2022 Collabora Ltd.
++ *
++ * Author: Elaine Zhang <zhangqing@rock-chips.com>
++ * Author: Sebastian Reichel <sebastian.reichel@collabora.com>
++ */
++
++#ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
++#define _DT_BINDINGS_CLK_ROCKCHIP_RK3588_H
++
++/* cru-clocks indices */
++
++#define PLL_B0PLL			0
++#define PLL_B1PLL			1
++#define PLL_LPLL			2
++#define PLL_V0PLL			3
++#define PLL_AUPLL			4
++#define PLL_CPLL			5
++#define PLL_GPLL			6
++#define PLL_NPLL			7
++#define PLL_PPLL			8
++#define ARMCLK_L			9
++#define ARMCLK_B01			10
++#define ARMCLK_B23			11
++#define PCLK_BIGCORE0_ROOT		12
++#define PCLK_BIGCORE0_PVTM		13
++#define PCLK_BIGCORE1_ROOT		14
++#define PCLK_BIGCORE1_PVTM		15
++#define PCLK_DSU_S_ROOT			16
++#define PCLK_DSU_ROOT			17
++#define PCLK_DSU_NS_ROOT		18
++#define PCLK_LITCORE_PVTM		19
++#define PCLK_DBG			20
++#define PCLK_DSU			21
++#define PCLK_S_DAPLITE			22
++#define PCLK_M_DAPLITE			23
++#define MBIST_MCLK_PDM1			24
++#define MBIST_CLK_ACDCDIG		25
++#define HCLK_I2S2_2CH			26
++#define HCLK_I2S3_2CH			27
++#define CLK_I2S2_2CH_SRC		28
++#define CLK_I2S2_2CH_FRAC		29
++#define CLK_I2S2_2CH			30
++#define MCLK_I2S2_2CH			31
++#define I2S2_2CH_MCLKOUT		32
++#define CLK_DAC_ACDCDIG			33
++#define CLK_I2S3_2CH_SRC		34
++#define CLK_I2S3_2CH_FRAC		35
++#define CLK_I2S3_2CH			36
++#define MCLK_I2S3_2CH			37
++#define I2S3_2CH_MCLKOUT		38
++#define PCLK_ACDCDIG			39
++#define HCLK_I2S0_8CH			40
++#define CLK_I2S0_8CH_TX_SRC		41
++#define CLK_I2S0_8CH_TX_FRAC		42
++#define MCLK_I2S0_8CH_TX		43
++#define CLK_I2S0_8CH_TX			44
++#define CLK_I2S0_8CH_RX_SRC		45
++#define CLK_I2S0_8CH_RX_FRAC		46
++#define MCLK_I2S0_8CH_RX		47
++#define CLK_I2S0_8CH_RX			48
++#define I2S0_8CH_MCLKOUT		49
++#define HCLK_PDM1			50
++#define MCLK_PDM1			51
++#define HCLK_AUDIO_ROOT			52
++#define PCLK_AUDIO_ROOT			53
++#define HCLK_SPDIF0			54
++#define CLK_SPDIF0_SRC			55
++#define CLK_SPDIF0_FRAC			56
++#define MCLK_SPDIF0			57
++#define CLK_SPDIF0			58
++#define CLK_SPDIF1			59
++#define HCLK_SPDIF1			60
++#define CLK_SPDIF1_SRC			61
++#define CLK_SPDIF1_FRAC			62
++#define MCLK_SPDIF1			63
++#define ACLK_AV1_ROOT			64
++#define ACLK_AV1			65
++#define PCLK_AV1_ROOT			66
++#define PCLK_AV1			67
++#define PCLK_MAILBOX0			68
++#define PCLK_MAILBOX1			69
++#define PCLK_MAILBOX2			70
++#define PCLK_PMU2			71
++#define PCLK_PMUCM0_INTMUX		72
++#define PCLK_DDRCM0_INTMUX		73
++#define PCLK_TOP			74
++#define PCLK_PWM1			75
++#define CLK_PWM1			76
++#define CLK_PWM1_CAPTURE		77
++#define PCLK_PWM2			78
++#define CLK_PWM2			79
++#define CLK_PWM2_CAPTURE		80
++#define PCLK_PWM3			81
++#define CLK_PWM3			82
++#define CLK_PWM3_CAPTURE		83
++#define PCLK_BUSTIMER0			84
++#define PCLK_BUSTIMER1			85
++#define CLK_BUS_TIMER_ROOT		86
++#define CLK_BUSTIMER0			87
++#define CLK_BUSTIMER1			88
++#define CLK_BUSTIMER2			89
++#define CLK_BUSTIMER3			90
++#define CLK_BUSTIMER4			91
++#define CLK_BUSTIMER5			92
++#define CLK_BUSTIMER6			93
++#define CLK_BUSTIMER7			94
++#define CLK_BUSTIMER8			95
++#define CLK_BUSTIMER9			96
++#define CLK_BUSTIMER10			97
++#define CLK_BUSTIMER11			98
++#define PCLK_WDT0			99
++#define TCLK_WDT0			100
++#define PCLK_CAN0			101
++#define CLK_CAN0			102
++#define PCLK_CAN1			103
++#define CLK_CAN1			104
++#define PCLK_CAN2			105
++#define CLK_CAN2			106
++#define ACLK_DECOM			107
++#define PCLK_DECOM			108
++#define DCLK_DECOM			109
++#define ACLK_DMAC0			110
++#define ACLK_DMAC1			111
++#define ACLK_DMAC2			112
++#define ACLK_BUS_ROOT			113
++#define ACLK_GIC			114
++#define PCLK_GPIO1			115
++#define DBCLK_GPIO1			116
++#define PCLK_GPIO2			117
++#define DBCLK_GPIO2			118
++#define PCLK_GPIO3			119
++#define DBCLK_GPIO3			120
++#define PCLK_GPIO4			121
++#define DBCLK_GPIO4			122
++#define PCLK_I2C1			123
++#define PCLK_I2C2			124
++#define PCLK_I2C3			125
++#define PCLK_I2C4			126
++#define PCLK_I2C5			127
++#define PCLK_I2C6			128
++#define PCLK_I2C7			129
++#define PCLK_I2C8			130
++#define CLK_I2C1			131
++#define CLK_I2C2			132
++#define CLK_I2C3			133
++#define CLK_I2C4			134
++#define CLK_I2C5			135
++#define CLK_I2C6			136
++#define CLK_I2C7			137
++#define CLK_I2C8			138
++#define PCLK_OTPC_NS			139
++#define CLK_OTPC_NS			140
++#define CLK_OTPC_ARB			141
++#define CLK_OTPC_AUTO_RD_G		142
++#define CLK_OTP_PHY_G			143
++#define PCLK_SARADC			144
++#define CLK_SARADC			145
++#define PCLK_SPI0			146
++#define PCLK_SPI1			147
++#define PCLK_SPI2			148
++#define PCLK_SPI3			149
++#define PCLK_SPI4			150
++#define CLK_SPI0			151
++#define CLK_SPI1			152
++#define CLK_SPI2			153
++#define CLK_SPI3			154
++#define CLK_SPI4			155
++#define ACLK_SPINLOCK			156
++#define PCLK_TSADC			157
++#define CLK_TSADC			158
++#define PCLK_UART1			159
++#define PCLK_UART2			160
++#define PCLK_UART3			161
++#define PCLK_UART4			162
++#define PCLK_UART5			163
++#define PCLK_UART6			164
++#define PCLK_UART7			165
++#define PCLK_UART8			166
++#define PCLK_UART9			167
++#define CLK_UART1_SRC			168
++#define CLK_UART1_FRAC			169
++#define CLK_UART1			170
++#define SCLK_UART1			171
++#define CLK_UART2_SRC			172
++#define CLK_UART2_FRAC			173
++#define CLK_UART2			174
++#define SCLK_UART2			175
++#define CLK_UART3_SRC			176
++#define CLK_UART3_FRAC			177
++#define CLK_UART3			178
++#define SCLK_UART3			179
++#define CLK_UART4_SRC			180
++#define CLK_UART4_FRAC			181
++#define CLK_UART4			182
++#define SCLK_UART4			183
++#define CLK_UART5_SRC			184
++#define CLK_UART5_FRAC			185
++#define CLK_UART5			186
++#define SCLK_UART5			187
++#define CLK_UART6_SRC			188
++#define CLK_UART6_FRAC			189
++#define CLK_UART6			190
++#define SCLK_UART6			191
++#define CLK_UART7_SRC			192
++#define CLK_UART7_FRAC			193
++#define CLK_UART7			194
++#define SCLK_UART7			195
++#define CLK_UART8_SRC			196
++#define CLK_UART8_FRAC			197
++#define CLK_UART8			198
++#define SCLK_UART8			199
++#define CLK_UART9_SRC			200
++#define CLK_UART9_FRAC			201
++#define CLK_UART9			202
++#define SCLK_UART9			203
++#define ACLK_CENTER_ROOT		204
++#define ACLK_CENTER_LOW_ROOT		205
++#define HCLK_CENTER_ROOT		206
++#define PCLK_CENTER_ROOT		207
++#define ACLK_DMA2DDR			208
++#define ACLK_DDR_SHAREMEM		209
++#define ACLK_CENTER_S200_ROOT		210
++#define ACLK_CENTER_S400_ROOT		211
++#define FCLK_DDR_CM0_CORE		212
++#define CLK_DDR_TIMER_ROOT		213
++#define CLK_DDR_TIMER0			214
++#define CLK_DDR_TIMER1			215
++#define TCLK_WDT_DDR			216
++#define CLK_DDR_CM0_RTC			217
++#define PCLK_WDT			218
++#define PCLK_TIMER			219
++#define PCLK_DMA2DDR			220
++#define PCLK_SHAREMEM			221
++#define CLK_50M_SRC			222
++#define CLK_100M_SRC			223
++#define CLK_150M_SRC			224
++#define CLK_200M_SRC			225
++#define CLK_250M_SRC			226
++#define CLK_300M_SRC			227
++#define CLK_350M_SRC			228
++#define CLK_400M_SRC			229
++#define CLK_450M_SRC			230
++#define CLK_500M_SRC			231
++#define CLK_600M_SRC			232
++#define CLK_650M_SRC			233
++#define CLK_700M_SRC			234
++#define CLK_800M_SRC			235
++#define CLK_1000M_SRC			236
++#define CLK_1200M_SRC			237
++#define ACLK_TOP_M300_ROOT		238
++#define ACLK_TOP_M500_ROOT		239
++#define ACLK_TOP_M400_ROOT		240
++#define ACLK_TOP_S200_ROOT		241
++#define ACLK_TOP_S400_ROOT		242
++#define CLK_MIPI_CAMARAOUT_M0		243
++#define CLK_MIPI_CAMARAOUT_M1		244
++#define CLK_MIPI_CAMARAOUT_M2		245
++#define CLK_MIPI_CAMARAOUT_M3		246
++#define CLK_MIPI_CAMARAOUT_M4		247
++#define MCLK_GMAC0_OUT			248
++#define REFCLKO25M_ETH0_OUT		249
++#define REFCLKO25M_ETH1_OUT		250
++#define CLK_CIFOUT_OUT			251
++#define PCLK_MIPI_DCPHY0		252
++#define PCLK_MIPI_DCPHY1		253
++#define PCLK_CSIPHY0			254
++#define PCLK_CSIPHY1			255
++#define ACLK_TOP_ROOT			256
++#define PCLK_TOP_ROOT			257
++#define ACLK_LOW_TOP_ROOT		258
++#define PCLK_CRU			259
++#define PCLK_GPU_ROOT			260
++#define CLK_GPU_SRC			261
++#define CLK_GPU				262
++#define CLK_GPU_COREGROUP		263
++#define CLK_GPU_STACKS			264
++#define PCLK_GPU_PVTM			265
++#define CLK_GPU_PVTM			266
++#define CLK_CORE_GPU_PVTM		267
++#define PCLK_GPU_GRF			268
++#define ACLK_ISP1_ROOT			269
++#define HCLK_ISP1_ROOT			270
++#define CLK_ISP1_CORE			271
++#define CLK_ISP1_CORE_MARVIN		272
++#define CLK_ISP1_CORE_VICAP		273
++#define ACLK_ISP1			274
++#define HCLK_ISP1			275
++#define ACLK_NPU1			276
++#define HCLK_NPU1			277
++#define ACLK_NPU2			278
++#define HCLK_NPU2			279
++#define HCLK_NPU_CM0_ROOT		280
++#define FCLK_NPU_CM0_CORE		281
++#define CLK_NPU_CM0_RTC			282
++#define PCLK_NPU_PVTM			283
++#define PCLK_NPU_GRF			284
++#define CLK_NPU_PVTM			285
++#define CLK_CORE_NPU_PVTM		286
++#define ACLK_NPU0			287
++#define HCLK_NPU0			288
++#define HCLK_NPU_ROOT			289
++#define CLK_NPU_DSU0			290
++#define PCLK_NPU_ROOT			291
++#define PCLK_NPU_TIMER			292
++#define CLK_NPUTIMER_ROOT		293
++#define CLK_NPUTIMER0			294
++#define CLK_NPUTIMER1			295
++#define PCLK_NPU_WDT			296
++#define TCLK_NPU_WDT			297
++#define HCLK_EMMC			298
++#define ACLK_EMMC			299
++#define CCLK_EMMC			300
++#define BCLK_EMMC			301
++#define TMCLK_EMMC			302
++#define SCLK_SFC			303
++#define HCLK_SFC			304
++#define HCLK_SFC_XIP			305
++#define HCLK_NVM_ROOT			306
++#define ACLK_NVM_ROOT			307
++#define CLK_GMAC0_PTP_REF		308
++#define CLK_GMAC1_PTP_REF		309
++#define CLK_GMAC_125M			310
++#define CLK_GMAC_50M			311
++#define ACLK_PHP_GIC_ITS		312
++#define ACLK_MMU_PCIE			313
++#define ACLK_MMU_PHP			314
++#define ACLK_PCIE_4L_DBI		315
++#define ACLK_PCIE_2L_DBI		316
++#define ACLK_PCIE_1L0_DBI		317
++#define ACLK_PCIE_1L1_DBI		318
++#define ACLK_PCIE_1L2_DBI		319
++#define ACLK_PCIE_4L_MSTR		320
++#define ACLK_PCIE_2L_MSTR		321
++#define ACLK_PCIE_1L0_MSTR		322
++#define ACLK_PCIE_1L1_MSTR		323
++#define ACLK_PCIE_1L2_MSTR		324
++#define ACLK_PCIE_4L_SLV		325
++#define ACLK_PCIE_2L_SLV		326
++#define ACLK_PCIE_1L0_SLV		327
++#define ACLK_PCIE_1L1_SLV		328
++#define ACLK_PCIE_1L2_SLV		329
++#define PCLK_PCIE_4L			330
++#define PCLK_PCIE_2L			331
++#define PCLK_PCIE_1L0			332
++#define PCLK_PCIE_1L1			333
++#define PCLK_PCIE_1L2			334
++#define CLK_PCIE_AUX0			335
++#define CLK_PCIE_AUX1			336
++#define CLK_PCIE_AUX2			337
++#define CLK_PCIE_AUX3			338
++#define CLK_PCIE_AUX4			339
++#define CLK_PIPEPHY0_REF		340
++#define CLK_PIPEPHY1_REF		341
++#define CLK_PIPEPHY2_REF		342
++#define PCLK_PHP_ROOT			343
++#define PCLK_GMAC0			344
++#define PCLK_GMAC1			345
++#define ACLK_PCIE_ROOT			346
++#define ACLK_PHP_ROOT			347
++#define ACLK_PCIE_BRIDGE		348
++#define ACLK_GMAC0			349
++#define ACLK_GMAC1			350
++#define CLK_PMALIVE0			351
++#define CLK_PMALIVE1			352
++#define CLK_PMALIVE2			353
++#define ACLK_SATA0			354
++#define ACLK_SATA1			355
++#define ACLK_SATA2			356
++#define CLK_RXOOB0			357
++#define CLK_RXOOB1			358
++#define CLK_RXOOB2			359
++#define ACLK_USB3OTG2			360
++#define SUSPEND_CLK_USB3OTG2		361
++#define REF_CLK_USB3OTG2		362
++#define CLK_UTMI_OTG2			363
++#define CLK_PIPEPHY0_PIPE_G		364
++#define CLK_PIPEPHY1_PIPE_G		365
++#define CLK_PIPEPHY2_PIPE_G		366
++#define CLK_PIPEPHY0_PIPE_ASIC_G	367
++#define CLK_PIPEPHY1_PIPE_ASIC_G	368
++#define CLK_PIPEPHY2_PIPE_ASIC_G	369
++#define CLK_PIPEPHY2_PIPE_U3_G		370
++#define CLK_PCIE1L2_PIPE		371
++#define CLK_PCIE4L_PIPE			372
++#define CLK_PCIE2L_PIPE			373
++#define PCLK_PCIE_COMBO_PIPE_PHY0	374
++#define PCLK_PCIE_COMBO_PIPE_PHY1	375
++#define PCLK_PCIE_COMBO_PIPE_PHY2	376
++#define PCLK_PCIE_COMBO_PIPE_PHY	377
++#define HCLK_RGA3_1			378
++#define ACLK_RGA3_1			379
++#define CLK_RGA3_1_CORE			380
++#define ACLK_RGA3_ROOT			381
++#define HCLK_RGA3_ROOT			382
++#define ACLK_RKVDEC_CCU			383
++#define HCLK_RKVDEC0			384
++#define ACLK_RKVDEC0			385
++#define CLK_RKVDEC0_CA			386
++#define CLK_RKVDEC0_HEVC_CA		387
++#define CLK_RKVDEC0_CORE		388
++#define HCLK_RKVDEC1			389
++#define ACLK_RKVDEC1			390
++#define CLK_RKVDEC1_CA			391
++#define CLK_RKVDEC1_HEVC_CA		392
++#define CLK_RKVDEC1_CORE		393
++#define HCLK_SDIO			394
++#define CCLK_SRC_SDIO			395
++#define ACLK_USB_ROOT			396
++#define HCLK_USB_ROOT			397
++#define HCLK_HOST0			398
++#define HCLK_HOST_ARB0			399
++#define HCLK_HOST1			400
++#define HCLK_HOST_ARB1			401
++#define ACLK_USB3OTG0			402
++#define SUSPEND_CLK_USB3OTG0		403
++#define REF_CLK_USB3OTG0		404
++#define ACLK_USB3OTG1			405
++#define SUSPEND_CLK_USB3OTG1		406
++#define REF_CLK_USB3OTG1		407
++#define UTMI_OHCI_CLK48_HOST0		408
++#define UTMI_OHCI_CLK48_HOST1		409
++#define HCLK_IEP2P0			410
++#define ACLK_IEP2P0			411
++#define CLK_IEP2P0_CORE			412
++#define ACLK_JPEG_ENCODER0		413
++#define HCLK_JPEG_ENCODER0		414
++#define ACLK_JPEG_ENCODER1		415
++#define HCLK_JPEG_ENCODER1		416
++#define ACLK_JPEG_ENCODER2		417
++#define HCLK_JPEG_ENCODER2		418
++#define ACLK_JPEG_ENCODER3		419
++#define HCLK_JPEG_ENCODER3		420
++#define ACLK_JPEG_DECODER		421
++#define HCLK_JPEG_DECODER		422
++#define HCLK_RGA2			423
++#define ACLK_RGA2			424
++#define CLK_RGA2_CORE			425
++#define HCLK_RGA3_0			426
++#define ACLK_RGA3_0			427
++#define CLK_RGA3_0_CORE			428
++#define ACLK_VDPU_ROOT			429
++#define ACLK_VDPU_LOW_ROOT		430
++#define HCLK_VDPU_ROOT			431
++#define ACLK_JPEG_DECODER_ROOT		432
++#define ACLK_VPU			433
++#define HCLK_VPU			434
++#define HCLK_RKVENC0_ROOT		435
++#define ACLK_RKVENC0_ROOT		436
++#define HCLK_RKVENC0			437
++#define ACLK_RKVENC0			438
++#define CLK_RKVENC0_CORE		439
++#define HCLK_RKVENC1_ROOT		440
++#define ACLK_RKVENC1_ROOT		441
++#define HCLK_RKVENC1			442
++#define ACLK_RKVENC1			443
++#define CLK_RKVENC1_CORE		444
++#define ICLK_CSIHOST01			445
++#define ICLK_CSIHOST0			446
++#define ICLK_CSIHOST1			447
++#define PCLK_CSI_HOST_0			448
++#define PCLK_CSI_HOST_1			449
++#define PCLK_CSI_HOST_2			450
++#define PCLK_CSI_HOST_3			451
++#define PCLK_CSI_HOST_4			452
++#define PCLK_CSI_HOST_5			453
++#define ACLK_FISHEYE0			454
++#define HCLK_FISHEYE0			455
++#define CLK_FISHEYE0_CORE		456
++#define ACLK_FISHEYE1			457
++#define HCLK_FISHEYE1			458
++#define CLK_FISHEYE1_CORE		459
++#define CLK_ISP0_CORE			460
++#define CLK_ISP0_CORE_MARVIN		461
++#define CLK_ISP0_CORE_VICAP		462
++#define ACLK_ISP0			463
++#define HCLK_ISP0			464
++#define ACLK_VI_ROOT			465
++#define HCLK_VI_ROOT			466
++#define PCLK_VI_ROOT			467
++#define DCLK_VICAP			468
++#define ACLK_VICAP			469
++#define HCLK_VICAP			470
++#define PCLK_DP0			471
++#define PCLK_DP1			472
++#define PCLK_S_DP0			473
++#define PCLK_S_DP1			474
++#define CLK_DP0				475
++#define CLK_DP1				476
++#define HCLK_HDCP_KEY0			477
++#define ACLK_HDCP0			478
++#define HCLK_HDCP0			479
++#define PCLK_HDCP0			480
++#define HCLK_I2S4_8CH			481
++#define ACLK_TRNG0			482
++#define PCLK_TRNG0			483
++#define ACLK_VO0_ROOT			484
++#define HCLK_VO0_ROOT			485
++#define HCLK_VO0_S_ROOT			486
++#define PCLK_VO0_ROOT			487
++#define PCLK_VO0_S_ROOT			488
++#define PCLK_VO0GRF			489
++#define CLK_I2S4_8CH_TX_SRC		490
++#define CLK_I2S4_8CH_TX_FRAC		491
++#define MCLK_I2S4_8CH_TX		492
++#define CLK_I2S4_8CH_TX			493
++#define HCLK_I2S8_8CH			494
++#define CLK_I2S8_8CH_TX_SRC		495
++#define CLK_I2S8_8CH_TX_FRAC		496
++#define MCLK_I2S8_8CH_TX		497
++#define CLK_I2S8_8CH_TX			498
++#define HCLK_SPDIF2_DP0			499
++#define CLK_SPDIF2_DP0_SRC		500
++#define CLK_SPDIF2_DP0_FRAC		501
++#define MCLK_SPDIF2_DP0			502
++#define CLK_SPDIF2_DP0			503
++#define MCLK_SPDIF2			504
++#define HCLK_SPDIF5_DP1			505
++#define CLK_SPDIF5_DP1_SRC		506
++#define CLK_SPDIF5_DP1_FRAC		507
++#define MCLK_SPDIF5_DP1			508
++#define CLK_SPDIF5_DP1			509
++#define MCLK_SPDIF5			510
++#define PCLK_EDP0			511
++#define CLK_EDP0_24M			512
++#define CLK_EDP0_200M			513
++#define PCLK_EDP1			514
++#define CLK_EDP1_24M			515
++#define CLK_EDP1_200M			516
++#define HCLK_HDCP_KEY1			517
++#define ACLK_HDCP1			518
++#define HCLK_HDCP1			519
++#define PCLK_HDCP1			520
++#define ACLK_HDMIRX			521
++#define PCLK_HDMIRX			522
++#define CLK_HDMIRX_REF			523
++#define CLK_HDMIRX_AUD_SRC		524
++#define CLK_HDMIRX_AUD_FRAC		525
++#define CLK_HDMIRX_AUD			526
++#define CLK_HDMIRX_AUD_P_MUX		527
++#define PCLK_HDMITX0			528
++#define CLK_HDMITX0_EARC		529
++#define CLK_HDMITX0_REF			530
++#define PCLK_HDMITX1			531
++#define CLK_HDMITX1_EARC		532
++#define CLK_HDMITX1_REF			533
++#define CLK_HDMITRX_REFSRC		534
++#define ACLK_TRNG1			535
++#define PCLK_TRNG1			536
++#define ACLK_HDCP1_ROOT			537
++#define ACLK_HDMIRX_ROOT		538
++#define HCLK_VO1_ROOT			539
++#define HCLK_VO1_S_ROOT			540
++#define PCLK_VO1_ROOT			541
++#define PCLK_VO1_S_ROOT			542
++#define PCLK_S_EDP0			543
++#define PCLK_S_EDP1			544
++#define PCLK_S_HDMIRX			545
++#define HCLK_I2S10_8CH			546
++#define CLK_I2S10_8CH_RX_SRC		547
++#define CLK_I2S10_8CH_RX_FRAC		548
++#define CLK_I2S10_8CH_RX		549
++#define MCLK_I2S10_8CH_RX		550
++#define HCLK_I2S7_8CH			551
++#define CLK_I2S7_8CH_RX_SRC		552
++#define CLK_I2S7_8CH_RX_FRAC		553
++#define CLK_I2S7_8CH_RX			554
++#define MCLK_I2S7_8CH_RX		555
++#define HCLK_I2S9_8CH			556
++#define CLK_I2S9_8CH_RX_SRC		557
++#define CLK_I2S9_8CH_RX_FRAC		558
++#define CLK_I2S9_8CH_RX			559
++#define MCLK_I2S9_8CH_RX		560
++#define CLK_I2S5_8CH_TX_SRC		561
++#define CLK_I2S5_8CH_TX_FRAC		562
++#define CLK_I2S5_8CH_TX			563
++#define MCLK_I2S5_8CH_TX		564
++#define HCLK_I2S5_8CH			565
++#define CLK_I2S6_8CH_TX_SRC		566
++#define CLK_I2S6_8CH_TX_FRAC		567
++#define CLK_I2S6_8CH_TX			568
++#define MCLK_I2S6_8CH_TX		569
++#define CLK_I2S6_8CH_RX_SRC		570
++#define CLK_I2S6_8CH_RX_FRAC		571
++#define CLK_I2S6_8CH_RX			572
++#define MCLK_I2S6_8CH_RX		573
++#define I2S6_8CH_MCLKOUT		574
++#define HCLK_I2S6_8CH			575
++#define HCLK_SPDIF3			576
++#define CLK_SPDIF3_SRC			577
++#define CLK_SPDIF3_FRAC			578
++#define CLK_SPDIF3			579
++#define MCLK_SPDIF3			580
++#define HCLK_SPDIF4			581
++#define CLK_SPDIF4_SRC			582
++#define CLK_SPDIF4_FRAC			583
++#define CLK_SPDIF4			584
++#define MCLK_SPDIF4			585
++#define HCLK_SPDIFRX0			586
++#define MCLK_SPDIFRX0			587
++#define HCLK_SPDIFRX1			588
++#define MCLK_SPDIFRX1			589
++#define HCLK_SPDIFRX2			590
++#define MCLK_SPDIFRX2			591
++#define ACLK_VO1USB_TOP_ROOT		592
++#define HCLK_VO1USB_TOP_ROOT		593
++#define CLK_HDMIHDP0			594
++#define CLK_HDMIHDP1			595
++#define PCLK_HDPTX0			596
++#define PCLK_HDPTX1			597
++#define PCLK_USBDPPHY0			598
++#define PCLK_USBDPPHY1			599
++#define ACLK_VOP_ROOT			600
++#define ACLK_VOP_LOW_ROOT		601
++#define HCLK_VOP_ROOT			602
++#define PCLK_VOP_ROOT			603
++#define HCLK_VOP			604
++#define ACLK_VOP			605
++#define DCLK_VOP0_SRC			606
++#define DCLK_VOP1_SRC			607
++#define DCLK_VOP2_SRC			608
++#define DCLK_VOP0			609
++#define DCLK_VOP1			610
++#define DCLK_VOP2			611
++#define DCLK_VOP3			612
++#define PCLK_DSIHOST0			613
++#define PCLK_DSIHOST1			614
++#define CLK_DSIHOST0			615
++#define CLK_DSIHOST1			616
++#define CLK_VOP_PMU			617
++#define ACLK_VOP_DOBY			618
++#define ACLK_VOP_SUB_SRC		619
++#define CLK_USBDP_PHY0_IMMORTAL		620
++#define CLK_USBDP_PHY1_IMMORTAL		621
++#define CLK_PMU0			622
++#define PCLK_PMU0			623
++#define PCLK_PMU0IOC			624
++#define PCLK_GPIO0			625
++#define DBCLK_GPIO0			626
++#define PCLK_I2C0			627
++#define CLK_I2C0			628
++#define HCLK_I2S1_8CH			629
++#define CLK_I2S1_8CH_TX_SRC		630
++#define CLK_I2S1_8CH_TX_FRAC		631
++#define CLK_I2S1_8CH_TX			632
++#define MCLK_I2S1_8CH_TX		633
++#define CLK_I2S1_8CH_RX_SRC		634
++#define CLK_I2S1_8CH_RX_FRAC		635
++#define CLK_I2S1_8CH_RX			636
++#define MCLK_I2S1_8CH_RX		637
++#define I2S1_8CH_MCLKOUT		638
++#define CLK_PMU1_50M_SRC		639
++#define CLK_PMU1_100M_SRC		640
++#define CLK_PMU1_200M_SRC		641
++#define CLK_PMU1_300M_SRC		642
++#define CLK_PMU1_400M_SRC		643
++#define HCLK_PMU1_ROOT			644
++#define PCLK_PMU1_ROOT			645
++#define PCLK_PMU0_ROOT			646
++#define HCLK_PMU_CM0_ROOT		647
++#define PCLK_PMU1			648
++#define CLK_DDR_FAIL_SAFE		649
++#define CLK_PMU1			650
++#define HCLK_PDM0			651
++#define MCLK_PDM0			652
++#define HCLK_VAD			653
++#define FCLK_PMU_CM0_CORE		654
++#define CLK_PMU_CM0_RTC			655
++#define PCLK_PMU1_IOC			656
++#define PCLK_PMU1PWM			657
++#define CLK_PMU1PWM			658
++#define CLK_PMU1PWM_CAPTURE		659
++#define PCLK_PMU1TIMER			660
++#define CLK_PMU1TIMER_ROOT		661
++#define CLK_PMU1TIMER0			662
++#define CLK_PMU1TIMER1			663
++#define CLK_UART0_SRC			664
++#define CLK_UART0_FRAC			665
++#define CLK_UART0			666
++#define SCLK_UART0			667
++#define PCLK_UART0			668
++#define PCLK_PMU1WDT			669
++#define TCLK_PMU1WDT			670
++#define CLK_CR_PARA			671
++#define CLK_USB2PHY_HDPTXRXPHY_REF	672
++#define CLK_USBDPPHY_MIPIDCPPHY_REF	673
++#define CLK_REF_PIPE_PHY0_OSC_SRC	674
++#define CLK_REF_PIPE_PHY1_OSC_SRC	675
++#define CLK_REF_PIPE_PHY2_OSC_SRC	676
++#define CLK_REF_PIPE_PHY0_PLL_SRC	677
++#define CLK_REF_PIPE_PHY1_PLL_SRC	678
++#define CLK_REF_PIPE_PHY2_PLL_SRC	679
++#define CLK_REF_PIPE_PHY0		680
++#define CLK_REF_PIPE_PHY1		681
++#define CLK_REF_PIPE_PHY2		682
++#define SCLK_SDIO_DRV			683
++#define SCLK_SDIO_SAMPLE		684
++#define SCLK_SDMMC_DRV			685
++#define SCLK_SDMMC_SAMPLE		686
++#define CLK_PCIE1L0_PIPE		687
++#define CLK_PCIE1L1_PIPE		688
++#define CLK_BIGCORE0_PVTM		689
++#define CLK_CORE_BIGCORE0_PVTM		690
++#define CLK_BIGCORE1_PVTM		691
++#define CLK_CORE_BIGCORE1_PVTM		692
++#define CLK_LITCORE_PVTM		693
++#define CLK_CORE_LITCORE_PVTM		694
++#define CLK_AUX16M_0			695
++#define CLK_AUX16M_1			696
++#define CLK_PHY0_REF_ALT_P		697
++#define CLK_PHY0_REF_ALT_M		698
++#define CLK_PHY1_REF_ALT_P		699
++#define CLK_PHY1_REF_ALT_M		700
++#define ACLK_ISP1_PRE			701
++#define HCLK_ISP1_PRE			702
++#define HCLK_NVM			703
++#define ACLK_USB			704
++#define HCLK_USB			705
++#define ACLK_JPEG_DECODER_PRE		706
++#define ACLK_VDPU_LOW_PRE		707
++#define ACLK_RKVENC1_PRE		708
++#define HCLK_RKVENC1_PRE		709
++#define HCLK_RKVDEC0_PRE		710
++#define ACLK_RKVDEC0_PRE		711
++#define HCLK_RKVDEC1_PRE		712
++#define ACLK_RKVDEC1_PRE		713
++#define ACLK_HDCP0_PRE			714
++#define HCLK_VO0			715
++#define ACLK_HDCP1_PRE			716
++#define HCLK_VO1			717
++#define ACLK_AV1_PRE			718
++#define PCLK_AV1_PRE			719
++#define HCLK_SDIO_PRE			720
++
++#define CLK_NR_CLKS			(HCLK_SDIO_PRE + 1)
++
++/* scmi-clocks indices */
++
++#define SCMI_CLK_CPUL			0
++#define SCMI_CLK_DSU			1
++#define SCMI_CLK_CPUB01			2
++#define SCMI_CLK_CPUB23			3
++#define SCMI_CLK_DDR			4
++#define SCMI_CLK_GPU			5
++#define SCMI_CLK_NPU			6
++#define SCMI_CLK_SBUS			7
++#define SCMI_PCLK_SBUS			8
++#define SCMI_CCLK_SD			9
++#define SCMI_DCLK_SD			10
++#define SCMI_ACLK_SECURE_NS		11
++#define SCMI_HCLK_SECURE_NS		12
++#define SCMI_TCLK_WDT			13
++#define SCMI_KEYLADDER_CORE		14
++#define SCMI_KEYLADDER_RNG		15
++#define SCMI_ACLK_SECURE_S		16
++#define SCMI_HCLK_SECURE_S		17
++#define SCMI_PCLK_SECURE_S		18
++#define SCMI_CRYPTO_RNG			19
++#define SCMI_CRYPTO_CORE		20
++#define SCMI_CRYPTO_PKA			21
++#define SCMI_SPLL			22
++#define SCMI_HCLK_SD			23
++
++#endif
diff --git a/target/linux/rockchip/patches-6.1/337-thermal-drivers-rockchip-Fix-kernel-doc-warnings.patch b/target/linux/rockchip/patches-6.1/337-thermal-drivers-rockchip-Fix-kernel-doc-warnings.patch
new file mode 100644
index 00000000000..475b8595bbd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/337-thermal-drivers-rockchip-Fix-kernel-doc-warnings.patch
@@ -0,0 +1,60 @@
+From 318a88119531fb14c7a2cc8b263219130baf61f6 Mon Sep 17 00:00:00 2001
+From: Randy Dunlap <rdunlap@infradead.org>
+Date: Thu, 12 Jan 2023 22:45:00 -0800
+Subject: [PATCH 337/383] thermal/drivers/rockchip: Fix kernel-doc warnings
+
+Don't use "/**" to begin non-kernel-doc comments.
+Convert one function description to kernel-doc format.
+Prevents these kernel-doc warnings:
+
+drivers/thermal/rockchip_thermal.c:64: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
+ * The max sensors is two in rockchip SoCs.
+drivers/thermal/rockchip_thermal.c:179: warning: expecting prototype for TSADC Sensor Register description(). Prototype was for TSADCV2_USER_CON() instead
+drivers/thermal/rockchip_thermal.c:1342: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst
+ * Reset TSADC Controller, reset all tsadc registers.
+
+Signed-off-by: Randy Dunlap <rdunlap@infradead.org>
+Cc: "Rafael J. Wysocki" <rafael@kernel.org>
+Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
+Cc: Amit Kucheria <amitk@kernel.org>
+Cc: Zhang Rui <rui.zhang@intel.com>
+Cc: Heiko Stuebner <heiko@sntech.de>
+Cc: linux-pm@vger.kernel.org
+Cc: linux-arm-kernel@lists.infradead.org
+Cc: linux-rockchip@lists.infradead.org
+Link: https://lore.kernel.org/r/20230113064500.16103-1-rdunlap@infradead.org
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -60,7 +60,7 @@ enum adc_sort_mode {
+ 
+ #include "thermal_hwmon.h"
+ 
+-/**
++/*
+  * The max sensors is two in rockchip SoCs.
+  * Two sensors: CPU and GPU sensor.
+  */
+@@ -169,7 +169,7 @@ struct rockchip_thermal_data {
+ 	enum tshut_polarity tshut_polarity;
+ };
+ 
+-/**
++/*
+  * TSADC Sensor Register description:
+  *
+  * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
+@@ -1339,7 +1339,7 @@ rockchip_thermal_register_sensor(struct
+ }
+ 
+ /**
+- * Reset TSADC Controller, reset all tsadc registers.
++ * rockchip_thermal_reset_controller - Reset TSADC Controller, reset all tsadc registers.
+  * @reset: the reset controller of tsadc
+  */
+ static void rockchip_thermal_reset_controller(struct reset_control *reset)
diff --git a/target/linux/rockchip/patches-6.1/338-thermal-drivers-rockchip-Use-devm_platform_get_and_i.patch b/target/linux/rockchip/patches-6.1/338-thermal-drivers-rockchip-Use-devm_platform_get_and_i.patch
new file mode 100644
index 00000000000..dcf9eeced6d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/338-thermal-drivers-rockchip-Use-devm_platform_get_and_i.patch
@@ -0,0 +1,38 @@
+From d4d853398c3641c0e495f98fa9ff19a096905386 Mon Sep 17 00:00:00 2001
+From: ye xingchen <ye.xingchen@zte.com.cn>
+Date: Wed, 18 Jan 2023 16:39:30 +0800
+Subject: [PATCH 338/383] thermal/drivers/rockchip: Use
+ devm_platform_get_and_ioremap_resource()
+
+Convert platform_get_resource(), devm_ioremap_resource() to a single
+call to devm_platform_get_and_ioremap_resource(), as this is exactly
+what this function does.
+
+Signed-off-by: ye xingchen <ye.xingchen@zte.com.cn>
+Link: https://lore.kernel.org/r/202301181639300333679@zte.com.cn
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 4 +---
+ 1 file changed, 1 insertion(+), 3 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1354,7 +1354,6 @@ static int rockchip_thermal_probe(struct
+ 	struct device_node *np = pdev->dev.of_node;
+ 	struct rockchip_thermal_data *thermal;
+ 	const struct of_device_id *match;
+-	struct resource *res;
+ 	int irq;
+ 	int i;
+ 	int error;
+@@ -1378,8 +1377,7 @@ static int rockchip_thermal_probe(struct
+ 	if (!thermal->chip)
+ 		return -EINVAL;
+ 
+-	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+-	thermal->regs = devm_ioremap_resource(&pdev->dev, res);
++	thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ 	if (IS_ERR(thermal->regs))
+ 		return PTR_ERR(thermal->regs);
+ 
diff --git a/target/linux/rockchip/patches-6.1/339-thermal-Remove-debug-or-error-messages-in-get_temp-o.patch b/target/linux/rockchip/patches-6.1/339-thermal-Remove-debug-or-error-messages-in-get_temp-o.patch
new file mode 100644
index 00000000000..8790814f019
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/339-thermal-Remove-debug-or-error-messages-in-get_temp-o.patch
@@ -0,0 +1,47 @@
+From 0070138200f16a0398aff9cb2e65808d7f0a575a Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:34 +0100
+Subject: [PATCH 339/383] thermal: Remove debug or error messages in get_temp()
+ ops
+
+Some get_temp() ops implementation are showing an error or a debug
+message if the reading of the sensor fails.
+
+The debug message is already displayed from the call site of this
+ops. So we can remove it.
+
+On the other side, the error should not be displayed because in
+production that can raise tons of messages.
+
+Finally, some drivers are showing a debug message with the
+temperature, this is also accessible through the trace from the core
+code in the temperature_update() function.
+
+Another benefit is the dev_* messages are accessing the thermal zone
+device field from the structure, so we encapsulate even more the code
+by preventing these accesses.
+
+Remove those messages.
+
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> #Armada
+Acked-by: Florian Fainelli <f.fainelli@gmail.com> #brcmstb_thermal.c
+Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 3 ---
+ 1 file changed, 3 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1233,9 +1233,6 @@ static int rockchip_thermal_get_temp(str
+ 
+ 	retval = tsadc->get_temp(&tsadc->table,
+ 				 sensor->id, thermal->regs, out_temp);
+-	dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
+-		sensor->id, *out_temp, retval);
+-
+ 	return retval;
+ }
+ 
diff --git a/target/linux/rockchip/patches-6.1/340-thermal-hwmon-Do-not-set-no_hwmon-before-calling-the.patch b/target/linux/rockchip/patches-6.1/340-thermal-hwmon-Do-not-set-no_hwmon-before-calling-the.patch
new file mode 100644
index 00000000000..30a1e560ac0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/340-thermal-hwmon-Do-not-set-no_hwmon-before-calling-the.patch
@@ -0,0 +1,38 @@
+From 6f3245bb56af6ccc3d7c5b5a564bbacb8a277748 Mon Sep 17 00:00:00 2001
+From: Daniel Lezcano <daniel.lezcano@linaro.org>
+Date: Wed, 1 Mar 2023 21:14:35 +0100
+Subject: [PATCH 340/383] thermal/hwmon: Do not set no_hwmon before calling
+ thermal_add_hwmon_sysfs()
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+The thermal->tzp->no_hwmon parameter is only used when calling
+thermal_zone_device_register().
+
+Setting it to 'false' before calling thermal_add_hwmon_sysfs() has no
+effect.
+
+Remove the call and again prevent the drivers to access the thermal
+internals.
+
+Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> #R-Car
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Acked-by: Florian Fainelli <f.fainelli@gmail.com> #Broadcom
+Acked-by: Heiko Stuebner <heiko@sntech.de> #rockchip
+Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1451,7 +1451,6 @@ static int rockchip_thermal_probe(struct
+ 
+ 	for (i = 0; i < thermal->chip->chn_num; i++) {
+ 		rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
+-		thermal->sensors[i].tzd->tzp->no_hwmon = false;
+ 		error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
+ 		if (error)
+ 			dev_warn(&pdev->dev,
diff --git a/target/linux/rockchip/patches-6.1/341-thermal-drivers-rockchip-Simplify-getting-match-data.patch b/target/linux/rockchip/patches-6.1/341-thermal-drivers-rockchip-Simplify-getting-match-data.patch
new file mode 100644
index 00000000000..554f94a2646
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/341-thermal-drivers-rockchip-Simplify-getting-match-data.patch
@@ -0,0 +1,44 @@
+From a5afd6d05baeabb9f9d18c2879edf030e91f3355 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 8 Mar 2023 12:22:47 +0100
+Subject: [PATCH 341/383] thermal/drivers/rockchip: Simplify getting match data
+
+It's possible to directly get the match data in a generic
+way nowadays.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230308112253.15659-2-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 7 +------
+ 1 file changed, 1 insertion(+), 6 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1350,15 +1350,10 @@ static int rockchip_thermal_probe(struct
+ {
+ 	struct device_node *np = pdev->dev.of_node;
+ 	struct rockchip_thermal_data *thermal;
+-	const struct of_device_id *match;
+ 	int irq;
+ 	int i;
+ 	int error;
+ 
+-	match = of_match_node(of_rockchip_thermal_match, np);
+-	if (!match)
+-		return -ENXIO;
+-
+ 	irq = platform_get_irq(pdev, 0);
+ 	if (irq < 0)
+ 		return -EINVAL;
+@@ -1370,7 +1365,7 @@ static int rockchip_thermal_probe(struct
+ 
+ 	thermal->pdev = pdev;
+ 
+-	thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
++	thermal->chip = device_get_match_data(&pdev->dev);
+ 	if (!thermal->chip)
+ 		return -EINVAL;
+ 
diff --git a/target/linux/rockchip/patches-6.1/342-thermal-drivers-rockchip-Simplify-clock-logic.patch b/target/linux/rockchip/patches-6.1/342-thermal-drivers-rockchip-Simplify-clock-logic.patch
new file mode 100644
index 00000000000..b7a57b5af0f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/342-thermal-drivers-rockchip-Simplify-clock-logic.patch
@@ -0,0 +1,107 @@
+From 3444c6d3676ab753d2b7f582a265321fafb0678a Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 8 Mar 2023 12:22:48 +0100
+Subject: [PATCH 342/383] thermal/drivers/rockchip: Simplify clock logic
+
+By using devm_clk_get_enabled() the clock acquisition and
+enabling can be done in one step with automatic error
+handling.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230308112253.15659-3-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 33 +++++-------------------------
+ 1 file changed, 5 insertions(+), 28 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1380,14 +1380,14 @@ static int rockchip_thermal_probe(struct
+ 		return error;
+ 	}
+ 
+-	thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
++	thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
+ 	if (IS_ERR(thermal->clk)) {
+ 		error = PTR_ERR(thermal->clk);
+ 		dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
+ 		return error;
+ 	}
+ 
+-	thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
++	thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+ 	if (IS_ERR(thermal->pclk)) {
+ 		error = PTR_ERR(thermal->pclk);
+ 		dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
+@@ -1395,26 +1395,13 @@ static int rockchip_thermal_probe(struct
+ 		return error;
+ 	}
+ 
+-	error = clk_prepare_enable(thermal->clk);
+-	if (error) {
+-		dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
+-			error);
+-		return error;
+-	}
+-
+-	error = clk_prepare_enable(thermal->pclk);
+-	if (error) {
+-		dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
+-		goto err_disable_clk;
+-	}
+-
+ 	rockchip_thermal_reset_controller(thermal->reset);
+ 
+ 	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
+ 	if (error) {
+ 		dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
+ 			error);
+-		goto err_disable_pclk;
++		return error;
+ 	}
+ 
+ 	thermal->chip->initialize(thermal->grf, thermal->regs,
+@@ -1428,7 +1415,7 @@ static int rockchip_thermal_probe(struct
+ 			dev_err(&pdev->dev,
+ 				"failed to register sensor[%d] : error = %d\n",
+ 				i, error);
+-			goto err_disable_pclk;
++			return error;
+ 		}
+ 	}
+ 
+@@ -1439,7 +1426,7 @@ static int rockchip_thermal_probe(struct
+ 	if (error) {
+ 		dev_err(&pdev->dev,
+ 			"failed to request tsadc irq: %d\n", error);
+-		goto err_disable_pclk;
++		return error;
+ 	}
+ 
+ 	thermal->chip->control(thermal->regs, true);
+@@ -1456,13 +1443,6 @@ static int rockchip_thermal_probe(struct
+ 	platform_set_drvdata(pdev, thermal);
+ 
+ 	return 0;
+-
+-err_disable_pclk:
+-	clk_disable_unprepare(thermal->pclk);
+-err_disable_clk:
+-	clk_disable_unprepare(thermal->clk);
+-
+-	return error;
+ }
+ 
+ static int rockchip_thermal_remove(struct platform_device *pdev)
+@@ -1479,9 +1459,6 @@ static int rockchip_thermal_remove(struc
+ 
+ 	thermal->chip->control(thermal->regs, false);
+ 
+-	clk_disable_unprepare(thermal->pclk);
+-	clk_disable_unprepare(thermal->clk);
+-
+ 	return 0;
+ }
+ 
diff --git a/target/linux/rockchip/patches-6.1/343-thermal-drivers-rockchip-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/343-thermal-drivers-rockchip-Use-dev_err_probe.patch
new file mode 100644
index 00000000000..aa92d85680e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/343-thermal-drivers-rockchip-Use-dev_err_probe.patch
@@ -0,0 +1,97 @@
+From 1c35f48d619b204cd6b4c349495c977337940050 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 8 Mar 2023 12:22:49 +0100
+Subject: [PATCH 343/383] thermal/drivers/rockchip: Use dev_err_probe
+
+Use dev_err_probe to simplify error printing in the driver's probe
+routine.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230308112253.15659-4-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 50 +++++++++++-------------------
+ 1 file changed, 18 insertions(+), 32 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1374,35 +1374,26 @@ static int rockchip_thermal_probe(struct
+ 		return PTR_ERR(thermal->regs);
+ 
+ 	thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
+-	if (IS_ERR(thermal->reset)) {
+-		error = PTR_ERR(thermal->reset);
+-		dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
+-		return error;
+-	}
++	if (IS_ERR(thermal->reset))
++		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
++				     "failed to get tsadc reset.\n");
+ 
+ 	thermal->clk = devm_clk_get_enabled(&pdev->dev, "tsadc");
+-	if (IS_ERR(thermal->clk)) {
+-		error = PTR_ERR(thermal->clk);
+-		dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
+-		return error;
+-	}
++	if (IS_ERR(thermal->clk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->clk),
++				     "failed to get tsadc clock.\n");
+ 
+ 	thermal->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
+-	if (IS_ERR(thermal->pclk)) {
+-		error = PTR_ERR(thermal->pclk);
+-		dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
+-			error);
+-		return error;
+-	}
++	if (IS_ERR(thermal->pclk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->pclk),
++				     "failed to get apb_pclk clock.\n");
+ 
+ 	rockchip_thermal_reset_controller(thermal->reset);
+ 
+ 	error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
+-	if (error) {
+-		dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
+-			error);
+-		return error;
+-	}
++	if (error)
++		return dev_err_probe(&pdev->dev, error,
++				"failed to parse device tree data\n");
+ 
+ 	thermal->chip->initialize(thermal->grf, thermal->regs,
+ 				  thermal->tshut_polarity);
+@@ -1411,23 +1402,18 @@ static int rockchip_thermal_probe(struct
+ 		error = rockchip_thermal_register_sensor(pdev, thermal,
+ 						&thermal->sensors[i],
+ 						thermal->chip->chn_id[i]);
+-		if (error) {
+-			dev_err(&pdev->dev,
+-				"failed to register sensor[%d] : error = %d\n",
+-				i, error);
+-			return error;
+-		}
++		if (error)
++			return dev_err_probe(&pdev->dev, error,
++				"failed to register sensor[%d].\n", i);
+ 	}
+ 
+ 	error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
+ 					  &rockchip_thermal_alarm_irq_thread,
+ 					  IRQF_ONESHOT,
+ 					  "rockchip_thermal", thermal);
+-	if (error) {
+-		dev_err(&pdev->dev,
+-			"failed to request tsadc irq: %d\n", error);
+-		return error;
+-	}
++	if (error)
++		return dev_err_probe(&pdev->dev, error,
++				     "failed to request tsadc irq.\n");
+ 
+ 	thermal->chip->control(thermal->regs, true);
+ 
diff --git a/target/linux/rockchip/patches-6.1/344-thermal-drivers-rockchip-Simplify-channel-id-logic.patch b/target/linux/rockchip/patches-6.1/344-thermal-drivers-rockchip-Simplify-channel-id-logic.patch
new file mode 100644
index 00000000000..5becc7e79e1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/344-thermal-drivers-rockchip-Simplify-channel-id-logic.patch
@@ -0,0 +1,158 @@
+From b8e26c8425b5344afa931658def050d42be30897 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 8 Mar 2023 12:22:50 +0100
+Subject: [PATCH 344/383] thermal/drivers/rockchip: Simplify channel id logic
+
+Replace the channel ID lookup table by a simple offset, since
+the channel IDs are consecutive.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Link: https://lore.kernel.org/r/20230308112253.15659-5-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 48 +++++++++++++-----------------
+ 1 file changed, 21 insertions(+), 27 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -40,15 +40,6 @@ enum tshut_polarity {
+ };
+ 
+ /*
+- * The system has two Temperature Sensors.
+- * sensor0 is for CPU, and sensor1 is for GPU.
+- */
+-enum sensor_id {
+-	SENSOR_CPU = 0,
+-	SENSOR_GPU,
+-};
+-
+-/*
+  * The conversion table has the adc value and temperature.
+  * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
+  * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
+@@ -82,7 +73,7 @@ struct chip_tsadc_table {
+ 
+ /**
+  * struct rockchip_tsadc_chip - hold the private data of tsadc chip
+- * @chn_id: array of sensor ids of chip corresponding to the channel
++ * @chn_offset: the channel offset of the first channel
+  * @chn_num: the channel number of tsadc chip
+  * @tshut_temp: the hardware-controlled shutdown temperature value
+  * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
+@@ -98,7 +89,7 @@ struct chip_tsadc_table {
+  */
+ struct rockchip_tsadc_chip {
+ 	/* The sensor id of chip correspond to the ADC channel */
+-	int chn_id[SOC_MAX_SENSORS];
++	int chn_offset;
+ 	int chn_num;
+ 
+ 	/* The hardware-controlled tshut property */
+@@ -925,8 +916,8 @@ static void rk_tsadcv2_tshut_mode(int ch
+ }
+ 
+ static const struct rockchip_tsadc_chip px30_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
++	/* cpu, gpu */
++	.chn_offset = 0,
+ 	.chn_num = 2, /* 2 channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
+@@ -949,7 +940,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
++	/* cpu */
++	.chn_offset = 0,
+ 	.chn_num = 1, /* one channel for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -973,7 +965,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
++	/* cpu */
++	.chn_offset = 0,
+ 	.chn_num = 1, /* one channel for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -997,8 +990,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
+-	.chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
++	/* cpu, gpu */
++	.chn_offset = 1,
+ 	.chn_num = 2, /* two channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -1022,7 +1015,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
++	/* cpu */
++	.chn_offset = 0,
+ 	.chn_num = 1, /* one channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
+@@ -1045,8 +1039,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
++	/* cpu, gpu */
++	.chn_offset = 0,
+ 	.chn_num = 2, /* two channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -1070,8 +1064,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
++	/* cpu, gpu */
++	.chn_offset = 0,
+ 	.chn_num = 2, /* two channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -1095,8 +1089,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
++	/* cpu, gpu */
++	.chn_offset = 0,
+ 	.chn_num = 2, /* two channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -1120,8 +1114,8 @@ static const struct rockchip_tsadc_chip
+ };
+ 
+ static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
+-	.chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
+-	.chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
++	/* cpu, gpu */
++	.chn_offset = 0,
+ 	.chn_num = 2, /* two channels for tsadc */
+ 
+ 	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
+@@ -1401,7 +1395,7 @@ static int rockchip_thermal_probe(struct
+ 	for (i = 0; i < thermal->chip->chn_num; i++) {
+ 		error = rockchip_thermal_register_sensor(pdev, thermal,
+ 						&thermal->sensors[i],
+-						thermal->chip->chn_id[i]);
++						thermal->chip->chn_offset + i);
+ 		if (error)
+ 			return dev_err_probe(&pdev->dev, error,
+ 				"failed to register sensor[%d].\n", i);
diff --git a/target/linux/rockchip/patches-6.1/345-thermal-drivers-rockchip-Support-dynamic-sized-senso.patch b/target/linux/rockchip/patches-6.1/345-thermal-drivers-rockchip-Support-dynamic-sized-senso.patch
new file mode 100644
index 00000000000..c898bd8e37b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/345-thermal-drivers-rockchip-Support-dynamic-sized-senso.patch
@@ -0,0 +1,55 @@
+From 775d501bbd08d1a62d351f89bfa2ab0fd23b0bba Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Wed, 8 Mar 2023 12:22:51 +0100
+Subject: [PATCH 345/383] thermal/drivers/rockchip: Support dynamic sized
+ sensor array
+
+Dynamically allocate the sensors array based on the amount
+of platform sensors in preparation for rk3588 support, which
+needs 7 sensors.
+
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230308112253.15659-6-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 13 ++++++-------
+ 1 file changed, 6 insertions(+), 7 deletions(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -51,12 +51,6 @@ enum adc_sort_mode {
+ 
+ #include "thermal_hwmon.h"
+ 
+-/*
+- * The max sensors is two in rockchip SoCs.
+- * Two sensors: CPU and GPU sensor.
+- */
+-#define SOC_MAX_SENSORS	2
+-
+ /**
+  * struct chip_tsadc_table - hold information about chip-specific differences
+  * @id: conversion table
+@@ -147,7 +141,7 @@ struct rockchip_thermal_data {
+ 	struct platform_device *pdev;
+ 	struct reset_control *reset;
+ 
+-	struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
++	struct rockchip_thermal_sensor *sensors;
+ 
+ 	struct clk *clk;
+ 	struct clk *pclk;
+@@ -1363,6 +1357,11 @@ static int rockchip_thermal_probe(struct
+ 	if (!thermal->chip)
+ 		return -EINVAL;
+ 
++	thermal->sensors = devm_kcalloc(&pdev->dev, thermal->chip->chn_num,
++					sizeof(*thermal->sensors), GFP_KERNEL);
++	if (!thermal->sensors)
++		return -ENOMEM;
++
+ 	thermal->regs = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
+ 	if (IS_ERR(thermal->regs))
+ 		return PTR_ERR(thermal->regs);
diff --git a/target/linux/rockchip/patches-6.1/346-thermal-drivers-rockchip-Support-RK3588-SoC-in-the-t.patch b/target/linux/rockchip/patches-6.1/346-thermal-drivers-rockchip-Support-RK3588-SoC-in-the-t.patch
new file mode 100644
index 00000000000..717de4e126f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/346-thermal-drivers-rockchip-Support-RK3588-SoC-in-the-t.patch
@@ -0,0 +1,320 @@
+From fab29b4b14efc1ff3f6cb006f600e40ab2a988e0 Mon Sep 17 00:00:00 2001
+From: Finley Xiao <finley.xiao@rock-chips.com>
+Date: Wed, 8 Mar 2023 12:22:52 +0100
+Subject: [PATCH 346/383] thermal/drivers/rockchip: Support RK3588 SoC in the
+ thermal driver
+
+The RK3588 SoC has seven temperature sensor ADC channels:
+
+- Chip Center
+- CPU Cluster 1 (Dual A76 "Big" Cores)
+- CPU Cluster 2 (Dual A76 "Big" Cores)
+- CPU Cluster 0 (Quad A55 "Little" Cores)
+- Power Domain Center
+- Graphics Processing Unit
+- Neural Processing Unit
+
+Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
+[rebase, squash fixes]
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/20230308112253.15659-7-sebastian.reichel@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 177 +++++++++++++++++++++++++++++
+ 1 file changed, 177 insertions(+)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -165,29 +165,49 @@ struct rockchip_thermal_data {
+ #define TSADCV2_AUTO_CON			0x04
+ #define TSADCV2_INT_EN				0x08
+ #define TSADCV2_INT_PD				0x0c
++#define TSADCV3_AUTO_SRC_CON			0x0c
++#define TSADCV3_HT_INT_EN			0x14
++#define TSADCV3_HSHUT_GPIO_INT_EN		0x18
++#define TSADCV3_HSHUT_CRU_INT_EN		0x1c
++#define TSADCV3_INT_PD				0x24
++#define TSADCV3_HSHUT_PD			0x28
+ #define TSADCV2_DATA(chn)			(0x20 + (chn) * 0x04)
+ #define TSADCV2_COMP_INT(chn)		        (0x30 + (chn) * 0x04)
+ #define TSADCV2_COMP_SHUT(chn)		        (0x40 + (chn) * 0x04)
++#define TSADCV3_DATA(chn)			(0x2c + (chn) * 0x04)
++#define TSADCV3_COMP_INT(chn)		        (0x6c + (chn) * 0x04)
++#define TSADCV3_COMP_SHUT(chn)		        (0x10c + (chn) * 0x04)
+ #define TSADCV2_HIGHT_INT_DEBOUNCE		0x60
+ #define TSADCV2_HIGHT_TSHUT_DEBOUNCE		0x64
++#define TSADCV3_HIGHT_INT_DEBOUNCE		0x14c
++#define TSADCV3_HIGHT_TSHUT_DEBOUNCE		0x150
+ #define TSADCV2_AUTO_PERIOD			0x68
+ #define TSADCV2_AUTO_PERIOD_HT			0x6c
++#define TSADCV3_AUTO_PERIOD			0x154
++#define TSADCV3_AUTO_PERIOD_HT			0x158
+ 
+ #define TSADCV2_AUTO_EN				BIT(0)
++#define TSADCV2_AUTO_EN_MASK			BIT(16)
+ #define TSADCV2_AUTO_SRC_EN(chn)		BIT(4 + (chn))
++#define TSADCV3_AUTO_SRC_EN(chn)		BIT(chn)
++#define TSADCV3_AUTO_SRC_EN_MASK(chn)		BIT(16 + chn)
+ #define TSADCV2_AUTO_TSHUT_POLARITY_HIGH	BIT(8)
++#define TSADCV2_AUTO_TSHUT_POLARITY_MASK	BIT(24)
+ 
+ #define TSADCV3_AUTO_Q_SEL_EN			BIT(1)
+ 
+ #define TSADCV2_INT_SRC_EN(chn)			BIT(chn)
++#define TSADCV2_INT_SRC_EN_MASK(chn)		BIT(16 + (chn))
+ #define TSADCV2_SHUT_2GPIO_SRC_EN(chn)		BIT(4 + (chn))
+ #define TSADCV2_SHUT_2CRU_SRC_EN(chn)		BIT(8 + (chn))
+ 
+ #define TSADCV2_INT_PD_CLEAR_MASK		~BIT(8)
+ #define TSADCV3_INT_PD_CLEAR_MASK		~BIT(16)
++#define TSADCV4_INT_PD_CLEAR_MASK		0xffffffff
+ 
+ #define TSADCV2_DATA_MASK			0xfff
+ #define TSADCV3_DATA_MASK			0x3ff
++#define TSADCV4_DATA_MASK			0x1ff
+ 
+ #define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT	4
+ #define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT	4
+@@ -198,6 +218,8 @@ struct rockchip_thermal_data {
+ 
+ #define TSADCV5_AUTO_PERIOD_TIME		1622 /* 2.5ms */
+ #define TSADCV5_AUTO_PERIOD_HT_TIME		1622 /* 2.5ms */
++#define TSADCV6_AUTO_PERIOD_TIME		5000 /* 2.5ms */
++#define TSADCV6_AUTO_PERIOD_HT_TIME		5000 /* 2.5ms */
+ 
+ #define TSADCV2_USER_INTER_PD_SOC		0x340 /* 13 clocks */
+ #define TSADCV5_USER_INTER_PD_SOC		0xfc0 /* 97us, at least 90us */
+@@ -214,6 +236,12 @@ struct rockchip_thermal_data {
+ #define RK3568_GRF_TSADC_ANA_REG2		(0x10001 << 2)
+ #define RK3568_GRF_TSADC_TSEN			(0x10001 << 8)
+ 
++#define RK3588_GRF0_TSADC_CON			0x0100
++
++#define RK3588_GRF0_TSADC_TRM			(0xff0077 << 0)
++#define RK3588_GRF0_TSADC_SHUT_2CRU		(0x30003 << 10)
++#define RK3588_GRF0_TSADC_SHUT_2GPIO		(0x70007 << 12)
++
+ #define GRF_SARADC_TESTBIT_ON			(0x10001 << 2)
+ #define GRF_TSADC_TESTBIT_H_ON			(0x10001 << 2)
+ #define GRF_TSADC_VCM_EN_L			(0x10001 << 7)
+@@ -508,6 +536,15 @@ static const struct tsadc_table rk3568_c
+ 	{TSADCV2_DATA_MASK, 125000},
+ };
+ 
++static const struct tsadc_table rk3588_code_table[] = {
++	{0, -40000},
++	{215, -40000},
++	{285, 25000},
++	{350, 85000},
++	{395, 125000},
++	{TSADCV4_DATA_MASK, 125000},
++};
++
+ static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
+ 				   int temp)
+ {
+@@ -778,6 +815,25 @@ static void rk_tsadcv7_initialize(struct
+ 	}
+ }
+ 
++static void rk_tsadcv8_initialize(struct regmap *grf, void __iomem *regs,
++				  enum tshut_polarity tshut_polarity)
++{
++	writel_relaxed(TSADCV6_AUTO_PERIOD_TIME, regs + TSADCV3_AUTO_PERIOD);
++	writel_relaxed(TSADCV6_AUTO_PERIOD_HT_TIME,
++		       regs + TSADCV3_AUTO_PERIOD_HT);
++	writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
++		       regs + TSADCV3_HIGHT_INT_DEBOUNCE);
++	writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
++		       regs + TSADCV3_HIGHT_TSHUT_DEBOUNCE);
++	if (tshut_polarity == TSHUT_HIGH_ACTIVE)
++		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_HIGH |
++			       TSADCV2_AUTO_TSHUT_POLARITY_MASK,
++			       regs + TSADCV2_AUTO_CON);
++	else
++		writel_relaxed(TSADCV2_AUTO_TSHUT_POLARITY_MASK,
++			       regs + TSADCV2_AUTO_CON);
++}
++
+ static void rk_tsadcv2_irq_ack(void __iomem *regs)
+ {
+ 	u32 val;
+@@ -794,6 +850,17 @@ static void rk_tsadcv3_irq_ack(void __io
+ 	writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
+ }
+ 
++static void rk_tsadcv4_irq_ack(void __iomem *regs)
++{
++	u32 val;
++
++	val = readl_relaxed(regs + TSADCV3_INT_PD);
++	writel_relaxed(val & TSADCV4_INT_PD_CLEAR_MASK, regs + TSADCV3_INT_PD);
++	val = readl_relaxed(regs + TSADCV3_HSHUT_PD);
++	writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK,
++		       regs + TSADCV3_HSHUT_PD);
++}
++
+ static void rk_tsadcv2_control(void __iomem *regs, bool enable)
+ {
+ 	u32 val;
+@@ -829,6 +896,18 @@ static void rk_tsadcv3_control(void __io
+ 	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
+ }
+ 
++static void rk_tsadcv4_control(void __iomem *regs, bool enable)
++{
++	u32 val;
++
++	if (enable)
++		val = TSADCV2_AUTO_EN | TSADCV2_AUTO_EN_MASK;
++	else
++		val = TSADCV2_AUTO_EN_MASK;
++
++	writel_relaxed(val, regs + TSADCV2_AUTO_CON);
++}
++
+ static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
+ 			       int chn, void __iomem *regs, int *temp)
+ {
+@@ -839,6 +918,16 @@ static int rk_tsadcv2_get_temp(const str
+ 	return rk_tsadcv2_code_to_temp(table, val, temp);
+ }
+ 
++static int rk_tsadcv4_get_temp(const struct chip_tsadc_table *table,
++			       int chn, void __iomem *regs, int *temp)
++{
++	u32 val;
++
++	val = readl_relaxed(regs + TSADCV3_DATA(chn));
++
++	return rk_tsadcv2_code_to_temp(table, val, temp);
++}
++
+ static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
+ 				 int chn, void __iomem *regs, int temp)
+ {
+@@ -873,6 +962,33 @@ static int rk_tsadcv2_alarm_temp(const s
+ 	return 0;
+ }
+ 
++static int rk_tsadcv3_alarm_temp(const struct chip_tsadc_table *table,
++				 int chn, void __iomem *regs, int temp)
++{
++	u32 alarm_value;
++
++	/*
++	 * In some cases, some sensors didn't need the trip points, the
++	 * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
++	 * in the end, ignore this case and disable the high temperature
++	 * interrupt.
++	 */
++	if (temp == INT_MAX) {
++		writel_relaxed(TSADCV2_INT_SRC_EN_MASK(chn),
++			       regs + TSADCV3_HT_INT_EN);
++		return 0;
++	}
++	/* Make sure the value is valid */
++	alarm_value = rk_tsadcv2_temp_to_code(table, temp);
++	if (alarm_value == table->data_mask)
++		return -ERANGE;
++	writel_relaxed(alarm_value & table->data_mask,
++		       regs + TSADCV3_COMP_INT(chn));
++	writel_relaxed(TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn),
++		       regs + TSADCV3_HT_INT_EN);
++	return 0;
++}
++
+ static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
+ 				 int chn, void __iomem *regs, int temp)
+ {
+@@ -892,6 +1008,25 @@ static int rk_tsadcv2_tshut_temp(const s
+ 	return 0;
+ }
+ 
++static int rk_tsadcv3_tshut_temp(const struct chip_tsadc_table *table,
++				 int chn, void __iomem *regs, int temp)
++{
++	u32 tshut_value;
++
++	/* Make sure the value is valid */
++	tshut_value = rk_tsadcv2_temp_to_code(table, temp);
++	if (tshut_value == table->data_mask)
++		return -ERANGE;
++
++	writel_relaxed(tshut_value, regs + TSADCV3_COMP_SHUT(chn));
++
++	/* TSHUT will be valid */
++	writel_relaxed(TSADCV3_AUTO_SRC_EN(chn) | TSADCV3_AUTO_SRC_EN_MASK(chn),
++		       regs + TSADCV3_AUTO_SRC_CON);
++
++	return 0;
++}
++
+ static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
+ 				  enum tshut_mode mode)
+ {
+@@ -909,6 +1044,22 @@ static void rk_tsadcv2_tshut_mode(int ch
+ 	writel_relaxed(val, regs + TSADCV2_INT_EN);
+ }
+ 
++static void rk_tsadcv3_tshut_mode(int chn, void __iomem *regs,
++				  enum tshut_mode mode)
++{
++	u32 val_gpio, val_cru;
++
++	if (mode == TSHUT_MODE_GPIO) {
++		val_gpio = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
++		val_cru = TSADCV2_INT_SRC_EN_MASK(chn);
++	} else {
++		val_cru = TSADCV2_INT_SRC_EN(chn) | TSADCV2_INT_SRC_EN_MASK(chn);
++		val_gpio = TSADCV2_INT_SRC_EN_MASK(chn);
++	}
++	writel_relaxed(val_gpio, regs + TSADCV3_HSHUT_GPIO_INT_EN);
++	writel_relaxed(val_cru, regs + TSADCV3_HSHUT_CRU_INT_EN);
++}
++
+ static const struct rockchip_tsadc_chip px30_tsadc_data = {
+ 	/* cpu, gpu */
+ 	.chn_offset = 0,
+@@ -1132,6 +1283,28 @@ static const struct rockchip_tsadc_chip
+ 	},
+ };
+ 
++static const struct rockchip_tsadc_chip rk3588_tsadc_data = {
++	/* top, big_core0, big_core1, little_core, center, gpu, npu */
++	.chn_offset = 0,
++	.chn_num = 7, /* seven channels for tsadc */
++	.tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
++	.tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
++	.tshut_temp = 95000,
++	.initialize = rk_tsadcv8_initialize,
++	.irq_ack = rk_tsadcv4_irq_ack,
++	.control = rk_tsadcv4_control,
++	.get_temp = rk_tsadcv4_get_temp,
++	.set_alarm_temp = rk_tsadcv3_alarm_temp,
++	.set_tshut_temp = rk_tsadcv3_tshut_temp,
++	.set_tshut_mode = rk_tsadcv3_tshut_mode,
++	.table = {
++		.id = rk3588_code_table,
++		.length = ARRAY_SIZE(rk3588_code_table),
++		.data_mask = TSADCV4_DATA_MASK,
++		.mode = ADC_INCREMENT,
++	},
++};
++
+ static const struct of_device_id of_rockchip_thermal_match[] = {
+ 	{	.compatible = "rockchip,px30-tsadc",
+ 		.data = (void *)&px30_tsadc_data,
+@@ -1168,6 +1341,10 @@ static const struct of_device_id of_rock
+ 		.compatible = "rockchip,rk3568-tsadc",
+ 		.data = (void *)&rk3568_tsadc_data,
+ 	},
++	{
++		.compatible = "rockchip,rk3588-tsadc",
++		.data = (void *)&rk3588_tsadc_data,
++	},
+ 	{ /* end */ },
+ };
+ MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
diff --git a/target/linux/rockchip/patches-6.1/347-thermal-drivers-rockchip-use-devm_reset_control_arra.patch b/target/linux/rockchip/patches-6.1/347-thermal-drivers-rockchip-use-devm_reset_control_arra.patch
new file mode 100644
index 00000000000..f6a25908af3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/347-thermal-drivers-rockchip-use-devm_reset_control_arra.patch
@@ -0,0 +1,29 @@
+From 4258ee4cf05c992b7e1abbaf294a2a9a90e1a6e5 Mon Sep 17 00:00:00 2001
+From: Ye Xingchen <ye.xingchen@zte.com.cn>
+Date: Fri, 24 Mar 2023 11:08:55 +0800
+Subject: [PATCH 347/383] thermal/drivers/rockchip: use
+ devm_reset_control_array_get_exclusive()
+
+Switch devm_reset_control_array_get() to
+devm_reset_control_array_get_exclusive().
+
+Signed-off-by: Ye Xingchen <ye.xingchen@zte.com.cn>
+Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
+Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
+Link: https://lore.kernel.org/r/202303241108553006227@zte.com.cn
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/thermal/rockchip_thermal.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/thermal/rockchip_thermal.c
++++ b/drivers/thermal/rockchip_thermal.c
+@@ -1543,7 +1543,7 @@ static int rockchip_thermal_probe(struct
+ 	if (IS_ERR(thermal->regs))
+ 		return PTR_ERR(thermal->regs);
+ 
+-	thermal->reset = devm_reset_control_array_get(&pdev->dev, false, false);
++	thermal->reset = devm_reset_control_array_get_exclusive(&pdev->dev);
+ 	if (IS_ERR(thermal->reset))
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(thermal->reset),
+ 				     "failed to get tsadc reset.\n");
diff --git a/target/linux/rockchip/patches-6.1/348-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/348-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch
new file mode 100644
index 00000000000..758e4dd2296
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/348-iio-adc-rockchip_saradc-Add-support-for-RK3588.patch
@@ -0,0 +1,214 @@
+From 47148e1c3e8db2a8da6869a61f45ff7bc70b8186 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 17 May 2023 04:30:45 +0530
+Subject: [PATCH 348/383] iio: adc: rockchip_saradc: Add support for RK3588
+
+Refactor conversion operation to support rk3588 saradc and
+add separate start, read, powerdown in respective hooks.
+
+Signed-off-by: Simon Xue <xxm@rock-chips.com>
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iio/adc/rockchip_saradc.c | 127 +++++++++++++++++++++++++++---
+ 1 file changed, 115 insertions(+), 12 deletions(-)
+
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -37,10 +37,29 @@
+ #define SARADC_TIMEOUT			msecs_to_jiffies(100)
+ #define SARADC_MAX_CHANNELS		8
+ 
++/* v2 registers */
++#define SARADC2_CONV_CON		0x0
++#define SARADC_T_PD_SOC			0x4
++#define SARADC_T_DAS_SOC		0xc
++#define SARADC2_END_INT_EN		0x104
++#define SARADC2_ST_CON			0x108
++#define SARADC2_STATUS			0x10c
++#define SARADC2_END_INT_ST		0x110
++#define SARADC2_DATA_BASE		0x120
++
++#define SARADC2_EN_END_INT		BIT(0)
++#define SARADC2_START			BIT(4)
++#define SARADC2_SINGLE_MODE		BIT(5)
++
++struct rockchip_saradc;
++
+ struct rockchip_saradc_data {
+ 	const struct iio_chan_spec	*channels;
+ 	int				num_channels;
+ 	unsigned long			clk_rate;
++	void (*start)(struct rockchip_saradc *info, int chn);
++	int (*read)(struct rockchip_saradc *info);
++	void (*power_down)(struct rockchip_saradc *info);
+ };
+ 
+ struct rockchip_saradc {
+@@ -57,27 +76,77 @@ struct rockchip_saradc {
+ 	struct notifier_block nb;
+ };
+ 
+-static void rockchip_saradc_power_down(struct rockchip_saradc *info)
++static void rockchip_saradc_reset_controller(struct reset_control *reset);
++
++static void rockchip_saradc_start_v1(struct rockchip_saradc *info, int chn)
++{
++	/* 8 clock periods as delay between power up and start cmd */
++	writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
++	/* Select the channel to be used and trigger conversion */
++	writel(SARADC_CTRL_POWER_CTRL | (chn & SARADC_CTRL_CHN_MASK) |
++	       SARADC_CTRL_IRQ_ENABLE, info->regs + SARADC_CTRL);
++}
++
++static void rockchip_saradc_start_v2(struct rockchip_saradc *info, int chn)
++{
++	int val;
++
++	if (info->reset)
++		rockchip_saradc_reset_controller(info->reset);
++
++	writel_relaxed(0xc, info->regs + SARADC_T_DAS_SOC);
++	writel_relaxed(0x20, info->regs + SARADC_T_PD_SOC);
++	val = SARADC2_EN_END_INT << 16 | SARADC2_EN_END_INT;
++	writel_relaxed(val, info->regs + SARADC2_END_INT_EN);
++	val = SARADC2_START | SARADC2_SINGLE_MODE | chn;
++	writel(val << 16 | val, info->regs + SARADC2_CONV_CON);
++}
++
++static void rockchip_saradc_start(struct rockchip_saradc *info, int chn)
++{
++	info->data->start(info, chn);
++}
++
++static int rockchip_saradc_read_v1(struct rockchip_saradc *info)
++{
++	return readl_relaxed(info->regs + SARADC_DATA);
++}
++
++static int rockchip_saradc_read_v2(struct rockchip_saradc *info)
++{
++	int offset;
++
++	/* Clear irq */
++	writel_relaxed(0x1, info->regs + SARADC2_END_INT_ST);
++
++	offset = SARADC2_DATA_BASE + info->last_chan->channel * 0x4;
++
++	return readl_relaxed(info->regs + offset);
++}
++
++static int rockchip_saradc_read(struct rockchip_saradc *info)
++{
++	return info->data->read(info);
++}
++
++static void rockchip_saradc_power_down_v1(struct rockchip_saradc *info)
+ {
+-	/* Clear irq & power down adc */
+ 	writel_relaxed(0, info->regs + SARADC_CTRL);
+ }
+ 
++static void rockchip_saradc_power_down(struct rockchip_saradc *info)
++{
++	if (info->data->power_down)
++		info->data->power_down(info);
++}
++
+ static int rockchip_saradc_conversion(struct rockchip_saradc *info,
+ 				   struct iio_chan_spec const *chan)
+ {
+ 	reinit_completion(&info->completion);
+ 
+-	/* 8 clock periods as delay between power up and start cmd */
+-	writel_relaxed(8, info->regs + SARADC_DLY_PU_SOC);
+-
+ 	info->last_chan = chan;
+-
+-	/* Select the channel to be used and trigger conversion */
+-	writel(SARADC_CTRL_POWER_CTRL
+-			| (chan->channel & SARADC_CTRL_CHN_MASK)
+-			| SARADC_CTRL_IRQ_ENABLE,
+-		   info->regs + SARADC_CTRL);
++	rockchip_saradc_start(info, chan->channel);
+ 
+ 	if (!wait_for_completion_timeout(&info->completion, SARADC_TIMEOUT))
+ 		return -ETIMEDOUT;
+@@ -120,7 +189,7 @@ static irqreturn_t rockchip_saradc_isr(i
+ 	struct rockchip_saradc *info = dev_id;
+ 
+ 	/* Read value */
+-	info->last_val = readl_relaxed(info->regs + SARADC_DATA);
++	info->last_val = rockchip_saradc_read(info);
+ 	info->last_val &= GENMASK(info->last_chan->scan_type.realbits - 1, 0);
+ 
+ 	rockchip_saradc_power_down(info);
+@@ -160,6 +229,9 @@ static const struct rockchip_saradc_data
+ 	.channels = rockchip_saradc_iio_channels,
+ 	.num_channels = ARRAY_SIZE(rockchip_saradc_iio_channels),
+ 	.clk_rate = 1000000,
++	.start = rockchip_saradc_start_v1,
++	.read = rockchip_saradc_read_v1,
++	.power_down = rockchip_saradc_power_down_v1,
+ };
+ 
+ static const struct iio_chan_spec rockchip_rk3066_tsadc_iio_channels[] = {
+@@ -171,6 +243,9 @@ static const struct rockchip_saradc_data
+ 	.channels = rockchip_rk3066_tsadc_iio_channels,
+ 	.num_channels = ARRAY_SIZE(rockchip_rk3066_tsadc_iio_channels),
+ 	.clk_rate = 50000,
++	.start = rockchip_saradc_start_v1,
++	.read = rockchip_saradc_read_v1,
++	.power_down = rockchip_saradc_power_down_v1,
+ };
+ 
+ static const struct iio_chan_spec rockchip_rk3399_saradc_iio_channels[] = {
+@@ -186,6 +261,9 @@ static const struct rockchip_saradc_data
+ 	.channels = rockchip_rk3399_saradc_iio_channels,
+ 	.num_channels = ARRAY_SIZE(rockchip_rk3399_saradc_iio_channels),
+ 	.clk_rate = 1000000,
++	.start = rockchip_saradc_start_v1,
++	.read = rockchip_saradc_read_v1,
++	.power_down = rockchip_saradc_power_down_v1,
+ };
+ 
+ static const struct iio_chan_spec rockchip_rk3568_saradc_iio_channels[] = {
+@@ -203,6 +281,28 @@ static const struct rockchip_saradc_data
+ 	.channels = rockchip_rk3568_saradc_iio_channels,
+ 	.num_channels = ARRAY_SIZE(rockchip_rk3568_saradc_iio_channels),
+ 	.clk_rate = 1000000,
++	.start = rockchip_saradc_start_v1,
++	.read = rockchip_saradc_read_v1,
++	.power_down = rockchip_saradc_power_down_v1,
++};
++
++static const struct iio_chan_spec rockchip_rk3588_saradc_iio_channels[] = {
++	SARADC_CHANNEL(0, "adc0", 12),
++	SARADC_CHANNEL(1, "adc1", 12),
++	SARADC_CHANNEL(2, "adc2", 12),
++	SARADC_CHANNEL(3, "adc3", 12),
++	SARADC_CHANNEL(4, "adc4", 12),
++	SARADC_CHANNEL(5, "adc5", 12),
++	SARADC_CHANNEL(6, "adc6", 12),
++	SARADC_CHANNEL(7, "adc7", 12),
++};
++
++static const struct rockchip_saradc_data rk3588_saradc_data = {
++	.channels = rockchip_rk3588_saradc_iio_channels,
++	.num_channels = ARRAY_SIZE(rockchip_rk3588_saradc_iio_channels),
++	.clk_rate = 1000000,
++	.start = rockchip_saradc_start_v2,
++	.read = rockchip_saradc_read_v2,
+ };
+ 
+ static const struct of_device_id rockchip_saradc_match[] = {
+@@ -218,6 +318,9 @@ static const struct of_device_id rockchi
+ 	}, {
+ 		.compatible = "rockchip,rk3568-saradc",
+ 		.data = &rk3568_saradc_data,
++	}, {
++		.compatible = "rockchip,rk3588-saradc",
++		.data = &rk3588_saradc_data,
+ 	},
+ 	{},
+ };
diff --git a/target/linux/rockchip/patches-6.1/349-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_ena.patch b/target/linux/rockchip/patches-6.1/349-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_ena.patch
new file mode 100644
index 00000000000..6350440bb7f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/349-iio-adc-rockchip_saradc-Make-use-of-devm_clk_get_ena.patch
@@ -0,0 +1,137 @@
+From 76a183447cef744072efc3948720934566eec9be Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 17 May 2023 04:30:46 +0530
+Subject: [PATCH 349/383] iio: adc: rockchip_saradc: Make use of
+ devm_clk_get_enabled
+
+Use devm_clk_get_enabled() to avoid manually disabling the
+clock.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iio/adc/rockchip_saradc.c | 77 +++++--------------------------
+ 1 file changed, 11 insertions(+), 66 deletions(-)
+
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -336,20 +336,6 @@ static void rockchip_saradc_reset_contro
+ 	reset_control_deassert(reset);
+ }
+ 
+-static void rockchip_saradc_clk_disable(void *data)
+-{
+-	struct rockchip_saradc *info = data;
+-
+-	clk_disable_unprepare(info->clk);
+-}
+-
+-static void rockchip_saradc_pclk_disable(void *data)
+-{
+-	struct rockchip_saradc *info = data;
+-
+-	clk_disable_unprepare(info->pclk);
+-}
+-
+ static void rockchip_saradc_regulator_disable(void *data)
+ {
+ 	struct rockchip_saradc *info = data;
+@@ -483,16 +469,6 @@ static int rockchip_saradc_probe(struct
+ 		return ret;
+ 	}
+ 
+-	info->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
+-	if (IS_ERR(info->pclk))
+-		return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
+-				     "failed to get pclk\n");
+-
+-	info->clk = devm_clk_get(&pdev->dev, "saradc");
+-	if (IS_ERR(info->clk))
+-		return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
+-				     "failed to get adc clock\n");
+-
+ 	info->vref = devm_regulator_get(&pdev->dev, "vref");
+ 	if (IS_ERR(info->vref))
+ 		return dev_err_probe(&pdev->dev, PTR_ERR(info->vref),
+@@ -501,6 +477,16 @@ static int rockchip_saradc_probe(struct
+ 	if (info->reset)
+ 		rockchip_saradc_reset_controller(info->reset);
+ 
++	info->pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk");
++	if (IS_ERR(info->pclk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(info->pclk),
++				     "failed to get pclk\n");
++
++	info->clk = devm_clk_get_enabled(&pdev->dev, "saradc");
++	if (IS_ERR(info->clk))
++		return dev_err_probe(&pdev->dev, PTR_ERR(info->clk),
++				     "failed to get adc clock\n");
++
+ 	/*
+ 	 * Use a default value for the converter clock.
+ 	 * This may become user-configurable in the future.
+@@ -530,32 +516,6 @@ static int rockchip_saradc_probe(struct
+ 
+ 	info->uv_vref = ret;
+ 
+-	ret = clk_prepare_enable(info->pclk);
+-	if (ret < 0) {
+-		dev_err(&pdev->dev, "failed to enable pclk\n");
+-		return ret;
+-	}
+-	ret = devm_add_action_or_reset(&pdev->dev,
+-				       rockchip_saradc_pclk_disable, info);
+-	if (ret) {
+-		dev_err(&pdev->dev, "failed to register devm action, %d\n",
+-			ret);
+-		return ret;
+-	}
+-
+-	ret = clk_prepare_enable(info->clk);
+-	if (ret < 0) {
+-		dev_err(&pdev->dev, "failed to enable converter clock\n");
+-		return ret;
+-	}
+-	ret = devm_add_action_or_reset(&pdev->dev,
+-				       rockchip_saradc_clk_disable, info);
+-	if (ret) {
+-		dev_err(&pdev->dev, "failed to register devm action, %d\n",
+-			ret);
+-		return ret;
+-	}
+-
+ 	platform_set_drvdata(pdev, indio_dev);
+ 
+ 	indio_dev->name = dev_name(&pdev->dev);
+@@ -589,8 +549,6 @@ static int rockchip_saradc_suspend(struc
+ 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ 	struct rockchip_saradc *info = iio_priv(indio_dev);
+ 
+-	clk_disable_unprepare(info->clk);
+-	clk_disable_unprepare(info->pclk);
+ 	regulator_disable(info->vref);
+ 
+ 	return 0;
+@@ -600,21 +558,8 @@ static int rockchip_saradc_resume(struct
+ {
+ 	struct iio_dev *indio_dev = dev_get_drvdata(dev);
+ 	struct rockchip_saradc *info = iio_priv(indio_dev);
+-	int ret;
+-
+-	ret = regulator_enable(info->vref);
+-	if (ret)
+-		return ret;
+-
+-	ret = clk_prepare_enable(info->pclk);
+-	if (ret)
+-		return ret;
+-
+-	ret = clk_prepare_enable(info->clk);
+-	if (ret)
+-		clk_disable_unprepare(info->pclk);
+ 
+-	return ret;
++	return regulator_enable(info->vref);
+ }
+ 
+ static DEFINE_SIMPLE_DEV_PM_OPS(rockchip_saradc_pm_ops,
diff --git a/target/linux/rockchip/patches-6.1/350-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch b/target/linux/rockchip/patches-6.1/350-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch
new file mode 100644
index 00000000000..e8c2cf658bf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/350-iio-adc-rockchip_saradc-Use-of_device_get_match_data.patch
@@ -0,0 +1,46 @@
+From 3e7fa640c0b0d42dddd9d83696f320d36736772c Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 17 May 2023 04:30:47 +0530
+Subject: [PATCH 350/383] iio: adc: rockchip_saradc: Use
+ of_device_get_match_data
+
+Use of_device_get_match_data() to simplify the code.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iio/adc/rockchip_saradc.c | 8 ++++----
+ 1 file changed, 4 insertions(+), 4 deletions(-)
+
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -405,10 +405,10 @@ static void rockchip_saradc_regulator_un
+ 
+ static int rockchip_saradc_probe(struct platform_device *pdev)
+ {
++	const struct rockchip_saradc_data *match_data;
+ 	struct rockchip_saradc *info = NULL;
+ 	struct device_node *np = pdev->dev.of_node;
+ 	struct iio_dev *indio_dev = NULL;
+-	const struct of_device_id *match;
+ 	int ret;
+ 	int irq;
+ 
+@@ -422,13 +422,13 @@ static int rockchip_saradc_probe(struct
+ 	}
+ 	info = iio_priv(indio_dev);
+ 
+-	match = of_match_device(rockchip_saradc_match, &pdev->dev);
+-	if (!match) {
++	match_data = of_device_get_match_data(&pdev->dev);
++	if (!match_data) {
+ 		dev_err(&pdev->dev, "failed to match device\n");
+ 		return -ENODEV;
+ 	}
+ 
+-	info->data = match->data;
++	info->data = match_data;
+ 
+ 	/* Sanity check for possible later IP variants with more channels */
+ 	if (info->data->num_channels > SARADC_MAX_CHANNELS) {
diff --git a/target/linux/rockchip/patches-6.1/351-iio-adc-rockchip_saradc-Match-alignment-with-open-pa.patch b/target/linux/rockchip/patches-6.1/351-iio-adc-rockchip_saradc-Match-alignment-with-open-pa.patch
new file mode 100644
index 00000000000..14deda14046
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/351-iio-adc-rockchip_saradc-Match-alignment-with-open-pa.patch
@@ -0,0 +1,37 @@
+From e6818f0bc824d568f2de549dff6074125315dde2 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 17 May 2023 04:30:48 +0530
+Subject: [PATCH 351/383] iio: adc: rockchip_saradc: Match alignment with open
+ parenthesis
+
+Match alignment with open parenthesis for improving the code
+readability.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iio/adc/rockchip_saradc.c | 5 ++---
+ 1 file changed, 2 insertions(+), 3 deletions(-)
+
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -141,7 +141,7 @@ static void rockchip_saradc_power_down(s
+ }
+ 
+ static int rockchip_saradc_conversion(struct rockchip_saradc *info,
+-				   struct iio_chan_spec const *chan)
++				      struct iio_chan_spec const *chan)
+ {
+ 	reinit_completion(&info->completion);
+ 
+@@ -384,8 +384,7 @@ out:
+ }
+ 
+ static int rockchip_saradc_volt_notify(struct notifier_block *nb,
+-						   unsigned long event,
+-						   void *data)
++				       unsigned long event, void *data)
+ {
+ 	struct rockchip_saradc *info =
+ 			container_of(nb, struct rockchip_saradc, nb);
diff --git a/target/linux/rockchip/patches-6.1/352-iio-adc-rockchip_saradc-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/352-iio-adc-rockchip_saradc-Use-dev_err_probe.patch
new file mode 100644
index 00000000000..0e481c21e14
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/352-iio-adc-rockchip_saradc-Use-dev_err_probe.patch
@@ -0,0 +1,87 @@
+From 3282a5fc907d785598107ceb558486eeddf22991 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 17 May 2023 04:30:49 +0530
+Subject: [PATCH 352/383] iio: adc: rockchip_saradc: Use dev_err_probe
+
+Use dev_err_probe instead of dev_err in probe function,
+which simplifies code a little bit and prints the error
+code.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/iio/adc/rockchip_saradc.c | 45 ++++++++++++++-----------------
+ 1 file changed, 20 insertions(+), 25 deletions(-)
+
+--- a/drivers/iio/adc/rockchip_saradc.c
++++ b/drivers/iio/adc/rockchip_saradc.c
+@@ -415,25 +415,23 @@ static int rockchip_saradc_probe(struct
+ 		return -ENODEV;
+ 
+ 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*info));
+-	if (!indio_dev) {
+-		dev_err(&pdev->dev, "failed allocating iio device\n");
+-		return -ENOMEM;
+-	}
++	if (!indio_dev)
++		return dev_err_probe(&pdev->dev, -ENOMEM,
++				     "failed allocating iio device\n");
++
+ 	info = iio_priv(indio_dev);
+ 
+ 	match_data = of_device_get_match_data(&pdev->dev);
+-	if (!match_data) {
+-		dev_err(&pdev->dev, "failed to match device\n");
+-		return -ENODEV;
+-	}
++	if (!match_data)
++		return dev_err_probe(&pdev->dev, -ENODEV,
++				     "failed to match device\n");
+ 
+ 	info->data = match_data;
+ 
+ 	/* Sanity check for possible later IP variants with more channels */
+-	if (info->data->num_channels > SARADC_MAX_CHANNELS) {
+-		dev_err(&pdev->dev, "max channels exceeded");
+-		return -EINVAL;
+-	}
++	if (info->data->num_channels > SARADC_MAX_CHANNELS)
++		return dev_err_probe(&pdev->dev, -EINVAL,
++				     "max channels exceeded");
+ 
+ 	info->regs = devm_platform_ioremap_resource(pdev, 0);
+ 	if (IS_ERR(info->regs))
+@@ -491,23 +489,20 @@ static int rockchip_saradc_probe(struct
+ 	 * This may become user-configurable in the future.
+ 	 */
+ 	ret = clk_set_rate(info->clk, info->data->clk_rate);
+-	if (ret < 0) {
+-		dev_err(&pdev->dev, "failed to set adc clk rate, %d\n", ret);
+-		return ret;
+-	}
++	if (ret < 0)
++		return dev_err_probe(&pdev->dev, ret,
++				     "failed to set adc clk rate\n");
+ 
+ 	ret = regulator_enable(info->vref);
+-	if (ret < 0) {
+-		dev_err(&pdev->dev, "failed to enable vref regulator\n");
+-		return ret;
+-	}
++	if (ret < 0)
++		return dev_err_probe(&pdev->dev, ret,
++				     "failed to enable vref regulator\n");
++
+ 	ret = devm_add_action_or_reset(&pdev->dev,
+ 				       rockchip_saradc_regulator_disable, info);
+-	if (ret) {
+-		dev_err(&pdev->dev, "failed to register devm action, %d\n",
+-			ret);
+-		return ret;
+-	}
++	if (ret)
++		return dev_err_probe(&pdev->dev, ret,
++				     "failed to register devm action\n");
+ 
+ 	ret = regulator_get_voltage(info->vref);
+ 	if (ret < 0)
diff --git a/target/linux/rockchip/patches-6.1/353-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK.patch b/target/linux/rockchip/patches-6.1/353-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK.patch
new file mode 100644
index 00000000000..a7dac0c06ef
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/353-arm64-dts-rockchip-Add-DT-node-for-ADC-support-in-RK.patch
@@ -0,0 +1,36 @@
+From 8b429e32286bce5a132624ee2bab1a102ffff2a3 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Wed, 17 May 2023 04:30:50 +0530
+Subject: [PATCH 353/383] arm64: dts: rockchip: Add DT node for ADC support in
+ RK3588
+
+Add DT node for ADC support in RK3588.
+
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -2791,6 +2791,18 @@
+ 		status = "disabled";
+ 	};
+ 
++	saradc: saradc@fec10000 {
++		compatible = "rockchip,rk3588-saradc";
++		reg = <0x0 0xfec10000 0x0 0x10000>;
++		interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
++		#io-channel-cells = <1>;
++		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
++		clock-names = "saradc", "apb_pclk";
++		resets = <&cru SRST_P_SARADC>;
++		reset-names = "saradc-apb";
++		status = "disabled";
++	};
++
+ 	system_sram2: sram@ff001000 {
+ 		compatible = "mmio-sram";
+ 		reg = <0x0 0xff001000 0x0 0xef000>;
diff --git a/target/linux/rockchip/patches-6.1/354-clk-divider-Fix-handling-of-rates-UINT_MAX.patch b/target/linux/rockchip/patches-6.1/354-clk-divider-Fix-handling-of-rates-UINT_MAX.patch
new file mode 100644
index 00000000000..d31836c148d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/354-clk-divider-Fix-handling-of-rates-UINT_MAX.patch
@@ -0,0 +1,44 @@
+From 62c5be96675c0c9407575910c4ecc9ab23223366 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 18 May 2023 05:19:48 +0200
+Subject: [PATCH 354/383] clk: divider: Fix handling of rates > UINT_MAX
+
+Fix handling of rates that exceed UINT_MAX (4.29 GHz) to do something
+reasonably sensible. Right now asking for UINT_MAX+1 will effectively
+return the smallest rate available instead of the biggest one.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/clk-divider.c | 6 +++---
+ 1 file changed, 3 insertions(+), 3 deletions(-)
+
+--- a/drivers/clk/clk-divider.c
++++ b/drivers/clk/clk-divider.c
+@@ -220,7 +220,7 @@ static int _div_round_up(const struct cl
+ 			 unsigned long parent_rate, unsigned long rate,
+ 			 unsigned long flags)
+ {
+-	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	int div = DIV_ROUND_UP_ULL((u64)parent_rate, rate > UINT_MAX ? UINT_MAX : rate);
+ 
+ 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
+ 		div = __roundup_pow_of_two(div);
+@@ -237,7 +237,7 @@ static int _div_round_closest(const stru
+ 	int up, down;
+ 	unsigned long up_rate, down_rate;
+ 
+-	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	up = DIV_ROUND_UP_ULL((u64)parent_rate, rate > UINT_MAX ? UINT_MAX : rate);
+ 	down = parent_rate / rate;
+ 
+ 	if (flags & CLK_DIVIDER_POWER_OF_TWO) {
+@@ -473,7 +473,7 @@ int divider_get_val(unsigned long rate,
+ {
+ 	unsigned int div, value;
+ 
+-	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
++	div = DIV_ROUND_UP_ULL((u64)parent_rate, rate > UINT_MAX ? UINT_MAX : rate);
+ 
+ 	if (!_is_valid_div(table, div, flags))
+ 		return -EINVAL;
diff --git a/target/linux/rockchip/patches-6.1/355-clk-composite-Fix-handling-of-high-clock-rates.patch b/target/linux/rockchip/patches-6.1/355-clk-composite-Fix-handling-of-high-clock-rates.patch
new file mode 100644
index 00000000000..bbeabf2fde6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/355-clk-composite-Fix-handling-of-high-clock-rates.patch
@@ -0,0 +1,46 @@
+From 8c754b5fb21d7987f1ca55bcaecc506ef14b2f7d Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 18 May 2023 05:28:17 +0200
+Subject: [PATCH 355/383] clk: composite: Fix handling of high clock rates
+
+If clk_round_rate(clk, ULONG_MAX) is called to acquire the highest
+available clock rate and the highest available clock rate is smaller
+than ULONG_MAX/2, the result of "req->rate - tmp_req.rate" has the
+highest bit set. Since the input to abs() is signed, that means the
+number will be miss-interpreted.
+
+This results in the logic being reverted and the worst choice being
+selected as the best one. For example this has been observed on RK3588
+for the eMMC clock:
+
+GPLL:   abs(18446744073709551615 - 1188000000) = 1188000001
+CPLL:   abs(18446744073709551615 - 1500000000) = 1500000001
+XIN24M: abs(18446744073709551615 -   24000000) =   24000001
+
+With the updated logic any casting between signed and unsigned is
+avoided and the numbers look like this instead:
+
+GPLL:   18446744073709551615 - 1188000000 = 18446744072521551615
+CPLL:   18446744073709551615 - 1500000000 = 18446744072209551615
+XIN24M: 18446744073709551615 -   24000000 = 18446744073685551615
+
+As a result the parent with the highest acceptable rate is chosen
+instead of the parent clock with the lowest one.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ drivers/clk/clk-composite.c | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/clk/clk-composite.c
++++ b/drivers/clk/clk-composite.c
+@@ -119,7 +119,7 @@ static int clk_composite_determine_rate(
+ 			if (ret)
+ 				continue;
+ 
+-			rate_diff = abs(req->rate - tmp_req.rate);
++			rate_diff = req->rate > tmp_req.rate ? req->rate - tmp_req.rate : tmp_req.rate - req->rate;
+ 
+ 			if (!rate_diff || !req->best_parent_hw
+ 				       || best_rate_diff > rate_diff) {
diff --git a/target/linux/rockchip/patches-6.1/356-media-dt-bindings-media-rockchip-rga-add-rockchip-rk.patch b/target/linux/rockchip/patches-6.1/356-media-dt-bindings-media-rockchip-rga-add-rockchip-rk.patch
new file mode 100644
index 00000000000..eb227704658
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/356-media-dt-bindings-media-rockchip-rga-add-rockchip-rk.patch
@@ -0,0 +1,38 @@
+From 65ec9cb7675f429629ab444f68de1407d5e7874a Mon Sep 17 00:00:00 2001
+From: Michael Tretter <m.tretter@pengutronix.de>
+Date: Fri, 20 Jan 2023 10:14:21 +0100
+Subject: [PATCH 356/383] media: dt-bindings: media: rockchip-rga: add
+ rockchip,rk3568-rga
+
+Add a new compatible for the rk3568 Rockchip SoC, which also features an
+RGA, which is called RGA2 in the TRM Part2. It is the same core as used
+on the rk3288, which documents the same RGA2.
+
+Specify a new compatible for the rk3568 to be able to handle unknown
+SoC-specific differences in the driver.
+
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
+Reviewed-by: Ezequiel Garcia <ezequiel@vanguardiasur.com.ar>
+Acked-by: Sakari Ailus <sakari.ailus@linux.intel.com>
+Acked-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Link: https://lore.kernel.org/r/20230119-rk3568-rga-v1-1-43d4d14365e6@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/media/rockchip-rga.yaml | 4 +++-
+ 1 file changed, 3 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/media/rockchip-rga.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip-rga.yaml
+@@ -21,7 +21,9 @@ properties:
+       - const: rockchip,rk3288-rga
+       - const: rockchip,rk3399-rga
+       - items:
+-          - const: rockchip,rk3228-rga
++          - enum:
++              - rockchip,rk3228-rga
++              - rockchip,rk3568-rga
+           - const: rockchip,rk3288-rga
+ 
+   reg:
diff --git a/target/linux/rockchip/patches-6.1/357-arm64-dts-rockchip-Add-RGA2-support-to-rk356x.patch b/target/linux/rockchip/patches-6.1/357-arm64-dts-rockchip-Add-RGA2-support-to-rk356x.patch
new file mode 100644
index 00000000000..e8d933b92bf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/357-arm64-dts-rockchip-Add-RGA2-support-to-rk356x.patch
@@ -0,0 +1,38 @@
+From d521e2e3eaae676036d9d0d72166a54a89d837b8 Mon Sep 17 00:00:00 2001
+From: Michael Tretter <m.tretter@pengutronix.de>
+Date: Fri, 20 Jan 2023 10:14:22 +0100
+Subject: [PATCH 357/383] arm64: dts: rockchip: Add RGA2 support to rk356x
+
+The rk3568 also features a RGA2 block. Add the necessary device tree
+node.
+
+Acked-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Signed-off-by: Michael Tretter <m.tretter@pengutronix.de>
+Acked-by: Nicolas Dufresne <nicolas.dufresne@collabora.com>
+Link: https://lore.kernel.org/r/20230119-rk3568-rga-v1-2-43d4d14365e6@pengutronix.de
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -613,6 +613,17 @@
+ 		#iommu-cells = <0>;
+ 	};
+ 
++	rga: rga@fdeb0000 {
++		compatible = "rockchip,rk3568-rga", "rockchip,rk3288-rga";
++		reg = <0x0 0xfdeb0000 0x0 0x180>;
++		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
++		clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru CLK_RGA_CORE>;
++		clock-names = "aclk", "hclk", "sclk";
++		resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
++		reset-names = "core", "axi", "ahb";
++		power-domains = <&power RK3568_PD_RGA>;
++	};
++
+ 	vepu: video-codec@fdee0000 {
+ 		compatible = "rockchip,rk3568-vepu";
+ 		reg = <0x0 0xfdee0000 0x0 0x800>;
diff --git a/target/linux/rockchip/patches-6.1/358-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch b/target/linux/rockchip/patches-6.1/358-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch
new file mode 100644
index 00000000000..8b6d36497cf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/358-dt-bindings-arm-rockchip-Add-Edgeble-Neural-Compute-.patch
@@ -0,0 +1,41 @@
+From d18b4cbe5f50da216461f74474344d7d4ae427fa Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 16 May 2023 22:04:51 +0530
+Subject: [PATCH 358/383] dt-bindings: arm: rockchip: Add Edgeble Neural
+ Compute Module 6B
+
+Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
+based on Rockchip RK3588J from Edgeble AI.
+
+Edgeble Neural Compute Module 6B(Neu6B) IO board is an industrial
+form factor evaluation board from Edgeble AI.
+
+Neu6B needs to mount on top of this IO board in order to create complete
+Edgeble Neural Compute Module 6B(Neu6B) IO platform.
+
+This patch add dt-bindings for Edgeble Neu6 Model B SoM based IO board.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230516163454.997736-1-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -107,6 +107,12 @@ properties:
+           - const: edgeble,neural-compute-module-6a     # Edgeble Neural Compute Module 6A SoM
+           - const: rockchip,rk3588
+ 
++      - description: Edgeble Neural Compute Module 6(Neu6) Model B SoM based boards
++        items:
++          - const: edgeble,neural-compute-module-6b-io  # Edgeble Neural Compute Module 6B IO Board
++          - const: edgeble,neural-compute-module-6b     # Edgeble Neural Compute Module 6B SoM
++          - const: rockchip,rk3588
++
+       - description: Elgin RV1108 R1
+         items:
+           - const: elgin,rv1108-r1
diff --git a/target/linux/rockchip/patches-6.1/359-arm64-dts-rockchip-Add-Rockchip-RK3588J.patch b/target/linux/rockchip/patches-6.1/359-arm64-dts-rockchip-Add-Rockchip-RK3588J.patch
new file mode 100644
index 00000000000..6eec2bf6ab9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/359-arm64-dts-rockchip-Add-Rockchip-RK3588J.patch
@@ -0,0 +1,33 @@
+From c1a47d26199aa55b018c5bd4c6544db8dfec03f2 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 16 May 2023 22:04:52 +0530
+Subject: [PATCH 359/383] arm64: dts: rockchip: Add Rockchip RK3588J
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Rockchip RK3588J is the industrial-grade version of RK3588 SoC and
+is operated with -40 °C to +85 °C temparature.
+
+Add rk3588j specific dtsi for adding rk3588j specific operating points
+and other changes to be add in future.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230516163454.997736-2-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588j.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588j.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588j.dtsi
+@@ -0,0 +1,7 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 Rockchip Electronics Co., Ltd.
++ *
++ */
++
++#include "rk3588.dtsi"
diff --git a/target/linux/rockchip/patches-6.1/360-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-S.patch b/target/linux/rockchip/patches-6.1/360-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-S.patch
new file mode 100644
index 00000000000..85b94515e52
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/360-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-S.patch
@@ -0,0 +1,68 @@
+From f5fa895e94f65e5918f00122dbba3624e3ec86e8 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 16 May 2023 22:04:53 +0530
+Subject: [PATCH 360/383] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model
+ B SoM
+
+Neural Compute Module 6B(Neu6B) is a 96boards SoM-CB compute module
+based on Rockchip RK3588J from Edgeble AI.
+
+General features:
+- Rockchip RK3588J
+- up to 32GB LPDDR4x
+- up to 128GB eMMC
+- 2x MIPI CSI2 FPC
+
+On module WiFi6/BT5 is available in the following Neu6 variants.
+
+Neu6B needs to mount on top of associated Edgeble Neu6B IO boards for
+creating complete platform solutions.
+
+Enable eMMC for now to boot Linux successfully.
+
+Add support for Edgeble Neu6 Model B SoM.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230516163454.997736-3-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../dts/rockchip/rk3588-edgeble-neu6b.dtsi    | 32 +++++++++++++++++++
+ 1 file changed, 32 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
+
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b.dtsi
+@@ -0,0 +1,32 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
++ */
++
++/ {
++	compatible = "edgeble,neural-compute-module-6b", "rockchip,rk3588";
++
++	aliases {
++		mmc0 = &sdhci;
++	};
++
++	vcc12v_dcin: vcc12v-dcin-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc12v_dcin";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <12000000>;
++		regulator-max-microvolt = <12000000>;
++	};
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	max-frequency = <200000000>;
++	mmc-hs400-1_8v;
++	mmc-hs400-enhanced-strobe;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/361-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-I.patch b/target/linux/rockchip/patches-6.1/361-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-I.patch
new file mode 100644
index 00000000000..6e787be5a05
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/361-arm64-dts-rockchip-rk3588-Add-Edgeble-Neu6-Model-B-I.patch
@@ -0,0 +1,88 @@
+From 73aa3caa93f28147d9ac3217224279b60d988485 Mon Sep 17 00:00:00 2001
+From: Jagan Teki <jagan@edgeble.ai>
+Date: Tue, 16 May 2023 22:04:54 +0530
+Subject: [PATCH 361/383] arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model
+ B IO
+
+Neural Compute Module 6B(Neu6B) IO board is an industrial form factor
+ready-to-use IO board from Edgeble AI.
+
+IO board offers plenty of peripherals and connectivity options and
+this patch enables basic eMMC and UART which is enough to successfully
+boot Linux.
+
+General features:
+- microSD slot
+- 1x HDMI Out
+- 1x HDMI In
+- 2x DP
+- 1x eDP
+- 2x MIPI DSI connector
+- 4x MIPI CSI2 connector
+- 2x USB Host
+- 2x USB 3.0 OTG/Host
+- 1x SATA
+- 1x 2.5Gbps Ethernet
+- 1x 4G/5G mini PCIe
+- 1x M.2 E-Key slot
+- 1x Onboard PoE
+- 1x RS485, RS232, CAN
+- 1x Audio, MIC port
+- RTC battery slot
+- 40-pin GPIO expansion
+
+Neu6B needs to mount on top of this IO board in order to create a
+complete Edgeble Neural Compute Module 6B(Neu6B) IO platform.
+
+Add support for Edgeble Neu6 Model B IO Board.
+
+Signed-off-by: Jagan Teki <jagan@edgeble.ai>
+Link: https://lore.kernel.org/r/20230516163454.997736-4-jagan@edgeble.ai
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |  1 +
+ .../dts/rockchip/rk3588-edgeble-neu6b-io.dts  | 27 +++++++++++++++++++
+ 2 files changed, 28 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -96,6 +96,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-od
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-radxa-e25.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-rock-3a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6a-io.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-edgeble-neu6b-io.dts
+@@ -0,0 +1,27 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2023 Edgeble AI Technologies Pvt. Ltd.
++ */
++
++/dts-v1/;
++#include "rk3588j.dtsi"
++#include "rk3588-edgeble-neu6b.dtsi"
++
++/ {
++	model = "Edgeble Neu6B IO Board";
++	compatible = "edgeble,neural-compute-module-6b-io",
++		     "edgeble,neural-compute-module-6b", "rockchip,rk3588";
++
++	aliases {
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch b/target/linux/rockchip/patches-6.1/362-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
similarity index 78%
rename from target/linux/rockchip/patches-6.1/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
rename to target/linux/rockchip/patches-6.1/362-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
index 792028b2929..7c996c495aa 100644
--- a/target/linux/rockchip/patches-6.1/005-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
+++ b/target/linux/rockchip/patches-6.1/362-arm64-dts-rockchip-add-EEPROM-node-for-NanoPi-R4S.patch
@@ -1,12 +1,13 @@
-From af20b3384e8723077cc6484160b0cf4e9be321de Mon Sep 17 00:00:00 2001
+From cb86d7d0389543eb04f79887cfc9e14d7cd3d549 Mon Sep 17 00:00:00 2001
 From: Tianling Shen <cnsztl@gmail.com>
 Date: Mon, 7 Jun 2021 15:45:37 +0800
-Subject: [PATCH] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
+Subject: [PATCH 362/383] arm64: dts: rockchip: add EEPROM node for NanoPi R4S
 
 NanoPi R4S has a EEPROM attached to the 2nd I2C bus (U92), which
 stores the MAC address.
 
 Signed-off-by: Tianling Shen <cnsztl@gmail.com>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
  arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 9 +++++++++
  1 file changed, 9 insertions(+)
diff --git a/target/linux/rockchip/patches-6.1/363-rockchip-use-system-LED-for-OpenWrt.patch b/target/linux/rockchip/patches-6.1/363-rockchip-use-system-LED-for-OpenWrt.patch
new file mode 100644
index 00000000000..50ad260e21f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/363-rockchip-use-system-LED-for-OpenWrt.patch
@@ -0,0 +1,45 @@
+From dd1dfd48c44d5d6228d3a17a4a6c682c952dda15 Mon Sep 17 00:00:00 2001
+From: David Bauer <mail@david-bauer.net>
+Date: Fri, 10 Jul 2020 21:38:20 +0200
+Subject: [PATCH 363/383] rockchip: use system LED for OpenWrt
+
+Use the SYS LED on the casing for showing system status.
+
+This patch is kept separate from the NanoPi R2S support patch, as i plan
+on submitting the device support upstream.
+
+Signed-off-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 5 +++++
+ arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts     | 5 +++++
+ 2 files changed, 10 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
+@@ -16,6 +16,11 @@
+ 	aliases {
+ 		ethernet1 = &rtl8153;
+ 		mmc0 = &sdmmc;
++
++		led-boot = &sys_led;
++		led-failsafe = &sys_led;
++		led-running = &sys_led;
++		led-upgrade = &sys_led;
+ 	};
+ 
+ 	chosen {
+--- a/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3328-roc-cc.dts
+@@ -13,6 +13,11 @@
+ 	aliases {
+ 		mmc0 = &sdmmc;
+ 		mmc1 = &emmc;
++
++		led-boot = &power_led;
++		led-failsafe = &power_led;
++		led-running = &power_led;
++		led-upgrade = &power_led;
+ 	};
+ 
+ 	chosen {
diff --git a/target/linux/rockchip/patches-6.1/101-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch b/target/linux/rockchip/patches-6.1/364-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
similarity index 65%
rename from target/linux/rockchip/patches-6.1/101-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
rename to target/linux/rockchip/patches-6.1/364-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
index 5fe60d1adec..07ae46c855e 100644
--- a/target/linux/rockchip/patches-6.1/101-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
+++ b/target/linux/rockchip/patches-6.1/364-arm64-rockchip-add-OF-node-for-USB-eth-on-NanoPi-R2S.patch
@@ -1,20 +1,22 @@
-From 2795c8b31a686bdb8338f9404d18ef7a154f0d75 Mon Sep 17 00:00:00 2001
+From c7e0d368500083cae1ec84039ceabd308929509a Mon Sep 17 00:00:00 2001
 From: David Bauer <mail@david-bauer.net>
 Date: Sun, 26 Jul 2020 13:32:59 +0200
-Subject: [PATCH] arm64: rockchip: add OF node for USB eth on NanoPi R2S
+Subject: [PATCH 364/383] arm64: rockchip: add OF node for USB eth on NanoPi
+ R2S
 
 This adds the OF node for the USB3 ethernet adapter on the FriendlyARM
 NanoPi R2S. Add the correct value for the RTL8153 LED configuration
 register to match the blink behavior of the other port on the device.
 
 Signed-off-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
- arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 7 +++++++
- 1 file changed, 1 insertions(+)
+ arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts | 1 +
+ 1 file changed, 1 insertion(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-r2s.dts
-@@ -404,6 +404,7 @@
+@@ -402,6 +402,7 @@
  	rtl8153: device@2 {
  		compatible = "usbbda,8153";
  		reg = <2>;
diff --git a/target/linux/rockchip/patches-6.1/103-nanopi-r4s-sd-signalling.patch b/target/linux/rockchip/patches-6.1/365-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch
similarity index 65%
rename from target/linux/rockchip/patches-6.1/103-nanopi-r4s-sd-signalling.patch
rename to target/linux/rockchip/patches-6.1/365-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch
index 1a72b02d44a..d80d0391acc 100644
--- a/target/linux/rockchip/patches-6.1/103-nanopi-r4s-sd-signalling.patch
+++ b/target/linux/rockchip/patches-6.1/365-arm64-dts-rockchip-disable-UHS-modes-for-NanoPi-R4S.patch
@@ -1,5 +1,8 @@
+From cc168436ddb0538102c153463130f65c42ff667a Mon Sep 17 00:00:00 2001
 From: David Bauer <mail@david-bauer.net>
-Subject: arm64: dts: rockchip: disable UHS modes for NanoPi R4S
+Date: Sat, 27 May 2023 18:35:14 -0400
+Subject: [PATCH 365/383] arm64: dts: rockchip: disable UHS modes for NanoPi
+ R4S
 
 The NanoPi R4S leaves the SD card in 1.8V signalling when rebooting
 while U-Boot requires the card to be in 3.3V mode.
@@ -9,10 +12,14 @@ mode. This reduces transfer speeds but ensures a reboot whether from
 userspace or following a kernel panic is always working.
 
 Signed-off-by: David Bauer <mail@david-bauer.net>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts | 5 +++++
+ 1 file changed, 5 insertions(+)
 
 --- a/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
 +++ b/arch/arm64/boot/dts/rockchip/rk3399-nanopi-r4s.dts
-@@ -128,6 +128,11 @@
+@@ -121,6 +121,11 @@
  	status = "disabled";
  };
  
diff --git a/target/linux/rockchip/patches-6.1/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch b/target/linux/rockchip/patches-6.1/366-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
similarity index 81%
rename from target/linux/rockchip/patches-6.1/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch
rename to target/linux/rockchip/patches-6.1/366-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
index 620e28a4154..ad23d552f43 100644
--- a/target/linux/rockchip/patches-6.1/205-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-Neo3.patch
+++ b/target/linux/rockchip/patches-6.1/366-rockchip-rk3328-add-support-for-FriendlyARM-NanoPi-N.patch
@@ -1,7 +1,8 @@
-From 0f989817a4c1d2c3d196d550ff05cda98bc91324 Mon Sep 17 00:00:00 2001
-From: Julian Pidancet <julian@pidancet.net>
-Date: Sun, 23 Jan 2022 16:34:08 +0100
-Subject: [PATCH v2] rockchip: rk3328: add support for FriendlyARM NanoPi NEO3
+From a86cf14768f9cebd8cf4816d2fdbfcde2bc7a7cd Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Wed, 12 May 2021 13:04:20 -0400
+Subject: [PATCH 366/383] rockchip: rk3328: add support for FriendlyARM NanoPi
+ NEO3
 
 This patch adds support for FriendlyARM NanoPi NEO3
 
@@ -16,40 +17,29 @@ Fan:      2 Pin JST ZH 1.5mm Connector for 5V Fan
 GPIO:     26 pin-header, include I2C, UART, SPI, I2S, GPIO
 Power:    5V/1A, via Type-C or GPIO
 
-Signed-off-by: Julian Pidancet <julian@pidancet.net>
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
 ---
-
-This is another shot at previous work submitted by Marty Jones
-<mj8263788@gmail.com> (https://lore.kernel.org/linux-arm-kernel/20201228152836.02795e09.mj8263788@gmail.com/),
-which is now a year old.
-
-v2: Following up on Robin Murphy's comments, the NEO3 DTS is now
-standalone and no longer includes the nanopi R2S one. The lan_led and
-wan_len nodes have been removed, and the sys_led node has been renamed
-to status_led in accordance with the board schematics.
-
  arch/arm64/boot/dts/rockchip/Makefile         |   1 +
- .../boot/dts/rockchip/rk3328-nanopi-neo3.dts  | 396 ++++++++++++++++++
- 2 files changed, 397 insertions(+)
+ .../boot/dts/rockchip/rk3328-nanopi-neo3.dts  | 359 ++++++++++++++++++
+ 2 files changed, 360 insertions(+)
  create mode 100644 arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
 
 --- a/arch/arm64/boot/dts/rockchip/Makefile
 +++ b/arch/arm64/boot/dts/rockchip/Makefile
-@@ -12,6 +12,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
+@@ -16,6 +16,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-a1
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-evb.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2c-plus.dtb
 +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-neo3.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-nanopi-r2s.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus.dtb
  dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-orangepi-r1-plus-lts.dtb
- dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3328-rock64.dtb
 --- /dev/null
 +++ b/arch/arm64/boot/dts/rockchip/rk3328-nanopi-neo3.dts
-@@ -0,0 +1,394 @@
+@@ -0,0 +1,359 @@
 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 +/*
 + * Copyright (c) 2020 David Bauer <mail@david-bauer.net>
-+ * Copyright (c) 2022 Julian Pidancet <julian@pidancet.net>
 + */
 +
 +/dts-v1/;
@@ -62,13 +52,6 @@ to status_led in accordance with the board schematics.
 +	model = "FriendlyElec NanoPi NEO3";
 +	compatible = "friendlyarm,nanopi-neo3", "rockchip,rk3328";
 +
-+	aliases {
-+		led-boot = &status_led;
-+		led-failsafe = &status_led;
-+		led-running = &status_led;
-+		led-upgrade = &status_led;
-+	};
-+
 +	chosen {
 +		stdout-path = "serial2:1500000n8";
 +	};
@@ -95,12 +78,12 @@ to status_led in accordance with the board schematics.
 +
 +	leds {
 +		compatible = "gpio-leds";
-+		pinctrl-0 = <&status_led_pin>;
++		pinctrl-0 = <&stat_led_pin>;
 +		pinctrl-names = "default";
 +
-+		status_led: led-0 {
++		stat_led: led-1 {
 +			gpios = <&gpio0 RK_PA2 GPIO_ACTIVE_HIGH>;
-+			label = "nanopi-neo3:green:status";
++			label = "nanopi-neo3:green:stat";
 +		};
 +	};
 +
@@ -118,7 +101,7 @@ to status_led in accordance with the board schematics.
 +		regulator-type = "voltage";
 +		startup-delay-us = <2000>;
 +		states = <1800000 0x1>,
-+			 <3300000 0x0>;
++			  <3300000 0x0>;
 +		vin-supply = <&vcc_io_33>;
 +	};
 +
@@ -142,18 +125,6 @@ to status_led in accordance with the board schematics.
 +		regulator-min-microvolt = <5000000>;
 +		regulator-max-microvolt = <5000000>;
 +	};
-+
-+	vcc_rtl8153: vcc-rtl8153-regulator {
-+		compatible = "regulator-fixed";
-+		gpio = <&gpio2 RK_PC6 GPIO_ACTIVE_HIGH>;
-+		pinctrl-names = "default";
-+		pinctrl-0 = <&rtl8153_en_drv>;
-+		regulator-always-on;
-+		regulator-name = "vcc_rtl8153";
-+		regulator-min-microvolt = <5000000>;
-+		regulator-max-microvolt = <5000000>;
-+		enable-active-high;
-+	};
 +};
 +
 +&cpu0 {
@@ -342,14 +313,14 @@ to status_led in accordance with the board schematics.
 +		};
 +	};
 +
-+	ethernet-phy {
++	gmac2io {
 +		eth_phy_reset_pin: eth-phy-reset-pin {
 +			rockchip,pins = <1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_down>;
 +		};
 +	};
 +
 +	leds {
-+		status_led_pin: status-led-pin {
++		stat_led_pin: stat-led-pin {
 +			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
 +		};
 +	};
@@ -365,12 +336,6 @@ to status_led in accordance with the board schematics.
 +			rockchip,pins = <1 RK_PD4 RK_FUNC_GPIO &pcfg_pull_up>;
 +		};
 +	};
-+
-+	usb {
-+		rtl8153_en_drv: rtl8153-en-drv {
-+			rockchip,pins = <2 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
-+		};
-+	};
 +};
 +
 +&pwm2 {
@@ -430,13 +395,4 @@ to status_led in accordance with the board schematics.
 +&usbdrd3 {
 +	dr_mode = "host";
 +	status = "okay";
-+	#address-cells = <1>;
-+	#size-cells = <0>;
-+
-+	usb-eth@2 {
-+		compatible = "realtek,rtl8153";
-+		reg = <2>;
-+
-+		realtek,led-data = <0x87>;
-+	};
 +};
diff --git a/target/linux/rockchip/patches-6.1/367-dts-rockchip-fix-rock3-a.patch b/target/linux/rockchip/patches-6.1/367-dts-rockchip-fix-rock3-a.patch
new file mode 100644
index 00000000000..95660b5144d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/367-dts-rockchip-fix-rock3-a.patch
@@ -0,0 +1,110 @@
+From ca9300809c0bea2985dd18231b6882ef61929135 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sat, 27 May 2023 18:48:01 -0400
+Subject: [PATCH 367/383] dts: rockchip: fix rock3 a
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-rock-3a.dts      | 35 +++++++++----------
+ 1 file changed, 17 insertions(+), 18 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-rock-3a.dts
+@@ -32,13 +32,6 @@
+ 		};
+ 	};
+ 
+-	gmac1_clkin: external-gmac1-clock {
+-		compatible = "fixed-clock";
+-		clock-frequency = <125000000>;
+-		clock-output-names = "gmac1_clkin";
+-		#clock-cells = <0>;
+-	};
+-
+ 	leds {
+ 		compatible = "gpio-leds";
+ 
+@@ -256,18 +249,25 @@
+ 
+ &gmac1 {
+ 	assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
+-	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
+-	clock_in_out = "input";
++	assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru CLK_MAC1_2TOP>;
++	clock_in_out = "output";
+ 	phy-handle = <&rgmii_phy1>;
+-	phy-mode = "rgmii-id";
+-	phy-supply = <&vcc_3v3>;
++	phy-mode = "rgmii";
+ 	pinctrl-names = "default";
+ 	pinctrl-0 = <&gmac1m1_miim
+ 		     &gmac1m1_tx_bus2
+ 		     &gmac1m1_rx_bus2
+ 		     &gmac1m1_rgmii_clk
+-		     &gmac1m1_clkinout
+ 		     &gmac1m1_rgmii_bus>;
++
++	snps,reset-gpio = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++
++	tx_delay = <0x3c>;
++	rx_delay = <0x2f>;
++
+ 	status = "okay";
+ };
+ 
+@@ -413,6 +413,7 @@
+ 
+ 			vdda0v9_image: LDO_REG1 {
+ 				regulator-name = "vdda0v9_image";
++				regulator-always-on;
+ 				regulator-min-microvolt = <900000>;
+ 				regulator-max-microvolt = <900000>;
+ 
+@@ -449,6 +450,7 @@
+ 			vccio_acodec: LDO_REG4 {
+ 				regulator-name = "vccio_acodec";
+ 				regulator-always-on;
++				regulator-boot-on;
+ 				regulator-min-microvolt = <3300000>;
+ 				regulator-max-microvolt = <3300000>;
+ 
+@@ -507,6 +509,7 @@
+ 
+ 			vcca1v8_image: LDO_REG9 {
+ 				regulator-name = "vcca1v8_image";
++				regulator-always-on;
+ 				regulator-min-microvolt = <1800000>;
+ 				regulator-max-microvolt = <1800000>;
+ 
+@@ -527,6 +530,7 @@
+ 
+ 			vcc3v3_sd: SWITCH_REG2 {
+ 				regulator-name = "vcc3v3_sd";
++				regulator-always-on;
+ 
+ 				regulator-state-mem {
+ 					regulator-off-in-suspend;
+@@ -588,11 +592,6 @@
+ 	rgmii_phy1: ethernet-phy@0 {
+ 		compatible = "ethernet-phy-ieee802.3-c22";
+ 		reg = <0x0>;
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&eth_phy_rst>;
+-		reset-assert-us = <20000>;
+-		reset-deassert-us = <100000>;
+-		reset-gpios = <&gpio3 RK_PB0 GPIO_ACTIVE_LOW>;
+ 	};
+ };
+ 
+@@ -796,7 +795,7 @@
+ };
+ 
+ &usb_host0_xhci {
+-	extcon = <&usb2phy0>;
++	dr_mode = "host";
+ 	status = "okay";
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/368-dts-rockchip-fix-wifi-on-rock-pi-4b.patch b/target/linux/rockchip/patches-6.1/368-dts-rockchip-fix-wifi-on-rock-pi-4b.patch
new file mode 100644
index 00000000000..2915d548a37
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/368-dts-rockchip-fix-wifi-on-rock-pi-4b.patch
@@ -0,0 +1,21 @@
+From a86e557f9944b972b35329f2121277a2a6ef7dd3 Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sat, 27 May 2023 18:49:41 -0400
+Subject: [PATCH 368/383] dts: rockchip: fix wifi on rock pi 4b
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3399-rock-pi-4b.dts
+@@ -23,7 +23,7 @@
+ 		compatible = "brcm,bcm4329-fmac";
+ 		reg = <1>;
+ 		interrupt-parent = <&gpio0>;
+-		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_HIGH>;
++		interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ 		interrupt-names = "host-wake";
+ 		pinctrl-names = "default";
+ 		pinctrl-0 = <&wifi_host_wake_l>;
diff --git a/target/linux/rockchip/patches-6.1/369-dts-rockchip-fix-nanopi-r5c-r5s.patch b/target/linux/rockchip/patches-6.1/369-dts-rockchip-fix-nanopi-r5c-r5s.patch
new file mode 100644
index 00000000000..26b45b4c1e7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/369-dts-rockchip-fix-nanopi-r5c-r5s.patch
@@ -0,0 +1,233 @@
+From 72127f2c17ca963c368deabfa31261a5b6db9f2b Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Sat, 27 May 2023 18:51:15 -0400
+Subject: [PATCH 369/383] dts:rockchip: fix nanopi r5c/r5s
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ .../boot/dts/rockchip/rk3568-nanopi-r5c.dts   | 70 ++++++++++---------
+ .../boot/dts/rockchip/rk3568-nanopi-r5s.dts   | 17 ++---
+ 2 files changed, 41 insertions(+), 46 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5c.dts
+@@ -11,14 +11,14 @@
+ 
+ / {
+ 	model = "FriendlyElec NanoPi R5C";
+-	compatible = "friendlyarm,nanopi-r5c", "rockchip,rk3568";
++	compatible = "friendlyelec,nanopi-r5c", "rockchip,rk3568";
+ 
+-	gpio-keys {
++	gpio_keys: gpio-keys {
+ 		compatible = "gpio-keys";
+ 		pinctrl-names = "default";
+-		pinctrl-0 = <&reset_button_pin>;
++		pinctrl-0 = <&key1_pin>;
+ 
+-		button-reset {
++		key-reset {
+ 			debounce-interval = <50>;
+ 			gpios = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ 			label = "reset";
+@@ -28,39 +28,41 @@
+ 
+ 	gpio-leds {
+ 		compatible = "gpio-leds";
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&lan_led_pin>, <&power_led_pin>, <&wan_led_pin>, <&wlan_led_pin>;
+-
+-		led-lan {
+-			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_LAN;
+-			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
+-		};
+ 
+-		power_led: led-power {
+-			color = <LED_COLOR_ID_RED>;
+-			function = LED_FUNCTION_POWER;
++		sys_led: led-sys {
++			label = "red:sys";
+ 			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
+ 			gpios = <&gpio3 RK_PA2 GPIO_ACTIVE_HIGH>;
++			pinctrl-0 = <&sys_led_pin>;
+ 		};
+ 
+-		led-wan {
+-			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_WAN;
++		lan-led {
++			label = "green:lan";
++			gpios = <&gpio3 RK_PA3 GPIO_ACTIVE_HIGH>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan_led_pin>;
++		};
++
++		wan-led {
++			label = "green:wan";
+ 			gpios = <&gpio3 RK_PA4 GPIO_ACTIVE_HIGH>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&wan_led_pin>;
+ 		};
+ 
+-		led-wlan {
+-			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_WLAN;
++		wlan-led {
++			label = "green:wlan";
+ 			gpios = <&gpio3 RK_PA5 GPIO_ACTIVE_HIGH>;
++			pinctrl-names = "default";
++			pinctrl-0 = <&wlan_led_pin>;
+ 		};
+ 	};
+ };
+ 
+ &pcie2x1 {
+ 	pinctrl-names = "default";
+-	pinctrl-0 = <&pcie20_reset_pin>;
++	pinctrl-0 = <&m2_w_disable_pin>;
+ 	reset-gpios = <&gpio3 RK_PC1 GPIO_ACTIVE_HIGH>;
+ 	status = "okay";
+ };
+@@ -80,15 +82,21 @@
+ };
+ 
+ &pinctrl {
+-	gpio-leds {
+-		lan_led_pin: lan-led-pin {
+-			rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++	gpio-key {
++		key1_pin: key1-pin {
++			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
++	};
+ 
+-		power_led_pin: power-led-pin {
++	gpio-leds {
++		sys_led_pin: power-led-pin {
+ 			rockchip,pins = <3 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 
++		lan_led_pin: lan-led-pin {
++			rockchip,pins = <3 RK_PA3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
+ 		wan_led_pin: wan-led-pin {
+ 			rockchip,pins = <3 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+@@ -98,15 +106,9 @@
+ 		};
+ 	};
+ 
+-	pcie {
+-		pcie20_reset_pin: pcie20-reset-pin {
++	m2-pins {
++		m2_w_disable_pin: m2-w-disable-pin {
+ 			rockchip,pins = <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_up>;
+ 		};
+ 	};
+-
+-	rockchip-key {
+-		reset_button_pin: reset-button-pin {
+-			rockchip,pins = <0 RK_PB7 RK_FUNC_GPIO &pcfg_pull_up>;
+-		};
+-	};
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
++++ b/arch/arm64/boot/dts/rockchip/rk3568-nanopi-r5s.dts
+@@ -11,7 +11,7 @@
+ 
+ / {
+ 	model = "FriendlyElec NanoPi R5S";
+-	compatible = "friendlyarm,nanopi-r5s", "rockchip,rk3568";
++	compatible = "friendlyelec,nanopi-r5s", "rockchip,rk3568";
+ 
+ 	aliases {
+ 		ethernet0 = &gmac0;
+@@ -19,34 +19,34 @@
+ 
+ 	gpio-leds {
+ 		compatible = "gpio-leds";
+-		pinctrl-names = "default";
+-		pinctrl-0 = <&lan1_led_pin>, <&lan2_led_pin>, <&power_led_pin>, <&wan_led_pin>;
+ 
+-		led-lan1 {
+-			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_LAN;
+-			function-enumerator = <1>;
+-			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
++		sys_led: led-sys {
++			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
++			label = "red:power";
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&sys_led_pin>;
+ 		};
+ 
+-		led-lan2 {
+-			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_LAN;
+-			function-enumerator = <2>;
+-			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
++		wan_led: led-wan {
++			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
++			label = "green:wan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&wan_led_pin>;
+ 		};
+ 
+-		power_led: led-power {
+-			color = <LED_COLOR_ID_RED>;
+-			function = LED_FUNCTION_POWER;
+-			linux,default-trigger = "heartbeat";
+-			gpios = <&gpio4 RK_PD2 GPIO_ACTIVE_HIGH>;
++		lan1_led: led-lan1 {
++			gpios = <&gpio3 RK_PD6 GPIO_ACTIVE_HIGH>;
++			label = "green:lan1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan1_led_pin>;
+ 		};
+ 
+-		led-wan {
+-			color = <LED_COLOR_ID_GREEN>;
+-			function = LED_FUNCTION_WAN;
+-			gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
++		lan2_led: led-lan2 {
++			gpios = <&gpio3 RK_PD7 GPIO_ACTIVE_HIGH>;
++			label = "green:lan2";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan2_led_pin>;
+ 		};
+ 	};
+ };
+@@ -117,20 +117,21 @@
+ 	};
+ 
+ 	gpio-leds {
+-		lan1_led_pin: lan1-led-pin {
+-			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+ 
+-		lan2_led_pin: lan2-led-pin {
+-			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
+-		};
+-
+-		power_led_pin: power-led-pin {
++		sys_led_pin: sys-led-pin {
+ 			rockchip,pins = <4 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
+ 
+ 		wan_led_pin: wan-led-pin {
+ 			rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ 		};
++
++		lan1_led_pin: lan1-led-pin {
++			rockchip,pins = <3 RK_PD6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan2_led_pin: lan2-led-pin {
++			rockchip,pins = <3 RK_PD7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
+ 	};
+ };
diff --git a/target/linux/rockchip/patches-6.1/370-arm64-dts-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch b/target/linux/rockchip/patches-6.1/370-arm64-dts-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch
new file mode 100644
index 00000000000..cc570774765
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/370-arm64-dts-rockchip-add-FriendlyElec-NanoPi-R6C-R6S.patch
@@ -0,0 +1,802 @@
+From 24fd0083dc2fd9841f850bdf8b4a699152c702ab Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Tue, 30 May 2023 03:36:19 -0400
+Subject: [PATCH 370/383] arm64: dts: rockchip: add FriendlyElec NanoPi R6C/R6S
+
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   2 +
+ .../dts/rockchip/rk3588-nanopi6-common.dtsi   | 527 ++++++++++++++++++
+ .../boot/dts/rockchip/rk3588s-nanopi-r6c.dts  | 121 ++++
+ .../boot/dts/rockchip/rk3588s-nanopi-r6s.dts  | 121 ++++
+ 4 files changed, 771 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588-nanopi6-common.dtsi
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -101,4 +101,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ed
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588-nanopi6-common.dtsi
+@@ -0,0 +1,527 @@
++// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
++/*
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ *
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ *
++ */
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/usb/pd.h>
++#include "rk3588s.dtsi"
++
++/ {
++	model = "FriendlyElec boards based on Rockchip RK3588";
++	compatible = "friendlyelec,nanopi6",
++		     "rockchip,rk3588";
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc5v0_usb: vcc5v0-usb {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_usb";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_1v1_nldo_s3";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <1100000>;
++		regulator-max-microvolt = <1100000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB4 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sd_s0_pwr>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <3000000>;
++		regulator-min-microvolt = <3000000>;
++		regulator-name = "vcc_3v3_sd_s0";
++		vin-supply = <&vcc_3v3_s3>;
++	};
++
++	vcc_3v3_pcie20: vcc3v3-pcie20 {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc_3v3_pcie20";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_3v3_s3>;
++	};
++
++	vbus5v0_typec: vbus5v0-typec {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio1 RK_PD2 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&typec5v_pwren>;
++		regulator-name = "vbus5v0_typec";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	vcc5v0_host_20: vcc5v0-host-20 {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PB5 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&vcc5v0_host20_en>;
++		regulator-name = "vcc5v0_host_20";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++};
++
++&combphy0_ps {
++	status = "okay";
++};
++
++&combphy2_psu {
++	status = "okay";
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++	mem-supply = <&vdd_cpu_lit_mem_s0>;
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_big0_s0>;
++	mem-supply = <&vdd_cpu_big0_mem_s0>;
++};
++
++&cpu_b2 {
++	cpu-supply = <&vdd_cpu_big1_s0>;
++	mem-supply = <&vdd_cpu_big1_mem_s0>;
++};
++
++&i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0m2_xfer>;
++	status = "okay";
++
++	vdd_cpu_big0_s0: vdd_cpu_big0_mem_s0: regulator@42 {
++		compatible = "rockchip,rk8602";
++		reg = <0x42>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_big0_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <1050000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_cpu_big1_s0: vdd_cpu_big1_mem_s0: regulator@43 {
++		compatible = "rockchip,rk8603", "rockchip,rk8602";
++		reg = <0x43>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_big1_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <1050000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&spi2 {
++	status = "okay";
++	assigned-clocks = <&cru CLK_SPI2>;
++	assigned-clock-rates = <200000000>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++	num-cs = <1>;
++
++	rk806single: rk806single@0 {
++		compatible = "rockchip,rk806";
++		spi-max-frequency = <1000000>;
++		reg = <0x0>;
++
++		interrupt-parent = <&gpio0>;
++		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>, <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc5v0_sys>;
++		vcc6-supply = <&vcc5v0_sys>;
++		vcc7-supply = <&vcc5v0_sys>;
++		vcc8-supply = <&vcc5v0_sys>;
++		vcc9-supply = <&vcc5v0_sys>;
++		vcc10-supply = <&vcc5v0_sys>;
++		vcc11-supply = <&vcc_2v0_pldo_s3>;
++		vcc12-supply = <&vcc5v0_sys>;
++		vcc13-supply = <&vcc_1v1_nldo_s3>;
++		vcc14-supply = <&vcc_1v1_nldo_s3>;
++		vcca-supply = <&vcc5v0_sys>;
++
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		rk806_dvs1_null: dvs1-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs1_slp: dvs1-slp-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs1_pwrdn: dvs1-pwrdn-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs1_rst: dvs1-rst-pins {
++			pins = "gpio_pwrctrl1";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs2_null: dvs2-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs2_slp: dvs2-slp-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs2_pwrdn: dvs2-pwrdn-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs2_rst: dvs2-rst-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs2_dvs: dvs2-dvs-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun4";
++		};
++
++		rk806_dvs2_gpio: dvs2-gpio-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun5";
++		};
++
++		rk806_dvs3_null: dvs3-null-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs3_slp: dvs3-slp-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun1";
++		};
++
++		rk806_dvs3_pwrdn: dvs3-pwrdn-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun2";
++		};
++
++		rk806_dvs3_rst: dvs3-rst-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun3";
++		};
++
++		rk806_dvs3_dvs: dvs3-dvs-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun4";
++		};
++
++		rk806_dvs3_gpio: dvs3-gpio-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun5";
++		};
++
++		regulators {
++			vdd_cpu_lit_s0: vdd_cpu_lit_mem_s0: dcdc-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_lit_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_2v0_pldo_s3: dcdc-reg7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2000000>;
++				regulator-max-microvolt = <2000000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_2v0_pldo_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <2000000>;
++				};
++			};
++
++			vcc_3v3_s3: dcdc-reg8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-name = "vcc_3v3_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vcc_3v3_s0: pldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vcc_3v3_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd_s0: pldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vccio_sd_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&i2c6 {
++	status = "okay";
++
++	hym8563:hym8563@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-frequency = <32768>;
++		clock-output-names = "hym8563";
++		pinctrl-names = "default";
++		pinctrl-0 = <&rtc_int>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++		wakeup-source;
++	};
++};
++
++&gmac1 {
++	/* Use rgmii-rxid mode to disable rx delay inside Soc */
++	phy-mode = "rgmii-rxid";
++	clock_in_out = "output";
++
++	snps,no-vlhash;
++	snps,reset-gpio = <&gpio3 RK_PB7 GPIO_ACTIVE_LOW>;
++	snps,reset-active-low;
++	/* Reset time is 20ms, 100ms for rtl8211f */
++	snps,reset-delays-us = <0 20000 100000>;
++
++	pinctrl-names = "default";
++	pinctrl-0 = <&gmac1_miim
++		     &gmac1_tx_bus2
++		     &gmac1_rx_bus2
++		     &gmac1_rgmii_clk
++		     &gmac1_rgmii_bus>;
++
++	tx_delay = <0x42>;
++	/* rx_delay = <0x4f>; */
++
++	phy-handle = <&rgmii_phy1>;
++	status = "okay";
++};
++
++&mdio1 {
++	rgmii_phy1: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <1>;
++	};
++};
++
++&pcie2x1l1 {
++	reset-gpios = <&gpio1 RK_PA7 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc_3v3_pcie20>;
++	status = "okay";
++};
++
++&pcie2x1l2 {
++	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc_3v3_pcie20>;
++	status = "okay";
++};
++
++&pinctrl {
++	hym8563 {
++		rtc_int: rtc-int {
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	sdmmc {
++		sd_s0_pwr: sd-s0-pwr {
++			rockchip,pins = <4 RK_PB4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	usb {
++		typec5v_pwren: typec5v-pwren {
++			rockchip,pins = <1 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		usbc0_int: usbc0-int {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++};
++
++&saradc {
++	status = "okay";
++};
++
++&sdhci {
++	bus-width = <8>;
++	no-sdio;
++	no-sd;
++	non-removable;
++	cap-mmc-highspeed;
++	max-frequency = <200000000>;
++	mmc-hs200-1_8v;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	max-frequency = <150000000>;
++	no-sdio;
++	no-mmc;
++	pinctrl-names = "default";
++	pinctrl-0 = <&sdmmc_bus4 &sdmmc_clk &sdmmc_cmd &sdmmc_det>;
++	vmmc-supply = <&vcc_3v3_sd_s0>;
++	vqmmc-supply = <&vccio_sd_s0>;
++	status = "okay";
++};
++
++&tsadc {
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
++
++&u2phy2 {
++	status = "okay";
++};
++
++&u2phy3 {
++	status = "okay";
++};
++
++&u2phy2_host {
++	phy-supply = <&vcc5v0_host_20>;
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
++
++&u2phy0 {
++	status = "okay";
++};
++
++&usbdp_phy0 {
++	status = "okay";
++};
++
++&u2phy0_otg {
++	phy-supply = <&vbus5v0_typec>;
++	status = "okay";
++};
++
++&usbdp_phy0_u3 {
++	status = "okay";
++};
++
++&usbdrd3_0 {
++	status = "okay";
++};
++
++&usbdrd_dwc3_0 {
++	dr_mode = "otg";
++	extcon = <&u2phy0>;
++	status = "okay";
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c.dts
+@@ -0,0 +1,121 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ * Copyright (c) 2023, Marty Jones <mj8263788@gmail.com
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include "rk3588-nanopi6-common.dtsi"
++
++/ {
++	model = "FriendlyElec NanoPi R6C";
++	compatible = "friendlyelec,nanopi-r6c", "rockchip,rk3588";
++
++	aliases {
++		mmc0 = &sdmmc;
++		mmc1 = &sdhci;
++		ethernet0 = &gmac1;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gpio_keys: gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&key1_pin>;
++	};
++
++	gpio_leds: gpio-leds {
++		compatible = "gpio-leds";
++
++		sys_led: led-sys {
++			gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++			label = "red:sys";
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&sys_led_pin>;
++		};
++
++		wan_led: led-wan {
++			gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
++			label = "green:wan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&wan_led_pin>;
++		};
++
++		lan_led: led-lan {
++			gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
++			label = "green:lan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan1_led_pin>;
++		};
++
++		led1_led: led-led1 {
++			gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
++			label = "green:led1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&led1_led_pin>;
++		};
++	};
++};
++
++
++&pinctrl {
++	gpio-key {
++		key1_pin: key1-pin {
++			rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	gpio-leds {
++		sys_led_pin: sys-led-pin {
++			rockchip,pins =
++				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wan_led_pin: wan-led-pin {
++			rockchip,pins =
++				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan1_led_pin: lan1-led-pin {
++			rockchip,pins =
++				<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		led1_led_pin: led1-led-pin {
++			rockchip,pins =
++				<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_host20_en: vcc5v0-host20-en {
++			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&i2c6 {
++	clock-frequency = <200000>;
++	status = "okay";
++
++	eeprom@53 {
++		compatible = "microchip,24c02", "atmel,24c02";
++		reg = <0x53>;
++		#address-cells = <2>;
++		#size-cells = <0>;
++		pagesize = <16>;
++		size = <256>;
++
++		eui_48: eui-48@fa {
++			reg = <0xfa 0x06>;
++		};
++	};
++};
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6s.dts
+@@ -0,0 +1,121 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ * Copyright (c) 2023, Marty Jones <mj8263788@gmail.com
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include "rk3588-nanopi6-common.dtsi"
++
++/ {
++	model = "FriendlyElec NanoPi R6S";
++	compatible = "friendlyelec,nanopi-r6s", "rockchip,rk3588";
++
++	aliases {
++		mmc0 = &sdmmc;
++		mmc1 = &sdhci;
++		ethernet0 = &gmac1;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gpio_keys: gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&key1_pin>;
++	};
++
++	gpio_leds: gpio-leds {
++		compatible = "gpio-leds";
++
++		sys_led: led-sys {
++			gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++			label = "red:sys";
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&sys_led_pin>;
++		};
++
++		wan_led: led-wan {
++			gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
++			label = "green:wan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&wan_led_pin>;
++		};
++
++		lan_led: led-lan {
++			gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
++			label = "green:lan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan1_led_pin>;
++		};
++
++		lan2_led: led-lan2 {
++			gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
++			label = "green:lan1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan2_led_pin>;
++		};
++	};
++};
++
++
++&pinctrl {
++	gpio-key {
++		key1_pin: key1-pin {
++			rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	gpio-leds {
++		sys_led_pin: sys-led-pin {
++			rockchip,pins =
++				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wan_led_pin: wan-led-pin {
++			rockchip,pins =
++				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan1_led_pin: lan1-led-pin {
++			rockchip,pins =
++				<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan2_led_pin: lan2-led-pin {
++			rockchip,pins =
++				<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_host20_en: vcc5v0-host20-en {
++			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&i2c6 {
++	clock-frequency = <200000>;
++	status = "okay";
++
++	eeprom@53 {
++		compatible = "microchip,24c02", "atmel,24c02";
++		reg = <0x53>;
++		#address-cells = <2>;
++		#size-cells = <0>;
++		pagesize = <16>;
++		size = <256>;
++
++		eui_48: eui-48@fa {
++			reg = <0xfa 0x06>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/371-regulator-fan53555-Remove-unused-_SLEW_SHIFT-definit.patch b/target/linux/rockchip/patches-6.1/371-regulator-fan53555-Remove-unused-_SLEW_SHIFT-definit.patch
new file mode 100644
index 00000000000..95a097901b4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/371-regulator-fan53555-Remove-unused-_SLEW_SHIFT-definit.patch
@@ -0,0 +1,36 @@
+From eb7c8791d5a3795e949b260243dfd83f0479a514 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 6 Apr 2023 22:41:54 +0300
+Subject: [PATCH 371/383] regulator: fan53555: Remove unused *_SLEW_SHIFT
+ definitions
+
+Commit b61ac767db4d ("regulator: fan53555: Convert to use
+regulator_set_ramp_delay_regmap") removed the slew_shift member from
+struct fan53555_device_info, hence the {CTL,TCS}_SLEW_SHIFT definitions
+remained unused.  Drop them.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230406194158.963352-5-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/regulator/fan53555.c | 2 --
+ 1 file changed, 2 deletions(-)
+
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -49,7 +49,6 @@
+ /* Control bit definitions */
+ #define CTL_OUTPUT_DISCHG	(1 << 7)
+ #define CTL_SLEW_MASK		(0x7 << 4)
+-#define CTL_SLEW_SHIFT		4
+ #define CTL_RESET			(1 << 2)
+ #define CTL_MODE_VSEL0_MODE	BIT(0)
+ #define CTL_MODE_VSEL1_MODE	BIT(1)
+@@ -60,7 +59,6 @@
+ #define TCS_VSEL0_MODE		(1 << 7)
+ #define TCS_VSEL1_MODE		(1 << 6)
+ 
+-#define TCS_SLEW_SHIFT		3
+ #define TCS_SLEW_MASK		GENMASK(4, 3)
+ 
+ enum fan53555_vendor {
diff --git a/target/linux/rockchip/patches-6.1/372-regulator-fan53555-Make-use-of-the-bit-macros.patch b/target/linux/rockchip/patches-6.1/372-regulator-fan53555-Make-use-of-the-bit-macros.patch
new file mode 100644
index 00000000000..b350859653f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/372-regulator-fan53555-Make-use-of-the-bit-macros.patch
@@ -0,0 +1,53 @@
+From 01902ed242e817ab4a2ef9a56a632c3338c7c3ba Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 6 Apr 2023 22:41:55 +0300
+Subject: [PATCH 372/383] regulator: fan53555: Make use of the bit macros
+
+For consistency and improved clarity, use BIT() and GENMASK() macros for
+defining the bitfields inside the registers. No functional changes
+intended.
+
+While here, also fix DIE_{ID,REV} inconsistent indentation.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230406194158.963352-6-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/regulator/fan53555.c | 18 +++++++++---------
+ 1 file changed, 9 insertions(+), 9 deletions(-)
+
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -41,23 +41,23 @@
+ #define FAN53555_MONITOR	0x05
+ 
+ /* VSEL bit definitions */
+-#define VSEL_BUCK_EN	(1 << 7)
+-#define VSEL_MODE		(1 << 6)
++#define VSEL_BUCK_EN		BIT(7)
++#define VSEL_MODE		BIT(6)
+ /* Chip ID and Verison */
+-#define DIE_ID		0x0F	/* ID1 */
+-#define DIE_REV		0x0F	/* ID2 */
++#define DIE_ID			0x0F	/* ID1 */
++#define DIE_REV			0x0F	/* ID2 */
+ /* Control bit definitions */
+-#define CTL_OUTPUT_DISCHG	(1 << 7)
+-#define CTL_SLEW_MASK		(0x7 << 4)
+-#define CTL_RESET			(1 << 2)
++#define CTL_OUTPUT_DISCHG	BIT(7)
++#define CTL_SLEW_MASK		GENMASK(6, 4)
++#define CTL_RESET		BIT(2)
+ #define CTL_MODE_VSEL0_MODE	BIT(0)
+ #define CTL_MODE_VSEL1_MODE	BIT(1)
+ 
+ #define FAN53555_NVOLTAGES	64	/* Numbers of voltages */
+ #define FAN53526_NVOLTAGES	128
+ 
+-#define TCS_VSEL0_MODE		(1 << 7)
+-#define TCS_VSEL1_MODE		(1 << 6)
++#define TCS_VSEL0_MODE		BIT(7)
++#define TCS_VSEL1_MODE		BIT(6)
+ 
+ #define TCS_SLEW_MASK		GENMASK(4, 3)
+ 
diff --git a/target/linux/rockchip/patches-6.1/373-regulator-fan53555-Improve-vsel_mask-computation.patch b/target/linux/rockchip/patches-6.1/373-regulator-fan53555-Improve-vsel_mask-computation.patch
new file mode 100644
index 00000000000..84fbd9b047c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/373-regulator-fan53555-Improve-vsel_mask-computation.patch
@@ -0,0 +1,39 @@
+From 2ccdc4ccc73c99baa0d75b2ef83b204b4332d34d Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 6 Apr 2023 22:41:56 +0300
+Subject: [PATCH 373/383] regulator: fan53555: Improve vsel_mask computation
+
+In preparation for introducing support for additional regulators which
+do not use the maximum number of voltage selectors available for a given
+mask, improve the mask computation formula by using fls().
+
+Note fls() requires the bitops header, hence include it explicitly and
+drop bits.h which is already pulled by bitops.h.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230406194158.963352-7-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/regulator/fan53555.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -8,7 +8,7 @@
+ // Copyright (c) 2012 Marvell Technology Ltd.
+ // Yunfan Zhang <yfzhang@marvell.com>
+ 
+-#include <linux/bits.h>
++#include <linux/bitops.h>
+ #include <linux/err.h>
+ #include <linux/i2c.h>
+ #include <linux/module.h>
+@@ -486,7 +486,7 @@ static int fan53555_regulator_register(s
+ 	rdesc->min_uV = di->vsel_min;
+ 	rdesc->uV_step = di->vsel_step;
+ 	rdesc->vsel_reg = di->vol_reg;
+-	rdesc->vsel_mask = di->vsel_count - 1;
++	rdesc->vsel_mask = BIT(fls(di->vsel_count - 1)) - 1;
+ 	rdesc->ramp_reg = di->slew_reg;
+ 	rdesc->ramp_mask = di->slew_mask;
+ 	rdesc->ramp_delay_table = di->ramp_delay_table;
diff --git a/target/linux/rockchip/patches-6.1/374-regulator-fan53555-Use-dev_err_probe.patch b/target/linux/rockchip/patches-6.1/374-regulator-fan53555-Use-dev_err_probe.patch
new file mode 100644
index 00000000000..6e523b6fa48
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/374-regulator-fan53555-Use-dev_err_probe.patch
@@ -0,0 +1,106 @@
+From 5eea6d90de5e639c35ac794859dbd8214e9b276d Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 6 Apr 2023 22:41:57 +0300
+Subject: [PATCH 374/383] regulator: fan53555: Use dev_err_probe
+
+Use dev_err_probe() instead of dev_err() in the probe function, which
+ensures the error code is always printed and, additionally, simplifies
+the code a bit.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230406194158.963352-8-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/regulator/fan53555.c | 47 ++++++++++++++++--------------------
+ 1 file changed, 21 insertions(+), 26 deletions(-)
+
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -568,10 +568,9 @@ static int fan53555_regulator_probe(stru
+ 	if (!pdata)
+ 		pdata = fan53555_parse_dt(&client->dev, np, &di->desc);
+ 
+-	if (!pdata || !pdata->regulator) {
+-		dev_err(&client->dev, "Platform data not found!\n");
+-		return -ENODEV;
+-	}
++	if (!pdata || !pdata->regulator)
++		return dev_err_probe(&client->dev, -ENODEV,
++				     "Platform data not found!\n");
+ 
+ 	di->regulator = pdata->regulator;
+ 	if (client->dev.of_node) {
+@@ -580,10 +579,9 @@ static int fan53555_regulator_probe(stru
+ 	} else {
+ 		/* if no ramp constraint set, get the pdata ramp_delay */
+ 		if (!di->regulator->constraints.ramp_delay) {
+-			if (pdata->slew_rate >= ARRAY_SIZE(slew_rates)) {
+-				dev_err(&client->dev, "Invalid slew_rate\n");
+-				return -EINVAL;
+-			}
++			if (pdata->slew_rate >= ARRAY_SIZE(slew_rates))
++				return dev_err_probe(&client->dev, -EINVAL,
++						     "Invalid slew_rate\n");
+ 
+ 			di->regulator->constraints.ramp_delay
+ 					= slew_rates[pdata->slew_rate];
+@@ -593,34 +591,31 @@ static int fan53555_regulator_probe(stru
+ 	}
+ 
+ 	regmap = devm_regmap_init_i2c(client, &fan53555_regmap_config);
+-	if (IS_ERR(regmap)) {
+-		dev_err(&client->dev, "Failed to allocate regmap!\n");
+-		return PTR_ERR(regmap);
+-	}
++	if (IS_ERR(regmap))
++		return dev_err_probe(&client->dev, PTR_ERR(regmap),
++				     "Failed to allocate regmap!\n");
++
+ 	di->dev = &client->dev;
+ 	i2c_set_clientdata(client, di);
+ 	/* Get chip ID */
+ 	ret = regmap_read(regmap, FAN53555_ID1, &val);
+-	if (ret < 0) {
+-		dev_err(&client->dev, "Failed to get chip ID!\n");
+-		return ret;
+-	}
++	if (ret < 0)
++		return dev_err_probe(&client->dev, ret, "Failed to get chip ID!\n");
++
+ 	di->chip_id = val & DIE_ID;
+ 	/* Get chip revision */
+ 	ret = regmap_read(regmap, FAN53555_ID2, &val);
+-	if (ret < 0) {
+-		dev_err(&client->dev, "Failed to get chip Rev!\n");
+-		return ret;
+-	}
++	if (ret < 0)
++		return dev_err_probe(&client->dev, ret, "Failed to get chip Rev!\n");
++
+ 	di->chip_rev = val & DIE_REV;
+ 	dev_info(&client->dev, "FAN53555 Option[%d] Rev[%d] Detected!\n",
+ 				di->chip_id, di->chip_rev);
+ 	/* Device init */
+ 	ret = fan53555_device_setup(di, pdata);
+-	if (ret < 0) {
+-		dev_err(&client->dev, "Failed to setup device!\n");
+-		return ret;
+-	}
++	if (ret < 0)
++		return dev_err_probe(&client->dev, ret, "Failed to setup device!\n");
++
+ 	/* Register regulator */
+ 	config.dev = di->dev;
+ 	config.init_data = di->regulator;
+@@ -630,9 +625,9 @@ static int fan53555_regulator_probe(stru
+ 
+ 	ret = fan53555_regulator_register(di, &config);
+ 	if (ret < 0)
+-		dev_err(&client->dev, "Failed to register regulator!\n");
+-	return ret;
++		dev_err_probe(&client->dev, ret, "Failed to register regulator!\n");
+ 
++	return ret;
+ }
+ 
+ static const struct i2c_device_id fan53555_id[] = {
diff --git a/target/linux/rockchip/patches-6.1/375-regulator-fan53555-Add-support-for-RK860X.patch b/target/linux/rockchip/patches-6.1/375-regulator-fan53555-Add-support-for-RK860X.patch
new file mode 100644
index 00000000000..b5358d482c3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/375-regulator-fan53555-Add-support-for-RK860X.patch
@@ -0,0 +1,263 @@
+From 28972868fda7085871e2680f0a71325c8481f00a Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Thu, 6 Apr 2023 22:41:58 +0300
+Subject: [PATCH 375/383] regulator: fan53555: Add support for RK860X
+
+Extend the existing fan53555 driver to support the Rockchip RK860X
+regulators.
+
+RK8600/RK8601 are pretty similar to the FAN53555 regulators.
+
+RK8602/RK8603 are a bit different, having a wider output voltage
+selection range, from 0.5 V to 1.5 V in 6.25 mV steps. They also use
+additional VSEL0/VSEL1 registers for the voltage selector, but the
+enable and mode bits are still located in the original FAN53555 specific
+VSEL0/VSEL1 registers.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
+Link: https://lore.kernel.org/r/20230406194158.963352-9-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ drivers/regulator/fan53555.c | 121 ++++++++++++++++++++++++++++++++++-
+ 1 file changed, 118 insertions(+), 3 deletions(-)
+
+--- a/drivers/regulator/fan53555.c
++++ b/drivers/regulator/fan53555.c
+@@ -26,6 +26,9 @@
+ #define FAN53555_VSEL0		0x00
+ #define FAN53555_VSEL1		0x01
+ 
++#define RK8602_VSEL0		0x06
++#define RK8602_VSEL1		0x07
++
+ #define TCS4525_VSEL0		0x11
+ #define TCS4525_VSEL1		0x10
+ #define TCS4525_TIME		0x13
+@@ -55,6 +58,7 @@
+ 
+ #define FAN53555_NVOLTAGES	64	/* Numbers of voltages */
+ #define FAN53526_NVOLTAGES	128
++#define RK8602_NVOLTAGES	160
+ 
+ #define TCS_VSEL0_MODE		BIT(7)
+ #define TCS_VSEL1_MODE		BIT(6)
+@@ -64,6 +68,8 @@
+ enum fan53555_vendor {
+ 	FAN53526_VENDOR_FAIRCHILD = 0,
+ 	FAN53555_VENDOR_FAIRCHILD,
++	FAN53555_VENDOR_ROCKCHIP,	/* RK8600, RK8601 */
++	RK8602_VENDOR_ROCKCHIP,		/* RK8602, RK8603 */
+ 	FAN53555_VENDOR_SILERGY,
+ 	FAN53526_VENDOR_TCS,
+ };
+@@ -88,6 +94,14 @@ enum {
+ };
+ 
+ enum {
++	RK8600_CHIP_ID_08 = 8,		/* RK8600, RK8601 */
++};
++
++enum {
++	RK8602_CHIP_ID_10 = 10,		/* RK8602, RK8603 */
++};
++
++enum {
+ 	TCS4525_CHIP_ID_12 = 12,
+ };
+ 
+@@ -117,6 +131,8 @@ struct fan53555_device_info {
+ 	/* Voltage setting register */
+ 	unsigned int vol_reg;
+ 	unsigned int sleep_reg;
++	unsigned int en_reg;
++	unsigned int sleep_en_reg;
+ 	/* Voltage range and step(linear) */
+ 	unsigned int vsel_min;
+ 	unsigned int vsel_step;
+@@ -159,7 +175,7 @@ static int fan53555_set_suspend_enable(s
+ {
+ 	struct fan53555_device_info *di = rdev_get_drvdata(rdev);
+ 
+-	return regmap_update_bits(rdev->regmap, di->sleep_reg,
++	return regmap_update_bits(rdev->regmap, di->sleep_en_reg,
+ 				  VSEL_BUCK_EN, VSEL_BUCK_EN);
+ }
+ 
+@@ -167,7 +183,7 @@ static int fan53555_set_suspend_disable(
+ {
+ 	struct fan53555_device_info *di = rdev_get_drvdata(rdev);
+ 
+-	return regmap_update_bits(rdev->regmap, di->sleep_reg,
++	return regmap_update_bits(rdev->regmap, di->sleep_en_reg,
+ 				  VSEL_BUCK_EN, 0);
+ }
+ 
+@@ -317,6 +333,50 @@ static int fan53555_voltages_setup_fairc
+ 	return 0;
+ }
+ 
++static int fan53555_voltages_setup_rockchip(struct fan53555_device_info *di)
++{
++	/* Init voltage range and step */
++	switch (di->chip_id) {
++	case RK8600_CHIP_ID_08:
++		di->vsel_min = 712500;
++		di->vsel_step = 12500;
++		break;
++	default:
++		dev_err(di->dev,
++			"Chip ID %d not supported!\n", di->chip_id);
++		return -EINVAL;
++	}
++	di->slew_reg = FAN53555_CONTROL;
++	di->slew_mask = CTL_SLEW_MASK;
++	di->ramp_delay_table = slew_rates;
++	di->n_ramp_values = ARRAY_SIZE(slew_rates);
++	di->vsel_count = FAN53555_NVOLTAGES;
++
++	return 0;
++}
++
++static int rk8602_voltages_setup_rockchip(struct fan53555_device_info *di)
++{
++	/* Init voltage range and step */
++	switch (di->chip_id) {
++	case RK8602_CHIP_ID_10:
++		di->vsel_min = 500000;
++		di->vsel_step = 6250;
++		break;
++	default:
++		dev_err(di->dev,
++			"Chip ID %d not supported!\n", di->chip_id);
++		return -EINVAL;
++	}
++	di->slew_reg = FAN53555_CONTROL;
++	di->slew_mask = CTL_SLEW_MASK;
++	di->ramp_delay_table = slew_rates;
++	di->n_ramp_values = ARRAY_SIZE(slew_rates);
++	di->vsel_count = RK8602_NVOLTAGES;
++
++	return 0;
++}
++
+ static int fan53555_voltages_setup_silergy(struct fan53555_device_info *di)
+ {
+ 	/* Init voltage range and step */
+@@ -377,6 +437,7 @@ static int fan53555_device_setup(struct
+ 	switch (di->vendor) {
+ 	case FAN53526_VENDOR_FAIRCHILD:
+ 	case FAN53555_VENDOR_FAIRCHILD:
++	case FAN53555_VENDOR_ROCKCHIP:
+ 	case FAN53555_VENDOR_SILERGY:
+ 		switch (pdata->sleep_vsel_id) {
+ 		case FAN53555_VSEL_ID_0:
+@@ -391,6 +452,27 @@ static int fan53555_device_setup(struct
+ 			dev_err(di->dev, "Invalid VSEL ID!\n");
+ 			return -EINVAL;
+ 		}
++		di->sleep_en_reg = di->sleep_reg;
++		di->en_reg = di->vol_reg;
++		break;
++	case RK8602_VENDOR_ROCKCHIP:
++		switch (pdata->sleep_vsel_id) {
++		case FAN53555_VSEL_ID_0:
++			di->sleep_reg = RK8602_VSEL0;
++			di->vol_reg = RK8602_VSEL1;
++			di->sleep_en_reg = FAN53555_VSEL0;
++			di->en_reg = FAN53555_VSEL1;
++			break;
++		case FAN53555_VSEL_ID_1:
++			di->sleep_reg = RK8602_VSEL1;
++			di->vol_reg = RK8602_VSEL0;
++			di->sleep_en_reg = FAN53555_VSEL1;
++			di->en_reg = FAN53555_VSEL0;
++			break;
++		default:
++			dev_err(di->dev, "Invalid VSEL ID!\n");
++			return -EINVAL;
++		}
+ 		break;
+ 	case FAN53526_VENDOR_TCS:
+ 		switch (pdata->sleep_vsel_id) {
+@@ -406,6 +488,8 @@ static int fan53555_device_setup(struct
+ 			dev_err(di->dev, "Invalid VSEL ID!\n");
+ 			return -EINVAL;
+ 		}
++		di->sleep_en_reg = di->sleep_reg;
++		di->en_reg = di->vol_reg;
+ 		break;
+ 	default:
+ 		dev_err(di->dev, "vendor %d not supported!\n", di->vendor);
+@@ -427,10 +511,23 @@ static int fan53555_device_setup(struct
+ 		}
+ 		break;
+ 	case FAN53555_VENDOR_FAIRCHILD:
++	case FAN53555_VENDOR_ROCKCHIP:
+ 	case FAN53555_VENDOR_SILERGY:
+ 		di->mode_reg = di->vol_reg;
+ 		di->mode_mask = VSEL_MODE;
+ 		break;
++	case RK8602_VENDOR_ROCKCHIP:
++		di->mode_mask = VSEL_MODE;
++
++		switch (pdata->sleep_vsel_id) {
++		case FAN53555_VSEL_ID_0:
++			di->mode_reg = FAN53555_VSEL1;
++			break;
++		case FAN53555_VSEL_ID_1:
++			di->mode_reg = FAN53555_VSEL0;
++			break;
++		}
++		break;
+ 	case FAN53526_VENDOR_TCS:
+ 		di->mode_reg = TCS4525_COMMAND;
+ 
+@@ -456,6 +553,12 @@ static int fan53555_device_setup(struct
+ 	case FAN53555_VENDOR_FAIRCHILD:
+ 		ret = fan53555_voltages_setup_fairchild(di);
+ 		break;
++	case FAN53555_VENDOR_ROCKCHIP:
++		ret = fan53555_voltages_setup_rockchip(di);
++		break;
++	case RK8602_VENDOR_ROCKCHIP:
++		ret = rk8602_voltages_setup_rockchip(di);
++		break;
+ 	case FAN53555_VENDOR_SILERGY:
+ 		ret = fan53555_voltages_setup_silergy(di);
+ 		break;
+@@ -481,7 +584,7 @@ static int fan53555_regulator_register(s
+ 	rdesc->ops = &fan53555_regulator_ops;
+ 	rdesc->type = REGULATOR_VOLTAGE;
+ 	rdesc->n_voltages = di->vsel_count;
+-	rdesc->enable_reg = di->vol_reg;
++	rdesc->enable_reg = di->en_reg;
+ 	rdesc->enable_mask = VSEL_BUCK_EN;
+ 	rdesc->min_uV = di->vsel_min;
+ 	rdesc->uV_step = di->vsel_step;
+@@ -532,6 +635,12 @@ static const struct of_device_id __maybe
+ 		.compatible = "fcs,fan53555",
+ 		.data = (void *)FAN53555_VENDOR_FAIRCHILD
+ 	}, {
++		.compatible = "rockchip,rk8600",
++		.data = (void *)FAN53555_VENDOR_ROCKCHIP
++	}, {
++		.compatible = "rockchip,rk8602",
++		.data = (void *)RK8602_VENDOR_ROCKCHIP
++	}, {
+ 		.compatible = "silergy,syr827",
+ 		.data = (void *)FAN53555_VENDOR_SILERGY,
+ 	}, {
+@@ -638,6 +747,12 @@ static const struct i2c_device_id fan535
+ 		.name = "fan53555",
+ 		.driver_data = FAN53555_VENDOR_FAIRCHILD
+ 	}, {
++		.name = "rk8600",
++		.driver_data = FAN53555_VENDOR_ROCKCHIP
++	}, {
++		.name = "rk8602",
++		.driver_data = RK8602_VENDOR_ROCKCHIP
++	}, {
+ 		.name = "syr827",
+ 		.driver_data = FAN53555_VENDOR_SILERGY
+ 	}, {
diff --git a/target/linux/rockchip/patches-6.1/376-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch b/target/linux/rockchip/patches-6.1/376-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch
new file mode 100644
index 00000000000..2720cacac07
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/376-ASoC-rockchip-i2s_tdm-Make-the-grf-property-optional.patch
@@ -0,0 +1,56 @@
+From 47569184277746f7770ef28a3e7af1995c33ec4c Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Tue, 25 Oct 2022 14:41:30 +0200
+Subject: [PATCH 376/383] ASoC: rockchip: i2s_tdm: Make the grf property
+ optional
+
+Only IO Multiplex and two TRCM modes need access to the GRF, so
+making it a hard requirement is not a wise idea, as it complicates
+support for newer SoCs which do not do these things.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221025124132.399729-3-frattaroli.nicolas@gmail.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ sound/soc/rockchip/rockchip_i2s_tdm.c | 16 ++++++++++++----
+ 1 file changed, 12 insertions(+), 4 deletions(-)
+
+--- a/sound/soc/rockchip/rockchip_i2s_tdm.c
++++ b/sound/soc/rockchip/rockchip_i2s_tdm.c
+@@ -756,6 +756,12 @@ static int rockchip_i2s_io_multiplex(str
+ 	if (!i2s_tdm->io_multiplex)
+ 		return 0;
+ 
++	if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
++		dev_err(i2s_tdm->dev,
++			"io multiplex not supported for this device\n");
++		return -EINVAL;
++	}
++
+ 	if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
+ 		struct snd_pcm_str *playback_str =
+ 			&substream->pcm->streams[SNDRV_PCM_STREAM_PLAYBACK];
+@@ -1222,6 +1228,12 @@ static int common_soc_init(struct device
+ 	if (trcm == TRCM_TXRX)
+ 		return 0;
+ 
++	if (IS_ERR_OR_NULL(i2s_tdm->grf)) {
++		dev_err(i2s_tdm->dev,
++			"no grf present but non-txrx TRCM specified\n");
++		return -EINVAL;
++	}
++
+ 	for (i = 0; i < i2s_tdm->soc_data->config_count; i++) {
+ 		if (addr != configs[i].addr)
+ 			continue;
+@@ -1568,10 +1580,6 @@ static int rockchip_i2s_tdm_probe(struct
+ 		return ret;
+ 
+ 	i2s_tdm->grf = syscon_regmap_lookup_by_phandle(node, "rockchip,grf");
+-	if (IS_ERR(i2s_tdm->grf))
+-		return dev_err_probe(i2s_tdm->dev, PTR_ERR(i2s_tdm->grf),
+-				     "Error in rockchip,grf\n");
+-
+ 	i2s_tdm->tx_reset = devm_reset_control_get_optional_exclusive(&pdev->dev,
+ 								      "tx-m");
+ 	if (IS_ERR(i2s_tdm->tx_reset)) {
diff --git a/target/linux/rockchip/patches-6.1/377-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/377-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch
new file mode 100644
index 00000000000..b5d81987591
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/377-ASoC-rockchip-i2s_tdm-Add-support-for-RK3588.patch
@@ -0,0 +1,33 @@
+From 9f56deeeaef6355230dae01a8a05b060e6c40e01 Mon Sep 17 00:00:00 2001
+From: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Date: Tue, 25 Oct 2022 14:41:32 +0200
+Subject: [PATCH 377/383] ASoC: rockchip: i2s_tdm: Add support for RK3588
+
+This adds support for the RK3588 SoC to the I2S/TDM driver.
+
+Signed-off-by: Nicolas Frattaroli <frattaroli.nicolas@gmail.com>
+Link: https://lore.kernel.org/r/20221025124132.399729-5-frattaroli.nicolas@gmail.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ sound/soc/rockchip/rockchip_i2s_tdm.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/sound/soc/rockchip/rockchip_i2s_tdm.c
++++ b/sound/soc/rockchip/rockchip_i2s_tdm.c
+@@ -1318,6 +1318,7 @@ static const struct of_device_id rockchi
+ 	{ .compatible = "rockchip,rk1808-i2s-tdm", .data = &rk1808_i2s_soc_data },
+ 	{ .compatible = "rockchip,rk3308-i2s-tdm", .data = &rk3308_i2s_soc_data },
+ 	{ .compatible = "rockchip,rk3568-i2s-tdm", .data = &rk3568_i2s_soc_data },
++	{ .compatible = "rockchip,rk3588-i2s-tdm" },
+ 	{ .compatible = "rockchip,rv1126-i2s-tdm", .data = &rv1126_i2s_soc_data },
+ 	{},
+ };
+@@ -1556,7 +1557,7 @@ static int rockchip_i2s_tdm_probe(struct
+ 	i2s_tdm->dev = &pdev->dev;
+ 
+ 	of_id = of_match_device(rockchip_i2s_tdm_match, &pdev->dev);
+-	if (!of_id || !of_id->data)
++	if (!of_id)
+ 		return -EINVAL;
+ 
+ 	spin_lock_init(&i2s_tdm->lock);
diff --git a/target/linux/rockchip/patches-6.1/378-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch b/target/linux/rockchip/patches-6.1/378-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch
new file mode 100644
index 00000000000..29828bb24c2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/378-ASoC-rockchip-i2s-Add-compatible-for-RK3588.patch
@@ -0,0 +1,25 @@
+From 1f3b752958b2ab117896205d080c0d574645b5cf Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Wed, 15 Mar 2023 13:48:03 +0200
+Subject: [PATCH 378/383] ASoC: rockchip: i2s: Add compatible for RK3588
+
+The Rockchip I2S driver supports the RK3588/RK3588S SoCs, hence add the
+corresponding compatible string.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Link: https://lore.kernel.org/r/20230315114806.3819515-9-cristian.ciocaltea@collabora.com
+Signed-off-by: Mark Brown <broonie@kernel.org>
+---
+ sound/soc/rockchip/rockchip_i2s.c | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/sound/soc/rockchip/rockchip_i2s.c
++++ b/sound/soc/rockchip/rockchip_i2s.c
+@@ -659,6 +659,7 @@ static const struct of_device_id rockchi
+ 	{ .compatible = "rockchip,rk3366-i2s", },
+ 	{ .compatible = "rockchip,rk3368-i2s", },
+ 	{ .compatible = "rockchip,rk3399-i2s", .data = &rk3399_i2s_pins },
++	{ .compatible = "rockchip,rk3588-i2s", },
+ 	{ .compatible = "rockchip,rv1126-i2s", },
+ 	{},
+ };
diff --git a/target/linux/rockchip/patches-6.1/384-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-em.patch b/target/linux/rockchip/patches-6.1/384-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-em.patch
new file mode 100644
index 00000000000..cbd5df17247
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/384-arm64-dts-rockchip-add-default-pinctrl-for-rk3588-em.patch
@@ -0,0 +1,26 @@
+From 9245f96ff6940e531c5e145b6b72db7be26fa8ec Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Wed, 31 May 2023 11:12:16 -0500
+Subject: [PATCH 384/414] arm64: dts: rockchip: add default pinctrl for rk3588
+ emmc
+
+Add a default pinctrl definition for the rk3588 emmc.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -2011,6 +2011,9 @@
+ 			 <&cru TMCLK_EMMC>;
+ 		clock-names = "core", "bus", "axi", "block", "timer";
+ 		max-frequency = <200000000>;
++		pinctrl-0 = <&emmc_rstnout>, <&emmc_bus8>, <&emmc_clk>,
++			    <&emmc_cmd>, <&emmc_data_strobe>;
++		pinctrl-names = "default";
+ 		resets = <&cru SRST_C_EMMC>, <&cru SRST_H_EMMC>,
+ 			 <&cru SRST_A_EMMC>, <&cru SRST_B_EMMC>,
+ 			 <&cru SRST_T_EMMC>;
diff --git a/target/linux/rockchip/patches-6.1/385-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch b/target/linux/rockchip/patches-6.1/385-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch
new file mode 100644
index 00000000000..7f829d6571b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/385-arm64-dts-rockchip-Add-sdio-node-to-rk3588.patch
@@ -0,0 +1,37 @@
+From 58b9e2838dc57511c75fbe3d9759da082a63a6b3 Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Wed, 31 May 2023 11:12:17 -0500
+Subject: [PATCH 385/414] arm64: dts: rockchip: Add sdio node to rk3588
+
+Add SDIO node for rk3588/rk3588s.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 15 +++++++++++++++
+ 1 file changed, 15 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -2000,6 +2000,21 @@
+ 		status = "disabled";
+ 	};
+ 
++	sdio: mmc@fe2d0000 {
++		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
++		reg = <0x00 0xfe2d0000 0x00 0x4000>;
++		interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru HCLK_SDIO>, <&cru CCLK_SRC_SDIO>,
++			 <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
++		clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
++		fifo-depth = <0x100>;
++		max-frequency = <200000000>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&sdiom1_pins>;
++		power-domains = <&power RK3588_PD_SDIO>;
++		status = "disabled";
++	};
++
+ 	sdhci: mmc@fe2e0000 {
+ 		compatible = "rockchip,rk3588-dwcmshc";
+ 		reg = <0x0 0xfe2e0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-6.1/386-dt-bindings-vendor-prefixes-add-Indiedroid.patch b/target/linux/rockchip/patches-6.1/386-dt-bindings-vendor-prefixes-add-Indiedroid.patch
new file mode 100644
index 00000000000..67dc9b3d557
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/386-dt-bindings-vendor-prefixes-add-Indiedroid.patch
@@ -0,0 +1,25 @@
+From 64d7facfd7dab1204ecc7258262f403a3c547a0f Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Wed, 31 May 2023 11:12:18 -0500
+Subject: [PATCH 386/414] dt-bindings: vendor-prefixes: add Indiedroid
+
+Indiedroid is a sub-brand of Ameridroid for their line of single board
+computers.
+https://indiedroid.us/
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+---
+ Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+@@ -591,6 +591,8 @@ patternProperties:
+     description: Integrated Micro-Electronics Inc.
+   "^incircuit,.*":
+     description: In-Circuit GmbH
++  "^indiedroid,.*":
++    description: Indiedroid
+   "^inet-tek,.*":
+     description: Shenzhen iNet Mobile Internet Technology Co., Ltd
+   "^infineon,.*":
diff --git a/target/linux/rockchip/patches-6.1/387-dt-bindings-arm-rockchip-Add-Indiedroid-Nova.patch b/target/linux/rockchip/patches-6.1/387-dt-bindings-arm-rockchip-Add-Indiedroid-Nova.patch
new file mode 100644
index 00000000000..b532569ed01
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/387-dt-bindings-arm-rockchip-Add-Indiedroid-Nova.patch
@@ -0,0 +1,27 @@
+From 9f29a9ac74d2c69a8b2a62abdc392f14a0e3488b Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Wed, 31 May 2023 11:12:19 -0500
+Subject: [PATCH 387/414] dt-bindings: arm: rockchip: Add Indiedroid Nova
+
+Add Indiedroid Nova, an rk3588s based single board computer.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+---
+ Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
+ 1 file changed, 5 insertions(+)
+
+--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
++++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
+@@ -554,6 +554,11 @@ properties:
+               - khadas,edge-v
+           - const: rockchip,rk3399
+ 
++      - description: Indiedroid Nova SBC
++        items:
++          - const: indiedroid,nova
++          - const: rockchip,rk3588s
++
+       - description: Khadas Edge2 series boards
+         items:
+           - const: khadas,edge2
diff --git a/target/linux/rockchip/patches-6.1/388-arm64-dts-rockchip-Add-Indiedroid-Nova-board.patch b/target/linux/rockchip/patches-6.1/388-arm64-dts-rockchip-Add-Indiedroid-Nova-board.patch
new file mode 100644
index 00000000000..777203800d4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/388-arm64-dts-rockchip-Add-Indiedroid-Nova-board.patch
@@ -0,0 +1,822 @@
+From 026f1bad4abdd244046af0a192cfcab6c5dcdb0a Mon Sep 17 00:00:00 2001
+From: Chris Morgan <macromorgan@hotmail.com>
+Date: Wed, 31 May 2023 11:12:20 -0500
+Subject: [PATCH 388/414] arm64: dts: rockchip: Add Indiedroid Nova board
+
+The Indiedroid Nova is an SBC from a sub-brand of Ameridroid that
+includes the following hardware:
+
+ - A 40-pin GPIO header
+ - 2 USB-A 3.0 ports
+ - 2 USB-A 2.0 ports
+ - A USB-C 2.0 OTG port (used for USB power delivery)
+ - A USB-C 3.0 port that can do display port output.
+ - A Micro HDMI 2.1 port.
+ - A 1GB ethernet port.
+ - An RT8821CS based WiFi/Bluetooth module.
+ - A user replaceable eMMC module.
+ - An SDMMC card slot.
+ - A MIPI DSI connector.
+ - A MIPI CSI connector.
+ - A 3.5mm TRRS audio jack with microphone input.
+ - An 2 pin socket for an RTC battery.
+ - A 4 pin socket for a debug port.
+ - A power button (connected to PMIC), a reset button (connected to SoC
+   reset), a boot button, and a recovery button (both connected to the
+   ADC).
+ - 4GB, 8GB, or 16GB of system RAM.
+
+This initial devicetree includes support for the WiFi, bluetooth,
+analog audio out/in, SDMMC, eMMC, RTC, UART debugging, and has
+the regulator values from the schematics. ADC, graphics output, GPU,
+USB, and wired ethernet are still pending additional upstream changes.
+
+Analog audio will require changes to handle a difference between the
+requested clock frequency of 12288000 and the actual clock freqency
+of 12287999 before it will work properly. This will be done in a
+subsequent patch series.
+
+Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3588s-indiedroid-nova.dts  | 764 ++++++++++++++++++
+ 2 files changed, 765 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -100,6 +100,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-ed
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-edgeble-neu6b-io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588-rock-5b.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-indiedroid-nova.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-indiedroid-nova.dts
+@@ -0,0 +1,764 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include <dt-bindings/usb/pd.h>
++#include "rk3588s.dtsi"
++
++/ {
++	model = "Indiedroid Nova";
++	compatible = "indiedroid,nova", "rockchip,rk3588s";
++
++	aliases {
++		mmc0 = &sdhci;
++		mmc1 = &sdmmc;
++		mmc2 = &sdio;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	sdio_pwrseq: sdio-pwrseq {
++		compatible = "mmc-pwrseq-simple";
++		clock-names = "ext_clock";
++		clocks = <&rtc_hym8563>;
++		pinctrl-0 = <&wifi_enable_h>;
++		pinctrl-names = "default";
++		post-power-on-delay-ms = <200>;
++		reset-gpios = <&gpio0 RK_PC7 GPIO_ACTIVE_LOW>;
++	};
++
++	sound {
++		compatible = "audio-graph-card";
++		label = "rockchip,es8388-codec";
++		widgets = "Microphone", "Mic Jack",
++			  "Headphone", "Headphones";
++		routing = "LINPUT2", "Mic Jack",
++			  "Headphones", "LOUT1",
++			  "Headphones", "ROUT1";
++		dais = <&i2s0_8ch_p0>;
++	};
++
++	vbus5v0_typec: vbus5v0-typec {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio4 RK_PA5 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&typec5v_pwren>;
++		pinctrl-names = "default";
++		regulator-name = "vbus5v0_typec";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_usb>;
++	};
++
++	vcc_1v1_nldo_s3: vcc-1v1-nldo-s3 {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <1100000>;
++		regulator-min-microvolt = <1100000>;
++		regulator-name = "vcc_1v1_nldo_s3";
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	/* Regulator is enabled whenever vcc_1v8_s0 is above 1.6v */
++	vcc_3v3_s0: vcc-3v3-s0 {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <3300000>;
++		regulator-min-microvolt = <3300000>;
++		regulator-name = "vcc_3v3_s0";
++		vin-supply = <&vcc_3v3_s3>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vcc5v0_sys: vcc5v0-sys {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <5000000>;
++		regulator-min-microvolt = <5000000>;
++		regulator-name = "vcc5v0_sys";
++	};
++
++	vcc5v0_usb: vcc5v0-usb {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <5000000>;
++		regulator-min-microvolt = <5000000>;
++		regulator-name = "vcc5v0_usb";
++		vin-supply = <&vcc5v0_usbdcin>;
++	};
++
++	vcc5v0_usbdcin: vcc5v0-usbdcin {
++		compatible = "regulator-fixed";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <5000000>;
++		regulator-min-microvolt = <5000000>;
++		regulator-name = "vcc5v0_usbdcin";
++	};
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_b0{
++	cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1{
++	cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2{
++	cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3{
++	cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++/*
++ * Add labels for each GPIO pin exposed on the 40 pin header. Note that
++ * voltage of each GPIO pin could be either 3.3v or 1.8v (as noted by
++ * label).
++ */
++&gpio0 {
++	gpio-line-names = /* GPIO0 A0-A7 */
++			  "", "", "", "",
++			  "", "", "", "",
++			  /* GPIO0 B0-B7 */
++			  "", "", "", "",
++			  "", "", "", "",
++			  /* GPIO0 C0-C7 */
++			  "", "", "", "",
++			  "", "", "", "",
++			  /* GPIO0 D0-D7 */
++			  "HEADER_12_1v8", "", "", "HEADER_24_1v8",
++			  "", "", "", "";
++};
++
++&gpio1 {
++	gpio-line-names = /* GPIO1 A0-A7 */
++			  "HEADER_27_3v3", "HEADER_28_3v3", "", "",
++			  "HEADER_29_1v8", "", "HEADER_7_1v8", "",
++			  /* GPIO1 B0-B7 */
++			  "", "HEADER_31_1v8", "HEADER_33_1v8", "",
++			  "HEADER_11_1v8", "HEADER_13_1v8", "", "",
++			  /* GPIO1 C0-C7 */
++			  "", "", "", "",
++			  "", "", "", "",
++			  /* GPIO1 D0-D7 */
++			  "", "", "", "",
++			  "", "", "HEADER_5_3v3", "HEADER_3_3v3";
++};
++
++&gpio3 {
++	gpio-line-names = /* GPIO3 A0-A7 */
++			  "", "", "", "",
++			  "", "", "", "",
++			  /* GPIO3 B0-B7 */
++			  "HEADER_16_1v8", "HEADER_18_1v8", "", "",
++			  "", "", "", "HEADER_19_1v8",
++			  /* GPIO3 C0-C7 */
++			  "HEADER_21_1v8", "HEADER_23_1v8", "", "HEADER_26_1v8",
++			  "HEADER_15_1v8", "HEADER_22_1v8", "", "",
++			  /* GPIO3 D0-D7 */
++			  "", "", "", "",
++			  "", "", "", "";
++};
++
++&gpio4 {
++	gpio-line-names = /* GPIO4 A0-A7 */
++			  "", "", "HEADER_37_3v3", "HEADER_32_3v3",
++			  "HEADER_36_3v3", "", "HEADER_35_3v3", "HEADER_38_3v3",
++			  /* GPIO4 B0-B7 */
++			  "", "", "", "HEADER_40_3v3",
++			  "HEADER_8_3v3", "HEADER_10_3v3", "", "",
++			  /* GPIO4 C0-C7 */
++			  "", "", "", "",
++			  "", "", "", "",
++			  /* GPIO4 D0-D7 */
++			  "", "", "", "",
++			  "", "", "", "";
++};
++
++&i2c0 {
++	pinctrl-0 = <&i2c0m2_xfer>;
++	pinctrl-names = "default";
++	status = "okay";
++
++	vdd_cpu_big0_s0: regulator@42 {
++		compatible = "rockchip,rk8602";
++		reg = <0x42>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <1050000>;
++		regulator-min-microvolt = <550000>;
++		regulator-name = "vdd_cpu_big0_s0";
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_cpu_big1_s0: regulator@43 {
++		compatible = "rockchip,rk8603", "rockchip,rk8602";
++		reg = <0x43>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <1050000>;
++		regulator-min-microvolt = <550000>;
++		regulator-name = "vdd_cpu_big1_s0";
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&i2c2 {
++	status = "okay";
++
++	vdd_npu_s0: regulator@42 {
++		compatible = "rockchip,rk8602";
++		reg = <0x42>;
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-max-microvolt = <950000>;
++		regulator-min-microvolt = <550000>;
++		regulator-name = "vdd_npu_s0";
++		regulator-ramp-delay = <2300>;
++		fcs,suspend-voltage-selector = <1>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&i2c6 {
++	pinctrl-0 = <&i2c6m3_xfer>;
++	status = "okay";
++
++	fusb302: typec-portc@22 {
++		compatible = "fcs,fusb302";
++		reg = <0x22>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PC4 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-0 = <&usbc0_int>;
++		pinctrl-names = "default";
++		vbus-supply = <&vbus5v0_typec>;
++
++		connector {
++			compatible = "usb-c-connector";
++			data-role = "dual";
++			label = "USB-C";
++			power-role = "dual";
++			try-power-role = "sink";
++			source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
++			sink-pdos = <PDO_FIXED(5000, 1000, PDO_FIXED_USB_COMM)>;
++			op-sink-microwatt = <1000000>;
++		};
++	};
++
++	rtc_hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-output-names = "hym8563";
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-0 = <&hym8563_int>;
++		pinctrl-names = "default";
++		wakeup-source;
++	};
++};
++
++&i2c7 {
++	pinctrl-0 = <&i2c7m0_xfer>;
++	status = "okay";
++
++	es8388: audio-codec@11 {
++		compatible = "everest,es8388";
++		reg = <0x11>;
++		assigned-clock-rates = <12288000>;
++		assigned-clocks = <&cru I2S0_8CH_MCLKOUT>;
++		AVDD-supply = <&vcc_3v3_s3>;
++		clock-names = "mclk";
++		clocks = <&cru I2S0_8CH_MCLKOUT>;
++		DVDD-supply = <&vcc_1v8_s3>;
++		HPVDD-supply = <&vcc_3v3_s3>;
++		PVDD-supply = <&vcc_1v8_s3>;
++		#sound-dai-cells = <0>;
++
++		port {
++			es8388_p0_0: endpoint {
++				remote-endpoint = <&i2s0_8ch_p0_0>;
++			};
++		};
++	};
++};
++
++&i2s0_8ch {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2s0_lrck
++		     &i2s0_mclk
++		     &i2s0_sclk
++		     &i2s0_sdi0
++		     &i2s0_sdo0>;
++	status = "okay";
++
++	i2s0_8ch_p0: port {
++		i2s0_8ch_p0_0: endpoint {
++			dai-format = "i2s";
++			mclk-fs = <256>;
++			remote-endpoint = <&es8388_p0_0>;
++		};
++	};
++};
++
++
++&pinctrl {
++	bluetooth-pins {
++		bt_reset: bt-reset {
++			rockchip,pins =
++				<0 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_wake_dev: bt-wake-dev {
++			rockchip,pins =
++				<0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		bt_wake_host: bt-wake-host {
++			rockchip,pins =
++				<0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_down>;
++		};
++	};
++
++	hym8563 {
++
++		hym8563_int: hym8563-int {
++			rockchip,pins =
++				<0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	sdio-pwrseq {
++		wifi_enable_h: wifi-enable-h {
++			rockchip,pins =
++				<0 RK_PC7 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb-typec {
++		usbc0_int: usbc0-int {
++			rockchip,pins =
++				<0 RK_PC4 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		typec5v_pwren: typec5v-pwren {
++			rockchip,pins =
++				<4 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++/* HS400 modes seemed to cause io errors. */
++&sdhci {
++	bus-width = <8>;
++	no-mmc-hs400;
++	no-sd;
++	no-sdio;
++	non-removable;
++	max-frequency = <200000000>;
++	vmmc-supply = <&vcc_3v3_s0>;
++	vqmmc-supply = <&vcc_1v8_s3>;
++	status = "okay";
++};
++
++&sdio {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	cap-sdio-irq;
++	disable-wp;
++	keep-power-in-suspend;
++	max-frequency = <100000000>;
++	mmc-pwrseq = <&sdio_pwrseq>;
++	no-mmc;
++	no-sd;
++	non-removable;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3_s3>;
++	vqmmc-supply = <&vcc_1v8_s3>;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-mmc-highspeed;
++	cap-sd-highspeed;
++	disable-wp;
++	max-frequency = <200000000>;
++	no-sdio;
++	no-mmc;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3_s3>;
++	vqmmc-supply = <&vccio_sd_s0>;
++	status = "okay";
++};
++
++&spi2 {
++	#address-cells = <1>;
++	assigned-clocks = <&cru CLK_SPI2>;
++	assigned-clock-rates = <200000000>;
++	num-cs = <1>;
++	pinctrl-0 = <&spi2m2_pins>, <&spi2m2_cs0>;
++	pinctrl-names = "default";
++	#size-cells = <0>;
++	status = "okay";
++
++	pmic@0 {
++		compatible = "rockchip,rk806";
++		reg = <0x0>;
++		#gpio-cells = <2>;
++		gpio-controller;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++			    <&rk806_dvs2_null>, <&rk806_dvs3_null>;
++		pinctrl-names = "default";
++		spi-max-frequency = <1000000>;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc5v0_sys>;
++		vcc6-supply = <&vcc5v0_sys>;
++		vcc7-supply = <&vcc5v0_sys>;
++		vcc8-supply = <&vcc5v0_sys>;
++		vcc9-supply = <&vcc5v0_sys>;
++		vcc10-supply = <&vcc5v0_sys>;
++		vcc11-supply = <&vcc_2v0_pldo_s3>;
++		vcc12-supply = <&vcc5v0_sys>;
++		vcc13-supply = <&vcc_1v1_nldo_s3>;
++		vcc14-supply = <&vcc_1v1_nldo_s3>;
++		vcca-supply = <&vcc5v0_sys>;
++
++		rk806_dvs1_null: dvs1-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs2_null: dvs2-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs3_null: dvs3-null-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun0";
++		};
++
++		regulators {
++			vdd_gpu_s0: dcdc-reg1 {
++				regulator-boot-on;
++				regulator-enable-ramp-delay = <400>;
++				regulator-max-microvolt = <950000>;
++				regulator-min-microvolt = <550000>;
++				regulator-name = "vdd_gpu_s0";
++				regulator-ramp-delay = <12500>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_lit_s0: dcdc-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <950000>;
++				regulator-min-microvolt = <550000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_cpu_lit_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_logic_s0: dcdc-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <750000>;
++				regulator-min-microvolt = <675000>;
++				regulator-name = "vdd_logic_s0";
++				regulator-ramp-delay = <12500>;
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <750000>;
++				};
++			};
++
++			vdd_vdenc_s0: dcdc-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <950000>;
++				regulator-min-microvolt = <550000>;
++				regulator-name = "vdd_vdenc_s0";
++				regulator-ramp-delay = <12500>;
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_ddr_s0: dcdc-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <850000>;
++				regulator-ramp-delay = <12500>;
++				regulator-name = "vdd_ddr_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <850000>;
++				};
++			};
++
++			vdd2_ddr_s3: dcdc-reg6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1100000>;
++				regulator-min-microvolt = <1100000>;
++				regulator-name = "vdd2_ddr_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_2v0_pldo_s3: dcdc-reg7 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <2000000>;
++				regulator-min-microvolt = <2000000>;
++				regulator-name = "vdd_2v0_pldo_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <2000000>;
++				};
++			};
++
++			vcc_3v3_s3: dcdc-reg8 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <3300000>;
++				regulator-min-microvolt = <3300000>;
++				regulator-name = "vcc_3v3_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vddq_ddr_s0: dcdc-reg9 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <600000>;
++				regulator-min-microvolt = <600000>;
++				regulator-name = "vddq_ddr_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8_s3: dcdc-reg10 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1800000>;
++				regulator-min-microvolt = <1800000>;
++				regulator-name = "vcc_1v8_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vcc_1v8_s0: pldo-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1800000>;
++				regulator-min-microvolt = <1800000>;
++				regulator-name = "vcc_1v8_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca_1v8_s0: pldo-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1800000>;
++				regulator-min-microvolt = <1800000>;
++				regulator-name = "vcca_1v8_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdda_1v2_s0: pldo-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1200000>;
++				regulator-min-microvolt = <1200000>;
++				regulator-name = "vdda_1v2_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcca_3v3_s0: pldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <3300000>;
++				regulator-min-microvolt = <3300000>;
++				regulator-name = "vcca_3v3_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd_s0: pldo-reg5 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <3300000>;
++				regulator-min-microvolt = <1800000>;
++				regulator-name = "vccio_sd_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8_s3_pldo6: pldo-reg6 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1800000>;
++				regulator-min-microvolt = <1800000>;
++				regulator-name = "vcc_1v8_s3_pldo6";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_0v75_s3: nldo-reg1 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <750000>;
++				regulator-min-microvolt = <750000>;
++				regulator-name = "vdd_0v75_s3";
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <750000>;
++				};
++			};
++
++			vdda_ddr_pll_s0: nldo-reg2 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <850000>;
++				regulator-min-microvolt = <850000>;
++				regulator-name = "vdda_ddr_pll_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <850000>;
++				};
++			};
++
++			avdd_0v75_s0: nldo-reg3 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <750000>;
++				regulator-min-microvolt = <750000>;
++				regulator-name = "avdd_0v75_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdda_0v85_s0: nldo-reg4 {
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <850000>;
++				regulator-max-microvolt = <850000>;
++				regulator-name = "vdda_0v85_s0";
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			/* Schematics show not in use */
++			nldo-reg5 {
++			};
++		};
++	};
++};
++
++&tsadc {
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
++
++/* DMA seems to interfere with bluetooth device normal operation. */
++&uart9 {
++	pinctrl-0 = <&uart9m2_xfer>, <&uart9m2_ctsn>, <&uart9m2_rtsn>;
++	pinctrl-names = "default";
++	/delete-property/ dma-names;
++	/delete-property/ dmas;
++	uart-has-rtscts;
++	status = "okay";
++
++	bluetooth {
++		compatible = "realtek,rtl8821cs-bt",
++			     "realtek,rtl8723bs-bt";
++		device-wake-gpios = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
++		enable-gpios = <&gpio0 RK_PD4 GPIO_ACTIVE_HIGH>;
++		host-wake-gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		pinctrl-0 = <&bt_reset>, <&bt_wake_dev>, <&bt_wake_host>;
++		pinctrl-names = "default";
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/390-PM-devfreq-rockchip-dfi-Embed-desc-into-private-data.patch b/target/linux/rockchip/patches-6.1/390-PM-devfreq-rockchip-dfi-Embed-desc-into-private-data.patch
new file mode 100644
index 00000000000..cb3b814be1d
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/390-PM-devfreq-rockchip-dfi-Embed-desc-into-private-data.patch
@@ -0,0 +1,43 @@
+From daaf4f20581337c3635e74b3ef63dff4ef5a497c Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:30 +0200
+Subject: [PATCH 390/414] PM / devfreq: rockchip-dfi: Embed desc into private
+ data struct
+
+No need for an extra allocation, just embed the struct
+devfreq_event_desc into the private data struct.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 8 ++------
+ 1 file changed, 2 insertions(+), 6 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -49,7 +49,7 @@ struct dmc_usage {
+  */
+ struct rockchip_dfi {
+ 	struct devfreq_event_dev *edev;
+-	struct devfreq_event_desc *desc;
++	struct devfreq_event_desc desc;
+ 	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
+ 	struct device *dev;
+ 	void __iomem *regs;
+@@ -204,14 +204,10 @@ static int rockchip_dfi_probe(struct pla
+ 
+ 	data->dev = dev;
+ 
+-	desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
+-	if (!desc)
+-		return -ENOMEM;
+-
++	desc = &data->desc;
+ 	desc->ops = &rockchip_dfi_ops;
+ 	desc->driver_data = data;
+ 	desc->name = np->name;
+-	data->desc = desc;
+ 
+ 	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+ 	if (IS_ERR(data->edev)) {
diff --git a/target/linux/rockchip/patches-6.1/391-PM-devfreq-rockchip-dfi-use-consistent-name-for-priv.patch b/target/linux/rockchip/patches-6.1/391-PM-devfreq-rockchip-dfi-use-consistent-name-for-priv.patch
new file mode 100644
index 00000000000..46c6f07a3bf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/391-PM-devfreq-rockchip-dfi-use-consistent-name-for-priv.patch
@@ -0,0 +1,182 @@
+From 6942ca2cdc0a11277b9329dc0cc4ebc26213a490 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:31 +0200
+Subject: [PATCH 391/414] PM / devfreq: rockchip-dfi: use consistent name for
+ private data struct
+
+The variable name for the private data struct is 'info' in some
+functions and 'data' in others. Both names do not give a clue what
+type the variable has, so consistently use 'dfi'.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++--------------
+ 1 file changed, 36 insertions(+), 36 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -59,13 +59,13 @@ struct rockchip_dfi {
+ 
+ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+ {
+-	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+-	void __iomem *dfi_regs = info->regs;
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	void __iomem *dfi_regs = dfi->regs;
+ 	u32 val;
+ 	u32 ddr_type;
+ 
+ 	/* get ddr type */
+-	regmap_read(info->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
++	regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+ 	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+ 		    RK3399_PMUGRF_DDRTYPE_MASK;
+ 
+@@ -84,28 +84,28 @@ static void rockchip_dfi_start_hardware_
+ 
+ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+ {
+-	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
+-	void __iomem *dfi_regs = info->regs;
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
++	void __iomem *dfi_regs = dfi->regs;
+ 
+ 	writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
+ }
+ 
+ static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
+ {
+-	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	u32 tmp, max = 0;
+ 	u32 i, busier_ch = 0;
+-	void __iomem *dfi_regs = info->regs;
++	void __iomem *dfi_regs = dfi->regs;
+ 
+ 	rockchip_dfi_stop_hardware_counter(edev);
+ 
+ 	/* Find out which channel is busier */
+ 	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+-		info->ch_usage[i].access = readl_relaxed(dfi_regs +
++		dfi->ch_usage[i].access = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
+-		info->ch_usage[i].total = readl_relaxed(dfi_regs +
++		dfi->ch_usage[i].total = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_COUNT_NUM + i * 20);
+-		tmp = info->ch_usage[i].access;
++		tmp = dfi->ch_usage[i].access;
+ 		if (tmp > max) {
+ 			busier_ch = i;
+ 			max = tmp;
+@@ -118,20 +118,20 @@ static int rockchip_dfi_get_busier_ch(st
+ 
+ static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
+ {
+-	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 
+ 	rockchip_dfi_stop_hardware_counter(edev);
+-	clk_disable_unprepare(info->clk);
++	clk_disable_unprepare(dfi->clk);
+ 
+ 	return 0;
+ }
+ 
+ static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
+ {
+-	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	int ret;
+ 
+-	ret = clk_prepare_enable(info->clk);
++	ret = clk_prepare_enable(dfi->clk);
+ 	if (ret) {
+ 		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
+ 		return ret;
+@@ -149,13 +149,13 @@ static int rockchip_dfi_set_event(struct
+ static int rockchip_dfi_get_event(struct devfreq_event_dev *edev,
+ 				  struct devfreq_event_data *edata)
+ {
+-	struct rockchip_dfi *info = devfreq_event_get_drvdata(edev);
++	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	int busier_ch;
+ 
+ 	busier_ch = rockchip_dfi_get_busier_ch(edev);
+ 
+-	edata->load_count = info->ch_usage[busier_ch].access;
+-	edata->total_count = info->ch_usage[busier_ch].total;
++	edata->load_count = dfi->ch_usage[busier_ch].access;
++	edata->total_count = dfi->ch_usage[busier_ch].total;
+ 
+ 	return 0;
+ }
+@@ -176,47 +176,47 @@ MODULE_DEVICE_TABLE(of, rockchip_dfi_id_
+ static int rockchip_dfi_probe(struct platform_device *pdev)
+ {
+ 	struct device *dev = &pdev->dev;
+-	struct rockchip_dfi *data;
++	struct rockchip_dfi *dfi;
+ 	struct devfreq_event_desc *desc;
+ 	struct device_node *np = pdev->dev.of_node, *node;
+ 
+-	data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL);
+-	if (!data)
++	dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL);
++	if (!dfi)
+ 		return -ENOMEM;
+ 
+-	data->regs = devm_platform_ioremap_resource(pdev, 0);
+-	if (IS_ERR(data->regs))
+-		return PTR_ERR(data->regs);
+-
+-	data->clk = devm_clk_get(dev, "pclk_ddr_mon");
+-	if (IS_ERR(data->clk))
+-		return dev_err_probe(dev, PTR_ERR(data->clk),
++	dfi->regs = devm_platform_ioremap_resource(pdev, 0);
++	if (IS_ERR(dfi->regs))
++		return PTR_ERR(dfi->regs);
++
++	dfi->clk = devm_clk_get(dev, "pclk_ddr_mon");
++	if (IS_ERR(dfi->clk))
++		return dev_err_probe(dev, PTR_ERR(dfi->clk),
+ 				     "Cannot get the clk pclk_ddr_mon\n");
+ 
+ 	node = of_parse_phandle(np, "rockchip,pmu", 0);
+ 	if (!node)
+ 		return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
+ 
+-	data->regmap_pmu = syscon_node_to_regmap(node);
++	dfi->regmap_pmu = syscon_node_to_regmap(node);
+ 	of_node_put(node);
+-	if (IS_ERR(data->regmap_pmu))
+-		return PTR_ERR(data->regmap_pmu);
++	if (IS_ERR(dfi->regmap_pmu))
++		return PTR_ERR(dfi->regmap_pmu);
+ 
+-	data->dev = dev;
++	dfi->dev = dev;
+ 
+-	desc = &data->desc;
++	desc = &dfi->desc;
+ 	desc->ops = &rockchip_dfi_ops;
+-	desc->driver_data = data;
++	desc->driver_data = dfi;
+ 	desc->name = np->name;
+ 
+-	data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+-	if (IS_ERR(data->edev)) {
++	dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
++	if (IS_ERR(dfi->edev)) {
+ 		dev_err(&pdev->dev,
+ 			"failed to add devfreq-event device\n");
+-		return PTR_ERR(data->edev);
++		return PTR_ERR(dfi->edev);
+ 	}
+ 
+-	platform_set_drvdata(pdev, data);
++	platform_set_drvdata(pdev, dfi);
+ 
+ 	return 0;
+ }
diff --git a/target/linux/rockchip/patches-6.1/392-PM-devfreq-rockchip-dfi-Add-SoC-specific-init-functi.patch b/target/linux/rockchip/patches-6.1/392-PM-devfreq-rockchip-dfi-Add-SoC-specific-init-functi.patch
new file mode 100644
index 00000000000..7aeeab9424b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/392-PM-devfreq-rockchip-dfi-Add-SoC-specific-init-functi.patch
@@ -0,0 +1,119 @@
+From 584df97ad3faf621edd820541b131d66a5cf5e83 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:32 +0200
+Subject: [PATCH 392/414] PM / devfreq: rockchip-dfi: Add SoC specific init
+ function
+
+Move the RK3399 specifics to a SoC specific init function to make
+the way free for supporting other SoCs later.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 48 +++++++++++++++++++---------
+ 1 file changed, 33 insertions(+), 15 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -17,6 +17,7 @@
+ #include <linux/slab.h>
+ #include <linux/list.h>
+ #include <linux/of.h>
++#include <linux/of_device.h>
+ 
+ #include <soc/rockchip/rk3399_grf.h>
+ 
+@@ -55,27 +56,21 @@ struct rockchip_dfi {
+ 	void __iomem *regs;
+ 	struct regmap *regmap_pmu;
+ 	struct clk *clk;
++	u32 ddr_type;
+ };
+ 
+ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	void __iomem *dfi_regs = dfi->regs;
+-	u32 val;
+-	u32 ddr_type;
+-
+-	/* get ddr type */
+-	regmap_read(dfi->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+-	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+-		    RK3399_PMUGRF_DDRTYPE_MASK;
+ 
+ 	/* clear DDRMON_CTRL setting */
+ 	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+ 
+ 	/* set ddr type to dfi */
+-	if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
++	if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
+ 		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+-	else if (ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
++	else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
+ 		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+ 
+ 	/* enable count, use software mode */
+@@ -167,8 +162,26 @@ static const struct devfreq_event_ops ro
+ 	.set_event = rockchip_dfi_set_event,
+ };
+ 
++static int rk3399_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct regmap *regmap_pmu = dfi->regmap_pmu;
++	u32 val;
++
++	dfi->clk = devm_clk_get(dfi->dev, "pclk_ddr_mon");
++	if (IS_ERR(dfi->clk))
++		return dev_err_probe(dfi->dev, PTR_ERR(dfi->clk),
++				     "Cannot get the clk pclk_ddr_mon\n");
++
++	/* get ddr type */
++	regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
++	dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
++			RK3399_PMUGRF_DDRTYPE_MASK;
++
++	return 0;
++};
++
+ static const struct of_device_id rockchip_dfi_id_match[] = {
+-	{ .compatible = "rockchip,rk3399-dfi" },
++	{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
+ 	{ },
+ };
+ MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
+@@ -179,6 +192,12 @@ static int rockchip_dfi_probe(struct pla
+ 	struct rockchip_dfi *dfi;
+ 	struct devfreq_event_desc *desc;
+ 	struct device_node *np = pdev->dev.of_node, *node;
++	int (*soc_init)(struct rockchip_dfi *dfi);
++	int ret;
++
++	soc_init = of_device_get_match_data(&pdev->dev);
++	if (!soc_init)
++		return -EINVAL;
+ 
+ 	dfi = devm_kzalloc(dev, sizeof(*dfi), GFP_KERNEL);
+ 	if (!dfi)
+@@ -188,11 +207,6 @@ static int rockchip_dfi_probe(struct pla
+ 	if (IS_ERR(dfi->regs))
+ 		return PTR_ERR(dfi->regs);
+ 
+-	dfi->clk = devm_clk_get(dev, "pclk_ddr_mon");
+-	if (IS_ERR(dfi->clk))
+-		return dev_err_probe(dev, PTR_ERR(dfi->clk),
+-				     "Cannot get the clk pclk_ddr_mon\n");
+-
+ 	node = of_parse_phandle(np, "rockchip,pmu", 0);
+ 	if (!node)
+ 		return dev_err_probe(&pdev->dev, -ENODEV, "Can't find pmu_grf registers\n");
+@@ -209,6 +223,10 @@ static int rockchip_dfi_probe(struct pla
+ 	desc->driver_data = dfi;
+ 	desc->name = np->name;
+ 
++	ret = soc_init(dfi);
++	if (ret)
++		return ret;
++
+ 	dfi->edev = devm_devfreq_event_add_edev(&pdev->dev, desc);
+ 	if (IS_ERR(dfi->edev)) {
+ 		dev_err(&pdev->dev,
diff --git a/target/linux/rockchip/patches-6.1/393-PM-devfreq-rockchip-dfi-dfi-store-raw-values-in-coun.patch b/target/linux/rockchip/patches-6.1/393-PM-devfreq-rockchip-dfi-dfi-store-raw-values-in-coun.patch
new file mode 100644
index 00000000000..a6a152e51bf
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/393-PM-devfreq-rockchip-dfi-dfi-store-raw-values-in-coun.patch
@@ -0,0 +1,36 @@
+From d019e53c06c97c9dba462ad5ea691579c4a38c8a Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:33 +0200
+Subject: [PATCH 393/414] PM / devfreq: rockchip-dfi: dfi store raw values in
+ counter struct
+
+When adding perf support to the DFI driver the perf part will
+need the raw counter values, so move the fixed * 4 factor to
+rockchip_dfi_get_event().
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -97,7 +97,7 @@ static int rockchip_dfi_get_busier_ch(st
+ 	/* Find out which channel is busier */
+ 	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+ 		dfi->ch_usage[i].access = readl_relaxed(dfi_regs +
+-				DDRMON_CH0_DFI_ACCESS_NUM + i * 20) * 4;
++				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+ 		dfi->ch_usage[i].total = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_COUNT_NUM + i * 20);
+ 		tmp = dfi->ch_usage[i].access;
+@@ -149,7 +149,7 @@ static int rockchip_dfi_get_event(struct
+ 
+ 	busier_ch = rockchip_dfi_get_busier_ch(edev);
+ 
+-	edata->load_count = dfi->ch_usage[busier_ch].access;
++	edata->load_count = dfi->ch_usage[busier_ch].access * 4;
+ 	edata->total_count = dfi->ch_usage[busier_ch].total;
+ 
+ 	return 0;
diff --git a/target/linux/rockchip/patches-6.1/394-PM-devfreq-rockchip-dfi-Use-free-running-counter.patch b/target/linux/rockchip/patches-6.1/394-PM-devfreq-rockchip-dfi-Use-free-running-counter.patch
new file mode 100644
index 00000000000..c7a0b0f7367
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/394-PM-devfreq-rockchip-dfi-Use-free-running-counter.patch
@@ -0,0 +1,122 @@
+From 28dc17d0ca6eab000fa477c7143fe5c65d2423e8 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:34 +0200
+Subject: [PATCH 394/414] PM / devfreq: rockchip-dfi: Use free running counter
+
+The DDR_MON counters are free running counters. These are resetted to 0
+when starting them over like currently done when reading the current
+counter values.
+
+Resetting the counters becomes a problem with perf support we want to
+add later, because perf needs counters that are not modified elsewhere.
+
+This patch removes resetting the counters and keeps them running
+instead. That means we no longer use the absolute counter values but
+instead compare them with the counter values we read last time. Not
+stopping the counters also has the impact that they are running while
+we are reading them. We cannot read multiple timers atomically, so
+the values do not exactly fit together. The effect should be negligible
+though as the time between two measurements is some orders of magnitude
+bigger than the time we need to read multiple registers.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 52 ++++++++++++++++------------
+ 1 file changed, 30 insertions(+), 22 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -38,11 +38,15 @@
+ #define DDRMON_CH1_COUNT_NUM		0x3c
+ #define DDRMON_CH1_DFI_ACCESS_NUM	0x40
+ 
+-struct dmc_usage {
++struct dmc_count_channel {
+ 	u32 access;
+ 	u32 total;
+ };
+ 
++struct dmc_count {
++	struct dmc_count_channel c[RK3399_DMC_NUM_CH];
++};
++
+ /*
+  * The dfi controller can monitor DDR load. It has an upper and lower threshold
+  * for the operating points. Whenever the usage leaves these bounds an event is
+@@ -51,7 +55,7 @@ struct dmc_usage {
+ struct rockchip_dfi {
+ 	struct devfreq_event_dev *edev;
+ 	struct devfreq_event_desc desc;
+-	struct dmc_usage ch_usage[RK3399_DMC_NUM_CH];
++	struct dmc_count last_event_count;
+ 	struct device *dev;
+ 	void __iomem *regs;
+ 	struct regmap *regmap_pmu;
+@@ -85,30 +89,18 @@ static void rockchip_dfi_stop_hardware_c
+ 	writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
+ }
+ 
+-static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev)
++static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+-	u32 tmp, max = 0;
+-	u32 i, busier_ch = 0;
++	u32 i;
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+-	rockchip_dfi_stop_hardware_counter(edev);
+-
+-	/* Find out which channel is busier */
+ 	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+-		dfi->ch_usage[i].access = readl_relaxed(dfi_regs +
++		count->c[i].access = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+-		dfi->ch_usage[i].total = readl_relaxed(dfi_regs +
++		count->c[i].total = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_COUNT_NUM + i * 20);
+-		tmp = dfi->ch_usage[i].access;
+-		if (tmp > max) {
+-			busier_ch = i;
+-			max = tmp;
+-		}
+ 	}
+-	rockchip_dfi_start_hardware_counter(edev);
+-
+-	return busier_ch;
+ }
+ 
+ static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
+@@ -145,12 +137,28 @@ static int rockchip_dfi_get_event(struct
+ 				  struct devfreq_event_data *edata)
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+-	int busier_ch;
++	struct dmc_count count;
++	struct dmc_count *last = &dfi->last_event_count;
++	u32 access = 0, total = 0;
++	int i;
++
++	rockchip_dfi_read_counters(edev, &count);
++
++	/* We can only report one channel, so find the busiest one */
++	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
++		u32 a = count.c[i].access - last->c[i].access;
++		u32 t = count.c[i].total - last->c[i].total;
++
++		if (a > access) {
++			access = a;
++			total = t;
++		}
++	}
+ 
+-	busier_ch = rockchip_dfi_get_busier_ch(edev);
++	edata->load_count = access * 4;
++	edata->total_count = total;
+ 
+-	edata->load_count = dfi->ch_usage[busier_ch].access * 4;
+-	edata->total_count = dfi->ch_usage[busier_ch].total;
++	dfi->last_event_count = count;
+ 
+ 	return 0;
+ }
diff --git a/target/linux/rockchip/patches-6.1/395-PM-devfreq-rockchip-dfi-introduce-channel-mask.patch b/target/linux/rockchip/patches-6.1/395-PM-devfreq-rockchip-dfi-introduce-channel-mask.patch
new file mode 100644
index 00000000000..d4a10d8ccba
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/395-PM-devfreq-rockchip-dfi-introduce-channel-mask.patch
@@ -0,0 +1,84 @@
+From b08008c9f4396787040a48561b908c8acc82c349 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:35 +0200
+Subject: [PATCH 395/414] PM / devfreq: rockchip-dfi: introduce channel mask
+
+Different Rockchip SoC variants have a different number of channels.
+Introduce a channel mask to make the number of channels configurable
+from SoC initialization code.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 23 +++++++++++++++++------
+ 1 file changed, 17 insertions(+), 6 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -18,10 +18,11 @@
+ #include <linux/list.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/bits.h>
+ 
+ #include <soc/rockchip/rk3399_grf.h>
+ 
+-#define RK3399_DMC_NUM_CH	2
++#define DMC_MAX_CHANNELS	2
+ 
+ /* DDRMON_CTRL */
+ #define DDRMON_CTRL	0x04
+@@ -44,7 +45,7 @@ struct dmc_count_channel {
+ };
+ 
+ struct dmc_count {
+-	struct dmc_count_channel c[RK3399_DMC_NUM_CH];
++	struct dmc_count_channel c[DMC_MAX_CHANNELS];
+ };
+ 
+ /*
+@@ -61,6 +62,7 @@ struct rockchip_dfi {
+ 	struct regmap *regmap_pmu;
+ 	struct clk *clk;
+ 	u32 ddr_type;
++	unsigned int channel_mask;
+ };
+ 
+ static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
+@@ -95,7 +97,9 @@ static void rockchip_dfi_read_counters(s
+ 	u32 i;
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+-	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
++	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
++		if (!(dfi->channel_mask & BIT(i)))
++			continue;
+ 		count->c[i].access = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+ 		count->c[i].total = readl_relaxed(dfi_regs +
+@@ -145,9 +149,14 @@ static int rockchip_dfi_get_event(struct
+ 	rockchip_dfi_read_counters(edev, &count);
+ 
+ 	/* We can only report one channel, so find the busiest one */
+-	for (i = 0; i < RK3399_DMC_NUM_CH; i++) {
+-		u32 a = count.c[i].access - last->c[i].access;
+-		u32 t = count.c[i].total - last->c[i].total;
++	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
++		u32 a, t;
++
++		if (!(dfi->channel_mask & BIT(i)))
++			continue;
++
++		a = count.c[i].access - last->c[i].access;
++		t = count.c[i].total - last->c[i].total;
+ 
+ 		if (a > access) {
+ 			access = a;
+@@ -185,6 +194,8 @@ static int rk3399_dfi_init(struct rockch
+ 	dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+ 			RK3399_PMUGRF_DDRTYPE_MASK;
+ 
++	dfi->channel_mask = GENMASK(1, 0);
++
+ 	return 0;
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/396-PM-devfreq-rk3399_dmc-dfi-generalize-DDRTYPE-defines.patch b/target/linux/rockchip/patches-6.1/396-PM-devfreq-rk3399_dmc-dfi-generalize-DDRTYPE-defines.patch
new file mode 100644
index 00000000000..48b298481d1
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/396-PM-devfreq-rk3399_dmc-dfi-generalize-DDRTYPE-defines.patch
@@ -0,0 +1,124 @@
+From 71dd420de9dd4ed9e1830a97d7d05b9d241b71fe Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:36 +0200
+Subject: [PATCH 396/414] PM / devfreq: rk3399_dmc,dfi: generalize DDRTYPE
+ defines
+
+The DDRTYPE defines are named to be RK3399 specific, but they can be
+used for other Rockchip SoCs as well, so replace the RK3399_PMUGRF_
+prefix with ROCKCHIP_. They are defined in a SoC specific header
+file, so when generalizing the prefix also move the new defines to
+a SoC agnostic header file. While at it use GENMASK to define the
+DDRTYPE bitfield and give it a name including the full register name.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c |  9 +++++----
+ drivers/devfreq/rk3399_dmc.c         | 10 +++++-----
+ include/soc/rockchip/rk3399_grf.h    |  7 +------
+ include/soc/rockchip/rockchip_grf.h  | 17 +++++++++++++++++
+ 4 files changed, 28 insertions(+), 15 deletions(-)
+ create mode 100644 include/soc/rockchip/rockchip_grf.h
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -18,8 +18,10 @@
+ #include <linux/list.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
++#include <linux/bitfield.h>
+ #include <linux/bits.h>
+ 
++#include <soc/rockchip/rockchip_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
+ 
+ #define DMC_MAX_CHANNELS	2
+@@ -74,9 +76,9 @@ static void rockchip_dfi_start_hardware_
+ 	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
+ 
+ 	/* set ddr type to dfi */
+-	if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR3)
++	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
+ 		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
+-	else if (dfi->ddr_type == RK3399_PMUGRF_DDRTYPE_LPDDR4)
++	else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
+ 		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
+ 
+ 	/* enable count, use software mode */
+@@ -191,8 +193,7 @@ static int rk3399_dfi_init(struct rockch
+ 
+ 	/* get ddr type */
+ 	regmap_read(regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+-	dfi->ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+-			RK3399_PMUGRF_DDRTYPE_MASK;
++	dfi->ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
+ 
+ 	dfi->channel_mask = GENMASK(1, 0);
+ 
+--- a/drivers/devfreq/rk3399_dmc.c
++++ b/drivers/devfreq/rk3399_dmc.c
+@@ -22,6 +22,7 @@
+ #include <linux/suspend.h>
+ 
+ #include <soc/rockchip/pm_domains.h>
++#include <soc/rockchip/rockchip_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
+ #include <soc/rockchip/rockchip_sip.h>
+ 
+@@ -381,17 +382,16 @@ static int rk3399_dmcfreq_probe(struct p
+ 	}
+ 
+ 	regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val);
+-	ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) &
+-		    RK3399_PMUGRF_DDRTYPE_MASK;
++	ddr_type = FIELD_GET(RK3399_PMUGRF_OS_REG2_DDRTYPE, val);
+ 
+ 	switch (ddr_type) {
+-	case RK3399_PMUGRF_DDRTYPE_DDR3:
++	case ROCKCHIP_DDRTYPE_DDR3:
+ 		data->odt_dis_freq = data->ddr3_odt_dis_freq;
+ 		break;
+-	case RK3399_PMUGRF_DDRTYPE_LPDDR3:
++	case ROCKCHIP_DDRTYPE_LPDDR3:
+ 		data->odt_dis_freq = data->lpddr3_odt_dis_freq;
+ 		break;
+-	case RK3399_PMUGRF_DDRTYPE_LPDDR4:
++	case ROCKCHIP_DDRTYPE_LPDDR4:
+ 		data->odt_dis_freq = data->lpddr4_odt_dis_freq;
+ 		break;
+ 	default:
+--- a/include/soc/rockchip/rk3399_grf.h
++++ b/include/soc/rockchip/rk3399_grf.h
+@@ -11,11 +11,6 @@
+ 
+ /* PMU GRF Registers */
+ #define RK3399_PMUGRF_OS_REG2		0x308
+-#define RK3399_PMUGRF_DDRTYPE_SHIFT	13
+-#define RK3399_PMUGRF_DDRTYPE_MASK	7
+-#define RK3399_PMUGRF_DDRTYPE_DDR3	3
+-#define RK3399_PMUGRF_DDRTYPE_LPDDR2	5
+-#define RK3399_PMUGRF_DDRTYPE_LPDDR3	6
+-#define RK3399_PMUGRF_DDRTYPE_LPDDR4	7
++#define RK3399_PMUGRF_OS_REG2_DDRTYPE		GENMASK(15, 13)
+ 
+ #endif
+--- /dev/null
++++ b/include/soc/rockchip/rockchip_grf.h
+@@ -0,0 +1,17 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++/*
++ * Rockchip General Register Files definitions
++ */
++
++#ifndef __SOC_ROCKCHIP_GRF_H
++#define __SOC_ROCKCHIP_GRF_H
++
++/* Rockchip DDRTYPE defines */
++enum {
++	ROCKCHIP_DDRTYPE_DDR3	= 3,
++	ROCKCHIP_DDRTYPE_LPDDR2	= 5,
++	ROCKCHIP_DDRTYPE_LPDDR3	= 6,
++	ROCKCHIP_DDRTYPE_LPDDR4	= 7,
++};
++
++#endif /* __SOC_ROCKCHIP_GRF_H */
diff --git a/target/linux/rockchip/patches-6.1/397-PM-devfreq-rockchip-dfi-Clean-up-DDR-type-register-d.patch b/target/linux/rockchip/patches-6.1/397-PM-devfreq-rockchip-dfi-Clean-up-DDR-type-register-d.patch
new file mode 100644
index 00000000000..a277d0f8c49
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/397-PM-devfreq-rockchip-dfi-Clean-up-DDR-type-register-d.patch
@@ -0,0 +1,85 @@
+From 3787ec8983d7210be174eb0bc758029002c448e5 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:37 +0200
+Subject: [PATCH 397/414] PM / devfreq: rockchip-dfi: Clean up DDR type
+ register defines
+
+Use the HIWORD_UPDATE() define known from other rockchip drivers to
+make the defines look less odd to the readers who've seen other
+rockchip drivers.
+
+The HIWORD registers have their functional bits in the lower 16 bits
+whereas the upper 16 bits contain a mask. Only the functional bits that
+have the corresponding mask bit set are modified during a write. Although
+the register writes look different, the end result should be the same,
+at least there's no functional change intended with this patch.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 33 ++++++++++++++++++----------
+ 1 file changed, 21 insertions(+), 12 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -26,15 +26,19 @@
+ 
+ #define DMC_MAX_CHANNELS	2
+ 
++#define HIWORD_UPDATE(val, mask)	((val) | (mask) << 16)
++
+ /* DDRMON_CTRL */
+ #define DDRMON_CTRL	0x04
+-#define CLR_DDRMON_CTRL	(0x1f0000 << 0)
+-#define LPDDR4_EN	(0x10001 << 4)
+-#define HARDWARE_EN	(0x10001 << 3)
+-#define LPDDR3_EN	(0x10001 << 2)
+-#define SOFTWARE_EN	(0x10001 << 1)
+-#define SOFTWARE_DIS	(0x10000 << 1)
+-#define TIME_CNT_EN	(0x10001 << 0)
++#define DDRMON_CTRL_DDR4		BIT(5)
++#define DDRMON_CTRL_LPDDR4		BIT(4)
++#define DDRMON_CTRL_HARDWARE_EN		BIT(3)
++#define DDRMON_CTRL_LPDDR23		BIT(2)
++#define DDRMON_CTRL_SOFTWARE_EN		BIT(1)
++#define DDRMON_CTRL_TIMER_CNT_EN	BIT(0)
++#define DDRMON_CTRL_DDR_TYPE_MASK	(DDRMON_CTRL_DDR4 | \
++					 DDRMON_CTRL_LPDDR4 | \
++					 DDRMON_CTRL_LPDDR23)
+ 
+ #define DDRMON_CH0_COUNT_NUM		0x28
+ #define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
+@@ -73,16 +77,20 @@ static void rockchip_dfi_start_hardware_
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+ 	/* clear DDRMON_CTRL setting */
+-	writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL);
++	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
++		       DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
+ 
+ 	/* set ddr type to dfi */
+ 	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
+-		writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL);
++		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
++			       dfi_regs + DDRMON_CTRL);
+ 	else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
+-		writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL);
++		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
++			       dfi_regs + DDRMON_CTRL);
+ 
+ 	/* enable count, use software mode */
+-	writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL);
++	writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
++		       dfi_regs + DDRMON_CTRL);
+ }
+ 
+ static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
+@@ -90,7 +98,8 @@ static void rockchip_dfi_stop_hardware_c
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+-	writel_relaxed(SOFTWARE_DIS, dfi_regs + DDRMON_CTRL);
++	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
++		       dfi_regs + DDRMON_CTRL);
+ }
+ 
+ static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
diff --git a/target/linux/rockchip/patches-6.1/398-PM-devfreq-rockchip-dfi-Add-RK3568-support.patch b/target/linux/rockchip/patches-6.1/398-PM-devfreq-rockchip-dfi-Add-RK3568-support.patch
new file mode 100644
index 00000000000..f106348a3d0
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/398-PM-devfreq-rockchip-dfi-Add-RK3568-support.patch
@@ -0,0 +1,71 @@
+From 871f38fefb7142038faa50292215d8e19e8366ca Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:38 +0200
+Subject: [PATCH 398/414] PM / devfreq: rockchip-dfi: Add RK3568 support
+
+This adds RK3568 support to the DFI driver.  Only iniitialization
+differs from the currently supported RK3399.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 21 +++++++++++++++++++++
+ include/soc/rockchip/rk3568_grf.h    | 12 ++++++++++++
+ 2 files changed, 33 insertions(+)
+ create mode 100644 include/soc/rockchip/rk3568_grf.h
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -23,6 +23,7 @@
+ 
+ #include <soc/rockchip/rockchip_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
++#include <soc/rockchip/rk3568_grf.h>
+ 
+ #define DMC_MAX_CHANNELS	2
+ 
+@@ -209,10 +210,30 @@ static int rk3399_dfi_init(struct rockch
+ 	return 0;
+ };
+ 
++static int rk3568_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct regmap *regmap_pmu = dfi->regmap_pmu;
++	u32 reg2, reg3;
++
++	regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG2, &reg2);
++	regmap_read(regmap_pmu, RK3568_PMUGRF_OS_REG3, &reg3);
++
++	dfi->ddr_type = FIELD_GET(RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
++
++	if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
++		dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
++
++	dfi->channel_mask = 1;
++
++	return 0;
++};
++
+ static const struct of_device_id rockchip_dfi_id_match[] = {
+ 	{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
++	{ .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
+ 	{ },
+ };
++
+ MODULE_DEVICE_TABLE(of, rockchip_dfi_id_match);
+ 
+ static int rockchip_dfi_probe(struct platform_device *pdev)
+--- /dev/null
++++ b/include/soc/rockchip/rk3568_grf.h
+@@ -0,0 +1,12 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++#ifndef __SOC_RK3568_GRF_H
++#define __SOC_RK3568_GRF_H
++
++#define RK3568_PMUGRF_OS_REG2		0x208
++#define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO		GENMASK(15, 13)
++
++#define RK3568_PMUGRF_OS_REG3		0x20c
++#define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3		GENMASK(13, 12)
++#define RK3568_PMUGRF_OS_REG3_SYSREG_VERSION		GENMASK(31, 28)
++
++#endif /* __SOC_RK3568_GRF_H */
diff --git a/target/linux/rockchip/patches-6.1/399-PM-devfreq-rockchip-dfi-Handle-LPDDR2-correctly.patch b/target/linux/rockchip/patches-6.1/399-PM-devfreq-rockchip-dfi-Handle-LPDDR2-correctly.patch
new file mode 100644
index 00000000000..7c5e6c080ba
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/399-PM-devfreq-rockchip-dfi-Handle-LPDDR2-correctly.patch
@@ -0,0 +1,40 @@
+From e0606b7dac4764ef7d7cd07dbb127913a01cf0bb Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:39 +0200
+Subject: [PATCH 399/414] PM / devfreq: rockchip-dfi: Handle LPDDR2 correctly
+
+According to the downstream driver the DDRMON_CTRL_LPDDR23 bit must be
+set for both LPDDR2 and LPDDR3. Add the missing LPDDR2 case and while
+at it turn the if/else if/else into switch/case which makes it easier
+to read.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -82,12 +82,19 @@ static void rockchip_dfi_start_hardware_
+ 		       DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
+ 
+ 	/* set ddr type to dfi */
+-	if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR3)
++	switch (dfi->ddr_type) {
++	case ROCKCHIP_DDRTYPE_LPDDR2:
++	case ROCKCHIP_DDRTYPE_LPDDR3:
+ 		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
+ 			       dfi_regs + DDRMON_CTRL);
+-	else if (dfi->ddr_type == ROCKCHIP_DDRTYPE_LPDDR4)
++		break;
++	case ROCKCHIP_DDRTYPE_LPDDR4:
+ 		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
+ 			       dfi_regs + DDRMON_CTRL);
++		break;
++	default:
++		break;
++	}
+ 
+ 	/* enable count, use software mode */
+ 	writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
diff --git a/target/linux/rockchip/patches-6.1/400-PM-devfreq-rockchip-dfi-Handle-LPDDR4X.patch b/target/linux/rockchip/patches-6.1/400-PM-devfreq-rockchip-dfi-Handle-LPDDR4X.patch
new file mode 100644
index 00000000000..76fa42901d2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/400-PM-devfreq-rockchip-dfi-Handle-LPDDR4X.patch
@@ -0,0 +1,35 @@
+From 192bbf5cd0c46e1abf02c629e2ea28739b039465 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:40 +0200
+Subject: [PATCH 400/414] PM / devfreq: rockchip-dfi: Handle LPDDR4X
+
+In the DFI driver LPDDR4X can be handled in the same way as LPDDR4. Add
+the missing case.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 1 +
+ include/soc/rockchip/rockchip_grf.h  | 1 +
+ 2 files changed, 2 insertions(+)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -89,6 +89,7 @@ static void rockchip_dfi_start_hardware_
+ 			       dfi_regs + DDRMON_CTRL);
+ 		break;
+ 	case ROCKCHIP_DDRTYPE_LPDDR4:
++	case ROCKCHIP_DDRTYPE_LPDDR4X:
+ 		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
+ 			       dfi_regs + DDRMON_CTRL);
+ 		break;
+--- a/include/soc/rockchip/rockchip_grf.h
++++ b/include/soc/rockchip/rockchip_grf.h
+@@ -12,6 +12,7 @@ enum {
+ 	ROCKCHIP_DDRTYPE_LPDDR2	= 5,
+ 	ROCKCHIP_DDRTYPE_LPDDR3	= 6,
+ 	ROCKCHIP_DDRTYPE_LPDDR4	= 7,
++	ROCKCHIP_DDRTYPE_LPDDR4X = 8,
+ };
+ 
+ #endif /* __SOC_ROCKCHIP_GRF_H */
diff --git a/target/linux/rockchip/patches-6.1/401-PM-devfreq-rockchip-dfi-Pass-private-data-struct-to-.patch b/target/linux/rockchip/patches-6.1/401-PM-devfreq-rockchip-dfi-Pass-private-data-struct-to-.patch
new file mode 100644
index 00000000000..cd879c5979c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/401-PM-devfreq-rockchip-dfi-Pass-private-data-struct-to-.patch
@@ -0,0 +1,77 @@
+From b9b81d118d52e5e673b0fdecaf93adbde0beebd8 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:41 +0200
+Subject: [PATCH 401/414] PM / devfreq: rockchip-dfi: Pass private data struct
+ to internal functions
+
+The internal functions do not need the struct devfreq_event_dev *,
+so pass them the struct rockchip_dfi *. This is a preparation for
+adding perf support later which doesn't have a struct devfreq_event_dev *.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 15 ++++++---------
+ 1 file changed, 6 insertions(+), 9 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -72,9 +72,8 @@ struct rockchip_dfi {
+ 	unsigned int channel_mask;
+ };
+ 
+-static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev)
++static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi *dfi)
+ {
+-	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+ 	/* clear DDRMON_CTRL setting */
+@@ -102,18 +101,16 @@ static void rockchip_dfi_start_hardware_
+ 		       dfi_regs + DDRMON_CTRL);
+ }
+ 
+-static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev)
++static void rockchip_dfi_stop_hardware_counter(struct rockchip_dfi *dfi)
+ {
+-	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+ 	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+ 		       dfi_regs + DDRMON_CTRL);
+ }
+ 
+-static void rockchip_dfi_read_counters(struct devfreq_event_dev *edev, struct dmc_count *count)
++static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
+ {
+-	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	u32 i;
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
+@@ -131,7 +128,7 @@ static int rockchip_dfi_disable(struct d
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 
+-	rockchip_dfi_stop_hardware_counter(edev);
++	rockchip_dfi_stop_hardware_counter(dfi);
+ 	clk_disable_unprepare(dfi->clk);
+ 
+ 	return 0;
+@@ -148,7 +145,7 @@ static int rockchip_dfi_enable(struct de
+ 		return ret;
+ 	}
+ 
+-	rockchip_dfi_start_hardware_counter(edev);
++	rockchip_dfi_start_hardware_counter(dfi);
+ 	return 0;
+ }
+ 
+@@ -166,7 +163,7 @@ static int rockchip_dfi_get_event(struct
+ 	u32 access = 0, total = 0;
+ 	int i;
+ 
+-	rockchip_dfi_read_counters(edev, &count);
++	rockchip_dfi_read_counters(dfi, &count);
+ 
+ 	/* We can only report one channel, so find the busiest one */
+ 	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
diff --git a/target/linux/rockchip/patches-6.1/402-PM-devfreq-rockchip-dfi-Prepare-for-multiple-users.patch b/target/linux/rockchip/patches-6.1/402-PM-devfreq-rockchip-dfi-Prepare-for-multiple-users.patch
new file mode 100644
index 00000000000..ee5888811e2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/402-PM-devfreq-rockchip-dfi-Prepare-for-multiple-users.patch
@@ -0,0 +1,135 @@
+From 520ab63511920ec641657f8cc6838cc8645b1f08 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:42 +0200
+Subject: [PATCH 402/414] PM / devfreq: rockchip-dfi: Prepare for multiple
+ users
+
+When adding perf support later the DFI must be enabled when
+either of devfreq-event or perf is active. Prepare for that
+by adding a usage counter for the DFI. Also move enabling
+and disabling of the clock away from the devfreq-event specific
+functions to which the perf specific part won't have access.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 57 +++++++++++++++++++---------
+ 1 file changed, 40 insertions(+), 17 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -68,13 +68,28 @@ struct rockchip_dfi {
+ 	void __iomem *regs;
+ 	struct regmap *regmap_pmu;
+ 	struct clk *clk;
++	int usecount;
++	struct mutex mutex;
+ 	u32 ddr_type;
+ 	unsigned int channel_mask;
+ };
+ 
+-static void rockchip_dfi_start_hardware_counter(struct rockchip_dfi *dfi)
++static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
+ {
+ 	void __iomem *dfi_regs = dfi->regs;
++	int ret = 0;
++
++	mutex_lock(&dfi->mutex);
++
++	dfi->usecount++;
++	if (dfi->usecount > 1)
++		goto out;
++
++	ret = clk_prepare_enable(dfi->clk);
++	if (ret) {
++		dev_err(&dfi->edev->dev, "failed to enable dfi clk: %d\n", ret);
++		goto out;
++	}
+ 
+ 	/* clear DDRMON_CTRL setting */
+ 	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
+@@ -99,14 +114,30 @@ static void rockchip_dfi_start_hardware_
+ 	/* enable count, use software mode */
+ 	writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
+ 		       dfi_regs + DDRMON_CTRL);
++out:
++	mutex_unlock(&dfi->mutex);
++
++	return ret;
+ }
+ 
+-static void rockchip_dfi_stop_hardware_counter(struct rockchip_dfi *dfi)
++static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
+ {
+ 	void __iomem *dfi_regs = dfi->regs;
+ 
++	mutex_lock(&dfi->mutex);
++
++	dfi->usecount--;
++
++	WARN_ON_ONCE(dfi->usecount < 0);
++
++	if (dfi->usecount > 0)
++		goto out;
++
+ 	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+ 		       dfi_regs + DDRMON_CTRL);
++	clk_disable_unprepare(dfi->clk);
++out:
++	mutex_unlock(&dfi->mutex);
+ }
+ 
+ static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
+@@ -124,29 +155,20 @@ static void rockchip_dfi_read_counters(s
+ 	}
+ }
+ 
+-static int rockchip_dfi_disable(struct devfreq_event_dev *edev)
++static int rockchip_dfi_event_disable(struct devfreq_event_dev *edev)
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 
+-	rockchip_dfi_stop_hardware_counter(dfi);
+-	clk_disable_unprepare(dfi->clk);
++	rockchip_dfi_disable(dfi);
+ 
+ 	return 0;
+ }
+ 
+-static int rockchip_dfi_enable(struct devfreq_event_dev *edev)
++static int rockchip_dfi_event_enable(struct devfreq_event_dev *edev)
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+-	int ret;
+ 
+-	ret = clk_prepare_enable(dfi->clk);
+-	if (ret) {
+-		dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret);
+-		return ret;
+-	}
+-
+-	rockchip_dfi_start_hardware_counter(dfi);
+-	return 0;
++	return rockchip_dfi_enable(dfi);
+ }
+ 
+ static int rockchip_dfi_set_event(struct devfreq_event_dev *edev)
+@@ -190,8 +212,8 @@ static int rockchip_dfi_get_event(struct
+ }
+ 
+ static const struct devfreq_event_ops rockchip_dfi_ops = {
+-	.disable = rockchip_dfi_disable,
+-	.enable = rockchip_dfi_enable,
++	.disable = rockchip_dfi_event_disable,
++	.enable = rockchip_dfi_event_enable,
+ 	.get_event = rockchip_dfi_get_event,
+ 	.set_event = rockchip_dfi_set_event,
+ };
+@@ -272,6 +294,7 @@ static int rockchip_dfi_probe(struct pla
+ 		return PTR_ERR(dfi->regmap_pmu);
+ 
+ 	dfi->dev = dev;
++	mutex_init(&dfi->mutex);
+ 
+ 	desc = &dfi->desc;
+ 	desc->ops = &rockchip_dfi_ops;
diff --git a/target/linux/rockchip/patches-6.1/403-PM-devfreq-rockchip-dfi-give-variable-a-better-name.patch b/target/linux/rockchip/patches-6.1/403-PM-devfreq-rockchip-dfi-give-variable-a-better-name.patch
new file mode 100644
index 00000000000..73d23d16ed6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/403-PM-devfreq-rockchip-dfi-give-variable-a-better-name.patch
@@ -0,0 +1,78 @@
+From 86d650a48df6685ab1d5133a119e3c8cd2d620be Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:43 +0200
+Subject: [PATCH 403/414] PM / devfreq: rockchip-dfi: give variable a better
+ name
+
+struct dmc_count_channel::total counts the clock cycles of the DDR
+controller. Rename it accordingly to give the reader a better idea
+what this is about. While at it, at some documentation to struct
+dmc_count_channel.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 19 ++++++++++++-------
+ 1 file changed, 12 insertions(+), 7 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -46,9 +46,14 @@
+ #define DDRMON_CH1_COUNT_NUM		0x3c
+ #define DDRMON_CH1_DFI_ACCESS_NUM	0x40
+ 
++/**
++ * struct dmc_count_channel - structure to hold counter values from the DDR controller
++ * @access:       Number of read and write accesses
++ * @clock_cycles: DDR clock cycles
++ */
+ struct dmc_count_channel {
+ 	u32 access;
+-	u32 total;
++	u32 clock_cycles;
+ };
+ 
+ struct dmc_count {
+@@ -150,7 +155,7 @@ static void rockchip_dfi_read_counters(s
+ 			continue;
+ 		count->c[i].access = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+-		count->c[i].total = readl_relaxed(dfi_regs +
++		count->c[i].clock_cycles = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_COUNT_NUM + i * 20);
+ 	}
+ }
+@@ -182,29 +187,29 @@ static int rockchip_dfi_get_event(struct
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+ 	struct dmc_count count;
+ 	struct dmc_count *last = &dfi->last_event_count;
+-	u32 access = 0, total = 0;
++	u32 access = 0, clock_cycles = 0;
+ 	int i;
+ 
+ 	rockchip_dfi_read_counters(dfi, &count);
+ 
+ 	/* We can only report one channel, so find the busiest one */
+ 	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
+-		u32 a, t;
++		u32 a, c;
+ 
+ 		if (!(dfi->channel_mask & BIT(i)))
+ 			continue;
+ 
+ 		a = count.c[i].access - last->c[i].access;
+-		t = count.c[i].total - last->c[i].total;
++		c = count.c[i].clock_cycles - last->c[i].clock_cycles;
+ 
+ 		if (a > access) {
+ 			access = a;
+-			total = t;
++			clock_cycles = c;
+ 		}
+ 	}
+ 
+ 	edata->load_count = access * 4;
+-	edata->total_count = total;
++	edata->total_count = clock_cycles;
+ 
+ 	dfi->last_event_count = count;
+ 
diff --git a/target/linux/rockchip/patches-6.1/404-PM-devfreq-rockchip-dfi-Add-perf-support.patch b/target/linux/rockchip/patches-6.1/404-PM-devfreq-rockchip-dfi-Add-perf-support.patch
new file mode 100644
index 00000000000..23fc9004305
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/404-PM-devfreq-rockchip-dfi-Add-perf-support.patch
@@ -0,0 +1,593 @@
+From 6c88de2b2d35f01b4f6fb7bcbce3f5c928292133 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:44 +0200
+Subject: [PATCH 404/414] PM / devfreq: rockchip-dfi: Add perf support
+
+The DFI is a unit which is suitable for measuring DDR utilization, but
+so far it could only be used as an event driver for the DDR frequency
+scaling driver. This adds perf support to the DFI driver.
+
+Usage with the 'perf' tool can look like:
+
+perf stat -a -e rockchip_ddr/cycles/,\
+		rockchip_ddr/read-bytes/,\
+		rockchip_ddr/write-bytes/,\
+		rockchip_ddr/bytes/ sleep 1
+
+ Performance counter stats for 'system wide':
+
+        1582524826      rockchip_ddr/cycles/
+           1802.25 MB   rockchip_ddr/read-bytes/
+           1793.72 MB   rockchip_ddr/write-bytes/
+           3595.90 MB   rockchip_ddr/bytes/
+
+       1.014369709 seconds time elapsed
+
+perf support has been tested on a RK3568 and a RK3399, the latter with
+dual channel DDR.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 439 ++++++++++++++++++++++++++-
+ include/soc/rockchip/rk3399_grf.h    |   2 +
+ include/soc/rockchip/rk3568_grf.h    |   1 +
+ 3 files changed, 437 insertions(+), 5 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -16,10 +16,12 @@
+ #include <linux/regmap.h>
+ #include <linux/slab.h>
+ #include <linux/list.h>
++#include <linux/seqlock.h>
+ #include <linux/of.h>
+ #include <linux/of_device.h>
+ #include <linux/bitfield.h>
+ #include <linux/bits.h>
++#include <linux/perf_event.h>
+ 
+ #include <soc/rockchip/rockchip_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
+@@ -41,19 +43,39 @@
+ 					 DDRMON_CTRL_LPDDR4 | \
+ 					 DDRMON_CTRL_LPDDR23)
+ 
++#define DDRMON_CH0_WR_NUM		0x20
++#define DDRMON_CH0_RD_NUM		0x24
+ #define DDRMON_CH0_COUNT_NUM		0x28
+ #define DDRMON_CH0_DFI_ACCESS_NUM	0x2c
+ #define DDRMON_CH1_COUNT_NUM		0x3c
+ #define DDRMON_CH1_DFI_ACCESS_NUM	0x40
+ 
++#define PERF_EVENT_CYCLES		0x0
++#define PERF_EVENT_READ_BYTES		0x1
++#define PERF_EVENT_WRITE_BYTES		0x2
++#define PERF_EVENT_READ_BYTES0		0x3
++#define PERF_EVENT_WRITE_BYTES0		0x4
++#define PERF_EVENT_READ_BYTES1		0x5
++#define PERF_EVENT_WRITE_BYTES1		0x6
++#define PERF_EVENT_READ_BYTES2		0x7
++#define PERF_EVENT_WRITE_BYTES2		0x8
++#define PERF_EVENT_READ_BYTES3		0x9
++#define PERF_EVENT_WRITE_BYTES3		0xa
++#define PERF_EVENT_BYTES		0xb
++#define PERF_ACCESS_TYPE_MAX		0xc
++
+ /**
+  * struct dmc_count_channel - structure to hold counter values from the DDR controller
+  * @access:       Number of read and write accesses
+  * @clock_cycles: DDR clock cycles
++ * @read_access:  number of read accesses
++ * @write_acccess: number of write accesses
+  */
+ struct dmc_count_channel {
+-	u32 access;
+-	u32 clock_cycles;
++	u64 access;
++	u64 clock_cycles;
++	u64 read_access;
++	u64 write_access;
+ };
+ 
+ struct dmc_count {
+@@ -69,6 +91,11 @@ struct rockchip_dfi {
+ 	struct devfreq_event_dev *edev;
+ 	struct devfreq_event_desc desc;
+ 	struct dmc_count last_event_count;
++
++	struct dmc_count last_perf_count;
++	struct dmc_count total_count;
++	seqlock_t count_seqlock; /* protects last_perf_count and total_count */
++
+ 	struct device *dev;
+ 	void __iomem *regs;
+ 	struct regmap *regmap_pmu;
+@@ -77,6 +104,14 @@ struct rockchip_dfi {
+ 	struct mutex mutex;
+ 	u32 ddr_type;
+ 	unsigned int channel_mask;
++	enum cpuhp_state cpuhp_state;
++	struct hlist_node node;
++	struct pmu pmu;
++	struct hrtimer timer;
++	unsigned int cpu;
++	int active_events;
++	int burst_len;
++	int buswidth[DMC_MAX_CHANNELS];
+ };
+ 
+ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
+@@ -145,7 +180,7 @@ out:
+ 	mutex_unlock(&dfi->mutex);
+ }
+ 
+-static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *count)
++static void rockchip_dfi_read_counters(struct rockchip_dfi *dfi, struct dmc_count *c)
+ {
+ 	u32 i;
+ 	void __iomem *dfi_regs = dfi->regs;
+@@ -153,13 +188,36 @@ static void rockchip_dfi_read_counters(s
+ 	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
+ 		if (!(dfi->channel_mask & BIT(i)))
+ 			continue;
+-		count->c[i].access = readl_relaxed(dfi_regs +
++		c->c[i].read_access = readl_relaxed(dfi_regs +
++				DDRMON_CH0_RD_NUM + i * 20);
++		c->c[i].write_access = readl_relaxed(dfi_regs +
++				DDRMON_CH0_WR_NUM + i * 20);
++		c->c[i].access = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
+-		count->c[i].clock_cycles = readl_relaxed(dfi_regs +
++		c->c[i].clock_cycles = readl_relaxed(dfi_regs +
+ 				DDRMON_CH0_COUNT_NUM + i * 20);
+ 	}
+ }
+ 
++static void rockchip_ddr_perf_counters_add(struct rockchip_dfi *dfi,
++					   const struct dmc_count *now,
++					   struct dmc_count *res)
++{
++	const struct dmc_count *last = &dfi->last_perf_count;
++	int i;
++
++	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
++		res->c[i].read_access = dfi->total_count.c[i].read_access +
++			(u32)(now->c[i].read_access - last->c[i].read_access);
++		res->c[i].write_access = dfi->total_count.c[i].write_access +
++			(u32)(now->c[i].write_access - last->c[i].write_access);
++		res->c[i].access = dfi->total_count.c[i].access +
++			(u32)(now->c[i].access - last->c[i].access);
++		res->c[i].clock_cycles = dfi->total_count.c[i].clock_cycles +
++			(u32)(now->c[i].clock_cycles - last->c[i].clock_cycles);
++	}
++}
++
+ static int rockchip_dfi_event_disable(struct devfreq_event_dev *edev)
+ {
+ 	struct rockchip_dfi *dfi = devfreq_event_get_drvdata(edev);
+@@ -223,6 +281,367 @@ static const struct devfreq_event_ops ro
+ 	.set_event = rockchip_dfi_set_event,
+ };
+ 
++#ifdef CONFIG_PERF_EVENTS
++
++static ssize_t ddr_perf_cpumask_show(struct device *dev,
++				struct device_attribute *attr, char *buf)
++{
++	struct pmu *pmu = dev_get_drvdata(dev);
++	struct rockchip_dfi *dfi = container_of(pmu, struct rockchip_dfi, pmu);
++
++	return cpumap_print_to_pagebuf(true, buf, cpumask_of(dfi->cpu));
++}
++
++static struct device_attribute ddr_perf_cpumask_attr =
++	__ATTR(cpumask, 0444, ddr_perf_cpumask_show, NULL);
++
++static struct attribute *ddr_perf_cpumask_attrs[] = {
++	&ddr_perf_cpumask_attr.attr,
++	NULL,
++};
++
++static const struct attribute_group ddr_perf_cpumask_attr_group = {
++	.attrs = ddr_perf_cpumask_attrs,
++};
++
++PMU_EVENT_ATTR_STRING(cycles, ddr_pmu_cycles, "event="__stringify(PERF_EVENT_CYCLES))
++
++#define DFI_PMU_EVENT_ATTR(_name, _var, _str) \
++	PMU_EVENT_ATTR_STRING(_name, _var, _str); \
++	PMU_EVENT_ATTR_STRING(_name.unit, _var##_unit, "MB"); \
++	PMU_EVENT_ATTR_STRING(_name.scale, _var##_scale, "9.536743164e-07")
++
++DFI_PMU_EVENT_ATTR(read-bytes0, ddr_pmu_read_bytes0, "event="__stringify(PERF_EVENT_READ_BYTES0));
++DFI_PMU_EVENT_ATTR(write-bytes0, ddr_pmu_write_bytes0, "event="__stringify(PERF_EVENT_WRITE_BYTES0));
++
++DFI_PMU_EVENT_ATTR(read-bytes1, ddr_pmu_read_bytes1, "event="__stringify(PERF_EVENT_READ_BYTES1));
++DFI_PMU_EVENT_ATTR(write-bytes1, ddr_pmu_write_bytes1, "event="__stringify(PERF_EVENT_WRITE_BYTES1));
++
++DFI_PMU_EVENT_ATTR(read-bytes2, ddr_pmu_read_bytes2, "event="__stringify(PERF_EVENT_READ_BYTES2));
++DFI_PMU_EVENT_ATTR(write-bytes2, ddr_pmu_write_bytes2, "event="__stringify(PERF_EVENT_WRITE_BYTES2));
++
++DFI_PMU_EVENT_ATTR(read-bytes3, ddr_pmu_read_bytes3, "event="__stringify(PERF_EVENT_READ_BYTES3));
++DFI_PMU_EVENT_ATTR(write-bytes3, ddr_pmu_write_bytes3, "event="__stringify(PERF_EVENT_WRITE_BYTES3));
++
++DFI_PMU_EVENT_ATTR(read-bytes, ddr_pmu_read_bytes, "event="__stringify(PERF_EVENT_READ_BYTES));
++DFI_PMU_EVENT_ATTR(write-bytes, ddr_pmu_write_bytes, "event="__stringify(PERF_EVENT_WRITE_BYTES));
++
++DFI_PMU_EVENT_ATTR(bytes, ddr_pmu_bytes, "event="__stringify(PERF_EVENT_BYTES));
++
++#define DFI_ATTR_MB(_name) 		\
++	&_name.attr.attr,		\
++	&_name##_unit.attr.attr,	\
++	&_name##_scale.attr.attr
++
++static struct attribute *ddr_perf_events_attrs[] = {
++	&ddr_pmu_cycles.attr.attr,
++	DFI_ATTR_MB(ddr_pmu_read_bytes),
++	DFI_ATTR_MB(ddr_pmu_write_bytes),
++	DFI_ATTR_MB(ddr_pmu_read_bytes0),
++	DFI_ATTR_MB(ddr_pmu_write_bytes0),
++	DFI_ATTR_MB(ddr_pmu_read_bytes1),
++	DFI_ATTR_MB(ddr_pmu_write_bytes1),
++	DFI_ATTR_MB(ddr_pmu_read_bytes2),
++	DFI_ATTR_MB(ddr_pmu_write_bytes2),
++	DFI_ATTR_MB(ddr_pmu_read_bytes3),
++	DFI_ATTR_MB(ddr_pmu_write_bytes3),
++	DFI_ATTR_MB(ddr_pmu_bytes),
++	NULL,
++};
++
++static const struct attribute_group ddr_perf_events_attr_group = {
++	.name = "events",
++	.attrs = ddr_perf_events_attrs,
++};
++
++PMU_FORMAT_ATTR(event, "config:0-7");
++
++static struct attribute *ddr_perf_format_attrs[] = {
++	&format_attr_event.attr,
++	NULL,
++};
++
++static const struct attribute_group ddr_perf_format_attr_group = {
++	.name = "format",
++	.attrs = ddr_perf_format_attrs,
++};
++
++static const struct attribute_group *attr_groups[] = {
++	&ddr_perf_events_attr_group,
++	&ddr_perf_cpumask_attr_group,
++	&ddr_perf_format_attr_group,
++	NULL,
++};
++
++static int rockchip_ddr_perf_event_init(struct perf_event *event)
++{
++	struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
++
++	if (event->attr.type != event->pmu->type)
++		return -ENOENT;
++
++	if (event->attach_state & PERF_ATTACH_TASK)
++		return -EINVAL;
++
++	if (event->cpu < 0) {
++		dev_warn(dfi->dev, "Can't provide per-task data!\n");
++		return -EINVAL;
++	}
++
++	return 0;
++}
++
++static u64 rockchip_ddr_perf_event_get_count(struct perf_event *event)
++{
++	struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
++	int blen = dfi->burst_len;
++	struct dmc_count total, now;
++	unsigned int seq;
++	u64 c = 0;
++	int i;
++
++	rockchip_dfi_read_counters(dfi, &now);
++
++	do {
++		seq = read_seqbegin(&dfi->count_seqlock);
++
++		rockchip_ddr_perf_counters_add(dfi, &now, &total);
++
++	} while (read_seqretry(&dfi->count_seqlock, seq));
++
++	switch (event->attr.config) {
++	case PERF_EVENT_CYCLES:
++		c = total.c[0].clock_cycles;
++		break;
++	case PERF_EVENT_READ_BYTES:
++		for (i = 0; i < DMC_MAX_CHANNELS; i++)
++			c += total.c[i].read_access * blen * dfi->buswidth[i];
++		break;
++	case PERF_EVENT_WRITE_BYTES:
++		for (i = 0; i < DMC_MAX_CHANNELS; i++)
++			c += total.c[i].write_access * blen * dfi->buswidth[i];
++		break;
++	case PERF_EVENT_READ_BYTES0:
++		c = total.c[0].read_access * blen * dfi->buswidth[0];
++		break;
++	case PERF_EVENT_WRITE_BYTES0:
++		c = total.c[0].write_access * blen * dfi->buswidth[0];
++		break;
++	case PERF_EVENT_READ_BYTES1:
++		c = total.c[1].read_access * blen * dfi->buswidth[1];
++		break;
++	case PERF_EVENT_WRITE_BYTES1:
++		c = total.c[1].write_access * blen * dfi->buswidth[1];
++		break;
++	case PERF_EVENT_READ_BYTES2:
++		c = total.c[2].read_access * blen * dfi->buswidth[2];
++		break;
++	case PERF_EVENT_WRITE_BYTES2:
++		c = total.c[2].write_access * blen * dfi->buswidth[2];
++		break;
++	case PERF_EVENT_READ_BYTES3:
++		c = total.c[3].read_access * blen * dfi->buswidth[3];
++		break;
++	case PERF_EVENT_WRITE_BYTES3:
++		c = total.c[3].write_access * blen * dfi->buswidth[3];
++		break;
++	case PERF_EVENT_BYTES:
++		for (i = 0; i < DMC_MAX_CHANNELS; i++)
++			c += total.c[i].access * blen * dfi->buswidth[i];
++		break;
++	}
++
++	return c;
++}
++
++static void rockchip_ddr_perf_event_update(struct perf_event *event)
++{
++	u64 now;
++	s64 prev;
++
++	if (event->attr.config >= PERF_ACCESS_TYPE_MAX)
++		return;
++
++	now = rockchip_ddr_perf_event_get_count(event);
++	prev = local64_xchg(&event->hw.prev_count, now);
++	local64_add(now - prev, &event->count);
++}
++
++static void rockchip_ddr_perf_event_start(struct perf_event *event, int flags)
++{
++	u64 now = rockchip_ddr_perf_event_get_count(event);
++
++	local64_set(&event->hw.prev_count, now);
++}
++
++static int rockchip_ddr_perf_event_add(struct perf_event *event, int flags)
++{
++	struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
++
++	dfi->active_events++;
++
++	if (dfi->active_events == 1)
++		hrtimer_start(&dfi->timer, ns_to_ktime(NSEC_PER_SEC), HRTIMER_MODE_REL);
++
++	if (flags & PERF_EF_START)
++		rockchip_ddr_perf_event_start(event, flags);
++
++	return 0;
++}
++
++static void rockchip_ddr_perf_event_stop(struct perf_event *event, int flags)
++{
++	rockchip_ddr_perf_event_update(event);
++}
++
++static void rockchip_ddr_perf_event_del(struct perf_event *event, int flags)
++{
++	struct rockchip_dfi *dfi = container_of(event->pmu, struct rockchip_dfi, pmu);
++
++	rockchip_ddr_perf_event_stop(event, PERF_EF_UPDATE);
++
++	dfi->active_events--;
++
++	if (dfi->active_events == 0)
++		hrtimer_cancel(&dfi->timer);
++}
++
++static enum hrtimer_restart rockchip_dfi_timer(struct hrtimer *timer)
++{
++	struct rockchip_dfi *dfi = container_of(timer, struct rockchip_dfi, timer);
++	struct dmc_count now, total;
++
++	rockchip_dfi_read_counters(dfi, &now);
++
++	write_seqlock(&dfi->count_seqlock);
++
++	rockchip_ddr_perf_counters_add(dfi, &now, &total);
++	dfi->total_count = total;
++	dfi->last_perf_count = now;
++
++	write_sequnlock(&dfi->count_seqlock);
++
++	hrtimer_forward_now(&dfi->timer, ns_to_ktime(NSEC_PER_SEC));
++
++	return HRTIMER_RESTART;
++};
++
++static int ddr_perf_offline_cpu(unsigned int cpu, struct hlist_node *node)
++{
++	struct rockchip_dfi *dfi = hlist_entry_safe(node, struct rockchip_dfi, node);
++	int target;
++
++	if (cpu != dfi->cpu)
++		return 0;
++
++	target = cpumask_any_but(cpu_online_mask, cpu);
++	if (target >= nr_cpu_ids)
++		return 0;
++
++	perf_pmu_migrate_context(&dfi->pmu, cpu, target);
++	dfi->cpu = target;
++
++	return 0;
++}
++
++static void rockchip_ddr_cpuhp_remove_state(void *data)
++{
++	struct rockchip_dfi *dfi = data;
++
++	cpuhp_remove_multi_state(dfi->cpuhp_state);
++
++	rockchip_dfi_disable(dfi);
++}
++
++static void rockchip_ddr_cpuhp_remove_instance(void *data)
++{
++	struct rockchip_dfi *dfi = data;
++
++	cpuhp_state_remove_instance_nocalls(dfi->cpuhp_state, &dfi->node);
++}
++
++static void rockchip_ddr_perf_remove(void *data)
++{
++	struct rockchip_dfi *dfi = data;
++
++	perf_pmu_unregister(&dfi->pmu);
++}
++
++static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
++{
++	struct pmu *pmu = &dfi->pmu;
++	int ret;
++
++	seqlock_init(&dfi->count_seqlock);
++
++	pmu->module = THIS_MODULE;
++	pmu->capabilities = PERF_PMU_CAP_NO_EXCLUDE;
++	pmu->task_ctx_nr = perf_invalid_context;
++	pmu->attr_groups = attr_groups;
++	pmu->event_init  = rockchip_ddr_perf_event_init;
++	pmu->add = rockchip_ddr_perf_event_add;
++	pmu->del = rockchip_ddr_perf_event_del;
++	pmu->start = rockchip_ddr_perf_event_start;
++	pmu->stop = rockchip_ddr_perf_event_stop;
++	pmu->read = rockchip_ddr_perf_event_update;
++
++	dfi->cpu = raw_smp_processor_id();
++
++	ret = cpuhp_setup_state_multi(CPUHP_AP_ONLINE_DYN,
++				      "rockchip_ddr_perf_pmu",
++				      NULL,
++				      ddr_perf_offline_cpu);
++
++	if (ret < 0) {
++		dev_err(dfi->dev, "cpuhp_setup_state_multi failed: %d\n", ret);
++		return ret;
++	}
++
++	dfi->cpuhp_state = ret;
++
++	rockchip_dfi_enable(dfi);
++
++	ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_state, dfi);
++	if (ret)
++		return ret;
++
++	ret = cpuhp_state_add_instance_nocalls(dfi->cpuhp_state, &dfi->node);
++	if (ret) {
++		dev_err(dfi->dev, "Error %d registering hotplug\n", ret);
++		return ret;
++	}
++
++	ret = devm_add_action_or_reset(dfi->dev, rockchip_ddr_cpuhp_remove_instance, dfi);
++	if (ret)
++		return ret;
++
++	hrtimer_init(&dfi->timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
++	dfi->timer.function = rockchip_dfi_timer;
++
++	switch (dfi->ddr_type) {
++	case ROCKCHIP_DDRTYPE_LPDDR2:
++	case ROCKCHIP_DDRTYPE_LPDDR3:
++		dfi->burst_len = 8;
++		break;
++	case ROCKCHIP_DDRTYPE_LPDDR4:
++	case ROCKCHIP_DDRTYPE_LPDDR4X:
++		dfi->burst_len = 16;
++		break;
++	}
++
++	ret = perf_pmu_register(pmu, "rockchip_ddr", -1);
++	if (ret)
++		return ret;
++
++	return devm_add_action_or_reset(dfi->dev, rockchip_ddr_perf_remove, dfi);
++}
++#else
++static int rockchip_ddr_perf_init(struct rockchip_dfi *dfi)
++{
++	return 0;
++}
++#endif
++
+ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
+ {
+ 	struct regmap *regmap_pmu = dfi->regmap_pmu;
+@@ -239,6 +658,9 @@ static int rk3399_dfi_init(struct rockch
+ 
+ 	dfi->channel_mask = GENMASK(1, 0);
+ 
++	dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
++	dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
++
+ 	return 0;
+ };
+ 
+@@ -255,6 +677,8 @@ static int rk3568_dfi_init(struct rockch
+ 	if (FIELD_GET(RK3568_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
+ 		dfi->ddr_type |= FIELD_GET(RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
+ 
++	dfi->buswidth[0] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
++
+ 	dfi->channel_mask = 1;
+ 
+ 	return 0;
+@@ -317,6 +741,10 @@ static int rockchip_dfi_probe(struct pla
+ 		return PTR_ERR(dfi->edev);
+ 	}
+ 
++	ret = rockchip_ddr_perf_init(dfi);
++	if (ret)
++		return ret;
++
+ 	platform_set_drvdata(pdev, dfi);
+ 
+ 	return 0;
+@@ -327,6 +755,7 @@ static struct platform_driver rockchip_d
+ 	.driver = {
+ 		.name	= "rockchip-dfi",
+ 		.of_match_table = rockchip_dfi_id_match,
++		.suppress_bind_attrs = true,
+ 	},
+ };
+ module_platform_driver(rockchip_dfi_driver);
+--- a/include/soc/rockchip/rk3399_grf.h
++++ b/include/soc/rockchip/rk3399_grf.h
+@@ -12,5 +12,7 @@
+ /* PMU GRF Registers */
+ #define RK3399_PMUGRF_OS_REG2		0x308
+ #define RK3399_PMUGRF_OS_REG2_DDRTYPE		GENMASK(15, 13)
++#define RK3399_PMUGRF_OS_REG2_BW_CH0		GENMASK(3, 2)
++#define RK3399_PMUGRF_OS_REG2_BW_CH1		GENMASK(19, 18)
+ 
+ #endif
+--- a/include/soc/rockchip/rk3568_grf.h
++++ b/include/soc/rockchip/rk3568_grf.h
+@@ -4,6 +4,7 @@
+ 
+ #define RK3568_PMUGRF_OS_REG2		0x208
+ #define RK3568_PMUGRF_OS_REG2_DRAMTYPE_INFO		GENMASK(15, 13)
++#define RK3568_PMUGRF_OS_REG2_BW_CH0			GENMASK(3, 2)
+ 
+ #define RK3568_PMUGRF_OS_REG3		0x20c
+ #define RK3568_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3		GENMASK(13, 12)
diff --git a/target/linux/rockchip/patches-6.1/405-PM-devfreq-rockchip-dfi-make-register-stride-SoC-spe.patch b/target/linux/rockchip/patches-6.1/405-PM-devfreq-rockchip-dfi-make-register-stride-SoC-spe.patch
new file mode 100644
index 00000000000..a9b515587df
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/405-PM-devfreq-rockchip-dfi-make-register-stride-SoC-spe.patch
@@ -0,0 +1,56 @@
+From 1067b1854ad723a3cd57f76924fb3c7ddea6f22e Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:45 +0200
+Subject: [PATCH 405/414] PM / devfreq: rockchip-dfi: make register stride SoC
+ specific
+
+The currently supported RK3399 has a stride of 20 between the channel
+specific registers. Upcoming RK3588 has a different stride, so put
+the stride into driver data to make it configurable.
+While at it convert decimal 20 to hex 0x14 for consistency with RK3588
+which has a register stride 0x4000 and we want to write that in hex
+as well.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 11 +++++++----
+ 1 file changed, 7 insertions(+), 4 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -112,6 +112,7 @@ struct rockchip_dfi {
+ 	int active_events;
+ 	int burst_len;
+ 	int buswidth[DMC_MAX_CHANNELS];
++	int ddrmon_stride;
+ };
+ 
+ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
+@@ -189,13 +190,13 @@ static void rockchip_dfi_read_counters(s
+ 		if (!(dfi->channel_mask & BIT(i)))
+ 			continue;
+ 		c->c[i].read_access = readl_relaxed(dfi_regs +
+-				DDRMON_CH0_RD_NUM + i * 20);
++				DDRMON_CH0_RD_NUM + i * dfi->ddrmon_stride);
+ 		c->c[i].write_access = readl_relaxed(dfi_regs +
+-				DDRMON_CH0_WR_NUM + i * 20);
++				DDRMON_CH0_WR_NUM + i * dfi->ddrmon_stride);
+ 		c->c[i].access = readl_relaxed(dfi_regs +
+-				DDRMON_CH0_DFI_ACCESS_NUM + i * 20);
++				DDRMON_CH0_DFI_ACCESS_NUM + i * dfi->ddrmon_stride);
+ 		c->c[i].clock_cycles = readl_relaxed(dfi_regs +
+-				DDRMON_CH0_COUNT_NUM + i * 20);
++				DDRMON_CH0_COUNT_NUM + i * dfi->ddrmon_stride);
+ 	}
+ }
+ 
+@@ -661,6 +662,8 @@ static int rk3399_dfi_init(struct rockch
+ 	dfi->buswidth[0] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH0, val) == 0 ? 4 : 2;
+ 	dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
+ 
++	dfi->ddrmon_stride = 0x14;
++
+ 	return 0;
+ };
+ 
diff --git a/target/linux/rockchip/patches-6.1/406-PM-devfreq-rockchip-dfi-account-for-multiple-DDRMON_.patch b/target/linux/rockchip/patches-6.1/406-PM-devfreq-rockchip-dfi-account-for-multiple-DDRMON_.patch
new file mode 100644
index 00000000000..19128ce243b
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/406-PM-devfreq-rockchip-dfi-account-for-multiple-DDRMON_.patch
@@ -0,0 +1,137 @@
+From 69dbc52aef08f566494ae5da340dc708c3f3e362 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:46 +0200
+Subject: [PATCH 406/414] PM / devfreq: rockchip-dfi: account for multiple
+ DDRMON_CTRL registers
+
+The currently supported RK3399 has a set of registers per channel, but
+it has only a single DDRMON_CTRL register. With upcoming RK3588 this
+will be different, the RK3588 has a DDRMON_CTRL register per channel.
+
+Instead of expecting a single DDRMON_CTRL register, loop over the
+channels and write the channel specific DDRMON_CTRL register. Break
+out early out of the loop when there is only a single DDRMON_CTRL
+register like on the RK3399.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 72 ++++++++++++++++++----------
+ 1 file changed, 48 insertions(+), 24 deletions(-)
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -113,12 +113,13 @@ struct rockchip_dfi {
+ 	int burst_len;
+ 	int buswidth[DMC_MAX_CHANNELS];
+ 	int ddrmon_stride;
++	bool ddrmon_ctrl_single;
+ };
+ 
+ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
+ {
+ 	void __iomem *dfi_regs = dfi->regs;
+-	int ret = 0;
++	int i, ret = 0;
+ 
+ 	mutex_lock(&dfi->mutex);
+ 
+@@ -132,29 +133,41 @@ static int rockchip_dfi_enable(struct ro
+ 		goto out;
+ 	}
+ 
+-	/* clear DDRMON_CTRL setting */
+-	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN | DDRMON_CTRL_SOFTWARE_EN |
+-		       DDRMON_CTRL_HARDWARE_EN), dfi_regs + DDRMON_CTRL);
++	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
++		u32 ctrl = 0;
+ 
+-	/* set ddr type to dfi */
+-	switch (dfi->ddr_type) {
+-	case ROCKCHIP_DDRTYPE_LPDDR2:
+-	case ROCKCHIP_DDRTYPE_LPDDR3:
+-		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
+-			       dfi_regs + DDRMON_CTRL);
+-		break;
+-	case ROCKCHIP_DDRTYPE_LPDDR4:
+-	case ROCKCHIP_DDRTYPE_LPDDR4X:
+-		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
+-			       dfi_regs + DDRMON_CTRL);
+-		break;
+-	default:
+-		break;
+-	}
++		if (!(dfi->channel_mask & BIT(i)))
++			continue;
+ 
+-	/* enable count, use software mode */
+-	writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
+-		       dfi_regs + DDRMON_CTRL);
++		/* clear DDRMON_CTRL setting */
++		writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_TIMER_CNT_EN |
++			       DDRMON_CTRL_SOFTWARE_EN | DDRMON_CTRL_HARDWARE_EN),
++			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
++
++		/* set ddr type to dfi */
++		switch (dfi->ddr_type) {
++		case ROCKCHIP_DDRTYPE_LPDDR2:
++		case ROCKCHIP_DDRTYPE_LPDDR3:
++			ctrl = DDRMON_CTRL_LPDDR23;
++			break;
++		case ROCKCHIP_DDRTYPE_LPDDR4:
++		case ROCKCHIP_DDRTYPE_LPDDR4X:
++			ctrl = DDRMON_CTRL_LPDDR4;
++			break;
++		default:
++			break;
++		}
++
++		writel_relaxed(HIWORD_UPDATE(ctrl, DDRMON_CTRL_DDR_TYPE_MASK),
++			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
++
++		/* enable count, use software mode */
++		writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
++			       dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
++
++		if (dfi->ddrmon_ctrl_single)
++			break;
++	}
+ out:
+ 	mutex_unlock(&dfi->mutex);
+ 
+@@ -164,6 +177,7 @@ out:
+ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
+ {
+ 	void __iomem *dfi_regs = dfi->regs;
++	int i;
+ 
+ 	mutex_lock(&dfi->mutex);
+ 
+@@ -174,8 +188,17 @@ static void rockchip_dfi_disable(struct
+ 	if (dfi->usecount > 0)
+ 		goto out;
+ 
+-	writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+-		       dfi_regs + DDRMON_CTRL);
++	for (i = 0; i < DMC_MAX_CHANNELS; i++) {
++		if (!(dfi->channel_mask & BIT(i)))
++			continue;
++
++		writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
++			      dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
++
++		if (dfi->ddrmon_ctrl_single)
++			break;
++	}
++
+ 	clk_disable_unprepare(dfi->clk);
+ out:
+ 	mutex_unlock(&dfi->mutex);
+@@ -663,6 +686,7 @@ static int rk3399_dfi_init(struct rockch
+ 	dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
+ 
+ 	dfi->ddrmon_stride = 0x14;
++	dfi->ddrmon_ctrl_single = true;
+ 
+ 	return 0;
+ };
diff --git a/target/linux/rockchip/patches-6.1/407-PM-devfreq-rockchip-dfi-add-support-for-RK3588.patch b/target/linux/rockchip/patches-6.1/407-PM-devfreq-rockchip-dfi-add-support-for-RK3588.patch
new file mode 100644
index 00000000000..fe3e6a41be4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/407-PM-devfreq-rockchip-dfi-add-support-for-RK3588.patch
@@ -0,0 +1,88 @@
+From 8da074c57e10e444f8c21532eda1e6e72cba8e06 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:47 +0200
+Subject: [PATCH 407/414] PM / devfreq: rockchip-dfi: add support for RK3588
+
+Add support for the RK3588 to the driver. The RK3588 has four DDR
+channels with a register stride of 0x4000 between the channel
+registers, also it has a DDRMON_CTRL register per channel.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
+---
+ drivers/devfreq/event/rockchip-dfi.c | 30 +++++++++++++++++++++++++++-
+ include/soc/rockchip/rk3588_grf.h    | 18 +++++++++++++++++
+ 2 files changed, 47 insertions(+), 1 deletion(-)
+ create mode 100644 include/soc/rockchip/rk3588_grf.h
+
+--- a/drivers/devfreq/event/rockchip-dfi.c
++++ b/drivers/devfreq/event/rockchip-dfi.c
+@@ -26,8 +26,9 @@
+ #include <soc/rockchip/rockchip_grf.h>
+ #include <soc/rockchip/rk3399_grf.h>
+ #include <soc/rockchip/rk3568_grf.h>
++#include <soc/rockchip/rk3588_grf.h>
+ 
+-#define DMC_MAX_CHANNELS	2
++#define DMC_MAX_CHANNELS	4
+ 
+ #define HIWORD_UPDATE(val, mask)	((val) | (mask) << 16)
+ 
+@@ -711,9 +712,36 @@ static int rk3568_dfi_init(struct rockch
+ 	return 0;
+ };
+ 
++static int rk3588_dfi_init(struct rockchip_dfi *dfi)
++{
++	struct regmap *regmap_pmu = dfi->regmap_pmu;
++	u32 reg2, reg3, reg4;
++
++	regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG2, &reg2);
++	regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG3, &reg3);
++	regmap_read(regmap_pmu, RK3588_PMUGRF_OS_REG4, &reg4);
++
++	dfi->ddr_type = FIELD_GET(RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO, reg2);
++
++	if (FIELD_GET(RK3588_PMUGRF_OS_REG3_SYSREG_VERSION, reg3) >= 0x3)
++		dfi->ddr_type |= FIELD_GET(RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3, reg3) << 3;
++
++	dfi->buswidth[0] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH0, reg2) == 0 ? 4 : 2;
++	dfi->buswidth[1] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg2) == 0 ? 4 : 2;
++	dfi->buswidth[2] = FIELD_GET(RK3568_PMUGRF_OS_REG2_BW_CH0, reg4) == 0 ? 4 : 2;
++	dfi->buswidth[3] = FIELD_GET(RK3588_PMUGRF_OS_REG2_BW_CH1, reg4) == 0 ? 4 : 2;
++	dfi->channel_mask = FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg2) |
++			    FIELD_GET(RK3588_PMUGRF_OS_REG2_CH_INFO, reg4) << 2;
++
++	dfi->ddrmon_stride = 0x4000;
++
++	return 0;
++};
++
+ static const struct of_device_id rockchip_dfi_id_match[] = {
+ 	{ .compatible = "rockchip,rk3399-dfi", .data = rk3399_dfi_init },
+ 	{ .compatible = "rockchip,rk3568-dfi", .data = rk3568_dfi_init },
++	{ .compatible = "rockchip,rk3588-dfi", .data = rk3588_dfi_init },
+ 	{ },
+ };
+ 
+--- /dev/null
++++ b/include/soc/rockchip/rk3588_grf.h
+@@ -0,0 +1,18 @@
++/* SPDX-License-Identifier: GPL-2.0+ */
++#ifndef __SOC_RK3588_GRF_H
++#define __SOC_RK3588_GRF_H
++
++#define RK3588_PMUGRF_OS_REG2		0x208
++#define RK3588_PMUGRF_OS_REG2_DRAMTYPE_INFO		GENMASK(15, 13)
++#define RK3588_PMUGRF_OS_REG2_BW_CH0			GENMASK(3, 2)
++#define RK3588_PMUGRF_OS_REG2_BW_CH1                    GENMASK(19, 18)
++#define RK3588_PMUGRF_OS_REG2_CH_INFO                   GENMASK(29, 28)
++
++#define RK3588_PMUGRF_OS_REG3		0x20c
++#define RK3588_PMUGRF_OS_REG3_DRAMTYPE_INFO_V3		GENMASK(13, 12)
++#define RK3588_PMUGRF_OS_REG3_SYSREG_VERSION		GENMASK(31, 28)
++
++#define RK3588_PMUGRF_OS_REG4           0x210
++#define RK3588_PMUGRF_OS_REG5           0x214
++
++#endif /* __SOC_RK3588_GRF_H */
diff --git a/target/linux/rockchip/patches-6.1/408-dt-bindings-devfreq-event-convert-Rockchip-DFI-bindi.patch b/target/linux/rockchip/patches-6.1/408-dt-bindings-devfreq-event-convert-Rockchip-DFI-bindi.patch
new file mode 100644
index 00000000000..465ea7c9f02
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/408-dt-bindings-devfreq-event-convert-Rockchip-DFI-bindi.patch
@@ -0,0 +1,114 @@
+From a2f12b66bfdb39992e3ada96bfb1e677a440fcce Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:48 +0200
+Subject: [PATCH 408/414] dt-bindings: devfreq: event: convert Rockchip DFI
+ binding to yaml
+
+Convert the Rockchip DFI binding to yaml.
+
+Reviewed-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ .../bindings/devfreq/event/rockchip,dfi.yaml  | 61 +++++++++++++++++++
+ .../bindings/devfreq/event/rockchip-dfi.txt   | 18 ------
+ .../rockchip,rk3399-dmc.yaml                  |  2 +-
+ 3 files changed, 62 insertions(+), 19 deletions(-)
+ create mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
+ delete mode 100644 Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
+
+--- /dev/null
++++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
+@@ -0,0 +1,61 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/devfreq/event/rockchip,dfi.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Rockchip DFI
++
++maintainers:
++  - Sascha Hauer <s.hauer@pengutronix.de>
++
++properties:
++  compatible:
++    enum:
++      - rockchip,rk3399-dfi
++
++  clocks:
++    maxItems: 1
++
++  clock-names:
++    items:
++      - const: pclk_ddr_mon
++
++  interrupts:
++    maxItems: 1
++
++  reg:
++    maxItems: 1
++
++  rockchip,pmu:
++    $ref: /schemas/types.yaml#/definitions/phandle
++    description:
++      Phandle to the syscon managing the "PMU general register files".
++
++required:
++  - compatible
++  - clocks
++  - clock-names
++  - interrupts
++  - reg
++
++additionalProperties: false
++
++examples:
++  - |
++    #include <dt-bindings/interrupt-controller/arm-gic.h>
++    #include <dt-bindings/clock/rk3308-cru.h>
++
++    bus {
++      #address-cells = <2>;
++      #size-cells = <2>;
++
++      dfi: dfi@ff630000 {
++        compatible = "rockchip,rk3399-dfi";
++        reg = <0x00 0xff630000 0x00 0x4000>;
++        interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
++        rockchip,pmu = <&pmugrf>;
++        clocks = <&cru PCLK_DDR_MON>;
++        clock-names = "pclk_ddr_mon";
++      };
++    };
+--- a/Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt
++++ /dev/null
+@@ -1,18 +0,0 @@
+-
+-* Rockchip rk3399 DFI device
+-
+-Required properties:
+-- compatible: Must be "rockchip,rk3399-dfi".
+-- reg: physical base address of each DFI and length of memory mapped region
+-- rockchip,pmu: phandle to the syscon managing the "pmu general register files"
+-- clocks: phandles for clock specified in "clock-names" property
+-- clock-names : the name of clock used by the DFI, must be "pclk_ddr_mon";
+-
+-Example:
+-	dfi: dfi@ff630000 {
+-		compatible = "rockchip,rk3399-dfi";
+-		reg = <0x00 0xff630000 0x00 0x4000>;
+-		rockchip,pmu = <&pmugrf>;
+-		clocks = <&cru PCLK_DDR_MON>;
+-		clock-names = "pclk_ddr_mon";
+-	};
+--- a/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
++++ b/Documentation/devicetree/bindings/memory-controllers/rockchip,rk3399-dmc.yaml
+@@ -18,7 +18,7 @@ properties:
+     $ref: /schemas/types.yaml#/definitions/phandle
+     description:
+       Node to get DDR loading. Refer to
+-      Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt.
++      Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml.
+ 
+   clocks:
+     maxItems: 1
diff --git a/target/linux/rockchip/patches-6.1/409-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3568-su.patch b/target/linux/rockchip/patches-6.1/409-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3568-su.patch
new file mode 100644
index 00000000000..5a8e732e160
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/409-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3568-su.patch
@@ -0,0 +1,50 @@
+From cac156a68588ae687fd0be8615fc9918e9b2fe86 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:49 +0200
+Subject: [PATCH 409/414] dt-bindings: devfreq: event: rockchip,dfi: Add rk3568
+ support
+
+This adds the rockchip,rk3568-dfi compatible to the binding. Make clocks
+optional for this SoC as the RK3568 doesn't have a kernel controllable
+PCLK.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+---
+ .../bindings/devfreq/event/rockchip,dfi.yaml      | 15 +++++++++++++--
+ 1 file changed, 13 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
++++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
+@@ -13,6 +13,7 @@ properties:
+   compatible:
+     enum:
+       - rockchip,rk3399-dfi
++      - rockchip,rk3568-dfi
+ 
+   clocks:
+     maxItems: 1
+@@ -34,11 +35,21 @@ properties:
+ 
+ required:
+   - compatible
+-  - clocks
+-  - clock-names
+   - interrupts
+   - reg
+ 
++if:
++  properties:
++    compatible:
++      contains:
++        enum:
++          - rockchip,rk3399-dfi
++
++then:
++  required:
++    - clocks
++    - clock-names
++
+ additionalProperties: false
+ 
+ examples:
diff --git a/target/linux/rockchip/patches-6.1/410-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3588-su.patch b/target/linux/rockchip/patches-6.1/410-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3588-su.patch
new file mode 100644
index 00000000000..fb6353496e3
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/410-dt-bindings-devfreq-event-rockchip-dfi-Add-rk3588-su.patch
@@ -0,0 +1,46 @@
+From e56c1a25f8be8fef58e190674bcd099a0e466652 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:50 +0200
+Subject: [PATCH 410/414] dt-bindings: devfreq: event: rockchip,dfi: Add rk3588
+ support
+
+This adds rockchip,rk3588-dfi to the list of compatibles. Unlike ealier
+SoCs the rk3588 has four interrupts (one for each channel) instead of
+only one, so increase the number of allowed interrupts to four and also
+add interrupt-names.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ .../bindings/devfreq/event/rockchip,dfi.yaml       | 14 +++++++++++++-
+ 1 file changed, 13 insertions(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
++++ b/Documentation/devicetree/bindings/devfreq/event/rockchip,dfi.yaml
+@@ -14,6 +14,7 @@ properties:
+     enum:
+       - rockchip,rk3399-dfi
+       - rockchip,rk3568-dfi
++      - rockchip,rk3588-dfi
+ 
+   clocks:
+     maxItems: 1
+@@ -23,7 +24,18 @@ properties:
+       - const: pclk_ddr_mon
+ 
+   interrupts:
+-    maxItems: 1
++    minItems: 1
++    maxItems: 4
++
++  interrupt-names:
++    oneOf:
++      - items:
++          - const: ch0
++      - items:
++          - const: ch0
++          - const: ch1
++          - const: ch2
++          - const: ch3
+ 
+   reg:
+     maxItems: 1
diff --git a/target/linux/rockchip/patches-6.1/411-arm64-dts-rockchip-rk3399-Enable-DFI.patch b/target/linux/rockchip/patches-6.1/411-arm64-dts-rockchip-rk3399-Enable-DFI.patch
new file mode 100644
index 00000000000..050eeb26028
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/411-arm64-dts-rockchip-rk3399-Enable-DFI.patch
@@ -0,0 +1,24 @@
+From 6bda3afaebc2e69491f09e469dd5d72b94547a09 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:51 +0200
+Subject: [PATCH 411/414] arm64: dts: rockchip: rk3399: Enable DFI
+
+the DFI unit can provide useful data for measuring DDR utilization
+and works without any configuration from the board, so enable it in the
+dtsi file directly.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3399.dtsi | 1 -
+ 1 file changed, 1 deletion(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
+@@ -1333,7 +1333,6 @@
+ 		interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		clocks = <&cru PCLK_DDR_MON>;
+ 		clock-names = "pclk_ddr_mon";
+-		status = "disabled";
+ 	};
+ 
+ 	vpu: video-codec@ff650000 {
diff --git a/target/linux/rockchip/patches-6.1/412-arm64-dts-rockchip-rk356x-Add-DFI.patch b/target/linux/rockchip/patches-6.1/412-arm64-dts-rockchip-rk356x-Add-DFI.patch
new file mode 100644
index 00000000000..ce9dceb74f4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/412-arm64-dts-rockchip-rk356x-Add-DFI.patch
@@ -0,0 +1,29 @@
+From 512c554e882c8e326bffb5d8ac1d5f22d5b85012 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:52 +0200
+Subject: [PATCH 412/414] arm64: dts: rockchip: rk356x: Add DFI
+
+The DFI unit can be used to measure DRAM utilization using perf. Add the
+node to the device tree.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ arch/arm64/boot/dts/rockchip/rk356x.dtsi | 7 +++++++
+ 1 file changed, 7 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+@@ -959,6 +959,13 @@
+ 		reg = <0x0 0xfe1a8100 0x0 0x20>;
+ 	};
+ 
++	dfi: dfi@fe230000 {
++		compatible = "rockchip,rk3568-dfi";
++		reg = <0x00 0xfe230000 0x00 0x400>;
++		interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
++		rockchip,pmu = <&pmugrf>;
++	};
++
+ 	pcie2x1: pcie@fe260000 {
+ 		compatible = "rockchip,rk3568-pcie";
+ 		reg = <0x3 0xc0000000 0x0 0x00400000>,
diff --git a/target/linux/rockchip/patches-6.1/413-arm64-dts-rockchip-rk3588s-Add-DFI.patch b/target/linux/rockchip/patches-6.1/413-arm64-dts-rockchip-rk3588s-Add-DFI.patch
new file mode 100644
index 00000000000..386356845b6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/413-arm64-dts-rockchip-rk3588s-Add-DFI.patch
@@ -0,0 +1,47 @@
+From 2c76e96fe9d6237430b1cbe64907ab40bc09f315 Mon Sep 17 00:00:00 2001
+From: Sascha Hauer <s.hauer@pengutronix.de>
+Date: Wed, 24 May 2023 10:31:53 +0200
+Subject: [PATCH 413/414] arm64: dts: rockchip: rk3588s: Add DFI
+
+The DFI unit can be used to measure DRAM utilization using perf. Add the
+node to the device tree. The DFI needs a rockchip,pmu phandle to the pmu
+containing registers for SDRAM configuration details. This is added in
+this patch as well.
+
+Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 ++++++++++++++++
+ 1 file changed, 16 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -945,6 +945,11 @@
+ 		};
+ 	};
+ 
++	pmu1grf: syscon@fd58a000 {
++		compatible = "rockchip,rk3588-pmugrf", "syscon", "simple-mfd";
++		reg = <0x0 0xfd58a000 0x0 0x10000>;
++	};
++
+ 	sys_grf: syscon@fd58c000 {
+ 		compatible = "rockchip,rk3588-sys-grf", "syscon";
+ 		reg = <0x0 0xfd58c000 0x0 0x1000>;
+@@ -1890,6 +1895,17 @@
+ 		};
+ 	};
+ 
++	dfi: dfi@fe060000 {
++		reg = <0x00 0xfe060000 0x00 0x10000>;
++		compatible = "rockchip,rk3588-dfi";
++		interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "ch0", "ch1", "ch2", "ch3";
++		rockchip,pmu = <&pmu1grf>;
++	};
++
+ 	gmac1: ethernet@fe1c0000 {
+ 		compatible = "rockchip,rk3588-gmac", "snps,dwmac-4.20a";
+ 		reg = <0x0 0xfe1c0000 0x0 0x10000>;
diff --git a/target/linux/rockchip/patches-6.1/414-arm64-dts-rockchip-rk3588-add-cpu-2.4-GHz-operating-.patch b/target/linux/rockchip/patches-6.1/414-arm64-dts-rockchip-rk3588-add-cpu-2.4-GHz-operating-.patch
new file mode 100644
index 00000000000..2e5a3b32342
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/414-arm64-dts-rockchip-rk3588-add-cpu-2.4-GHz-operating-.patch
@@ -0,0 +1,39 @@
+From b47e957a3e8f2c70d1c265fb2334ab1de31c2aef Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Fri, 2 Jun 2023 02:56:41 -0400
+Subject: [PATCH 414/414] arm64: dts: rockchip: rk3588: add cpu 2.4 GHz
+ operating point
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 12 ++++++++++++
+ 1 file changed, 12 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -149,6 +149,12 @@
+ 					<925000 925000 1000000>;
+ 			clock-latency-ns = <40000>;
+ 		};
++		opp-2400000000 {
++			opp-hz = /bits/ 64 <2400000000>;
++			opp-microvolt = <1000000 1000000 1000000>,
++					<1000000 1000000 1000000>;
++			clock-latency-ns = <40000>;
++		};
+ 	};
+ 
+ 	cluster2_opp_table: opp-table-cluster2 {
+@@ -226,6 +232,12 @@
+ 					<925000 925000 1000000>;
+ 			clock-latency-ns = <40000>;
+ 		};
++		opp-2400000000 {
++			opp-hz = /bits/ 64 <2400000000>;
++			opp-microvolt = <1000000 1000000 1000000>,
++					<1000000 1000000 1000000>;
++			clock-latency-ns = <40000>;
++		};
+ 	};
+ 
+ 	cpus {
diff --git a/target/linux/rockchip/patches-6.1/416-dt-bindings-iio-rockchip-Fix-oneOf-condition-failed-.patch b/target/linux/rockchip/patches-6.1/416-dt-bindings-iio-rockchip-Fix-oneOf-condition-failed-.patch
new file mode 100644
index 00000000000..7b18cceec3c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/416-dt-bindings-iio-rockchip-Fix-oneOf-condition-failed-.patch
@@ -0,0 +1,37 @@
+From 3e3c84448422ec7c86db84a539ad9cfcc62dd4c2 Mon Sep 17 00:00:00 2001
+From: Shreeya Patel <shreeya.patel@collabora.com>
+Date: Sat, 10 Jun 2023 20:06:01 +0530
+Subject: [PATCH] dt-bindings: iio: rockchip: Fix 'oneOf' condition failed
+ warning
+
+rk3588-saradc isn't compatible with the rk3399-saradc variant,
+hence, fix the following dtbs_check warning for 'oneOf' condition
+failure.
+
+DTC_CHK arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb
+/home/shreeya/linux/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dtb:
+	saradc@fec10000: compatible: 'oneOf' conditional failed,
+	one must be fixed:
+	['rockchip,rk3588-saradc'] is too short
+	'rockchip,saradc' was expected
+	'rockchip,rk3066-tsadc' was expected
+	'rockchip,rk3399-saradc' was expected
+
+Fixes: 2daf2ae9793d ("dt-bindings: iio: adc: Add rockchip,rk3588-saradc string")
+Signed-off-by: Shreeya Patel <shreeya.patel@collabora.com>
+Reviewed-by: Heiko Stuebner <heiko@sntech.de>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+---
+ Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
++++ b/Documentation/devicetree/bindings/iio/adc/rockchip-saradc.yaml
+@@ -15,6 +15,7 @@ properties:
+       - const: rockchip,saradc
+       - const: rockchip,rk3066-tsadc
+       - const: rockchip,rk3399-saradc
++      - const: rockchip,rk3588-saradc
+       - items:
+           - enum:
+               - rockchip,px30-saradc
diff --git a/target/linux/rockchip/patches-6.1/417-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch b/target/linux/rockchip/patches-6.1/417-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch
new file mode 100644
index 00000000000..9862d4528e2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/417-rockchip-add-FriendlyElec-NanoPi-R6C-Plus.patch
@@ -0,0 +1,144 @@
+From ba70dba1ea8347003c94f0fdad00ff6dd765408c Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Tue, 13 Jun 2023 02:40:07 -0400
+Subject: [PATCH] rockchip: add FriendlyElec NanoPi R6C Plus
+
+Signed-off-by: Marty Jones <mj8263788@gmail.com>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../dts/rockchip/rk3588s-nanopi-r6c-plus.dts  | 121 ++++++++++++++++++
+ 2 files changed, 122 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c-plus.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -104,4 +104,5 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-i
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-khadas-edge2.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-nanopi-r6c-plus.dts
+@@ -0,0 +1,121 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++/*
++ * Copyright (c) 2022 FriendlyElec Computer Tech. Co., Ltd.
++ * (http://www.friendlyelec.com)
++ * Copyright (c) 2023, Marty Jones <mj8263788@gmail.com
++ * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
++ */
++
++/dts-v1/;
++
++#include "rk3588-nanopi6-common.dtsi"
++
++/ {
++	model = "FriendlyElec NanoPi R6C Plus";
++	compatible = "friendlyelec,nanopi-r6c-plus", "rockchip,rk3588";
++
++	aliases {
++		mmc0 = &sdmmc;
++		mmc1 = &sdhci;
++		ethernet0 = &gmac1;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	gpio_keys: gpio-keys {
++		compatible = "gpio-keys";
++		pinctrl-names = "default";
++		pinctrl-0 = <&key1_pin>;
++	};
++
++	gpio_leds: gpio-leds {
++		compatible = "gpio-leds";
++
++		sys_led: led-sys {
++			gpios = <&gpio1 RK_PC1 GPIO_ACTIVE_HIGH>;
++			label = "red:sys";
++			linux,default-trigger = "heartbeat";
++			pinctrl-names = "default";
++			pinctrl-0 = <&sys_led_pin>;
++		};
++
++		wan_led: led-wan {
++			gpios = <&gpio1 RK_PC2 GPIO_ACTIVE_HIGH>;
++			label = "green:wan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&wan_led_pin>;
++		};
++
++		lan_led: led-lan {
++			gpios = <&gpio1 RK_PC3 GPIO_ACTIVE_HIGH>;
++			label = "green:lan";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan1_led_pin>;
++		};
++
++		lan2_led: led-lan2 {
++			gpios = <&gpio1 RK_PC4 GPIO_ACTIVE_HIGH>;
++			label = "green:lan1";
++			pinctrl-names = "default";
++			pinctrl-0 = <&lan2_led_pin>;
++		};
++	};
++};
++
++
++&pinctrl {
++	gpio-key {
++		key1_pin: key1-pin {
++			rockchip,pins = <1 RK_PC0 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++	};
++
++	gpio-leds {
++		sys_led_pin: sys-led-pin {
++			rockchip,pins =
++				<1 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		wan_led_pin: wan-led-pin {
++			rockchip,pins =
++				<1 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan1_led_pin: lan1-led-pin {
++			rockchip,pins =
++				<1 RK_PC3 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++
++		lan2_led_pin: lan2-led-pin {
++			rockchip,pins =
++				<1 RK_PC4 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb {
++		vcc5v0_host20_en: vcc5v0-host20-en {
++			rockchip,pins = <4 RK_PB5 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&i2c6 {
++	clock-frequency = <200000>;
++	status = "okay";
++
++	eeprom@53 {
++		compatible = "microchip,24c02", "atmel,24c02";
++		reg = <0x53>;
++		#address-cells = <2>;
++		#size-cells = <0>;
++		pagesize = <16>;
++		size = <256>;
++
++		eui_48: eui-48@fa {
++			reg = <0xfa 0x06>;
++		};
++	};
++};
diff --git a/target/linux/rockchip/patches-6.1/418-irqchip-gic-v3-Enable-Rockchip-3588001-erratum-worka.patch b/target/linux/rockchip/patches-6.1/418-irqchip-gic-v3-Enable-Rockchip-3588001-erratum-worka.patch
new file mode 100644
index 00000000000..ab6d9405584
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/418-irqchip-gic-v3-Enable-Rockchip-3588001-erratum-worka.patch
@@ -0,0 +1,33 @@
+From 567f67acac94e7bbc4cb4b71ff9773555d02609a Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 3 Jul 2023 18:41:29 +0200
+Subject: [PATCH] irqchip/gic-v3: Enable Rockchip 3588001 erratum workaround
+ for RK3588S
+
+Commit a8707f553884 ("irqchip/gic-v3: Add Rockchip 3588001 erratum
+workaround") mentioned RK3588S (the slimmed down variant of RK3588)
+being affected, but did not check for its compatible value. Thus the
+quirk is not applied on RK3588S. Since the GIC ITS node got added to the
+upstream DT, boards using RK3588S are no longer booting without this
+quirk being applied.
+
+Fixes: 06cdac8e8407 ("arm64: dts: rockchip: add GIC ITS support to rk3588")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Signed-off-by: Marc Zyngier <maz@kernel.org>
+Link: https://lore.kernel.org/r/20230703164129.193991-1-sebastian.reichel@collabora.com
+---
+ drivers/irqchip/irq-gic-v3-its.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -4742,7 +4742,8 @@ static bool __maybe_unused its_enable_rk
+ {
+ 	struct its_node *its = data;
+ 
+-	if (!of_machine_is_compatible("rockchip,rk3588"))
++	if (!of_machine_is_compatible("rockchip,rk3588") &&
++	    !of_machine_is_compatible("rockchip,rk3588s"))
+ 		return false;
+ 
+ 	its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE;
diff --git a/target/linux/rockchip/patches-6.1/502-arm64-defconfig-Enable-Rockchip-OTP-memory-driver.patch b/target/linux/rockchip/patches-6.1/502-arm64-defconfig-Enable-Rockchip-OTP-memory-driver.patch
new file mode 100644
index 00000000000..2a128aff3e6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/502-arm64-defconfig-Enable-Rockchip-OTP-memory-driver.patch
@@ -0,0 +1,27 @@
+From c31f91cb13a2e0f9f0b8048b5d9623e1a51ef4d3 Mon Sep 17 00:00:00 2001
+From: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+Date: Sat, 3 Jun 2023 00:00:50 +0300
+Subject: [PATCH 02/16] arm64: defconfig: Enable Rockchip OTP memory driver
+
+The Rockchip one-time programmable memory driver provides access to
+various SoC specific information, e.g. leakage currents of the
+CPU/GPU/NPU components found on a RK3588 SoC.
+
+Enable the driver as built-in to allow client device drivers (e.g.
+cpufreq) to access the required data for proper settings adjustment.
+
+Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -1274,6 +1274,7 @@ CONFIG_NVMEM_IMX_OCOTP_SCU=y
+ CONFIG_NVMEM_MTK_EFUSE=y
+ CONFIG_NVMEM_QCOM_QFPROM=y
+ CONFIG_NVMEM_ROCKCHIP_EFUSE=y
++CONFIG_NVMEM_ROCKCHIP_OTP=y
+ CONFIG_NVMEM_SUNXI_SID=y
+ CONFIG_NVMEM_UNIPHIER_EFUSE=y
+ CONFIG_NVMEM_MESON_EFUSE=m
diff --git a/target/linux/rockchip/patches-6.1/503-mfd-rk808-Make-MFD_RK8XX-tristate.patch b/target/linux/rockchip/patches-6.1/503-mfd-rk808-Make-MFD_RK8XX-tristate.patch
new file mode 100644
index 00000000000..8354b91cb6f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/503-mfd-rk808-Make-MFD_RK8XX-tristate.patch
@@ -0,0 +1,26 @@
+From 677a15a324a741649f7f72d57e899ace02901966 Mon Sep 17 00:00:00 2001
+From: Geert Uytterhoeven <geert+renesas@glider.be>
+Date: Tue, 4 Jul 2023 15:07:48 +0200
+Subject: [PATCH 03/16] mfd: rk808: Make MFD_RK8XX tristate
+
+There is no reason for MFD_RK8XX to be bool, all drivers that depend on
+it, or that select it, are tristate.
+
+Fixes: c20e8c5b1203af37 ("mfd: rk808: Split into core and i2c")
+Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/mfd/Kconfig | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/drivers/mfd/Kconfig
++++ b/drivers/mfd/Kconfig
+@@ -1203,7 +1203,7 @@ config MFD_RC5T583
+ 	  different functionality of the device.
+ 
+ config MFD_RK8XX
+-	bool
++	tristate
+ 	select MFD_CORE
+ 
+ config MFD_RK8XX_I2C
diff --git a/target/linux/rockchip/patches-6.1/504-dt-bindings-vendor-prefixes-Add-prefix-for-belling.patch b/target/linux/rockchip/patches-6.1/504-dt-bindings-vendor-prefixes-Add-prefix-for-belling.patch
new file mode 100644
index 00000000000..1bc12bd13e7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/504-dt-bindings-vendor-prefixes-Add-prefix-for-belling.patch
@@ -0,0 +1,26 @@
+From 80e2f784eaa8175644640ae20c3238534a0122fb Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 10 Jul 2023 18:52:16 +0200
+Subject: [PATCH 04/16] dt-bindings: vendor-prefixes: Add prefix for belling
+
+Add a vendor prefix entry for belling (https://www.belling.com.cn)
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230710165228.105983-2-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/vendor-prefixes.yaml
++++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml
+@@ -184,6 +184,8 @@ patternProperties:
+     description: Compass Electronics Group, LLC
+   "^beagle,.*":
+     description: BeagleBoard.org Foundation
++  "^belling,.*":
++    description: Shanghai Belling Co., Ltd.
+   "^bhf,.*":
+     description: Beckhoff Automation GmbH & Co. KG
+   "^bitmain,.*":
diff --git a/target/linux/rockchip/patches-6.1/505-dt-bindings-eeprom-at24-add-Belling-BL24C16A.patch b/target/linux/rockchip/patches-6.1/505-dt-bindings-eeprom-at24-add-Belling-BL24C16A.patch
new file mode 100644
index 00000000000..c49895a4513
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/505-dt-bindings-eeprom-at24-add-Belling-BL24C16A.patch
@@ -0,0 +1,27 @@
+From f3c21b7bd54ae0c33f289879267d93b90b6fb5a8 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 10 Jul 2023 18:52:17 +0200
+Subject: [PATCH 05/16] dt-bindings: eeprom: at24: add Belling BL24C16A
+
+Add binding for Belling BL24C16A, which is compatible with Atmel 24C16.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+Acked-by: Conor Dooley <conor.dooley@microchip.com>
+Link: https://lore.kernel.org/r/20230710165228.105983-3-sebastian.reichel@collabora.com
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ Documentation/devicetree/bindings/eeprom/at24.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/eeprom/at24.yaml
++++ b/Documentation/devicetree/bindings/eeprom/at24.yaml
+@@ -99,6 +99,9 @@ properties:
+       # These are special cases that don't conform to the above pattern.
+       # Each requires a standard at24 model as fallback.
+       - items:
++          - const: belling,bl24c16a
++          - const: atmel,24c16
++      - items:
+           - enum:
+               - rohm,br24g01
+               - rohm,br24t01
diff --git a/target/linux/rockchip/patches-6.1/506-dt-bindings-phy-rockchip-add-RK3588-PCIe-v3-phy.patch b/target/linux/rockchip/patches-6.1/506-dt-bindings-phy-rockchip-add-RK3588-PCIe-v3-phy.patch
new file mode 100644
index 00000000000..a4294c7b9c4
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/506-dt-bindings-phy-rockchip-add-RK3588-PCIe-v3-phy.patch
@@ -0,0 +1,72 @@
+From bd52e123d6a479ec3a82d10b689f9bfc15b3b471 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Mon, 10 Jul 2023 19:51:11 +0200
+Subject: [PATCH 06/16] dt-bindings: phy: rockchip: add RK3588 PCIe v3 phy
+
+When the RK3568 PCIe v3 PHY supported has been upstreamed, RK3588
+support was included, but the DT binding does not reflect this.
+This adds the missing bits.
+
+Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ .../bindings/phy/rockchip,pcie3-phy.yaml      | 33 ++++++++++++++++---
+ 1 file changed, 28 insertions(+), 5 deletions(-)
+
+--- a/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
++++ b/Documentation/devicetree/bindings/phy/rockchip,pcie3-phy.yaml
+@@ -13,19 +13,18 @@ properties:
+   compatible:
+     enum:
+       - rockchip,rk3568-pcie3-phy
++      - rockchip,rk3588-pcie3-phy
+ 
+   reg:
+     maxItems: 1
+ 
+   clocks:
+-    minItems: 3
++    minItems: 1
+     maxItems: 3
+ 
+   clock-names:
+-    items:
+-      - const: refclk_m
+-      - const: refclk_n
+-      - const: pclk
++    minItems: 1
++    maxItems: 3
+ 
+   data-lanes:
+     description: which lanes (by position) should be mapped to which
+@@ -61,6 +60,30 @@ required:
+   - rockchip,phy-grf
+   - "#phy-cells"
+ 
++allOf:
++  - if:
++      properties:
++        compatible:
++          enum:
++            - rockchip,rk3588-pcie3-phy
++    then:
++      properties:
++        clocks:
++          maxItems: 1
++        clock-names:
++          items:
++            - const: pclk
++    else:
++      properties:
++        clocks:
++          minItems: 3
++
++        clock-names:
++          items:
++            - const: refclk_m
++            - const: refclk_n
++            - const: pclk
++
+ additionalProperties: false
+ 
+ examples:
diff --git a/target/linux/rockchip/patches-6.1/507-dt-bindings-PCI-dwc-improve-msi-handling.patch b/target/linux/rockchip/patches-6.1/507-dt-bindings-PCI-dwc-improve-msi-handling.patch
new file mode 100644
index 00000000000..deb200cfb16
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/507-dt-bindings-PCI-dwc-improve-msi-handling.patch
@@ -0,0 +1,43 @@
+From 872b174a8eb3e9471522622ffe4114985faeccf0 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Sat, 15 Jul 2023 00:37:44 +0200
+Subject: [PATCH 07/16] dt-bindings: PCI: dwc: improve msi handling
+
+Allow missing "msi" interrupt, iff the node has a "msi-map" property.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ .../devicetree/bindings/pci/snps,dw-pcie.yaml     | 15 +++++++++------
+ 1 file changed, 9 insertions(+), 6 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml
+@@ -25,6 +25,15 @@ select:
+ allOf:
+   - $ref: /schemas/pci/pci-bus.yaml#
+   - $ref: /schemas/pci/snps,dw-pcie-common.yaml#
++  - if:
++      not:
++        required:
++          - msi-map
++    then:
++      properties:
++        interrupt-names:
++          contains:
++            const: msi
+ 
+ properties:
+   reg:
+@@ -202,12 +211,6 @@ properties:
+         - description: Combined Error interrupt signal.
+           const: err
+ 
+-    allOf:
+-      - contains:
+-          enum:
+-            - msi
+-            - msg
+-
+ additionalProperties: true
+ 
+ required:
diff --git a/target/linux/rockchip/patches-6.1/508-arm64-defconfig-enable-Synopsys-AHCI-SATA-support.patch b/target/linux/rockchip/patches-6.1/508-arm64-defconfig-enable-Synopsys-AHCI-SATA-support.patch
new file mode 100644
index 00000000000..1e204b204bd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/508-arm64-defconfig-enable-Synopsys-AHCI-SATA-support.patch
@@ -0,0 +1,23 @@
+From 4e04a701a45e2155b979fd982a3447e9b84354d4 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 25 Jul 2023 15:47:18 +0200
+Subject: [PATCH 08/16] arm64: defconfig: enable Synopsys AHCI SATA support
+
+Enable support for the DesignWare AHCI Host Controller. It is used
+by recent Rockchip SoCs.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ arch/arm64/configs/defconfig | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/configs/defconfig
++++ b/arch/arm64/configs/defconfig
+@@ -302,6 +302,7 @@ CONFIG_SATA_AHCI=y
+ CONFIG_SATA_AHCI_PLATFORM=y
+ CONFIG_AHCI_BRCM=m
+ CONFIG_AHCI_CEVA=y
++CONFIG_AHCI_DWC=m
+ CONFIG_AHCI_MVEBU=y
+ CONFIG_AHCI_XGENE=y
+ CONFIG_AHCI_QORIQ=y
diff --git a/target/linux/rockchip/patches-6.1/509-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch b/target/linux/rockchip/patches-6.1/509-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch
new file mode 100644
index 00000000000..bfbd84a1dcd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/509-dt-bindings-usb-add-rk3588-compatible-to-rockchip-dw.patch
@@ -0,0 +1,61 @@
+From ce7d7fe0542a0c4322bb36bcb4eb09c829840237 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Thu, 20 Jul 2023 18:05:56 +0200
+Subject: [PATCH 09/16] dt-bindings: usb: add rk3588 compatible to
+ rockchip,dwc3
+
+RK3588 has three DWC3 controllers. Two of them are fully functional in
+host, device and OTG mode including USB2 support. They are connected to
+dedicated PHYs, that also support USB-C's DisplayPort alternate mode.
+
+The third controller is connected to one of the combphy's shared
+with PCIe and SATA. It can only be used in host mode and does not
+support USB2. Compared to the other controllers this one needs
+some extra clocks.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ .../devicetree/bindings/usb/rockchip,dwc3.yaml        | 11 +++++++++--
+ 1 file changed, 9 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
++++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+@@ -30,6 +30,7 @@ select:
+         enum:
+           - rockchip,rk3328-dwc3
+           - rockchip,rk3568-dwc3
++          - rockchip,rk3588-dwc3
+   required:
+     - compatible
+ 
+@@ -39,6 +40,7 @@ properties:
+       - enum:
+           - rockchip,rk3328-dwc3
+           - rockchip,rk3568-dwc3
++          - rockchip,rk3588-dwc3
+       - const: snps,dwc3
+ 
+   reg:
+@@ -58,7 +60,9 @@ properties:
+           Master/Core clock, must to be >= 62.5 MHz for SS
+           operation and >= 30MHz for HS operation
+       - description:
+-          Controller grf clock
++          Controller grf clock OR UTMI clock
++      - description:
++          PIPE clock
+ 
+   clock-names:
+     minItems: 3
+@@ -66,7 +70,10 @@ properties:
+       - const: ref_clk
+       - const: suspend_clk
+       - const: bus_clk
+-      - const: grf_clk
++      - enum:
++          - grf_clk
++          - utmi
++      - const: pipe
+ 
+   power-domains:
+     maxItems: 1
diff --git a/target/linux/rockchip/patches-6.1/510-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch b/target/linux/rockchip/patches-6.1/510-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch
new file mode 100644
index 00000000000..95329237bbb
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/510-dt-bindings-soc-rockchip-add-rk3588-USB3-syscon.patch
@@ -0,0 +1,57 @@
+From 1009b78caa4c2ca434c98f22cd38873f0f6cd83d Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 30 May 2023 18:49:48 +0200
+Subject: [PATCH 10/16] dt-bindings: soc: rockchip: add rk3588 USB3 syscon
+
+RK3588 USB3 support requires the GRF for USB, USBDP PHY and VO.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ .../devicetree/bindings/soc/rockchip/grf.yaml | 22 +++++++++++++++++++
+ 1 file changed, 22 insertions(+)
+
+--- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
++++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml
+@@ -28,6 +28,9 @@ properties:
+               - rockchip,rk3588-sys-grf
+               - rockchip,rk3588-pcie3-phy-grf
+               - rockchip,rk3588-pcie3-pipe-grf
++              - rockchip,rk3588-usb-grf
++              - rockchip,rk3588-usbdpphy-grf
++              - rockchip,rk3588-vo-grf
+               - rockchip,rv1108-usbgrf
+           - const: syscon
+       - items:
+@@ -64,6 +67,9 @@ properties:
+   reg:
+     maxItems: 1
+ 
++  clocks:
++    maxItems: 1
++
+   "#address-cells":
+     const: 1
+ 
+@@ -245,6 +251,22 @@ allOf:
+ 
+           unevaluatedProperties: false
+ 
++  - if:
++      properties:
++        compatible:
++          contains:
++            enum:
++              - rockchip,rk3588-vo-grf
++
++    then:
++      required:
++        - clocks
++
++    else:
++      properties:
++        clocks: false
++
++
+ examples:
+   - |
+     #include <dt-bindings/clock/rk3399-cru.h>
diff --git a/target/linux/rockchip/patches-6.1/511-dt-bindings-media-rockchip-Add-resets-property-into-.patch b/target/linux/rockchip/patches-6.1/511-dt-bindings-media-rockchip-Add-resets-property-into-.patch
new file mode 100644
index 00000000000..786b25e0430
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/511-dt-bindings-media-rockchip-Add-resets-property-into-.patch
@@ -0,0 +1,27 @@
+From 86674aee98f7d04e56cccbb8f1f0f8ca42a2207e Mon Sep 17 00:00:00 2001
+From: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+Date: Mon, 12 Jun 2023 14:57:58 +0200
+Subject: [PATCH 11/16] dt-bindings: media: rockchip: Add resets property into
+ decoder node
+
+RK3588 AV1 decoder hardware block have resets lines and driver code
+already suppport it.
+Update yaml file to be aligned with this feature.
+
+Signed-off-by: Benjamin Gaignard <benjamin.gaignard@collabora.com>
+---
+ Documentation/devicetree/bindings/media/rockchip-vpu.yaml | 3 +++
+ 1 file changed, 3 insertions(+)
+
+--- a/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
++++ b/Documentation/devicetree/bindings/media/rockchip-vpu.yaml
+@@ -67,6 +67,9 @@ properties:
+   iommus:
+     maxItems: 1
+ 
++  resets:
++    maxItems: 4
++
+ required:
+   - compatible
+   - reg
diff --git a/target/linux/rockchip/patches-6.1/512-dt-bindings-es8328-convert-to-DT-schema-format.patch b/target/linux/rockchip/patches-6.1/512-dt-bindings-es8328-convert-to-DT-schema-format.patch
new file mode 100644
index 00000000000..4447da94ab9
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/512-dt-bindings-es8328-convert-to-DT-schema-format.patch
@@ -0,0 +1,136 @@
+From 1fe90f727d4f8e3e5860d47c7a8cd3d356ca5620 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 25 Jul 2023 18:49:43 +0200
+Subject: [PATCH 12/16] dt-bindings: es8328: convert to DT schema format
+
+Convert the binding to DT schema format.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ .../devicetree/bindings/sound/es8328.txt      | 38 ---------
+ .../bindings/sound/everest,es8328.yaml        | 77 +++++++++++++++++++
+ 2 files changed, 77 insertions(+), 38 deletions(-)
+ delete mode 100644 Documentation/devicetree/bindings/sound/es8328.txt
+ create mode 100644 Documentation/devicetree/bindings/sound/everest,es8328.yaml
+
+--- a/Documentation/devicetree/bindings/sound/es8328.txt
++++ /dev/null
+@@ -1,38 +0,0 @@
+-Everest ES8328 audio CODEC
+-
+-This device supports both I2C and SPI.
+-
+-Required properties:
+-
+-  - compatible  : Should be "everest,es8328" or "everest,es8388"
+-  - DVDD-supply : Regulator providing digital core supply voltage 1.8 - 3.6V
+-  - AVDD-supply : Regulator providing analog supply voltage 3.3V
+-  - PVDD-supply : Regulator providing digital IO supply voltage 1.8 - 3.6V
+-  - IPVDD-supply : Regulator providing analog output voltage 3.3V
+-  - clocks : A 22.5792 or 11.2896 MHz clock
+-  - reg : the I2C address of the device for I2C, the chip select number for SPI
+-
+-Pins on the device (for linking into audio routes):
+-
+-  * LOUT1
+-  * LOUT2
+-  * ROUT1
+-  * ROUT2
+-  * LINPUT1
+-  * RINPUT1
+-  * LINPUT2
+-  * RINPUT2
+-  * Mic Bias
+-
+-
+-Example:
+-
+-codec: es8328@11 {
+-	compatible = "everest,es8328";
+-	DVDD-supply = <&reg_3p3v>;
+-	AVDD-supply = <&reg_3p3v>;
+-	PVDD-supply = <&reg_3p3v>;
+-	HPVDD-supply = <&reg_3p3v>;
+-	clocks = <&clks 169>;
+-	reg = <0x11>;
+-};
+--- /dev/null
++++ b/Documentation/devicetree/bindings/sound/everest,es8328.yaml
+@@ -0,0 +1,77 @@
++# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
++%YAML 1.2
++---
++$id: http://devicetree.org/schemas/sound/everest,es8328.yaml#
++$schema: http://devicetree.org/meta-schemas/core.yaml#
++
++title: Everest ES8328 audio CODEC
++
++description:
++  Everest Audio Codec, which can be connected via I2C or SPI.
++  Pins on the device (for linking into audio routes) are
++  * LOUT1
++  * LOUT2
++  * ROUT1
++  * ROUT2
++  * LINPUT1
++  * RINPUT1
++  * LINPUT2
++  * RINPUT2
++  * Mic Bias
++
++maintainers:
++  - David Yang <yangxiaohua@everest-semi.com>
++
++properties:
++  compatible:
++    enum:
++      - everest,es8328
++      - everest,es8388
++
++  reg:
++    maxItems: 1
++
++  "#sound-dai-cells":
++    const: 0
++
++  clocks:
++    items:
++      - description: A 22.5792 or 11.2896 MHz clock
++
++  DVDD-supply:
++    description: Regulator providing digital core supply voltage 1.8 - 3.6V
++
++  AVDD-supply:
++    description: Regulator providing analog supply voltage 3.3V
++
++  PVDD-supply:
++    description: Regulator providing digital IO supply voltage 1.8 - 3.6V
++
++  IPVDD-supply:
++    description: Regulator providing analog output voltage 3.3V
++
++required:
++  - compatible
++  - clocks
++  - DVDD-supply
++  - AVDD-supply
++  - PVDD-supply
++  - IPVDD-supply
++
++additionalProperties: false
++
++examples:
++  - |
++    i2c {
++      #address-cells = <1>;
++      #size-cells = <0>;
++      es8328: codec@11 {
++        compatible = "everest,es8328";
++        reg = <0x11>;
++        AVDD-supply = <&reg_3p3v>;
++        DVDD-supply = <&reg_3p3v>;
++        HPVDD-supply = <&reg_3p3v>;
++        PVDD-supply = <&reg_3p3v>;
++        clocks = <&clks 169>;
++      };
++    };
diff --git a/target/linux/rockchip/patches-6.1/513-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch b/target/linux/rockchip/patches-6.1/513-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch
new file mode 100644
index 00000000000..06033503bfd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/513-clk-rockchip-rk3588-fix-pclk_vo0grf-and-pclk_vo1grf.patch
@@ -0,0 +1,72 @@
+From fb03ca05f94ed0698cafa7135576e9a58ea75048 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Tue, 13 Jun 2023 16:45:05 +0200
+Subject: [PATCH 13/16] clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grf
+
+Currently pclk_vo1grf is not exposed, but it should be referenced
+from the vo1_grf syscon, which needs it enabled. That syscon will
+be required for HDMI-RX functionality among other things.
+
+Apart from that pclk_vo0grf and pclk_vo1grf are both linked gates
+and need the VO's hclk enabled in addition to their parent clock.
+
+No Fixes tag has been added, since the logic requiring these clocks
+is not yet upstream anyways.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/clk/rockchip/clk-rk3588.c               | 11 +++++------
+ include/dt-bindings/clock/rockchip,rk3588-cru.h |  3 ++-
+ 2 files changed, 7 insertions(+), 7 deletions(-)
+
+--- a/drivers/clk/rockchip/clk-rk3588.c
++++ b/drivers/clk/rockchip/clk-rk3588.c
+@@ -1851,8 +1851,6 @@ static struct rockchip_clk_branch rk3588
+ 			RK3588_CLKGATE_CON(56), 0, GFLAGS),
+ 	GATE(PCLK_TRNG0, "pclk_trng0", "pclk_vo0_root", 0,
+ 			RK3588_CLKGATE_CON(56), 1, GFLAGS),
+-	GATE(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", CLK_IGNORE_UNUSED,
+-			RK3588_CLKGATE_CON(55), 10, GFLAGS),
+ 	COMPOSITE(CLK_I2S4_8CH_TX_SRC, "clk_i2s4_8ch_tx_src", gpll_aupll_p, 0,
+ 			RK3588_CLKSEL_CON(118), 5, 1, MFLAGS, 0, 5, DFLAGS,
+ 			RK3588_CLKGATE_CON(56), 11, GFLAGS),
+@@ -1998,8 +1996,6 @@ static struct rockchip_clk_branch rk3588
+ 			RK3588_CLKGATE_CON(60), 9, GFLAGS),
+ 	GATE(PCLK_TRNG1, "pclk_trng1", "pclk_vo1_root", 0,
+ 			RK3588_CLKGATE_CON(60), 10, GFLAGS),
+-	GATE(0, "pclk_vo1grf", "pclk_vo1_root", CLK_IGNORE_UNUSED,
+-			RK3588_CLKGATE_CON(59), 12, GFLAGS),
+ 	GATE(PCLK_S_EDP0, "pclk_s_edp0", "pclk_vo1_s_root", 0,
+ 			RK3588_CLKGATE_CON(59), 14, GFLAGS),
+ 	GATE(PCLK_S_EDP1, "pclk_s_edp1", "pclk_vo1_s_root", 0,
+@@ -2447,12 +2443,15 @@ static struct rockchip_clk_branch rk3588
+ 	GATE_LINK(HCLK_RKVDEC1_PRE, "hclk_rkvdec1_pre", "hclk_rkvdec1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 4, GFLAGS),
+ 	GATE_LINK(ACLK_RKVDEC1_PRE, "aclk_rkvdec1_pre", "aclk_rkvdec1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(41), 5, GFLAGS),
+ 	GATE_LINK(ACLK_HDCP0_PRE, "aclk_hdcp0_pre", "aclk_vo0_root", "aclk_vop_low_root", 0, RK3588_CLKGATE_CON(55), 9, GFLAGS),
+-	GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", 0, RK3588_CLKGATE_CON(55), 5, GFLAGS),
++	GATE_LINK(HCLK_VO0, "hclk_vo0", "hclk_vo0_root", "hclk_vop_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(55), 5, GFLAGS),
+ 	GATE_LINK(ACLK_HDCP1_PRE, "aclk_hdcp1_pre", "aclk_hdcp1_root", "aclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 6, GFLAGS),
+-	GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", 0, RK3588_CLKGATE_CON(59), 9, GFLAGS),
++	GATE_LINK(HCLK_VO1, "hclk_vo1", "hclk_vo1_root", "hclk_vo1usb_top_root", RK3588_LINKED_CLK, RK3588_CLKGATE_CON(59), 9, GFLAGS),
+ 	GATE_LINK(ACLK_AV1_PRE, "aclk_av1_pre", "aclk_av1_root", "aclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 1, GFLAGS),
+ 	GATE_LINK(PCLK_AV1_PRE, "pclk_av1_pre", "pclk_av1_root", "hclk_vdpu_root", 0, RK3588_CLKGATE_CON(68), 4, GFLAGS),
+ 	GATE_LINK(HCLK_SDIO_PRE, "hclk_sdio_pre", "hclk_sdio_root", "hclk_nvm", 0, RK3588_CLKGATE_CON(75), 1, GFLAGS),
++	GATE_LINK(PCLK_VO0GRF, "pclk_vo0grf", "pclk_vo0_root", "hclk_vo0", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(55), 10, GFLAGS),
++	GATE_LINK(PCLK_VO1GRF, "pclk_vo1grf", "pclk_vo1_root", "hclk_vo1", CLK_IGNORE_UNUSED, RK3588_CLKGATE_CON(59), 12, GFLAGS),
++
+ };
+ 
+ static void __init rk3588_clk_init(struct device_node *np)
+--- a/include/dt-bindings/clock/rockchip,rk3588-cru.h
++++ b/include/dt-bindings/clock/rockchip,rk3588-cru.h
+@@ -733,8 +733,9 @@
+ #define ACLK_AV1_PRE			718
+ #define PCLK_AV1_PRE			719
+ #define HCLK_SDIO_PRE			720
++#define PCLK_VO1GRF			721
+ 
+-#define CLK_NR_CLKS			(HCLK_SDIO_PRE + 1)
++#define CLK_NR_CLKS			(PCLK_VO1GRF + 1)
+ 
+ /* scmi-clocks indices */
+ 
diff --git a/target/linux/rockchip/patches-6.1/515-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch b/target/linux/rockchip/patches-6.1/515-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch
new file mode 100644
index 00000000000..4227ffae7c2
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/515-dt-bindings-PCI-dwc-rockchip-Fix-interrupt-names-iss.patch
@@ -0,0 +1,91 @@
+From 07329be104dc1ea8a2504222cacda20a997454f2 Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Sat, 15 Jul 2023 00:39:28 +0200
+Subject: [PATCH 15/16] dt-bindings: PCI: dwc: rockchip: Fix interrupt-names
+ issue
+
+The RK356x (and RK3588) have 5 ganged interrupts. For example the
+"legacy" interrupt combines "inta/intb/intc/intd" with a register
+providing the details, which specific interrupt triggered. The
+interrupts from the second level are part of the Synopsys DW PCIe
+System Information Interface (SII). Some of them are listed in the
+Interrupt Signals section, the others are mostly common SII output
+signals. The grouping and the ganged interrupt controllers are
+specific to the Rockchip implementation.
+
+Currently the binding is not specifying these interrupts resulting
+in a bunch of errors for all rk356x/rk3588 boards using PCIe.
+
+Fix this by specifying the interrupts and add them to the example
+to prevent regressions.
+
+This changes the reference from snps,dw-pcie.yaml to
+snps,dw-pcie-common.yaml, since the interrupts are vendor
+specific and should not be listed in the generic file. The
+only other bit from the generic binding are the reg-names,
+which are overwritten by this binding.
+
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ .../bindings/pci/rockchip-dw-pcie.yaml        | 32 +++++++++++++++++--
+ 1 file changed, 30 insertions(+), 2 deletions(-)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -61,7 +61,29 @@ properties:
+       - const: pipe
+ 
+   interrupts:
+-    maxItems: 5
++    items:
++      - description:
++          Combined system interrupt, which is used to signal the following
++          interrupts - phy_link_up, dll_link_up, link_req_rst_not, hp_pme,
++          hp, hp_msi, link_auto_bw, link_auto_bw_msi, bw_mgt, bw_mgt_msi,
++          edma_wr, edma_rd, dpa_sub_upd, rbar_update, link_eq_req, ep_elbi_app
++      - description:
++          Combined PM interrupt, which is used to signal the following
++          interrupts - linkst_in_l1sub, linkst_in_l1, linkst_in_l2,
++          linkst_in_l0s, linkst_out_l1sub, linkst_out_l1, linkst_out_l2,
++          linkst_out_l0s, pm_dstate_update
++      - description:
++          Combined message interrupt, which is used to signal the following
++          interrupts - ven_msg, unlock_msg, ltr_msg, cfg_pme, cfg_pme_msi,
++          pm_pme, pm_to_ack, pm_turnoff, obff_idle, obff_obff, obff_cpu_active
++      - description:
++          Combined legacy interrupt, which is used to signal the following
++          interrupts - inta, intb, intc, intd
++      - description:
++          Combined error interrupt, which is used to signal the following
++          interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
++          tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
++          nf_err_rx, f_err_rx, radm_qoverflow
+ 
+   interrupt-names:
+     items:
+@@ -74,6 +96,7 @@ properties:
+   legacy-interrupt-controller:
+     description: Interrupt controller node for handling legacy PCI interrupts.
+     type: object
++    additionalProperties: false
+     properties:
+       "#address-cells":
+         const: 0
+@@ -81,11 +104,16 @@ properties:
+       "#interrupt-cells":
+         const: 1
+ 
+-      "interrupt-controller": true
++      interrupt-controller: true
+ 
+       interrupts:
+         items:
+           - description: combined legacy interrupt
++    required:
++      - "#address-cells"
++      - "#interrupt-cells"
++      - interrupt-controller
++      - interrupts
+ 
+   msi-map: true
+ 
diff --git a/target/linux/rockchip/patches-6.1/516-rockchip-sync-rk3588.patch b/target/linux/rockchip/patches-6.1/516-rockchip-sync-rk3588.patch
new file mode 100644
index 00000000000..90511ad413e
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/516-rockchip-sync-rk3588.patch
@@ -0,0 +1,588 @@
+From c54299eaa633b0aeaeb05a6e53cabd4e73ec09cd Mon Sep 17 00:00:00 2001
+From: Marty Jones <mj8263788@gmail.com>
+Date: Mon, 21 Aug 2023 15:46:52 -0400
+Subject: [PATCH 16/16] rockchip: sync rk3588
+
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 153 +++++++++++++++++--
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 171 ++++++++++++++--------
+ 2 files changed, 254 insertions(+), 70 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -35,6 +35,31 @@
+ 		};
+ 	};
+ 
++	usb_host1_xhci: usb@fc400000 {
++		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
++		reg = <0x0 0xfc400000 0x0 0x400000>;
++		interrupts = <GIC_SPI 221 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru REF_CLK_USB3OTG1>, <&cru SUSPEND_CLK_USB3OTG1>,
++			 <&cru ACLK_USB3OTG1>;
++		clock-names = "ref_clk", "suspend_clk", "bus_clk";
++		dr_mode = "host";
++		phys = <&u2phy1_otg>, <&usbdp_phy1_u3>;
++		phy-names = "usb2-phy", "usb3-phy";
++		phy_type = "utmi_wide";
++		power-domains = <&power RK3588_PD_USB>;
++		resets = <&cru SRST_A_USB3OTG1>;
++		snps,dis_enblslpm_quirk;
++		snps,dis-u2-freeclk-exists-quirk;
++		snps,dis-del-phy-power-chg-quirk;
++		snps,dis-tx-ipgap-linecheck-quirk;
++		status = "disabled";
++	};
++
++	pcie30_phy_grf: syscon@fd5b8000 {
++		compatible = "rockchip,rk3588-pcie3-phy-grf", "syscon";
++		reg = <0x0 0xfd5b8000 0x0 0x10000>;
++	};
++
+ 	pipe_phy1_grf: syscon@fd5c0000 {
+ 		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+ 		reg = <0x0 0xfd5c0000 0x0 0x100>;
+@@ -62,7 +87,6 @@
+ 			clock-names = "phyclk";
+ 			clock-output-names = "usb480m_phy1";
+ 			#clock-cells = <0>;
+-			rockchip,usbctrl-grf = <&usb_grf>;
+ 			status = "disabled";
+ 
+ 			u2phy1_otg: otg-port {
+@@ -140,10 +164,110 @@
+ 		status = "disabled";
+ 	};
+ 
+-	pcie2x1l0: pcie@fe170000 {
++	pcie3x4: pcie@fe150000 {
+ 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ 		#address-cells = <3>;
+ 		#size-cells = <2>;
++		bus-range = <0x00 0x0f>;
++		clocks = <&cru ACLK_PCIE_4L_MSTR>, <&cru ACLK_PCIE_4L_SLV>,
++			 <&cru ACLK_PCIE_4L_DBI>, <&cru PCLK_PCIE_4L>,
++			 <&cru CLK_PCIE_AUX0>, <&cru CLK_PCIE4L_PIPE>;
++		clock-names = "aclk_mst", "aclk_slv",
++			      "aclk_dbi", "pclk",
++			      "aux", "pipe";
++		device_type = "pci";
++		interrupts = <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
++				<0 0 0 2 &pcie3x4_intc 1>,
++				<0 0 0 3 &pcie3x4_intc 2>,
++				<0 0 0 4 &pcie3x4_intc 3>;
++		linux,pci-domain = <0>;
++		max-link-speed = <3>;
++		msi-map = <0x0000 &its1 0x0000 0x1000>;
++		num-lanes = <4>;
++		phys = <&pcie30phy>;
++		phy-names = "pcie-phy";
++		power-domains = <&power RK3588_PD_PCIE>;
++		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
++			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
++			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
++		reg = <0xa 0x40000000 0x0 0x00400000>,
++		      <0x0 0xfe150000 0x0 0x00010000>,
++		      <0x0 0xf0000000 0x0 0x00100000>;
++		reg-names = "dbi", "apb", "config";
++		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
++		reset-names = "pwr", "pipe";
++		status = "disabled";
++
++		pcie3x4_intc: legacy-interrupt-controller {
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 260 IRQ_TYPE_EDGE_RISING 0>;
++		};
++	};
++
++	pcie3x2: pcie@fe160000 {
++		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
++		#address-cells = <3>;
++		#size-cells = <2>;
++		bus-range = <0x10 0x1f>;
++		clocks = <&cru ACLK_PCIE_2L_MSTR>, <&cru ACLK_PCIE_2L_SLV>,
++			 <&cru ACLK_PCIE_2L_DBI>, <&cru PCLK_PCIE_2L>,
++			 <&cru CLK_PCIE_AUX1>, <&cru CLK_PCIE2L_PIPE>;
++		clock-names = "aclk_mst", "aclk_slv",
++			      "aclk_dbi", "pclk",
++			      "aux", "pipe";
++		device_type = "pci";
++		interrupts = <GIC_SPI 258 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 257 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++		#interrupt-cells = <1>;
++		interrupt-map-mask = <0 0 0 7>;
++		interrupt-map = <0 0 0 1 &pcie3x2_intc 0>,
++				<0 0 0 2 &pcie3x2_intc 1>,
++				<0 0 0 3 &pcie3x2_intc 2>,
++				<0 0 0 4 &pcie3x2_intc 3>;
++		linux,pci-domain = <1>;
++		max-link-speed = <3>;
++		msi-map = <0x1000 &its1 0x1000 0x1000>;
++		num-lanes = <2>;
++		phys = <&pcie30phy>;
++		phy-names = "pcie-phy";
++		power-domains = <&power RK3588_PD_PCIE>;
++		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
++			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
++			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
++		reg = <0xa 0x40400000 0x0 0x00400000>,
++		      <0x0 0xfe160000 0x0 0x00010000>,
++		      <0x0 0xf1000000 0x0 0x00100000>;
++		reg-names = "dbi", "apb", "config";
++		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
++		reset-names = "pwr", "pipe";
++		status = "disabled";
++
++		pcie3x2_intc: legacy-interrupt-controller {
++			interrupt-controller;
++			#address-cells = <0>;
++			#interrupt-cells = <1>;
++			interrupt-parent = <&gic>;
++			interrupts = <GIC_SPI 255 IRQ_TYPE_EDGE_RISING 0>;
++		};
++	};
++
++	pcie2x1l0: pcie@fe170000 {
++		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+ 		bus-range = <0x20 0x2f>;
+ 		clocks = <&cru ACLK_PCIE_1L0_MSTR>, <&cru ACLK_PCIE_1L0_SLV>,
+ 			 <&cru ACLK_PCIE_1L0_DBI>, <&cru PCLK_PCIE_1L0>,
+@@ -165,9 +289,6 @@
+ 				<0 0 0 3 &pcie2x1l0_intc 2>,
+ 				<0 0 0 4 &pcie2x1l0_intc 3>;
+ 		linux,pci-domain = <2>;
+-		num-ib-windows = <8>;
+-		num-ob-windows = <8>;
+-		num-viewport = <4>;
+ 		max-link-speed = <2>;
+ 		msi-map = <0x2000 &its0 0x2000 0x1000>;
+ 		num-lanes = <1>;
+@@ -176,13 +297,15 @@
+ 		power-domains = <&power RK3588_PD_PCIE>;
+ 		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
+-			 <0x03000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>;
++			 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+ 		reg = <0xa 0x40800000 0x0 0x00400000>,
+ 		      <0x0 0xfe170000 0x0 0x00010000>,
+ 		      <0x0 0xf2000000 0x0 0x00100000>;
+ 		reg-names = "dbi", "apb", "config";
+ 		resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
+ 		reset-names = "pwr", "pipe";
++		#address-cells = <3>;
++		#size-cells = <2>;
+ 		status = "disabled";
+ 
+ 		pcie2x1l0_intc: legacy-interrupt-controller {
+@@ -192,7 +315,6 @@
+ 			interrupt-parent = <&gic>;
+ 			interrupts = <GIC_SPI 240 IRQ_TYPE_EDGE_RISING 0>;
+ 		};
+-
+ 	};
+ 
+ 	gmac0: ethernet@fe1b0000 {
+@@ -247,11 +369,11 @@
+ 	sata1: sata@fe220000 {
+ 		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ 		reg = <0 0xfe220000 0 0x1000>;
++		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		clocks = <&cru ACLK_SATA1>, <&cru CLK_PMALIVE1>,
+ 			 <&cru CLK_RXOOB1>, <&cru CLK_PIPEPHY1_REF>,
+ 			 <&cru CLK_PIPEPHY1_PIPE_ASIC_G>;
+ 		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+-		interrupts = <GIC_SPI 274 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		ports-implemented = <0x1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -301,16 +423,29 @@
+ 	combphy1_ps: phy@fee10000 {
+ 		compatible = "rockchip,rk3588-naneng-combphy";
+ 		reg = <0x0 0xfee10000 0x0 0x100>;
+-		#phy-cells = <1>;
+ 		clocks = <&cru CLK_REF_PIPE_PHY1>, <&cru PCLK_PCIE_COMBO_PIPE_PHY1>,
+ 			 <&cru PCLK_PHP_ROOT>;
+ 		clock-names = "ref", "apb", "pipe";
+ 		assigned-clocks = <&cru CLK_REF_PIPE_PHY1>;
+ 		assigned-clock-rates = <100000000>;
++		#phy-cells = <1>;
+ 		resets = <&cru SRST_REF_PIPE_PHY1>, <&cru SRST_P_PCIE2_PHY1>;
+ 		reset-names = "phy", "apb";
+ 		rockchip,pipe-grf = <&php_grf>;
+ 		rockchip,pipe-phy-grf = <&pipe_phy1_grf>;
+ 		status = "disabled";
+ 	};
++
++	pcie30phy: phy@fee80000 {
++		compatible = "rockchip,rk3588-pcie3-phy";
++		reg = <0x0 0xfee80000 0x0 0x20000>;
++		#phy-cells = <0>;
++		clocks = <&cru PCLK_PCIE_COMBO_PIPE_PHY>;
++		clock-names = "pclk";
++		resets = <&cru SRST_PCIE30_PHY>;
++		reset-names = "phy";
++		rockchip,pipe-grf = <&php_grf>;
++		rockchip,phy-grf = <&pcie30_phy_grf>;
++		status = "disabled";
++	};
+ };
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -8,9 +8,9 @@
+ #include <dt-bindings/interrupt-controller/irq.h>
+ #include <dt-bindings/power/rk3588-power.h>
+ #include <dt-bindings/reset/rockchip,rk3588-cru.h>
+-#include <dt-bindings/thermal/thermal.h>
+ #include <dt-bindings/phy/phy.h>
+ #include <dt-bindings/ata/ahci.h>
++#include <dt-bindings/thermal/thermal.h>
+ 
+ / {
+ 	compatible = "rockchip,rk3588";
+@@ -149,7 +149,7 @@
+ 					<925000 925000 1000000>;
+ 			clock-latency-ns = <40000>;
+ 		};
+-		opp-2400000000 {
++		opp-2400000000  {
+ 			opp-hz = /bits/ 64 <2400000000>;
+ 			opp-microvolt = <1000000 1000000 1000000>,
+ 					<1000000 1000000 1000000>;
+@@ -884,6 +884,28 @@
+ 		};
+ 	};
+ 
++	usb_host0_xhci: usb@fc000000 {
++		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
++		reg = <0x0 0xfc000000 0x0 0x400000>;
++		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru REF_CLK_USB3OTG0>, <&cru SUSPEND_CLK_USB3OTG0>,
++			 <&cru ACLK_USB3OTG0>;
++		clock-names = "ref_clk", "suspend_clk", "bus_clk";
++		dr_mode = "otg";
++		phys = <&u2phy0_otg>, <&usbdp_phy0_u3>;
++		phy-names = "usb2-phy", "usb3-phy";
++		phy_type = "utmi_wide";
++		power-domains = <&power RK3588_PD_USB>;
++		resets = <&cru SRST_A_USB3OTG0>;
++		snps,dis_enblslpm_quirk;
++		snps,dis-u1-entry-quirk;
++		snps,dis-u2-entry-quirk;
++		snps,dis-u2-freeclk-exists-quirk;
++		snps,dis-del-phy-power-chg-quirk;
++		snps,dis-tx-ipgap-linecheck-quirk;
++		status = "disabled";
++	};
++
+ 	usb_host0_ehci: usb@fc800000 {
+ 		compatible = "rockchip,rk3588-ehci", "generic-ehci";
+ 		reg = <0x0 0xfc800000 0x0 0x40000>;
+@@ -928,6 +950,27 @@
+ 		status = "disabled";
+ 	};
+ 
++	usb_host2_xhci: usb@fcd00000 {
++		compatible = "rockchip,rk3588-dwc3", "snps,dwc3";
++		reg = <0x0 0xfcd00000 0x0 0x400000>;
++		interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
++			 <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>,
++			 <&cru CLK_PIPEPHY2_PIPE_U3_G>;
++		clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe";
++		dr_mode = "host";
++		phys = <&combphy2_psu PHY_TYPE_USB3>;
++		phy-names = "usb3-phy";
++		phy_type = "utmi_wide";
++		resets = <&cru SRST_A_USB3OTG2>;
++		snps,dis_enblslpm_quirk;
++		snps,dis-u2-freeclk-exists-quirk;
++		snps,dis-del-phy-power-chg-quirk;
++		snps,dis-tx-ipgap-linecheck-quirk;
++		snps,dis_rxdet_inp3_quirk;
++		status = "disabled";
++	};
++
+ 	usbhost3_0: usbhost3_0 {
+ 		compatible = "rockchip,rk3588-dwc3", "rockchip,rk3399-dwc3";
+ 		clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>,
+@@ -967,6 +1010,36 @@
+ 		reg = <0x0 0xfd58c000 0x0 0x1000>;
+ 	};
+ 
++	bigcore0_grf: syscon@fd590000 {
++		compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
++		reg = <0x0 0xfd590000 0x0 0x100>;
++	};
++
++	bigcore1_grf: syscon@fd592000 {
++		compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
++		reg = <0x0 0xfd592000 0x0 0x100>;
++	};
++
++	php_grf: syscon@fd5b0000 {
++		compatible = "rockchip,rk3588-php-grf", "syscon";
++		reg = <0x0 0xfd5b0000 0x0 0x1000>;
++	};
++
++	pipe_phy0_grf: syscon@fd5bc000 {
++		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
++		reg = <0x0 0xfd5bc000 0x0 0x100>;
++	};
++
++	pipe_phy2_grf: syscon@fd5c4000 {
++		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
++		reg = <0x0 0xfd5c4000 0x0 0x100>;
++	};
++
++	usbdpphy0_grf: syscon@fd5c8000 {
++		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
++		reg = <0x0 0xfd5c8000 0x0 0x4000>;
++	};
++
+ 	usb2phy0_grf: syscon@fd5d0000 {
+ 		compatible = "rockchip,rk3588-usb2phy-grf", "syscon",
+ 			     "simple-mfd";
+@@ -984,7 +1057,6 @@
+ 			clock-names = "phyclk";
+ 			clock-output-names = "usb480m_phy0";
+ 			#clock-cells = <0>;
+-			rockchip,usbctrl-grf = <&usb_grf>;
+ 			status = "disabled";
+ 
+ 			u2phy0_otg: otg-port {
+@@ -1055,36 +1127,6 @@
+ 		};
+ 	};
+ 
+-	bigcore0_grf: syscon@fd590000 {
+-		compatible = "rockchip,rk3588-bigcore0-grf", "syscon";
+-		reg = <0x0 0xfd590000 0x0 0x100>;
+-	};
+-
+-	bigcore1_grf: syscon@fd592000 {
+-		compatible = "rockchip,rk3588-bigcore1-grf", "syscon";
+-		reg = <0x0 0xfd592000 0x0 0x100>;
+-	};
+-
+-	php_grf: syscon@fd5b0000 {
+-		compatible = "rockchip,rk3588-php-grf", "syscon";
+-		reg = <0x0 0xfd5b0000 0x0 0x1000>;
+-	};
+-
+-	pipe_phy0_grf: syscon@fd5bc000 {
+-		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+-		reg = <0x0 0xfd5bc000 0x0 0x100>;
+-	};
+-
+-	pipe_phy2_grf: syscon@fd5c4000 {
+-		compatible = "rockchip,rk3588-pipe-phy-grf", "syscon";
+-		reg = <0x0 0xfd5c4000 0x0 0x100>;
+-	};
+-
+-	usbdpphy0_grf: syscon@fd5c8000 {
+-		compatible = "rockchip,rk3588-usbdpphy-grf", "syscon";
+-		reg = <0x0 0xfd5c8000 0x0 0x4000>;
+-	};
+-
+ 	ioc: syscon@fd5f0000 {
+ 		compatible = "rockchip,rk3588-ioc", "syscon";
+ 		reg = <0x0 0xfd5f0000 0x0 0x10000>;
+@@ -1801,8 +1843,6 @@
+ 
+ 	pcie2x1l1: pcie@fe180000 {
+ 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+ 		bus-range = <0x30 0x3f>;
+ 		clocks = <&cru ACLK_PCIE_1L1_MSTR>, <&cru ACLK_PCIE_1L1_SLV>,
+ 			 <&cru ACLK_PCIE_1L1_DBI>, <&cru PCLK_PCIE_1L1>,
+@@ -1824,9 +1864,6 @@
+ 				<0 0 0 3 &pcie2x1l1_intc 2>,
+ 				<0 0 0 4 &pcie2x1l1_intc 3>;
+ 		linux,pci-domain = <3>;
+-		num-ib-windows = <8>;
+-		num-ob-windows = <8>;
+-		num-viewport = <4>;
+ 		max-link-speed = <2>;
+ 		msi-map = <0x3000 &its0 0x3000 0x1000>;
+ 		num-lanes = <1>;
+@@ -1835,13 +1872,15 @@
+ 		power-domains = <&power RK3588_PD_PCIE>;
+ 		ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
+-			 <0x03000000 0x9 0xc0000000 0x9 0xc0000000 0x0 0x40000000>;
++			 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+ 		reg = <0xa 0x40c00000 0x0 0x00400000>,
+ 		      <0x0 0xfe180000 0x0 0x00010000>,
+ 		      <0x0 0xf3000000 0x0 0x00100000>;
+ 		reg-names = "dbi", "apb", "config";
+ 		resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
+ 		reset-names = "pwr", "pipe";
++		#address-cells = <3>;
++		#size-cells = <2>;
+ 		status = "disabled";
+ 
+ 		pcie2x1l1_intc: legacy-interrupt-controller {
+@@ -1855,8 +1894,6 @@
+ 
+ 	pcie2x1l2: pcie@fe190000 {
+ 		compatible = "rockchip,rk3588-pcie", "rockchip,rk3568-pcie";
+-		#address-cells = <3>;
+-		#size-cells = <2>;
+ 		bus-range = <0x40 0x4f>;
+ 		clocks = <&cru ACLK_PCIE_1L2_MSTR>, <&cru ACLK_PCIE_1L2_SLV>,
+ 			 <&cru ACLK_PCIE_1L2_DBI>, <&cru PCLK_PCIE_1L2>,
+@@ -1878,9 +1915,6 @@
+ 				<0 0 0 3 &pcie2x1l2_intc 2>,
+ 				<0 0 0 4 &pcie2x1l2_intc 3>;
+ 		linux,pci-domain = <4>;
+-		num-ib-windows = <8>;
+-		num-ob-windows = <8>;
+-		num-viewport = <4>;
+ 		max-link-speed = <2>;
+ 		msi-map = <0x4000 &its0 0x4000 0x1000>;
+ 		num-lanes = <1>;
+@@ -1889,13 +1923,15 @@
+ 		power-domains = <&power RK3588_PD_PCIE>;
+ 		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+-			 <0x03000000 0xa 0x00000000 0xa 0x00000000 0x0 0x40000000>;
++			 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+ 		reg = <0xa 0x41000000 0x0 0x00400000>,
+ 		      <0x0 0xfe190000 0x0 0x00010000>,
+ 		      <0x0 0xf4000000 0x0 0x00100000>;
+ 		reg-names = "dbi", "apb", "config";
+ 		resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
+ 		reset-names = "pwr", "pipe";
++		#address-cells = <3>;
++		#size-cells = <2>;
+ 		status = "disabled";
+ 
+ 		pcie2x1l2_intc: legacy-interrupt-controller {
+@@ -1970,11 +2006,11 @@
+ 	sata0: sata@fe210000 {
+ 		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ 		reg = <0 0xfe210000 0 0x1000>;
++		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		clocks = <&cru ACLK_SATA0>, <&cru CLK_PMALIVE0>,
+ 			 <&cru CLK_RXOOB0>, <&cru CLK_PIPEPHY0_REF>,
+ 			 <&cru CLK_PIPEPHY0_PIPE_ASIC_G>;
+ 		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+-		interrupts = <GIC_SPI 273 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		ports-implemented = <0x1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -1993,11 +2029,11 @@
+ 	sata2: sata@fe230000 {
+ 		compatible = "rockchip,rk3588-dwc-ahci", "snps,dwc-ahci";
+ 		reg = <0 0xfe230000 0 0x1000>;
++		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		clocks = <&cru ACLK_SATA2>, <&cru CLK_PMALIVE2>,
+ 			 <&cru CLK_RXOOB2>, <&cru CLK_PIPEPHY2_REF>,
+ 			 <&cru CLK_PIPEPHY2_PIPE_ASIC_G>;
+ 		clock-names = "sata", "pmalive", "rxoob", "ref", "asic";
+-		interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>;
+ 		ports-implemented = <0x1>;
+ 		#address-cells = <1>;
+ 		#size-cells = <0>;
+@@ -2651,6 +2687,17 @@
+ 		pinctrl-1 = <&tsadc_shut>;
+ 		pinctrl-names = "gpio", "otpout";
+ 		#thermal-sensor-cells = <1>;
++	};
++
++	saradc: adc@fec10000 {
++		compatible = "rockchip,rk3588-saradc";
++		reg = <0x0 0xfec10000 0x0 0x10000>;
++		interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
++		#io-channel-cells = <1>;
++		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
++		clock-names = "saradc", "apb_pclk";
++		resets = <&cru SRST_P_SARADC>;
++		reset-names = "saradc-apb";
+ 		status = "disabled";
+ 	};
+ 
+@@ -2808,12 +2855,12 @@
+ 	combphy0_ps: phy@fee00000 {
+ 		compatible = "rockchip,rk3588-naneng-combphy";
+ 		reg = <0x0 0xfee00000 0x0 0x100>;
+-		#phy-cells = <1>;
+ 		clocks = <&cru CLK_REF_PIPE_PHY0>, <&cru PCLK_PCIE_COMBO_PIPE_PHY0>,
+ 			 <&cru PCLK_PHP_ROOT>;
+ 		clock-names = "ref", "apb", "pipe";
+ 		assigned-clocks = <&cru CLK_REF_PIPE_PHY0>;
+ 		assigned-clock-rates = <100000000>;
++		#phy-cells = <1>;
+ 		resets = <&cru SRST_REF_PIPE_PHY0>, <&cru SRST_P_PCIE2_PHY0>;
+ 		reset-names = "phy", "apb";
+ 		rockchip,pipe-grf = <&php_grf>;
+@@ -2824,12 +2871,12 @@
+ 	combphy2_psu: phy@fee20000 {
+ 		compatible = "rockchip,rk3588-naneng-combphy";
+ 		reg = <0x0 0xfee20000 0x0 0x100>;
+-		#phy-cells = <1>;
+ 		clocks = <&cru CLK_REF_PIPE_PHY2>, <&cru PCLK_PCIE_COMBO_PIPE_PHY2>,
+ 			 <&cru PCLK_PHP_ROOT>;
+ 		clock-names = "ref", "apb", "pipe";
+ 		assigned-clocks = <&cru CLK_REF_PIPE_PHY2>;
+ 		assigned-clock-rates = <100000000>;
++		#phy-cells = <1>;
+ 		resets = <&cru SRST_REF_PIPE_PHY2>, <&cru SRST_P_PCIE2_PHY2>;
+ 		reset-names = "phy", "apb";
+ 		rockchip,pipe-grf = <&php_grf>;
+@@ -2837,18 +2884,6 @@
+ 		status = "disabled";
+ 	};
+ 
+-	saradc: saradc@fec10000 {
+-		compatible = "rockchip,rk3588-saradc";
+-		reg = <0x0 0xfec10000 0x0 0x10000>;
+-		interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH 0>;
+-		#io-channel-cells = <1>;
+-		clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
+-		clock-names = "saradc", "apb_pclk";
+-		resets = <&cru SRST_P_SARADC>;
+-		reset-names = "saradc-apb";
+-		status = "disabled";
+-	};
+-
+ 	system_sram2: sram@ff001000 {
+ 		compatible = "mmio-sram";
+ 		reg = <0x0 0xff001000 0x0 0xef000>;
+@@ -2924,6 +2959,20 @@
+ 			#interrupt-cells = <2>;
+ 		};
+ 	};
++
++	av1d: av1d@fdc70000 {
++		compatible = "rockchip,rk3588-av1-vpu";
++		reg = <0x0 0xfdc70000 0x0 0x800>;
++		interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "vdpu";
++		clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
++		clock-names = "aclk", "hclk";
++		assigned-clocks = <&cru ACLK_AV1>, <&cru PCLK_AV1>;
++		assigned-clock-rates = <400000000>, <400000000>;
++		resets = <&cru SRST_A_AV1>, <&cru SRST_P_AV1>, <&cru SRST_A_AV1_BIU>, <&cru SRST_P_AV1_BIU>;
++		power-domains = <&power RK3588_PD_AV1>;
++		status = "okay";
++	};
+ };
+ 
+ #include "rk3588s-pinctrl.dtsi"
diff --git a/target/linux/rockchip/patches-6.1/517-usb-typec-tcpm_-try-to-get-role-switch-from-tcpc-fwnode.patch b/target/linux/rockchip/patches-6.1/517-usb-typec-tcpm_-try-to-get-role-switch-from-tcpc-fwnode.patch
new file mode 100644
index 00000000000..b083e8373b7
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/517-usb-typec-tcpm_-try-to-get-role-switch-from-tcpc-fwnode.patch
@@ -0,0 +1,54 @@
+From d56de8c9a17d8f5202d0f37dd06ce186cc512586 Mon Sep 17 00:00:00 2001
+From: Li Jun <jun.li@nxp.com>
+Date: Tue, 28 Mar 2023 16:23:04 +0800
+Subject: [PATCH] usb: typec: tcpm: try to get role switch from tcpc fwnode
+
+Try to get usb role switch from tcpc fwnode if failed to
+get role switch from port dev, this is for case the port
+for role switch endpoint is located in connector node,
+as per connector binding doc, port@0 for HS is required.
+
+ptn5110: tcpc@50 {
+	compatible = "nxp,ptn5110";
+	...
+	status = "okay";
+
+	connector {
+		compatible = "usb-c-connector";
+		label = "USB-C";
+		...
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				typec_conn: endpoint {
+					remote-endpoint = <&usb2_controller>;
+				};
+			};
+		};
+	};
+};
+
+Signed-off-by: Li Jun <jun.li@nxp.com>
+Reviewed-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+Link: https://lore.kernel.org/r/1679991784-25500-1-git-send-email-jun.li@nxp.com
+Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -6595,6 +6595,8 @@ struct tcpm_port *tcpm_register_port(str
+ 	port->port_type = port->typec_caps.type;
+ 
+ 	port->role_sw = usb_role_switch_get(port->dev);
++	if (!port->role_sw)
++		port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode);
+ 	if (IS_ERR(port->role_sw)) {
+ 		err = PTR_ERR(port->role_sw);
+ 		goto out_destroy_wq;
diff --git a/target/linux/rockchip/patches-6.1/518-usb-typec-tcpm-avoid-graph-warning.patch b/target/linux/rockchip/patches-6.1/518-usb-typec-tcpm-avoid-graph-warning.patch
new file mode 100644
index 00000000000..7f75bb6de2a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/518-usb-typec-tcpm-avoid-graph-warning.patch
@@ -0,0 +1,42 @@
+From 396d66b5fc156556b67eb05ef625128917f0610c Mon Sep 17 00:00:00 2001
+From: Sebastian Reichel <sebastian.reichel@collabora.com>
+Date: Fri, 28 Jul 2023 16:43:16 +0200
+Subject: [PATCH 86/98] usb: typec: tcpm: avoid graph warning
+
+When using a devicetree as described in commit d56de8c9a17d ("usb:
+typec: tcpm: try to get role switch from tcpc fwnode"), the kernel
+will print an error when probing the TCPM driver, which looks
+similar to this:
+
+OF: graph: no port node found in /i2c@feac0000/usb-typec@22
+
+This is a false positive, since the code first tries to find a ports
+node for the device and only then checks the fwnode. Fix this by
+swapping the order.
+
+Note, that this will now generate a error message for devicetrees with
+a role-switch ports node directly in the TCPM node instead of in the
+connectors sub-node, before falling back to the legacy behaviour. These
+devicetrees generate warnings when being checked against the bindings,
+and should be fixed.
+
+Fixes: d56de8c9a17d ("usb: typec: tcpm: try to get role switch from tcpc fwnode")
+Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/usb/typec/tcpm/tcpm.c | 4 ++--
+ 1 file changed, 2 insertions(+), 2 deletions(-)
+
+--- a/drivers/usb/typec/tcpm/tcpm.c
++++ b/drivers/usb/typec/tcpm/tcpm.c
+@@ -6594,9 +6594,9 @@ struct tcpm_port *tcpm_register_port(str
+ 	port->partner_desc.identity = &port->partner_ident;
+ 	port->port_type = port->typec_caps.type;
+ 
+-	port->role_sw = usb_role_switch_get(port->dev);
++	port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode);
+ 	if (!port->role_sw)
+-		port->role_sw = fwnode_usb_role_switch_get(tcpc->fwnode);
++		port->role_sw = usb_role_switch_get(port->dev);
+ 	if (IS_ERR(port->role_sw)) {
+ 		err = PTR_ERR(port->role_sw);
+ 		goto out_destroy_wq;
diff --git a/target/linux/rockchip/patches-6.1/519-irqchip-fix-its-timeout-issue.patch b/target/linux/rockchip/patches-6.1/519-irqchip-fix-its-timeout-issue.patch
new file mode 100644
index 00000000000..976658ededd
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/519-irqchip-fix-its-timeout-issue.patch
@@ -0,0 +1,210 @@
+From d441305416aa91190df5865bbc0e3c684ec183b0 Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@protonmail.com>
+Date: Fri, 11 Aug 2023 17:56:00 +0300
+Subject: [PATCH 1/1] irqchip/irq-gic-v3-its: fix its timeout issue for rk35xx
+ boards
+
+---
+ drivers/irqchip/irq-gic-v3-its.c | 79 +++++++++++++++++++++++++++++---
+ 1 file changed, 72 insertions(+), 7 deletions(-)
+
+--- a/drivers/irqchip/irq-gic-v3-its.c
++++ b/drivers/irqchip/irq-gic-v3-its.c
+@@ -167,6 +167,7 @@ struct its_device {
+ 	struct its_node		*its;
+ 	struct event_lpi_map	event_map;
+ 	void			*itt;
++	u32			itt_sz;
+ 	u32			nr_ites;
+ 	u32			device_id;
+ 	bool			shared;
+@@ -2204,6 +2205,9 @@ static void gic_reset_prop_table(void *v
+ static struct page *its_allocate_prop_table(gfp_t gfp_flags)
+ {
+ 	struct page *prop_page;
++	
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
+ 
+ 	prop_page = alloc_pages(gfp_flags, get_order(LPI_PROPBASE_SZ));
+ 	if (!prop_page)
+@@ -2328,6 +2332,7 @@ static int its_setup_baser(struct its_no
+ 	u32 alloc_pages, psz;
+ 	struct page *page;
+ 	void *base;
++	gfp_t gfp_flags;
+ 
+ 	psz = baser->psz;
+ 	alloc_pages = (PAGE_ORDER_TO_SIZE(order) / psz);
+@@ -2339,7 +2344,11 @@ static int its_setup_baser(struct its_no
+ 		order = get_order(GITS_BASER_PAGES_MAX * psz);
+ 	}
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order);
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
++	
++	page = alloc_pages_node(its->numa_node, gfp_flags, order);
+ 	if (!page)
+ 		return -ENOMEM;
+ 
+@@ -2389,6 +2398,15 @@ retry_baser:
+ 	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
+ 		tmp &= ~GITS_BASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588")) {
++		if (tmp & GITS_BASER_SHAREABILITY_MASK)
++			tmp &= ~GITS_BASER_SHAREABILITY_MASK;
++		else
++			gic_flush_dcache_to_poc(base, PAGE_ORDER_TO_SIZE(order));
++	}
++
+ 	if ((val ^ tmp) & GITS_BASER_SHAREABILITY_MASK) {
+ 		/*
+ 		 * Shareability didn't stick. Just use
+@@ -2970,7 +2988,9 @@ static int its_alloc_collections(struct
+ static struct page *its_allocate_pending_table(gfp_t gfp_flags)
+ {
+ 	struct page *pend_page;
+-
++	
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
+ 	pend_page = alloc_pages(gfp_flags | __GFP_ZERO,
+ 				get_order(LPI_PENDBASE_SZ));
+ 	if (!pend_page)
+@@ -3129,6 +3149,11 @@ static void its_cpu_init_lpis(void)
+ 	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
+ 		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588"))
++		tmp &= ~GICR_PROPBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ val) & GICR_PROPBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GICR_PROPBASER_SHAREABILITY_MASK)) {
+ 			/*
+@@ -3156,6 +3181,11 @@ static void its_cpu_init_lpis(void)
+ 	if (gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE)
+ 		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588"))
++		tmp &= ~GICR_PENDBASER_SHAREABILITY_MASK;
++
+ 	if (!(tmp & GICR_PENDBASER_SHAREABILITY_MASK)) {
+ 		/*
+ 		 * The HW reports non-shareable, we must remove the
+@@ -3319,7 +3349,11 @@ static bool its_alloc_table_entry(struct
+ 
+ 	/* Allocate memory for 2nd level table */
+ 	if (!table[idx]) {
+-		page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++		gfp_t gfp_flags = GFP_KERNEL | __GFP_ZERO;
++
++		if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++			gfp_flags |= GFP_DMA32;
++		page = alloc_pages_node(its->numa_node, gfp_flags,
+ 					get_order(baser->psz));
+ 		if (!page)
+ 			return false;
+@@ -3408,6 +3442,7 @@ static struct its_device *its_create_dev
+ 	int nr_lpis;
+ 	int nr_ites;
+ 	int sz;
++	gfp_t gfp_flags;
+ 
+ 	if (!its_alloc_device_table(its, dev_id))
+ 		return NULL;
+@@ -3423,7 +3458,15 @@ static struct its_device *its_create_dev
+ 	nr_ites = max(2, nvecs);
+ 	sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1);
+ 	sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1;
+-	itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node);
++	gfp_flags = GFP_KERNEL;
++	
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588")) {
++		gfp_flags |= GFP_DMA32;
++		itt = (void *)__get_free_pages(gfp_flags, get_order(sz));
++	} else {
++		itt = kzalloc_node(sz, gfp_flags, its->numa_node);
++	}
++
+ 	if (alloc_lpis) {
+ 		lpi_map = its_lpi_alloc(nvecs, &lpi_base, &nr_lpis);
+ 		if (lpi_map)
+@@ -3437,7 +3480,13 @@ static struct its_device *its_create_dev
+ 
+ 	if (!dev || !itt ||  !col_map || (!lpi_map && alloc_lpis)) {
+ 		kfree(dev);
+-		kfree(itt);
++
++		if (of_machine_is_compatible("rockchip,rk3568") ||
++		    of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++			free_pages((unsigned long)itt, get_order(sz));
++		else
++			kfree(itt);
++
+ 		bitmap_free(lpi_map);
+ 		kfree(col_map);
+ 		return NULL;
+@@ -3447,6 +3496,7 @@ static struct its_device *its_create_dev
+ 
+ 	dev->its = its;
+ 	dev->itt = itt;
++	dev->itt_sz = sz;
+ 	dev->nr_ites = nr_ites;
+ 	dev->event_map.lpi_map = lpi_map;
+ 	dev->event_map.col_map = col_map;
+@@ -3474,7 +3524,13 @@ static void its_free_device(struct its_d
+ 	list_del(&its_dev->entry);
+ 	raw_spin_unlock_irqrestore(&its_dev->its->lock, flags);
+ 	kfree(its_dev->event_map.col_map);
+-	kfree(its_dev->itt);
++	
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	    of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		free_pages((unsigned long)its_dev->itt, get_order(its_dev->itt_sz));
++	else
++		kfree(its_dev->itt);
++	
+ 	kfree(its_dev);
+ }
+ 
+@@ -5061,6 +5117,7 @@ static int __init its_probe_one(struct r
+ 	struct page *page;
+ 	u32 ctlr;
+ 	int err;
++	gfp_t gfp_flags;
+ 
+ 	its_base = its_map_one(res, &err);
+ 	if (!its_base)
+@@ -5114,7 +5171,10 @@ static int __init its_probe_one(struct r
+ 
+ 	its->numa_node = numa_node;
+ 
+-	page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO,
++	gfp_flags = GFP_KERNEL | __GFP_ZERO;
++	if (of_machine_is_compatible("rockchip,rk3568") || of_machine_is_compatible("rockchip,rk3566") || of_machine_is_compatible("rockchip,rk3588"))
++		gfp_flags |= GFP_DMA32;
++	page = alloc_pages_node(its->numa_node, gfp_flags,
+ 				get_order(ITS_CMD_QUEUE_SZ));
+ 	if (!page) {
+ 		err = -ENOMEM;
+@@ -5148,6 +5208,11 @@ static int __init its_probe_one(struct r
+ 	if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE)
+ 		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
+ 
++	if (of_machine_is_compatible("rockchip,rk3568") ||
++	     of_machine_is_compatible("rockchip,rk3566") ||
++	     of_machine_is_compatible("rockchip,rk3588"))
++		tmp &= ~GITS_CBASER_SHAREABILITY_MASK;
++
+ 	if ((tmp ^ baser) & GITS_CBASER_SHAREABILITY_MASK) {
+ 		if (!(tmp & GITS_CBASER_SHAREABILITY_MASK)) {
+ 			/*
diff --git a/target/linux/rockchip/patches-6.1/520-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch b/target/linux/rockchip/patches-6.1/520-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch
new file mode 100644
index 00000000000..31882737ab6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/520-arm64-dts-rockchip-Add-sfc-node-to-rk3588s.patch
@@ -0,0 +1,35 @@
+From 3eaf2abd11aa7f3b2fb04d60c64b2c756fe030eb Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@6tel.net>
+Date: Mon, 9 Oct 2023 22:27:26 +0300
+Subject: [PATCH] arm64: dts: rockchip: Add sfc node to rk3588s
+
+Add SFC (SPI Flash) to RK3588S SOC.
+
+Reviewed-by: Dhruva Gole <d-gole@ti.com>
+Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net>
+Link: https://lore.kernel.org/r/d36a64edfaede92ce2e158b0d9dc4f5998e019e3.1696878787.git.efectn@6tel.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 11 +++++++++++
+ 1 file changed, 11 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -2049,6 +2049,17 @@
+ 		};
+ 	};
+ 
++	sfc: spi@fe2b0000 {
++		compatible = "rockchip,sfc";
++		reg = <0x0 0xfe2b0000 0x0 0x4000>;
++		interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH 0>;
++		clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
++		clock-names = "clk_sfc", "hclk_sfc";
++		#address-cells = <1>;
++		#size-cells = <0>;
++		status = "disabled";
++	};
++
+ 	sdmmc: mmc@fe2c0000 {
+ 		compatible = "rockchip,rk3588-dw-mshc", "rockchip,rk3288-dw-mshc";
+ 		reg = <0x0 0xfe2c0000 0x0 0x4000>;
diff --git a/target/linux/rockchip/patches-6.1/521-arm64-dts-rockchip-Add-Orange-Pi-5.patch b/target/linux/rockchip/patches-6.1/521-arm64-dts-rockchip-Add-Orange-Pi-5.patch
new file mode 100644
index 00000000000..63333e14946
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/521-arm64-dts-rockchip-Add-Orange-Pi-5.patch
@@ -0,0 +1,693 @@
+From b6bc755d806eac3fbddb7ea278fc7d2eb57dba4a Mon Sep 17 00:00:00 2001
+From: Muhammed Efe Cetin <efectn@6tel.net>
+Date: Mon, 9 Oct 2023 22:27:27 +0300
+Subject: [PATCH] arm64: dts: rockchip: Add Orange Pi 5
+MIME-Version: 1.0
+Content-Type: text/plain; charset=UTF-8
+Content-Transfer-Encoding: 8bit
+
+Add initial support for OPi5 that includes support for USB2, PCIe2, Sata,
+Sdmmc, SPI Flash, PMIC.
+
+Signed-off-by: Muhammed Efe Cetin <efectn@6tel.net>
+Reviewed-by: Ondřej Jirman <megi@xff.cz>
+Link: https://lore.kernel.org/r/4212da199c9c532b60d380bf1dfa83490e16bc13.1696878787.git.efectn@6tel.net
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/Makefile         |   1 +
+ .../boot/dts/rockchip/rk3588s-orangepi-5.dts  | 662 ++++++++++++++++++
+ 2 files changed, 663 insertions(+)
+ create mode 100644 arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -106,3 +106,4 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-n
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-nanopi-r6c-plus.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-rock-5a.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3588s-orangepi-5.dtb
+--- /dev/null
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-orangepi-5.dts
+@@ -0,0 +1,662 @@
++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
++
++/dts-v1/;
++
++#include <dt-bindings/gpio/gpio.h>
++#include <dt-bindings/leds/common.h>
++#include <dt-bindings/input/input.h>
++#include <dt-bindings/pinctrl/rockchip.h>
++#include "rk3588s.dtsi"
++
++/ {
++	model = "Xunlong Orange Pi 5";
++	compatible = "xunlong,orangepi-5", "rockchip,rk3588s";
++
++	aliases {
++		mmc0 = &sdmmc;
++		serial2 = &uart2;
++	};
++
++	chosen {
++		stdout-path = "serial2:1500000n8";
++	};
++
++	adc-keys {
++		compatible = "adc-keys";
++		io-channels = <&saradc 1>;
++		io-channel-names = "buttons";
++		keyup-threshold-microvolt = <1800000>;
++		poll-interval = <100>;
++
++		button-recovery {
++			label = "Recovery";
++			linux,code = <KEY_VENDOR>;
++			press-threshold-microvolt = <1800>;
++		};
++	};
++
++	leds {
++		compatible = "gpio-leds";
++		pinctrl-names = "default";
++		pinctrl-0 =<&leds_gpio>;
++
++		led-1 {
++			gpios = <&gpio1 RK_PA2 GPIO_ACTIVE_HIGH>;
++			label = "status_led";
++			linux,default-trigger = "heartbeat";
++		};
++	};
++
++	vbus_typec: vbus-typec-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_HIGH>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&typec5v_pwren>;
++		regulator-name = "vbus_typec";
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++
++	vcc5v0_sys: vcc5v0-sys-regulator {
++		compatible = "regulator-fixed";
++		regulator-name = "vcc5v0_sys";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <5000000>;
++		regulator-max-microvolt = <5000000>;
++	};
++
++	vcc_3v3_sd_s0: vcc-3v3-sd-s0-regulator {
++		compatible = "regulator-fixed";
++		enable-active-low;
++		gpios = <&gpio4 RK_PB5 GPIO_ACTIVE_LOW>;
++		regulator-name = "vcc_3v3_sd_s0";
++		regulator-boot-on;
++		regulator-min-microvolt = <3300000>;
++		regulator-max-microvolt = <3300000>;
++		vin-supply = <&vcc_3v3_s3>;
++	};
++
++	vcc3v3_pcie20: vcc3v3-pcie20-regulator {
++		compatible = "regulator-fixed";
++		enable-active-high;
++		gpios = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
++		regulator-name = "vcc3v3_pcie20";
++		regulator-boot-on;
++		regulator-min-microvolt = <1800000>;
++		regulator-max-microvolt = <1800000>;
++		startup-delay-us = <50000>;
++		vin-supply = <&vcc5v0_sys>;
++	};
++};
++
++&combphy0_ps {
++	status = "okay";
++};
++
++&combphy2_psu {
++	status = "okay";
++};
++
++&cpu_b0 {
++	cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b1 {
++	cpu-supply = <&vdd_cpu_big0_s0>;
++};
++
++&cpu_b2 {
++	cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_b3 {
++	cpu-supply = <&vdd_cpu_big1_s0>;
++};
++
++&cpu_l0 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l1 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l2 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&cpu_l3 {
++	cpu-supply = <&vdd_cpu_lit_s0>;
++};
++
++&gmac1 {
++	clock_in_out = "output";
++	phy-handle = <&rgmii_phy1>;
++	phy-mode = "rgmii-rxid";
++	pinctrl-0 = <&gmac1_miim
++		     &gmac1_tx_bus2
++		     &gmac1_rx_bus2
++		     &gmac1_rgmii_clk
++		     &gmac1_rgmii_bus>;
++	pinctrl-names = "default";
++	tx_delay = <0x42>;
++	status = "okay";
++};
++
++&i2c0 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c0m2_xfer>;
++	status = "okay";
++
++	vdd_cpu_big0_s0: regulator@42 {
++		compatible = "rockchip,rk8602";
++		reg = <0x42>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_big0_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <1050000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++
++	vdd_cpu_big1_s0: regulator@43 {
++		compatible = "rockchip,rk8603", "rockchip,rk8602";
++		reg = <0x43>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_cpu_big1_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <1050000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&i2c2 {
++	status = "okay";
++
++	vdd_npu_s0: regulator@42 {
++		compatible = "rockchip,rk8602";
++		reg = <0x42>;
++		fcs,suspend-voltage-selector = <1>;
++		regulator-name = "vdd_npu_s0";
++		regulator-always-on;
++		regulator-boot-on;
++		regulator-min-microvolt = <550000>;
++		regulator-max-microvolt = <950000>;
++		regulator-ramp-delay = <2300>;
++		vin-supply = <&vcc5v0_sys>;
++
++		regulator-state-mem {
++			regulator-off-in-suspend;
++		};
++	};
++};
++
++&i2c6 {
++	pinctrl-names = "default";
++	pinctrl-0 = <&i2c6m3_xfer>;
++	status = "okay";
++
++	hym8563: rtc@51 {
++		compatible = "haoyu,hym8563";
++		reg = <0x51>;
++		#clock-cells = <0>;
++		clock-output-names = "hym8563";
++		pinctrl-names = "default";
++		pinctrl-0 = <&hym8563_int>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <RK_PB0 IRQ_TYPE_LEVEL_LOW>;
++		wakeup-source;
++	};
++};
++
++&mdio1 {
++	rgmii_phy1: ethernet-phy@1 {
++		compatible = "ethernet-phy-ieee802.3-c22";
++		reg = <0x1>;
++		reset-assert-us = <20000>;
++		reset-deassert-us = <100000>;
++		reset-gpios = <&gpio3 RK_PB2 GPIO_ACTIVE_LOW>;
++	};
++};
++
++&pcie2x1l2 {
++	reset-gpios = <&gpio3 RK_PD1 GPIO_ACTIVE_HIGH>;
++	vpcie3v3-supply = <&vcc3v3_pcie20>;
++	status = "okay";
++};
++
++&pinctrl {
++	gpio-func {
++		leds_gpio: leds-gpio {
++			rockchip,pins = <0 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	hym8563 {
++		hym8563_int: hym8563-int {
++			rockchip,pins = <0 RK_PB0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++
++	usb-typec {
++		usbc0_int: usbc0-int {
++			rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_up>;
++		};
++
++		typec5v_pwren: typec5v-pwren {
++			rockchip,pins = <3 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
++		};
++	};
++};
++
++&saradc {
++	vref-supply = <&avcc_1v8_s0>;
++	status = "okay";
++};
++
++&sdmmc {
++	bus-width = <4>;
++	cap-sd-highspeed;
++	disable-wp;
++	max-frequency = <150000000>;
++	no-mmc;
++	no-sdio;
++	sd-uhs-sdr104;
++	vmmc-supply = <&vcc_3v3_sd_s0>;
++	vqmmc-supply = <&vccio_sd_s0>;
++	status = "okay";
++};
++
++&sfc {
++	pinctrl-names = "default";
++	pinctrl-0 = <&fspim0_pins>;
++	status = "okay";
++
++	flash@0 {
++		compatible = "jedec,spi-nor";
++		reg = <0x0>;
++		spi-max-frequency = <100000000>;
++		spi-rx-bus-width = <4>;
++		spi-tx-bus-width = <1>;
++	};
++};
++
++&spi2 {
++	status = "okay";
++	assigned-clocks = <&cru CLK_SPI2>;
++	assigned-clock-rates = <200000000>;
++	num-cs = <1>;
++	pinctrl-names = "default";
++	pinctrl-0 = <&spi2m2_cs0 &spi2m2_pins>;
++
++	pmic@0 {
++		compatible = "rockchip,rk806";
++		reg = <0x0>;
++		interrupt-parent = <&gpio0>;
++		interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
++		pinctrl-names = "default";
++		pinctrl-0 = <&pmic_pins>, <&rk806_dvs1_null>,
++				<&rk806_dvs2_null>, <&rk806_dvs3_null>;
++		spi-max-frequency = <1000000>;
++
++		vcc1-supply = <&vcc5v0_sys>;
++		vcc2-supply = <&vcc5v0_sys>;
++		vcc3-supply = <&vcc5v0_sys>;
++		vcc4-supply = <&vcc5v0_sys>;
++		vcc5-supply = <&vcc5v0_sys>;
++		vcc6-supply = <&vcc5v0_sys>;
++		vcc7-supply = <&vcc5v0_sys>;
++		vcc8-supply = <&vcc5v0_sys>;
++		vcc9-supply = <&vcc5v0_sys>;
++		vcc10-supply = <&vcc5v0_sys>;
++		vcc11-supply = <&vcc_2v0_pldo_s3>;
++		vcc12-supply = <&vcc5v0_sys>;
++		vcc13-supply = <&vcc_1v1_nldo_s3>;
++		vcc14-supply = <&vcc_1v1_nldo_s3>;
++		vcca-supply = <&vcc5v0_sys>;
++
++		gpio-controller;
++		#gpio-cells = <2>;
++
++		rk806_dvs1_null: dvs1-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs2_null: dvs2-null-pins {
++			pins = "gpio_pwrctrl2";
++			function = "pin_fun0";
++		};
++
++		rk806_dvs3_null: dvs3-null-pins {
++			pins = "gpio_pwrctrl3";
++			function = "pin_fun0";
++		};
++
++		regulators {
++			vdd_gpu_s0: dcdc-reg1 {
++				regulator-name = "vdd_gpu_s0";
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++				regulator-enable-ramp-delay = <400>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_cpu_lit_s0: dcdc-reg2 {
++				regulator-name = "vdd_cpu_lit_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_log_s0: dcdc-reg3 {
++				regulator-name = "vdd_log_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <750000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <750000>;
++				};
++			};
++
++			vdd_vdenc_s0: dcdc-reg4 {
++				regulator-name = "vdd_vdenc_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <550000>;
++				regulator-max-microvolt = <950000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_ddr_s0: dcdc-reg5 {
++				regulator-name = "vdd_ddr_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <675000>;
++				regulator-max-microvolt = <900000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <850000>;
++				};
++			};
++
++			vcc_1v1_nldo_s3: vdd2_ddr_s3: dcdc-reg6 {
++				regulator-name = "vdd2_ddr_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-max-microvolt = <1100000>;
++				regulator-min-microvolt = <1100000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++				};
++			};
++
++			vcc_2v0_pldo_s3: dcdc-reg7 {
++				regulator-name = "vdd_2v0_pldo_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <2000000>;
++				regulator-max-microvolt = <2000000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <2000000>;
++				};
++			};
++
++			vcc_3v3_s3: dcdc-reg8 {
++				regulator-name = "vcc_3v3_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <3300000>;
++				};
++			};
++
++			vddq_ddr_s0: dcdc-reg9 {
++				regulator-name = "vddq_ddr_s0";
++				regulator-always-on;
++				regulator-boot-on;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8_s3: dcdc-reg10 {
++				regulator-name = "vcc_1v8_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			avcc_1v8_s0: pldo-reg1 {
++				regulator-name = "avcc_1v8_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_1v8_s0: pldo-reg2 {
++				regulator-name = "vcc_1v8_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			avdd_1v2_s0: pldo-reg3 {
++				regulator-name = "avdd_1v2_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1200000>;
++				regulator-max-microvolt = <1200000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vcc_3v3_s0: pldo-reg4 {
++				regulator-name = "vcc_3v3_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <3300000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vccio_sd_s0: pldo-reg5 {
++				regulator-name = "vccio_sd_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <3300000>;
++				regulator-ramp-delay = <12500>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			pldo6_s3: pldo-reg6 {
++				regulator-name = "pldo6_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <1800000>;
++				regulator-max-microvolt = <1800000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <1800000>;
++				};
++			};
++
++			vdd_0v75_s3: nldo-reg1 {
++				regulator-name = "vdd_0v75_s3";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++
++				regulator-state-mem {
++					regulator-on-in-suspend;
++					regulator-suspend-microvolt = <750000>;
++				};
++			};
++
++			vdd_ddr_pll_s0: nldo-reg2 {
++				regulator-name = "vdd_ddr_pll_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <850000>;
++				regulator-max-microvolt = <850000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++					regulator-suspend-microvolt = <850000>;
++				};
++			};
++
++			avdd_0v75_s0: nldo-reg3 {
++				regulator-name = "avdd_0v75_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_0v85_s0: nldo-reg4 {
++				regulator-name = "vdd_0v85_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <850000>;
++				regulator-max-microvolt = <850000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++
++			vdd_0v75_s0: nldo-reg5 {
++				regulator-name = "vdd_0v75_s0";
++				regulator-always-on;
++				regulator-boot-on;
++				regulator-min-microvolt = <750000>;
++				regulator-max-microvolt = <750000>;
++
++				regulator-state-mem {
++					regulator-off-in-suspend;
++				};
++			};
++		};
++	};
++};
++
++&tsadc {
++	status = "okay";
++};
++
++&u2phy2 {
++	status = "okay";
++};
++
++&u2phy2_host {
++	status = "okay";
++};
++
++&u2phy3 {
++	status = "okay";
++};
++
++&u2phy3_host {
++	status = "okay";
++};
++
++&uart2 {
++	pinctrl-0 = <&uart2m0_xfer>;
++	status = "okay";
++};
++
++&usb_host0_ehci {
++	status = "okay";
++};
++
++&usb_host0_ohci {
++	status = "okay";
++};
++
++&usb_host1_ehci {
++	status = "okay";
++};
++
++&usb_host1_ohci {
++	status = "okay";
++};
diff --git a/target/linux/rockchip/patches-6.1/522-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch b/target/linux/rockchip/patches-6.1/522-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch
new file mode 100644
index 00000000000..25526ba23cc
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/522-arm64-dts-rockchip-Add-I2S2-M0-pin-definitions-to-rk.patch
@@ -0,0 +1,58 @@
+From bf012368bb0ab69167d49715789fac34dfcd457e Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 8 Oct 2023 15:04:59 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add I2S2 M0 pin definitions to rk3588s
+
+This is used on Orange Pi 5 Plus.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Link: https://lore.kernel.org/r/20231008130515.1155664-2-megi@xff.cz
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ .../boot/dts/rockchip/rk3588s-pinctrl.dtsi    | 35 +++++++++++++++++++
+ 1 file changed, 35 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
+@@ -1350,6 +1350,41 @@
+ 
+ 	i2s2 {
+ 		/omit-if-no-ref/
++		i2s2m0_lrck: i2s2m0-lrck {
++			rockchip,pins =
++				/* i2s2m0_lrck */
++				<2 RK_PC0 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_mclk: i2s2m0-mclk {
++			rockchip,pins =
++				/* i2s2m0_mclk */
++				<2 RK_PB6 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_sclk: i2s2m0-sclk {
++			rockchip,pins =
++				/* i2s2m0_sclk */
++				<2 RK_PB7 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_sdi: i2s2m0-sdi {
++			rockchip,pins =
++				/* i2s2m0_sdi */
++				<2 RK_PC3 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
++		i2s2m0_sdo: i2s2m0-sdo {
++			rockchip,pins =
++				/* i2s2m0_sdo */
++				<4 RK_PC3 2 &pcfg_pull_none>;
++		};
++
++		/omit-if-no-ref/
+ 		i2s2m1_lrck: i2s2m1-lrck {
+ 			rockchip,pins =
+ 				/* i2s2m1_lrck */
diff --git a/target/linux/rockchip/patches-6.1/523-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch b/target/linux/rockchip/patches-6.1/523-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch
new file mode 100644
index 00000000000..4a9cb6ea395
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/523-arm64-dts-rockchip-Add-UART9-M0-pin-definitions-to-r.patch
@@ -0,0 +1,32 @@
+From 3d77a3e51b0faed820a8db985dce5af1cc4eae32 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Sun, 8 Oct 2023 15:05:00 +0200
+Subject: [PATCH] arm64: dts: rockchip: Add UART9 M0 pin definitions to rk3588s
+
+This is used on Orange Pi 5 Plus.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Link: https://lore.kernel.org/r/20231008130515.1155664-3-megi@xff.cz
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi | 9 +++++++++
+ 1 file changed, 9 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s-pinctrl.dtsi
+@@ -3343,6 +3343,15 @@
+ 
+ 	uart9 {
+ 		/omit-if-no-ref/
++		uart9m0_xfer: uart9m0-xfer {
++			rockchip,pins =
++				/* uart9_rx_m0 */
++				<2 RK_PC4 10 &pcfg_pull_up>,
++				/* uart9_tx_m0 */
++				<2 RK_PC2 10 &pcfg_pull_up>;
++		};
++
++		/omit-if-no-ref/
+ 		uart9m1_xfer: uart9m1-xfer {
+ 			rockchip,pins =
+ 				/* uart9_rx_m1 */
diff --git a/target/linux/rockchip/patches-6.1/524-1-dt-bindings-PCI-dwc-rockchip-Add-atu-property.patch b/target/linux/rockchip/patches-6.1/524-1-dt-bindings-PCI-dwc-rockchip-Add-atu-property.patch
new file mode 100644
index 00000000000..8e7fac9d463
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/524-1-dt-bindings-PCI-dwc-rockchip-Add-atu-property.patch
@@ -0,0 +1,43 @@
+From a46b2e6952fb8a8165cffe06b3896cd755901856 Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <niklas.cassel@wdc.com>
+Date: Tue, 24 Oct 2023 17:10:08 +0200
+Subject: [PATCH 1/4] dt-bindings: PCI: dwc: rockchip: Add atu property
+
+Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml
+using:
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+and snps,dw-pcie.yaml does have the atu property defined, in order to be
+able to use this property, while still making sure 'make CHECK_DTBS=y'
+pass, we need to add this property to rockchip-dw-pcie.yaml.
+
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+---
+ Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -29,16 +29,20 @@ properties:
+           - const: rockchip,rk3568-pcie
+ 
+   reg:
++    minItems: 3
+     items:
+       - description: Data Bus Interface (DBI) registers
+       - description: Rockchip designed configuration registers
+       - description: Config registers
++      - description: iATU registers
+ 
+   reg-names:
++    minItems: 3
+     items:
+       - const: dbi
+       - const: apb
+       - const: config
++      - const: atu
+ 
+   clocks:
+     minItems: 5
diff --git a/target/linux/rockchip/patches-6.1/524-2-arm64-dts-rockchip-add-missing-mandatory-rk3588-PCIe.patch b/target/linux/rockchip/patches-6.1/524-2-arm64-dts-rockchip-add-missing-mandatory-rk3588-PCIe.patch
new file mode 100644
index 00000000000..5eda78028f6
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/524-2-arm64-dts-rockchip-add-missing-mandatory-rk3588-PCIe.patch
@@ -0,0 +1,125 @@
+From cfe52e84e30b591175229a461f278f53266f2705 Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <niklas.cassel@wdc.com>
+Date: Tue, 24 Oct 2023 17:10:09 +0200
+Subject: [PATCH 2/4] arm64: dts: rockchip: add missing mandatory rk3588 PCIe
+ atu property
+
+From the snps,dw-pcie.yaml devicetree binding:
+"At least DBI reg-space and peripheral devices CFG-space outbound window
+are required for the normal controller work. iATU memory IO region is
+also required if the space is unrolled (IP-core version >= 4.80a)."
+
+All the PCIe controllers in rk3588 are using the iATU unroll feature,
+and thus have to supply the atu property in the device tree node.
+
+The size of the iATU region equals to:
+MAX(num inbound ATU regions, num outbound ATU regions) * 0x200.
+
+Where for each 0x200 region, the registers controlling the
+IATU_REGION_OUTBOUND starts at offset 0x0, and the registers controlling
+IATU_REGION_INBOUND starts at offset 0x100.
+
+pcie3x4 and pcie3x2 have 16 ATU inbound regions, 16 ATU outbound regions,
+so they have size: max(16, 16) * 0x200 = 0x2000
+
+pcie2x1l0, pcie2x1l1, and pcie2x1l2 have 8 ATU inbound regions, 8 ATU
+outbound regions, so they have size: max(8, 8) * 0x200 = 0x1000
+
+On the rk3588 based rock-5b board:
+Before this patch, dw_pcie_iatu_detect() fails to detect all iATUs:
+rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
+rockchip-dw-pcie a41000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
+rockchip-dw-pcie a40800000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
+
+After this patch, dw_pcie_iatu_detect() succeeds to detect all iATUs:
+rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G
+rockchip-dw-pcie a41000000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
+rockchip-dw-pcie a40800000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G
+
+Fixes: 8d81b77f4c49 ("arm64: dts: rockchip: add rk3588 PCIe2 support")
+Fixes: 0acf4fa7f187 ("arm64: dts: rockchip: add PCIe3 support for rk3588")
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi  | 21 ++++++++++++---------
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 14 ++++++++------
+ 2 files changed, 20 insertions(+), 15 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -198,10 +198,11 @@
+ 		ranges = <0x01000000 0x0 0xf0100000 0x0 0xf0100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf0200000 0x0 0xf0200000 0x0 0x00e00000>,
+ 			 <0x03000000 0x0 0x40000000 0x9 0x00000000 0x0 0x40000000>;
+-		reg = <0xa 0x40000000 0x0 0x00400000>,
++		reg = <0xa 0x40000000 0x0 0x00300000>,
+ 		      <0x0 0xfe150000 0x0 0x00010000>,
+-		      <0x0 0xf0000000 0x0 0x00100000>;
+-		reg-names = "dbi", "apb", "config";
++		      <0x0 0xf0000000 0x0 0x00100000>,
++		      <0xa 0x40300000 0x0 0x00002000>;
++		reg-names = "dbi", "apb", "config", "atu";
+ 		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ 		reset-names = "pwr", "pipe";
+ 		status = "disabled";
+@@ -249,10 +250,11 @@
+ 		ranges = <0x01000000 0x0 0xf1100000 0x0 0xf1100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf1200000 0x0 0xf1200000 0x0 0x00e00000>,
+ 			 <0x03000000 0x0 0x40000000 0x9 0x40000000 0x0 0x40000000>;
+-		reg = <0xa 0x40400000 0x0 0x00400000>,
++		reg = <0xa 0x40400000 0x0 0x00300000>,
+ 		      <0x0 0xfe160000 0x0 0x00010000>,
+-		      <0x0 0xf1000000 0x0 0x00100000>;
+-		reg-names = "dbi", "apb", "config";
++		      <0x0 0xf1000000 0x0 0x00100000>,
++		      <0xa 0x40700000 0x0 0x00002000>;
++		reg-names = "dbi", "apb", "config", "atu";
+ 		resets = <&cru SRST_PCIE1_POWER_UP>, <&cru SRST_P_PCIE1>;
+ 		reset-names = "pwr", "pipe";
+ 		status = "disabled";
+@@ -298,10 +300,11 @@
+ 		ranges = <0x01000000 0x0 0xf2100000 0x0 0xf2100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf2200000 0x0 0xf2200000 0x0 0x00e00000>,
+ 			 <0x03000000 0x0 0x40000000 0x9 0x80000000 0x0 0x40000000>;
+-		reg = <0xa 0x40800000 0x0 0x00400000>,
++		reg = <0xa 0x40800000 0x0 0x00300000>,
+ 		      <0x0 0xfe170000 0x0 0x00010000>,
+-		      <0x0 0xf2000000 0x0 0x00100000>;
+-		reg-names = "dbi", "apb", "config";
++		      <0x0 0xf2000000 0x0 0x00100000>,
++		      <0xa 0x40b00000 0x0 0x00001000>;
++		reg-names = "dbi", "apb", "config", "atu";
+ 		resets = <&cru SRST_PCIE2_POWER_UP>, <&cru SRST_P_PCIE2>;
+ 		reset-names = "pwr", "pipe";
+ 		#address-cells = <3>;
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1873,10 +1873,11 @@
+ 		ranges = <0x01000000 0x0 0xf3100000 0x0 0xf3100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf3200000 0x0 0xf3200000 0x0 0x00e00000>,
+ 			 <0x03000000 0x0 0x40000000 0x9 0xc0000000 0x0 0x40000000>;
+-		reg = <0xa 0x40c00000 0x0 0x00400000>,
++		reg = <0xa 0x40c00000 0x0 0x00300000>,
+ 		      <0x0 0xfe180000 0x0 0x00010000>,
+-		      <0x0 0xf3000000 0x0 0x00100000>;
+-		reg-names = "dbi", "apb", "config";
++		      <0x0 0xf3000000 0x0 0x00100000>,
++		      <0xa 0x40f00000 0x0 0x00001000>;
++		reg-names = "dbi", "apb", "config", "atu";
+ 		resets = <&cru SRST_PCIE3_POWER_UP>, <&cru SRST_P_PCIE3>;
+ 		reset-names = "pwr", "pipe";
+ 		#address-cells = <3>;
+@@ -1924,10 +1925,11 @@
+ 		ranges = <0x01000000 0x0 0xf4100000 0x0 0xf4100000 0x0 0x00100000>,
+ 			 <0x02000000 0x0 0xf4200000 0x0 0xf4200000 0x0 0x00e00000>,
+ 			 <0x03000000 0x0 0x40000000 0xa 0x00000000 0x0 0x40000000>;
+-		reg = <0xa 0x41000000 0x0 0x00400000>,
++		reg = <0xa 0x41000000 0x0 0x00300000>,
+ 		      <0x0 0xfe190000 0x0 0x00010000>,
+-		      <0x0 0xf4000000 0x0 0x00100000>;
+-		reg-names = "dbi", "apb", "config";
++		      <0x0 0xf4000000 0x0 0x00100000>,
++		      <0xa 0x41300000 0x0 0x00001000>;
++		reg-names = "dbi", "apb", "config", "atu";
+ 		resets = <&cru SRST_PCIE4_POWER_UP>, <&cru SRST_P_PCIE4>;
+ 		reset-names = "pwr", "pipe";
+ 		#address-cells = <3>;
diff --git a/target/linux/rockchip/patches-6.1/524-3-dt-bindings-PCI-dwc-rockchip-Add-dma-properties.patch b/target/linux/rockchip/patches-6.1/524-3-dt-bindings-PCI-dwc-rockchip-Add-dma-properties.patch
new file mode 100644
index 00000000000..c615142d33f
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/524-3-dt-bindings-PCI-dwc-rockchip-Add-dma-properties.patch
@@ -0,0 +1,78 @@
+From 0dd352eeb32e4e729060361afc194eb4c7c24e16 Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <niklas.cassel@wdc.com>
+Date: Tue, 24 Oct 2023 17:10:10 +0200
+Subject: [PATCH 3/4] dt-bindings: PCI: dwc: rockchip: Add dma properties
+
+Even though rockchip-dw-pcie.yaml inherits snps,dw-pcie.yaml
+using:
+
+allOf:
+  - $ref: /schemas/pci/snps,dw-pcie.yaml#
+
+and snps,dw-pcie.yaml does have the dma properties defined, in order to be
+able to use these properties, while still making sure 'make CHECK_DTBS=y'
+pass, we need to add these properties to rockchip-dw-pcie.yaml.
+
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+---
+ .../bindings/pci/rockchip-dw-pcie.yaml        | 20 +++++++++++++++++++
+ 1 file changed, 20 insertions(+)
+
+--- a/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
++++ b/Documentation/devicetree/bindings/pci/rockchip-dw-pcie.yaml
+@@ -35,6 +35,7 @@ properties:
+       - description: Rockchip designed configuration registers
+       - description: Config registers
+       - description: iATU registers
++      - description: eDMA registers
+ 
+   reg-names:
+     minItems: 3
+@@ -43,6 +44,7 @@ properties:
+       - const: apb
+       - const: config
+       - const: atu
++      - const: dma
+ 
+   clocks:
+     minItems: 5
+@@ -65,6 +67,7 @@ properties:
+       - const: pipe
+ 
+   interrupts:
++    minItems: 5
+     items:
+       - description:
+           Combined system interrupt, which is used to signal the following
+@@ -88,14 +91,31 @@ properties:
+           interrupts - aer_rc_err, aer_rc_err_msi, rx_cpl_timeout,
+           tx_cpl_timeout, cor_err_sent, nf_err_sent, f_err_sent, cor_err_rx,
+           nf_err_rx, f_err_rx, radm_qoverflow
++      - description:
++          Indicates that the eDMA Tx/Rx transfer is complete or that an
++          error has occurred on the corresponding channel.
++      - description:
++          Indicates that the eDMA Tx/Rx transfer is complete or that an
++          error has occurred on the corresponding channel.
++      - description:
++          Indicates that the eDMA Tx/Rx transfer is complete or that an
++          error has occurred on the corresponding channel.
++      - description:
++          Indicates that the eDMA Tx/Rx transfer is complete or that an
++          error has occurred on the corresponding channel.
+ 
+   interrupt-names:
++    minItems: 5
+     items:
+       - const: sys
+       - const: pmc
+       - const: msg
+       - const: legacy
+       - const: err
++      - const: dma0
++      - const: dma1
++      - const: dma2
++      - const: dma3
+ 
+   legacy-interrupt-controller:
+     description: Interrupt controller node for handling legacy PCI interrupts.
diff --git a/target/linux/rockchip/patches-6.1/525-arm64-dts-rockchip-add-missing-rk3588-PCIe-dma-prope.patch b/target/linux/rockchip/patches-6.1/525-arm64-dts-rockchip-add-missing-rk3588-PCIe-dma-prope.patch
new file mode 100644
index 00000000000..cbf46c01848
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/525-arm64-dts-rockchip-add-missing-rk3588-PCIe-dma-prope.patch
@@ -0,0 +1,63 @@
+From dcf394c09e5d49f02a906e2113fb39e67ebe3d1f Mon Sep 17 00:00:00 2001
+From: Niklas Cassel <niklas.cassel@wdc.com>
+Date: Sat, 21 Oct 2023 00:44:11 +0200
+Subject: [PATCH 2/2] arm64: dts: rockchip: add missing rk3588 PCIe dma
+ properties
+
+The rk3588 has 5 PCIe controllers, however, according the the rk3588 TRM
+(Technical Reference Manual), only pcie3x4 supports the embedded DMA
+controller (eDMA) on the DWC PCIe controller.
+
+The size of the eDMA region equals to:
+0x200 + MAX(NUM_DMA_RD_CHAN, NUM_DMA_WR_CHAN) * 0x200.
+
+Where for each 0x200 region, the registers controlling the write channel
+starts at offset 0x0, and the registers controlling the read channel
+starts at offset 0x100.
+
+pcie3x4 has two DMA read channels and two DMA write channels,
+so it has size: 0x200 + max(2, 2) * 0x200 = 0x600
+
+On the rk3588 based rock-5b board, when building with CONFIG_DW_EDMA=y:
+Before this patch, only the iATUs are detected:
+rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G
+
+After this patch, both the iATUs and the eDMA channels are detected:
+rockchip-dw-pcie a40000000.pcie: iATU: unroll T, 16 ob, 16 ib, align 64K, limit 8G
+rockchip-dw-pcie a40000000.pcie: eDMA: unroll T, 2 wr, 2 rd
+
+Signed-off-by: Niklas Cassel <niklas.cassel@wdc.com>
+---
+ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 14 ++++++++++----
+ 1 file changed, 10 insertions(+), 4 deletions(-)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588.dtsi
+@@ -180,8 +180,13 @@
+ 			     <GIC_SPI 262 IRQ_TYPE_LEVEL_HIGH 0>,
+ 			     <GIC_SPI 261 IRQ_TYPE_LEVEL_HIGH 0>,
+ 			     <GIC_SPI 260 IRQ_TYPE_LEVEL_HIGH 0>,
+-			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>;
+-		interrupt-names = "sys", "pmc", "msg", "legacy", "err";
++			     <GIC_SPI 259 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH 0>,
++			     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH 0>;
++		interrupt-names = "sys", "pmc", "msg", "legacy", "err",
++				  "dma0", "dma1", "dma2", "dma3";
+ 		#interrupt-cells = <1>;
+ 		interrupt-map-mask = <0 0 0 7>;
+ 		interrupt-map = <0 0 0 1 &pcie3x4_intc 0>,
+@@ -201,8 +206,9 @@
+ 		reg = <0xa 0x40000000 0x0 0x00300000>,
+ 		      <0x0 0xfe150000 0x0 0x00010000>,
+ 		      <0x0 0xf0000000 0x0 0x00100000>,
+-		      <0xa 0x40300000 0x0 0x00002000>;
+-		reg-names = "dbi", "apb", "config", "atu";
++		      <0xa 0x40300000 0x0 0x00002000>,
++		      <0xa 0x40380000 0x0 0x00000600>;
++		reg-names = "dbi", "apb", "config", "atu", "dma";
+ 		resets = <&cru SRST_PCIE0_POWER_UP>, <&cru SRST_P_PCIE0>;
+ 		reset-names = "pwr", "pipe";
+ 		status = "disabled";
diff --git a/target/linux/rockchip/patches-6.1/526-dt-bindings-usb-rockchip-dwc3-fix-reference-to-nonex.patch b/target/linux/rockchip/patches-6.1/526-dt-bindings-usb-rockchip-dwc3-fix-reference-to-nonex.patch
new file mode 100644
index 00000000000..af993c1ee4c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/526-dt-bindings-usb-rockchip-dwc3-fix-reference-to-nonex.patch
@@ -0,0 +1,29 @@
+From e60a641980644156bc91f494b2764fe50d7185e8 Mon Sep 17 00:00:00 2001
+From: Vegard Nossum <vegard.nossum@oracle.com>
+Date: Sun, 22 Oct 2023 20:51:50 +0200
+Subject: [PATCH] dt-bindings: usb: rockchip,dwc3: fix reference to nonexistent
+ file
+
+This file was renamed but left a dangling reference. Fix it.
+
+Fixes: 0f48b0ed356d ("dt-bindings: phy: rename phy-rockchip-inno-usb2.yaml")
+Cc: Johan Jonker <jbx6244@gmail.com>
+Cc: Vinod Koul <vkoul@kernel.org>
+Cc: Rob Herring <robh@kernel.org>
+Cc: Heiko Stuebner <heiko@sntech.de>
+Signed-off-by: Vegard Nossum <vegard.nossum@oracle.com>
+---
+ Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml | 2 +-
+ 1 file changed, 1 insertion(+), 1 deletion(-)
+
+--- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
++++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml
+@@ -15,7 +15,7 @@ description:
+   Phy documentation is provided in the following places.
+ 
+   USB2.0 PHY
+-  Documentation/devicetree/bindings/phy/phy-rockchip-inno-usb2.yaml
++  Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
+ 
+   Type-C PHY
+   Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
diff --git a/target/linux/rockchip/patches-6.1/527-dt-bindings-mfd-rk8xx-Deprecate-rockchip-system-powe.patch b/target/linux/rockchip/patches-6.1/527-dt-bindings-mfd-rk8xx-Deprecate-rockchip-system-powe.patch
new file mode 100644
index 00000000000..9b43288daee
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/527-dt-bindings-mfd-rk8xx-Deprecate-rockchip-system-powe.patch
@@ -0,0 +1,95 @@
+From cead8c188a5d93385c587692ee9a572602c4d4cf Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 19 Oct 2023 18:57:23 +0200
+Subject: [PATCH] dt-bindings: mfd: rk8xx: Deprecate
+ rockchip,system-power-controller
+
+Deprecate support for this property in favor of standard
+system-power-controller one.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml | 3 +++
+ Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml | 3 +++
+ Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml | 3 +++
+ Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml | 3 +++
+ Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml | 3 +++
+ 5 files changed, 15 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk805.yaml
+@@ -42,9 +42,12 @@ properties:
+ 
+   rockchip,system-power-controller:
+     type: boolean
++    deprecated: true
+     description:
+       Telling whether or not this PMIC is controlling the system power.
+ 
++  system-power-controller: true
++
+   wakeup-source:
+     type: boolean
+     description:
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk808.yaml
+@@ -37,9 +37,12 @@ properties:
+ 
+   rockchip,system-power-controller:
+     type: boolean
++    deprecated: true
+     description:
+       Telling whether or not this PMIC is controlling the system power.
+ 
++  system-power-controller: true
++
+   wakeup-source:
+     type: boolean
+     description:
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk809.yaml
+@@ -37,9 +37,12 @@ properties:
+ 
+   rockchip,system-power-controller:
+     type: boolean
++    deprecated: true
+     description:
+       Telling whether or not this PMIC is controlling the system power.
+ 
++  system-power-controller: true
++
+   wakeup-source:
+     type: boolean
+     description:
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk817.yaml
+@@ -38,9 +38,12 @@ properties:
+ 
+   rockchip,system-power-controller:
+     type: boolean
++    deprecated: true
+     description:
+       Telling whether or not this PMIC is controlling the system power.
+ 
++  system-power-controller: true
++
+   wakeup-source:
+     type: boolean
+     description:
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk818.yaml
+@@ -37,9 +37,12 @@ properties:
+ 
+   rockchip,system-power-controller:
+     type: boolean
++    deprecated: true
+     description:
+       Telling whether or not this PMIC is controlling the system power.
+ 
++  system-power-controller: true
++
+   wakeup-source:
+     type: boolean
+     description:
diff --git a/target/linux/rockchip/patches-6.1/528-dt-bindings-mfd-rk806-Allow-system-power-controller-.patch b/target/linux/rockchip/patches-6.1/528-dt-bindings-mfd-rk806-Allow-system-power-controller-.patch
new file mode 100644
index 00000000000..fd5fd9c824a
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/528-dt-bindings-mfd-rk806-Allow-system-power-controller-.patch
@@ -0,0 +1,26 @@
+From 198dedeb1281ca377d9d4f657e25ebd7d4ae8c91 Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 19 Oct 2023 18:57:24 +0200
+Subject: [PATCH] dt-bindings: mfd: rk806: Allow system-power-controller
+ property
+
+Declare support for this property.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Reviewed-by: Rob Herring <robh@kernel.org>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml | 2 ++
+ 1 file changed, 2 insertions(+)
+
+--- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
++++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml
+@@ -29,6 +29,8 @@ properties:
+   '#gpio-cells':
+     const: 2
+ 
++  system-power-controller: true
++
+   vcc1-supply:
+     description:
+       The input supply for dcdc-reg1.
diff --git a/target/linux/rockchip/patches-6.1/529-mfd-rk8xx-Add-support-for-standard-system-power-cont.patch b/target/linux/rockchip/patches-6.1/529-mfd-rk8xx-Add-support-for-standard-system-power-cont.patch
new file mode 100644
index 00000000000..78d80bba0ff
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/529-mfd-rk8xx-Add-support-for-standard-system-power-cont.patch
@@ -0,0 +1,26 @@
+From ae5180c9d0bc240f0656d36ec1eab9be37c1eb9f Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 19 Oct 2023 18:57:25 +0200
+Subject: [PATCH] mfd: rk8xx: Add support for standard system-power-controller
+ property
+
+DT property rockchip,system-power-controller is now deprecated.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/mfd/rk8xx-core.c | 3 ++-
+ 1 file changed, 2 insertions(+), 1 deletion(-)
+
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -685,7 +685,8 @@ int rk8xx_probe(struct device *dev, int
+ 	if (ret)
+ 		return dev_err_probe(dev, ret, "failed to add MFD devices\n");
+ 
+-	if (device_property_read_bool(dev, "rockchip,system-power-controller")) {
++	if (device_property_read_bool(dev, "rockchip,system-power-controller") ||
++	    device_property_read_bool(dev, "system-power-controller")) {
+ 		ret = devm_register_sys_off_handler(dev,
+ 				    SYS_OFF_MODE_POWER_OFF_PREPARE, SYS_OFF_PRIO_HIGH,
+ 				    &rk808_power_off, rk808);
diff --git a/target/linux/rockchip/patches-6.1/530-mfd-rk8xx-Add-support-for-RK806-power-off.patch b/target/linux/rockchip/patches-6.1/530-mfd-rk8xx-Add-support-for-RK806-power-off.patch
new file mode 100644
index 00000000000..f478a728c6c
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/530-mfd-rk8xx-Add-support-for-RK806-power-off.patch
@@ -0,0 +1,27 @@
+From 4198e8898b71d0bee8dc9e49749a81fea45d2d5b Mon Sep 17 00:00:00 2001
+From: Ondrej Jirman <megi@xff.cz>
+Date: Thu, 19 Oct 2023 18:57:26 +0200
+Subject: [PATCH] mfd: rk8xx: Add support for RK806 power off
+
+Use DEV_OFF bit to power off the RK806 PMIC, when system-power-controller
+is used in DTS.
+
+Signed-off-by: Ondrej Jirman <megi@xff.cz>
+Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
+---
+ drivers/mfd/rk8xx-core.c | 4 ++++
+ 1 file changed, 4 insertions(+)
+
+--- a/drivers/mfd/rk8xx-core.c
++++ b/drivers/mfd/rk8xx-core.c
+@@ -525,6 +525,10 @@ static int rk808_power_off(struct sys_of
+ 		reg = RK805_DEV_CTRL_REG;
+ 		bit = DEV_OFF;
+ 		break;
++	case RK806_ID:
++		reg = RK806_SYS_CFG3;
++		bit = DEV_OFF;
++		break;
+ 	case RK808_ID:
+ 		reg = RK808_DEVCTRL_REG,
+ 		bit = DEV_OFF_RST;
diff --git a/target/linux/rockchip/patches-6.1/531-arm64-dts-rockchip-Fix-rk3588-USB-power-domain-clocks.patch b/target/linux/rockchip/patches-6.1/531-arm64-dts-rockchip-Fix-rk3588-USB-power-domain-clocks.patch
new file mode 100644
index 00000000000..6b948a99fef
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/531-arm64-dts-rockchip-Fix-rk3588-USB-power-domain-clocks.patch
@@ -0,0 +1,44 @@
+From 44de8996ed5a10f08f2fe947182da6535edcfae5 Mon Sep 17 00:00:00 2001
+From: Sam Edwards <cfsworks@gmail.com>
+Date: Fri, 15 Dec 2023 19:10:19 -0700
+Subject: arm64: dts: rockchip: Fix rk3588 USB power-domain clocks
+
+The QoS blocks saved/restored when toggling the PD_USB power domain are
+clocked by ACLK_USB. Attempting to access these memory regions without
+that clock running will result in an indefinite CPU stall.
+
+The PD_USB node wasn't specifying this clock dependency, resulting in
+hangs when trying to toggle the power domain (either on or off), unless
+we get "lucky" and have ACLK_USB running for another reason at the time.
+This "luck" can result from the bootloader leaving USB powered/clocked,
+and if no built-in driver wants USB, Linux will disable the unused
+PD+CLK on boot when {pd,clk}_ignore_unused aren't given. This can also
+be unlucky because the two cleanup tasks run in parallel and race: if
+the CLK is disabled first, the PD deactivation stalls the boot. In any
+case, the PD cannot then be reenabled (if e.g. the driver loads later)
+once the clock has been stopped.
+
+Fix this by specifying a dependency on ACLK_USB, instead of only
+ACLK_USB_ROOT. The child-parent relationship means the former implies
+the latter anyway.
+
+Fixes: c9211fa2602b8 ("arm64: dts: rockchip: Add base DT for rk3588 SoC")
+Cc: stable@vger.kernel.org
+Signed-off-by: Sam Edwards <CFSworks@gmail.com>
+Link: https://lore.kernel.org/r/20231216021019.1543811-1-CFSworks@gmail.com
+[changed to only include the missing clock, not dropping the root-clocks]
+Signed-off-by: Heiko Stuebner <heiko@sntech.de>
+---
+ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 1 +
+ 1 file changed, 1 insertion(+)
+
+--- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
++++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi
+@@ -1504,6 +1504,7 @@
+ 				reg = <RK3588_PD_USB>;
+ 				clocks = <&cru PCLK_PHP_ROOT>,
+ 					 <&cru ACLK_USB_ROOT>,
++					 <&cru ACLK_USB>,
+ 					 <&cru HCLK_USB_ROOT>,
+ 					 <&cru HCLK_HOST0>,
+ 					 <&cru HCLK_HOST_ARB0>,
diff --git a/target/linux/rockchip/patches-6.1/801-char-add-support-for-rockchip-hardware-random-number.patch b/target/linux/rockchip/patches-6.1/801-char-add-support-for-rockchip-hardware-random-number.patch
deleted file mode 100644
index bf479e5f6f8..00000000000
--- a/target/linux/rockchip/patches-6.1/801-char-add-support-for-rockchip-hardware-random-number.patch
+++ /dev/null
@@ -1,45 +0,0 @@
-From e5b5361651940ff5c0c1784dfd0130abec7ab535 Mon Sep 17 00:00:00 2001
-From: wevsty <ty@wevs.org>
-Date: Mon, 24 Aug 2020 02:27:11 +0800
-Subject: [PATCH] char: add support for rockchip hardware random number
- generator
-
-This patch provides hardware random number generator support for all rockchip SOC.
-
-rockchip-rng.c from  https://github.com/rockchip-linux/kernel/blob/develop-4.4/drivers/char/hw_random/rockchip-rng.c
-
-Signed-off-by: wevsty <ty@wevs.org>
----
-
---- a/drivers/char/hw_random/Kconfig
-+++ b/drivers/char/hw_random/Kconfig
-@@ -372,6 +372,19 @@ config HW_RANDOM_STM32
- 
- 	  If unsure, say N.
- 
-+config HW_RANDOM_ROCKCHIP
-+	tristate "Rockchip Random Number Generator support"
-+	depends on ARCH_ROCKCHIP
-+	default HW_RANDOM
-+	help
-+	  This driver provides kernel-side support for the Random Number
-+	  Generator hardware found on Rockchip cpus.
-+
-+	  To compile this driver as a module, choose M here: the
-+	  module will be called rockchip-rng.
-+
-+	  If unsure, say Y.
-+
- config HW_RANDOM_PIC32
- 	tristate "Microchip PIC32 Random Number Generator support"
- 	depends on HW_RANDOM && MACH_PIC32
---- a/drivers/char/hw_random/Makefile
-+++ b/drivers/char/hw_random/Makefile
-@@ -34,6 +34,7 @@ obj-$(CONFIG_HW_RANDOM_IPROC_RNG200) +=
- obj-$(CONFIG_HW_RANDOM_ST) += st-rng.o
- obj-$(CONFIG_HW_RANDOM_XGENE) += xgene-rng.o
- obj-$(CONFIG_HW_RANDOM_STM32) += stm32-rng.o
-+obj-$(CONFIG_HW_RANDOM_ROCKCHIP) += rockchip-rng.o
- obj-$(CONFIG_HW_RANDOM_PIC32) += pic32-rng.o
- obj-$(CONFIG_HW_RANDOM_MESON) += meson-rng.o
- obj-$(CONFIG_HW_RANDOM_CAVIUM) += cavium-rng.o cavium-rng-vf.o
diff --git a/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch b/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
index 19b9b5b3996..3fbaeef8962 100644
--- a/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
+++ b/target/linux/rockchip/patches-6.1/802-arm64-dts-rockchip-add-hardware-random-number-genera.patch
@@ -11,7 +11,7 @@ Signed-off-by: wevsty <ty@wevs.org>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -279,6 +279,17 @@
+@@ -281,6 +281,17 @@
  		status = "disabled";
  	};
  
@@ -31,7 +31,7 @@ Signed-off-by: wevsty <ty@wevs.org>
  		reg = <0x0 0xff100000 0x0 0x1000>;
 --- a/arch/arm64/boot/dts/rockchip/rk3399.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3399.dtsi
-@@ -2065,6 +2065,16 @@
+@@ -2078,6 +2078,16 @@
  		};
  	};
  
diff --git a/target/linux/rockchip/patches-6.1/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch b/target/linux/rockchip/patches-6.1/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
index 14f69157b20..74b76af622d 100644
--- a/target/linux/rockchip/patches-6.1/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
+++ b/target/linux/rockchip/patches-6.1/804-clk-rockchip-support-setting-ddr-clock-via-SIP-Version-2-.patch
@@ -179,7 +179,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  	GATE(0, "clk_ddrupctl", "clk_ddr", CLK_IGNORE_UNUSED,
 --- a/drivers/clk/rockchip/clk.h
 +++ b/drivers/clk/rockchip/clk.h
-@@ -418,7 +418,8 @@ struct clk *rockchip_clk_register_mmc(co
+@@ -486,7 +486,8 @@ struct clk *rockchip_clk_register_mmc(co
   * DDRCLK flags, including method of setting the rate
   * ROCKCHIP_DDRCLK_SIP: use SIP call to bl31 to change ddrclk rate.
   */
diff --git a/target/linux/rockchip/patches-6.1/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch b/target/linux/rockchip/patches-6.1/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch
index 6d8ce8da4ab..86d046133bd 100644
--- a/target/linux/rockchip/patches-6.1/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch
+++ b/target/linux/rockchip/patches-6.1/806-arm64-dts-rockchip-rk3328-add-dfi-node.patch
@@ -11,7 +11,7 @@ Signed-off-by: Tianling Shen <cnsztl@immortalwrt.org>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -1023,6 +1023,13 @@
+@@ -1025,6 +1025,13 @@
  		status = "disabled";
  	};
  
diff --git a/target/linux/rockchip/patches-6.1/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch b/target/linux/rockchip/patches-6.1/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
index 981bc70fbf5..4794e462a63 100644
--- a/target/linux/rockchip/patches-6.1/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
+++ b/target/linux/rockchip/patches-6.1/807-arm64-dts-nanopi-r2s-add-rk3328-dmc-relate-node.patch
@@ -24,7 +24,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  #include "rk3328.dtsi"
  
  / {
-@@ -121,6 +122,72 @@
+@@ -119,6 +120,72 @@
  		regulator-boot-on;
  		vin-supply = <&vdd_5v>;
  	};
@@ -97,7 +97,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  };
  
  &cpu0 {
-@@ -139,6 +206,10 @@
+@@ -137,6 +204,10 @@
  	cpu-supply = <&vdd_arm>;
  };
  
@@ -108,7 +108,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  &display_subsystem {
  	status = "disabled";
  };
-@@ -206,6 +277,7 @@
+@@ -200,6 +271,7 @@
  				regulator-name = "vdd_log";
  				regulator-always-on;
  				regulator-boot-on;
@@ -116,7 +116,7 @@ Signed-off-by: hmz007 <hmz007@gmail.com>
  				regulator-min-microvolt = <712500>;
  				regulator-max-microvolt = <1450000>;
  				regulator-ramp-delay = <12500>;
-@@ -220,6 +292,7 @@
+@@ -214,6 +286,7 @@
  				regulator-name = "vdd_arm";
  				regulator-always-on;
  				regulator-boot-on;
diff --git a/target/linux/rockchip/patches-6.1/808-drv-net-phy-add-JLSemi-jl2xxx-driver.patch b/target/linux/rockchip/patches-6.1/808-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
index d685d62ae70..d591e944996 100644
--- a/target/linux/rockchip/patches-6.1/808-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
+++ b/target/linux/rockchip/patches-6.1/808-drv-net-phy-add-JLSemi-jl2xxx-driver.patch
@@ -1,6 +1,6 @@
 --- a/drivers/net/phy/Kconfig
 +++ b/drivers/net/phy/Kconfig
-@@ -277,6 +277,11 @@ config INTEL_XWAY_PHY
+@@ -280,6 +280,11 @@ config INTEL_XWAY_PHY
  	  PEF 7061, PEF 7071 and PEF 7072 or integrated into the Intel
  	  SoCs xRX200, xRX300, xRX330, xRX350 and xRX550.
  
diff --git a/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch b/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
index 315ac0e34a3..7079d9b2f38 100644
--- a/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
+++ b/target/linux/rockchip/patches-6.1/991-arm64-dts-rockchip-add-more-cpu-operating-points-for.patch
@@ -20,7 +20,7 @@ Signed-off-by: Leonidas P. Papadakos <papadakospan@gmail.com>
 
 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi
 +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi
-@@ -140,6 +140,21 @@
+@@ -142,6 +142,21 @@
  			opp-microvolt = <1300000>;
  			clock-latency-ns = <40000>;
  		};
diff --git a/target/linux/rockchip/patches-6.1/993-rockchip-rk356x-add-support-for-new-boards.patch b/target/linux/rockchip/patches-6.1/993-rockchip-rk356x-add-support-for-new-boards.patch
new file mode 100644
index 00000000000..6968a7e4019
--- /dev/null
+++ b/target/linux/rockchip/patches-6.1/993-rockchip-rk356x-add-support-for-new-boards.patch
@@ -0,0 +1,30 @@
+From b4c1701740668201f75e93a04f92e5e5975ad87e Mon Sep 17 00:00:00 2001
+From: DHDAXCW <lasstp5011@gmail.com>
+Date: Thu, 22 Feb 2024 14:52:34 +0800
+Subject: [PATCH] wode
+
+---
+ arch/arm64/boot/dts/rockchip/Makefile | 6 ++++++
+ 1 file changed, 6 insertions(+)
+
+--- a/arch/arm64/boot/dts/rockchip/Makefile
++++ b/arch/arm64/boot/dts/rockchip/Makefile
+@@ -86,11 +86,18 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-so
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-model-a.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-box-demo.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-1.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399-doornet2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat1.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat1n.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-lubancat-zero-n.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r66s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-fastrhino-r68s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat-2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat2.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat2n.dtb
++dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-lubancat2io.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5c.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-nanopi-r5s.dtb
+ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-odroid-m1.dtb
diff --git a/target/linux/rockchip/patches-6.1/993-v91-i2s-mclk.patch b/target/linux/rockchip/patches-6.1/993-v91-i2s-mclk.patch
deleted file mode 100644
index 39b5c411ae3..00000000000
--- a/target/linux/rockchip/patches-6.1/993-v91-i2s-mclk.patch
+++ /dev/null
@@ -1,80 +0,0 @@
---- a/drivers/clk/rockchip/clk-rk3568.c
-+++ b/drivers/clk/rockchip/clk-rk3568.c
-@@ -13,6 +13,8 @@
- #include <dt-bindings/clock/rk3568-cru.h>
- #include "clk.h"
- 
-+#define RK3568_GRF_SOC_CON1	0x504
-+#define RK3568_GRF_SOC_CON2	0x508
- #define RK3568_GRF_SOC_STATUS0	0x580
- 
- enum rk3568_pmu_plls {
-@@ -247,13 +249,13 @@ PNAME(dpll_gpll_cpll_p)			= { "dpll", "g
- PNAME(clk_ddr1x_p)			= { "clk_ddrphy1x_src", "dpll" };
- PNAME(gpll200_gpll150_gpll100_xin24m_p)	= { "gpll_200m", "gpll_150m", "gpll_100m", "xin24m" };
- PNAME(gpll100_gpll75_gpll50_p)		= { "gpll_100m", "gpll_75m", "cpll_50m" };
--PNAME(i2s0_mclkout_tx_p)		= { "clk_i2s0_8ch_tx", "xin_osc0_half" };
--PNAME(i2s0_mclkout_rx_p)		= { "clk_i2s0_8ch_rx", "xin_osc0_half" };
--PNAME(i2s1_mclkout_tx_p)		= { "clk_i2s1_8ch_tx", "xin_osc0_half" };
--PNAME(i2s1_mclkout_rx_p)		= { "clk_i2s1_8ch_rx", "xin_osc0_half" };
--PNAME(i2s2_mclkout_p)			= { "clk_i2s2_2ch", "xin_osc0_half" };
--PNAME(i2s3_mclkout_tx_p)		= { "clk_i2s3_2ch_tx", "xin_osc0_half" };
--PNAME(i2s3_mclkout_rx_p)		= { "clk_i2s3_2ch_rx", "xin_osc0_half" };
-+PNAME(i2s0_mclkout_tx_p)		= { "mclk_i2s0_8ch_tx", "xin_osc0_half" };
-+PNAME(i2s0_mclkout_rx_p)		= { "mclk_i2s0_8ch_rx", "xin_osc0_half" };
-+PNAME(i2s1_mclkout_tx_p)		= { "mclk_i2s1_8ch_tx", "xin_osc0_half" };
-+PNAME(i2s1_mclkout_rx_p)		= { "mclk_i2s1_8ch_rx", "xin_osc0_half" };
-+PNAME(i2s2_mclkout_p)			= { "mclk_i2s2_2ch", "xin_osc0_half" };
-+PNAME(i2s3_mclkout_tx_p)		= { "mclk_i2s3_2ch_tx", "xin_osc0_half" };
-+PNAME(i2s3_mclkout_rx_p)		= { "mclk_i2s3_2ch_rx", "xin_osc0_half" };
- PNAME(mclk_pdm_p)			= { "gpll_300m", "cpll_250m", "gpll_200m", "gpll_100m" };
- PNAME(clk_i2c_p)			= { "gpll_200m", "gpll_100m", "xin24m", "cpll_100m" };
- PNAME(gpll200_gpll150_gpll100_p)	= { "gpll_200m", "gpll_150m", "gpll_100m" };
-@@ -307,6 +309,12 @@ PNAME(clk_mac_2top_p)			= { "cpll_125m",
- PNAME(clk_pwm0_p)			= { "xin24m", "clk_pdpmu" };
- PNAME(aclk_rkvdec_pre_p)		= { "gpll", "cpll" };
- PNAME(clk_rkvdec_core_p)		= { "gpll", "cpll", "dummy_npll", "dummy_vpll" };
-+PNAME(i2s1_mclkout_p)			= { "i2s1_mclkout_rx", "i2s1_mclkout_tx" };
-+PNAME(i2s3_mclkout_p)			= { "i2s3_mclkout_rx", "i2s3_mclkout_tx" };
-+PNAME(i2s1_mclk_rx_ioe_p)		= { "i2s1_mclkin_rx", "i2s1_mclkout_rx" };
-+PNAME(i2s1_mclk_tx_ioe_p)		= { "i2s1_mclkin_tx", "i2s1_mclkout_tx" };
-+PNAME(i2s2_mclk_ioe_p)			= { "i2s2_mclkin", "i2s2_mclkout" };
-+PNAME(i2s3_mclk_ioe_p)			= { "i2s3_mclkin", "i2s3_mclkout" };
- 
- static struct rockchip_pll_clock rk3568_pmu_pll_clks[] __initdata = {
- 	[ppll] = PLL(pll_rk3328, PLL_PPLL, "ppll",  mux_pll_p,
-@@ -704,6 +712,19 @@ static struct rockchip_clk_branch rk3568
- 			RK3568_CLKSEL_CON(83), 15, 1, MFLAGS,
- 			RK3568_CLKGATE_CON(7), 11, GFLAGS),
- 
-+	MUXGRF(I2S1_MCLKOUT, "i2s1_mclkout", i2s1_mclkout_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
-+			RK3568_GRF_SOC_CON1, 5, 1, MFLAGS),
-+	MUXGRF(I2S3_MCLKOUT, "i2s3_mclkout", i2s3_mclkout_p,  CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
-+			RK3568_GRF_SOC_CON2, 15, 1, MFLAGS),
-+	MUXGRF(I2S1_MCLK_RX_IOE, "i2s1_mclk_rx_ioe", i2s1_mclk_rx_ioe_p,  0,
-+			RK3568_GRF_SOC_CON2, 0, 1, MFLAGS),
-+	MUXGRF(I2S1_MCLK_TX_IOE, "i2s1_mclk_tx_ioe", i2s1_mclk_tx_ioe_p,  0,
-+			RK3568_GRF_SOC_CON2, 1, 1, MFLAGS),
-+	MUXGRF(I2S2_MCLK_IOE, "i2s2_mclk_ioe", i2s2_mclk_ioe_p,  0,
-+			RK3568_GRF_SOC_CON2, 2, 1, MFLAGS),
-+	MUXGRF(I2S3_MCLK_IOE, "i2s3_mclk_ioe", i2s3_mclk_ioe_p,  0,
-+			RK3568_GRF_SOC_CON2, 3, 1, MFLAGS),
-+
- 	GATE(HCLK_PDM, "hclk_pdm", "hclk_gic_audio", 0,
- 			RK3568_CLKGATE_CON(5), 14, GFLAGS),
- 	COMPOSITE_NODIV(MCLK_PDM, "mclk_pdm", mclk_pdm_p, 0,
---- a/include/dt-bindings/clock/rk3568-cru.h
-+++ b/include/dt-bindings/clock/rk3568-cru.h
-@@ -479,6 +479,12 @@
- #define CPLL_25M		416
- #define CPLL_100M		417
- #define SCLK_DDRCLK		418
-+#define I2S1_MCLKOUT		419
-+#define I2S3_MCLKOUT		420
-+#define I2S1_MCLK_RX_IOE	421
-+#define I2S1_MCLK_TX_IOE	422
-+#define I2S2_MCLK_IOE		423
-+#define I2S3_MCLK_IOE		424
- 
- #define PCLK_CORE_PVTM		450
-